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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
a23db284 WL |
2 | #ifndef _GEN_PV_LOCK_SLOWPATH |
3 | #error "do not include this file" | |
4 | #endif | |
5 | ||
6 | #include <linux/hash.h> | |
7 | #include <linux/bootmem.h> | |
cba77f03 | 8 | #include <linux/debug_locks.h> |
a23db284 WL |
9 | |
10 | /* | |
11 | * Implement paravirt qspinlocks; the general idea is to halt the vcpus instead | |
12 | * of spinning them. | |
13 | * | |
14 | * This relies on the architecture to provide two paravirt hypercalls: | |
15 | * | |
16 | * pv_wait(u8 *ptr, u8 val) -- suspends the vcpu if *ptr == val | |
17 | * pv_kick(cpu) -- wakes a suspended vcpu | |
18 | * | |
19 | * Using these we implement __pv_queued_spin_lock_slowpath() and | |
20 | * __pv_queued_spin_unlock() to replace native_queued_spin_lock_slowpath() and | |
21 | * native_queued_spin_unlock(). | |
22 | */ | |
23 | ||
24 | #define _Q_SLOW_VAL (3U << _Q_LOCKED_OFFSET) | |
25 | ||
cd0272fa WL |
26 | /* |
27 | * Queue Node Adaptive Spinning | |
28 | * | |
29 | * A queue node vCPU will stop spinning if the vCPU in the previous node is | |
30 | * not running. The one lock stealing attempt allowed at slowpath entry | |
31 | * mitigates the slight slowdown for non-overcommitted guest with this | |
32 | * aggressive wait-early mechanism. | |
33 | * | |
34 | * The status of the previous node will be checked at fixed interval | |
35 | * controlled by PV_PREV_CHECK_MASK. This is to ensure that we won't | |
36 | * pound on the cacheline of the previous node too heavily. | |
37 | */ | |
38 | #define PV_PREV_CHECK_MASK 0xff | |
39 | ||
75d22702 WL |
40 | /* |
41 | * Queue node uses: vcpu_running & vcpu_halted. | |
42 | * Queue head uses: vcpu_running & vcpu_hashed. | |
43 | */ | |
a23db284 WL |
44 | enum vcpu_state { |
45 | vcpu_running = 0, | |
75d22702 WL |
46 | vcpu_halted, /* Used only in pv_wait_node */ |
47 | vcpu_hashed, /* = pv_hash'ed + vcpu_halted */ | |
a23db284 WL |
48 | }; |
49 | ||
50 | struct pv_node { | |
51 | struct mcs_spinlock mcs; | |
52 | struct mcs_spinlock __res[3]; | |
53 | ||
54 | int cpu; | |
55 | u8 state; | |
56 | }; | |
57 | ||
eaff0e70 WL |
58 | /* |
59 | * Include queued spinlock statistics code | |
60 | */ | |
61 | #include "qspinlock_stat.h" | |
62 | ||
1c4941fd | 63 | /* |
11752adb WL |
64 | * Hybrid PV queued/unfair lock |
65 | * | |
1c4941fd WL |
66 | * By replacing the regular queued_spin_trylock() with the function below, |
67 | * it will be called once when a lock waiter enter the PV slowpath before | |
11752adb WL |
68 | * being queued. |
69 | * | |
70 | * The pending bit is set by the queue head vCPU of the MCS wait queue in | |
71 | * pv_wait_head_or_lock() to signal that it is ready to spin on the lock. | |
72 | * When that bit becomes visible to the incoming waiters, no lock stealing | |
73 | * is allowed. The function will return immediately to make the waiters | |
74 | * enter the MCS wait queue. So lock starvation shouldn't happen as long | |
75 | * as the queued mode vCPUs are actively running to set the pending bit | |
76 | * and hence disabling lock stealing. | |
77 | * | |
78 | * When the pending bit isn't set, the lock waiters will stay in the unfair | |
79 | * mode spinning on the lock unless the MCS wait queue is empty. In this | |
80 | * case, the lock waiters will enter the queued mode slowpath trying to | |
81 | * become the queue head and set the pending bit. | |
82 | * | |
83 | * This hybrid PV queued/unfair lock combines the best attributes of a | |
84 | * queued lock (no lock starvation) and an unfair lock (good performance | |
85 | * on not heavily contended locks). | |
1c4941fd | 86 | */ |
11752adb WL |
87 | #define queued_spin_trylock(l) pv_hybrid_queued_unfair_trylock(l) |
88 | static inline bool pv_hybrid_queued_unfair_trylock(struct qspinlock *lock) | |
1c4941fd | 89 | { |
11752adb WL |
90 | /* |
91 | * Stay in unfair lock mode as long as queued mode waiters are | |
92 | * present in the MCS wait queue but the pending bit isn't set. | |
93 | */ | |
94 | for (;;) { | |
95 | int val = atomic_read(&lock->val); | |
96 | ||
97 | if (!(val & _Q_LOCKED_PENDING_MASK) && | |
625e88be | 98 | (cmpxchg_acquire(&lock->locked, 0, _Q_LOCKED_VAL) == 0)) { |
11752adb WL |
99 | qstat_inc(qstat_pv_lock_stealing, true); |
100 | return true; | |
101 | } | |
102 | if (!(val & _Q_TAIL_MASK) || (val & _Q_PENDING_MASK)) | |
103 | break; | |
104 | ||
105 | cpu_relax(); | |
64a5e3cb PZ |
106 | } |
107 | ||
108 | return false; | |
1c4941fd WL |
109 | } |
110 | ||
111 | /* | |
112 | * The pending bit is used by the queue head vCPU to indicate that it | |
113 | * is actively spinning on the lock and no lock stealing is allowed. | |
114 | */ | |
115 | #if _Q_PENDING_BITS == 8 | |
116 | static __always_inline void set_pending(struct qspinlock *lock) | |
117 | { | |
625e88be | 118 | WRITE_ONCE(lock->pending, 1); |
1c4941fd WL |
119 | } |
120 | ||
121 | static __always_inline void clear_pending(struct qspinlock *lock) | |
122 | { | |
625e88be | 123 | WRITE_ONCE(lock->pending, 0); |
1c4941fd WL |
124 | } |
125 | ||
126 | /* | |
127 | * The pending bit check in pv_queued_spin_steal_lock() isn't a memory | |
34d54f3d WL |
128 | * barrier. Therefore, an atomic cmpxchg_acquire() is used to acquire the |
129 | * lock just to be sure that it will get it. | |
1c4941fd WL |
130 | */ |
131 | static __always_inline int trylock_clear_pending(struct qspinlock *lock) | |
132 | { | |
625e88be WD |
133 | return !READ_ONCE(lock->locked) && |
134 | (cmpxchg_acquire(&lock->locked_pending, _Q_PENDING_VAL, | |
34d54f3d | 135 | _Q_LOCKED_VAL) == _Q_PENDING_VAL); |
1c4941fd WL |
136 | } |
137 | #else /* _Q_PENDING_BITS == 8 */ | |
138 | static __always_inline void set_pending(struct qspinlock *lock) | |
139 | { | |
e37837fb | 140 | atomic_or(_Q_PENDING_VAL, &lock->val); |
1c4941fd WL |
141 | } |
142 | ||
143 | static __always_inline void clear_pending(struct qspinlock *lock) | |
144 | { | |
e37837fb | 145 | atomic_andnot(_Q_PENDING_VAL, &lock->val); |
1c4941fd WL |
146 | } |
147 | ||
148 | static __always_inline int trylock_clear_pending(struct qspinlock *lock) | |
149 | { | |
150 | int val = atomic_read(&lock->val); | |
151 | ||
152 | for (;;) { | |
153 | int old, new; | |
154 | ||
155 | if (val & _Q_LOCKED_MASK) | |
156 | break; | |
157 | ||
158 | /* | |
159 | * Try to clear pending bit & set locked bit | |
160 | */ | |
161 | old = val; | |
162 | new = (val & ~_Q_PENDING_MASK) | _Q_LOCKED_VAL; | |
34d54f3d | 163 | val = atomic_cmpxchg_acquire(&lock->val, old, new); |
1c4941fd WL |
164 | |
165 | if (val == old) | |
166 | return 1; | |
167 | } | |
168 | return 0; | |
169 | } | |
170 | #endif /* _Q_PENDING_BITS == 8 */ | |
171 | ||
a23db284 WL |
172 | /* |
173 | * Lock and MCS node addresses hash table for fast lookup | |
174 | * | |
175 | * Hashing is done on a per-cacheline basis to minimize the need to access | |
176 | * more than one cacheline. | |
177 | * | |
178 | * Dynamically allocate a hash table big enough to hold at least 4X the | |
179 | * number of possible cpus in the system. Allocation is done on page | |
180 | * granularity. So the minimum number of hash buckets should be at least | |
181 | * 256 (64-bit) or 512 (32-bit) to fully utilize a 4k page. | |
182 | * | |
183 | * Since we should not be holding locks from NMI context (very rare indeed) the | |
184 | * max load factor is 0.75, which is around the point where open addressing | |
185 | * breaks down. | |
186 | * | |
187 | */ | |
188 | struct pv_hash_entry { | |
189 | struct qspinlock *lock; | |
190 | struct pv_node *node; | |
191 | }; | |
192 | ||
193 | #define PV_HE_PER_LINE (SMP_CACHE_BYTES / sizeof(struct pv_hash_entry)) | |
194 | #define PV_HE_MIN (PAGE_SIZE / sizeof(struct pv_hash_entry)) | |
195 | ||
196 | static struct pv_hash_entry *pv_lock_hash; | |
197 | static unsigned int pv_lock_hash_bits __read_mostly; | |
198 | ||
199 | /* | |
200 | * Allocate memory for the PV qspinlock hash buckets | |
201 | * | |
202 | * This function should be called from the paravirt spinlock initialization | |
203 | * routine. | |
204 | */ | |
205 | void __init __pv_init_lock_hash(void) | |
206 | { | |
207 | int pv_hash_size = ALIGN(4 * num_possible_cpus(), PV_HE_PER_LINE); | |
208 | ||
209 | if (pv_hash_size < PV_HE_MIN) | |
210 | pv_hash_size = PV_HE_MIN; | |
211 | ||
212 | /* | |
213 | * Allocate space from bootmem which should be page-size aligned | |
214 | * and hence cacheline aligned. | |
215 | */ | |
216 | pv_lock_hash = alloc_large_system_hash("PV qspinlock", | |
217 | sizeof(struct pv_hash_entry), | |
3d375d78 PT |
218 | pv_hash_size, 0, |
219 | HASH_EARLY | HASH_ZERO, | |
a23db284 WL |
220 | &pv_lock_hash_bits, NULL, |
221 | pv_hash_size, pv_hash_size); | |
222 | } | |
223 | ||
224 | #define for_each_hash_entry(he, offset, hash) \ | |
225 | for (hash &= ~(PV_HE_PER_LINE - 1), he = &pv_lock_hash[hash], offset = 0; \ | |
226 | offset < (1 << pv_lock_hash_bits); \ | |
227 | offset++, he = &pv_lock_hash[(hash + offset) & ((1 << pv_lock_hash_bits) - 1)]) | |
228 | ||
229 | static struct qspinlock **pv_hash(struct qspinlock *lock, struct pv_node *node) | |
230 | { | |
231 | unsigned long offset, hash = hash_ptr(lock, pv_lock_hash_bits); | |
232 | struct pv_hash_entry *he; | |
45e898b7 | 233 | int hopcnt = 0; |
a23db284 WL |
234 | |
235 | for_each_hash_entry(he, offset, hash) { | |
45e898b7 | 236 | hopcnt++; |
a23db284 WL |
237 | if (!cmpxchg(&he->lock, NULL, lock)) { |
238 | WRITE_ONCE(he->node, node); | |
45e898b7 | 239 | qstat_hop(hopcnt); |
a23db284 WL |
240 | return &he->lock; |
241 | } | |
242 | } | |
243 | /* | |
244 | * Hard assume there is a free entry for us. | |
245 | * | |
246 | * This is guaranteed by ensuring every blocked lock only ever consumes | |
247 | * a single entry, and since we only have 4 nesting levels per CPU | |
248 | * and allocated 4*nr_possible_cpus(), this must be so. | |
249 | * | |
250 | * The single entry is guaranteed by having the lock owner unhash | |
251 | * before it releases. | |
252 | */ | |
253 | BUG(); | |
254 | } | |
255 | ||
256 | static struct pv_node *pv_unhash(struct qspinlock *lock) | |
257 | { | |
258 | unsigned long offset, hash = hash_ptr(lock, pv_lock_hash_bits); | |
259 | struct pv_hash_entry *he; | |
260 | struct pv_node *node; | |
261 | ||
262 | for_each_hash_entry(he, offset, hash) { | |
263 | if (READ_ONCE(he->lock) == lock) { | |
264 | node = READ_ONCE(he->node); | |
265 | WRITE_ONCE(he->lock, NULL); | |
266 | return node; | |
267 | } | |
268 | } | |
269 | /* | |
270 | * Hard assume we'll find an entry. | |
271 | * | |
272 | * This guarantees a limited lookup time and is itself guaranteed by | |
273 | * having the lock owner do the unhash -- IFF the unlock sees the | |
274 | * SLOW flag, there MUST be a hash entry. | |
275 | */ | |
276 | BUG(); | |
277 | } | |
278 | ||
cd0272fa WL |
279 | /* |
280 | * Return true if when it is time to check the previous node which is not | |
281 | * in a running state. | |
282 | */ | |
283 | static inline bool | |
284 | pv_wait_early(struct pv_node *prev, int loop) | |
285 | { | |
cd0272fa WL |
286 | if ((loop & PV_PREV_CHECK_MASK) != 0) |
287 | return false; | |
288 | ||
75437bb3 | 289 | return READ_ONCE(prev->state) != vcpu_running || vcpu_is_preempted(prev->cpu); |
cd0272fa WL |
290 | } |
291 | ||
a23db284 WL |
292 | /* |
293 | * Initialize the PV part of the mcs_spinlock node. | |
294 | */ | |
295 | static void pv_init_node(struct mcs_spinlock *node) | |
296 | { | |
297 | struct pv_node *pn = (struct pv_node *)node; | |
298 | ||
299 | BUILD_BUG_ON(sizeof(struct pv_node) > 5*sizeof(struct mcs_spinlock)); | |
300 | ||
301 | pn->cpu = smp_processor_id(); | |
302 | pn->state = vcpu_running; | |
303 | } | |
304 | ||
305 | /* | |
306 | * Wait for node->locked to become true, halt the vcpu after a short spin. | |
75d22702 WL |
307 | * pv_kick_node() is used to set _Q_SLOW_VAL and fill in hash table on its |
308 | * behalf. | |
a23db284 | 309 | */ |
cd0272fa | 310 | static void pv_wait_node(struct mcs_spinlock *node, struct mcs_spinlock *prev) |
a23db284 WL |
311 | { |
312 | struct pv_node *pn = (struct pv_node *)node; | |
cd0272fa | 313 | struct pv_node *pp = (struct pv_node *)prev; |
a23db284 | 314 | int loop; |
cd0272fa | 315 | bool wait_early; |
a23db284 | 316 | |
08be8f63 | 317 | for (;;) { |
cd0272fa | 318 | for (wait_early = false, loop = SPIN_THRESHOLD; loop; loop--) { |
a23db284 WL |
319 | if (READ_ONCE(node->locked)) |
320 | return; | |
cd0272fa WL |
321 | if (pv_wait_early(pp, loop)) { |
322 | wait_early = true; | |
323 | break; | |
324 | } | |
a23db284 WL |
325 | cpu_relax(); |
326 | } | |
327 | ||
328 | /* | |
329 | * Order pn->state vs pn->locked thusly: | |
330 | * | |
331 | * [S] pn->state = vcpu_halted [S] next->locked = 1 | |
332 | * MB MB | |
75d22702 | 333 | * [L] pn->locked [RmW] pn->state = vcpu_hashed |
a23db284 | 334 | * |
75d22702 | 335 | * Matches the cmpxchg() from pv_kick_node(). |
a23db284 | 336 | */ |
b92b8b35 | 337 | smp_store_mb(pn->state, vcpu_halted); |
a23db284 | 338 | |
45e898b7 WL |
339 | if (!READ_ONCE(node->locked)) { |
340 | qstat_inc(qstat_pv_wait_node, true); | |
cd0272fa | 341 | qstat_inc(qstat_pv_wait_early, wait_early); |
a23db284 | 342 | pv_wait(&pn->state, vcpu_halted); |
45e898b7 | 343 | } |
a23db284 WL |
344 | |
345 | /* | |
45e898b7 | 346 | * If pv_kick_node() changed us to vcpu_hashed, retain that |
1c4941fd WL |
347 | * value so that pv_wait_head_or_lock() knows to not also try |
348 | * to hash this lock. | |
a23db284 | 349 | */ |
75d22702 | 350 | cmpxchg(&pn->state, vcpu_halted, vcpu_running); |
a23db284 WL |
351 | |
352 | /* | |
353 | * If the locked flag is still not set after wakeup, it is a | |
354 | * spurious wakeup and the vCPU should wait again. However, | |
355 | * there is a pretty high overhead for CPU halting and kicking. | |
356 | * So it is better to spin for a while in the hope that the | |
357 | * MCS lock will be released soon. | |
358 | */ | |
45e898b7 | 359 | qstat_inc(qstat_pv_spurious_wakeup, !READ_ONCE(node->locked)); |
a23db284 | 360 | } |
75d22702 | 361 | |
a23db284 WL |
362 | /* |
363 | * By now our node->locked should be 1 and our caller will not actually | |
364 | * spin-wait for it. We do however rely on our caller to do a | |
365 | * load-acquire for us. | |
366 | */ | |
367 | } | |
368 | ||
369 | /* | |
75d22702 WL |
370 | * Called after setting next->locked = 1 when we're the lock owner. |
371 | * | |
1c4941fd WL |
372 | * Instead of waking the waiters stuck in pv_wait_node() advance their state |
373 | * such that they're waiting in pv_wait_head_or_lock(), this avoids a | |
374 | * wake/sleep cycle. | |
a23db284 | 375 | */ |
75d22702 | 376 | static void pv_kick_node(struct qspinlock *lock, struct mcs_spinlock *node) |
a23db284 WL |
377 | { |
378 | struct pv_node *pn = (struct pv_node *)node; | |
379 | ||
380 | /* | |
75d22702 WL |
381 | * If the vCPU is indeed halted, advance its state to match that of |
382 | * pv_wait_node(). If OTOH this fails, the vCPU was running and will | |
383 | * observe its next->locked value and advance itself. | |
a23db284 | 384 | * |
75d22702 | 385 | * Matches with smp_store_mb() and cmpxchg() in pv_wait_node() |
34d54f3d WL |
386 | * |
387 | * The write to next->locked in arch_mcs_spin_unlock_contended() | |
388 | * must be ordered before the read of pn->state in the cmpxchg() | |
389 | * below for the code to work correctly. To guarantee full ordering | |
390 | * irrespective of the success or failure of the cmpxchg(), | |
391 | * a relaxed version with explicit barrier is used. The control | |
392 | * dependency will order the reading of pn->state before any | |
393 | * subsequent writes. | |
75d22702 | 394 | */ |
34d54f3d WL |
395 | smp_mb__before_atomic(); |
396 | if (cmpxchg_relaxed(&pn->state, vcpu_halted, vcpu_hashed) | |
397 | != vcpu_halted) | |
75d22702 WL |
398 | return; |
399 | ||
400 | /* | |
401 | * Put the lock into the hash table and set the _Q_SLOW_VAL. | |
a23db284 | 402 | * |
75d22702 WL |
403 | * As this is the same vCPU that will check the _Q_SLOW_VAL value and |
404 | * the hash table later on at unlock time, no atomic instruction is | |
405 | * needed. | |
a23db284 | 406 | */ |
625e88be | 407 | WRITE_ONCE(lock->locked, _Q_SLOW_VAL); |
75d22702 | 408 | (void)pv_hash(lock, pn); |
a23db284 WL |
409 | } |
410 | ||
411 | /* | |
1c4941fd WL |
412 | * Wait for l->locked to become clear and acquire the lock; |
413 | * halt the vcpu after a short spin. | |
a23db284 | 414 | * __pv_queued_spin_unlock() will wake us. |
1c4941fd WL |
415 | * |
416 | * The current value of the lock will be returned for additional processing. | |
a23db284 | 417 | */ |
1c4941fd WL |
418 | static u32 |
419 | pv_wait_head_or_lock(struct qspinlock *lock, struct mcs_spinlock *node) | |
a23db284 WL |
420 | { |
421 | struct pv_node *pn = (struct pv_node *)node; | |
a23db284 | 422 | struct qspinlock **lp = NULL; |
45e898b7 | 423 | int waitcnt = 0; |
a23db284 WL |
424 | int loop; |
425 | ||
75d22702 WL |
426 | /* |
427 | * If pv_kick_node() already advanced our state, we don't need to | |
428 | * insert ourselves into the hash table anymore. | |
429 | */ | |
430 | if (READ_ONCE(pn->state) == vcpu_hashed) | |
431 | lp = (struct qspinlock **)1; | |
432 | ||
32d62510 WL |
433 | /* |
434 | * Tracking # of slowpath locking operations | |
435 | */ | |
436 | qstat_inc(qstat_pv_lock_slowpath, true); | |
437 | ||
45e898b7 | 438 | for (;; waitcnt++) { |
cd0272fa WL |
439 | /* |
440 | * Set correct vCPU state to be used by queue node wait-early | |
441 | * mechanism. | |
442 | */ | |
443 | WRITE_ONCE(pn->state, vcpu_running); | |
444 | ||
1c4941fd WL |
445 | /* |
446 | * Set the pending bit in the active lock spinning loop to | |
447 | * disable lock stealing before attempting to acquire the lock. | |
448 | */ | |
449 | set_pending(lock); | |
a23db284 | 450 | for (loop = SPIN_THRESHOLD; loop; loop--) { |
1c4941fd WL |
451 | if (trylock_clear_pending(lock)) |
452 | goto gotlock; | |
a23db284 WL |
453 | cpu_relax(); |
454 | } | |
1c4941fd WL |
455 | clear_pending(lock); |
456 | ||
a23db284 | 457 | |
a23db284 WL |
458 | if (!lp) { /* ONCE */ |
459 | lp = pv_hash(lock, pn); | |
75d22702 | 460 | |
a23db284 | 461 | /* |
3b3fdf10 WD |
462 | * We must hash before setting _Q_SLOW_VAL, such that |
463 | * when we observe _Q_SLOW_VAL in __pv_queued_spin_unlock() | |
464 | * we'll be sure to be able to observe our hash entry. | |
a23db284 | 465 | * |
3b3fdf10 WD |
466 | * [S] <hash> [Rmw] l->locked == _Q_SLOW_VAL |
467 | * MB RMB | |
468 | * [RmW] l->locked = _Q_SLOW_VAL [L] <unhash> | |
a23db284 | 469 | * |
3b3fdf10 | 470 | * Matches the smp_rmb() in __pv_queued_spin_unlock(). |
a23db284 | 471 | */ |
625e88be | 472 | if (xchg(&lock->locked, _Q_SLOW_VAL) == 0) { |
a23db284 | 473 | /* |
1c4941fd WL |
474 | * The lock was free and now we own the lock. |
475 | * Change the lock value back to _Q_LOCKED_VAL | |
476 | * and unhash the table. | |
a23db284 | 477 | */ |
625e88be | 478 | WRITE_ONCE(lock->locked, _Q_LOCKED_VAL); |
a23db284 | 479 | WRITE_ONCE(*lp, NULL); |
1c4941fd | 480 | goto gotlock; |
a23db284 WL |
481 | } |
482 | } | |
229ce631 | 483 | WRITE_ONCE(pn->state, vcpu_hashed); |
45e898b7 WL |
484 | qstat_inc(qstat_pv_wait_head, true); |
485 | qstat_inc(qstat_pv_wait_again, waitcnt); | |
625e88be | 486 | pv_wait(&lock->locked, _Q_SLOW_VAL); |
a23db284 WL |
487 | |
488 | /* | |
08be8f63 WL |
489 | * Because of lock stealing, the queue head vCPU may not be |
490 | * able to acquire the lock before it has to wait again. | |
a23db284 WL |
491 | */ |
492 | } | |
493 | ||
494 | /* | |
1c4941fd WL |
495 | * The cmpxchg() or xchg() call before coming here provides the |
496 | * acquire semantics for locking. The dummy ORing of _Q_LOCKED_VAL | |
497 | * here is to indicate to the compiler that the value will always | |
498 | * be nozero to enable better code optimization. | |
a23db284 | 499 | */ |
1c4941fd WL |
500 | gotlock: |
501 | return (u32)(atomic_read(&lock->val) | _Q_LOCKED_VAL); | |
a23db284 WL |
502 | } |
503 | ||
504 | /* | |
d7804530 WL |
505 | * PV versions of the unlock fastpath and slowpath functions to be used |
506 | * instead of queued_spin_unlock(). | |
a23db284 | 507 | */ |
d7804530 WL |
508 | __visible void |
509 | __pv_queued_spin_unlock_slowpath(struct qspinlock *lock, u8 locked) | |
a23db284 | 510 | { |
a23db284 | 511 | struct pv_node *node; |
a23db284 | 512 | |
0b792bf5 PZ |
513 | if (unlikely(locked != _Q_SLOW_VAL)) { |
514 | WARN(!debug_locks_silent, | |
515 | "pvqspinlock: lock 0x%lx has corrupted value 0x%x!\n", | |
516 | (unsigned long)lock, atomic_read(&lock->val)); | |
cba77f03 WL |
517 | return; |
518 | } | |
519 | ||
3b3fdf10 WD |
520 | /* |
521 | * A failed cmpxchg doesn't provide any memory-ordering guarantees, | |
522 | * so we need a barrier to order the read of the node data in | |
523 | * pv_unhash *after* we've read the lock being _Q_SLOW_VAL. | |
524 | * | |
1c4941fd | 525 | * Matches the cmpxchg() in pv_wait_head_or_lock() setting _Q_SLOW_VAL. |
3b3fdf10 WD |
526 | */ |
527 | smp_rmb(); | |
528 | ||
a23db284 WL |
529 | /* |
530 | * Since the above failed to release, this must be the SLOW path. | |
531 | * Therefore start by looking up the blocked node and unhashing it. | |
532 | */ | |
533 | node = pv_unhash(lock); | |
534 | ||
535 | /* | |
536 | * Now that we have a reference to the (likely) blocked pv_node, | |
537 | * release the lock. | |
538 | */ | |
625e88be | 539 | smp_store_release(&lock->locked, 0); |
a23db284 WL |
540 | |
541 | /* | |
542 | * At this point the memory pointed at by lock can be freed/reused, | |
543 | * however we can still use the pv_node to kick the CPU. | |
75d22702 WL |
544 | * The other vCPU may not really be halted, but kicking an active |
545 | * vCPU is harmless other than the additional latency in completing | |
546 | * the unlock. | |
a23db284 | 547 | */ |
45e898b7 | 548 | qstat_inc(qstat_pv_kick_unlock, true); |
93edc8bd | 549 | pv_kick(node->cpu); |
a23db284 | 550 | } |
d7804530 | 551 | |
a23db284 WL |
552 | /* |
553 | * Include the architecture specific callee-save thunk of the | |
554 | * __pv_queued_spin_unlock(). This thunk is put together with | |
d7804530 WL |
555 | * __pv_queued_spin_unlock() to make the callee-save thunk and the real unlock |
556 | * function close to each other sharing consecutive instruction cachelines. | |
557 | * Alternatively, architecture specific version of __pv_queued_spin_unlock() | |
558 | * can be defined. | |
a23db284 WL |
559 | */ |
560 | #include <asm/qspinlock_paravirt.h> | |
561 | ||
d7804530 WL |
562 | #ifndef __pv_queued_spin_unlock |
563 | __visible void __pv_queued_spin_unlock(struct qspinlock *lock) | |
564 | { | |
d7804530 WL |
565 | u8 locked; |
566 | ||
567 | /* | |
568 | * We must not unlock if SLOW, because in that case we must first | |
569 | * unhash. Otherwise it would be possible to have multiple @lock | |
570 | * entries, which would be BAD. | |
571 | */ | |
625e88be | 572 | locked = cmpxchg_release(&lock->locked, _Q_LOCKED_VAL, 0); |
d7804530 WL |
573 | if (likely(locked == _Q_LOCKED_VAL)) |
574 | return; | |
575 | ||
576 | __pv_queued_spin_unlock_slowpath(lock, locked); | |
577 | } | |
578 | #endif /* __pv_queued_spin_unlock */ |