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1da177e4
LT
1/*
2 * Dynamic DMA mapping support.
3 *
563aaf06 4 * This implementation is a fallback for platforms that do not support
1da177e4
LT
5 * I/O TLBs (aka DMA address translation hardware).
6 * Copyright (C) 2000 Asit Mallick <Asit.K.Mallick@intel.com>
7 * Copyright (C) 2000 Goutham Rao <goutham.rao@intel.com>
8 * Copyright (C) 2000, 2003 Hewlett-Packard Co
9 * David Mosberger-Tang <davidm@hpl.hp.com>
10 *
11 * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API.
12 * 00/12/13 davidm Rename to swiotlb.c and add mark_clean() to avoid
13 * unnecessary i-cache flushing.
569c8bf5
JL
14 * 04/07/.. ak Better overflow handling. Assorted fixes.
15 * 05/09/10 linville Add support for syncing ranges, support syncing for
16 * DMA_BIDIRECTIONAL mappings, miscellaneous cleanup.
fb05a379 17 * 08/12/11 beckyb Add highmem support
1da177e4
LT
18 */
19
20#include <linux/cache.h>
17e5ad6c 21#include <linux/dma-mapping.h>
1da177e4 22#include <linux/mm.h>
8bc3bcc9 23#include <linux/export.h>
1da177e4
LT
24#include <linux/spinlock.h>
25#include <linux/string.h>
0016fdee 26#include <linux/swiotlb.h>
fb05a379 27#include <linux/pfn.h>
1da177e4
LT
28#include <linux/types.h>
29#include <linux/ctype.h>
ef9b1893 30#include <linux/highmem.h>
5a0e3ad6 31#include <linux/gfp.h>
1da177e4
LT
32
33#include <asm/io.h>
1da177e4 34#include <asm/dma.h>
17e5ad6c 35#include <asm/scatterlist.h>
1da177e4
LT
36
37#include <linux/init.h>
38#include <linux/bootmem.h>
a8522509 39#include <linux/iommu-helper.h>
1da177e4 40
ce5be5a1 41#define CREATE_TRACE_POINTS
2b2b614d
ZK
42#include <trace/events/swiotlb.h>
43
1da177e4
LT
44#define OFFSET(val,align) ((unsigned long) \
45 ( (val) & ( (align) - 1)))
46
0b9afede
AW
47#define SLABS_PER_PAGE (1 << (PAGE_SHIFT - IO_TLB_SHIFT))
48
49/*
50 * Minimum IO TLB size to bother booting with. Systems with mainly
51 * 64bit capable cards will only lightly use the swiotlb. If we can't
52 * allocate a contiguous 1MB, we're probably in trouble anyway.
53 */
54#define IO_TLB_MIN_SLABS ((1<<20) >> IO_TLB_SHIFT)
55
1da177e4
LT
56int swiotlb_force;
57
58/*
bfc5501f
KRW
59 * Used to do a quick range check in swiotlb_tbl_unmap_single and
60 * swiotlb_tbl_sync_single_*, to see if the memory was in fact allocated by this
1da177e4
LT
61 * API.
62 */
ff7204a7 63static phys_addr_t io_tlb_start, io_tlb_end;
1da177e4
LT
64
65/*
b595076a 66 * The number of IO TLB blocks (in groups of 64) between io_tlb_start and
1da177e4
LT
67 * io_tlb_end. This is command line adjustable via setup_io_tlb_npages.
68 */
69static unsigned long io_tlb_nslabs;
70
71/*
72 * When the IOMMU overflows we return a fallback buffer. This sets the size.
73 */
74static unsigned long io_tlb_overflow = 32*1024;
75
ee3f6ba8 76static phys_addr_t io_tlb_overflow_buffer;
1da177e4
LT
77
78/*
79 * This is a free list describing the number of free entries available from
80 * each index
81 */
82static unsigned int *io_tlb_list;
83static unsigned int io_tlb_index;
84
85/*
86 * We need to save away the original address corresponding to a mapped entry
87 * for the sync operations.
88 */
8e0629c1 89#define INVALID_PHYS_ADDR (~(phys_addr_t)0)
bc40ac66 90static phys_addr_t *io_tlb_orig_addr;
1da177e4
LT
91
92/*
93 * Protect the above data structures in the map and unmap calls
94 */
95static DEFINE_SPINLOCK(io_tlb_lock);
96
5740afdb
FT
97static int late_alloc;
98
1da177e4
LT
99static int __init
100setup_io_tlb_npages(char *str)
101{
102 if (isdigit(*str)) {
e8579e72 103 io_tlb_nslabs = simple_strtoul(str, &str, 0);
1da177e4
LT
104 /* avoid tail segment of size < IO_TLB_SEGSIZE */
105 io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE);
106 }
107 if (*str == ',')
108 ++str;
b18485e7 109 if (!strcmp(str, "force"))
1da177e4 110 swiotlb_force = 1;
b18485e7 111
c729de8f 112 return 0;
1da177e4 113}
c729de8f 114early_param("swiotlb", setup_io_tlb_npages);
1da177e4
LT
115/* make io_tlb_overflow tunable too? */
116
f21ffe9f 117unsigned long swiotlb_nr_tbl(void)
5f98ecdb
FT
118{
119 return io_tlb_nslabs;
120}
f21ffe9f 121EXPORT_SYMBOL_GPL(swiotlb_nr_tbl);
c729de8f
YL
122
123/* default to 64MB */
124#define IO_TLB_DEFAULT_SIZE (64UL<<20)
125unsigned long swiotlb_size_or_default(void)
126{
127 unsigned long size;
128
129 size = io_tlb_nslabs << IO_TLB_SHIFT;
130
131 return size ? size : (IO_TLB_DEFAULT_SIZE);
132}
133
02ca646e 134/* Note that this doesn't work with highmem page */
70a7d3cc
JF
135static dma_addr_t swiotlb_virt_to_bus(struct device *hwdev,
136 volatile void *address)
e08e1f7a 137{
862d196b 138 return phys_to_dma(hwdev, virt_to_phys(address));
e08e1f7a
IC
139}
140
ac2cbab2
YL
141static bool no_iotlb_memory;
142
ad32e8cb 143void swiotlb_print_info(void)
2e5b2b86 144{
ad32e8cb 145 unsigned long bytes = io_tlb_nslabs << IO_TLB_SHIFT;
ff7204a7 146 unsigned char *vstart, *vend;
2e5b2b86 147
ac2cbab2
YL
148 if (no_iotlb_memory) {
149 pr_warn("software IO TLB: No low mem\n");
150 return;
151 }
152
ff7204a7 153 vstart = phys_to_virt(io_tlb_start);
c40dba06 154 vend = phys_to_virt(io_tlb_end);
2e5b2b86 155
3af684c7 156 printk(KERN_INFO "software IO TLB [mem %#010llx-%#010llx] (%luMB) mapped at [%p-%p]\n",
ff7204a7 157 (unsigned long long)io_tlb_start,
c40dba06 158 (unsigned long long)io_tlb_end,
ff7204a7 159 bytes >> 20, vstart, vend - 1);
2e5b2b86
IC
160}
161
ac2cbab2 162int __init swiotlb_init_with_tbl(char *tlb, unsigned long nslabs, int verbose)
1da177e4 163{
ee3f6ba8 164 void *v_overflow_buffer;
563aaf06 165 unsigned long i, bytes;
1da177e4 166
abbceff7 167 bytes = nslabs << IO_TLB_SHIFT;
1da177e4 168
abbceff7 169 io_tlb_nslabs = nslabs;
ff7204a7
AD
170 io_tlb_start = __pa(tlb);
171 io_tlb_end = io_tlb_start + bytes;
1da177e4 172
ee3f6ba8
AD
173 /*
174 * Get the overflow emergency buffer
175 */
ad6492b8 176 v_overflow_buffer = memblock_virt_alloc_low_nopanic(
457ff1de
SS
177 PAGE_ALIGN(io_tlb_overflow),
178 PAGE_SIZE);
ee3f6ba8 179 if (!v_overflow_buffer)
ac2cbab2 180 return -ENOMEM;
ee3f6ba8
AD
181
182 io_tlb_overflow_buffer = __pa(v_overflow_buffer);
183
1da177e4
LT
184 /*
185 * Allocate and initialize the free list array. This array is used
186 * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE
187 * between io_tlb_start and io_tlb_end.
188 */
457ff1de
SS
189 io_tlb_list = memblock_virt_alloc(
190 PAGE_ALIGN(io_tlb_nslabs * sizeof(int)),
191 PAGE_SIZE);
457ff1de
SS
192 io_tlb_orig_addr = memblock_virt_alloc(
193 PAGE_ALIGN(io_tlb_nslabs * sizeof(phys_addr_t)),
194 PAGE_SIZE);
8e0629c1
JB
195 for (i = 0; i < io_tlb_nslabs; i++) {
196 io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE);
197 io_tlb_orig_addr[i] = INVALID_PHYS_ADDR;
198 }
199 io_tlb_index = 0;
1da177e4 200
ad32e8cb
FT
201 if (verbose)
202 swiotlb_print_info();
ac2cbab2
YL
203
204 return 0;
1da177e4
LT
205}
206
abbceff7
FT
207/*
208 * Statically reserve bounce buffer space and initialize bounce buffer data
209 * structures for the software IO TLB used to implement the DMA API.
210 */
ac2cbab2
YL
211void __init
212swiotlb_init(int verbose)
abbceff7 213{
c729de8f 214 size_t default_size = IO_TLB_DEFAULT_SIZE;
ff7204a7 215 unsigned char *vstart;
abbceff7
FT
216 unsigned long bytes;
217
218 if (!io_tlb_nslabs) {
219 io_tlb_nslabs = (default_size >> IO_TLB_SHIFT);
220 io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE);
221 }
222
223 bytes = io_tlb_nslabs << IO_TLB_SHIFT;
224
ac2cbab2 225 /* Get IO TLB memory from the low pages */
ad6492b8 226 vstart = memblock_virt_alloc_low_nopanic(PAGE_ALIGN(bytes), PAGE_SIZE);
ac2cbab2
YL
227 if (vstart && !swiotlb_init_with_tbl(vstart, io_tlb_nslabs, verbose))
228 return;
abbceff7 229
ac2cbab2 230 if (io_tlb_start)
457ff1de
SS
231 memblock_free_early(io_tlb_start,
232 PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT));
ac2cbab2
YL
233 pr_warn("Cannot allocate SWIOTLB buffer");
234 no_iotlb_memory = true;
1da177e4
LT
235}
236
0b9afede
AW
237/*
238 * Systems with larger DMA zones (those that don't support ISA) can
239 * initialize the swiotlb later using the slab allocator if needed.
240 * This should be just like above, but with some error catching.
241 */
242int
563aaf06 243swiotlb_late_init_with_default_size(size_t default_size)
0b9afede 244{
74838b75 245 unsigned long bytes, req_nslabs = io_tlb_nslabs;
ff7204a7 246 unsigned char *vstart = NULL;
0b9afede 247 unsigned int order;
74838b75 248 int rc = 0;
0b9afede
AW
249
250 if (!io_tlb_nslabs) {
251 io_tlb_nslabs = (default_size >> IO_TLB_SHIFT);
252 io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE);
253 }
254
255 /*
256 * Get IO TLB memory from the low pages
257 */
563aaf06 258 order = get_order(io_tlb_nslabs << IO_TLB_SHIFT);
0b9afede 259 io_tlb_nslabs = SLABS_PER_PAGE << order;
563aaf06 260 bytes = io_tlb_nslabs << IO_TLB_SHIFT;
0b9afede
AW
261
262 while ((SLABS_PER_PAGE << order) > IO_TLB_MIN_SLABS) {
ff7204a7
AD
263 vstart = (void *)__get_free_pages(GFP_DMA | __GFP_NOWARN,
264 order);
265 if (vstart)
0b9afede
AW
266 break;
267 order--;
268 }
269
ff7204a7 270 if (!vstart) {
74838b75
KRW
271 io_tlb_nslabs = req_nslabs;
272 return -ENOMEM;
273 }
563aaf06 274 if (order != get_order(bytes)) {
0b9afede
AW
275 printk(KERN_WARNING "Warning: only able to allocate %ld MB "
276 "for software IO TLB\n", (PAGE_SIZE << order) >> 20);
277 io_tlb_nslabs = SLABS_PER_PAGE << order;
278 }
ff7204a7 279 rc = swiotlb_late_init_with_tbl(vstart, io_tlb_nslabs);
74838b75 280 if (rc)
ff7204a7 281 free_pages((unsigned long)vstart, order);
74838b75
KRW
282 return rc;
283}
284
285int
286swiotlb_late_init_with_tbl(char *tlb, unsigned long nslabs)
287{
288 unsigned long i, bytes;
ee3f6ba8 289 unsigned char *v_overflow_buffer;
74838b75
KRW
290
291 bytes = nslabs << IO_TLB_SHIFT;
292
293 io_tlb_nslabs = nslabs;
ff7204a7
AD
294 io_tlb_start = virt_to_phys(tlb);
295 io_tlb_end = io_tlb_start + bytes;
74838b75 296
ff7204a7 297 memset(tlb, 0, bytes);
0b9afede 298
ee3f6ba8
AD
299 /*
300 * Get the overflow emergency buffer
301 */
302 v_overflow_buffer = (void *)__get_free_pages(GFP_DMA,
303 get_order(io_tlb_overflow));
304 if (!v_overflow_buffer)
305 goto cleanup2;
306
307 io_tlb_overflow_buffer = virt_to_phys(v_overflow_buffer);
308
0b9afede
AW
309 /*
310 * Allocate and initialize the free list array. This array is used
311 * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE
312 * between io_tlb_start and io_tlb_end.
313 */
314 io_tlb_list = (unsigned int *)__get_free_pages(GFP_KERNEL,
315 get_order(io_tlb_nslabs * sizeof(int)));
316 if (!io_tlb_list)
ee3f6ba8 317 goto cleanup3;
0b9afede 318
bc40ac66
BB
319 io_tlb_orig_addr = (phys_addr_t *)
320 __get_free_pages(GFP_KERNEL,
321 get_order(io_tlb_nslabs *
322 sizeof(phys_addr_t)));
0b9afede 323 if (!io_tlb_orig_addr)
ee3f6ba8 324 goto cleanup4;
0b9afede 325
8e0629c1
JB
326 for (i = 0; i < io_tlb_nslabs; i++) {
327 io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE);
328 io_tlb_orig_addr[i] = INVALID_PHYS_ADDR;
329 }
330 io_tlb_index = 0;
0b9afede 331
ad32e8cb 332 swiotlb_print_info();
0b9afede 333
5740afdb
FT
334 late_alloc = 1;
335
0b9afede
AW
336 return 0;
337
338cleanup4:
25667d67
TL
339 free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs *
340 sizeof(int)));
0b9afede 341 io_tlb_list = NULL;
ee3f6ba8
AD
342cleanup3:
343 free_pages((unsigned long)v_overflow_buffer,
344 get_order(io_tlb_overflow));
345 io_tlb_overflow_buffer = 0;
0b9afede 346cleanup2:
c40dba06 347 io_tlb_end = 0;
ff7204a7 348 io_tlb_start = 0;
74838b75 349 io_tlb_nslabs = 0;
0b9afede
AW
350 return -ENOMEM;
351}
352
5740afdb
FT
353void __init swiotlb_free(void)
354{
ee3f6ba8 355 if (!io_tlb_orig_addr)
5740afdb
FT
356 return;
357
358 if (late_alloc) {
ee3f6ba8 359 free_pages((unsigned long)phys_to_virt(io_tlb_overflow_buffer),
5740afdb
FT
360 get_order(io_tlb_overflow));
361 free_pages((unsigned long)io_tlb_orig_addr,
362 get_order(io_tlb_nslabs * sizeof(phys_addr_t)));
363 free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs *
364 sizeof(int)));
ff7204a7 365 free_pages((unsigned long)phys_to_virt(io_tlb_start),
5740afdb
FT
366 get_order(io_tlb_nslabs << IO_TLB_SHIFT));
367 } else {
457ff1de
SS
368 memblock_free_late(io_tlb_overflow_buffer,
369 PAGE_ALIGN(io_tlb_overflow));
370 memblock_free_late(__pa(io_tlb_orig_addr),
371 PAGE_ALIGN(io_tlb_nslabs * sizeof(phys_addr_t)));
372 memblock_free_late(__pa(io_tlb_list),
373 PAGE_ALIGN(io_tlb_nslabs * sizeof(int)));
374 memblock_free_late(io_tlb_start,
375 PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT));
5740afdb 376 }
f21ffe9f 377 io_tlb_nslabs = 0;
5740afdb
FT
378}
379
9c5a3621 380int is_swiotlb_buffer(phys_addr_t paddr)
640aebfe 381{
ff7204a7 382 return paddr >= io_tlb_start && paddr < io_tlb_end;
640aebfe
FT
383}
384
fb05a379
BB
385/*
386 * Bounce: copy the swiotlb buffer back to the original dma location
387 */
af51a9f1
AD
388static void swiotlb_bounce(phys_addr_t orig_addr, phys_addr_t tlb_addr,
389 size_t size, enum dma_data_direction dir)
fb05a379 390{
af51a9f1
AD
391 unsigned long pfn = PFN_DOWN(orig_addr);
392 unsigned char *vaddr = phys_to_virt(tlb_addr);
fb05a379
BB
393
394 if (PageHighMem(pfn_to_page(pfn))) {
395 /* The buffer does not have a mapping. Map it in and copy */
af51a9f1 396 unsigned int offset = orig_addr & ~PAGE_MASK;
fb05a379
BB
397 char *buffer;
398 unsigned int sz = 0;
399 unsigned long flags;
400
401 while (size) {
67131ad0 402 sz = min_t(size_t, PAGE_SIZE - offset, size);
fb05a379
BB
403
404 local_irq_save(flags);
c3eede8e 405 buffer = kmap_atomic(pfn_to_page(pfn));
fb05a379 406 if (dir == DMA_TO_DEVICE)
af51a9f1 407 memcpy(vaddr, buffer + offset, sz);
ef9b1893 408 else
af51a9f1 409 memcpy(buffer + offset, vaddr, sz);
c3eede8e 410 kunmap_atomic(buffer);
ef9b1893 411 local_irq_restore(flags);
fb05a379
BB
412
413 size -= sz;
414 pfn++;
af51a9f1 415 vaddr += sz;
fb05a379 416 offset = 0;
ef9b1893 417 }
af51a9f1
AD
418 } else if (dir == DMA_TO_DEVICE) {
419 memcpy(vaddr, phys_to_virt(orig_addr), size);
ef9b1893 420 } else {
af51a9f1 421 memcpy(phys_to_virt(orig_addr), vaddr, size);
ef9b1893 422 }
1b548f66
JF
423}
424
e05ed4d1
AD
425phys_addr_t swiotlb_tbl_map_single(struct device *hwdev,
426 dma_addr_t tbl_dma_addr,
427 phys_addr_t orig_addr, size_t size,
428 enum dma_data_direction dir)
1da177e4
LT
429{
430 unsigned long flags;
e05ed4d1 431 phys_addr_t tlb_addr;
1da177e4
LT
432 unsigned int nslots, stride, index, wrap;
433 int i;
681cc5cd
FT
434 unsigned long mask;
435 unsigned long offset_slots;
436 unsigned long max_slots;
437
ac2cbab2
YL
438 if (no_iotlb_memory)
439 panic("Can not allocate SWIOTLB buffer earlier and can't now provide you with the DMA bounce buffer");
440
681cc5cd 441 mask = dma_get_seg_boundary(hwdev);
681cc5cd 442
eb605a57
FT
443 tbl_dma_addr &= mask;
444
445 offset_slots = ALIGN(tbl_dma_addr, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT;
a5ddde4a
IC
446
447 /*
448 * Carefully handle integer overflow which can occur when mask == ~0UL.
449 */
b15a3891
JB
450 max_slots = mask + 1
451 ? ALIGN(mask + 1, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT
452 : 1UL << (BITS_PER_LONG - IO_TLB_SHIFT);
1da177e4
LT
453
454 /*
455 * For mappings greater than a page, we limit the stride (and
456 * hence alignment) to a page size.
457 */
458 nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT;
459 if (size > PAGE_SIZE)
460 stride = (1 << (PAGE_SHIFT - IO_TLB_SHIFT));
461 else
462 stride = 1;
463
34814545 464 BUG_ON(!nslots);
1da177e4
LT
465
466 /*
467 * Find suitable number of IO TLB entries size that will fit this
468 * request and allocate a buffer from that IO TLB pool.
469 */
470 spin_lock_irqsave(&io_tlb_lock, flags);
a7133a15
AM
471 index = ALIGN(io_tlb_index, stride);
472 if (index >= io_tlb_nslabs)
473 index = 0;
474 wrap = index;
475
476 do {
a8522509
FT
477 while (iommu_is_span_boundary(index, nslots, offset_slots,
478 max_slots)) {
b15a3891
JB
479 index += stride;
480 if (index >= io_tlb_nslabs)
481 index = 0;
a7133a15
AM
482 if (index == wrap)
483 goto not_found;
484 }
485
486 /*
487 * If we find a slot that indicates we have 'nslots' number of
488 * contiguous buffers, we allocate the buffers from that slot
489 * and mark the entries as '0' indicating unavailable.
490 */
491 if (io_tlb_list[index] >= nslots) {
492 int count = 0;
493
494 for (i = index; i < (int) (index + nslots); i++)
495 io_tlb_list[i] = 0;
496 for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE - 1) && io_tlb_list[i]; i--)
497 io_tlb_list[i] = ++count;
e05ed4d1 498 tlb_addr = io_tlb_start + (index << IO_TLB_SHIFT);
1da177e4 499
a7133a15
AM
500 /*
501 * Update the indices to avoid searching in the next
502 * round.
503 */
504 io_tlb_index = ((index + nslots) < io_tlb_nslabs
505 ? (index + nslots) : 0);
506
507 goto found;
508 }
509 index += stride;
510 if (index >= io_tlb_nslabs)
511 index = 0;
512 } while (index != wrap);
513
514not_found:
515 spin_unlock_irqrestore(&io_tlb_lock, flags);
0cb637bf
KRW
516 if (printk_ratelimit())
517 dev_warn(hwdev, "swiotlb buffer is full (sz: %zd bytes)\n", size);
e05ed4d1 518 return SWIOTLB_MAP_ERROR;
a7133a15 519found:
1da177e4
LT
520 spin_unlock_irqrestore(&io_tlb_lock, flags);
521
522 /*
523 * Save away the mapping from the original address to the DMA address.
524 * This is needed when we sync the memory. Then we sync the buffer if
525 * needed.
526 */
bc40ac66 527 for (i = 0; i < nslots; i++)
e05ed4d1 528 io_tlb_orig_addr[index+i] = orig_addr + (i << IO_TLB_SHIFT);
1da177e4 529 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)
af51a9f1 530 swiotlb_bounce(orig_addr, tlb_addr, size, DMA_TO_DEVICE);
1da177e4 531
e05ed4d1 532 return tlb_addr;
1da177e4 533}
d7ef1533 534EXPORT_SYMBOL_GPL(swiotlb_tbl_map_single);
1da177e4 535
eb605a57
FT
536/*
537 * Allocates bounce buffer and returns its kernel virtual address.
538 */
539
e05ed4d1
AD
540phys_addr_t map_single(struct device *hwdev, phys_addr_t phys, size_t size,
541 enum dma_data_direction dir)
eb605a57 542{
ff7204a7 543 dma_addr_t start_dma_addr = phys_to_dma(hwdev, io_tlb_start);
eb605a57
FT
544
545 return swiotlb_tbl_map_single(hwdev, start_dma_addr, phys, size, dir);
546}
547
1da177e4
LT
548/*
549 * dma_addr is the kernel virtual address of the bounce buffer to unmap.
550 */
61ca08c3
AD
551void swiotlb_tbl_unmap_single(struct device *hwdev, phys_addr_t tlb_addr,
552 size_t size, enum dma_data_direction dir)
1da177e4
LT
553{
554 unsigned long flags;
555 int i, count, nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT;
61ca08c3
AD
556 int index = (tlb_addr - io_tlb_start) >> IO_TLB_SHIFT;
557 phys_addr_t orig_addr = io_tlb_orig_addr[index];
1da177e4
LT
558
559 /*
560 * First, sync the memory before unmapping the entry
561 */
8e0629c1
JB
562 if (orig_addr != INVALID_PHYS_ADDR &&
563 ((dir == DMA_FROM_DEVICE) || (dir == DMA_BIDIRECTIONAL)))
af51a9f1 564 swiotlb_bounce(orig_addr, tlb_addr, size, DMA_FROM_DEVICE);
1da177e4
LT
565
566 /*
567 * Return the buffer to the free list by setting the corresponding
af901ca1 568 * entries to indicate the number of contiguous entries available.
1da177e4
LT
569 * While returning the entries to the free list, we merge the entries
570 * with slots below and above the pool being returned.
571 */
572 spin_lock_irqsave(&io_tlb_lock, flags);
573 {
574 count = ((index + nslots) < ALIGN(index + 1, IO_TLB_SEGSIZE) ?
575 io_tlb_list[index + nslots] : 0);
576 /*
577 * Step 1: return the slots to the free list, merging the
578 * slots with superceeding slots
579 */
8e0629c1 580 for (i = index + nslots - 1; i >= index; i--) {
1da177e4 581 io_tlb_list[i] = ++count;
8e0629c1
JB
582 io_tlb_orig_addr[i] = INVALID_PHYS_ADDR;
583 }
1da177e4
LT
584 /*
585 * Step 2: merge the returned slots with the preceding slots,
586 * if available (non zero)
587 */
588 for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE -1) && io_tlb_list[i]; i--)
589 io_tlb_list[i] = ++count;
590 }
591 spin_unlock_irqrestore(&io_tlb_lock, flags);
592}
d7ef1533 593EXPORT_SYMBOL_GPL(swiotlb_tbl_unmap_single);
1da177e4 594
fbfda893
AD
595void swiotlb_tbl_sync_single(struct device *hwdev, phys_addr_t tlb_addr,
596 size_t size, enum dma_data_direction dir,
597 enum dma_sync_target target)
1da177e4 598{
fbfda893
AD
599 int index = (tlb_addr - io_tlb_start) >> IO_TLB_SHIFT;
600 phys_addr_t orig_addr = io_tlb_orig_addr[index];
bc40ac66 601
8e0629c1
JB
602 if (orig_addr == INVALID_PHYS_ADDR)
603 return;
fbfda893 604 orig_addr += (unsigned long)tlb_addr & ((1 << IO_TLB_SHIFT) - 1);
df336d1c 605
de69e0f0
JL
606 switch (target) {
607 case SYNC_FOR_CPU:
608 if (likely(dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL))
af51a9f1 609 swiotlb_bounce(orig_addr, tlb_addr,
fbfda893 610 size, DMA_FROM_DEVICE);
34814545
ES
611 else
612 BUG_ON(dir != DMA_TO_DEVICE);
de69e0f0
JL
613 break;
614 case SYNC_FOR_DEVICE:
615 if (likely(dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL))
af51a9f1 616 swiotlb_bounce(orig_addr, tlb_addr,
fbfda893 617 size, DMA_TO_DEVICE);
34814545
ES
618 else
619 BUG_ON(dir != DMA_FROM_DEVICE);
de69e0f0
JL
620 break;
621 default:
1da177e4 622 BUG();
de69e0f0 623 }
1da177e4 624}
d7ef1533 625EXPORT_SYMBOL_GPL(swiotlb_tbl_sync_single);
1da177e4
LT
626
627void *
628swiotlb_alloc_coherent(struct device *hwdev, size_t size,
06a54497 629 dma_addr_t *dma_handle, gfp_t flags)
1da177e4 630{
563aaf06 631 dma_addr_t dev_addr;
1da177e4
LT
632 void *ret;
633 int order = get_order(size);
284901a9 634 u64 dma_mask = DMA_BIT_MASK(32);
1e74f300
FT
635
636 if (hwdev && hwdev->coherent_dma_mask)
637 dma_mask = hwdev->coherent_dma_mask;
1da177e4 638
25667d67 639 ret = (void *)__get_free_pages(flags, order);
e05ed4d1
AD
640 if (ret) {
641 dev_addr = swiotlb_virt_to_bus(hwdev, ret);
642 if (dev_addr + size - 1 > dma_mask) {
643 /*
644 * The allocated memory isn't reachable by the device.
645 */
646 free_pages((unsigned long) ret, order);
647 ret = NULL;
648 }
1da177e4
LT
649 }
650 if (!ret) {
651 /*
bfc5501f
KRW
652 * We are either out of memory or the device can't DMA to
653 * GFP_DMA memory; fall back on map_single(), which
ceb5ac32 654 * will grab memory from the lowest available address range.
1da177e4 655 */
e05ed4d1
AD
656 phys_addr_t paddr = map_single(hwdev, 0, size, DMA_FROM_DEVICE);
657 if (paddr == SWIOTLB_MAP_ERROR)
1da177e4 658 return NULL;
1da177e4 659
e05ed4d1
AD
660 ret = phys_to_virt(paddr);
661 dev_addr = phys_to_dma(hwdev, paddr);
1da177e4 662
61ca08c3
AD
663 /* Confirm address can be DMA'd by device */
664 if (dev_addr + size - 1 > dma_mask) {
665 printk("hwdev DMA mask = 0x%016Lx, dev_addr = 0x%016Lx\n",
666 (unsigned long long)dma_mask,
667 (unsigned long long)dev_addr);
a2b89b59 668
61ca08c3
AD
669 /* DMA_TO_DEVICE to avoid memcpy in unmap_single */
670 swiotlb_tbl_unmap_single(hwdev, paddr,
671 size, DMA_TO_DEVICE);
672 return NULL;
673 }
1da177e4 674 }
e05ed4d1 675
1da177e4 676 *dma_handle = dev_addr;
e05ed4d1
AD
677 memset(ret, 0, size);
678
1da177e4
LT
679 return ret;
680}
874d6a95 681EXPORT_SYMBOL(swiotlb_alloc_coherent);
1da177e4
LT
682
683void
684swiotlb_free_coherent(struct device *hwdev, size_t size, void *vaddr,
02ca646e 685 dma_addr_t dev_addr)
1da177e4 686{
862d196b 687 phys_addr_t paddr = dma_to_phys(hwdev, dev_addr);
02ca646e 688
aa24886e 689 WARN_ON(irqs_disabled());
02ca646e
FT
690 if (!is_swiotlb_buffer(paddr))
691 free_pages((unsigned long)vaddr, get_order(size));
1da177e4 692 else
bfc5501f 693 /* DMA_TO_DEVICE to avoid memcpy in swiotlb_tbl_unmap_single */
61ca08c3 694 swiotlb_tbl_unmap_single(hwdev, paddr, size, DMA_TO_DEVICE);
1da177e4 695}
874d6a95 696EXPORT_SYMBOL(swiotlb_free_coherent);
1da177e4
LT
697
698static void
22d48269
KRW
699swiotlb_full(struct device *dev, size_t size, enum dma_data_direction dir,
700 int do_panic)
1da177e4
LT
701{
702 /*
703 * Ran out of IOMMU space for this operation. This is very bad.
704 * Unfortunately the drivers cannot handle this operation properly.
17e5ad6c 705 * unless they check for dma_mapping_error (most don't)
1da177e4
LT
706 * When the mapping is small enough return a static buffer to limit
707 * the damage, or panic when the transfer is too big.
708 */
563aaf06 709 printk(KERN_ERR "DMA: Out of SW-IOMMU space for %zu bytes at "
94b32486 710 "device %s\n", size, dev ? dev_name(dev) : "?");
1da177e4 711
c7084b35
CD
712 if (size <= io_tlb_overflow || !do_panic)
713 return;
714
715 if (dir == DMA_BIDIRECTIONAL)
716 panic("DMA: Random memory could be DMA accessed\n");
717 if (dir == DMA_FROM_DEVICE)
718 panic("DMA: Random memory could be DMA written\n");
719 if (dir == DMA_TO_DEVICE)
720 panic("DMA: Random memory could be DMA read\n");
1da177e4
LT
721}
722
723/*
724 * Map a single buffer of the indicated size for DMA in streaming mode. The
17e5ad6c 725 * physical address to use is returned.
1da177e4
LT
726 *
727 * Once the device is given the dma address, the device owns this memory until
ceb5ac32 728 * either swiotlb_unmap_page or swiotlb_dma_sync_single is performed.
1da177e4 729 */
f98eee8e
FT
730dma_addr_t swiotlb_map_page(struct device *dev, struct page *page,
731 unsigned long offset, size_t size,
732 enum dma_data_direction dir,
733 struct dma_attrs *attrs)
1da177e4 734{
e05ed4d1 735 phys_addr_t map, phys = page_to_phys(page) + offset;
862d196b 736 dma_addr_t dev_addr = phys_to_dma(dev, phys);
1da177e4 737
34814545 738 BUG_ON(dir == DMA_NONE);
1da177e4 739 /*
ceb5ac32 740 * If the address happens to be in the device's DMA window,
1da177e4
LT
741 * we can safely return the device addr and not worry about bounce
742 * buffering it.
743 */
b9394647 744 if (dma_capable(dev, dev_addr, size) && !swiotlb_force)
1da177e4
LT
745 return dev_addr;
746
2b2b614d
ZK
747 trace_swiotlb_bounced(dev, dev_addr, size, swiotlb_force);
748
e05ed4d1 749 /* Oh well, have to allocate and map a bounce buffer. */
f98eee8e 750 map = map_single(dev, phys, size, dir);
e05ed4d1 751 if (map == SWIOTLB_MAP_ERROR) {
f98eee8e 752 swiotlb_full(dev, size, dir, 1);
ee3f6ba8 753 return phys_to_dma(dev, io_tlb_overflow_buffer);
1da177e4
LT
754 }
755
e05ed4d1 756 dev_addr = phys_to_dma(dev, map);
1da177e4 757
e05ed4d1 758 /* Ensure that the address returned is DMA'ble */
fba99fa3 759 if (!dma_capable(dev, dev_addr, size)) {
61ca08c3 760 swiotlb_tbl_unmap_single(dev, map, size, dir);
ee3f6ba8 761 return phys_to_dma(dev, io_tlb_overflow_buffer);
fba99fa3 762 }
1da177e4
LT
763
764 return dev_addr;
765}
f98eee8e 766EXPORT_SYMBOL_GPL(swiotlb_map_page);
1da177e4 767
1da177e4
LT
768/*
769 * Unmap a single streaming mode DMA translation. The dma_addr and size must
ceb5ac32 770 * match what was provided for in a previous swiotlb_map_page call. All
1da177e4
LT
771 * other usages are undefined.
772 *
773 * After this call, reads by the cpu to the buffer are guaranteed to see
774 * whatever the device wrote there.
775 */
7fcebbd2 776static void unmap_single(struct device *hwdev, dma_addr_t dev_addr,
22d48269 777 size_t size, enum dma_data_direction dir)
1da177e4 778{
862d196b 779 phys_addr_t paddr = dma_to_phys(hwdev, dev_addr);
1da177e4 780
34814545 781 BUG_ON(dir == DMA_NONE);
7fcebbd2 782
02ca646e 783 if (is_swiotlb_buffer(paddr)) {
61ca08c3 784 swiotlb_tbl_unmap_single(hwdev, paddr, size, dir);
7fcebbd2
BB
785 return;
786 }
787
788 if (dir != DMA_FROM_DEVICE)
789 return;
790
02ca646e
FT
791 /*
792 * phys_to_virt doesn't work with hihgmem page but we could
793 * call dma_mark_clean() with hihgmem page here. However, we
794 * are fine since dma_mark_clean() is null on POWERPC. We can
795 * make dma_mark_clean() take a physical address if necessary.
796 */
797 dma_mark_clean(phys_to_virt(paddr), size);
7fcebbd2
BB
798}
799
800void swiotlb_unmap_page(struct device *hwdev, dma_addr_t dev_addr,
801 size_t size, enum dma_data_direction dir,
802 struct dma_attrs *attrs)
803{
804 unmap_single(hwdev, dev_addr, size, dir);
1da177e4 805}
f98eee8e 806EXPORT_SYMBOL_GPL(swiotlb_unmap_page);
874d6a95 807
1da177e4
LT
808/*
809 * Make physical memory consistent for a single streaming mode DMA translation
810 * after a transfer.
811 *
ceb5ac32 812 * If you perform a swiotlb_map_page() but wish to interrogate the buffer
17e5ad6c
TL
813 * using the cpu, yet do not wish to teardown the dma mapping, you must
814 * call this function before doing so. At the next point you give the dma
1da177e4
LT
815 * address back to the card, you must first perform a
816 * swiotlb_dma_sync_for_device, and then the device again owns the buffer
817 */
be6b0267 818static void
8270f3f1 819swiotlb_sync_single(struct device *hwdev, dma_addr_t dev_addr,
d7ef1533
KRW
820 size_t size, enum dma_data_direction dir,
821 enum dma_sync_target target)
1da177e4 822{
862d196b 823 phys_addr_t paddr = dma_to_phys(hwdev, dev_addr);
1da177e4 824
34814545 825 BUG_ON(dir == DMA_NONE);
380d6878 826
02ca646e 827 if (is_swiotlb_buffer(paddr)) {
fbfda893 828 swiotlb_tbl_sync_single(hwdev, paddr, size, dir, target);
380d6878
BB
829 return;
830 }
831
832 if (dir != DMA_FROM_DEVICE)
833 return;
834
02ca646e 835 dma_mark_clean(phys_to_virt(paddr), size);
1da177e4
LT
836}
837
8270f3f1
JL
838void
839swiotlb_sync_single_for_cpu(struct device *hwdev, dma_addr_t dev_addr,
160c1d8e 840 size_t size, enum dma_data_direction dir)
8270f3f1 841{
de69e0f0 842 swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_CPU);
8270f3f1 843}
874d6a95 844EXPORT_SYMBOL(swiotlb_sync_single_for_cpu);
8270f3f1 845
1da177e4
LT
846void
847swiotlb_sync_single_for_device(struct device *hwdev, dma_addr_t dev_addr,
160c1d8e 848 size_t size, enum dma_data_direction dir)
1da177e4 849{
de69e0f0 850 swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_DEVICE);
1da177e4 851}
874d6a95 852EXPORT_SYMBOL(swiotlb_sync_single_for_device);
1da177e4
LT
853
854/*
855 * Map a set of buffers described by scatterlist in streaming mode for DMA.
ceb5ac32 856 * This is the scatter-gather version of the above swiotlb_map_page
1da177e4
LT
857 * interface. Here the scatter gather list elements are each tagged with the
858 * appropriate dma address and length. They are obtained via
859 * sg_dma_{address,length}(SG).
860 *
861 * NOTE: An implementation may be able to use a smaller number of
862 * DMA address/length pairs than there are SG table elements.
863 * (for example via virtual mapping capabilities)
864 * The routine returns the number of addr/length pairs actually
865 * used, at most nents.
866 *
ceb5ac32 867 * Device ownership issues as mentioned above for swiotlb_map_page are the
1da177e4
LT
868 * same here.
869 */
870int
309df0c5 871swiotlb_map_sg_attrs(struct device *hwdev, struct scatterlist *sgl, int nelems,
160c1d8e 872 enum dma_data_direction dir, struct dma_attrs *attrs)
1da177e4 873{
dbfd49fe 874 struct scatterlist *sg;
1da177e4
LT
875 int i;
876
34814545 877 BUG_ON(dir == DMA_NONE);
1da177e4 878
dbfd49fe 879 for_each_sg(sgl, sg, nelems, i) {
961d7d0e 880 phys_addr_t paddr = sg_phys(sg);
862d196b 881 dma_addr_t dev_addr = phys_to_dma(hwdev, paddr);
bc40ac66 882
cf56e3f2 883 if (swiotlb_force ||
b9394647 884 !dma_capable(hwdev, dev_addr, sg->length)) {
e05ed4d1
AD
885 phys_addr_t map = map_single(hwdev, sg_phys(sg),
886 sg->length, dir);
887 if (map == SWIOTLB_MAP_ERROR) {
1da177e4
LT
888 /* Don't panic here, we expect map_sg users
889 to do proper error handling. */
890 swiotlb_full(hwdev, sg->length, dir, 0);
309df0c5
AK
891 swiotlb_unmap_sg_attrs(hwdev, sgl, i, dir,
892 attrs);
4d86ec7a 893 sg_dma_len(sgl) = 0;
1da177e4
LT
894 return 0;
895 }
e05ed4d1 896 sg->dma_address = phys_to_dma(hwdev, map);
1da177e4
LT
897 } else
898 sg->dma_address = dev_addr;
4d86ec7a 899 sg_dma_len(sg) = sg->length;
1da177e4
LT
900 }
901 return nelems;
902}
309df0c5
AK
903EXPORT_SYMBOL(swiotlb_map_sg_attrs);
904
905int
906swiotlb_map_sg(struct device *hwdev, struct scatterlist *sgl, int nelems,
22d48269 907 enum dma_data_direction dir)
309df0c5
AK
908{
909 return swiotlb_map_sg_attrs(hwdev, sgl, nelems, dir, NULL);
910}
874d6a95 911EXPORT_SYMBOL(swiotlb_map_sg);
1da177e4
LT
912
913/*
914 * Unmap a set of streaming mode DMA translations. Again, cpu read rules
ceb5ac32 915 * concerning calls here are the same as for swiotlb_unmap_page() above.
1da177e4
LT
916 */
917void
309df0c5 918swiotlb_unmap_sg_attrs(struct device *hwdev, struct scatterlist *sgl,
160c1d8e 919 int nelems, enum dma_data_direction dir, struct dma_attrs *attrs)
1da177e4 920{
dbfd49fe 921 struct scatterlist *sg;
1da177e4
LT
922 int i;
923
34814545 924 BUG_ON(dir == DMA_NONE);
1da177e4 925
7fcebbd2 926 for_each_sg(sgl, sg, nelems, i)
4d86ec7a 927 unmap_single(hwdev, sg->dma_address, sg_dma_len(sg), dir);
7fcebbd2 928
1da177e4 929}
309df0c5
AK
930EXPORT_SYMBOL(swiotlb_unmap_sg_attrs);
931
932void
933swiotlb_unmap_sg(struct device *hwdev, struct scatterlist *sgl, int nelems,
22d48269 934 enum dma_data_direction dir)
309df0c5
AK
935{
936 return swiotlb_unmap_sg_attrs(hwdev, sgl, nelems, dir, NULL);
937}
874d6a95 938EXPORT_SYMBOL(swiotlb_unmap_sg);
1da177e4
LT
939
940/*
941 * Make physical memory consistent for a set of streaming mode DMA translations
942 * after a transfer.
943 *
944 * The same as swiotlb_sync_single_* but for a scatter-gather list, same rules
945 * and usage.
946 */
be6b0267 947static void
dbfd49fe 948swiotlb_sync_sg(struct device *hwdev, struct scatterlist *sgl,
d7ef1533
KRW
949 int nelems, enum dma_data_direction dir,
950 enum dma_sync_target target)
1da177e4 951{
dbfd49fe 952 struct scatterlist *sg;
1da177e4
LT
953 int i;
954
380d6878
BB
955 for_each_sg(sgl, sg, nelems, i)
956 swiotlb_sync_single(hwdev, sg->dma_address,
4d86ec7a 957 sg_dma_len(sg), dir, target);
1da177e4
LT
958}
959
8270f3f1
JL
960void
961swiotlb_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg,
160c1d8e 962 int nelems, enum dma_data_direction dir)
8270f3f1 963{
de69e0f0 964 swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_CPU);
8270f3f1 965}
874d6a95 966EXPORT_SYMBOL(swiotlb_sync_sg_for_cpu);
8270f3f1 967
1da177e4
LT
968void
969swiotlb_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg,
160c1d8e 970 int nelems, enum dma_data_direction dir)
1da177e4 971{
de69e0f0 972 swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_DEVICE);
1da177e4 973}
874d6a95 974EXPORT_SYMBOL(swiotlb_sync_sg_for_device);
1da177e4
LT
975
976int
8d8bb39b 977swiotlb_dma_mapping_error(struct device *hwdev, dma_addr_t dma_addr)
1da177e4 978{
ee3f6ba8 979 return (dma_addr == phys_to_dma(hwdev, io_tlb_overflow_buffer));
1da177e4 980}
874d6a95 981EXPORT_SYMBOL(swiotlb_dma_mapping_error);
1da177e4
LT
982
983/*
17e5ad6c 984 * Return whether the given device DMA address mask can be supported
1da177e4 985 * properly. For example, if your device can only drive the low 24-bits
17e5ad6c 986 * during bus mastering, then you would pass 0x00ffffff as the mask to
1da177e4
LT
987 * this function.
988 */
989int
563aaf06 990swiotlb_dma_supported(struct device *hwdev, u64 mask)
1da177e4 991{
c40dba06 992 return phys_to_dma(hwdev, io_tlb_end - 1) <= mask;
1da177e4 993}
1da177e4 994EXPORT_SYMBOL(swiotlb_dma_supported);