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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Dynamic DMA mapping support. | |
3 | * | |
563aaf06 | 4 | * This implementation is a fallback for platforms that do not support |
1da177e4 LT |
5 | * I/O TLBs (aka DMA address translation hardware). |
6 | * Copyright (C) 2000 Asit Mallick <Asit.K.Mallick@intel.com> | |
7 | * Copyright (C) 2000 Goutham Rao <goutham.rao@intel.com> | |
8 | * Copyright (C) 2000, 2003 Hewlett-Packard Co | |
9 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
10 | * | |
11 | * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API. | |
12 | * 00/12/13 davidm Rename to swiotlb.c and add mark_clean() to avoid | |
13 | * unnecessary i-cache flushing. | |
569c8bf5 JL |
14 | * 04/07/.. ak Better overflow handling. Assorted fixes. |
15 | * 05/09/10 linville Add support for syncing ranges, support syncing for | |
16 | * DMA_BIDIRECTIONAL mappings, miscellaneous cleanup. | |
1da177e4 LT |
17 | */ |
18 | ||
19 | #include <linux/cache.h> | |
17e5ad6c | 20 | #include <linux/dma-mapping.h> |
1da177e4 LT |
21 | #include <linux/mm.h> |
22 | #include <linux/module.h> | |
1da177e4 LT |
23 | #include <linux/spinlock.h> |
24 | #include <linux/string.h> | |
25 | #include <linux/types.h> | |
26 | #include <linux/ctype.h> | |
27 | ||
28 | #include <asm/io.h> | |
1da177e4 | 29 | #include <asm/dma.h> |
17e5ad6c | 30 | #include <asm/scatterlist.h> |
1da177e4 LT |
31 | |
32 | #include <linux/init.h> | |
33 | #include <linux/bootmem.h> | |
a8522509 | 34 | #include <linux/iommu-helper.h> |
1da177e4 LT |
35 | |
36 | #define OFFSET(val,align) ((unsigned long) \ | |
37 | ( (val) & ( (align) - 1))) | |
38 | ||
f9527f12 | 39 | #define SG_ENT_VIRT_ADDRESS(sg) (sg_virt((sg))) |
93fbff63 | 40 | #define SG_ENT_PHYS_ADDRESS(sg) virt_to_bus(SG_ENT_VIRT_ADDRESS(sg)) |
1da177e4 LT |
41 | |
42 | /* | |
43 | * Maximum allowable number of contiguous slabs to map, | |
44 | * must be a power of 2. What is the appropriate value ? | |
45 | * The complexity of {map,unmap}_single is linearly dependent on this value. | |
46 | */ | |
47 | #define IO_TLB_SEGSIZE 128 | |
48 | ||
49 | /* | |
50 | * log of the size of each IO TLB slab. The number of slabs is command line | |
51 | * controllable. | |
52 | */ | |
53 | #define IO_TLB_SHIFT 11 | |
54 | ||
0b9afede AW |
55 | #define SLABS_PER_PAGE (1 << (PAGE_SHIFT - IO_TLB_SHIFT)) |
56 | ||
57 | /* | |
58 | * Minimum IO TLB size to bother booting with. Systems with mainly | |
59 | * 64bit capable cards will only lightly use the swiotlb. If we can't | |
60 | * allocate a contiguous 1MB, we're probably in trouble anyway. | |
61 | */ | |
62 | #define IO_TLB_MIN_SLABS ((1<<20) >> IO_TLB_SHIFT) | |
63 | ||
de69e0f0 JL |
64 | /* |
65 | * Enumeration for sync targets | |
66 | */ | |
67 | enum dma_sync_target { | |
68 | SYNC_FOR_CPU = 0, | |
69 | SYNC_FOR_DEVICE = 1, | |
70 | }; | |
71 | ||
1da177e4 LT |
72 | int swiotlb_force; |
73 | ||
74 | /* | |
75 | * Used to do a quick range check in swiotlb_unmap_single and | |
76 | * swiotlb_sync_single_*, to see if the memory was in fact allocated by this | |
77 | * API. | |
78 | */ | |
79 | static char *io_tlb_start, *io_tlb_end; | |
80 | ||
81 | /* | |
82 | * The number of IO TLB blocks (in groups of 64) betweeen io_tlb_start and | |
83 | * io_tlb_end. This is command line adjustable via setup_io_tlb_npages. | |
84 | */ | |
85 | static unsigned long io_tlb_nslabs; | |
86 | ||
87 | /* | |
88 | * When the IOMMU overflows we return a fallback buffer. This sets the size. | |
89 | */ | |
90 | static unsigned long io_tlb_overflow = 32*1024; | |
91 | ||
92 | void *io_tlb_overflow_buffer; | |
93 | ||
94 | /* | |
95 | * This is a free list describing the number of free entries available from | |
96 | * each index | |
97 | */ | |
98 | static unsigned int *io_tlb_list; | |
99 | static unsigned int io_tlb_index; | |
100 | ||
101 | /* | |
102 | * We need to save away the original address corresponding to a mapped entry | |
103 | * for the sync operations. | |
104 | */ | |
25667d67 | 105 | static unsigned char **io_tlb_orig_addr; |
1da177e4 LT |
106 | |
107 | /* | |
108 | * Protect the above data structures in the map and unmap calls | |
109 | */ | |
110 | static DEFINE_SPINLOCK(io_tlb_lock); | |
111 | ||
112 | static int __init | |
113 | setup_io_tlb_npages(char *str) | |
114 | { | |
115 | if (isdigit(*str)) { | |
e8579e72 | 116 | io_tlb_nslabs = simple_strtoul(str, &str, 0); |
1da177e4 LT |
117 | /* avoid tail segment of size < IO_TLB_SEGSIZE */ |
118 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
119 | } | |
120 | if (*str == ',') | |
121 | ++str; | |
122 | if (!strcmp(str, "force")) | |
123 | swiotlb_force = 1; | |
124 | return 1; | |
125 | } | |
126 | __setup("swiotlb=", setup_io_tlb_npages); | |
127 | /* make io_tlb_overflow tunable too? */ | |
128 | ||
129 | /* | |
130 | * Statically reserve bounce buffer space and initialize bounce buffer data | |
17e5ad6c | 131 | * structures for the software IO TLB used to implement the DMA API. |
1da177e4 | 132 | */ |
563aaf06 JB |
133 | void __init |
134 | swiotlb_init_with_default_size(size_t default_size) | |
1da177e4 | 135 | { |
563aaf06 | 136 | unsigned long i, bytes; |
1da177e4 LT |
137 | |
138 | if (!io_tlb_nslabs) { | |
e8579e72 | 139 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); |
1da177e4 LT |
140 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); |
141 | } | |
142 | ||
563aaf06 JB |
143 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
144 | ||
1da177e4 LT |
145 | /* |
146 | * Get IO TLB memory from the low pages | |
147 | */ | |
563aaf06 | 148 | io_tlb_start = alloc_bootmem_low_pages(bytes); |
1da177e4 LT |
149 | if (!io_tlb_start) |
150 | panic("Cannot allocate SWIOTLB buffer"); | |
563aaf06 | 151 | io_tlb_end = io_tlb_start + bytes; |
1da177e4 LT |
152 | |
153 | /* | |
154 | * Allocate and initialize the free list array. This array is used | |
155 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
156 | * between io_tlb_start and io_tlb_end. | |
157 | */ | |
158 | io_tlb_list = alloc_bootmem(io_tlb_nslabs * sizeof(int)); | |
25667d67 | 159 | for (i = 0; i < io_tlb_nslabs; i++) |
1da177e4 LT |
160 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); |
161 | io_tlb_index = 0; | |
25667d67 | 162 | io_tlb_orig_addr = alloc_bootmem(io_tlb_nslabs * sizeof(char *)); |
1da177e4 LT |
163 | |
164 | /* | |
165 | * Get the overflow emergency buffer | |
166 | */ | |
167 | io_tlb_overflow_buffer = alloc_bootmem_low(io_tlb_overflow); | |
563aaf06 JB |
168 | if (!io_tlb_overflow_buffer) |
169 | panic("Cannot allocate SWIOTLB overflow buffer!\n"); | |
170 | ||
25667d67 TL |
171 | printk(KERN_INFO "Placing software IO TLB between 0x%lx - 0x%lx\n", |
172 | virt_to_bus(io_tlb_start), virt_to_bus(io_tlb_end)); | |
1da177e4 LT |
173 | } |
174 | ||
563aaf06 JB |
175 | void __init |
176 | swiotlb_init(void) | |
1da177e4 | 177 | { |
25667d67 | 178 | swiotlb_init_with_default_size(64 * (1<<20)); /* default to 64MB */ |
1da177e4 LT |
179 | } |
180 | ||
0b9afede AW |
181 | /* |
182 | * Systems with larger DMA zones (those that don't support ISA) can | |
183 | * initialize the swiotlb later using the slab allocator if needed. | |
184 | * This should be just like above, but with some error catching. | |
185 | */ | |
186 | int | |
563aaf06 | 187 | swiotlb_late_init_with_default_size(size_t default_size) |
0b9afede | 188 | { |
563aaf06 | 189 | unsigned long i, bytes, req_nslabs = io_tlb_nslabs; |
0b9afede AW |
190 | unsigned int order; |
191 | ||
192 | if (!io_tlb_nslabs) { | |
193 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); | |
194 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
195 | } | |
196 | ||
197 | /* | |
198 | * Get IO TLB memory from the low pages | |
199 | */ | |
563aaf06 | 200 | order = get_order(io_tlb_nslabs << IO_TLB_SHIFT); |
0b9afede | 201 | io_tlb_nslabs = SLABS_PER_PAGE << order; |
563aaf06 | 202 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
0b9afede AW |
203 | |
204 | while ((SLABS_PER_PAGE << order) > IO_TLB_MIN_SLABS) { | |
205 | io_tlb_start = (char *)__get_free_pages(GFP_DMA | __GFP_NOWARN, | |
206 | order); | |
207 | if (io_tlb_start) | |
208 | break; | |
209 | order--; | |
210 | } | |
211 | ||
212 | if (!io_tlb_start) | |
213 | goto cleanup1; | |
214 | ||
563aaf06 | 215 | if (order != get_order(bytes)) { |
0b9afede AW |
216 | printk(KERN_WARNING "Warning: only able to allocate %ld MB " |
217 | "for software IO TLB\n", (PAGE_SIZE << order) >> 20); | |
218 | io_tlb_nslabs = SLABS_PER_PAGE << order; | |
563aaf06 | 219 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
0b9afede | 220 | } |
563aaf06 JB |
221 | io_tlb_end = io_tlb_start + bytes; |
222 | memset(io_tlb_start, 0, bytes); | |
0b9afede AW |
223 | |
224 | /* | |
225 | * Allocate and initialize the free list array. This array is used | |
226 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
227 | * between io_tlb_start and io_tlb_end. | |
228 | */ | |
229 | io_tlb_list = (unsigned int *)__get_free_pages(GFP_KERNEL, | |
230 | get_order(io_tlb_nslabs * sizeof(int))); | |
231 | if (!io_tlb_list) | |
232 | goto cleanup2; | |
233 | ||
234 | for (i = 0; i < io_tlb_nslabs; i++) | |
235 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); | |
236 | io_tlb_index = 0; | |
237 | ||
25667d67 TL |
238 | io_tlb_orig_addr = (unsigned char **)__get_free_pages(GFP_KERNEL, |
239 | get_order(io_tlb_nslabs * sizeof(char *))); | |
0b9afede AW |
240 | if (!io_tlb_orig_addr) |
241 | goto cleanup3; | |
242 | ||
25667d67 | 243 | memset(io_tlb_orig_addr, 0, io_tlb_nslabs * sizeof(char *)); |
0b9afede AW |
244 | |
245 | /* | |
246 | * Get the overflow emergency buffer | |
247 | */ | |
248 | io_tlb_overflow_buffer = (void *)__get_free_pages(GFP_DMA, | |
249 | get_order(io_tlb_overflow)); | |
250 | if (!io_tlb_overflow_buffer) | |
251 | goto cleanup4; | |
252 | ||
25667d67 TL |
253 | printk(KERN_INFO "Placing %luMB software IO TLB between 0x%lx - " |
254 | "0x%lx\n", bytes >> 20, | |
255 | virt_to_bus(io_tlb_start), virt_to_bus(io_tlb_end)); | |
0b9afede AW |
256 | |
257 | return 0; | |
258 | ||
259 | cleanup4: | |
25667d67 TL |
260 | free_pages((unsigned long)io_tlb_orig_addr, get_order(io_tlb_nslabs * |
261 | sizeof(char *))); | |
0b9afede AW |
262 | io_tlb_orig_addr = NULL; |
263 | cleanup3: | |
25667d67 TL |
264 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * |
265 | sizeof(int))); | |
0b9afede | 266 | io_tlb_list = NULL; |
0b9afede | 267 | cleanup2: |
563aaf06 | 268 | io_tlb_end = NULL; |
0b9afede AW |
269 | free_pages((unsigned long)io_tlb_start, order); |
270 | io_tlb_start = NULL; | |
271 | cleanup1: | |
272 | io_tlb_nslabs = req_nslabs; | |
273 | return -ENOMEM; | |
274 | } | |
275 | ||
be6b0267 | 276 | static int |
1da177e4 LT |
277 | address_needs_mapping(struct device *hwdev, dma_addr_t addr) |
278 | { | |
279 | dma_addr_t mask = 0xffffffff; | |
280 | /* If the device has a mask, use it, otherwise default to 32 bits */ | |
281 | if (hwdev && hwdev->dma_mask) | |
282 | mask = *hwdev->dma_mask; | |
283 | return (addr & ~mask) != 0; | |
284 | } | |
285 | ||
286 | /* | |
287 | * Allocates bounce buffer and returns its kernel virtual address. | |
288 | */ | |
289 | static void * | |
25667d67 | 290 | map_single(struct device *hwdev, char *buffer, size_t size, int dir) |
1da177e4 LT |
291 | { |
292 | unsigned long flags; | |
293 | char *dma_addr; | |
294 | unsigned int nslots, stride, index, wrap; | |
295 | int i; | |
681cc5cd FT |
296 | unsigned long start_dma_addr; |
297 | unsigned long mask; | |
298 | unsigned long offset_slots; | |
299 | unsigned long max_slots; | |
300 | ||
301 | mask = dma_get_seg_boundary(hwdev); | |
302 | start_dma_addr = virt_to_bus(io_tlb_start) & mask; | |
303 | ||
304 | offset_slots = ALIGN(start_dma_addr, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
b15a3891 JB |
305 | max_slots = mask + 1 |
306 | ? ALIGN(mask + 1, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT | |
307 | : 1UL << (BITS_PER_LONG - IO_TLB_SHIFT); | |
1da177e4 LT |
308 | |
309 | /* | |
310 | * For mappings greater than a page, we limit the stride (and | |
311 | * hence alignment) to a page size. | |
312 | */ | |
313 | nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
314 | if (size > PAGE_SIZE) | |
315 | stride = (1 << (PAGE_SHIFT - IO_TLB_SHIFT)); | |
316 | else | |
317 | stride = 1; | |
318 | ||
34814545 | 319 | BUG_ON(!nslots); |
1da177e4 LT |
320 | |
321 | /* | |
322 | * Find suitable number of IO TLB entries size that will fit this | |
323 | * request and allocate a buffer from that IO TLB pool. | |
324 | */ | |
325 | spin_lock_irqsave(&io_tlb_lock, flags); | |
a7133a15 AM |
326 | index = ALIGN(io_tlb_index, stride); |
327 | if (index >= io_tlb_nslabs) | |
328 | index = 0; | |
329 | wrap = index; | |
330 | ||
331 | do { | |
a8522509 FT |
332 | while (iommu_is_span_boundary(index, nslots, offset_slots, |
333 | max_slots)) { | |
b15a3891 JB |
334 | index += stride; |
335 | if (index >= io_tlb_nslabs) | |
336 | index = 0; | |
a7133a15 AM |
337 | if (index == wrap) |
338 | goto not_found; | |
339 | } | |
340 | ||
341 | /* | |
342 | * If we find a slot that indicates we have 'nslots' number of | |
343 | * contiguous buffers, we allocate the buffers from that slot | |
344 | * and mark the entries as '0' indicating unavailable. | |
345 | */ | |
346 | if (io_tlb_list[index] >= nslots) { | |
347 | int count = 0; | |
348 | ||
349 | for (i = index; i < (int) (index + nslots); i++) | |
350 | io_tlb_list[i] = 0; | |
351 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE - 1) && io_tlb_list[i]; i--) | |
352 | io_tlb_list[i] = ++count; | |
353 | dma_addr = io_tlb_start + (index << IO_TLB_SHIFT); | |
1da177e4 | 354 | |
a7133a15 AM |
355 | /* |
356 | * Update the indices to avoid searching in the next | |
357 | * round. | |
358 | */ | |
359 | io_tlb_index = ((index + nslots) < io_tlb_nslabs | |
360 | ? (index + nslots) : 0); | |
361 | ||
362 | goto found; | |
363 | } | |
364 | index += stride; | |
365 | if (index >= io_tlb_nslabs) | |
366 | index = 0; | |
367 | } while (index != wrap); | |
368 | ||
369 | not_found: | |
370 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
371 | return NULL; | |
372 | found: | |
1da177e4 LT |
373 | spin_unlock_irqrestore(&io_tlb_lock, flags); |
374 | ||
375 | /* | |
376 | * Save away the mapping from the original address to the DMA address. | |
377 | * This is needed when we sync the memory. Then we sync the buffer if | |
378 | * needed. | |
379 | */ | |
df336d1c KF |
380 | for (i = 0; i < nslots; i++) |
381 | io_tlb_orig_addr[index+i] = buffer + (i << IO_TLB_SHIFT); | |
1da177e4 | 382 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL) |
25667d67 | 383 | memcpy(dma_addr, buffer, size); |
1da177e4 LT |
384 | |
385 | return dma_addr; | |
386 | } | |
387 | ||
388 | /* | |
389 | * dma_addr is the kernel virtual address of the bounce buffer to unmap. | |
390 | */ | |
391 | static void | |
392 | unmap_single(struct device *hwdev, char *dma_addr, size_t size, int dir) | |
393 | { | |
394 | unsigned long flags; | |
395 | int i, count, nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
396 | int index = (dma_addr - io_tlb_start) >> IO_TLB_SHIFT; | |
25667d67 | 397 | char *buffer = io_tlb_orig_addr[index]; |
1da177e4 LT |
398 | |
399 | /* | |
400 | * First, sync the memory before unmapping the entry | |
401 | */ | |
25667d67 | 402 | if (buffer && ((dir == DMA_FROM_DEVICE) || (dir == DMA_BIDIRECTIONAL))) |
1da177e4 LT |
403 | /* |
404 | * bounce... copy the data back into the original buffer * and | |
405 | * delete the bounce buffer. | |
406 | */ | |
25667d67 | 407 | memcpy(buffer, dma_addr, size); |
1da177e4 LT |
408 | |
409 | /* | |
410 | * Return the buffer to the free list by setting the corresponding | |
411 | * entries to indicate the number of contigous entries available. | |
412 | * While returning the entries to the free list, we merge the entries | |
413 | * with slots below and above the pool being returned. | |
414 | */ | |
415 | spin_lock_irqsave(&io_tlb_lock, flags); | |
416 | { | |
417 | count = ((index + nslots) < ALIGN(index + 1, IO_TLB_SEGSIZE) ? | |
418 | io_tlb_list[index + nslots] : 0); | |
419 | /* | |
420 | * Step 1: return the slots to the free list, merging the | |
421 | * slots with superceeding slots | |
422 | */ | |
423 | for (i = index + nslots - 1; i >= index; i--) | |
424 | io_tlb_list[i] = ++count; | |
425 | /* | |
426 | * Step 2: merge the returned slots with the preceding slots, | |
427 | * if available (non zero) | |
428 | */ | |
429 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE -1) && io_tlb_list[i]; i--) | |
430 | io_tlb_list[i] = ++count; | |
431 | } | |
432 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
433 | } | |
434 | ||
435 | static void | |
de69e0f0 JL |
436 | sync_single(struct device *hwdev, char *dma_addr, size_t size, |
437 | int dir, int target) | |
1da177e4 LT |
438 | { |
439 | int index = (dma_addr - io_tlb_start) >> IO_TLB_SHIFT; | |
25667d67 | 440 | char *buffer = io_tlb_orig_addr[index]; |
1da177e4 | 441 | |
df336d1c KF |
442 | buffer += ((unsigned long)dma_addr & ((1 << IO_TLB_SHIFT) - 1)); |
443 | ||
de69e0f0 JL |
444 | switch (target) { |
445 | case SYNC_FOR_CPU: | |
446 | if (likely(dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
25667d67 | 447 | memcpy(buffer, dma_addr, size); |
34814545 ES |
448 | else |
449 | BUG_ON(dir != DMA_TO_DEVICE); | |
de69e0f0 JL |
450 | break; |
451 | case SYNC_FOR_DEVICE: | |
452 | if (likely(dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
25667d67 | 453 | memcpy(dma_addr, buffer, size); |
34814545 ES |
454 | else |
455 | BUG_ON(dir != DMA_FROM_DEVICE); | |
de69e0f0 JL |
456 | break; |
457 | default: | |
1da177e4 | 458 | BUG(); |
de69e0f0 | 459 | } |
1da177e4 LT |
460 | } |
461 | ||
462 | void * | |
463 | swiotlb_alloc_coherent(struct device *hwdev, size_t size, | |
06a54497 | 464 | dma_addr_t *dma_handle, gfp_t flags) |
1da177e4 | 465 | { |
563aaf06 | 466 | dma_addr_t dev_addr; |
1da177e4 LT |
467 | void *ret; |
468 | int order = get_order(size); | |
469 | ||
470 | /* | |
471 | * XXX fix me: the DMA API should pass us an explicit DMA mask | |
472 | * instead, or use ZONE_DMA32 (ia64 overloads ZONE_DMA to be a ~32 | |
473 | * bit range instead of a 16MB one). | |
474 | */ | |
475 | flags |= GFP_DMA; | |
476 | ||
25667d67 | 477 | ret = (void *)__get_free_pages(flags, order); |
93fbff63 | 478 | if (ret && address_needs_mapping(hwdev, virt_to_bus(ret))) { |
1da177e4 LT |
479 | /* |
480 | * The allocated memory isn't reachable by the device. | |
481 | * Fall back on swiotlb_map_single(). | |
482 | */ | |
483 | free_pages((unsigned long) ret, order); | |
484 | ret = NULL; | |
485 | } | |
486 | if (!ret) { | |
487 | /* | |
488 | * We are either out of memory or the device can't DMA | |
489 | * to GFP_DMA memory; fall back on | |
490 | * swiotlb_map_single(), which will grab memory from | |
491 | * the lowest available address range. | |
492 | */ | |
493 | dma_addr_t handle; | |
494 | handle = swiotlb_map_single(NULL, NULL, size, DMA_FROM_DEVICE); | |
17a941d8 | 495 | if (swiotlb_dma_mapping_error(handle)) |
1da177e4 LT |
496 | return NULL; |
497 | ||
93fbff63 | 498 | ret = bus_to_virt(handle); |
1da177e4 LT |
499 | } |
500 | ||
501 | memset(ret, 0, size); | |
93fbff63 | 502 | dev_addr = virt_to_bus(ret); |
1da177e4 LT |
503 | |
504 | /* Confirm address can be DMA'd by device */ | |
505 | if (address_needs_mapping(hwdev, dev_addr)) { | |
563aaf06 JB |
506 | printk("hwdev DMA mask = 0x%016Lx, dev_addr = 0x%016Lx\n", |
507 | (unsigned long long)*hwdev->dma_mask, | |
508 | (unsigned long long)dev_addr); | |
1da177e4 LT |
509 | panic("swiotlb_alloc_coherent: allocated memory is out of " |
510 | "range for device"); | |
511 | } | |
512 | *dma_handle = dev_addr; | |
513 | return ret; | |
514 | } | |
515 | ||
516 | void | |
517 | swiotlb_free_coherent(struct device *hwdev, size_t size, void *vaddr, | |
518 | dma_addr_t dma_handle) | |
519 | { | |
aa24886e | 520 | WARN_ON(irqs_disabled()); |
1da177e4 LT |
521 | if (!(vaddr >= (void *)io_tlb_start |
522 | && vaddr < (void *)io_tlb_end)) | |
523 | free_pages((unsigned long) vaddr, get_order(size)); | |
524 | else | |
525 | /* DMA_TO_DEVICE to avoid memcpy in unmap_single */ | |
526 | swiotlb_unmap_single (hwdev, dma_handle, size, DMA_TO_DEVICE); | |
527 | } | |
528 | ||
529 | static void | |
530 | swiotlb_full(struct device *dev, size_t size, int dir, int do_panic) | |
531 | { | |
532 | /* | |
533 | * Ran out of IOMMU space for this operation. This is very bad. | |
534 | * Unfortunately the drivers cannot handle this operation properly. | |
17e5ad6c | 535 | * unless they check for dma_mapping_error (most don't) |
1da177e4 LT |
536 | * When the mapping is small enough return a static buffer to limit |
537 | * the damage, or panic when the transfer is too big. | |
538 | */ | |
563aaf06 | 539 | printk(KERN_ERR "DMA: Out of SW-IOMMU space for %zu bytes at " |
1da177e4 LT |
540 | "device %s\n", size, dev ? dev->bus_id : "?"); |
541 | ||
542 | if (size > io_tlb_overflow && do_panic) { | |
17e5ad6c TL |
543 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) |
544 | panic("DMA: Memory would be corrupted\n"); | |
545 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL) | |
546 | panic("DMA: Random memory would be DMAed\n"); | |
1da177e4 LT |
547 | } |
548 | } | |
549 | ||
550 | /* | |
551 | * Map a single buffer of the indicated size for DMA in streaming mode. The | |
17e5ad6c | 552 | * physical address to use is returned. |
1da177e4 LT |
553 | * |
554 | * Once the device is given the dma address, the device owns this memory until | |
555 | * either swiotlb_unmap_single or swiotlb_dma_sync_single is performed. | |
556 | */ | |
557 | dma_addr_t | |
309df0c5 AK |
558 | swiotlb_map_single_attrs(struct device *hwdev, void *ptr, size_t size, |
559 | int dir, struct dma_attrs *attrs) | |
1da177e4 | 560 | { |
563aaf06 | 561 | dma_addr_t dev_addr = virt_to_bus(ptr); |
1da177e4 LT |
562 | void *map; |
563 | ||
34814545 | 564 | BUG_ON(dir == DMA_NONE); |
1da177e4 LT |
565 | /* |
566 | * If the pointer passed in happens to be in the device's DMA window, | |
567 | * we can safely return the device addr and not worry about bounce | |
568 | * buffering it. | |
569 | */ | |
25667d67 | 570 | if (!address_needs_mapping(hwdev, dev_addr) && !swiotlb_force) |
1da177e4 LT |
571 | return dev_addr; |
572 | ||
573 | /* | |
574 | * Oh well, have to allocate and map a bounce buffer. | |
575 | */ | |
25667d67 | 576 | map = map_single(hwdev, ptr, size, dir); |
1da177e4 LT |
577 | if (!map) { |
578 | swiotlb_full(hwdev, size, dir, 1); | |
579 | map = io_tlb_overflow_buffer; | |
580 | } | |
581 | ||
93fbff63 | 582 | dev_addr = virt_to_bus(map); |
1da177e4 LT |
583 | |
584 | /* | |
585 | * Ensure that the address returned is DMA'ble | |
586 | */ | |
587 | if (address_needs_mapping(hwdev, dev_addr)) | |
588 | panic("map_single: bounce buffer is not DMA'ble"); | |
589 | ||
590 | return dev_addr; | |
591 | } | |
309df0c5 AK |
592 | EXPORT_SYMBOL(swiotlb_map_single_attrs); |
593 | ||
594 | dma_addr_t | |
595 | swiotlb_map_single(struct device *hwdev, void *ptr, size_t size, int dir) | |
596 | { | |
597 | return swiotlb_map_single_attrs(hwdev, ptr, size, dir, NULL); | |
598 | } | |
1da177e4 | 599 | |
1da177e4 LT |
600 | /* |
601 | * Unmap a single streaming mode DMA translation. The dma_addr and size must | |
602 | * match what was provided for in a previous swiotlb_map_single call. All | |
603 | * other usages are undefined. | |
604 | * | |
605 | * After this call, reads by the cpu to the buffer are guaranteed to see | |
606 | * whatever the device wrote there. | |
607 | */ | |
608 | void | |
309df0c5 AK |
609 | swiotlb_unmap_single_attrs(struct device *hwdev, dma_addr_t dev_addr, |
610 | size_t size, int dir, struct dma_attrs *attrs) | |
1da177e4 | 611 | { |
93fbff63 | 612 | char *dma_addr = bus_to_virt(dev_addr); |
1da177e4 | 613 | |
34814545 | 614 | BUG_ON(dir == DMA_NONE); |
1da177e4 LT |
615 | if (dma_addr >= io_tlb_start && dma_addr < io_tlb_end) |
616 | unmap_single(hwdev, dma_addr, size, dir); | |
617 | else if (dir == DMA_FROM_DEVICE) | |
cde14bbf | 618 | dma_mark_clean(dma_addr, size); |
1da177e4 | 619 | } |
309df0c5 | 620 | EXPORT_SYMBOL(swiotlb_unmap_single_attrs); |
1da177e4 | 621 | |
309df0c5 AK |
622 | void |
623 | swiotlb_unmap_single(struct device *hwdev, dma_addr_t dev_addr, size_t size, | |
624 | int dir) | |
625 | { | |
626 | return swiotlb_unmap_single_attrs(hwdev, dev_addr, size, dir, NULL); | |
627 | } | |
1da177e4 LT |
628 | /* |
629 | * Make physical memory consistent for a single streaming mode DMA translation | |
630 | * after a transfer. | |
631 | * | |
632 | * If you perform a swiotlb_map_single() but wish to interrogate the buffer | |
17e5ad6c TL |
633 | * using the cpu, yet do not wish to teardown the dma mapping, you must |
634 | * call this function before doing so. At the next point you give the dma | |
1da177e4 LT |
635 | * address back to the card, you must first perform a |
636 | * swiotlb_dma_sync_for_device, and then the device again owns the buffer | |
637 | */ | |
be6b0267 | 638 | static void |
8270f3f1 | 639 | swiotlb_sync_single(struct device *hwdev, dma_addr_t dev_addr, |
de69e0f0 | 640 | size_t size, int dir, int target) |
1da177e4 | 641 | { |
93fbff63 | 642 | char *dma_addr = bus_to_virt(dev_addr); |
1da177e4 | 643 | |
34814545 | 644 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 645 | if (dma_addr >= io_tlb_start && dma_addr < io_tlb_end) |
de69e0f0 | 646 | sync_single(hwdev, dma_addr, size, dir, target); |
1da177e4 | 647 | else if (dir == DMA_FROM_DEVICE) |
cde14bbf | 648 | dma_mark_clean(dma_addr, size); |
1da177e4 LT |
649 | } |
650 | ||
8270f3f1 JL |
651 | void |
652 | swiotlb_sync_single_for_cpu(struct device *hwdev, dma_addr_t dev_addr, | |
653 | size_t size, int dir) | |
654 | { | |
de69e0f0 | 655 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_CPU); |
8270f3f1 JL |
656 | } |
657 | ||
1da177e4 LT |
658 | void |
659 | swiotlb_sync_single_for_device(struct device *hwdev, dma_addr_t dev_addr, | |
660 | size_t size, int dir) | |
661 | { | |
de69e0f0 | 662 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_DEVICE); |
1da177e4 LT |
663 | } |
664 | ||
878a97cf JL |
665 | /* |
666 | * Same as above, but for a sub-range of the mapping. | |
667 | */ | |
be6b0267 | 668 | static void |
878a97cf | 669 | swiotlb_sync_single_range(struct device *hwdev, dma_addr_t dev_addr, |
de69e0f0 JL |
670 | unsigned long offset, size_t size, |
671 | int dir, int target) | |
878a97cf | 672 | { |
93fbff63 | 673 | char *dma_addr = bus_to_virt(dev_addr) + offset; |
878a97cf | 674 | |
34814545 | 675 | BUG_ON(dir == DMA_NONE); |
878a97cf | 676 | if (dma_addr >= io_tlb_start && dma_addr < io_tlb_end) |
de69e0f0 | 677 | sync_single(hwdev, dma_addr, size, dir, target); |
878a97cf | 678 | else if (dir == DMA_FROM_DEVICE) |
cde14bbf | 679 | dma_mark_clean(dma_addr, size); |
878a97cf JL |
680 | } |
681 | ||
682 | void | |
683 | swiotlb_sync_single_range_for_cpu(struct device *hwdev, dma_addr_t dev_addr, | |
684 | unsigned long offset, size_t size, int dir) | |
685 | { | |
de69e0f0 JL |
686 | swiotlb_sync_single_range(hwdev, dev_addr, offset, size, dir, |
687 | SYNC_FOR_CPU); | |
878a97cf JL |
688 | } |
689 | ||
690 | void | |
691 | swiotlb_sync_single_range_for_device(struct device *hwdev, dma_addr_t dev_addr, | |
692 | unsigned long offset, size_t size, int dir) | |
693 | { | |
de69e0f0 JL |
694 | swiotlb_sync_single_range(hwdev, dev_addr, offset, size, dir, |
695 | SYNC_FOR_DEVICE); | |
878a97cf JL |
696 | } |
697 | ||
309df0c5 AK |
698 | void swiotlb_unmap_sg_attrs(struct device *, struct scatterlist *, int, int, |
699 | struct dma_attrs *); | |
1da177e4 LT |
700 | /* |
701 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
702 | * This is the scatter-gather version of the above swiotlb_map_single | |
703 | * interface. Here the scatter gather list elements are each tagged with the | |
704 | * appropriate dma address and length. They are obtained via | |
705 | * sg_dma_{address,length}(SG). | |
706 | * | |
707 | * NOTE: An implementation may be able to use a smaller number of | |
708 | * DMA address/length pairs than there are SG table elements. | |
709 | * (for example via virtual mapping capabilities) | |
710 | * The routine returns the number of addr/length pairs actually | |
711 | * used, at most nents. | |
712 | * | |
713 | * Device ownership issues as mentioned above for swiotlb_map_single are the | |
714 | * same here. | |
715 | */ | |
716 | int | |
309df0c5 AK |
717 | swiotlb_map_sg_attrs(struct device *hwdev, struct scatterlist *sgl, int nelems, |
718 | int dir, struct dma_attrs *attrs) | |
1da177e4 | 719 | { |
dbfd49fe | 720 | struct scatterlist *sg; |
25667d67 | 721 | void *addr; |
563aaf06 | 722 | dma_addr_t dev_addr; |
1da177e4 LT |
723 | int i; |
724 | ||
34814545 | 725 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 726 | |
dbfd49fe | 727 | for_each_sg(sgl, sg, nelems, i) { |
25667d67 TL |
728 | addr = SG_ENT_VIRT_ADDRESS(sg); |
729 | dev_addr = virt_to_bus(addr); | |
730 | if (swiotlb_force || address_needs_mapping(hwdev, dev_addr)) { | |
731 | void *map = map_single(hwdev, addr, sg->length, dir); | |
7e870233 | 732 | if (!map) { |
1da177e4 LT |
733 | /* Don't panic here, we expect map_sg users |
734 | to do proper error handling. */ | |
735 | swiotlb_full(hwdev, sg->length, dir, 0); | |
309df0c5 AK |
736 | swiotlb_unmap_sg_attrs(hwdev, sgl, i, dir, |
737 | attrs); | |
dbfd49fe | 738 | sgl[0].dma_length = 0; |
1da177e4 LT |
739 | return 0; |
740 | } | |
cde14bbf | 741 | sg->dma_address = virt_to_bus(map); |
1da177e4 LT |
742 | } else |
743 | sg->dma_address = dev_addr; | |
744 | sg->dma_length = sg->length; | |
745 | } | |
746 | return nelems; | |
747 | } | |
309df0c5 AK |
748 | EXPORT_SYMBOL(swiotlb_map_sg_attrs); |
749 | ||
750 | int | |
751 | swiotlb_map_sg(struct device *hwdev, struct scatterlist *sgl, int nelems, | |
752 | int dir) | |
753 | { | |
754 | return swiotlb_map_sg_attrs(hwdev, sgl, nelems, dir, NULL); | |
755 | } | |
1da177e4 LT |
756 | |
757 | /* | |
758 | * Unmap a set of streaming mode DMA translations. Again, cpu read rules | |
759 | * concerning calls here are the same as for swiotlb_unmap_single() above. | |
760 | */ | |
761 | void | |
309df0c5 AK |
762 | swiotlb_unmap_sg_attrs(struct device *hwdev, struct scatterlist *sgl, |
763 | int nelems, int dir, struct dma_attrs *attrs) | |
1da177e4 | 764 | { |
dbfd49fe | 765 | struct scatterlist *sg; |
1da177e4 LT |
766 | int i; |
767 | ||
34814545 | 768 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 769 | |
dbfd49fe | 770 | for_each_sg(sgl, sg, nelems, i) { |
1da177e4 | 771 | if (sg->dma_address != SG_ENT_PHYS_ADDRESS(sg)) |
93fbff63 JB |
772 | unmap_single(hwdev, bus_to_virt(sg->dma_address), |
773 | sg->dma_length, dir); | |
1da177e4 | 774 | else if (dir == DMA_FROM_DEVICE) |
cde14bbf | 775 | dma_mark_clean(SG_ENT_VIRT_ADDRESS(sg), sg->dma_length); |
dbfd49fe | 776 | } |
1da177e4 | 777 | } |
309df0c5 AK |
778 | EXPORT_SYMBOL(swiotlb_unmap_sg_attrs); |
779 | ||
780 | void | |
781 | swiotlb_unmap_sg(struct device *hwdev, struct scatterlist *sgl, int nelems, | |
782 | int dir) | |
783 | { | |
784 | return swiotlb_unmap_sg_attrs(hwdev, sgl, nelems, dir, NULL); | |
785 | } | |
1da177e4 LT |
786 | |
787 | /* | |
788 | * Make physical memory consistent for a set of streaming mode DMA translations | |
789 | * after a transfer. | |
790 | * | |
791 | * The same as swiotlb_sync_single_* but for a scatter-gather list, same rules | |
792 | * and usage. | |
793 | */ | |
be6b0267 | 794 | static void |
dbfd49fe | 795 | swiotlb_sync_sg(struct device *hwdev, struct scatterlist *sgl, |
de69e0f0 | 796 | int nelems, int dir, int target) |
1da177e4 | 797 | { |
dbfd49fe | 798 | struct scatterlist *sg; |
1da177e4 LT |
799 | int i; |
800 | ||
34814545 | 801 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 802 | |
dbfd49fe | 803 | for_each_sg(sgl, sg, nelems, i) { |
1da177e4 | 804 | if (sg->dma_address != SG_ENT_PHYS_ADDRESS(sg)) |
93fbff63 | 805 | sync_single(hwdev, bus_to_virt(sg->dma_address), |
de69e0f0 | 806 | sg->dma_length, dir, target); |
cde14bbf JB |
807 | else if (dir == DMA_FROM_DEVICE) |
808 | dma_mark_clean(SG_ENT_VIRT_ADDRESS(sg), sg->dma_length); | |
dbfd49fe | 809 | } |
1da177e4 LT |
810 | } |
811 | ||
8270f3f1 JL |
812 | void |
813 | swiotlb_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg, | |
814 | int nelems, int dir) | |
815 | { | |
de69e0f0 | 816 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_CPU); |
8270f3f1 JL |
817 | } |
818 | ||
1da177e4 LT |
819 | void |
820 | swiotlb_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg, | |
821 | int nelems, int dir) | |
822 | { | |
de69e0f0 | 823 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_DEVICE); |
1da177e4 LT |
824 | } |
825 | ||
826 | int | |
827 | swiotlb_dma_mapping_error(dma_addr_t dma_addr) | |
828 | { | |
93fbff63 | 829 | return (dma_addr == virt_to_bus(io_tlb_overflow_buffer)); |
1da177e4 LT |
830 | } |
831 | ||
832 | /* | |
17e5ad6c | 833 | * Return whether the given device DMA address mask can be supported |
1da177e4 | 834 | * properly. For example, if your device can only drive the low 24-bits |
17e5ad6c | 835 | * during bus mastering, then you would pass 0x00ffffff as the mask to |
1da177e4 LT |
836 | * this function. |
837 | */ | |
838 | int | |
563aaf06 | 839 | swiotlb_dma_supported(struct device *hwdev, u64 mask) |
1da177e4 | 840 | { |
25667d67 | 841 | return virt_to_bus(io_tlb_end - 1) <= mask; |
1da177e4 LT |
842 | } |
843 | ||
1da177e4 LT |
844 | EXPORT_SYMBOL(swiotlb_map_single); |
845 | EXPORT_SYMBOL(swiotlb_unmap_single); | |
846 | EXPORT_SYMBOL(swiotlb_map_sg); | |
847 | EXPORT_SYMBOL(swiotlb_unmap_sg); | |
848 | EXPORT_SYMBOL(swiotlb_sync_single_for_cpu); | |
849 | EXPORT_SYMBOL(swiotlb_sync_single_for_device); | |
878a97cf JL |
850 | EXPORT_SYMBOL_GPL(swiotlb_sync_single_range_for_cpu); |
851 | EXPORT_SYMBOL_GPL(swiotlb_sync_single_range_for_device); | |
1da177e4 LT |
852 | EXPORT_SYMBOL(swiotlb_sync_sg_for_cpu); |
853 | EXPORT_SYMBOL(swiotlb_sync_sg_for_device); | |
854 | EXPORT_SYMBOL(swiotlb_dma_mapping_error); | |
25667d67 TL |
855 | EXPORT_SYMBOL(swiotlb_alloc_coherent); |
856 | EXPORT_SYMBOL(swiotlb_free_coherent); | |
1da177e4 | 857 | EXPORT_SYMBOL(swiotlb_dma_supported); |