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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Dynamic DMA mapping support. | |
3 | * | |
563aaf06 | 4 | * This implementation is a fallback for platforms that do not support |
1da177e4 LT |
5 | * I/O TLBs (aka DMA address translation hardware). |
6 | * Copyright (C) 2000 Asit Mallick <Asit.K.Mallick@intel.com> | |
7 | * Copyright (C) 2000 Goutham Rao <goutham.rao@intel.com> | |
8 | * Copyright (C) 2000, 2003 Hewlett-Packard Co | |
9 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
10 | * | |
11 | * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API. | |
12 | * 00/12/13 davidm Rename to swiotlb.c and add mark_clean() to avoid | |
13 | * unnecessary i-cache flushing. | |
569c8bf5 JL |
14 | * 04/07/.. ak Better overflow handling. Assorted fixes. |
15 | * 05/09/10 linville Add support for syncing ranges, support syncing for | |
16 | * DMA_BIDIRECTIONAL mappings, miscellaneous cleanup. | |
fb05a379 | 17 | * 08/12/11 beckyb Add highmem support |
1da177e4 LT |
18 | */ |
19 | ||
20 | #include <linux/cache.h> | |
ea8c64ac | 21 | #include <linux/dma-direct.h> |
1da177e4 | 22 | #include <linux/mm.h> |
8bc3bcc9 | 23 | #include <linux/export.h> |
1da177e4 LT |
24 | #include <linux/spinlock.h> |
25 | #include <linux/string.h> | |
0016fdee | 26 | #include <linux/swiotlb.h> |
fb05a379 | 27 | #include <linux/pfn.h> |
1da177e4 LT |
28 | #include <linux/types.h> |
29 | #include <linux/ctype.h> | |
ef9b1893 | 30 | #include <linux/highmem.h> |
5a0e3ad6 | 31 | #include <linux/gfp.h> |
84be456f | 32 | #include <linux/scatterlist.h> |
c7753208 | 33 | #include <linux/mem_encrypt.h> |
e7de6c7c | 34 | #include <linux/set_memory.h> |
1da177e4 LT |
35 | |
36 | #include <asm/io.h> | |
1da177e4 LT |
37 | #include <asm/dma.h> |
38 | ||
39 | #include <linux/init.h> | |
40 | #include <linux/bootmem.h> | |
a8522509 | 41 | #include <linux/iommu-helper.h> |
1da177e4 | 42 | |
ce5be5a1 | 43 | #define CREATE_TRACE_POINTS |
2b2b614d ZK |
44 | #include <trace/events/swiotlb.h> |
45 | ||
1da177e4 LT |
46 | #define OFFSET(val,align) ((unsigned long) \ |
47 | ( (val) & ( (align) - 1))) | |
48 | ||
0b9afede AW |
49 | #define SLABS_PER_PAGE (1 << (PAGE_SHIFT - IO_TLB_SHIFT)) |
50 | ||
51 | /* | |
52 | * Minimum IO TLB size to bother booting with. Systems with mainly | |
53 | * 64bit capable cards will only lightly use the swiotlb. If we can't | |
54 | * allocate a contiguous 1MB, we're probably in trouble anyway. | |
55 | */ | |
56 | #define IO_TLB_MIN_SLABS ((1<<20) >> IO_TLB_SHIFT) | |
57 | ||
ae7871be | 58 | enum swiotlb_force swiotlb_force; |
1da177e4 LT |
59 | |
60 | /* | |
bfc5501f KRW |
61 | * Used to do a quick range check in swiotlb_tbl_unmap_single and |
62 | * swiotlb_tbl_sync_single_*, to see if the memory was in fact allocated by this | |
1da177e4 LT |
63 | * API. |
64 | */ | |
ff7204a7 | 65 | static phys_addr_t io_tlb_start, io_tlb_end; |
1da177e4 LT |
66 | |
67 | /* | |
b595076a | 68 | * The number of IO TLB blocks (in groups of 64) between io_tlb_start and |
1da177e4 LT |
69 | * io_tlb_end. This is command line adjustable via setup_io_tlb_npages. |
70 | */ | |
71 | static unsigned long io_tlb_nslabs; | |
72 | ||
73 | /* | |
74 | * When the IOMMU overflows we return a fallback buffer. This sets the size. | |
75 | */ | |
76 | static unsigned long io_tlb_overflow = 32*1024; | |
77 | ||
ee3f6ba8 | 78 | static phys_addr_t io_tlb_overflow_buffer; |
1da177e4 LT |
79 | |
80 | /* | |
81 | * This is a free list describing the number of free entries available from | |
82 | * each index | |
83 | */ | |
84 | static unsigned int *io_tlb_list; | |
85 | static unsigned int io_tlb_index; | |
86 | ||
7453c549 KRW |
87 | /* |
88 | * Max segment that we can provide which (if pages are contingous) will | |
89 | * not be bounced (unless SWIOTLB_FORCE is set). | |
90 | */ | |
91 | unsigned int max_segment; | |
92 | ||
1da177e4 LT |
93 | /* |
94 | * We need to save away the original address corresponding to a mapped entry | |
95 | * for the sync operations. | |
96 | */ | |
8e0629c1 | 97 | #define INVALID_PHYS_ADDR (~(phys_addr_t)0) |
bc40ac66 | 98 | static phys_addr_t *io_tlb_orig_addr; |
1da177e4 LT |
99 | |
100 | /* | |
101 | * Protect the above data structures in the map and unmap calls | |
102 | */ | |
103 | static DEFINE_SPINLOCK(io_tlb_lock); | |
104 | ||
5740afdb FT |
105 | static int late_alloc; |
106 | ||
1da177e4 LT |
107 | static int __init |
108 | setup_io_tlb_npages(char *str) | |
109 | { | |
110 | if (isdigit(*str)) { | |
e8579e72 | 111 | io_tlb_nslabs = simple_strtoul(str, &str, 0); |
1da177e4 LT |
112 | /* avoid tail segment of size < IO_TLB_SEGSIZE */ |
113 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
114 | } | |
115 | if (*str == ',') | |
116 | ++str; | |
fff5d992 | 117 | if (!strcmp(str, "force")) { |
ae7871be | 118 | swiotlb_force = SWIOTLB_FORCE; |
fff5d992 GU |
119 | } else if (!strcmp(str, "noforce")) { |
120 | swiotlb_force = SWIOTLB_NO_FORCE; | |
121 | io_tlb_nslabs = 1; | |
122 | } | |
b18485e7 | 123 | |
c729de8f | 124 | return 0; |
1da177e4 | 125 | } |
c729de8f | 126 | early_param("swiotlb", setup_io_tlb_npages); |
1da177e4 LT |
127 | /* make io_tlb_overflow tunable too? */ |
128 | ||
f21ffe9f | 129 | unsigned long swiotlb_nr_tbl(void) |
5f98ecdb FT |
130 | { |
131 | return io_tlb_nslabs; | |
132 | } | |
f21ffe9f | 133 | EXPORT_SYMBOL_GPL(swiotlb_nr_tbl); |
c729de8f | 134 | |
7453c549 KRW |
135 | unsigned int swiotlb_max_segment(void) |
136 | { | |
137 | return max_segment; | |
138 | } | |
139 | EXPORT_SYMBOL_GPL(swiotlb_max_segment); | |
140 | ||
141 | void swiotlb_set_max_segment(unsigned int val) | |
142 | { | |
143 | if (swiotlb_force == SWIOTLB_FORCE) | |
144 | max_segment = 1; | |
145 | else | |
146 | max_segment = rounddown(val, PAGE_SIZE); | |
147 | } | |
148 | ||
c729de8f YL |
149 | /* default to 64MB */ |
150 | #define IO_TLB_DEFAULT_SIZE (64UL<<20) | |
151 | unsigned long swiotlb_size_or_default(void) | |
152 | { | |
153 | unsigned long size; | |
154 | ||
155 | size = io_tlb_nslabs << IO_TLB_SHIFT; | |
156 | ||
157 | return size ? size : (IO_TLB_DEFAULT_SIZE); | |
158 | } | |
159 | ||
ac2cbab2 YL |
160 | static bool no_iotlb_memory; |
161 | ||
ad32e8cb | 162 | void swiotlb_print_info(void) |
2e5b2b86 | 163 | { |
ad32e8cb | 164 | unsigned long bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
ff7204a7 | 165 | unsigned char *vstart, *vend; |
2e5b2b86 | 166 | |
ac2cbab2 YL |
167 | if (no_iotlb_memory) { |
168 | pr_warn("software IO TLB: No low mem\n"); | |
169 | return; | |
170 | } | |
171 | ||
ff7204a7 | 172 | vstart = phys_to_virt(io_tlb_start); |
c40dba06 | 173 | vend = phys_to_virt(io_tlb_end); |
2e5b2b86 | 174 | |
3af684c7 | 175 | printk(KERN_INFO "software IO TLB [mem %#010llx-%#010llx] (%luMB) mapped at [%p-%p]\n", |
ff7204a7 | 176 | (unsigned long long)io_tlb_start, |
c40dba06 | 177 | (unsigned long long)io_tlb_end, |
ff7204a7 | 178 | bytes >> 20, vstart, vend - 1); |
2e5b2b86 IC |
179 | } |
180 | ||
c7753208 TL |
181 | /* |
182 | * Early SWIOTLB allocation may be too early to allow an architecture to | |
183 | * perform the desired operations. This function allows the architecture to | |
184 | * call SWIOTLB when the operations are possible. It needs to be called | |
185 | * before the SWIOTLB memory is used. | |
186 | */ | |
187 | void __init swiotlb_update_mem_attributes(void) | |
188 | { | |
189 | void *vaddr; | |
190 | unsigned long bytes; | |
191 | ||
192 | if (no_iotlb_memory || late_alloc) | |
193 | return; | |
194 | ||
195 | vaddr = phys_to_virt(io_tlb_start); | |
196 | bytes = PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT); | |
e7de6c7c | 197 | set_memory_decrypted((unsigned long)vaddr, bytes >> PAGE_SHIFT); |
c7753208 TL |
198 | memset(vaddr, 0, bytes); |
199 | ||
200 | vaddr = phys_to_virt(io_tlb_overflow_buffer); | |
201 | bytes = PAGE_ALIGN(io_tlb_overflow); | |
e7de6c7c | 202 | set_memory_decrypted((unsigned long)vaddr, bytes >> PAGE_SHIFT); |
c7753208 TL |
203 | memset(vaddr, 0, bytes); |
204 | } | |
205 | ||
ac2cbab2 | 206 | int __init swiotlb_init_with_tbl(char *tlb, unsigned long nslabs, int verbose) |
1da177e4 | 207 | { |
ee3f6ba8 | 208 | void *v_overflow_buffer; |
563aaf06 | 209 | unsigned long i, bytes; |
1da177e4 | 210 | |
abbceff7 | 211 | bytes = nslabs << IO_TLB_SHIFT; |
1da177e4 | 212 | |
abbceff7 | 213 | io_tlb_nslabs = nslabs; |
ff7204a7 AD |
214 | io_tlb_start = __pa(tlb); |
215 | io_tlb_end = io_tlb_start + bytes; | |
1da177e4 | 216 | |
ee3f6ba8 AD |
217 | /* |
218 | * Get the overflow emergency buffer | |
219 | */ | |
ad6492b8 | 220 | v_overflow_buffer = memblock_virt_alloc_low_nopanic( |
457ff1de SS |
221 | PAGE_ALIGN(io_tlb_overflow), |
222 | PAGE_SIZE); | |
ee3f6ba8 | 223 | if (!v_overflow_buffer) |
ac2cbab2 | 224 | return -ENOMEM; |
ee3f6ba8 AD |
225 | |
226 | io_tlb_overflow_buffer = __pa(v_overflow_buffer); | |
227 | ||
1da177e4 LT |
228 | /* |
229 | * Allocate and initialize the free list array. This array is used | |
230 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
231 | * between io_tlb_start and io_tlb_end. | |
232 | */ | |
457ff1de SS |
233 | io_tlb_list = memblock_virt_alloc( |
234 | PAGE_ALIGN(io_tlb_nslabs * sizeof(int)), | |
235 | PAGE_SIZE); | |
457ff1de SS |
236 | io_tlb_orig_addr = memblock_virt_alloc( |
237 | PAGE_ALIGN(io_tlb_nslabs * sizeof(phys_addr_t)), | |
238 | PAGE_SIZE); | |
8e0629c1 JB |
239 | for (i = 0; i < io_tlb_nslabs; i++) { |
240 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); | |
241 | io_tlb_orig_addr[i] = INVALID_PHYS_ADDR; | |
242 | } | |
243 | io_tlb_index = 0; | |
1da177e4 | 244 | |
ad32e8cb FT |
245 | if (verbose) |
246 | swiotlb_print_info(); | |
ac2cbab2 | 247 | |
7453c549 | 248 | swiotlb_set_max_segment(io_tlb_nslabs << IO_TLB_SHIFT); |
ac2cbab2 | 249 | return 0; |
1da177e4 LT |
250 | } |
251 | ||
abbceff7 FT |
252 | /* |
253 | * Statically reserve bounce buffer space and initialize bounce buffer data | |
254 | * structures for the software IO TLB used to implement the DMA API. | |
255 | */ | |
ac2cbab2 YL |
256 | void __init |
257 | swiotlb_init(int verbose) | |
abbceff7 | 258 | { |
c729de8f | 259 | size_t default_size = IO_TLB_DEFAULT_SIZE; |
ff7204a7 | 260 | unsigned char *vstart; |
abbceff7 FT |
261 | unsigned long bytes; |
262 | ||
263 | if (!io_tlb_nslabs) { | |
264 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); | |
265 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
266 | } | |
267 | ||
268 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; | |
269 | ||
ac2cbab2 | 270 | /* Get IO TLB memory from the low pages */ |
ad6492b8 | 271 | vstart = memblock_virt_alloc_low_nopanic(PAGE_ALIGN(bytes), PAGE_SIZE); |
ac2cbab2 YL |
272 | if (vstart && !swiotlb_init_with_tbl(vstart, io_tlb_nslabs, verbose)) |
273 | return; | |
abbceff7 | 274 | |
ac2cbab2 | 275 | if (io_tlb_start) |
457ff1de SS |
276 | memblock_free_early(io_tlb_start, |
277 | PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT)); | |
ac2cbab2 YL |
278 | pr_warn("Cannot allocate SWIOTLB buffer"); |
279 | no_iotlb_memory = true; | |
1da177e4 LT |
280 | } |
281 | ||
0b9afede AW |
282 | /* |
283 | * Systems with larger DMA zones (those that don't support ISA) can | |
284 | * initialize the swiotlb later using the slab allocator if needed. | |
285 | * This should be just like above, but with some error catching. | |
286 | */ | |
287 | int | |
563aaf06 | 288 | swiotlb_late_init_with_default_size(size_t default_size) |
0b9afede | 289 | { |
74838b75 | 290 | unsigned long bytes, req_nslabs = io_tlb_nslabs; |
ff7204a7 | 291 | unsigned char *vstart = NULL; |
0b9afede | 292 | unsigned int order; |
74838b75 | 293 | int rc = 0; |
0b9afede AW |
294 | |
295 | if (!io_tlb_nslabs) { | |
296 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); | |
297 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
298 | } | |
299 | ||
300 | /* | |
301 | * Get IO TLB memory from the low pages | |
302 | */ | |
563aaf06 | 303 | order = get_order(io_tlb_nslabs << IO_TLB_SHIFT); |
0b9afede | 304 | io_tlb_nslabs = SLABS_PER_PAGE << order; |
563aaf06 | 305 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
0b9afede AW |
306 | |
307 | while ((SLABS_PER_PAGE << order) > IO_TLB_MIN_SLABS) { | |
ff7204a7 AD |
308 | vstart = (void *)__get_free_pages(GFP_DMA | __GFP_NOWARN, |
309 | order); | |
310 | if (vstart) | |
0b9afede AW |
311 | break; |
312 | order--; | |
313 | } | |
314 | ||
ff7204a7 | 315 | if (!vstart) { |
74838b75 KRW |
316 | io_tlb_nslabs = req_nslabs; |
317 | return -ENOMEM; | |
318 | } | |
563aaf06 | 319 | if (order != get_order(bytes)) { |
0b9afede AW |
320 | printk(KERN_WARNING "Warning: only able to allocate %ld MB " |
321 | "for software IO TLB\n", (PAGE_SIZE << order) >> 20); | |
322 | io_tlb_nslabs = SLABS_PER_PAGE << order; | |
323 | } | |
ff7204a7 | 324 | rc = swiotlb_late_init_with_tbl(vstart, io_tlb_nslabs); |
74838b75 | 325 | if (rc) |
ff7204a7 | 326 | free_pages((unsigned long)vstart, order); |
7453c549 | 327 | |
74838b75 KRW |
328 | return rc; |
329 | } | |
330 | ||
331 | int | |
332 | swiotlb_late_init_with_tbl(char *tlb, unsigned long nslabs) | |
333 | { | |
334 | unsigned long i, bytes; | |
ee3f6ba8 | 335 | unsigned char *v_overflow_buffer; |
74838b75 KRW |
336 | |
337 | bytes = nslabs << IO_TLB_SHIFT; | |
338 | ||
339 | io_tlb_nslabs = nslabs; | |
ff7204a7 AD |
340 | io_tlb_start = virt_to_phys(tlb); |
341 | io_tlb_end = io_tlb_start + bytes; | |
74838b75 | 342 | |
e7de6c7c | 343 | set_memory_decrypted((unsigned long)tlb, bytes >> PAGE_SHIFT); |
ff7204a7 | 344 | memset(tlb, 0, bytes); |
0b9afede | 345 | |
ee3f6ba8 AD |
346 | /* |
347 | * Get the overflow emergency buffer | |
348 | */ | |
349 | v_overflow_buffer = (void *)__get_free_pages(GFP_DMA, | |
350 | get_order(io_tlb_overflow)); | |
351 | if (!v_overflow_buffer) | |
352 | goto cleanup2; | |
353 | ||
e7de6c7c CH |
354 | set_memory_decrypted((unsigned long)v_overflow_buffer, |
355 | io_tlb_overflow >> PAGE_SHIFT); | |
c7753208 | 356 | memset(v_overflow_buffer, 0, io_tlb_overflow); |
ee3f6ba8 AD |
357 | io_tlb_overflow_buffer = virt_to_phys(v_overflow_buffer); |
358 | ||
0b9afede AW |
359 | /* |
360 | * Allocate and initialize the free list array. This array is used | |
361 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
362 | * between io_tlb_start and io_tlb_end. | |
363 | */ | |
364 | io_tlb_list = (unsigned int *)__get_free_pages(GFP_KERNEL, | |
365 | get_order(io_tlb_nslabs * sizeof(int))); | |
366 | if (!io_tlb_list) | |
ee3f6ba8 | 367 | goto cleanup3; |
0b9afede | 368 | |
bc40ac66 BB |
369 | io_tlb_orig_addr = (phys_addr_t *) |
370 | __get_free_pages(GFP_KERNEL, | |
371 | get_order(io_tlb_nslabs * | |
372 | sizeof(phys_addr_t))); | |
0b9afede | 373 | if (!io_tlb_orig_addr) |
ee3f6ba8 | 374 | goto cleanup4; |
0b9afede | 375 | |
8e0629c1 JB |
376 | for (i = 0; i < io_tlb_nslabs; i++) { |
377 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); | |
378 | io_tlb_orig_addr[i] = INVALID_PHYS_ADDR; | |
379 | } | |
380 | io_tlb_index = 0; | |
0b9afede | 381 | |
ad32e8cb | 382 | swiotlb_print_info(); |
0b9afede | 383 | |
5740afdb FT |
384 | late_alloc = 1; |
385 | ||
7453c549 KRW |
386 | swiotlb_set_max_segment(io_tlb_nslabs << IO_TLB_SHIFT); |
387 | ||
0b9afede AW |
388 | return 0; |
389 | ||
390 | cleanup4: | |
25667d67 TL |
391 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * |
392 | sizeof(int))); | |
0b9afede | 393 | io_tlb_list = NULL; |
ee3f6ba8 AD |
394 | cleanup3: |
395 | free_pages((unsigned long)v_overflow_buffer, | |
396 | get_order(io_tlb_overflow)); | |
397 | io_tlb_overflow_buffer = 0; | |
0b9afede | 398 | cleanup2: |
c40dba06 | 399 | io_tlb_end = 0; |
ff7204a7 | 400 | io_tlb_start = 0; |
74838b75 | 401 | io_tlb_nslabs = 0; |
7453c549 | 402 | max_segment = 0; |
0b9afede AW |
403 | return -ENOMEM; |
404 | } | |
405 | ||
7f2c8bbd | 406 | void __init swiotlb_exit(void) |
5740afdb | 407 | { |
ee3f6ba8 | 408 | if (!io_tlb_orig_addr) |
5740afdb FT |
409 | return; |
410 | ||
411 | if (late_alloc) { | |
ee3f6ba8 | 412 | free_pages((unsigned long)phys_to_virt(io_tlb_overflow_buffer), |
5740afdb FT |
413 | get_order(io_tlb_overflow)); |
414 | free_pages((unsigned long)io_tlb_orig_addr, | |
415 | get_order(io_tlb_nslabs * sizeof(phys_addr_t))); | |
416 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * | |
417 | sizeof(int))); | |
ff7204a7 | 418 | free_pages((unsigned long)phys_to_virt(io_tlb_start), |
5740afdb FT |
419 | get_order(io_tlb_nslabs << IO_TLB_SHIFT)); |
420 | } else { | |
457ff1de SS |
421 | memblock_free_late(io_tlb_overflow_buffer, |
422 | PAGE_ALIGN(io_tlb_overflow)); | |
423 | memblock_free_late(__pa(io_tlb_orig_addr), | |
424 | PAGE_ALIGN(io_tlb_nslabs * sizeof(phys_addr_t))); | |
425 | memblock_free_late(__pa(io_tlb_list), | |
426 | PAGE_ALIGN(io_tlb_nslabs * sizeof(int))); | |
427 | memblock_free_late(io_tlb_start, | |
428 | PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT)); | |
5740afdb | 429 | } |
f21ffe9f | 430 | io_tlb_nslabs = 0; |
7453c549 | 431 | max_segment = 0; |
5740afdb FT |
432 | } |
433 | ||
9c5a3621 | 434 | int is_swiotlb_buffer(phys_addr_t paddr) |
640aebfe | 435 | { |
ff7204a7 | 436 | return paddr >= io_tlb_start && paddr < io_tlb_end; |
640aebfe FT |
437 | } |
438 | ||
fb05a379 BB |
439 | /* |
440 | * Bounce: copy the swiotlb buffer back to the original dma location | |
441 | */ | |
af51a9f1 AD |
442 | static void swiotlb_bounce(phys_addr_t orig_addr, phys_addr_t tlb_addr, |
443 | size_t size, enum dma_data_direction dir) | |
fb05a379 | 444 | { |
af51a9f1 AD |
445 | unsigned long pfn = PFN_DOWN(orig_addr); |
446 | unsigned char *vaddr = phys_to_virt(tlb_addr); | |
fb05a379 BB |
447 | |
448 | if (PageHighMem(pfn_to_page(pfn))) { | |
449 | /* The buffer does not have a mapping. Map it in and copy */ | |
af51a9f1 | 450 | unsigned int offset = orig_addr & ~PAGE_MASK; |
fb05a379 BB |
451 | char *buffer; |
452 | unsigned int sz = 0; | |
453 | unsigned long flags; | |
454 | ||
455 | while (size) { | |
67131ad0 | 456 | sz = min_t(size_t, PAGE_SIZE - offset, size); |
fb05a379 BB |
457 | |
458 | local_irq_save(flags); | |
c3eede8e | 459 | buffer = kmap_atomic(pfn_to_page(pfn)); |
fb05a379 | 460 | if (dir == DMA_TO_DEVICE) |
af51a9f1 | 461 | memcpy(vaddr, buffer + offset, sz); |
ef9b1893 | 462 | else |
af51a9f1 | 463 | memcpy(buffer + offset, vaddr, sz); |
c3eede8e | 464 | kunmap_atomic(buffer); |
ef9b1893 | 465 | local_irq_restore(flags); |
fb05a379 BB |
466 | |
467 | size -= sz; | |
468 | pfn++; | |
af51a9f1 | 469 | vaddr += sz; |
fb05a379 | 470 | offset = 0; |
ef9b1893 | 471 | } |
af51a9f1 AD |
472 | } else if (dir == DMA_TO_DEVICE) { |
473 | memcpy(vaddr, phys_to_virt(orig_addr), size); | |
ef9b1893 | 474 | } else { |
af51a9f1 | 475 | memcpy(phys_to_virt(orig_addr), vaddr, size); |
ef9b1893 | 476 | } |
1b548f66 JF |
477 | } |
478 | ||
e05ed4d1 AD |
479 | phys_addr_t swiotlb_tbl_map_single(struct device *hwdev, |
480 | dma_addr_t tbl_dma_addr, | |
481 | phys_addr_t orig_addr, size_t size, | |
0443fa00 AD |
482 | enum dma_data_direction dir, |
483 | unsigned long attrs) | |
1da177e4 LT |
484 | { |
485 | unsigned long flags; | |
e05ed4d1 | 486 | phys_addr_t tlb_addr; |
1da177e4 LT |
487 | unsigned int nslots, stride, index, wrap; |
488 | int i; | |
681cc5cd FT |
489 | unsigned long mask; |
490 | unsigned long offset_slots; | |
491 | unsigned long max_slots; | |
492 | ||
ac2cbab2 YL |
493 | if (no_iotlb_memory) |
494 | panic("Can not allocate SWIOTLB buffer earlier and can't now provide you with the DMA bounce buffer"); | |
495 | ||
d7b417fa TL |
496 | if (mem_encrypt_active()) |
497 | pr_warn_once("%s is active and system is using DMA bounce buffers\n", | |
498 | sme_active() ? "SME" : "SEV"); | |
648babb7 | 499 | |
681cc5cd | 500 | mask = dma_get_seg_boundary(hwdev); |
681cc5cd | 501 | |
eb605a57 FT |
502 | tbl_dma_addr &= mask; |
503 | ||
504 | offset_slots = ALIGN(tbl_dma_addr, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
a5ddde4a IC |
505 | |
506 | /* | |
507 | * Carefully handle integer overflow which can occur when mask == ~0UL. | |
508 | */ | |
b15a3891 JB |
509 | max_slots = mask + 1 |
510 | ? ALIGN(mask + 1, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT | |
511 | : 1UL << (BITS_PER_LONG - IO_TLB_SHIFT); | |
1da177e4 LT |
512 | |
513 | /* | |
602d9858 NY |
514 | * For mappings greater than or equal to a page, we limit the stride |
515 | * (and hence alignment) to a page size. | |
1da177e4 LT |
516 | */ |
517 | nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
602d9858 | 518 | if (size >= PAGE_SIZE) |
1da177e4 LT |
519 | stride = (1 << (PAGE_SHIFT - IO_TLB_SHIFT)); |
520 | else | |
521 | stride = 1; | |
522 | ||
34814545 | 523 | BUG_ON(!nslots); |
1da177e4 LT |
524 | |
525 | /* | |
526 | * Find suitable number of IO TLB entries size that will fit this | |
527 | * request and allocate a buffer from that IO TLB pool. | |
528 | */ | |
529 | spin_lock_irqsave(&io_tlb_lock, flags); | |
a7133a15 AM |
530 | index = ALIGN(io_tlb_index, stride); |
531 | if (index >= io_tlb_nslabs) | |
532 | index = 0; | |
533 | wrap = index; | |
534 | ||
535 | do { | |
a8522509 FT |
536 | while (iommu_is_span_boundary(index, nslots, offset_slots, |
537 | max_slots)) { | |
b15a3891 JB |
538 | index += stride; |
539 | if (index >= io_tlb_nslabs) | |
540 | index = 0; | |
a7133a15 AM |
541 | if (index == wrap) |
542 | goto not_found; | |
543 | } | |
544 | ||
545 | /* | |
546 | * If we find a slot that indicates we have 'nslots' number of | |
547 | * contiguous buffers, we allocate the buffers from that slot | |
548 | * and mark the entries as '0' indicating unavailable. | |
549 | */ | |
550 | if (io_tlb_list[index] >= nslots) { | |
551 | int count = 0; | |
552 | ||
553 | for (i = index; i < (int) (index + nslots); i++) | |
554 | io_tlb_list[i] = 0; | |
555 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE - 1) && io_tlb_list[i]; i--) | |
556 | io_tlb_list[i] = ++count; | |
e05ed4d1 | 557 | tlb_addr = io_tlb_start + (index << IO_TLB_SHIFT); |
1da177e4 | 558 | |
a7133a15 AM |
559 | /* |
560 | * Update the indices to avoid searching in the next | |
561 | * round. | |
562 | */ | |
563 | io_tlb_index = ((index + nslots) < io_tlb_nslabs | |
564 | ? (index + nslots) : 0); | |
565 | ||
566 | goto found; | |
567 | } | |
568 | index += stride; | |
569 | if (index >= io_tlb_nslabs) | |
570 | index = 0; | |
571 | } while (index != wrap); | |
572 | ||
573 | not_found: | |
574 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
d0bc0c2a | 575 | if (!(attrs & DMA_ATTR_NO_WARN) && printk_ratelimit()) |
0cb637bf | 576 | dev_warn(hwdev, "swiotlb buffer is full (sz: %zd bytes)\n", size); |
e05ed4d1 | 577 | return SWIOTLB_MAP_ERROR; |
a7133a15 | 578 | found: |
1da177e4 LT |
579 | spin_unlock_irqrestore(&io_tlb_lock, flags); |
580 | ||
581 | /* | |
582 | * Save away the mapping from the original address to the DMA address. | |
583 | * This is needed when we sync the memory. Then we sync the buffer if | |
584 | * needed. | |
585 | */ | |
bc40ac66 | 586 | for (i = 0; i < nslots; i++) |
e05ed4d1 | 587 | io_tlb_orig_addr[index+i] = orig_addr + (i << IO_TLB_SHIFT); |
0443fa00 AD |
588 | if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) && |
589 | (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
af51a9f1 | 590 | swiotlb_bounce(orig_addr, tlb_addr, size, DMA_TO_DEVICE); |
1da177e4 | 591 | |
e05ed4d1 | 592 | return tlb_addr; |
1da177e4 LT |
593 | } |
594 | ||
eb605a57 FT |
595 | /* |
596 | * Allocates bounce buffer and returns its kernel virtual address. | |
597 | */ | |
598 | ||
023600f1 AC |
599 | static phys_addr_t |
600 | map_single(struct device *hwdev, phys_addr_t phys, size_t size, | |
0443fa00 | 601 | enum dma_data_direction dir, unsigned long attrs) |
eb605a57 | 602 | { |
fff5d992 GU |
603 | dma_addr_t start_dma_addr; |
604 | ||
605 | if (swiotlb_force == SWIOTLB_NO_FORCE) { | |
606 | dev_warn_ratelimited(hwdev, "Cannot do DMA to address %pa\n", | |
607 | &phys); | |
608 | return SWIOTLB_MAP_ERROR; | |
609 | } | |
eb605a57 | 610 | |
b6e05477 | 611 | start_dma_addr = __phys_to_dma(hwdev, io_tlb_start); |
0443fa00 AD |
612 | return swiotlb_tbl_map_single(hwdev, start_dma_addr, phys, size, |
613 | dir, attrs); | |
eb605a57 FT |
614 | } |
615 | ||
1da177e4 LT |
616 | /* |
617 | * dma_addr is the kernel virtual address of the bounce buffer to unmap. | |
618 | */ | |
61ca08c3 | 619 | void swiotlb_tbl_unmap_single(struct device *hwdev, phys_addr_t tlb_addr, |
0443fa00 AD |
620 | size_t size, enum dma_data_direction dir, |
621 | unsigned long attrs) | |
1da177e4 LT |
622 | { |
623 | unsigned long flags; | |
624 | int i, count, nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
61ca08c3 AD |
625 | int index = (tlb_addr - io_tlb_start) >> IO_TLB_SHIFT; |
626 | phys_addr_t orig_addr = io_tlb_orig_addr[index]; | |
1da177e4 LT |
627 | |
628 | /* | |
629 | * First, sync the memory before unmapping the entry | |
630 | */ | |
8e0629c1 | 631 | if (orig_addr != INVALID_PHYS_ADDR && |
0443fa00 | 632 | !(attrs & DMA_ATTR_SKIP_CPU_SYNC) && |
8e0629c1 | 633 | ((dir == DMA_FROM_DEVICE) || (dir == DMA_BIDIRECTIONAL))) |
af51a9f1 | 634 | swiotlb_bounce(orig_addr, tlb_addr, size, DMA_FROM_DEVICE); |
1da177e4 LT |
635 | |
636 | /* | |
637 | * Return the buffer to the free list by setting the corresponding | |
af901ca1 | 638 | * entries to indicate the number of contiguous entries available. |
1da177e4 LT |
639 | * While returning the entries to the free list, we merge the entries |
640 | * with slots below and above the pool being returned. | |
641 | */ | |
642 | spin_lock_irqsave(&io_tlb_lock, flags); | |
643 | { | |
644 | count = ((index + nslots) < ALIGN(index + 1, IO_TLB_SEGSIZE) ? | |
645 | io_tlb_list[index + nslots] : 0); | |
646 | /* | |
647 | * Step 1: return the slots to the free list, merging the | |
648 | * slots with superceeding slots | |
649 | */ | |
8e0629c1 | 650 | for (i = index + nslots - 1; i >= index; i--) { |
1da177e4 | 651 | io_tlb_list[i] = ++count; |
8e0629c1 JB |
652 | io_tlb_orig_addr[i] = INVALID_PHYS_ADDR; |
653 | } | |
1da177e4 LT |
654 | /* |
655 | * Step 2: merge the returned slots with the preceding slots, | |
656 | * if available (non zero) | |
657 | */ | |
658 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE -1) && io_tlb_list[i]; i--) | |
659 | io_tlb_list[i] = ++count; | |
660 | } | |
661 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
662 | } | |
663 | ||
fbfda893 AD |
664 | void swiotlb_tbl_sync_single(struct device *hwdev, phys_addr_t tlb_addr, |
665 | size_t size, enum dma_data_direction dir, | |
666 | enum dma_sync_target target) | |
1da177e4 | 667 | { |
fbfda893 AD |
668 | int index = (tlb_addr - io_tlb_start) >> IO_TLB_SHIFT; |
669 | phys_addr_t orig_addr = io_tlb_orig_addr[index]; | |
bc40ac66 | 670 | |
8e0629c1 JB |
671 | if (orig_addr == INVALID_PHYS_ADDR) |
672 | return; | |
fbfda893 | 673 | orig_addr += (unsigned long)tlb_addr & ((1 << IO_TLB_SHIFT) - 1); |
df336d1c | 674 | |
de69e0f0 JL |
675 | switch (target) { |
676 | case SYNC_FOR_CPU: | |
677 | if (likely(dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
af51a9f1 | 678 | swiotlb_bounce(orig_addr, tlb_addr, |
fbfda893 | 679 | size, DMA_FROM_DEVICE); |
34814545 ES |
680 | else |
681 | BUG_ON(dir != DMA_TO_DEVICE); | |
de69e0f0 JL |
682 | break; |
683 | case SYNC_FOR_DEVICE: | |
684 | if (likely(dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
af51a9f1 | 685 | swiotlb_bounce(orig_addr, tlb_addr, |
fbfda893 | 686 | size, DMA_TO_DEVICE); |
34814545 ES |
687 | else |
688 | BUG_ON(dir != DMA_FROM_DEVICE); | |
de69e0f0 JL |
689 | break; |
690 | default: | |
1da177e4 | 691 | BUG(); |
de69e0f0 | 692 | } |
1da177e4 LT |
693 | } |
694 | ||
0803e605 | 695 | #ifdef CONFIG_DMA_DIRECT_OPS |
0176adb0 CH |
696 | static inline bool dma_coherent_ok(struct device *dev, dma_addr_t addr, |
697 | size_t size) | |
1da177e4 | 698 | { |
0176adb0 | 699 | u64 mask = DMA_BIT_MASK(32); |
1e74f300 | 700 | |
0176adb0 CH |
701 | if (dev && dev->coherent_dma_mask) |
702 | mask = dev->coherent_dma_mask; | |
703 | return addr + size - 1 <= mask; | |
704 | } | |
1da177e4 | 705 | |
0176adb0 CH |
706 | static void * |
707 | swiotlb_alloc_buffer(struct device *dev, size_t size, dma_addr_t *dma_handle, | |
708 | unsigned long attrs) | |
709 | { | |
710 | phys_addr_t phys_addr; | |
1da177e4 | 711 | |
0176adb0 CH |
712 | if (swiotlb_force == SWIOTLB_NO_FORCE) |
713 | goto out_warn; | |
1da177e4 | 714 | |
0176adb0 | 715 | phys_addr = swiotlb_tbl_map_single(dev, |
b6e05477 | 716 | __phys_to_dma(dev, io_tlb_start), |
0176adb0 CH |
717 | 0, size, DMA_FROM_DEVICE, 0); |
718 | if (phys_addr == SWIOTLB_MAP_ERROR) | |
719 | goto out_warn; | |
a2b89b59 | 720 | |
b6e05477 | 721 | *dma_handle = __phys_to_dma(dev, phys_addr); |
9e7f06c8 | 722 | if (!dma_coherent_ok(dev, *dma_handle, size)) |
0176adb0 | 723 | goto out_unmap; |
e05ed4d1 | 724 | |
0176adb0 CH |
725 | memset(phys_to_virt(phys_addr), 0, size); |
726 | return phys_to_virt(phys_addr); | |
e05ed4d1 | 727 | |
0176adb0 CH |
728 | out_unmap: |
729 | dev_warn(dev, "hwdev DMA mask = 0x%016Lx, dev_addr = 0x%016Lx\n", | |
730 | (unsigned long long)(dev ? dev->coherent_dma_mask : 0), | |
731 | (unsigned long long)*dma_handle); | |
94cc81f9 | 732 | |
0176adb0 CH |
733 | /* |
734 | * DMA_TO_DEVICE to avoid memcpy in unmap_single. | |
735 | * DMA_ATTR_SKIP_CPU_SYNC is optional. | |
736 | */ | |
737 | swiotlb_tbl_unmap_single(dev, phys_addr, size, DMA_TO_DEVICE, | |
738 | DMA_ATTR_SKIP_CPU_SYNC); | |
739 | out_warn: | |
892a0be4 | 740 | if (!(attrs & DMA_ATTR_NO_WARN) && printk_ratelimit()) { |
0176adb0 CH |
741 | dev_warn(dev, |
742 | "swiotlb: coherent allocation failed, size=%zu\n", | |
743 | size); | |
d0bc0c2a CK |
744 | dump_stack(); |
745 | } | |
94cc81f9 | 746 | return NULL; |
1da177e4 | 747 | } |
0176adb0 | 748 | |
a25381aa CH |
749 | static bool swiotlb_free_buffer(struct device *dev, size_t size, |
750 | dma_addr_t dma_addr) | |
751 | { | |
752 | phys_addr_t phys_addr = dma_to_phys(dev, dma_addr); | |
753 | ||
754 | WARN_ON_ONCE(irqs_disabled()); | |
755 | ||
756 | if (!is_swiotlb_buffer(phys_addr)) | |
757 | return false; | |
758 | ||
759 | /* | |
760 | * DMA_TO_DEVICE to avoid memcpy in swiotlb_tbl_unmap_single. | |
761 | * DMA_ATTR_SKIP_CPU_SYNC is optional. | |
762 | */ | |
763 | swiotlb_tbl_unmap_single(dev, phys_addr, size, DMA_TO_DEVICE, | |
764 | DMA_ATTR_SKIP_CPU_SYNC); | |
765 | return true; | |
766 | } | |
0803e605 | 767 | #endif |
a25381aa | 768 | |
1da177e4 | 769 | static void |
22d48269 KRW |
770 | swiotlb_full(struct device *dev, size_t size, enum dma_data_direction dir, |
771 | int do_panic) | |
1da177e4 | 772 | { |
fff5d992 GU |
773 | if (swiotlb_force == SWIOTLB_NO_FORCE) |
774 | return; | |
775 | ||
1da177e4 LT |
776 | /* |
777 | * Ran out of IOMMU space for this operation. This is very bad. | |
778 | * Unfortunately the drivers cannot handle this operation properly. | |
17e5ad6c | 779 | * unless they check for dma_mapping_error (most don't) |
1da177e4 LT |
780 | * When the mapping is small enough return a static buffer to limit |
781 | * the damage, or panic when the transfer is too big. | |
782 | */ | |
0d2e1898 GU |
783 | dev_err_ratelimited(dev, "DMA: Out of SW-IOMMU space for %zu bytes\n", |
784 | size); | |
1da177e4 | 785 | |
c7084b35 CD |
786 | if (size <= io_tlb_overflow || !do_panic) |
787 | return; | |
788 | ||
789 | if (dir == DMA_BIDIRECTIONAL) | |
790 | panic("DMA: Random memory could be DMA accessed\n"); | |
791 | if (dir == DMA_FROM_DEVICE) | |
792 | panic("DMA: Random memory could be DMA written\n"); | |
793 | if (dir == DMA_TO_DEVICE) | |
794 | panic("DMA: Random memory could be DMA read\n"); | |
1da177e4 LT |
795 | } |
796 | ||
797 | /* | |
798 | * Map a single buffer of the indicated size for DMA in streaming mode. The | |
17e5ad6c | 799 | * physical address to use is returned. |
1da177e4 LT |
800 | * |
801 | * Once the device is given the dma address, the device owns this memory until | |
ceb5ac32 | 802 | * either swiotlb_unmap_page or swiotlb_dma_sync_single is performed. |
1da177e4 | 803 | */ |
f98eee8e FT |
804 | dma_addr_t swiotlb_map_page(struct device *dev, struct page *page, |
805 | unsigned long offset, size_t size, | |
806 | enum dma_data_direction dir, | |
00085f1e | 807 | unsigned long attrs) |
1da177e4 | 808 | { |
e05ed4d1 | 809 | phys_addr_t map, phys = page_to_phys(page) + offset; |
862d196b | 810 | dma_addr_t dev_addr = phys_to_dma(dev, phys); |
1da177e4 | 811 | |
34814545 | 812 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 813 | /* |
ceb5ac32 | 814 | * If the address happens to be in the device's DMA window, |
1da177e4 LT |
815 | * we can safely return the device addr and not worry about bounce |
816 | * buffering it. | |
817 | */ | |
ae7871be | 818 | if (dma_capable(dev, dev_addr, size) && swiotlb_force != SWIOTLB_FORCE) |
1da177e4 LT |
819 | return dev_addr; |
820 | ||
2b2b614d ZK |
821 | trace_swiotlb_bounced(dev, dev_addr, size, swiotlb_force); |
822 | ||
e05ed4d1 | 823 | /* Oh well, have to allocate and map a bounce buffer. */ |
0443fa00 | 824 | map = map_single(dev, phys, size, dir, attrs); |
e05ed4d1 | 825 | if (map == SWIOTLB_MAP_ERROR) { |
f98eee8e | 826 | swiotlb_full(dev, size, dir, 1); |
b6e05477 | 827 | return __phys_to_dma(dev, io_tlb_overflow_buffer); |
1da177e4 LT |
828 | } |
829 | ||
b6e05477 | 830 | dev_addr = __phys_to_dma(dev, map); |
1da177e4 | 831 | |
e05ed4d1 | 832 | /* Ensure that the address returned is DMA'ble */ |
0443fa00 AD |
833 | if (dma_capable(dev, dev_addr, size)) |
834 | return dev_addr; | |
835 | ||
d29fa0cb AD |
836 | attrs |= DMA_ATTR_SKIP_CPU_SYNC; |
837 | swiotlb_tbl_unmap_single(dev, map, size, dir, attrs); | |
1da177e4 | 838 | |
b6e05477 | 839 | return __phys_to_dma(dev, io_tlb_overflow_buffer); |
1da177e4 LT |
840 | } |
841 | ||
1da177e4 LT |
842 | /* |
843 | * Unmap a single streaming mode DMA translation. The dma_addr and size must | |
ceb5ac32 | 844 | * match what was provided for in a previous swiotlb_map_page call. All |
1da177e4 LT |
845 | * other usages are undefined. |
846 | * | |
847 | * After this call, reads by the cpu to the buffer are guaranteed to see | |
848 | * whatever the device wrote there. | |
849 | */ | |
7fcebbd2 | 850 | static void unmap_single(struct device *hwdev, dma_addr_t dev_addr, |
0443fa00 AD |
851 | size_t size, enum dma_data_direction dir, |
852 | unsigned long attrs) | |
1da177e4 | 853 | { |
862d196b | 854 | phys_addr_t paddr = dma_to_phys(hwdev, dev_addr); |
1da177e4 | 855 | |
34814545 | 856 | BUG_ON(dir == DMA_NONE); |
7fcebbd2 | 857 | |
02ca646e | 858 | if (is_swiotlb_buffer(paddr)) { |
0443fa00 | 859 | swiotlb_tbl_unmap_single(hwdev, paddr, size, dir, attrs); |
7fcebbd2 BB |
860 | return; |
861 | } | |
862 | ||
863 | if (dir != DMA_FROM_DEVICE) | |
864 | return; | |
865 | ||
02ca646e FT |
866 | /* |
867 | * phys_to_virt doesn't work with hihgmem page but we could | |
868 | * call dma_mark_clean() with hihgmem page here. However, we | |
869 | * are fine since dma_mark_clean() is null on POWERPC. We can | |
870 | * make dma_mark_clean() take a physical address if necessary. | |
871 | */ | |
872 | dma_mark_clean(phys_to_virt(paddr), size); | |
7fcebbd2 BB |
873 | } |
874 | ||
875 | void swiotlb_unmap_page(struct device *hwdev, dma_addr_t dev_addr, | |
876 | size_t size, enum dma_data_direction dir, | |
00085f1e | 877 | unsigned long attrs) |
7fcebbd2 | 878 | { |
0443fa00 | 879 | unmap_single(hwdev, dev_addr, size, dir, attrs); |
1da177e4 | 880 | } |
874d6a95 | 881 | |
1da177e4 LT |
882 | /* |
883 | * Make physical memory consistent for a single streaming mode DMA translation | |
884 | * after a transfer. | |
885 | * | |
ceb5ac32 | 886 | * If you perform a swiotlb_map_page() but wish to interrogate the buffer |
17e5ad6c TL |
887 | * using the cpu, yet do not wish to teardown the dma mapping, you must |
888 | * call this function before doing so. At the next point you give the dma | |
1da177e4 LT |
889 | * address back to the card, you must first perform a |
890 | * swiotlb_dma_sync_for_device, and then the device again owns the buffer | |
891 | */ | |
be6b0267 | 892 | static void |
8270f3f1 | 893 | swiotlb_sync_single(struct device *hwdev, dma_addr_t dev_addr, |
d7ef1533 KRW |
894 | size_t size, enum dma_data_direction dir, |
895 | enum dma_sync_target target) | |
1da177e4 | 896 | { |
862d196b | 897 | phys_addr_t paddr = dma_to_phys(hwdev, dev_addr); |
1da177e4 | 898 | |
34814545 | 899 | BUG_ON(dir == DMA_NONE); |
380d6878 | 900 | |
02ca646e | 901 | if (is_swiotlb_buffer(paddr)) { |
fbfda893 | 902 | swiotlb_tbl_sync_single(hwdev, paddr, size, dir, target); |
380d6878 BB |
903 | return; |
904 | } | |
905 | ||
906 | if (dir != DMA_FROM_DEVICE) | |
907 | return; | |
908 | ||
02ca646e | 909 | dma_mark_clean(phys_to_virt(paddr), size); |
1da177e4 LT |
910 | } |
911 | ||
8270f3f1 JL |
912 | void |
913 | swiotlb_sync_single_for_cpu(struct device *hwdev, dma_addr_t dev_addr, | |
160c1d8e | 914 | size_t size, enum dma_data_direction dir) |
8270f3f1 | 915 | { |
de69e0f0 | 916 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_CPU); |
8270f3f1 JL |
917 | } |
918 | ||
1da177e4 LT |
919 | void |
920 | swiotlb_sync_single_for_device(struct device *hwdev, dma_addr_t dev_addr, | |
160c1d8e | 921 | size_t size, enum dma_data_direction dir) |
1da177e4 | 922 | { |
de69e0f0 | 923 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_DEVICE); |
1da177e4 LT |
924 | } |
925 | ||
926 | /* | |
927 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
ceb5ac32 | 928 | * This is the scatter-gather version of the above swiotlb_map_page |
1da177e4 LT |
929 | * interface. Here the scatter gather list elements are each tagged with the |
930 | * appropriate dma address and length. They are obtained via | |
931 | * sg_dma_{address,length}(SG). | |
932 | * | |
933 | * NOTE: An implementation may be able to use a smaller number of | |
934 | * DMA address/length pairs than there are SG table elements. | |
935 | * (for example via virtual mapping capabilities) | |
936 | * The routine returns the number of addr/length pairs actually | |
937 | * used, at most nents. | |
938 | * | |
ceb5ac32 | 939 | * Device ownership issues as mentioned above for swiotlb_map_page are the |
1da177e4 LT |
940 | * same here. |
941 | */ | |
942 | int | |
309df0c5 | 943 | swiotlb_map_sg_attrs(struct device *hwdev, struct scatterlist *sgl, int nelems, |
00085f1e | 944 | enum dma_data_direction dir, unsigned long attrs) |
1da177e4 | 945 | { |
dbfd49fe | 946 | struct scatterlist *sg; |
1da177e4 LT |
947 | int i; |
948 | ||
34814545 | 949 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 950 | |
dbfd49fe | 951 | for_each_sg(sgl, sg, nelems, i) { |
961d7d0e | 952 | phys_addr_t paddr = sg_phys(sg); |
862d196b | 953 | dma_addr_t dev_addr = phys_to_dma(hwdev, paddr); |
bc40ac66 | 954 | |
ae7871be | 955 | if (swiotlb_force == SWIOTLB_FORCE || |
b9394647 | 956 | !dma_capable(hwdev, dev_addr, sg->length)) { |
e05ed4d1 | 957 | phys_addr_t map = map_single(hwdev, sg_phys(sg), |
0443fa00 | 958 | sg->length, dir, attrs); |
e05ed4d1 | 959 | if (map == SWIOTLB_MAP_ERROR) { |
1da177e4 LT |
960 | /* Don't panic here, we expect map_sg users |
961 | to do proper error handling. */ | |
962 | swiotlb_full(hwdev, sg->length, dir, 0); | |
d29fa0cb | 963 | attrs |= DMA_ATTR_SKIP_CPU_SYNC; |
309df0c5 AK |
964 | swiotlb_unmap_sg_attrs(hwdev, sgl, i, dir, |
965 | attrs); | |
4d86ec7a | 966 | sg_dma_len(sgl) = 0; |
1da177e4 LT |
967 | return 0; |
968 | } | |
b6e05477 | 969 | sg->dma_address = __phys_to_dma(hwdev, map); |
1da177e4 LT |
970 | } else |
971 | sg->dma_address = dev_addr; | |
4d86ec7a | 972 | sg_dma_len(sg) = sg->length; |
1da177e4 LT |
973 | } |
974 | return nelems; | |
975 | } | |
309df0c5 | 976 | |
1da177e4 LT |
977 | /* |
978 | * Unmap a set of streaming mode DMA translations. Again, cpu read rules | |
ceb5ac32 | 979 | * concerning calls here are the same as for swiotlb_unmap_page() above. |
1da177e4 LT |
980 | */ |
981 | void | |
309df0c5 | 982 | swiotlb_unmap_sg_attrs(struct device *hwdev, struct scatterlist *sgl, |
00085f1e KK |
983 | int nelems, enum dma_data_direction dir, |
984 | unsigned long attrs) | |
1da177e4 | 985 | { |
dbfd49fe | 986 | struct scatterlist *sg; |
1da177e4 LT |
987 | int i; |
988 | ||
34814545 | 989 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 990 | |
7fcebbd2 | 991 | for_each_sg(sgl, sg, nelems, i) |
0443fa00 AD |
992 | unmap_single(hwdev, sg->dma_address, sg_dma_len(sg), dir, |
993 | attrs); | |
1da177e4 | 994 | } |
309df0c5 | 995 | |
1da177e4 LT |
996 | /* |
997 | * Make physical memory consistent for a set of streaming mode DMA translations | |
998 | * after a transfer. | |
999 | * | |
1000 | * The same as swiotlb_sync_single_* but for a scatter-gather list, same rules | |
1001 | * and usage. | |
1002 | */ | |
be6b0267 | 1003 | static void |
dbfd49fe | 1004 | swiotlb_sync_sg(struct device *hwdev, struct scatterlist *sgl, |
d7ef1533 KRW |
1005 | int nelems, enum dma_data_direction dir, |
1006 | enum dma_sync_target target) | |
1da177e4 | 1007 | { |
dbfd49fe | 1008 | struct scatterlist *sg; |
1da177e4 LT |
1009 | int i; |
1010 | ||
380d6878 BB |
1011 | for_each_sg(sgl, sg, nelems, i) |
1012 | swiotlb_sync_single(hwdev, sg->dma_address, | |
4d86ec7a | 1013 | sg_dma_len(sg), dir, target); |
1da177e4 LT |
1014 | } |
1015 | ||
8270f3f1 JL |
1016 | void |
1017 | swiotlb_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg, | |
160c1d8e | 1018 | int nelems, enum dma_data_direction dir) |
8270f3f1 | 1019 | { |
de69e0f0 | 1020 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_CPU); |
8270f3f1 JL |
1021 | } |
1022 | ||
1da177e4 LT |
1023 | void |
1024 | swiotlb_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg, | |
160c1d8e | 1025 | int nelems, enum dma_data_direction dir) |
1da177e4 | 1026 | { |
de69e0f0 | 1027 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_DEVICE); |
1da177e4 LT |
1028 | } |
1029 | ||
1030 | int | |
8d8bb39b | 1031 | swiotlb_dma_mapping_error(struct device *hwdev, dma_addr_t dma_addr) |
1da177e4 | 1032 | { |
b6e05477 | 1033 | return (dma_addr == __phys_to_dma(hwdev, io_tlb_overflow_buffer)); |
1da177e4 LT |
1034 | } |
1035 | ||
1036 | /* | |
17e5ad6c | 1037 | * Return whether the given device DMA address mask can be supported |
1da177e4 | 1038 | * properly. For example, if your device can only drive the low 24-bits |
17e5ad6c | 1039 | * during bus mastering, then you would pass 0x00ffffff as the mask to |
1da177e4 LT |
1040 | * this function. |
1041 | */ | |
1042 | int | |
563aaf06 | 1043 | swiotlb_dma_supported(struct device *hwdev, u64 mask) |
1da177e4 | 1044 | { |
b6e05477 | 1045 | return __phys_to_dma(hwdev, io_tlb_end - 1) <= mask; |
1da177e4 | 1046 | } |
251533eb CH |
1047 | |
1048 | #ifdef CONFIG_DMA_DIRECT_OPS | |
1049 | void *swiotlb_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle, | |
1050 | gfp_t gfp, unsigned long attrs) | |
1051 | { | |
1052 | void *vaddr; | |
1053 | ||
0176adb0 CH |
1054 | /* temporary workaround: */ |
1055 | if (gfp & __GFP_NOWARN) | |
1056 | attrs |= DMA_ATTR_NO_WARN; | |
1057 | ||
251533eb CH |
1058 | /* |
1059 | * Don't print a warning when the first allocation attempt fails. | |
1060 | * swiotlb_alloc_coherent() will print a warning when the DMA memory | |
1061 | * allocation ultimately failed. | |
1062 | */ | |
1063 | gfp |= __GFP_NOWARN; | |
1064 | ||
1065 | vaddr = dma_direct_alloc(dev, size, dma_handle, gfp, attrs); | |
1066 | if (!vaddr) | |
0176adb0 | 1067 | vaddr = swiotlb_alloc_buffer(dev, size, dma_handle, attrs); |
251533eb CH |
1068 | return vaddr; |
1069 | } | |
1070 | ||
1071 | void swiotlb_free(struct device *dev, size_t size, void *vaddr, | |
1072 | dma_addr_t dma_addr, unsigned long attrs) | |
1073 | { | |
a25381aa | 1074 | if (!swiotlb_free_buffer(dev, size, dma_addr)) |
251533eb CH |
1075 | dma_direct_free(dev, size, vaddr, dma_addr, attrs); |
1076 | } | |
1077 | ||
1078 | const struct dma_map_ops swiotlb_dma_ops = { | |
1079 | .mapping_error = swiotlb_dma_mapping_error, | |
1080 | .alloc = swiotlb_alloc, | |
1081 | .free = swiotlb_free, | |
1082 | .sync_single_for_cpu = swiotlb_sync_single_for_cpu, | |
1083 | .sync_single_for_device = swiotlb_sync_single_for_device, | |
1084 | .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu, | |
1085 | .sync_sg_for_device = swiotlb_sync_sg_for_device, | |
1086 | .map_sg = swiotlb_map_sg_attrs, | |
1087 | .unmap_sg = swiotlb_unmap_sg_attrs, | |
1088 | .map_page = swiotlb_map_page, | |
1089 | .unmap_page = swiotlb_unmap_page, | |
66bdb147 | 1090 | .dma_supported = dma_direct_supported, |
251533eb CH |
1091 | }; |
1092 | #endif /* CONFIG_DMA_DIRECT_OPS */ |