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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Dynamic DMA mapping support. | |
3 | * | |
563aaf06 | 4 | * This implementation is a fallback for platforms that do not support |
1da177e4 LT |
5 | * I/O TLBs (aka DMA address translation hardware). |
6 | * Copyright (C) 2000 Asit Mallick <Asit.K.Mallick@intel.com> | |
7 | * Copyright (C) 2000 Goutham Rao <goutham.rao@intel.com> | |
8 | * Copyright (C) 2000, 2003 Hewlett-Packard Co | |
9 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
10 | * | |
11 | * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API. | |
12 | * 00/12/13 davidm Rename to swiotlb.c and add mark_clean() to avoid | |
13 | * unnecessary i-cache flushing. | |
569c8bf5 JL |
14 | * 04/07/.. ak Better overflow handling. Assorted fixes. |
15 | * 05/09/10 linville Add support for syncing ranges, support syncing for | |
16 | * DMA_BIDIRECTIONAL mappings, miscellaneous cleanup. | |
fb05a379 | 17 | * 08/12/11 beckyb Add highmem support |
1da177e4 LT |
18 | */ |
19 | ||
20 | #include <linux/cache.h> | |
17e5ad6c | 21 | #include <linux/dma-mapping.h> |
1da177e4 LT |
22 | #include <linux/mm.h> |
23 | #include <linux/module.h> | |
1da177e4 LT |
24 | #include <linux/spinlock.h> |
25 | #include <linux/string.h> | |
0016fdee | 26 | #include <linux/swiotlb.h> |
fb05a379 | 27 | #include <linux/pfn.h> |
1da177e4 LT |
28 | #include <linux/types.h> |
29 | #include <linux/ctype.h> | |
ef9b1893 | 30 | #include <linux/highmem.h> |
1da177e4 LT |
31 | |
32 | #include <asm/io.h> | |
1da177e4 | 33 | #include <asm/dma.h> |
17e5ad6c | 34 | #include <asm/scatterlist.h> |
1da177e4 LT |
35 | |
36 | #include <linux/init.h> | |
37 | #include <linux/bootmem.h> | |
a8522509 | 38 | #include <linux/iommu-helper.h> |
1da177e4 LT |
39 | |
40 | #define OFFSET(val,align) ((unsigned long) \ | |
41 | ( (val) & ( (align) - 1))) | |
42 | ||
0b9afede AW |
43 | #define SLABS_PER_PAGE (1 << (PAGE_SHIFT - IO_TLB_SHIFT)) |
44 | ||
45 | /* | |
46 | * Minimum IO TLB size to bother booting with. Systems with mainly | |
47 | * 64bit capable cards will only lightly use the swiotlb. If we can't | |
48 | * allocate a contiguous 1MB, we're probably in trouble anyway. | |
49 | */ | |
50 | #define IO_TLB_MIN_SLABS ((1<<20) >> IO_TLB_SHIFT) | |
51 | ||
de69e0f0 JL |
52 | /* |
53 | * Enumeration for sync targets | |
54 | */ | |
55 | enum dma_sync_target { | |
56 | SYNC_FOR_CPU = 0, | |
57 | SYNC_FOR_DEVICE = 1, | |
58 | }; | |
59 | ||
1da177e4 LT |
60 | int swiotlb_force; |
61 | ||
62 | /* | |
ceb5ac32 BB |
63 | * Used to do a quick range check in unmap_single and |
64 | * sync_single_*, to see if the memory was in fact allocated by this | |
1da177e4 LT |
65 | * API. |
66 | */ | |
67 | static char *io_tlb_start, *io_tlb_end; | |
68 | ||
69 | /* | |
70 | * The number of IO TLB blocks (in groups of 64) betweeen io_tlb_start and | |
71 | * io_tlb_end. This is command line adjustable via setup_io_tlb_npages. | |
72 | */ | |
73 | static unsigned long io_tlb_nslabs; | |
74 | ||
75 | /* | |
76 | * When the IOMMU overflows we return a fallback buffer. This sets the size. | |
77 | */ | |
78 | static unsigned long io_tlb_overflow = 32*1024; | |
79 | ||
80 | void *io_tlb_overflow_buffer; | |
81 | ||
82 | /* | |
83 | * This is a free list describing the number of free entries available from | |
84 | * each index | |
85 | */ | |
86 | static unsigned int *io_tlb_list; | |
87 | static unsigned int io_tlb_index; | |
88 | ||
89 | /* | |
90 | * We need to save away the original address corresponding to a mapped entry | |
91 | * for the sync operations. | |
92 | */ | |
bc40ac66 | 93 | static phys_addr_t *io_tlb_orig_addr; |
1da177e4 LT |
94 | |
95 | /* | |
96 | * Protect the above data structures in the map and unmap calls | |
97 | */ | |
98 | static DEFINE_SPINLOCK(io_tlb_lock); | |
99 | ||
100 | static int __init | |
101 | setup_io_tlb_npages(char *str) | |
102 | { | |
103 | if (isdigit(*str)) { | |
e8579e72 | 104 | io_tlb_nslabs = simple_strtoul(str, &str, 0); |
1da177e4 LT |
105 | /* avoid tail segment of size < IO_TLB_SEGSIZE */ |
106 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
107 | } | |
108 | if (*str == ',') | |
109 | ++str; | |
110 | if (!strcmp(str, "force")) | |
111 | swiotlb_force = 1; | |
112 | return 1; | |
113 | } | |
114 | __setup("swiotlb=", setup_io_tlb_npages); | |
115 | /* make io_tlb_overflow tunable too? */ | |
116 | ||
70a7d3cc | 117 | dma_addr_t __weak swiotlb_phys_to_bus(struct device *hwdev, phys_addr_t paddr) |
e08e1f7a IC |
118 | { |
119 | return paddr; | |
120 | } | |
121 | ||
42d7c5e3 | 122 | phys_addr_t __weak swiotlb_bus_to_phys(struct device *hwdev, dma_addr_t baddr) |
e08e1f7a IC |
123 | { |
124 | return baddr; | |
125 | } | |
126 | ||
70a7d3cc JF |
127 | static dma_addr_t swiotlb_virt_to_bus(struct device *hwdev, |
128 | volatile void *address) | |
e08e1f7a | 129 | { |
70a7d3cc | 130 | return swiotlb_phys_to_bus(hwdev, virt_to_phys(address)); |
e08e1f7a IC |
131 | } |
132 | ||
42d7c5e3 | 133 | void * __weak swiotlb_bus_to_virt(struct device *hwdev, dma_addr_t address) |
e08e1f7a | 134 | { |
42d7c5e3 | 135 | return phys_to_virt(swiotlb_bus_to_phys(hwdev, address)); |
e08e1f7a IC |
136 | } |
137 | ||
ef5722f6 BB |
138 | int __weak swiotlb_arch_address_needs_mapping(struct device *hwdev, |
139 | dma_addr_t addr, size_t size) | |
140 | { | |
141 | return !is_buffer_dma_capable(dma_get_mask(hwdev), addr, size); | |
142 | } | |
143 | ||
2e5b2b86 IC |
144 | static void swiotlb_print_info(unsigned long bytes) |
145 | { | |
146 | phys_addr_t pstart, pend; | |
2e5b2b86 IC |
147 | |
148 | pstart = virt_to_phys(io_tlb_start); | |
149 | pend = virt_to_phys(io_tlb_end); | |
150 | ||
2e5b2b86 IC |
151 | printk(KERN_INFO "Placing %luMB software IO TLB between %p - %p\n", |
152 | bytes >> 20, io_tlb_start, io_tlb_end); | |
70a7d3cc JF |
153 | printk(KERN_INFO "software IO TLB at phys %#llx - %#llx\n", |
154 | (unsigned long long)pstart, | |
155 | (unsigned long long)pend); | |
2e5b2b86 IC |
156 | } |
157 | ||
1da177e4 LT |
158 | /* |
159 | * Statically reserve bounce buffer space and initialize bounce buffer data | |
17e5ad6c | 160 | * structures for the software IO TLB used to implement the DMA API. |
1da177e4 | 161 | */ |
563aaf06 JB |
162 | void __init |
163 | swiotlb_init_with_default_size(size_t default_size) | |
1da177e4 | 164 | { |
563aaf06 | 165 | unsigned long i, bytes; |
1da177e4 LT |
166 | |
167 | if (!io_tlb_nslabs) { | |
e8579e72 | 168 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); |
1da177e4 LT |
169 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); |
170 | } | |
171 | ||
563aaf06 JB |
172 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
173 | ||
1da177e4 LT |
174 | /* |
175 | * Get IO TLB memory from the low pages | |
176 | */ | |
3885123d | 177 | io_tlb_start = alloc_bootmem_low_pages(bytes); |
1da177e4 LT |
178 | if (!io_tlb_start) |
179 | panic("Cannot allocate SWIOTLB buffer"); | |
563aaf06 | 180 | io_tlb_end = io_tlb_start + bytes; |
1da177e4 LT |
181 | |
182 | /* | |
183 | * Allocate and initialize the free list array. This array is used | |
184 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
185 | * between io_tlb_start and io_tlb_end. | |
186 | */ | |
187 | io_tlb_list = alloc_bootmem(io_tlb_nslabs * sizeof(int)); | |
25667d67 | 188 | for (i = 0; i < io_tlb_nslabs; i++) |
1da177e4 LT |
189 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); |
190 | io_tlb_index = 0; | |
bc40ac66 | 191 | io_tlb_orig_addr = alloc_bootmem(io_tlb_nslabs * sizeof(phys_addr_t)); |
1da177e4 LT |
192 | |
193 | /* | |
194 | * Get the overflow emergency buffer | |
195 | */ | |
196 | io_tlb_overflow_buffer = alloc_bootmem_low(io_tlb_overflow); | |
563aaf06 JB |
197 | if (!io_tlb_overflow_buffer) |
198 | panic("Cannot allocate SWIOTLB overflow buffer!\n"); | |
199 | ||
2e5b2b86 | 200 | swiotlb_print_info(bytes); |
1da177e4 LT |
201 | } |
202 | ||
563aaf06 JB |
203 | void __init |
204 | swiotlb_init(void) | |
1da177e4 | 205 | { |
25667d67 | 206 | swiotlb_init_with_default_size(64 * (1<<20)); /* default to 64MB */ |
1da177e4 LT |
207 | } |
208 | ||
0b9afede AW |
209 | /* |
210 | * Systems with larger DMA zones (those that don't support ISA) can | |
211 | * initialize the swiotlb later using the slab allocator if needed. | |
212 | * This should be just like above, but with some error catching. | |
213 | */ | |
214 | int | |
563aaf06 | 215 | swiotlb_late_init_with_default_size(size_t default_size) |
0b9afede | 216 | { |
563aaf06 | 217 | unsigned long i, bytes, req_nslabs = io_tlb_nslabs; |
0b9afede AW |
218 | unsigned int order; |
219 | ||
220 | if (!io_tlb_nslabs) { | |
221 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); | |
222 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
223 | } | |
224 | ||
225 | /* | |
226 | * Get IO TLB memory from the low pages | |
227 | */ | |
563aaf06 | 228 | order = get_order(io_tlb_nslabs << IO_TLB_SHIFT); |
0b9afede | 229 | io_tlb_nslabs = SLABS_PER_PAGE << order; |
563aaf06 | 230 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
0b9afede AW |
231 | |
232 | while ((SLABS_PER_PAGE << order) > IO_TLB_MIN_SLABS) { | |
bb52196b FT |
233 | io_tlb_start = (void *)__get_free_pages(GFP_DMA | __GFP_NOWARN, |
234 | order); | |
0b9afede AW |
235 | if (io_tlb_start) |
236 | break; | |
237 | order--; | |
238 | } | |
239 | ||
240 | if (!io_tlb_start) | |
241 | goto cleanup1; | |
242 | ||
563aaf06 | 243 | if (order != get_order(bytes)) { |
0b9afede AW |
244 | printk(KERN_WARNING "Warning: only able to allocate %ld MB " |
245 | "for software IO TLB\n", (PAGE_SIZE << order) >> 20); | |
246 | io_tlb_nslabs = SLABS_PER_PAGE << order; | |
563aaf06 | 247 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
0b9afede | 248 | } |
563aaf06 JB |
249 | io_tlb_end = io_tlb_start + bytes; |
250 | memset(io_tlb_start, 0, bytes); | |
0b9afede AW |
251 | |
252 | /* | |
253 | * Allocate and initialize the free list array. This array is used | |
254 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
255 | * between io_tlb_start and io_tlb_end. | |
256 | */ | |
257 | io_tlb_list = (unsigned int *)__get_free_pages(GFP_KERNEL, | |
258 | get_order(io_tlb_nslabs * sizeof(int))); | |
259 | if (!io_tlb_list) | |
260 | goto cleanup2; | |
261 | ||
262 | for (i = 0; i < io_tlb_nslabs; i++) | |
263 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); | |
264 | io_tlb_index = 0; | |
265 | ||
bc40ac66 BB |
266 | io_tlb_orig_addr = (phys_addr_t *) |
267 | __get_free_pages(GFP_KERNEL, | |
268 | get_order(io_tlb_nslabs * | |
269 | sizeof(phys_addr_t))); | |
0b9afede AW |
270 | if (!io_tlb_orig_addr) |
271 | goto cleanup3; | |
272 | ||
bc40ac66 | 273 | memset(io_tlb_orig_addr, 0, io_tlb_nslabs * sizeof(phys_addr_t)); |
0b9afede AW |
274 | |
275 | /* | |
276 | * Get the overflow emergency buffer | |
277 | */ | |
278 | io_tlb_overflow_buffer = (void *)__get_free_pages(GFP_DMA, | |
279 | get_order(io_tlb_overflow)); | |
280 | if (!io_tlb_overflow_buffer) | |
281 | goto cleanup4; | |
282 | ||
2e5b2b86 | 283 | swiotlb_print_info(bytes); |
0b9afede AW |
284 | |
285 | return 0; | |
286 | ||
287 | cleanup4: | |
bc40ac66 BB |
288 | free_pages((unsigned long)io_tlb_orig_addr, |
289 | get_order(io_tlb_nslabs * sizeof(phys_addr_t))); | |
0b9afede AW |
290 | io_tlb_orig_addr = NULL; |
291 | cleanup3: | |
25667d67 TL |
292 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * |
293 | sizeof(int))); | |
0b9afede | 294 | io_tlb_list = NULL; |
0b9afede | 295 | cleanup2: |
563aaf06 | 296 | io_tlb_end = NULL; |
0b9afede AW |
297 | free_pages((unsigned long)io_tlb_start, order); |
298 | io_tlb_start = NULL; | |
299 | cleanup1: | |
300 | io_tlb_nslabs = req_nslabs; | |
301 | return -ENOMEM; | |
302 | } | |
303 | ||
ef5722f6 | 304 | static inline int |
2797982e | 305 | address_needs_mapping(struct device *hwdev, dma_addr_t addr, size_t size) |
1da177e4 | 306 | { |
ef5722f6 | 307 | return swiotlb_arch_address_needs_mapping(hwdev, addr, size); |
1da177e4 LT |
308 | } |
309 | ||
640aebfe FT |
310 | static int is_swiotlb_buffer(char *addr) |
311 | { | |
312 | return addr >= io_tlb_start && addr < io_tlb_end; | |
313 | } | |
314 | ||
fb05a379 BB |
315 | /* |
316 | * Bounce: copy the swiotlb buffer back to the original dma location | |
317 | */ | |
318 | static void swiotlb_bounce(phys_addr_t phys, char *dma_addr, size_t size, | |
319 | enum dma_data_direction dir) | |
320 | { | |
321 | unsigned long pfn = PFN_DOWN(phys); | |
322 | ||
323 | if (PageHighMem(pfn_to_page(pfn))) { | |
324 | /* The buffer does not have a mapping. Map it in and copy */ | |
325 | unsigned int offset = phys & ~PAGE_MASK; | |
326 | char *buffer; | |
327 | unsigned int sz = 0; | |
328 | unsigned long flags; | |
329 | ||
330 | while (size) { | |
67131ad0 | 331 | sz = min_t(size_t, PAGE_SIZE - offset, size); |
fb05a379 BB |
332 | |
333 | local_irq_save(flags); | |
334 | buffer = kmap_atomic(pfn_to_page(pfn), | |
335 | KM_BOUNCE_READ); | |
336 | if (dir == DMA_TO_DEVICE) | |
337 | memcpy(dma_addr, buffer + offset, sz); | |
ef9b1893 | 338 | else |
fb05a379 BB |
339 | memcpy(buffer + offset, dma_addr, sz); |
340 | kunmap_atomic(buffer, KM_BOUNCE_READ); | |
ef9b1893 | 341 | local_irq_restore(flags); |
fb05a379 BB |
342 | |
343 | size -= sz; | |
344 | pfn++; | |
345 | dma_addr += sz; | |
346 | offset = 0; | |
ef9b1893 JF |
347 | } |
348 | } else { | |
ef9b1893 | 349 | if (dir == DMA_TO_DEVICE) |
fb05a379 | 350 | memcpy(dma_addr, phys_to_virt(phys), size); |
ef9b1893 | 351 | else |
fb05a379 | 352 | memcpy(phys_to_virt(phys), dma_addr, size); |
ef9b1893 | 353 | } |
1b548f66 JF |
354 | } |
355 | ||
1da177e4 LT |
356 | /* |
357 | * Allocates bounce buffer and returns its kernel virtual address. | |
358 | */ | |
359 | static void * | |
bc40ac66 | 360 | map_single(struct device *hwdev, phys_addr_t phys, size_t size, int dir) |
1da177e4 LT |
361 | { |
362 | unsigned long flags; | |
363 | char *dma_addr; | |
364 | unsigned int nslots, stride, index, wrap; | |
365 | int i; | |
681cc5cd FT |
366 | unsigned long start_dma_addr; |
367 | unsigned long mask; | |
368 | unsigned long offset_slots; | |
369 | unsigned long max_slots; | |
370 | ||
371 | mask = dma_get_seg_boundary(hwdev); | |
70a7d3cc | 372 | start_dma_addr = swiotlb_virt_to_bus(hwdev, io_tlb_start) & mask; |
681cc5cd FT |
373 | |
374 | offset_slots = ALIGN(start_dma_addr, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
a5ddde4a IC |
375 | |
376 | /* | |
377 | * Carefully handle integer overflow which can occur when mask == ~0UL. | |
378 | */ | |
b15a3891 JB |
379 | max_slots = mask + 1 |
380 | ? ALIGN(mask + 1, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT | |
381 | : 1UL << (BITS_PER_LONG - IO_TLB_SHIFT); | |
1da177e4 LT |
382 | |
383 | /* | |
384 | * For mappings greater than a page, we limit the stride (and | |
385 | * hence alignment) to a page size. | |
386 | */ | |
387 | nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
388 | if (size > PAGE_SIZE) | |
389 | stride = (1 << (PAGE_SHIFT - IO_TLB_SHIFT)); | |
390 | else | |
391 | stride = 1; | |
392 | ||
34814545 | 393 | BUG_ON(!nslots); |
1da177e4 LT |
394 | |
395 | /* | |
396 | * Find suitable number of IO TLB entries size that will fit this | |
397 | * request and allocate a buffer from that IO TLB pool. | |
398 | */ | |
399 | spin_lock_irqsave(&io_tlb_lock, flags); | |
a7133a15 AM |
400 | index = ALIGN(io_tlb_index, stride); |
401 | if (index >= io_tlb_nslabs) | |
402 | index = 0; | |
403 | wrap = index; | |
404 | ||
405 | do { | |
a8522509 FT |
406 | while (iommu_is_span_boundary(index, nslots, offset_slots, |
407 | max_slots)) { | |
b15a3891 JB |
408 | index += stride; |
409 | if (index >= io_tlb_nslabs) | |
410 | index = 0; | |
a7133a15 AM |
411 | if (index == wrap) |
412 | goto not_found; | |
413 | } | |
414 | ||
415 | /* | |
416 | * If we find a slot that indicates we have 'nslots' number of | |
417 | * contiguous buffers, we allocate the buffers from that slot | |
418 | * and mark the entries as '0' indicating unavailable. | |
419 | */ | |
420 | if (io_tlb_list[index] >= nslots) { | |
421 | int count = 0; | |
422 | ||
423 | for (i = index; i < (int) (index + nslots); i++) | |
424 | io_tlb_list[i] = 0; | |
425 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE - 1) && io_tlb_list[i]; i--) | |
426 | io_tlb_list[i] = ++count; | |
427 | dma_addr = io_tlb_start + (index << IO_TLB_SHIFT); | |
1da177e4 | 428 | |
a7133a15 AM |
429 | /* |
430 | * Update the indices to avoid searching in the next | |
431 | * round. | |
432 | */ | |
433 | io_tlb_index = ((index + nslots) < io_tlb_nslabs | |
434 | ? (index + nslots) : 0); | |
435 | ||
436 | goto found; | |
437 | } | |
438 | index += stride; | |
439 | if (index >= io_tlb_nslabs) | |
440 | index = 0; | |
441 | } while (index != wrap); | |
442 | ||
443 | not_found: | |
444 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
445 | return NULL; | |
446 | found: | |
1da177e4 LT |
447 | spin_unlock_irqrestore(&io_tlb_lock, flags); |
448 | ||
449 | /* | |
450 | * Save away the mapping from the original address to the DMA address. | |
451 | * This is needed when we sync the memory. Then we sync the buffer if | |
452 | * needed. | |
453 | */ | |
bc40ac66 BB |
454 | for (i = 0; i < nslots; i++) |
455 | io_tlb_orig_addr[index+i] = phys + (i << IO_TLB_SHIFT); | |
1da177e4 | 456 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL) |
fb05a379 | 457 | swiotlb_bounce(phys, dma_addr, size, DMA_TO_DEVICE); |
1da177e4 LT |
458 | |
459 | return dma_addr; | |
460 | } | |
461 | ||
462 | /* | |
463 | * dma_addr is the kernel virtual address of the bounce buffer to unmap. | |
464 | */ | |
465 | static void | |
7fcebbd2 | 466 | do_unmap_single(struct device *hwdev, char *dma_addr, size_t size, int dir) |
1da177e4 LT |
467 | { |
468 | unsigned long flags; | |
469 | int i, count, nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
470 | int index = (dma_addr - io_tlb_start) >> IO_TLB_SHIFT; | |
bc40ac66 | 471 | phys_addr_t phys = io_tlb_orig_addr[index]; |
1da177e4 LT |
472 | |
473 | /* | |
474 | * First, sync the memory before unmapping the entry | |
475 | */ | |
bc40ac66 | 476 | if (phys && ((dir == DMA_FROM_DEVICE) || (dir == DMA_BIDIRECTIONAL))) |
fb05a379 | 477 | swiotlb_bounce(phys, dma_addr, size, DMA_FROM_DEVICE); |
1da177e4 LT |
478 | |
479 | /* | |
480 | * Return the buffer to the free list by setting the corresponding | |
481 | * entries to indicate the number of contigous entries available. | |
482 | * While returning the entries to the free list, we merge the entries | |
483 | * with slots below and above the pool being returned. | |
484 | */ | |
485 | spin_lock_irqsave(&io_tlb_lock, flags); | |
486 | { | |
487 | count = ((index + nslots) < ALIGN(index + 1, IO_TLB_SEGSIZE) ? | |
488 | io_tlb_list[index + nslots] : 0); | |
489 | /* | |
490 | * Step 1: return the slots to the free list, merging the | |
491 | * slots with superceeding slots | |
492 | */ | |
493 | for (i = index + nslots - 1; i >= index; i--) | |
494 | io_tlb_list[i] = ++count; | |
495 | /* | |
496 | * Step 2: merge the returned slots with the preceding slots, | |
497 | * if available (non zero) | |
498 | */ | |
499 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE -1) && io_tlb_list[i]; i--) | |
500 | io_tlb_list[i] = ++count; | |
501 | } | |
502 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
503 | } | |
504 | ||
505 | static void | |
de69e0f0 JL |
506 | sync_single(struct device *hwdev, char *dma_addr, size_t size, |
507 | int dir, int target) | |
1da177e4 | 508 | { |
bc40ac66 BB |
509 | int index = (dma_addr - io_tlb_start) >> IO_TLB_SHIFT; |
510 | phys_addr_t phys = io_tlb_orig_addr[index]; | |
511 | ||
512 | phys += ((unsigned long)dma_addr & ((1 << IO_TLB_SHIFT) - 1)); | |
df336d1c | 513 | |
de69e0f0 JL |
514 | switch (target) { |
515 | case SYNC_FOR_CPU: | |
516 | if (likely(dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
fb05a379 | 517 | swiotlb_bounce(phys, dma_addr, size, DMA_FROM_DEVICE); |
34814545 ES |
518 | else |
519 | BUG_ON(dir != DMA_TO_DEVICE); | |
de69e0f0 JL |
520 | break; |
521 | case SYNC_FOR_DEVICE: | |
522 | if (likely(dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
fb05a379 | 523 | swiotlb_bounce(phys, dma_addr, size, DMA_TO_DEVICE); |
34814545 ES |
524 | else |
525 | BUG_ON(dir != DMA_FROM_DEVICE); | |
de69e0f0 JL |
526 | break; |
527 | default: | |
1da177e4 | 528 | BUG(); |
de69e0f0 | 529 | } |
1da177e4 LT |
530 | } |
531 | ||
532 | void * | |
533 | swiotlb_alloc_coherent(struct device *hwdev, size_t size, | |
06a54497 | 534 | dma_addr_t *dma_handle, gfp_t flags) |
1da177e4 | 535 | { |
563aaf06 | 536 | dma_addr_t dev_addr; |
1da177e4 LT |
537 | void *ret; |
538 | int order = get_order(size); | |
284901a9 | 539 | u64 dma_mask = DMA_BIT_MASK(32); |
1e74f300 FT |
540 | |
541 | if (hwdev && hwdev->coherent_dma_mask) | |
542 | dma_mask = hwdev->coherent_dma_mask; | |
1da177e4 | 543 | |
25667d67 | 544 | ret = (void *)__get_free_pages(flags, order); |
70a7d3cc JF |
545 | if (ret && |
546 | !is_buffer_dma_capable(dma_mask, swiotlb_virt_to_bus(hwdev, ret), | |
547 | size)) { | |
1da177e4 LT |
548 | /* |
549 | * The allocated memory isn't reachable by the device. | |
1da177e4 LT |
550 | */ |
551 | free_pages((unsigned long) ret, order); | |
552 | ret = NULL; | |
553 | } | |
554 | if (!ret) { | |
555 | /* | |
556 | * We are either out of memory or the device can't DMA | |
ceb5ac32 BB |
557 | * to GFP_DMA memory; fall back on map_single(), which |
558 | * will grab memory from the lowest available address range. | |
1da177e4 | 559 | */ |
bc40ac66 | 560 | ret = map_single(hwdev, 0, size, DMA_FROM_DEVICE); |
9dfda12b | 561 | if (!ret) |
1da177e4 | 562 | return NULL; |
1da177e4 LT |
563 | } |
564 | ||
565 | memset(ret, 0, size); | |
70a7d3cc | 566 | dev_addr = swiotlb_virt_to_bus(hwdev, ret); |
1da177e4 LT |
567 | |
568 | /* Confirm address can be DMA'd by device */ | |
1e74f300 | 569 | if (!is_buffer_dma_capable(dma_mask, dev_addr, size)) { |
563aaf06 | 570 | printk("hwdev DMA mask = 0x%016Lx, dev_addr = 0x%016Lx\n", |
1e74f300 | 571 | (unsigned long long)dma_mask, |
563aaf06 | 572 | (unsigned long long)dev_addr); |
a2b89b59 FT |
573 | |
574 | /* DMA_TO_DEVICE to avoid memcpy in unmap_single */ | |
7fcebbd2 | 575 | do_unmap_single(hwdev, ret, size, DMA_TO_DEVICE); |
a2b89b59 | 576 | return NULL; |
1da177e4 LT |
577 | } |
578 | *dma_handle = dev_addr; | |
579 | return ret; | |
580 | } | |
874d6a95 | 581 | EXPORT_SYMBOL(swiotlb_alloc_coherent); |
1da177e4 LT |
582 | |
583 | void | |
584 | swiotlb_free_coherent(struct device *hwdev, size_t size, void *vaddr, | |
585 | dma_addr_t dma_handle) | |
586 | { | |
aa24886e | 587 | WARN_ON(irqs_disabled()); |
640aebfe | 588 | if (!is_swiotlb_buffer(vaddr)) |
1da177e4 LT |
589 | free_pages((unsigned long) vaddr, get_order(size)); |
590 | else | |
591 | /* DMA_TO_DEVICE to avoid memcpy in unmap_single */ | |
7fcebbd2 | 592 | do_unmap_single(hwdev, vaddr, size, DMA_TO_DEVICE); |
1da177e4 | 593 | } |
874d6a95 | 594 | EXPORT_SYMBOL(swiotlb_free_coherent); |
1da177e4 LT |
595 | |
596 | static void | |
597 | swiotlb_full(struct device *dev, size_t size, int dir, int do_panic) | |
598 | { | |
599 | /* | |
600 | * Ran out of IOMMU space for this operation. This is very bad. | |
601 | * Unfortunately the drivers cannot handle this operation properly. | |
17e5ad6c | 602 | * unless they check for dma_mapping_error (most don't) |
1da177e4 LT |
603 | * When the mapping is small enough return a static buffer to limit |
604 | * the damage, or panic when the transfer is too big. | |
605 | */ | |
563aaf06 | 606 | printk(KERN_ERR "DMA: Out of SW-IOMMU space for %zu bytes at " |
94b32486 | 607 | "device %s\n", size, dev ? dev_name(dev) : "?"); |
1da177e4 LT |
608 | |
609 | if (size > io_tlb_overflow && do_panic) { | |
17e5ad6c TL |
610 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) |
611 | panic("DMA: Memory would be corrupted\n"); | |
612 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL) | |
613 | panic("DMA: Random memory would be DMAed\n"); | |
1da177e4 LT |
614 | } |
615 | } | |
616 | ||
617 | /* | |
618 | * Map a single buffer of the indicated size for DMA in streaming mode. The | |
17e5ad6c | 619 | * physical address to use is returned. |
1da177e4 LT |
620 | * |
621 | * Once the device is given the dma address, the device owns this memory until | |
ceb5ac32 | 622 | * either swiotlb_unmap_page or swiotlb_dma_sync_single is performed. |
1da177e4 | 623 | */ |
f98eee8e FT |
624 | dma_addr_t swiotlb_map_page(struct device *dev, struct page *page, |
625 | unsigned long offset, size_t size, | |
626 | enum dma_data_direction dir, | |
627 | struct dma_attrs *attrs) | |
1da177e4 | 628 | { |
f98eee8e | 629 | phys_addr_t phys = page_to_phys(page) + offset; |
f98eee8e | 630 | dma_addr_t dev_addr = swiotlb_phys_to_bus(dev, phys); |
1da177e4 LT |
631 | void *map; |
632 | ||
34814545 | 633 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 634 | /* |
ceb5ac32 | 635 | * If the address happens to be in the device's DMA window, |
1da177e4 LT |
636 | * we can safely return the device addr and not worry about bounce |
637 | * buffering it. | |
638 | */ | |
cf56e3f2 | 639 | if (!address_needs_mapping(dev, dev_addr, size) && !swiotlb_force) |
1da177e4 LT |
640 | return dev_addr; |
641 | ||
642 | /* | |
643 | * Oh well, have to allocate and map a bounce buffer. | |
644 | */ | |
f98eee8e | 645 | map = map_single(dev, phys, size, dir); |
1da177e4 | 646 | if (!map) { |
f98eee8e | 647 | swiotlb_full(dev, size, dir, 1); |
1da177e4 LT |
648 | map = io_tlb_overflow_buffer; |
649 | } | |
650 | ||
f98eee8e | 651 | dev_addr = swiotlb_virt_to_bus(dev, map); |
1da177e4 LT |
652 | |
653 | /* | |
654 | * Ensure that the address returned is DMA'ble | |
655 | */ | |
f98eee8e | 656 | if (address_needs_mapping(dev, dev_addr, size)) |
1da177e4 LT |
657 | panic("map_single: bounce buffer is not DMA'ble"); |
658 | ||
659 | return dev_addr; | |
660 | } | |
f98eee8e | 661 | EXPORT_SYMBOL_GPL(swiotlb_map_page); |
1da177e4 | 662 | |
1da177e4 LT |
663 | /* |
664 | * Unmap a single streaming mode DMA translation. The dma_addr and size must | |
ceb5ac32 | 665 | * match what was provided for in a previous swiotlb_map_page call. All |
1da177e4 LT |
666 | * other usages are undefined. |
667 | * | |
668 | * After this call, reads by the cpu to the buffer are guaranteed to see | |
669 | * whatever the device wrote there. | |
670 | */ | |
7fcebbd2 BB |
671 | static void unmap_single(struct device *hwdev, dma_addr_t dev_addr, |
672 | size_t size, int dir) | |
1da177e4 | 673 | { |
42d7c5e3 | 674 | char *dma_addr = swiotlb_bus_to_virt(hwdev, dev_addr); |
1da177e4 | 675 | |
34814545 | 676 | BUG_ON(dir == DMA_NONE); |
7fcebbd2 BB |
677 | |
678 | if (is_swiotlb_buffer(dma_addr)) { | |
679 | do_unmap_single(hwdev, dma_addr, size, dir); | |
680 | return; | |
681 | } | |
682 | ||
683 | if (dir != DMA_FROM_DEVICE) | |
684 | return; | |
685 | ||
686 | dma_mark_clean(dma_addr, size); | |
687 | } | |
688 | ||
689 | void swiotlb_unmap_page(struct device *hwdev, dma_addr_t dev_addr, | |
690 | size_t size, enum dma_data_direction dir, | |
691 | struct dma_attrs *attrs) | |
692 | { | |
693 | unmap_single(hwdev, dev_addr, size, dir); | |
1da177e4 | 694 | } |
f98eee8e | 695 | EXPORT_SYMBOL_GPL(swiotlb_unmap_page); |
874d6a95 | 696 | |
1da177e4 LT |
697 | /* |
698 | * Make physical memory consistent for a single streaming mode DMA translation | |
699 | * after a transfer. | |
700 | * | |
ceb5ac32 | 701 | * If you perform a swiotlb_map_page() but wish to interrogate the buffer |
17e5ad6c TL |
702 | * using the cpu, yet do not wish to teardown the dma mapping, you must |
703 | * call this function before doing so. At the next point you give the dma | |
1da177e4 LT |
704 | * address back to the card, you must first perform a |
705 | * swiotlb_dma_sync_for_device, and then the device again owns the buffer | |
706 | */ | |
be6b0267 | 707 | static void |
8270f3f1 | 708 | swiotlb_sync_single(struct device *hwdev, dma_addr_t dev_addr, |
de69e0f0 | 709 | size_t size, int dir, int target) |
1da177e4 | 710 | { |
42d7c5e3 | 711 | char *dma_addr = swiotlb_bus_to_virt(hwdev, dev_addr); |
1da177e4 | 712 | |
34814545 | 713 | BUG_ON(dir == DMA_NONE); |
380d6878 BB |
714 | |
715 | if (is_swiotlb_buffer(dma_addr)) { | |
de69e0f0 | 716 | sync_single(hwdev, dma_addr, size, dir, target); |
380d6878 BB |
717 | return; |
718 | } | |
719 | ||
720 | if (dir != DMA_FROM_DEVICE) | |
721 | return; | |
722 | ||
723 | dma_mark_clean(dma_addr, size); | |
1da177e4 LT |
724 | } |
725 | ||
8270f3f1 JL |
726 | void |
727 | swiotlb_sync_single_for_cpu(struct device *hwdev, dma_addr_t dev_addr, | |
160c1d8e | 728 | size_t size, enum dma_data_direction dir) |
8270f3f1 | 729 | { |
de69e0f0 | 730 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_CPU); |
8270f3f1 | 731 | } |
874d6a95 | 732 | EXPORT_SYMBOL(swiotlb_sync_single_for_cpu); |
8270f3f1 | 733 | |
1da177e4 LT |
734 | void |
735 | swiotlb_sync_single_for_device(struct device *hwdev, dma_addr_t dev_addr, | |
160c1d8e | 736 | size_t size, enum dma_data_direction dir) |
1da177e4 | 737 | { |
de69e0f0 | 738 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_DEVICE); |
1da177e4 | 739 | } |
874d6a95 | 740 | EXPORT_SYMBOL(swiotlb_sync_single_for_device); |
1da177e4 | 741 | |
878a97cf JL |
742 | /* |
743 | * Same as above, but for a sub-range of the mapping. | |
744 | */ | |
be6b0267 | 745 | static void |
878a97cf | 746 | swiotlb_sync_single_range(struct device *hwdev, dma_addr_t dev_addr, |
de69e0f0 JL |
747 | unsigned long offset, size_t size, |
748 | int dir, int target) | |
878a97cf | 749 | { |
380d6878 | 750 | swiotlb_sync_single(hwdev, dev_addr + offset, size, dir, target); |
878a97cf JL |
751 | } |
752 | ||
753 | void | |
754 | swiotlb_sync_single_range_for_cpu(struct device *hwdev, dma_addr_t dev_addr, | |
160c1d8e FT |
755 | unsigned long offset, size_t size, |
756 | enum dma_data_direction dir) | |
878a97cf | 757 | { |
de69e0f0 JL |
758 | swiotlb_sync_single_range(hwdev, dev_addr, offset, size, dir, |
759 | SYNC_FOR_CPU); | |
878a97cf | 760 | } |
874d6a95 | 761 | EXPORT_SYMBOL_GPL(swiotlb_sync_single_range_for_cpu); |
878a97cf JL |
762 | |
763 | void | |
764 | swiotlb_sync_single_range_for_device(struct device *hwdev, dma_addr_t dev_addr, | |
160c1d8e FT |
765 | unsigned long offset, size_t size, |
766 | enum dma_data_direction dir) | |
878a97cf | 767 | { |
de69e0f0 JL |
768 | swiotlb_sync_single_range(hwdev, dev_addr, offset, size, dir, |
769 | SYNC_FOR_DEVICE); | |
878a97cf | 770 | } |
874d6a95 | 771 | EXPORT_SYMBOL_GPL(swiotlb_sync_single_range_for_device); |
878a97cf | 772 | |
1da177e4 LT |
773 | /* |
774 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
ceb5ac32 | 775 | * This is the scatter-gather version of the above swiotlb_map_page |
1da177e4 LT |
776 | * interface. Here the scatter gather list elements are each tagged with the |
777 | * appropriate dma address and length. They are obtained via | |
778 | * sg_dma_{address,length}(SG). | |
779 | * | |
780 | * NOTE: An implementation may be able to use a smaller number of | |
781 | * DMA address/length pairs than there are SG table elements. | |
782 | * (for example via virtual mapping capabilities) | |
783 | * The routine returns the number of addr/length pairs actually | |
784 | * used, at most nents. | |
785 | * | |
ceb5ac32 | 786 | * Device ownership issues as mentioned above for swiotlb_map_page are the |
1da177e4 LT |
787 | * same here. |
788 | */ | |
789 | int | |
309df0c5 | 790 | swiotlb_map_sg_attrs(struct device *hwdev, struct scatterlist *sgl, int nelems, |
160c1d8e | 791 | enum dma_data_direction dir, struct dma_attrs *attrs) |
1da177e4 | 792 | { |
dbfd49fe | 793 | struct scatterlist *sg; |
1da177e4 LT |
794 | int i; |
795 | ||
34814545 | 796 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 797 | |
dbfd49fe | 798 | for_each_sg(sgl, sg, nelems, i) { |
961d7d0e IC |
799 | phys_addr_t paddr = sg_phys(sg); |
800 | dma_addr_t dev_addr = swiotlb_phys_to_bus(hwdev, paddr); | |
bc40ac66 | 801 | |
cf56e3f2 | 802 | if (swiotlb_force || |
2797982e | 803 | address_needs_mapping(hwdev, dev_addr, sg->length)) { |
bc40ac66 BB |
804 | void *map = map_single(hwdev, sg_phys(sg), |
805 | sg->length, dir); | |
7e870233 | 806 | if (!map) { |
1da177e4 LT |
807 | /* Don't panic here, we expect map_sg users |
808 | to do proper error handling. */ | |
809 | swiotlb_full(hwdev, sg->length, dir, 0); | |
309df0c5 AK |
810 | swiotlb_unmap_sg_attrs(hwdev, sgl, i, dir, |
811 | attrs); | |
dbfd49fe | 812 | sgl[0].dma_length = 0; |
1da177e4 LT |
813 | return 0; |
814 | } | |
70a7d3cc | 815 | sg->dma_address = swiotlb_virt_to_bus(hwdev, map); |
1da177e4 LT |
816 | } else |
817 | sg->dma_address = dev_addr; | |
818 | sg->dma_length = sg->length; | |
819 | } | |
820 | return nelems; | |
821 | } | |
309df0c5 AK |
822 | EXPORT_SYMBOL(swiotlb_map_sg_attrs); |
823 | ||
824 | int | |
825 | swiotlb_map_sg(struct device *hwdev, struct scatterlist *sgl, int nelems, | |
826 | int dir) | |
827 | { | |
828 | return swiotlb_map_sg_attrs(hwdev, sgl, nelems, dir, NULL); | |
829 | } | |
874d6a95 | 830 | EXPORT_SYMBOL(swiotlb_map_sg); |
1da177e4 LT |
831 | |
832 | /* | |
833 | * Unmap a set of streaming mode DMA translations. Again, cpu read rules | |
ceb5ac32 | 834 | * concerning calls here are the same as for swiotlb_unmap_page() above. |
1da177e4 LT |
835 | */ |
836 | void | |
309df0c5 | 837 | swiotlb_unmap_sg_attrs(struct device *hwdev, struct scatterlist *sgl, |
160c1d8e | 838 | int nelems, enum dma_data_direction dir, struct dma_attrs *attrs) |
1da177e4 | 839 | { |
dbfd49fe | 840 | struct scatterlist *sg; |
1da177e4 LT |
841 | int i; |
842 | ||
34814545 | 843 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 844 | |
7fcebbd2 BB |
845 | for_each_sg(sgl, sg, nelems, i) |
846 | unmap_single(hwdev, sg->dma_address, sg->dma_length, dir); | |
847 | ||
1da177e4 | 848 | } |
309df0c5 AK |
849 | EXPORT_SYMBOL(swiotlb_unmap_sg_attrs); |
850 | ||
851 | void | |
852 | swiotlb_unmap_sg(struct device *hwdev, struct scatterlist *sgl, int nelems, | |
853 | int dir) | |
854 | { | |
855 | return swiotlb_unmap_sg_attrs(hwdev, sgl, nelems, dir, NULL); | |
856 | } | |
874d6a95 | 857 | EXPORT_SYMBOL(swiotlb_unmap_sg); |
1da177e4 LT |
858 | |
859 | /* | |
860 | * Make physical memory consistent for a set of streaming mode DMA translations | |
861 | * after a transfer. | |
862 | * | |
863 | * The same as swiotlb_sync_single_* but for a scatter-gather list, same rules | |
864 | * and usage. | |
865 | */ | |
be6b0267 | 866 | static void |
dbfd49fe | 867 | swiotlb_sync_sg(struct device *hwdev, struct scatterlist *sgl, |
de69e0f0 | 868 | int nelems, int dir, int target) |
1da177e4 | 869 | { |
dbfd49fe | 870 | struct scatterlist *sg; |
1da177e4 LT |
871 | int i; |
872 | ||
380d6878 BB |
873 | for_each_sg(sgl, sg, nelems, i) |
874 | swiotlb_sync_single(hwdev, sg->dma_address, | |
de69e0f0 | 875 | sg->dma_length, dir, target); |
1da177e4 LT |
876 | } |
877 | ||
8270f3f1 JL |
878 | void |
879 | swiotlb_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg, | |
160c1d8e | 880 | int nelems, enum dma_data_direction dir) |
8270f3f1 | 881 | { |
de69e0f0 | 882 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_CPU); |
8270f3f1 | 883 | } |
874d6a95 | 884 | EXPORT_SYMBOL(swiotlb_sync_sg_for_cpu); |
8270f3f1 | 885 | |
1da177e4 LT |
886 | void |
887 | swiotlb_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg, | |
160c1d8e | 888 | int nelems, enum dma_data_direction dir) |
1da177e4 | 889 | { |
de69e0f0 | 890 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_DEVICE); |
1da177e4 | 891 | } |
874d6a95 | 892 | EXPORT_SYMBOL(swiotlb_sync_sg_for_device); |
1da177e4 LT |
893 | |
894 | int | |
8d8bb39b | 895 | swiotlb_dma_mapping_error(struct device *hwdev, dma_addr_t dma_addr) |
1da177e4 | 896 | { |
70a7d3cc | 897 | return (dma_addr == swiotlb_virt_to_bus(hwdev, io_tlb_overflow_buffer)); |
1da177e4 | 898 | } |
874d6a95 | 899 | EXPORT_SYMBOL(swiotlb_dma_mapping_error); |
1da177e4 LT |
900 | |
901 | /* | |
17e5ad6c | 902 | * Return whether the given device DMA address mask can be supported |
1da177e4 | 903 | * properly. For example, if your device can only drive the low 24-bits |
17e5ad6c | 904 | * during bus mastering, then you would pass 0x00ffffff as the mask to |
1da177e4 LT |
905 | * this function. |
906 | */ | |
907 | int | |
563aaf06 | 908 | swiotlb_dma_supported(struct device *hwdev, u64 mask) |
1da177e4 | 909 | { |
70a7d3cc | 910 | return swiotlb_virt_to_bus(hwdev, io_tlb_end - 1) <= mask; |
1da177e4 | 911 | } |
1da177e4 | 912 | EXPORT_SYMBOL(swiotlb_dma_supported); |