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ba9703b0 XL |
1 | // This code is automatically generated. DO NOT MODIFY. |
2 | // | |
3 | // Instead, modify `crates/stdarch-gen/neon.spec` and run the following command to re-generate this file: | |
4 | // | |
5 | // ``` | |
6 | // OUT_DIR=`pwd`/crates/core_arch cargo run -p stdarch-gen -- crates/stdarch-gen/neon.spec | |
7 | // ``` | |
8 | use super::*; | |
9 | #[cfg(test)] | |
10 | use stdarch_test::assert_instr; | |
11 | ||
17df50a5 XL |
12 | /// Absolute difference between the arguments of Floating |
13 | #[inline] | |
14 | #[target_feature(enable = "neon")] | |
15 | #[cfg_attr(test, assert_instr(fabd))] | |
16 | pub unsafe fn vabd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
17 | #[allow(improper_ctypes)] | |
18 | extern "C" { | |
19 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fabd.v1f64")] | |
20 | fn vabd_f64_(a: float64x1_t, b: float64x1_t) -> float64x1_t; | |
21 | } | |
22 | vabd_f64_(a, b) | |
23 | } | |
24 | ||
25 | /// Absolute difference between the arguments of Floating | |
26 | #[inline] | |
27 | #[target_feature(enable = "neon")] | |
28 | #[cfg_attr(test, assert_instr(fabd))] | |
29 | pub unsafe fn vabdq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
30 | #[allow(improper_ctypes)] | |
31 | extern "C" { | |
32 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fabd.v2f64")] | |
33 | fn vabdq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; | |
34 | } | |
35 | vabdq_f64_(a, b) | |
36 | } | |
37 | ||
38 | /// Unsigned Absolute difference Long | |
39 | #[inline] | |
40 | #[target_feature(enable = "neon")] | |
41 | #[cfg_attr(test, assert_instr(uabdl))] | |
42 | pub unsafe fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { | |
43 | let c: uint8x8_t = simd_shuffle8!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); | |
44 | let d: uint8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
45 | simd_cast(vabd_u8(c, d)) | |
46 | } | |
47 | ||
48 | /// Unsigned Absolute difference Long | |
49 | #[inline] | |
50 | #[target_feature(enable = "neon")] | |
51 | #[cfg_attr(test, assert_instr(uabdl))] | |
52 | pub unsafe fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { | |
53 | let c: uint16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
54 | let d: uint16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
55 | simd_cast(vabd_u16(c, d)) | |
56 | } | |
57 | ||
58 | /// Unsigned Absolute difference Long | |
59 | #[inline] | |
60 | #[target_feature(enable = "neon")] | |
61 | #[cfg_attr(test, assert_instr(uabdl))] | |
62 | pub unsafe fn vabdl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { | |
63 | let c: uint32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
64 | let d: uint32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
65 | simd_cast(vabd_u32(c, d)) | |
66 | } | |
67 | ||
68 | /// Signed Absolute difference Long | |
69 | #[inline] | |
70 | #[target_feature(enable = "neon")] | |
71 | #[cfg_attr(test, assert_instr(sabdl))] | |
72 | pub unsafe fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { | |
73 | let c: int8x8_t = simd_shuffle8!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); | |
74 | let d: int8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
75 | let e: uint8x8_t = simd_cast(vabd_s8(c, d)); | |
76 | simd_cast(e) | |
77 | } | |
78 | ||
79 | /// Signed Absolute difference Long | |
80 | #[inline] | |
81 | #[target_feature(enable = "neon")] | |
82 | #[cfg_attr(test, assert_instr(sabdl))] | |
83 | pub unsafe fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { | |
84 | let c: int16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
85 | let d: int16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
86 | let e: uint16x4_t = simd_cast(vabd_s16(c, d)); | |
87 | simd_cast(e) | |
88 | } | |
89 | ||
90 | /// Signed Absolute difference Long | |
91 | #[inline] | |
92 | #[target_feature(enable = "neon")] | |
93 | #[cfg_attr(test, assert_instr(sabdl))] | |
94 | pub unsafe fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { | |
95 | let c: int32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
96 | let d: int32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
97 | let e: uint32x2_t = simd_cast(vabd_s32(c, d)); | |
98 | simd_cast(e) | |
99 | } | |
100 | ||
ba9703b0 XL |
101 | /// Compare bitwise Equal (vector) |
102 | #[inline] | |
103 | #[target_feature(enable = "neon")] | |
104 | #[cfg_attr(test, assert_instr(cmeq))] | |
105 | pub unsafe fn vceq_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { | |
106 | simd_eq(a, b) | |
107 | } | |
108 | ||
109 | /// Compare bitwise Equal (vector) | |
110 | #[inline] | |
111 | #[target_feature(enable = "neon")] | |
112 | #[cfg_attr(test, assert_instr(cmeq))] | |
113 | pub unsafe fn vceqq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
114 | simd_eq(a, b) | |
115 | } | |
116 | ||
117 | /// Compare bitwise Equal (vector) | |
118 | #[inline] | |
119 | #[target_feature(enable = "neon")] | |
120 | #[cfg_attr(test, assert_instr(cmeq))] | |
121 | pub unsafe fn vceq_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { | |
122 | simd_eq(a, b) | |
123 | } | |
124 | ||
125 | /// Compare bitwise Equal (vector) | |
126 | #[inline] | |
127 | #[target_feature(enable = "neon")] | |
128 | #[cfg_attr(test, assert_instr(cmeq))] | |
129 | pub unsafe fn vceqq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { | |
130 | simd_eq(a, b) | |
131 | } | |
132 | ||
133 | /// Compare bitwise Equal (vector) | |
134 | #[inline] | |
135 | #[target_feature(enable = "neon")] | |
136 | #[cfg_attr(test, assert_instr(cmeq))] | |
137 | pub unsafe fn vceq_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t { | |
138 | simd_eq(a, b) | |
139 | } | |
140 | ||
141 | /// Compare bitwise Equal (vector) | |
142 | #[inline] | |
143 | #[target_feature(enable = "neon")] | |
144 | #[cfg_attr(test, assert_instr(cmeq))] | |
145 | pub unsafe fn vceqq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t { | |
146 | simd_eq(a, b) | |
147 | } | |
148 | ||
149 | /// Floating-point compare equal | |
150 | #[inline] | |
151 | #[target_feature(enable = "neon")] | |
152 | #[cfg_attr(test, assert_instr(fcmeq))] | |
153 | pub unsafe fn vceq_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { | |
154 | simd_eq(a, b) | |
155 | } | |
156 | ||
157 | /// Floating-point compare equal | |
158 | #[inline] | |
159 | #[target_feature(enable = "neon")] | |
160 | #[cfg_attr(test, assert_instr(fcmeq))] | |
161 | pub unsafe fn vceqq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { | |
162 | simd_eq(a, b) | |
163 | } | |
164 | ||
17df50a5 XL |
165 | /// Signed compare bitwise equal to zero |
166 | #[inline] | |
167 | #[target_feature(enable = "neon")] | |
168 | #[cfg_attr(test, assert_instr(cmeq))] | |
169 | pub unsafe fn vceqz_s8(a: int8x8_t) -> uint8x8_t { | |
170 | let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
171 | simd_eq(a, transmute(b)) | |
172 | } | |
173 | ||
174 | /// Signed compare bitwise equal to zero | |
175 | #[inline] | |
176 | #[target_feature(enable = "neon")] | |
177 | #[cfg_attr(test, assert_instr(cmeq))] | |
178 | pub unsafe fn vceqzq_s8(a: int8x16_t) -> uint8x16_t { | |
179 | let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
180 | simd_eq(a, transmute(b)) | |
181 | } | |
182 | ||
183 | /// Signed compare bitwise equal to zero | |
184 | #[inline] | |
185 | #[target_feature(enable = "neon")] | |
186 | #[cfg_attr(test, assert_instr(cmeq))] | |
187 | pub unsafe fn vceqz_s16(a: int16x4_t) -> uint16x4_t { | |
188 | let b: i16x4 = i16x4::new(0, 0, 0, 0); | |
189 | simd_eq(a, transmute(b)) | |
190 | } | |
191 | ||
192 | /// Signed compare bitwise equal to zero | |
193 | #[inline] | |
194 | #[target_feature(enable = "neon")] | |
195 | #[cfg_attr(test, assert_instr(cmeq))] | |
196 | pub unsafe fn vceqzq_s16(a: int16x8_t) -> uint16x8_t { | |
197 | let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
198 | simd_eq(a, transmute(b)) | |
199 | } | |
200 | ||
201 | /// Signed compare bitwise equal to zero | |
202 | #[inline] | |
203 | #[target_feature(enable = "neon")] | |
204 | #[cfg_attr(test, assert_instr(cmeq))] | |
205 | pub unsafe fn vceqz_s32(a: int32x2_t) -> uint32x2_t { | |
206 | let b: i32x2 = i32x2::new(0, 0); | |
207 | simd_eq(a, transmute(b)) | |
208 | } | |
209 | ||
210 | /// Signed compare bitwise equal to zero | |
211 | #[inline] | |
212 | #[target_feature(enable = "neon")] | |
213 | #[cfg_attr(test, assert_instr(cmeq))] | |
214 | pub unsafe fn vceqzq_s32(a: int32x4_t) -> uint32x4_t { | |
215 | let b: i32x4 = i32x4::new(0, 0, 0, 0); | |
216 | simd_eq(a, transmute(b)) | |
217 | } | |
218 | ||
219 | /// Signed compare bitwise equal to zero | |
220 | #[inline] | |
221 | #[target_feature(enable = "neon")] | |
222 | #[cfg_attr(test, assert_instr(cmeq))] | |
223 | pub unsafe fn vceqz_s64(a: int64x1_t) -> uint64x1_t { | |
224 | let b: i64x1 = i64x1::new(0); | |
225 | simd_eq(a, transmute(b)) | |
226 | } | |
227 | ||
228 | /// Signed compare bitwise equal to zero | |
229 | #[inline] | |
230 | #[target_feature(enable = "neon")] | |
231 | #[cfg_attr(test, assert_instr(cmeq))] | |
232 | pub unsafe fn vceqzq_s64(a: int64x2_t) -> uint64x2_t { | |
233 | let b: i64x2 = i64x2::new(0, 0); | |
234 | simd_eq(a, transmute(b)) | |
235 | } | |
236 | ||
237 | /// Signed compare bitwise equal to zero | |
238 | #[inline] | |
239 | #[target_feature(enable = "neon")] | |
240 | #[cfg_attr(test, assert_instr(cmeq))] | |
241 | pub unsafe fn vceqz_p8(a: poly8x8_t) -> uint8x8_t { | |
242 | let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
243 | simd_eq(a, transmute(b)) | |
244 | } | |
245 | ||
246 | /// Signed compare bitwise equal to zero | |
247 | #[inline] | |
248 | #[target_feature(enable = "neon")] | |
249 | #[cfg_attr(test, assert_instr(cmeq))] | |
250 | pub unsafe fn vceqzq_p8(a: poly8x16_t) -> uint8x16_t { | |
251 | let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
252 | simd_eq(a, transmute(b)) | |
253 | } | |
254 | ||
255 | /// Signed compare bitwise equal to zero | |
256 | #[inline] | |
257 | #[target_feature(enable = "neon")] | |
258 | #[cfg_attr(test, assert_instr(cmeq))] | |
259 | pub unsafe fn vceqz_p64(a: poly64x1_t) -> uint64x1_t { | |
260 | let b: i64x1 = i64x1::new(0); | |
261 | simd_eq(a, transmute(b)) | |
262 | } | |
263 | ||
264 | /// Signed compare bitwise equal to zero | |
265 | #[inline] | |
266 | #[target_feature(enable = "neon")] | |
267 | #[cfg_attr(test, assert_instr(cmeq))] | |
268 | pub unsafe fn vceqzq_p64(a: poly64x2_t) -> uint64x2_t { | |
269 | let b: i64x2 = i64x2::new(0, 0); | |
270 | simd_eq(a, transmute(b)) | |
271 | } | |
272 | ||
273 | /// Unsigned compare bitwise equal to zero | |
274 | #[inline] | |
275 | #[target_feature(enable = "neon")] | |
276 | #[cfg_attr(test, assert_instr(cmeq))] | |
277 | pub unsafe fn vceqz_u8(a: uint8x8_t) -> uint8x8_t { | |
278 | let b: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
279 | simd_eq(a, transmute(b)) | |
280 | } | |
281 | ||
282 | /// Unsigned compare bitwise equal to zero | |
283 | #[inline] | |
284 | #[target_feature(enable = "neon")] | |
285 | #[cfg_attr(test, assert_instr(cmeq))] | |
286 | pub unsafe fn vceqzq_u8(a: uint8x16_t) -> uint8x16_t { | |
287 | let b: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
288 | simd_eq(a, transmute(b)) | |
289 | } | |
290 | ||
291 | /// Unsigned compare bitwise equal to zero | |
292 | #[inline] | |
293 | #[target_feature(enable = "neon")] | |
294 | #[cfg_attr(test, assert_instr(cmeq))] | |
295 | pub unsafe fn vceqz_u16(a: uint16x4_t) -> uint16x4_t { | |
296 | let b: u16x4 = u16x4::new(0, 0, 0, 0); | |
297 | simd_eq(a, transmute(b)) | |
298 | } | |
299 | ||
300 | /// Unsigned compare bitwise equal to zero | |
301 | #[inline] | |
302 | #[target_feature(enable = "neon")] | |
303 | #[cfg_attr(test, assert_instr(cmeq))] | |
304 | pub unsafe fn vceqzq_u16(a: uint16x8_t) -> uint16x8_t { | |
305 | let b: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
306 | simd_eq(a, transmute(b)) | |
307 | } | |
308 | ||
309 | /// Unsigned compare bitwise equal to zero | |
310 | #[inline] | |
311 | #[target_feature(enable = "neon")] | |
312 | #[cfg_attr(test, assert_instr(cmeq))] | |
313 | pub unsafe fn vceqz_u32(a: uint32x2_t) -> uint32x2_t { | |
314 | let b: u32x2 = u32x2::new(0, 0); | |
315 | simd_eq(a, transmute(b)) | |
316 | } | |
317 | ||
318 | /// Unsigned compare bitwise equal to zero | |
319 | #[inline] | |
320 | #[target_feature(enable = "neon")] | |
321 | #[cfg_attr(test, assert_instr(cmeq))] | |
322 | pub unsafe fn vceqzq_u32(a: uint32x4_t) -> uint32x4_t { | |
323 | let b: u32x4 = u32x4::new(0, 0, 0, 0); | |
324 | simd_eq(a, transmute(b)) | |
325 | } | |
326 | ||
327 | /// Unsigned compare bitwise equal to zero | |
328 | #[inline] | |
329 | #[target_feature(enable = "neon")] | |
330 | #[cfg_attr(test, assert_instr(cmeq))] | |
331 | pub unsafe fn vceqz_u64(a: uint64x1_t) -> uint64x1_t { | |
332 | let b: u64x1 = u64x1::new(0); | |
333 | simd_eq(a, transmute(b)) | |
334 | } | |
335 | ||
336 | /// Unsigned compare bitwise equal to zero | |
337 | #[inline] | |
338 | #[target_feature(enable = "neon")] | |
339 | #[cfg_attr(test, assert_instr(cmeq))] | |
340 | pub unsafe fn vceqzq_u64(a: uint64x2_t) -> uint64x2_t { | |
341 | let b: u64x2 = u64x2::new(0, 0); | |
342 | simd_eq(a, transmute(b)) | |
343 | } | |
344 | ||
345 | /// Floating-point compare bitwise equal to zero | |
346 | #[inline] | |
347 | #[target_feature(enable = "neon")] | |
348 | #[cfg_attr(test, assert_instr(fcmeq))] | |
349 | pub unsafe fn vceqz_f32(a: float32x2_t) -> uint32x2_t { | |
350 | let b: f32x2 = f32x2::new(0.0, 0.0); | |
351 | simd_eq(a, transmute(b)) | |
352 | } | |
353 | ||
354 | /// Floating-point compare bitwise equal to zero | |
355 | #[inline] | |
356 | #[target_feature(enable = "neon")] | |
357 | #[cfg_attr(test, assert_instr(fcmeq))] | |
358 | pub unsafe fn vceqzq_f32(a: float32x4_t) -> uint32x4_t { | |
359 | let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); | |
360 | simd_eq(a, transmute(b)) | |
361 | } | |
362 | ||
363 | /// Floating-point compare bitwise equal to zero | |
364 | #[inline] | |
365 | #[target_feature(enable = "neon")] | |
366 | #[cfg_attr(test, assert_instr(fcmeq))] | |
367 | pub unsafe fn vceqz_f64(a: float64x1_t) -> uint64x1_t { | |
368 | let b: f64 = 0.0; | |
369 | simd_eq(a, transmute(b)) | |
370 | } | |
371 | ||
372 | /// Floating-point compare bitwise equal to zero | |
373 | #[inline] | |
374 | #[target_feature(enable = "neon")] | |
375 | #[cfg_attr(test, assert_instr(fcmeq))] | |
376 | pub unsafe fn vceqzq_f64(a: float64x2_t) -> uint64x2_t { | |
377 | let b: f64x2 = f64x2::new(0.0, 0.0); | |
378 | simd_eq(a, transmute(b)) | |
379 | } | |
380 | ||
381 | /// Signed compare bitwise Test bits nonzero | |
382 | #[inline] | |
383 | #[target_feature(enable = "neon")] | |
384 | #[cfg_attr(test, assert_instr(cmtst))] | |
385 | pub unsafe fn vtst_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { | |
386 | let c: int64x1_t = simd_and(a, b); | |
387 | let d: i64x1 = i64x1::new(0); | |
388 | simd_ne(c, transmute(d)) | |
389 | } | |
390 | ||
391 | /// Signed compare bitwise Test bits nonzero | |
392 | #[inline] | |
393 | #[target_feature(enable = "neon")] | |
394 | #[cfg_attr(test, assert_instr(cmtst))] | |
395 | pub unsafe fn vtstq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { | |
396 | let c: int64x2_t = simd_and(a, b); | |
397 | let d: i64x2 = i64x2::new(0, 0); | |
398 | simd_ne(c, transmute(d)) | |
399 | } | |
400 | ||
401 | /// Signed compare bitwise Test bits nonzero | |
402 | #[inline] | |
403 | #[target_feature(enable = "neon")] | |
404 | #[cfg_attr(test, assert_instr(cmtst))] | |
405 | pub unsafe fn vtst_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t { | |
406 | let c: poly64x1_t = simd_and(a, b); | |
407 | let d: i64x1 = i64x1::new(0); | |
408 | simd_ne(c, transmute(d)) | |
409 | } | |
410 | ||
411 | /// Signed compare bitwise Test bits nonzero | |
412 | #[inline] | |
413 | #[target_feature(enable = "neon")] | |
414 | #[cfg_attr(test, assert_instr(cmtst))] | |
415 | pub unsafe fn vtstq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t { | |
416 | let c: poly64x2_t = simd_and(a, b); | |
417 | let d: i64x2 = i64x2::new(0, 0); | |
418 | simd_ne(c, transmute(d)) | |
419 | } | |
420 | ||
421 | /// Unsigned compare bitwise Test bits nonzero | |
422 | #[inline] | |
423 | #[target_feature(enable = "neon")] | |
424 | #[cfg_attr(test, assert_instr(cmtst))] | |
425 | pub unsafe fn vtst_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { | |
426 | let c: uint64x1_t = simd_and(a, b); | |
427 | let d: u64x1 = u64x1::new(0); | |
428 | simd_ne(c, transmute(d)) | |
429 | } | |
430 | ||
431 | /// Unsigned compare bitwise Test bits nonzero | |
432 | #[inline] | |
433 | #[target_feature(enable = "neon")] | |
434 | #[cfg_attr(test, assert_instr(cmtst))] | |
435 | pub unsafe fn vtstq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
436 | let c: uint64x2_t = simd_and(a, b); | |
437 | let d: u64x2 = u64x2::new(0, 0); | |
438 | simd_ne(c, transmute(d)) | |
439 | } | |
440 | ||
441 | /// Floating-point absolute value | |
442 | #[inline] | |
443 | #[target_feature(enable = "neon")] | |
444 | #[cfg_attr(test, assert_instr(fabs))] | |
445 | pub unsafe fn vabs_f64(a: float64x1_t) -> float64x1_t { | |
446 | simd_fabs(a) | |
447 | } | |
448 | ||
449 | /// Floating-point absolute value | |
450 | #[inline] | |
451 | #[target_feature(enable = "neon")] | |
452 | #[cfg_attr(test, assert_instr(fabs))] | |
453 | pub unsafe fn vabsq_f64(a: float64x2_t) -> float64x2_t { | |
454 | simd_fabs(a) | |
455 | } | |
456 | ||
ba9703b0 XL |
457 | /// Compare signed greater than |
458 | #[inline] | |
459 | #[target_feature(enable = "neon")] | |
460 | #[cfg_attr(test, assert_instr(cmgt))] | |
461 | pub unsafe fn vcgt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { | |
462 | simd_gt(a, b) | |
463 | } | |
464 | ||
465 | /// Compare signed greater than | |
466 | #[inline] | |
467 | #[target_feature(enable = "neon")] | |
468 | #[cfg_attr(test, assert_instr(cmgt))] | |
469 | pub unsafe fn vcgtq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { | |
470 | simd_gt(a, b) | |
471 | } | |
472 | ||
473 | /// Compare unsigned highe | |
474 | #[inline] | |
475 | #[target_feature(enable = "neon")] | |
476 | #[cfg_attr(test, assert_instr(cmhi))] | |
477 | pub unsafe fn vcgt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { | |
478 | simd_gt(a, b) | |
479 | } | |
480 | ||
481 | /// Compare unsigned highe | |
482 | #[inline] | |
483 | #[target_feature(enable = "neon")] | |
484 | #[cfg_attr(test, assert_instr(cmhi))] | |
485 | pub unsafe fn vcgtq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
486 | simd_gt(a, b) | |
487 | } | |
488 | ||
489 | /// Floating-point compare greater than | |
490 | #[inline] | |
491 | #[target_feature(enable = "neon")] | |
492 | #[cfg_attr(test, assert_instr(fcmgt))] | |
493 | pub unsafe fn vcgt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { | |
494 | simd_gt(a, b) | |
495 | } | |
496 | ||
497 | /// Floating-point compare greater than | |
498 | #[inline] | |
499 | #[target_feature(enable = "neon")] | |
500 | #[cfg_attr(test, assert_instr(fcmgt))] | |
501 | pub unsafe fn vcgtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { | |
502 | simd_gt(a, b) | |
503 | } | |
504 | ||
505 | /// Compare signed less than | |
506 | #[inline] | |
507 | #[target_feature(enable = "neon")] | |
508 | #[cfg_attr(test, assert_instr(cmgt))] | |
509 | pub unsafe fn vclt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { | |
510 | simd_lt(a, b) | |
511 | } | |
512 | ||
513 | /// Compare signed less than | |
514 | #[inline] | |
515 | #[target_feature(enable = "neon")] | |
516 | #[cfg_attr(test, assert_instr(cmgt))] | |
517 | pub unsafe fn vcltq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { | |
518 | simd_lt(a, b) | |
519 | } | |
520 | ||
521 | /// Compare unsigned less than | |
522 | #[inline] | |
523 | #[target_feature(enable = "neon")] | |
524 | #[cfg_attr(test, assert_instr(cmhi))] | |
525 | pub unsafe fn vclt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { | |
526 | simd_lt(a, b) | |
527 | } | |
528 | ||
529 | /// Compare unsigned less than | |
530 | #[inline] | |
531 | #[target_feature(enable = "neon")] | |
532 | #[cfg_attr(test, assert_instr(cmhi))] | |
533 | pub unsafe fn vcltq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
534 | simd_lt(a, b) | |
535 | } | |
536 | ||
537 | /// Floating-point compare less than | |
538 | #[inline] | |
539 | #[target_feature(enable = "neon")] | |
540 | #[cfg_attr(test, assert_instr(fcmgt))] | |
541 | pub unsafe fn vclt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { | |
542 | simd_lt(a, b) | |
543 | } | |
544 | ||
545 | /// Floating-point compare less than | |
546 | #[inline] | |
547 | #[target_feature(enable = "neon")] | |
548 | #[cfg_attr(test, assert_instr(fcmgt))] | |
549 | pub unsafe fn vcltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { | |
550 | simd_lt(a, b) | |
551 | } | |
552 | ||
553 | /// Compare signed less than or equal | |
554 | #[inline] | |
555 | #[target_feature(enable = "neon")] | |
556 | #[cfg_attr(test, assert_instr(cmge))] | |
557 | pub unsafe fn vcle_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { | |
558 | simd_le(a, b) | |
559 | } | |
560 | ||
561 | /// Compare signed less than or equal | |
562 | #[inline] | |
563 | #[target_feature(enable = "neon")] | |
564 | #[cfg_attr(test, assert_instr(cmge))] | |
565 | pub unsafe fn vcleq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { | |
566 | simd_le(a, b) | |
567 | } | |
568 | ||
569 | /// Compare unsigned less than or equal | |
570 | #[inline] | |
571 | #[target_feature(enable = "neon")] | |
572 | #[cfg_attr(test, assert_instr(cmhs))] | |
573 | pub unsafe fn vcle_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { | |
574 | simd_le(a, b) | |
575 | } | |
576 | ||
577 | /// Compare unsigned less than or equal | |
578 | #[inline] | |
579 | #[target_feature(enable = "neon")] | |
580 | #[cfg_attr(test, assert_instr(cmhs))] | |
581 | pub unsafe fn vcleq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
582 | simd_le(a, b) | |
583 | } | |
584 | ||
585 | /// Floating-point compare less than or equal | |
586 | #[inline] | |
587 | #[target_feature(enable = "neon")] | |
588 | #[cfg_attr(test, assert_instr(fcmge))] | |
589 | pub unsafe fn vcle_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { | |
590 | simd_le(a, b) | |
591 | } | |
592 | ||
593 | /// Floating-point compare less than or equal | |
594 | #[inline] | |
595 | #[target_feature(enable = "neon")] | |
596 | #[cfg_attr(test, assert_instr(fcmge))] | |
597 | pub unsafe fn vcleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { | |
598 | simd_le(a, b) | |
599 | } | |
600 | ||
601 | /// Compare signed greater than or equal | |
602 | #[inline] | |
603 | #[target_feature(enable = "neon")] | |
604 | #[cfg_attr(test, assert_instr(cmge))] | |
605 | pub unsafe fn vcge_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { | |
606 | simd_ge(a, b) | |
607 | } | |
608 | ||
609 | /// Compare signed greater than or equal | |
610 | #[inline] | |
611 | #[target_feature(enable = "neon")] | |
612 | #[cfg_attr(test, assert_instr(cmge))] | |
613 | pub unsafe fn vcgeq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { | |
614 | simd_ge(a, b) | |
615 | } | |
616 | ||
617 | /// Compare unsigned greater than or equal | |
618 | #[inline] | |
619 | #[target_feature(enable = "neon")] | |
620 | #[cfg_attr(test, assert_instr(cmhs))] | |
621 | pub unsafe fn vcge_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { | |
622 | simd_ge(a, b) | |
623 | } | |
624 | ||
625 | /// Compare unsigned greater than or equal | |
626 | #[inline] | |
627 | #[target_feature(enable = "neon")] | |
628 | #[cfg_attr(test, assert_instr(cmhs))] | |
629 | pub unsafe fn vcgeq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
630 | simd_ge(a, b) | |
631 | } | |
632 | ||
633 | /// Floating-point compare greater than or equal | |
634 | #[inline] | |
635 | #[target_feature(enable = "neon")] | |
636 | #[cfg_attr(test, assert_instr(fcmge))] | |
637 | pub unsafe fn vcge_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { | |
638 | simd_ge(a, b) | |
639 | } | |
640 | ||
641 | /// Floating-point compare greater than or equal | |
642 | #[inline] | |
643 | #[target_feature(enable = "neon")] | |
644 | #[cfg_attr(test, assert_instr(fcmge))] | |
645 | pub unsafe fn vcgeq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { | |
646 | simd_ge(a, b) | |
647 | } | |
648 | ||
17df50a5 | 649 | /// Compare signed greater than or equal to zero |
ba9703b0 XL |
650 | #[inline] |
651 | #[target_feature(enable = "neon")] | |
17df50a5 XL |
652 | #[cfg_attr(test, assert_instr(cmge))] |
653 | pub unsafe fn vcgez_s8(a: int8x8_t) -> uint8x8_t { | |
654 | let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
655 | simd_ge(a, transmute(b)) | |
ba9703b0 XL |
656 | } |
657 | ||
17df50a5 | 658 | /// Compare signed greater than or equal to zero |
ba9703b0 XL |
659 | #[inline] |
660 | #[target_feature(enable = "neon")] | |
17df50a5 XL |
661 | #[cfg_attr(test, assert_instr(cmge))] |
662 | pub unsafe fn vcgezq_s8(a: int8x16_t) -> uint8x16_t { | |
663 | let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
664 | simd_ge(a, transmute(b)) | |
ba9703b0 XL |
665 | } |
666 | ||
17df50a5 | 667 | /// Compare signed greater than or equal to zero |
ba9703b0 XL |
668 | #[inline] |
669 | #[target_feature(enable = "neon")] | |
17df50a5 XL |
670 | #[cfg_attr(test, assert_instr(cmge))] |
671 | pub unsafe fn vcgez_s16(a: int16x4_t) -> uint16x4_t { | |
672 | let b: i16x4 = i16x4::new(0, 0, 0, 0); | |
673 | simd_ge(a, transmute(b)) | |
ba9703b0 XL |
674 | } |
675 | ||
17df50a5 | 676 | /// Compare signed greater than or equal to zero |
ba9703b0 XL |
677 | #[inline] |
678 | #[target_feature(enable = "neon")] | |
17df50a5 XL |
679 | #[cfg_attr(test, assert_instr(cmge))] |
680 | pub unsafe fn vcgezq_s16(a: int16x8_t) -> uint16x8_t { | |
681 | let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
682 | simd_ge(a, transmute(b)) | |
ba9703b0 XL |
683 | } |
684 | ||
17df50a5 | 685 | /// Compare signed greater than or equal to zero |
fc512014 XL |
686 | #[inline] |
687 | #[target_feature(enable = "neon")] | |
17df50a5 XL |
688 | #[cfg_attr(test, assert_instr(cmge))] |
689 | pub unsafe fn vcgez_s32(a: int32x2_t) -> uint32x2_t { | |
690 | let b: i32x2 = i32x2::new(0, 0); | |
691 | simd_ge(a, transmute(b)) | |
fc512014 XL |
692 | } |
693 | ||
17df50a5 | 694 | /// Compare signed greater than or equal to zero |
fc512014 XL |
695 | #[inline] |
696 | #[target_feature(enable = "neon")] | |
17df50a5 XL |
697 | #[cfg_attr(test, assert_instr(cmge))] |
698 | pub unsafe fn vcgezq_s32(a: int32x4_t) -> uint32x4_t { | |
699 | let b: i32x4 = i32x4::new(0, 0, 0, 0); | |
700 | simd_ge(a, transmute(b)) | |
fc512014 XL |
701 | } |
702 | ||
17df50a5 | 703 | /// Compare signed greater than or equal to zero |
fc512014 XL |
704 | #[inline] |
705 | #[target_feature(enable = "neon")] | |
17df50a5 XL |
706 | #[cfg_attr(test, assert_instr(cmge))] |
707 | pub unsafe fn vcgez_s64(a: int64x1_t) -> uint64x1_t { | |
708 | let b: i64x1 = i64x1::new(0); | |
709 | simd_ge(a, transmute(b)) | |
fc512014 XL |
710 | } |
711 | ||
17df50a5 | 712 | /// Compare signed greater than or equal to zero |
fc512014 XL |
713 | #[inline] |
714 | #[target_feature(enable = "neon")] | |
17df50a5 XL |
715 | #[cfg_attr(test, assert_instr(cmge))] |
716 | pub unsafe fn vcgezq_s64(a: int64x2_t) -> uint64x2_t { | |
717 | let b: i64x2 = i64x2::new(0, 0); | |
718 | simd_ge(a, transmute(b)) | |
fc512014 XL |
719 | } |
720 | ||
17df50a5 XL |
721 | /// Floating-point compare greater than or equal to zero |
722 | #[inline] | |
723 | #[target_feature(enable = "neon")] | |
724 | #[cfg_attr(test, assert_instr(fcmge))] | |
725 | pub unsafe fn vcgez_f32(a: float32x2_t) -> uint32x2_t { | |
726 | let b: f32x2 = f32x2::new(0.0, 0.0); | |
727 | simd_ge(a, transmute(b)) | |
728 | } | |
729 | ||
730 | /// Floating-point compare greater than or equal to zero | |
731 | #[inline] | |
732 | #[target_feature(enable = "neon")] | |
733 | #[cfg_attr(test, assert_instr(fcmge))] | |
734 | pub unsafe fn vcgezq_f32(a: float32x4_t) -> uint32x4_t { | |
735 | let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); | |
736 | simd_ge(a, transmute(b)) | |
737 | } | |
738 | ||
739 | /// Floating-point compare greater than or equal to zero | |
740 | #[inline] | |
741 | #[target_feature(enable = "neon")] | |
742 | #[cfg_attr(test, assert_instr(fcmge))] | |
743 | pub unsafe fn vcgez_f64(a: float64x1_t) -> uint64x1_t { | |
744 | let b: f64 = 0.0; | |
745 | simd_ge(a, transmute(b)) | |
746 | } | |
747 | ||
748 | /// Floating-point compare greater than or equal to zero | |
749 | #[inline] | |
750 | #[target_feature(enable = "neon")] | |
751 | #[cfg_attr(test, assert_instr(fcmge))] | |
752 | pub unsafe fn vcgezq_f64(a: float64x2_t) -> uint64x2_t { | |
753 | let b: f64x2 = f64x2::new(0.0, 0.0); | |
754 | simd_ge(a, transmute(b)) | |
755 | } | |
756 | ||
757 | /// Compare signed greater than zero | |
758 | #[inline] | |
759 | #[target_feature(enable = "neon")] | |
760 | #[cfg_attr(test, assert_instr(cmgt))] | |
761 | pub unsafe fn vcgtz_s8(a: int8x8_t) -> uint8x8_t { | |
762 | let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
763 | simd_gt(a, transmute(b)) | |
764 | } | |
765 | ||
766 | /// Compare signed greater than zero | |
767 | #[inline] | |
768 | #[target_feature(enable = "neon")] | |
769 | #[cfg_attr(test, assert_instr(cmgt))] | |
770 | pub unsafe fn vcgtzq_s8(a: int8x16_t) -> uint8x16_t { | |
771 | let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
772 | simd_gt(a, transmute(b)) | |
773 | } | |
774 | ||
775 | /// Compare signed greater than zero | |
776 | #[inline] | |
777 | #[target_feature(enable = "neon")] | |
778 | #[cfg_attr(test, assert_instr(cmgt))] | |
779 | pub unsafe fn vcgtz_s16(a: int16x4_t) -> uint16x4_t { | |
780 | let b: i16x4 = i16x4::new(0, 0, 0, 0); | |
781 | simd_gt(a, transmute(b)) | |
782 | } | |
783 | ||
784 | /// Compare signed greater than zero | |
785 | #[inline] | |
786 | #[target_feature(enable = "neon")] | |
787 | #[cfg_attr(test, assert_instr(cmgt))] | |
788 | pub unsafe fn vcgtzq_s16(a: int16x8_t) -> uint16x8_t { | |
789 | let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
790 | simd_gt(a, transmute(b)) | |
791 | } | |
792 | ||
793 | /// Compare signed greater than zero | |
794 | #[inline] | |
795 | #[target_feature(enable = "neon")] | |
796 | #[cfg_attr(test, assert_instr(cmgt))] | |
797 | pub unsafe fn vcgtz_s32(a: int32x2_t) -> uint32x2_t { | |
798 | let b: i32x2 = i32x2::new(0, 0); | |
799 | simd_gt(a, transmute(b)) | |
800 | } | |
801 | ||
802 | /// Compare signed greater than zero | |
803 | #[inline] | |
804 | #[target_feature(enable = "neon")] | |
805 | #[cfg_attr(test, assert_instr(cmgt))] | |
806 | pub unsafe fn vcgtzq_s32(a: int32x4_t) -> uint32x4_t { | |
807 | let b: i32x4 = i32x4::new(0, 0, 0, 0); | |
808 | simd_gt(a, transmute(b)) | |
809 | } | |
810 | ||
811 | /// Compare signed greater than zero | |
812 | #[inline] | |
813 | #[target_feature(enable = "neon")] | |
814 | #[cfg_attr(test, assert_instr(cmgt))] | |
815 | pub unsafe fn vcgtz_s64(a: int64x1_t) -> uint64x1_t { | |
816 | let b: i64x1 = i64x1::new(0); | |
817 | simd_gt(a, transmute(b)) | |
818 | } | |
819 | ||
820 | /// Compare signed greater than zero | |
821 | #[inline] | |
822 | #[target_feature(enable = "neon")] | |
823 | #[cfg_attr(test, assert_instr(cmgt))] | |
824 | pub unsafe fn vcgtzq_s64(a: int64x2_t) -> uint64x2_t { | |
825 | let b: i64x2 = i64x2::new(0, 0); | |
826 | simd_gt(a, transmute(b)) | |
827 | } | |
828 | ||
829 | /// Floating-point compare greater than zero | |
830 | #[inline] | |
831 | #[target_feature(enable = "neon")] | |
832 | #[cfg_attr(test, assert_instr(fcmgt))] | |
833 | pub unsafe fn vcgtz_f32(a: float32x2_t) -> uint32x2_t { | |
834 | let b: f32x2 = f32x2::new(0.0, 0.0); | |
835 | simd_gt(a, transmute(b)) | |
836 | } | |
837 | ||
838 | /// Floating-point compare greater than zero | |
839 | #[inline] | |
840 | #[target_feature(enable = "neon")] | |
841 | #[cfg_attr(test, assert_instr(fcmgt))] | |
842 | pub unsafe fn vcgtzq_f32(a: float32x4_t) -> uint32x4_t { | |
843 | let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); | |
844 | simd_gt(a, transmute(b)) | |
845 | } | |
846 | ||
847 | /// Floating-point compare greater than zero | |
848 | #[inline] | |
849 | #[target_feature(enable = "neon")] | |
850 | #[cfg_attr(test, assert_instr(fcmgt))] | |
851 | pub unsafe fn vcgtz_f64(a: float64x1_t) -> uint64x1_t { | |
852 | let b: f64 = 0.0; | |
853 | simd_gt(a, transmute(b)) | |
854 | } | |
855 | ||
856 | /// Floating-point compare greater than zero | |
857 | #[inline] | |
858 | #[target_feature(enable = "neon")] | |
859 | #[cfg_attr(test, assert_instr(fcmgt))] | |
860 | pub unsafe fn vcgtzq_f64(a: float64x2_t) -> uint64x2_t { | |
861 | let b: f64x2 = f64x2::new(0.0, 0.0); | |
862 | simd_gt(a, transmute(b)) | |
863 | } | |
864 | ||
865 | /// Compare signed less than or equal to zero | |
866 | #[inline] | |
867 | #[target_feature(enable = "neon")] | |
868 | #[cfg_attr(test, assert_instr(cmgt))] | |
869 | pub unsafe fn vclez_s8(a: int8x8_t) -> uint8x8_t { | |
870 | let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
871 | simd_le(a, transmute(b)) | |
872 | } | |
873 | ||
874 | /// Compare signed less than or equal to zero | |
875 | #[inline] | |
876 | #[target_feature(enable = "neon")] | |
877 | #[cfg_attr(test, assert_instr(cmgt))] | |
878 | pub unsafe fn vclezq_s8(a: int8x16_t) -> uint8x16_t { | |
879 | let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
880 | simd_le(a, transmute(b)) | |
881 | } | |
882 | ||
883 | /// Compare signed less than or equal to zero | |
884 | #[inline] | |
885 | #[target_feature(enable = "neon")] | |
886 | #[cfg_attr(test, assert_instr(cmgt))] | |
887 | pub unsafe fn vclez_s16(a: int16x4_t) -> uint16x4_t { | |
888 | let b: i16x4 = i16x4::new(0, 0, 0, 0); | |
889 | simd_le(a, transmute(b)) | |
890 | } | |
891 | ||
892 | /// Compare signed less than or equal to zero | |
893 | #[inline] | |
894 | #[target_feature(enable = "neon")] | |
895 | #[cfg_attr(test, assert_instr(cmgt))] | |
896 | pub unsafe fn vclezq_s16(a: int16x8_t) -> uint16x8_t { | |
897 | let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
898 | simd_le(a, transmute(b)) | |
899 | } | |
900 | ||
901 | /// Compare signed less than or equal to zero | |
902 | #[inline] | |
903 | #[target_feature(enable = "neon")] | |
904 | #[cfg_attr(test, assert_instr(cmgt))] | |
905 | pub unsafe fn vclez_s32(a: int32x2_t) -> uint32x2_t { | |
906 | let b: i32x2 = i32x2::new(0, 0); | |
907 | simd_le(a, transmute(b)) | |
908 | } | |
909 | ||
910 | /// Compare signed less than or equal to zero | |
911 | #[inline] | |
912 | #[target_feature(enable = "neon")] | |
913 | #[cfg_attr(test, assert_instr(cmgt))] | |
914 | pub unsafe fn vclezq_s32(a: int32x4_t) -> uint32x4_t { | |
915 | let b: i32x4 = i32x4::new(0, 0, 0, 0); | |
916 | simd_le(a, transmute(b)) | |
917 | } | |
918 | ||
919 | /// Compare signed less than or equal to zero | |
920 | #[inline] | |
921 | #[target_feature(enable = "neon")] | |
922 | #[cfg_attr(test, assert_instr(cmgt))] | |
923 | pub unsafe fn vclez_s64(a: int64x1_t) -> uint64x1_t { | |
924 | let b: i64x1 = i64x1::new(0); | |
925 | simd_le(a, transmute(b)) | |
926 | } | |
927 | ||
928 | /// Compare signed less than or equal to zero | |
929 | #[inline] | |
930 | #[target_feature(enable = "neon")] | |
931 | #[cfg_attr(test, assert_instr(cmgt))] | |
932 | pub unsafe fn vclezq_s64(a: int64x2_t) -> uint64x2_t { | |
933 | let b: i64x2 = i64x2::new(0, 0); | |
934 | simd_le(a, transmute(b)) | |
935 | } | |
936 | ||
937 | /// Floating-point compare less than or equal to zero | |
938 | #[inline] | |
939 | #[target_feature(enable = "neon")] | |
940 | #[cfg_attr(test, assert_instr(fcmle))] | |
941 | pub unsafe fn vclez_f32(a: float32x2_t) -> uint32x2_t { | |
942 | let b: f32x2 = f32x2::new(0.0, 0.0); | |
943 | simd_le(a, transmute(b)) | |
944 | } | |
945 | ||
946 | /// Floating-point compare less than or equal to zero | |
947 | #[inline] | |
948 | #[target_feature(enable = "neon")] | |
949 | #[cfg_attr(test, assert_instr(fcmle))] | |
950 | pub unsafe fn vclezq_f32(a: float32x4_t) -> uint32x4_t { | |
951 | let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); | |
952 | simd_le(a, transmute(b)) | |
953 | } | |
954 | ||
955 | /// Floating-point compare less than or equal to zero | |
956 | #[inline] | |
957 | #[target_feature(enable = "neon")] | |
958 | #[cfg_attr(test, assert_instr(fcmle))] | |
959 | pub unsafe fn vclez_f64(a: float64x1_t) -> uint64x1_t { | |
960 | let b: f64 = 0.0; | |
961 | simd_le(a, transmute(b)) | |
962 | } | |
963 | ||
964 | /// Floating-point compare less than or equal to zero | |
965 | #[inline] | |
966 | #[target_feature(enable = "neon")] | |
967 | #[cfg_attr(test, assert_instr(fcmle))] | |
968 | pub unsafe fn vclezq_f64(a: float64x2_t) -> uint64x2_t { | |
969 | let b: f64x2 = f64x2::new(0.0, 0.0); | |
970 | simd_le(a, transmute(b)) | |
971 | } | |
972 | ||
973 | /// Compare signed less than zero | |
974 | #[inline] | |
975 | #[target_feature(enable = "neon")] | |
976 | #[cfg_attr(test, assert_instr(sshr))] | |
977 | pub unsafe fn vcltz_s8(a: int8x8_t) -> uint8x8_t { | |
978 | let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
979 | simd_lt(a, transmute(b)) | |
980 | } | |
981 | ||
982 | /// Compare signed less than zero | |
983 | #[inline] | |
984 | #[target_feature(enable = "neon")] | |
985 | #[cfg_attr(test, assert_instr(sshr))] | |
986 | pub unsafe fn vcltzq_s8(a: int8x16_t) -> uint8x16_t { | |
987 | let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
988 | simd_lt(a, transmute(b)) | |
989 | } | |
990 | ||
991 | /// Compare signed less than zero | |
992 | #[inline] | |
993 | #[target_feature(enable = "neon")] | |
994 | #[cfg_attr(test, assert_instr(sshr))] | |
995 | pub unsafe fn vcltz_s16(a: int16x4_t) -> uint16x4_t { | |
996 | let b: i16x4 = i16x4::new(0, 0, 0, 0); | |
997 | simd_lt(a, transmute(b)) | |
998 | } | |
999 | ||
1000 | /// Compare signed less than zero | |
1001 | #[inline] | |
1002 | #[target_feature(enable = "neon")] | |
1003 | #[cfg_attr(test, assert_instr(sshr))] | |
1004 | pub unsafe fn vcltzq_s16(a: int16x8_t) -> uint16x8_t { | |
1005 | let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
1006 | simd_lt(a, transmute(b)) | |
1007 | } | |
1008 | ||
1009 | /// Compare signed less than zero | |
1010 | #[inline] | |
1011 | #[target_feature(enable = "neon")] | |
1012 | #[cfg_attr(test, assert_instr(sshr))] | |
1013 | pub unsafe fn vcltz_s32(a: int32x2_t) -> uint32x2_t { | |
1014 | let b: i32x2 = i32x2::new(0, 0); | |
1015 | simd_lt(a, transmute(b)) | |
1016 | } | |
1017 | ||
1018 | /// Compare signed less than zero | |
1019 | #[inline] | |
1020 | #[target_feature(enable = "neon")] | |
1021 | #[cfg_attr(test, assert_instr(sshr))] | |
1022 | pub unsafe fn vcltzq_s32(a: int32x4_t) -> uint32x4_t { | |
1023 | let b: i32x4 = i32x4::new(0, 0, 0, 0); | |
1024 | simd_lt(a, transmute(b)) | |
1025 | } | |
1026 | ||
1027 | /// Compare signed less than zero | |
1028 | #[inline] | |
1029 | #[target_feature(enable = "neon")] | |
1030 | #[cfg_attr(test, assert_instr(sshr))] | |
1031 | pub unsafe fn vcltz_s64(a: int64x1_t) -> uint64x1_t { | |
1032 | let b: i64x1 = i64x1::new(0); | |
1033 | simd_lt(a, transmute(b)) | |
1034 | } | |
1035 | ||
1036 | /// Compare signed less than zero | |
1037 | #[inline] | |
1038 | #[target_feature(enable = "neon")] | |
1039 | #[cfg_attr(test, assert_instr(sshr))] | |
1040 | pub unsafe fn vcltzq_s64(a: int64x2_t) -> uint64x2_t { | |
1041 | let b: i64x2 = i64x2::new(0, 0); | |
1042 | simd_lt(a, transmute(b)) | |
1043 | } | |
1044 | ||
1045 | /// Floating-point compare less than zero | |
1046 | #[inline] | |
1047 | #[target_feature(enable = "neon")] | |
1048 | #[cfg_attr(test, assert_instr(fcmlt))] | |
1049 | pub unsafe fn vcltz_f32(a: float32x2_t) -> uint32x2_t { | |
1050 | let b: f32x2 = f32x2::new(0.0, 0.0); | |
1051 | simd_lt(a, transmute(b)) | |
1052 | } | |
1053 | ||
1054 | /// Floating-point compare less than zero | |
1055 | #[inline] | |
1056 | #[target_feature(enable = "neon")] | |
1057 | #[cfg_attr(test, assert_instr(fcmlt))] | |
1058 | pub unsafe fn vcltzq_f32(a: float32x4_t) -> uint32x4_t { | |
1059 | let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); | |
1060 | simd_lt(a, transmute(b)) | |
1061 | } | |
1062 | ||
1063 | /// Floating-point compare less than zero | |
1064 | #[inline] | |
1065 | #[target_feature(enable = "neon")] | |
1066 | #[cfg_attr(test, assert_instr(fcmlt))] | |
1067 | pub unsafe fn vcltz_f64(a: float64x1_t) -> uint64x1_t { | |
1068 | let b: f64 = 0.0; | |
1069 | simd_lt(a, transmute(b)) | |
1070 | } | |
1071 | ||
1072 | /// Floating-point compare less than zero | |
1073 | #[inline] | |
1074 | #[target_feature(enable = "neon")] | |
1075 | #[cfg_attr(test, assert_instr(fcmlt))] | |
1076 | pub unsafe fn vcltzq_f64(a: float64x2_t) -> uint64x2_t { | |
1077 | let b: f64x2 = f64x2::new(0.0, 0.0); | |
1078 | simd_lt(a, transmute(b)) | |
1079 | } | |
1080 | ||
1081 | /// Floating-point absolute compare greater than | |
1082 | #[inline] | |
1083 | #[target_feature(enable = "neon")] | |
1084 | #[cfg_attr(test, assert_instr(facgt))] | |
1085 | pub unsafe fn vcagt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { | |
1086 | #[allow(improper_ctypes)] | |
1087 | extern "C" { | |
1088 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.facgt.v1i64.v1f64")] | |
1089 | fn vcagt_f64_(a: float64x1_t, b: float64x1_t) -> uint64x1_t; | |
1090 | } | |
1091 | vcagt_f64_(a, b) | |
1092 | } | |
1093 | ||
1094 | /// Floating-point absolute compare greater than | |
1095 | #[inline] | |
1096 | #[target_feature(enable = "neon")] | |
1097 | #[cfg_attr(test, assert_instr(facgt))] | |
1098 | pub unsafe fn vcagtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { | |
1099 | #[allow(improper_ctypes)] | |
1100 | extern "C" { | |
1101 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.facgt.v2i64.v2f64")] | |
1102 | fn vcagtq_f64_(a: float64x2_t, b: float64x2_t) -> uint64x2_t; | |
1103 | } | |
1104 | vcagtq_f64_(a, b) | |
1105 | } | |
1106 | ||
1107 | /// Floating-point absolute compare greater than or equal | |
1108 | #[inline] | |
1109 | #[target_feature(enable = "neon")] | |
1110 | #[cfg_attr(test, assert_instr(facge))] | |
1111 | pub unsafe fn vcage_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { | |
1112 | #[allow(improper_ctypes)] | |
1113 | extern "C" { | |
1114 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.facge.v1i64.v1f64")] | |
1115 | fn vcage_f64_(a: float64x1_t, b: float64x1_t) -> uint64x1_t; | |
1116 | } | |
1117 | vcage_f64_(a, b) | |
1118 | } | |
1119 | ||
1120 | /// Floating-point absolute compare greater than or equal | |
1121 | #[inline] | |
1122 | #[target_feature(enable = "neon")] | |
1123 | #[cfg_attr(test, assert_instr(facge))] | |
1124 | pub unsafe fn vcageq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { | |
1125 | #[allow(improper_ctypes)] | |
1126 | extern "C" { | |
1127 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.facge.v2i64.v2f64")] | |
1128 | fn vcageq_f64_(a: float64x2_t, b: float64x2_t) -> uint64x2_t; | |
1129 | } | |
1130 | vcageq_f64_(a, b) | |
1131 | } | |
1132 | ||
1133 | /// Floating-point absolute compare less than | |
1134 | #[inline] | |
1135 | #[target_feature(enable = "neon")] | |
1136 | #[cfg_attr(test, assert_instr(facgt))] | |
1137 | pub unsafe fn vcalt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { | |
1138 | vcagt_f64(b, a) | |
1139 | } | |
1140 | ||
1141 | /// Floating-point absolute compare less than | |
1142 | #[inline] | |
1143 | #[target_feature(enable = "neon")] | |
1144 | #[cfg_attr(test, assert_instr(facgt))] | |
1145 | pub unsafe fn vcaltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { | |
1146 | vcagtq_f64(b, a) | |
1147 | } | |
1148 | ||
1149 | /// Floating-point absolute compare less than or equal | |
1150 | #[inline] | |
1151 | #[target_feature(enable = "neon")] | |
1152 | #[cfg_attr(test, assert_instr(facge))] | |
1153 | pub unsafe fn vcale_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { | |
1154 | vcage_f64(b, a) | |
1155 | } | |
1156 | ||
1157 | /// Floating-point absolute compare less than or equal | |
1158 | #[inline] | |
1159 | #[target_feature(enable = "neon")] | |
1160 | #[cfg_attr(test, assert_instr(facge))] | |
1161 | pub unsafe fn vcaleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { | |
1162 | vcageq_f64(b, a) | |
1163 | } | |
1164 | ||
1165 | /// Insert vector element from another vector element | |
1166 | #[inline] | |
1167 | #[target_feature(enable = "neon")] | |
1168 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1169 | #[rustc_legacy_const_generics(1, 3)] | |
1170 | pub unsafe fn vcopy_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t { | |
1171 | static_assert_imm3!(LANE1); | |
1172 | static_assert_imm3!(LANE2); | |
1173 | match LANE1 & 0b111 { | |
1174 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1175 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1176 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1177 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), | |
1178 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), | |
1179 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), | |
1180 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), | |
1181 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), | |
1182 | _ => unreachable_unchecked(), | |
1183 | } | |
1184 | } | |
1185 | ||
1186 | /// Insert vector element from another vector element | |
1187 | #[inline] | |
1188 | #[target_feature(enable = "neon")] | |
1189 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1190 | #[rustc_legacy_const_generics(1, 3)] | |
1191 | pub unsafe fn vcopyq_laneq_s8<const LANE1: i32, const LANE2: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t { | |
1192 | static_assert_imm4!(LANE1); | |
1193 | static_assert_imm4!(LANE2); | |
1194 | match LANE1 & 0b1111 { | |
1195 | 0 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1196 | 1 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1197 | 2 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1198 | 3 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1199 | 4 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1200 | 5 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1201 | 6 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1202 | 7 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1203 | 8 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), | |
1204 | 9 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), | |
1205 | 10 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), | |
1206 | 11 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), | |
1207 | 12 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), | |
1208 | 13 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), | |
1209 | 14 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), | |
1210 | 15 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), | |
1211 | _ => unreachable_unchecked(), | |
1212 | } | |
1213 | } | |
1214 | ||
1215 | /// Insert vector element from another vector element | |
1216 | #[inline] | |
1217 | #[target_feature(enable = "neon")] | |
1218 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1219 | #[rustc_legacy_const_generics(1, 3)] | |
1220 | pub unsafe fn vcopy_lane_s16<const LANE1: i32, const LANE2: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t { | |
1221 | static_assert_imm2!(LANE1); | |
1222 | static_assert_imm2!(LANE2); | |
1223 | match LANE1 & 0b11 { | |
1224 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1, 2, 3]), | |
1225 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32, 2, 3]), | |
1226 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 4 + LANE2 as u32, 3]), | |
1227 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 4 + LANE2 as u32]), | |
1228 | _ => unreachable_unchecked(), | |
1229 | } | |
1230 | } | |
1231 | ||
1232 | /// Insert vector element from another vector element | |
1233 | #[inline] | |
1234 | #[target_feature(enable = "neon")] | |
1235 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1236 | #[rustc_legacy_const_generics(1, 3)] | |
1237 | pub unsafe fn vcopyq_laneq_s16<const LANE1: i32, const LANE2: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t { | |
1238 | static_assert_imm3!(LANE1); | |
1239 | static_assert_imm3!(LANE2); | |
1240 | match LANE1 & 0b111 { | |
1241 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1242 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1243 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1244 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), | |
1245 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), | |
1246 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), | |
1247 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), | |
1248 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), | |
1249 | _ => unreachable_unchecked(), | |
1250 | } | |
1251 | } | |
1252 | ||
1253 | /// Insert vector element from another vector element | |
1254 | #[inline] | |
1255 | #[target_feature(enable = "neon")] | |
1256 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1257 | #[rustc_legacy_const_generics(1, 3)] | |
1258 | pub unsafe fn vcopy_lane_s32<const LANE1: i32, const LANE2: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t { | |
1259 | static_assert_imm1!(LANE1); | |
1260 | static_assert_imm1!(LANE2); | |
1261 | match LANE1 & 0b1 { | |
1262 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
1263 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
1264 | _ => unreachable_unchecked(), | |
1265 | } | |
1266 | } | |
1267 | ||
1268 | /// Insert vector element from another vector element | |
1269 | #[inline] | |
1270 | #[target_feature(enable = "neon")] | |
1271 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1272 | #[rustc_legacy_const_generics(1, 3)] | |
1273 | pub unsafe fn vcopyq_laneq_s32<const LANE1: i32, const LANE2: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t { | |
1274 | static_assert_imm2!(LANE1); | |
1275 | static_assert_imm2!(LANE2); | |
1276 | match LANE1 & 0b11 { | |
1277 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1, 2, 3]), | |
1278 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32, 2, 3]), | |
1279 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 4 + LANE2 as u32, 3]), | |
1280 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 4 + LANE2 as u32]), | |
1281 | _ => unreachable_unchecked(), | |
1282 | } | |
1283 | } | |
1284 | ||
1285 | /// Insert vector element from another vector element | |
1286 | #[inline] | |
1287 | #[target_feature(enable = "neon")] | |
1288 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1289 | #[rustc_legacy_const_generics(1, 3)] | |
1290 | pub unsafe fn vcopyq_laneq_s64<const LANE1: i32, const LANE2: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t { | |
1291 | static_assert_imm1!(LANE1); | |
1292 | static_assert_imm1!(LANE2); | |
1293 | match LANE1 & 0b1 { | |
1294 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
1295 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
1296 | _ => unreachable_unchecked(), | |
1297 | } | |
1298 | } | |
1299 | ||
1300 | /// Insert vector element from another vector element | |
1301 | #[inline] | |
1302 | #[target_feature(enable = "neon")] | |
1303 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1304 | #[rustc_legacy_const_generics(1, 3)] | |
1305 | pub unsafe fn vcopy_lane_u8<const LANE1: i32, const LANE2: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { | |
1306 | static_assert_imm3!(LANE1); | |
1307 | static_assert_imm3!(LANE2); | |
1308 | match LANE1 & 0b111 { | |
1309 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1310 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1311 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1312 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), | |
1313 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), | |
1314 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), | |
1315 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), | |
1316 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), | |
1317 | _ => unreachable_unchecked(), | |
1318 | } | |
1319 | } | |
1320 | ||
1321 | /// Insert vector element from another vector element | |
1322 | #[inline] | |
1323 | #[target_feature(enable = "neon")] | |
1324 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1325 | #[rustc_legacy_const_generics(1, 3)] | |
1326 | pub unsafe fn vcopyq_laneq_u8<const LANE1: i32, const LANE2: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { | |
1327 | static_assert_imm4!(LANE1); | |
1328 | static_assert_imm4!(LANE2); | |
1329 | match LANE1 & 0b1111 { | |
1330 | 0 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1331 | 1 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1332 | 2 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1333 | 3 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1334 | 4 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1335 | 5 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1336 | 6 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1337 | 7 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1338 | 8 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), | |
1339 | 9 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), | |
1340 | 10 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), | |
1341 | 11 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), | |
1342 | 12 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), | |
1343 | 13 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), | |
1344 | 14 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), | |
1345 | 15 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), | |
1346 | _ => unreachable_unchecked(), | |
1347 | } | |
1348 | } | |
1349 | ||
1350 | /// Insert vector element from another vector element | |
1351 | #[inline] | |
1352 | #[target_feature(enable = "neon")] | |
1353 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1354 | #[rustc_legacy_const_generics(1, 3)] | |
1355 | pub unsafe fn vcopy_lane_u16<const LANE1: i32, const LANE2: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { | |
1356 | static_assert_imm2!(LANE1); | |
1357 | static_assert_imm2!(LANE2); | |
1358 | match LANE1 & 0b11 { | |
1359 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1, 2, 3]), | |
1360 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32, 2, 3]), | |
1361 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 4 + LANE2 as u32, 3]), | |
1362 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 4 + LANE2 as u32]), | |
1363 | _ => unreachable_unchecked(), | |
1364 | } | |
1365 | } | |
1366 | ||
1367 | /// Insert vector element from another vector element | |
1368 | #[inline] | |
1369 | #[target_feature(enable = "neon")] | |
1370 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1371 | #[rustc_legacy_const_generics(1, 3)] | |
1372 | pub unsafe fn vcopyq_laneq_u16<const LANE1: i32, const LANE2: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { | |
1373 | static_assert_imm3!(LANE1); | |
1374 | static_assert_imm3!(LANE2); | |
1375 | match LANE1 & 0b111 { | |
1376 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1377 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1378 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1379 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), | |
1380 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), | |
1381 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), | |
1382 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), | |
1383 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), | |
1384 | _ => unreachable_unchecked(), | |
1385 | } | |
1386 | } | |
1387 | ||
1388 | /// Insert vector element from another vector element | |
1389 | #[inline] | |
1390 | #[target_feature(enable = "neon")] | |
1391 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1392 | #[rustc_legacy_const_generics(1, 3)] | |
1393 | pub unsafe fn vcopy_lane_u32<const LANE1: i32, const LANE2: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { | |
1394 | static_assert_imm1!(LANE1); | |
1395 | static_assert_imm1!(LANE2); | |
1396 | match LANE1 & 0b1 { | |
1397 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
1398 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
1399 | _ => unreachable_unchecked(), | |
1400 | } | |
1401 | } | |
1402 | ||
1403 | /// Insert vector element from another vector element | |
1404 | #[inline] | |
1405 | #[target_feature(enable = "neon")] | |
1406 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1407 | #[rustc_legacy_const_generics(1, 3)] | |
1408 | pub unsafe fn vcopyq_laneq_u32<const LANE1: i32, const LANE2: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { | |
1409 | static_assert_imm2!(LANE1); | |
1410 | static_assert_imm2!(LANE2); | |
1411 | match LANE1 & 0b11 { | |
1412 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1, 2, 3]), | |
1413 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32, 2, 3]), | |
1414 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 4 + LANE2 as u32, 3]), | |
1415 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 4 + LANE2 as u32]), | |
1416 | _ => unreachable_unchecked(), | |
1417 | } | |
1418 | } | |
1419 | ||
1420 | /// Insert vector element from another vector element | |
1421 | #[inline] | |
1422 | #[target_feature(enable = "neon")] | |
1423 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1424 | #[rustc_legacy_const_generics(1, 3)] | |
1425 | pub unsafe fn vcopyq_laneq_u64<const LANE1: i32, const LANE2: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
1426 | static_assert_imm1!(LANE1); | |
1427 | static_assert_imm1!(LANE2); | |
1428 | match LANE1 & 0b1 { | |
1429 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
1430 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
1431 | _ => unreachable_unchecked(), | |
1432 | } | |
1433 | } | |
1434 | ||
1435 | /// Insert vector element from another vector element | |
1436 | #[inline] | |
1437 | #[target_feature(enable = "neon")] | |
1438 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1439 | #[rustc_legacy_const_generics(1, 3)] | |
1440 | pub unsafe fn vcopy_lane_p8<const LANE1: i32, const LANE2: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { | |
1441 | static_assert_imm3!(LANE1); | |
1442 | static_assert_imm3!(LANE2); | |
1443 | match LANE1 & 0b111 { | |
1444 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1445 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1446 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1447 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), | |
1448 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), | |
1449 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), | |
1450 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), | |
1451 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), | |
1452 | _ => unreachable_unchecked(), | |
1453 | } | |
1454 | } | |
1455 | ||
1456 | /// Insert vector element from another vector element | |
1457 | #[inline] | |
1458 | #[target_feature(enable = "neon")] | |
1459 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1460 | #[rustc_legacy_const_generics(1, 3)] | |
1461 | pub unsafe fn vcopyq_laneq_p8<const LANE1: i32, const LANE2: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { | |
1462 | static_assert_imm4!(LANE1); | |
1463 | static_assert_imm4!(LANE2); | |
1464 | match LANE1 & 0b1111 { | |
1465 | 0 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1466 | 1 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1467 | 2 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1468 | 3 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1469 | 4 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1470 | 5 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1471 | 6 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1472 | 7 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1473 | 8 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), | |
1474 | 9 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), | |
1475 | 10 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), | |
1476 | 11 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), | |
1477 | 12 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), | |
1478 | 13 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), | |
1479 | 14 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), | |
1480 | 15 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), | |
1481 | _ => unreachable_unchecked(), | |
1482 | } | |
1483 | } | |
1484 | ||
1485 | /// Insert vector element from another vector element | |
1486 | #[inline] | |
1487 | #[target_feature(enable = "neon")] | |
1488 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1489 | #[rustc_legacy_const_generics(1, 3)] | |
1490 | pub unsafe fn vcopy_lane_p16<const LANE1: i32, const LANE2: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { | |
1491 | static_assert_imm2!(LANE1); | |
1492 | static_assert_imm2!(LANE2); | |
1493 | match LANE1 & 0b11 { | |
1494 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1, 2, 3]), | |
1495 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32, 2, 3]), | |
1496 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 4 + LANE2 as u32, 3]), | |
1497 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 4 + LANE2 as u32]), | |
1498 | _ => unreachable_unchecked(), | |
1499 | } | |
1500 | } | |
1501 | ||
1502 | /// Insert vector element from another vector element | |
1503 | #[inline] | |
1504 | #[target_feature(enable = "neon")] | |
1505 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1506 | #[rustc_legacy_const_generics(1, 3)] | |
1507 | pub unsafe fn vcopyq_laneq_p16<const LANE1: i32, const LANE2: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { | |
1508 | static_assert_imm3!(LANE1); | |
1509 | static_assert_imm3!(LANE2); | |
1510 | match LANE1 & 0b111 { | |
1511 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1512 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1513 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1514 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), | |
1515 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), | |
1516 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), | |
1517 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), | |
1518 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), | |
1519 | _ => unreachable_unchecked(), | |
1520 | } | |
1521 | } | |
1522 | ||
1523 | /// Insert vector element from another vector element | |
1524 | #[inline] | |
1525 | #[target_feature(enable = "neon")] | |
1526 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1527 | #[rustc_legacy_const_generics(1, 3)] | |
1528 | pub unsafe fn vcopyq_laneq_p64<const LANE1: i32, const LANE2: i32>(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { | |
1529 | static_assert_imm1!(LANE1); | |
1530 | static_assert_imm1!(LANE2); | |
1531 | match LANE1 & 0b1 { | |
1532 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
1533 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
1534 | _ => unreachable_unchecked(), | |
1535 | } | |
1536 | } | |
1537 | ||
1538 | /// Insert vector element from another vector element | |
1539 | #[inline] | |
1540 | #[target_feature(enable = "neon")] | |
1541 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1542 | #[rustc_legacy_const_generics(1, 3)] | |
1543 | pub unsafe fn vcopy_lane_f32<const LANE1: i32, const LANE2: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
1544 | static_assert_imm1!(LANE1); | |
1545 | static_assert_imm1!(LANE2); | |
1546 | match LANE1 & 0b1 { | |
1547 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
1548 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
1549 | _ => unreachable_unchecked(), | |
1550 | } | |
1551 | } | |
1552 | ||
1553 | /// Insert vector element from another vector element | |
1554 | #[inline] | |
1555 | #[target_feature(enable = "neon")] | |
1556 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1557 | #[rustc_legacy_const_generics(1, 3)] | |
1558 | pub unsafe fn vcopyq_laneq_f32<const LANE1: i32, const LANE2: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
1559 | static_assert_imm2!(LANE1); | |
1560 | static_assert_imm2!(LANE2); | |
1561 | match LANE1 & 0b11 { | |
1562 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1, 2, 3]), | |
1563 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32, 2, 3]), | |
1564 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 4 + LANE2 as u32, 3]), | |
1565 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 4 + LANE2 as u32]), | |
1566 | _ => unreachable_unchecked(), | |
1567 | } | |
1568 | } | |
1569 | ||
1570 | /// Insert vector element from another vector element | |
1571 | #[inline] | |
1572 | #[target_feature(enable = "neon")] | |
1573 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1574 | #[rustc_legacy_const_generics(1, 3)] | |
1575 | pub unsafe fn vcopyq_laneq_f64<const LANE1: i32, const LANE2: i32>(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
1576 | static_assert_imm1!(LANE1); | |
1577 | static_assert_imm1!(LANE2); | |
1578 | match LANE1 & 0b1 { | |
1579 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
1580 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
1581 | _ => unreachable_unchecked(), | |
1582 | } | |
1583 | } | |
1584 | ||
1585 | /// Insert vector element from another vector element | |
1586 | #[inline] | |
1587 | #[target_feature(enable = "neon")] | |
1588 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1589 | #[rustc_legacy_const_generics(1, 3)] | |
1590 | pub unsafe fn vcopy_laneq_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x16_t) -> int8x8_t { | |
1591 | static_assert_imm3!(LANE1); | |
1592 | static_assert_imm4!(LANE2); | |
1593 | let a: int8x16_t = simd_shuffle16!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); | |
1594 | match LANE1 & 0b111 { | |
1595 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1596 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1597 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1598 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), | |
1599 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), | |
1600 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), | |
1601 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), | |
1602 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), | |
1603 | _ => unreachable_unchecked(), | |
1604 | } | |
1605 | } | |
1606 | ||
1607 | /// Insert vector element from another vector element | |
1608 | #[inline] | |
1609 | #[target_feature(enable = "neon")] | |
1610 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1611 | #[rustc_legacy_const_generics(1, 3)] | |
1612 | pub unsafe fn vcopy_laneq_s16<const LANE1: i32, const LANE2: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t { | |
1613 | static_assert_imm2!(LANE1); | |
1614 | static_assert_imm3!(LANE2); | |
1615 | let a: int16x8_t = simd_shuffle8!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); | |
1616 | match LANE1 & 0b11 { | |
1617 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3]), | |
1618 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3]), | |
1619 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3]), | |
1620 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32]), | |
1621 | _ => unreachable_unchecked(), | |
1622 | } | |
1623 | } | |
1624 | ||
1625 | /// Insert vector element from another vector element | |
1626 | #[inline] | |
1627 | #[target_feature(enable = "neon")] | |
1628 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1629 | #[rustc_legacy_const_generics(1, 3)] | |
1630 | pub unsafe fn vcopy_laneq_s32<const LANE1: i32, const LANE2: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t { | |
1631 | static_assert_imm1!(LANE1); | |
1632 | static_assert_imm2!(LANE2); | |
1633 | let a: int32x4_t = simd_shuffle4!(a, a, [0, 1, 2, 3]); | |
1634 | match LANE1 & 0b1 { | |
1635 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1]), | |
1636 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32]), | |
1637 | _ => unreachable_unchecked(), | |
1638 | } | |
1639 | } | |
1640 | ||
1641 | /// Insert vector element from another vector element | |
1642 | #[inline] | |
1643 | #[target_feature(enable = "neon")] | |
1644 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1645 | #[rustc_legacy_const_generics(1, 3)] | |
1646 | pub unsafe fn vcopy_laneq_u8<const LANE1: i32, const LANE2: i32>(a: uint8x8_t, b: uint8x16_t) -> uint8x8_t { | |
1647 | static_assert_imm3!(LANE1); | |
1648 | static_assert_imm4!(LANE2); | |
1649 | let a: uint8x16_t = simd_shuffle16!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); | |
1650 | match LANE1 & 0b111 { | |
1651 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1652 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1653 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1654 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), | |
1655 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), | |
1656 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), | |
1657 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), | |
1658 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), | |
1659 | _ => unreachable_unchecked(), | |
1660 | } | |
1661 | } | |
1662 | ||
1663 | /// Insert vector element from another vector element | |
1664 | #[inline] | |
1665 | #[target_feature(enable = "neon")] | |
1666 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1667 | #[rustc_legacy_const_generics(1, 3)] | |
1668 | pub unsafe fn vcopy_laneq_u16<const LANE1: i32, const LANE2: i32>(a: uint16x4_t, b: uint16x8_t) -> uint16x4_t { | |
1669 | static_assert_imm2!(LANE1); | |
1670 | static_assert_imm3!(LANE2); | |
1671 | let a: uint16x8_t = simd_shuffle8!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); | |
1672 | match LANE1 & 0b11 { | |
1673 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3]), | |
1674 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3]), | |
1675 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3]), | |
1676 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32]), | |
1677 | _ => unreachable_unchecked(), | |
1678 | } | |
1679 | } | |
1680 | ||
1681 | /// Insert vector element from another vector element | |
1682 | #[inline] | |
1683 | #[target_feature(enable = "neon")] | |
1684 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1685 | #[rustc_legacy_const_generics(1, 3)] | |
1686 | pub unsafe fn vcopy_laneq_u32<const LANE1: i32, const LANE2: i32>(a: uint32x2_t, b: uint32x4_t) -> uint32x2_t { | |
1687 | static_assert_imm1!(LANE1); | |
1688 | static_assert_imm2!(LANE2); | |
1689 | let a: uint32x4_t = simd_shuffle4!(a, a, [0, 1, 2, 3]); | |
1690 | match LANE1 & 0b1 { | |
1691 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1]), | |
1692 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32]), | |
1693 | _ => unreachable_unchecked(), | |
1694 | } | |
1695 | } | |
1696 | ||
1697 | /// Insert vector element from another vector element | |
1698 | #[inline] | |
1699 | #[target_feature(enable = "neon")] | |
1700 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1701 | #[rustc_legacy_const_generics(1, 3)] | |
1702 | pub unsafe fn vcopy_laneq_p8<const LANE1: i32, const LANE2: i32>(a: poly8x8_t, b: poly8x16_t) -> poly8x8_t { | |
1703 | static_assert_imm3!(LANE1); | |
1704 | static_assert_imm4!(LANE2); | |
1705 | let a: poly8x16_t = simd_shuffle16!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); | |
1706 | match LANE1 & 0b111 { | |
1707 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1708 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1709 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1710 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), | |
1711 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), | |
1712 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), | |
1713 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), | |
1714 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), | |
1715 | _ => unreachable_unchecked(), | |
1716 | } | |
1717 | } | |
1718 | ||
1719 | /// Insert vector element from another vector element | |
1720 | #[inline] | |
1721 | #[target_feature(enable = "neon")] | |
1722 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1723 | #[rustc_legacy_const_generics(1, 3)] | |
1724 | pub unsafe fn vcopy_laneq_p16<const LANE1: i32, const LANE2: i32>(a: poly16x4_t, b: poly16x8_t) -> poly16x4_t { | |
1725 | static_assert_imm2!(LANE1); | |
1726 | static_assert_imm3!(LANE2); | |
1727 | let a: poly16x8_t = simd_shuffle8!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); | |
1728 | match LANE1 & 0b11 { | |
1729 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3]), | |
1730 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3]), | |
1731 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3]), | |
1732 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32]), | |
1733 | _ => unreachable_unchecked(), | |
1734 | } | |
1735 | } | |
1736 | ||
1737 | /// Insert vector element from another vector element | |
1738 | #[inline] | |
1739 | #[target_feature(enable = "neon")] | |
1740 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1741 | #[rustc_legacy_const_generics(1, 3)] | |
1742 | pub unsafe fn vcopy_laneq_f32<const LANE1: i32, const LANE2: i32>(a: float32x2_t, b: float32x4_t) -> float32x2_t { | |
1743 | static_assert_imm1!(LANE1); | |
1744 | static_assert_imm2!(LANE2); | |
1745 | let a: float32x4_t = simd_shuffle4!(a, a, [0, 1, 2, 3]); | |
1746 | match LANE1 & 0b1 { | |
1747 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1]), | |
1748 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32]), | |
1749 | _ => unreachable_unchecked(), | |
1750 | } | |
1751 | } | |
1752 | ||
1753 | /// Insert vector element from another vector element | |
1754 | #[inline] | |
1755 | #[target_feature(enable = "neon")] | |
1756 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1757 | #[rustc_legacy_const_generics(1, 3)] | |
1758 | pub unsafe fn vcopyq_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x16_t, b: int8x8_t) -> int8x16_t { | |
1759 | static_assert_imm4!(LANE1); | |
1760 | static_assert_imm3!(LANE2); | |
1761 | let b: int8x16_t = simd_shuffle16!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); | |
1762 | match LANE1 & 0b1111 { | |
1763 | 0 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1764 | 1 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1765 | 2 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1766 | 3 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1767 | 4 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1768 | 5 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1769 | 6 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1770 | 7 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1771 | 8 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), | |
1772 | 9 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), | |
1773 | 10 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), | |
1774 | 11 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), | |
1775 | 12 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), | |
1776 | 13 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), | |
1777 | 14 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), | |
1778 | 15 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), | |
1779 | _ => unreachable_unchecked(), | |
1780 | } | |
1781 | } | |
1782 | ||
1783 | /// Insert vector element from another vector element | |
1784 | #[inline] | |
1785 | #[target_feature(enable = "neon")] | |
1786 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1787 | #[rustc_legacy_const_generics(1, 3)] | |
1788 | pub unsafe fn vcopyq_lane_s16<const LANE1: i32, const LANE2: i32>(a: int16x8_t, b: int16x4_t) -> int16x8_t { | |
1789 | static_assert_imm3!(LANE1); | |
1790 | static_assert_imm2!(LANE2); | |
1791 | let b: int16x8_t = simd_shuffle8!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]); | |
1792 | match LANE1 & 0b111 { | |
1793 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1794 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1795 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1796 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), | |
1797 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), | |
1798 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), | |
1799 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), | |
1800 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), | |
1801 | _ => unreachable_unchecked(), | |
1802 | } | |
1803 | } | |
1804 | ||
1805 | /// Insert vector element from another vector element | |
1806 | #[inline] | |
1807 | #[target_feature(enable = "neon")] | |
1808 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1809 | #[rustc_legacy_const_generics(1, 3)] | |
1810 | pub unsafe fn vcopyq_lane_s32<const LANE1: i32, const LANE2: i32>(a: int32x4_t, b: int32x2_t) -> int32x4_t { | |
1811 | static_assert_imm2!(LANE1); | |
1812 | static_assert_imm1!(LANE2); | |
1813 | let b: int32x4_t = simd_shuffle4!(b, b, [0, 1, 2, 3]); | |
1814 | match LANE1 & 0b11 { | |
1815 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1, 2, 3]), | |
1816 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32, 2, 3]), | |
1817 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 4 + LANE2 as u32, 3]), | |
1818 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 4 + LANE2 as u32]), | |
1819 | _ => unreachable_unchecked(), | |
1820 | } | |
1821 | } | |
1822 | ||
1823 | /// Insert vector element from another vector element | |
1824 | #[inline] | |
1825 | #[target_feature(enable = "neon")] | |
1826 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1827 | #[rustc_legacy_const_generics(1, 3)] | |
1828 | pub unsafe fn vcopyq_lane_u8<const LANE1: i32, const LANE2: i32>(a: uint8x16_t, b: uint8x8_t) -> uint8x16_t { | |
1829 | static_assert_imm4!(LANE1); | |
1830 | static_assert_imm3!(LANE2); | |
1831 | let b: uint8x16_t = simd_shuffle16!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); | |
1832 | match LANE1 & 0b1111 { | |
1833 | 0 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1834 | 1 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1835 | 2 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1836 | 3 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1837 | 4 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1838 | 5 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1839 | 6 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1840 | 7 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1841 | 8 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), | |
1842 | 9 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), | |
1843 | 10 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), | |
1844 | 11 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), | |
1845 | 12 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), | |
1846 | 13 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), | |
1847 | 14 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), | |
1848 | 15 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), | |
1849 | _ => unreachable_unchecked(), | |
1850 | } | |
1851 | } | |
1852 | ||
1853 | /// Insert vector element from another vector element | |
1854 | #[inline] | |
1855 | #[target_feature(enable = "neon")] | |
1856 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1857 | #[rustc_legacy_const_generics(1, 3)] | |
1858 | pub unsafe fn vcopyq_lane_u16<const LANE1: i32, const LANE2: i32>(a: uint16x8_t, b: uint16x4_t) -> uint16x8_t { | |
1859 | static_assert_imm3!(LANE1); | |
1860 | static_assert_imm2!(LANE2); | |
1861 | let b: uint16x8_t = simd_shuffle8!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]); | |
1862 | match LANE1 & 0b111 { | |
1863 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1864 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1865 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1866 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), | |
1867 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), | |
1868 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), | |
1869 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), | |
1870 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), | |
1871 | _ => unreachable_unchecked(), | |
1872 | } | |
1873 | } | |
1874 | ||
1875 | /// Insert vector element from another vector element | |
1876 | #[inline] | |
1877 | #[target_feature(enable = "neon")] | |
1878 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1879 | #[rustc_legacy_const_generics(1, 3)] | |
1880 | pub unsafe fn vcopyq_lane_u32<const LANE1: i32, const LANE2: i32>(a: uint32x4_t, b: uint32x2_t) -> uint32x4_t { | |
1881 | static_assert_imm2!(LANE1); | |
1882 | static_assert_imm1!(LANE2); | |
1883 | let b: uint32x4_t = simd_shuffle4!(b, b, [0, 1, 2, 3]); | |
1884 | match LANE1 & 0b11 { | |
1885 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1, 2, 3]), | |
1886 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32, 2, 3]), | |
1887 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 4 + LANE2 as u32, 3]), | |
1888 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 4 + LANE2 as u32]), | |
1889 | _ => unreachable_unchecked(), | |
1890 | } | |
1891 | } | |
1892 | ||
1893 | /// Insert vector element from another vector element | |
1894 | #[inline] | |
1895 | #[target_feature(enable = "neon")] | |
1896 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1897 | #[rustc_legacy_const_generics(1, 3)] | |
1898 | pub unsafe fn vcopyq_lane_p8<const LANE1: i32, const LANE2: i32>(a: poly8x16_t, b: poly8x8_t) -> poly8x16_t { | |
1899 | static_assert_imm4!(LANE1); | |
1900 | static_assert_imm3!(LANE2); | |
1901 | let b: poly8x16_t = simd_shuffle16!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); | |
1902 | match LANE1 & 0b1111 { | |
1903 | 0 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1904 | 1 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1905 | 2 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1906 | 3 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1907 | 4 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1908 | 5 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1909 | 6 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1910 | 7 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1911 | 8 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), | |
1912 | 9 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), | |
1913 | 10 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), | |
1914 | 11 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), | |
1915 | 12 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), | |
1916 | 13 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), | |
1917 | 14 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), | |
1918 | 15 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), | |
1919 | _ => unreachable_unchecked(), | |
1920 | } | |
1921 | } | |
1922 | ||
1923 | /// Insert vector element from another vector element | |
1924 | #[inline] | |
1925 | #[target_feature(enable = "neon")] | |
1926 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1927 | #[rustc_legacy_const_generics(1, 3)] | |
1928 | pub unsafe fn vcopyq_lane_p16<const LANE1: i32, const LANE2: i32>(a: poly16x8_t, b: poly16x4_t) -> poly16x8_t { | |
1929 | static_assert_imm3!(LANE1); | |
1930 | static_assert_imm2!(LANE2); | |
1931 | let b: poly16x8_t = simd_shuffle8!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]); | |
1932 | match LANE1 & 0b111 { | |
1933 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1934 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1935 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1936 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), | |
1937 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), | |
1938 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), | |
1939 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), | |
1940 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), | |
1941 | _ => unreachable_unchecked(), | |
1942 | } | |
1943 | } | |
1944 | ||
1945 | /// Insert vector element from another vector element | |
1946 | #[inline] | |
1947 | #[target_feature(enable = "neon")] | |
1948 | #[cfg_attr(test, assert_instr(zip1, LANE1 = 1, LANE2 = 0))] | |
1949 | #[rustc_legacy_const_generics(1, 3)] | |
1950 | pub unsafe fn vcopyq_lane_s64<const LANE1: i32, const LANE2: i32>(a: int64x2_t, b: int64x1_t) -> int64x2_t { | |
1951 | static_assert_imm1!(LANE1); | |
1952 | static_assert!(LANE2 : i32 where LANE2 == 0); | |
1953 | let b: int64x2_t = simd_shuffle2!(b, b, [0, 1]); | |
1954 | match LANE1 & 0b1 { | |
1955 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
1956 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
1957 | _ => unreachable_unchecked(), | |
1958 | } | |
1959 | } | |
1960 | ||
1961 | /// Insert vector element from another vector element | |
1962 | #[inline] | |
1963 | #[target_feature(enable = "neon")] | |
1964 | #[cfg_attr(test, assert_instr(zip1, LANE1 = 1, LANE2 = 0))] | |
1965 | #[rustc_legacy_const_generics(1, 3)] | |
1966 | pub unsafe fn vcopyq_lane_u64<const LANE1: i32, const LANE2: i32>(a: uint64x2_t, b: uint64x1_t) -> uint64x2_t { | |
1967 | static_assert_imm1!(LANE1); | |
1968 | static_assert!(LANE2 : i32 where LANE2 == 0); | |
1969 | let b: uint64x2_t = simd_shuffle2!(b, b, [0, 1]); | |
1970 | match LANE1 & 0b1 { | |
1971 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
1972 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
1973 | _ => unreachable_unchecked(), | |
1974 | } | |
1975 | } | |
1976 | ||
1977 | /// Insert vector element from another vector element | |
1978 | #[inline] | |
1979 | #[target_feature(enable = "neon")] | |
1980 | #[cfg_attr(test, assert_instr(zip1, LANE1 = 1, LANE2 = 0))] | |
1981 | #[rustc_legacy_const_generics(1, 3)] | |
1982 | pub unsafe fn vcopyq_lane_p64<const LANE1: i32, const LANE2: i32>(a: poly64x2_t, b: poly64x1_t) -> poly64x2_t { | |
1983 | static_assert_imm1!(LANE1); | |
1984 | static_assert!(LANE2 : i32 where LANE2 == 0); | |
1985 | let b: poly64x2_t = simd_shuffle2!(b, b, [0, 1]); | |
1986 | match LANE1 & 0b1 { | |
1987 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
1988 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
1989 | _ => unreachable_unchecked(), | |
1990 | } | |
1991 | } | |
1992 | ||
1993 | /// Insert vector element from another vector element | |
1994 | #[inline] | |
1995 | #[target_feature(enable = "neon")] | |
1996 | #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] | |
1997 | #[rustc_legacy_const_generics(1, 3)] | |
1998 | pub unsafe fn vcopyq_lane_f32<const LANE1: i32, const LANE2: i32>(a: float32x4_t, b: float32x2_t) -> float32x4_t { | |
1999 | static_assert_imm2!(LANE1); | |
2000 | static_assert_imm1!(LANE2); | |
2001 | let b: float32x4_t = simd_shuffle4!(b, b, [0, 1, 2, 3]); | |
2002 | match LANE1 & 0b11 { | |
2003 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1, 2, 3]), | |
2004 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32, 2, 3]), | |
2005 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 4 + LANE2 as u32, 3]), | |
2006 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 4 + LANE2 as u32]), | |
2007 | _ => unreachable_unchecked(), | |
2008 | } | |
2009 | } | |
2010 | ||
2011 | /// Insert vector element from another vector element | |
2012 | #[inline] | |
2013 | #[target_feature(enable = "neon")] | |
2014 | #[cfg_attr(test, assert_instr(zip1, LANE1 = 1, LANE2 = 0))] | |
2015 | #[rustc_legacy_const_generics(1, 3)] | |
2016 | pub unsafe fn vcopyq_lane_f64<const LANE1: i32, const LANE2: i32>(a: float64x2_t, b: float64x1_t) -> float64x2_t { | |
2017 | static_assert_imm1!(LANE1); | |
2018 | static_assert!(LANE2 : i32 where LANE2 == 0); | |
2019 | let b: float64x2_t = simd_shuffle2!(b, b, [0, 1]); | |
2020 | match LANE1 & 0b1 { | |
2021 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
2022 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
2023 | _ => unreachable_unchecked(), | |
2024 | } | |
2025 | } | |
2026 | ||
2027 | /// Insert vector element from another vector element | |
2028 | #[inline] | |
2029 | #[target_feature(enable = "neon")] | |
2030 | #[cfg_attr(test, assert_instr(nop))] | |
2031 | pub unsafe fn vcreate_f64(a: u64) -> float64x1_t { | |
2032 | transmute(a) | |
2033 | } | |
2034 | ||
2035 | /// Fixed-point convert to floating-point | |
2036 | #[inline] | |
2037 | #[target_feature(enable = "neon")] | |
2038 | #[cfg_attr(test, assert_instr(scvtf))] | |
2039 | pub unsafe fn vcvt_f64_s64(a: int64x1_t) -> float64x1_t { | |
2040 | simd_cast(a) | |
2041 | } | |
2042 | ||
2043 | /// Fixed-point convert to floating-point | |
2044 | #[inline] | |
2045 | #[target_feature(enable = "neon")] | |
2046 | #[cfg_attr(test, assert_instr(scvtf))] | |
2047 | pub unsafe fn vcvtq_f64_s64(a: int64x2_t) -> float64x2_t { | |
2048 | simd_cast(a) | |
2049 | } | |
2050 | ||
2051 | /// Fixed-point convert to floating-point | |
2052 | #[inline] | |
2053 | #[target_feature(enable = "neon")] | |
2054 | #[cfg_attr(test, assert_instr(ucvtf))] | |
2055 | pub unsafe fn vcvt_f64_u64(a: uint64x1_t) -> float64x1_t { | |
2056 | simd_cast(a) | |
2057 | } | |
2058 | ||
2059 | /// Fixed-point convert to floating-point | |
2060 | #[inline] | |
2061 | #[target_feature(enable = "neon")] | |
2062 | #[cfg_attr(test, assert_instr(ucvtf))] | |
2063 | pub unsafe fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t { | |
2064 | simd_cast(a) | |
2065 | } | |
2066 | ||
2067 | /// Floating-point convert to higher precision long | |
2068 | #[inline] | |
2069 | #[target_feature(enable = "neon")] | |
2070 | #[cfg_attr(test, assert_instr(fcvtl))] | |
2071 | pub unsafe fn vcvt_f64_f32(a: float32x2_t) -> float64x2_t { | |
2072 | simd_cast(a) | |
2073 | } | |
2074 | ||
2075 | /// Floating-point convert to higher precision long | |
2076 | #[inline] | |
2077 | #[target_feature(enable = "neon")] | |
2078 | #[cfg_attr(test, assert_instr(fcvtl))] | |
2079 | pub unsafe fn vcvt_high_f64_f32(a: float32x4_t) -> float64x2_t { | |
2080 | let b: float32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
2081 | simd_cast(b) | |
2082 | } | |
2083 | ||
2084 | /// Floating-point convert to lower precision narrow | |
2085 | #[inline] | |
2086 | #[target_feature(enable = "neon")] | |
2087 | #[cfg_attr(test, assert_instr(fcvtn))] | |
2088 | pub unsafe fn vcvt_f32_f64(a: float64x2_t) -> float32x2_t { | |
2089 | simd_cast(a) | |
2090 | } | |
2091 | ||
2092 | /// Floating-point convert to lower precision narrow | |
2093 | #[inline] | |
2094 | #[target_feature(enable = "neon")] | |
2095 | #[cfg_attr(test, assert_instr(fcvtn))] | |
2096 | pub unsafe fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t { | |
2097 | simd_shuffle4!(a, simd_cast(b), [0, 1, 2, 3]) | |
2098 | } | |
2099 | ||
2100 | /// Floating-point convert to lower precision narrow, rounding to odd | |
2101 | #[inline] | |
2102 | #[target_feature(enable = "neon")] | |
2103 | #[cfg_attr(test, assert_instr(fcvtxn))] | |
2104 | pub unsafe fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t { | |
2105 | #[allow(improper_ctypes)] | |
2106 | extern "C" { | |
2107 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtxn.v2f32.v2f64")] | |
2108 | fn vcvtx_f32_f64_(a: float64x2_t) -> float32x2_t; | |
2109 | } | |
2110 | vcvtx_f32_f64_(a) | |
2111 | } | |
2112 | ||
2113 | /// Floating-point convert to lower precision narrow, rounding to odd | |
2114 | #[inline] | |
2115 | #[target_feature(enable = "neon")] | |
2116 | #[cfg_attr(test, assert_instr(fcvtxn))] | |
2117 | pub unsafe fn vcvtx_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t { | |
2118 | simd_shuffle4!(a, vcvtx_f32_f64(b), [0, 1, 2, 3]) | |
2119 | } | |
2120 | ||
2121 | /// Fixed-point convert to floating-point | |
2122 | #[inline] | |
2123 | #[target_feature(enable = "neon")] | |
2124 | #[cfg_attr(test, assert_instr(scvtf, N = 2))] | |
2125 | #[rustc_legacy_const_generics(1)] | |
2126 | pub unsafe fn vcvt_n_f64_s64<const N: i32>(a: int64x1_t) -> float64x1_t { | |
2127 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2128 | #[allow(improper_ctypes)] | |
2129 | extern "C" { | |
2130 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfxs2fp.v1f64.v1i64")] | |
2131 | fn vcvt_n_f64_s64_(a: int64x1_t, n: i32) -> float64x1_t; | |
2132 | } | |
2133 | vcvt_n_f64_s64_(a, N) | |
2134 | } | |
2135 | ||
2136 | /// Fixed-point convert to floating-point | |
2137 | #[inline] | |
2138 | #[target_feature(enable = "neon")] | |
2139 | #[cfg_attr(test, assert_instr(scvtf, N = 2))] | |
2140 | #[rustc_legacy_const_generics(1)] | |
2141 | pub unsafe fn vcvtq_n_f64_s64<const N: i32>(a: int64x2_t) -> float64x2_t { | |
2142 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2143 | #[allow(improper_ctypes)] | |
2144 | extern "C" { | |
2145 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64")] | |
2146 | fn vcvtq_n_f64_s64_(a: int64x2_t, n: i32) -> float64x2_t; | |
2147 | } | |
2148 | vcvtq_n_f64_s64_(a, N) | |
2149 | } | |
2150 | ||
2151 | /// Fixed-point convert to floating-point | |
2152 | #[inline] | |
2153 | #[target_feature(enable = "neon")] | |
2154 | #[cfg_attr(test, assert_instr(scvtf, N = 2))] | |
2155 | #[rustc_legacy_const_generics(1)] | |
2156 | pub unsafe fn vcvts_n_f32_s32<const N: i32>(a: i32) -> f32 { | |
2157 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
2158 | #[allow(improper_ctypes)] | |
2159 | extern "C" { | |
2160 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfxs2fp.f32.i32")] | |
2161 | fn vcvts_n_f32_s32_(a: i32, n: i32) -> f32; | |
2162 | } | |
2163 | vcvts_n_f32_s32_(a, N) | |
2164 | } | |
2165 | ||
2166 | /// Fixed-point convert to floating-point | |
2167 | #[inline] | |
2168 | #[target_feature(enable = "neon")] | |
2169 | #[cfg_attr(test, assert_instr(scvtf, N = 2))] | |
2170 | #[rustc_legacy_const_generics(1)] | |
2171 | pub unsafe fn vcvtd_n_f64_s64<const N: i32>(a: i64) -> f64 { | |
2172 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2173 | #[allow(improper_ctypes)] | |
2174 | extern "C" { | |
2175 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfxs2fp.f64.i64")] | |
2176 | fn vcvtd_n_f64_s64_(a: i64, n: i32) -> f64; | |
2177 | } | |
2178 | vcvtd_n_f64_s64_(a, N) | |
2179 | } | |
2180 | ||
2181 | /// Fixed-point convert to floating-point | |
2182 | #[inline] | |
2183 | #[target_feature(enable = "neon")] | |
2184 | #[cfg_attr(test, assert_instr(ucvtf, N = 2))] | |
2185 | #[rustc_legacy_const_generics(1)] | |
2186 | pub unsafe fn vcvt_n_f64_u64<const N: i32>(a: uint64x1_t) -> float64x1_t { | |
2187 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2188 | #[allow(improper_ctypes)] | |
2189 | extern "C" { | |
2190 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfxu2fp.v1f64.v1i64")] | |
2191 | fn vcvt_n_f64_u64_(a: uint64x1_t, n: i32) -> float64x1_t; | |
2192 | } | |
2193 | vcvt_n_f64_u64_(a, N) | |
2194 | } | |
2195 | ||
2196 | /// Fixed-point convert to floating-point | |
2197 | #[inline] | |
2198 | #[target_feature(enable = "neon")] | |
2199 | #[cfg_attr(test, assert_instr(ucvtf, N = 2))] | |
2200 | #[rustc_legacy_const_generics(1)] | |
2201 | pub unsafe fn vcvtq_n_f64_u64<const N: i32>(a: uint64x2_t) -> float64x2_t { | |
2202 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2203 | #[allow(improper_ctypes)] | |
2204 | extern "C" { | |
2205 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64")] | |
2206 | fn vcvtq_n_f64_u64_(a: uint64x2_t, n: i32) -> float64x2_t; | |
2207 | } | |
2208 | vcvtq_n_f64_u64_(a, N) | |
2209 | } | |
2210 | ||
2211 | /// Fixed-point convert to floating-point | |
2212 | #[inline] | |
2213 | #[target_feature(enable = "neon")] | |
2214 | #[cfg_attr(test, assert_instr(ucvtf, N = 2))] | |
2215 | #[rustc_legacy_const_generics(1)] | |
2216 | pub unsafe fn vcvts_n_f32_u32<const N: i32>(a: u32) -> f32 { | |
2217 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
2218 | #[allow(improper_ctypes)] | |
2219 | extern "C" { | |
2220 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfxu2fp.f32.i32")] | |
2221 | fn vcvts_n_f32_u32_(a: u32, n: i32) -> f32; | |
2222 | } | |
2223 | vcvts_n_f32_u32_(a, N) | |
2224 | } | |
2225 | ||
2226 | /// Fixed-point convert to floating-point | |
2227 | #[inline] | |
2228 | #[target_feature(enable = "neon")] | |
2229 | #[cfg_attr(test, assert_instr(ucvtf, N = 2))] | |
2230 | #[rustc_legacy_const_generics(1)] | |
2231 | pub unsafe fn vcvtd_n_f64_u64<const N: i32>(a: u64) -> f64 { | |
2232 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2233 | #[allow(improper_ctypes)] | |
2234 | extern "C" { | |
2235 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfxu2fp.f64.i64")] | |
2236 | fn vcvtd_n_f64_u64_(a: u64, n: i32) -> f64; | |
2237 | } | |
2238 | vcvtd_n_f64_u64_(a, N) | |
2239 | } | |
2240 | ||
2241 | /// Floating-point convert to fixed-point, rounding toward zero | |
2242 | #[inline] | |
2243 | #[target_feature(enable = "neon")] | |
2244 | #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] | |
2245 | #[rustc_legacy_const_generics(1)] | |
2246 | pub unsafe fn vcvt_n_s64_f64<const N: i32>(a: float64x1_t) -> int64x1_t { | |
2247 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2248 | #[allow(improper_ctypes)] | |
2249 | extern "C" { | |
2250 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfp2fxs.v1i64.v1f64")] | |
2251 | fn vcvt_n_s64_f64_(a: float64x1_t, n: i32) -> int64x1_t; | |
2252 | } | |
2253 | vcvt_n_s64_f64_(a, N) | |
2254 | } | |
2255 | ||
2256 | /// Floating-point convert to fixed-point, rounding toward zero | |
2257 | #[inline] | |
2258 | #[target_feature(enable = "neon")] | |
2259 | #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] | |
2260 | #[rustc_legacy_const_generics(1)] | |
2261 | pub unsafe fn vcvtq_n_s64_f64<const N: i32>(a: float64x2_t) -> int64x2_t { | |
2262 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2263 | #[allow(improper_ctypes)] | |
2264 | extern "C" { | |
2265 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfp2fxs.v2i64.v2f64")] | |
2266 | fn vcvtq_n_s64_f64_(a: float64x2_t, n: i32) -> int64x2_t; | |
2267 | } | |
2268 | vcvtq_n_s64_f64_(a, N) | |
2269 | } | |
2270 | ||
2271 | /// Floating-point convert to fixed-point, rounding toward zero | |
2272 | #[inline] | |
2273 | #[target_feature(enable = "neon")] | |
2274 | #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] | |
2275 | #[rustc_legacy_const_generics(1)] | |
2276 | pub unsafe fn vcvts_n_s32_f32<const N: i32>(a: f32) -> i32 { | |
2277 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
2278 | #[allow(improper_ctypes)] | |
2279 | extern "C" { | |
2280 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfp2fxs.i32.f32")] | |
2281 | fn vcvts_n_s32_f32_(a: f32, n: i32) -> i32; | |
2282 | } | |
2283 | vcvts_n_s32_f32_(a, N) | |
2284 | } | |
2285 | ||
2286 | /// Floating-point convert to fixed-point, rounding toward zero | |
2287 | #[inline] | |
2288 | #[target_feature(enable = "neon")] | |
2289 | #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] | |
2290 | #[rustc_legacy_const_generics(1)] | |
2291 | pub unsafe fn vcvtd_n_s64_f64<const N: i32>(a: f64) -> i64 { | |
2292 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2293 | #[allow(improper_ctypes)] | |
2294 | extern "C" { | |
2295 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfp2fxs.i64.f64")] | |
2296 | fn vcvtd_n_s64_f64_(a: f64, n: i32) -> i64; | |
2297 | } | |
2298 | vcvtd_n_s64_f64_(a, N) | |
2299 | } | |
2300 | ||
2301 | /// Floating-point convert to fixed-point, rounding toward zero | |
2302 | #[inline] | |
2303 | #[target_feature(enable = "neon")] | |
2304 | #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] | |
2305 | #[rustc_legacy_const_generics(1)] | |
2306 | pub unsafe fn vcvt_n_u64_f64<const N: i32>(a: float64x1_t) -> uint64x1_t { | |
2307 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2308 | #[allow(improper_ctypes)] | |
2309 | extern "C" { | |
2310 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfp2fxu.v1i64.v1f64")] | |
2311 | fn vcvt_n_u64_f64_(a: float64x1_t, n: i32) -> uint64x1_t; | |
2312 | } | |
2313 | vcvt_n_u64_f64_(a, N) | |
2314 | } | |
2315 | ||
2316 | /// Floating-point convert to fixed-point, rounding toward zero | |
2317 | #[inline] | |
2318 | #[target_feature(enable = "neon")] | |
2319 | #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] | |
2320 | #[rustc_legacy_const_generics(1)] | |
2321 | pub unsafe fn vcvtq_n_u64_f64<const N: i32>(a: float64x2_t) -> uint64x2_t { | |
2322 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2323 | #[allow(improper_ctypes)] | |
2324 | extern "C" { | |
2325 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfp2fxu.v2i64.v2f64")] | |
2326 | fn vcvtq_n_u64_f64_(a: float64x2_t, n: i32) -> uint64x2_t; | |
2327 | } | |
2328 | vcvtq_n_u64_f64_(a, N) | |
2329 | } | |
2330 | ||
2331 | /// Floating-point convert to fixed-point, rounding toward zero | |
2332 | #[inline] | |
2333 | #[target_feature(enable = "neon")] | |
2334 | #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] | |
2335 | #[rustc_legacy_const_generics(1)] | |
2336 | pub unsafe fn vcvts_n_u32_f32<const N: i32>(a: f32) -> u32 { | |
2337 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
2338 | #[allow(improper_ctypes)] | |
2339 | extern "C" { | |
2340 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfp2fxu.i32.f32")] | |
2341 | fn vcvts_n_u32_f32_(a: f32, n: i32) -> u32; | |
2342 | } | |
2343 | vcvts_n_u32_f32_(a, N) | |
2344 | } | |
2345 | ||
2346 | /// Floating-point convert to fixed-point, rounding toward zero | |
2347 | #[inline] | |
2348 | #[target_feature(enable = "neon")] | |
2349 | #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] | |
2350 | #[rustc_legacy_const_generics(1)] | |
2351 | pub unsafe fn vcvtd_n_u64_f64<const N: i32>(a: f64) -> u64 { | |
2352 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2353 | #[allow(improper_ctypes)] | |
2354 | extern "C" { | |
2355 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfp2fxu.i64.f64")] | |
2356 | fn vcvtd_n_u64_f64_(a: f64, n: i32) -> u64; | |
2357 | } | |
2358 | vcvtd_n_u64_f64_(a, N) | |
2359 | } | |
2360 | ||
2361 | /// Fixed-point convert to floating-point | |
2362 | #[inline] | |
2363 | #[target_feature(enable = "neon")] | |
2364 | #[cfg_attr(test, assert_instr(scvtf))] | |
2365 | pub unsafe fn vcvts_f32_s32(a: i32) -> f32 { | |
2366 | a as f32 | |
2367 | } | |
2368 | ||
2369 | /// Fixed-point convert to floating-point | |
2370 | #[inline] | |
2371 | #[target_feature(enable = "neon")] | |
2372 | #[cfg_attr(test, assert_instr(scvtf))] | |
2373 | pub unsafe fn vcvtd_f64_s64(a: i64) -> f64 { | |
2374 | a as f64 | |
2375 | } | |
2376 | ||
2377 | /// Fixed-point convert to floating-point | |
2378 | #[inline] | |
2379 | #[target_feature(enable = "neon")] | |
2380 | #[cfg_attr(test, assert_instr(ucvtf))] | |
2381 | pub unsafe fn vcvts_f32_u32(a: u32) -> f32 { | |
2382 | a as f32 | |
2383 | } | |
2384 | ||
2385 | /// Fixed-point convert to floating-point | |
2386 | #[inline] | |
2387 | #[target_feature(enable = "neon")] | |
2388 | #[cfg_attr(test, assert_instr(ucvtf))] | |
2389 | pub unsafe fn vcvtd_f64_u64(a: u64) -> f64 { | |
2390 | a as f64 | |
2391 | } | |
2392 | ||
2393 | /// Fixed-point convert to floating-point | |
2394 | #[inline] | |
2395 | #[target_feature(enable = "neon")] | |
2396 | #[cfg_attr(test, assert_instr(fcvtzs))] | |
2397 | pub unsafe fn vcvts_s32_f32(a: f32) -> i32 { | |
2398 | a as i32 | |
2399 | } | |
2400 | ||
2401 | /// Fixed-point convert to floating-point | |
2402 | #[inline] | |
2403 | #[target_feature(enable = "neon")] | |
2404 | #[cfg_attr(test, assert_instr(fcvtzs))] | |
2405 | pub unsafe fn vcvtd_s64_f64(a: f64) -> i64 { | |
2406 | a as i64 | |
2407 | } | |
2408 | ||
2409 | /// Fixed-point convert to floating-point | |
2410 | #[inline] | |
2411 | #[target_feature(enable = "neon")] | |
2412 | #[cfg_attr(test, assert_instr(fcvtzu))] | |
2413 | pub unsafe fn vcvts_u32_f32(a: f32) -> u32 { | |
2414 | a as u32 | |
2415 | } | |
2416 | ||
2417 | /// Fixed-point convert to floating-point | |
2418 | #[inline] | |
2419 | #[target_feature(enable = "neon")] | |
2420 | #[cfg_attr(test, assert_instr(fcvtzu))] | |
2421 | pub unsafe fn vcvtd_u64_f64(a: f64) -> u64 { | |
2422 | a as u64 | |
2423 | } | |
2424 | ||
2425 | /// Floating-point convert to signed fixed-point, rounding toward zero | |
2426 | #[inline] | |
2427 | #[target_feature(enable = "neon")] | |
2428 | #[cfg_attr(test, assert_instr(fcvtzs))] | |
2429 | pub unsafe fn vcvt_s64_f64(a: float64x1_t) -> int64x1_t { | |
2430 | simd_cast(a) | |
2431 | } | |
2432 | ||
2433 | /// Floating-point convert to signed fixed-point, rounding toward zero | |
2434 | #[inline] | |
2435 | #[target_feature(enable = "neon")] | |
2436 | #[cfg_attr(test, assert_instr(fcvtzs))] | |
2437 | pub unsafe fn vcvtq_s64_f64(a: float64x2_t) -> int64x2_t { | |
2438 | simd_cast(a) | |
2439 | } | |
2440 | ||
2441 | /// Floating-point convert to unsigned fixed-point, rounding toward zero | |
2442 | #[inline] | |
2443 | #[target_feature(enable = "neon")] | |
2444 | #[cfg_attr(test, assert_instr(fcvtzu))] | |
2445 | pub unsafe fn vcvt_u64_f64(a: float64x1_t) -> uint64x1_t { | |
2446 | simd_cast(a) | |
2447 | } | |
2448 | ||
2449 | /// Floating-point convert to unsigned fixed-point, rounding toward zero | |
2450 | #[inline] | |
2451 | #[target_feature(enable = "neon")] | |
2452 | #[cfg_attr(test, assert_instr(fcvtzu))] | |
2453 | pub unsafe fn vcvtq_u64_f64(a: float64x2_t) -> uint64x2_t { | |
2454 | simd_cast(a) | |
2455 | } | |
2456 | ||
2457 | /// Floating-point convert to signed integer, rounding to nearest with ties to away | |
2458 | #[inline] | |
2459 | #[target_feature(enable = "neon")] | |
2460 | #[cfg_attr(test, assert_instr(fcvtas))] | |
2461 | pub unsafe fn vcvta_s32_f32(a: float32x2_t) -> int32x2_t { | |
2462 | #[allow(improper_ctypes)] | |
2463 | extern "C" { | |
2464 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtas.v2i32.v2f32")] | |
2465 | fn vcvta_s32_f32_(a: float32x2_t) -> int32x2_t; | |
2466 | } | |
2467 | vcvta_s32_f32_(a) | |
2468 | } | |
2469 | ||
2470 | /// Floating-point convert to signed integer, rounding to nearest with ties to away | |
2471 | #[inline] | |
2472 | #[target_feature(enable = "neon")] | |
2473 | #[cfg_attr(test, assert_instr(fcvtas))] | |
2474 | pub unsafe fn vcvtaq_s32_f32(a: float32x4_t) -> int32x4_t { | |
2475 | #[allow(improper_ctypes)] | |
2476 | extern "C" { | |
2477 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtas.v4i32.v4f32")] | |
2478 | fn vcvtaq_s32_f32_(a: float32x4_t) -> int32x4_t; | |
2479 | } | |
2480 | vcvtaq_s32_f32_(a) | |
2481 | } | |
2482 | ||
2483 | /// Floating-point convert to signed integer, rounding to nearest with ties to away | |
2484 | #[inline] | |
2485 | #[target_feature(enable = "neon")] | |
2486 | #[cfg_attr(test, assert_instr(fcvtas))] | |
2487 | pub unsafe fn vcvta_s64_f64(a: float64x1_t) -> int64x1_t { | |
2488 | #[allow(improper_ctypes)] | |
2489 | extern "C" { | |
2490 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtas.v1i64.v1f64")] | |
2491 | fn vcvta_s64_f64_(a: float64x1_t) -> int64x1_t; | |
2492 | } | |
2493 | vcvta_s64_f64_(a) | |
2494 | } | |
2495 | ||
2496 | /// Floating-point convert to signed integer, rounding to nearest with ties to away | |
2497 | #[inline] | |
2498 | #[target_feature(enable = "neon")] | |
2499 | #[cfg_attr(test, assert_instr(fcvtas))] | |
2500 | pub unsafe fn vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t { | |
2501 | #[allow(improper_ctypes)] | |
2502 | extern "C" { | |
2503 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtas.v2i64.v2f64")] | |
2504 | fn vcvtaq_s64_f64_(a: float64x2_t) -> int64x2_t; | |
2505 | } | |
2506 | vcvtaq_s64_f64_(a) | |
2507 | } | |
2508 | ||
2509 | /// Floating-point convert to integer, rounding to nearest with ties to away | |
2510 | #[inline] | |
2511 | #[target_feature(enable = "neon")] | |
2512 | #[cfg_attr(test, assert_instr(fcvtas))] | |
2513 | pub unsafe fn vcvtas_s32_f32(a: f32) -> i32 { | |
2514 | #[allow(improper_ctypes)] | |
2515 | extern "C" { | |
2516 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtas.i32.f32")] | |
2517 | fn vcvtas_s32_f32_(a: f32) -> i32; | |
2518 | } | |
2519 | vcvtas_s32_f32_(a) | |
2520 | } | |
2521 | ||
2522 | /// Floating-point convert to integer, rounding to nearest with ties to away | |
2523 | #[inline] | |
2524 | #[target_feature(enable = "neon")] | |
2525 | #[cfg_attr(test, assert_instr(fcvtas))] | |
2526 | pub unsafe fn vcvtad_s64_f64(a: f64) -> i64 { | |
2527 | #[allow(improper_ctypes)] | |
2528 | extern "C" { | |
2529 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtas.i64.f64")] | |
2530 | fn vcvtad_s64_f64_(a: f64) -> i64; | |
2531 | } | |
2532 | vcvtad_s64_f64_(a) | |
2533 | } | |
2534 | ||
2535 | /// Floating-point convert to integer, rounding to nearest with ties to away | |
2536 | #[inline] | |
2537 | #[target_feature(enable = "neon")] | |
2538 | #[cfg_attr(test, assert_instr(fcvtau))] | |
2539 | pub unsafe fn vcvtas_u32_f32(a: f32) -> u32 { | |
2540 | #[allow(improper_ctypes)] | |
2541 | extern "C" { | |
2542 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtau.i32.f32")] | |
2543 | fn vcvtas_u32_f32_(a: f32) -> u32; | |
2544 | } | |
2545 | vcvtas_u32_f32_(a) | |
2546 | } | |
2547 | ||
2548 | /// Floating-point convert to integer, rounding to nearest with ties to away | |
2549 | #[inline] | |
2550 | #[target_feature(enable = "neon")] | |
2551 | #[cfg_attr(test, assert_instr(fcvtau))] | |
2552 | pub unsafe fn vcvtad_u64_f64(a: f64) -> u64 { | |
2553 | #[allow(improper_ctypes)] | |
2554 | extern "C" { | |
2555 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtau.i64.f64")] | |
2556 | fn vcvtad_u64_f64_(a: f64) -> u64; | |
2557 | } | |
2558 | vcvtad_u64_f64_(a) | |
2559 | } | |
2560 | ||
2561 | /// Floating-point convert to signed integer, rounding to nearest with ties to even | |
2562 | #[inline] | |
2563 | #[target_feature(enable = "neon")] | |
2564 | #[cfg_attr(test, assert_instr(fcvtns))] | |
2565 | pub unsafe fn vcvtn_s32_f32(a: float32x2_t) -> int32x2_t { | |
2566 | #[allow(improper_ctypes)] | |
2567 | extern "C" { | |
2568 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtns.v2i32.v2f32")] | |
2569 | fn vcvtn_s32_f32_(a: float32x2_t) -> int32x2_t; | |
2570 | } | |
2571 | vcvtn_s32_f32_(a) | |
2572 | } | |
2573 | ||
2574 | /// Floating-point convert to signed integer, rounding to nearest with ties to even | |
2575 | #[inline] | |
2576 | #[target_feature(enable = "neon")] | |
2577 | #[cfg_attr(test, assert_instr(fcvtns))] | |
2578 | pub unsafe fn vcvtnq_s32_f32(a: float32x4_t) -> int32x4_t { | |
2579 | #[allow(improper_ctypes)] | |
2580 | extern "C" { | |
2581 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtns.v4i32.v4f32")] | |
2582 | fn vcvtnq_s32_f32_(a: float32x4_t) -> int32x4_t; | |
2583 | } | |
2584 | vcvtnq_s32_f32_(a) | |
2585 | } | |
2586 | ||
2587 | /// Floating-point convert to signed integer, rounding to nearest with ties to even | |
2588 | #[inline] | |
2589 | #[target_feature(enable = "neon")] | |
2590 | #[cfg_attr(test, assert_instr(fcvtns))] | |
2591 | pub unsafe fn vcvtn_s64_f64(a: float64x1_t) -> int64x1_t { | |
2592 | #[allow(improper_ctypes)] | |
2593 | extern "C" { | |
2594 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtns.v1i64.v1f64")] | |
2595 | fn vcvtn_s64_f64_(a: float64x1_t) -> int64x1_t; | |
2596 | } | |
2597 | vcvtn_s64_f64_(a) | |
2598 | } | |
2599 | ||
2600 | /// Floating-point convert to signed integer, rounding to nearest with ties to even | |
2601 | #[inline] | |
2602 | #[target_feature(enable = "neon")] | |
2603 | #[cfg_attr(test, assert_instr(fcvtns))] | |
2604 | pub unsafe fn vcvtnq_s64_f64(a: float64x2_t) -> int64x2_t { | |
2605 | #[allow(improper_ctypes)] | |
2606 | extern "C" { | |
2607 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtns.v2i64.v2f64")] | |
2608 | fn vcvtnq_s64_f64_(a: float64x2_t) -> int64x2_t; | |
2609 | } | |
2610 | vcvtnq_s64_f64_(a) | |
2611 | } | |
2612 | ||
2613 | /// Floating-point convert to signed integer, rounding to nearest with ties to even | |
2614 | #[inline] | |
2615 | #[target_feature(enable = "neon")] | |
2616 | #[cfg_attr(test, assert_instr(fcvtns))] | |
2617 | pub unsafe fn vcvtns_s32_f32(a: f32) -> i32 { | |
2618 | #[allow(improper_ctypes)] | |
2619 | extern "C" { | |
2620 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtns.i32.f32")] | |
2621 | fn vcvtns_s32_f32_(a: f32) -> i32; | |
2622 | } | |
2623 | vcvtns_s32_f32_(a) | |
2624 | } | |
2625 | ||
2626 | /// Floating-point convert to signed integer, rounding to nearest with ties to even | |
2627 | #[inline] | |
2628 | #[target_feature(enable = "neon")] | |
2629 | #[cfg_attr(test, assert_instr(fcvtns))] | |
2630 | pub unsafe fn vcvtnd_s64_f64(a: f64) -> i64 { | |
2631 | #[allow(improper_ctypes)] | |
2632 | extern "C" { | |
2633 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtns.i64.f64")] | |
2634 | fn vcvtnd_s64_f64_(a: f64) -> i64; | |
2635 | } | |
2636 | vcvtnd_s64_f64_(a) | |
2637 | } | |
2638 | ||
2639 | /// Floating-point convert to signed integer, rounding toward minus infinity | |
2640 | #[inline] | |
2641 | #[target_feature(enable = "neon")] | |
2642 | #[cfg_attr(test, assert_instr(fcvtms))] | |
2643 | pub unsafe fn vcvtm_s32_f32(a: float32x2_t) -> int32x2_t { | |
2644 | #[allow(improper_ctypes)] | |
2645 | extern "C" { | |
2646 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtms.v2i32.v2f32")] | |
2647 | fn vcvtm_s32_f32_(a: float32x2_t) -> int32x2_t; | |
2648 | } | |
2649 | vcvtm_s32_f32_(a) | |
2650 | } | |
2651 | ||
2652 | /// Floating-point convert to signed integer, rounding toward minus infinity | |
2653 | #[inline] | |
2654 | #[target_feature(enable = "neon")] | |
2655 | #[cfg_attr(test, assert_instr(fcvtms))] | |
2656 | pub unsafe fn vcvtmq_s32_f32(a: float32x4_t) -> int32x4_t { | |
2657 | #[allow(improper_ctypes)] | |
2658 | extern "C" { | |
2659 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtms.v4i32.v4f32")] | |
2660 | fn vcvtmq_s32_f32_(a: float32x4_t) -> int32x4_t; | |
2661 | } | |
2662 | vcvtmq_s32_f32_(a) | |
2663 | } | |
2664 | ||
2665 | /// Floating-point convert to signed integer, rounding toward minus infinity | |
2666 | #[inline] | |
2667 | #[target_feature(enable = "neon")] | |
2668 | #[cfg_attr(test, assert_instr(fcvtms))] | |
2669 | pub unsafe fn vcvtm_s64_f64(a: float64x1_t) -> int64x1_t { | |
2670 | #[allow(improper_ctypes)] | |
2671 | extern "C" { | |
2672 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtms.v1i64.v1f64")] | |
2673 | fn vcvtm_s64_f64_(a: float64x1_t) -> int64x1_t; | |
2674 | } | |
2675 | vcvtm_s64_f64_(a) | |
2676 | } | |
2677 | ||
2678 | /// Floating-point convert to signed integer, rounding toward minus infinity | |
2679 | #[inline] | |
2680 | #[target_feature(enable = "neon")] | |
2681 | #[cfg_attr(test, assert_instr(fcvtms))] | |
2682 | pub unsafe fn vcvtmq_s64_f64(a: float64x2_t) -> int64x2_t { | |
2683 | #[allow(improper_ctypes)] | |
2684 | extern "C" { | |
2685 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtms.v2i64.v2f64")] | |
2686 | fn vcvtmq_s64_f64_(a: float64x2_t) -> int64x2_t; | |
2687 | } | |
2688 | vcvtmq_s64_f64_(a) | |
2689 | } | |
2690 | ||
2691 | /// Floating-point convert to signed integer, rounding toward minus infinity | |
2692 | #[inline] | |
2693 | #[target_feature(enable = "neon")] | |
2694 | #[cfg_attr(test, assert_instr(fcvtms))] | |
2695 | pub unsafe fn vcvtms_s32_f32(a: f32) -> i32 { | |
2696 | #[allow(improper_ctypes)] | |
2697 | extern "C" { | |
2698 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtms.i32.f32")] | |
2699 | fn vcvtms_s32_f32_(a: f32) -> i32; | |
2700 | } | |
2701 | vcvtms_s32_f32_(a) | |
2702 | } | |
2703 | ||
2704 | /// Floating-point convert to signed integer, rounding toward minus infinity | |
2705 | #[inline] | |
2706 | #[target_feature(enable = "neon")] | |
2707 | #[cfg_attr(test, assert_instr(fcvtms))] | |
2708 | pub unsafe fn vcvtmd_s64_f64(a: f64) -> i64 { | |
2709 | #[allow(improper_ctypes)] | |
2710 | extern "C" { | |
2711 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtms.i64.f64")] | |
2712 | fn vcvtmd_s64_f64_(a: f64) -> i64; | |
2713 | } | |
2714 | vcvtmd_s64_f64_(a) | |
2715 | } | |
2716 | ||
2717 | /// Floating-point convert to signed integer, rounding toward plus infinity | |
2718 | #[inline] | |
2719 | #[target_feature(enable = "neon")] | |
2720 | #[cfg_attr(test, assert_instr(fcvtps))] | |
2721 | pub unsafe fn vcvtp_s32_f32(a: float32x2_t) -> int32x2_t { | |
2722 | #[allow(improper_ctypes)] | |
2723 | extern "C" { | |
2724 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtps.v2i32.v2f32")] | |
2725 | fn vcvtp_s32_f32_(a: float32x2_t) -> int32x2_t; | |
2726 | } | |
2727 | vcvtp_s32_f32_(a) | |
2728 | } | |
2729 | ||
2730 | /// Floating-point convert to signed integer, rounding toward plus infinity | |
2731 | #[inline] | |
2732 | #[target_feature(enable = "neon")] | |
2733 | #[cfg_attr(test, assert_instr(fcvtps))] | |
2734 | pub unsafe fn vcvtpq_s32_f32(a: float32x4_t) -> int32x4_t { | |
2735 | #[allow(improper_ctypes)] | |
2736 | extern "C" { | |
2737 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtps.v4i32.v4f32")] | |
2738 | fn vcvtpq_s32_f32_(a: float32x4_t) -> int32x4_t; | |
2739 | } | |
2740 | vcvtpq_s32_f32_(a) | |
2741 | } | |
2742 | ||
2743 | /// Floating-point convert to signed integer, rounding toward plus infinity | |
2744 | #[inline] | |
2745 | #[target_feature(enable = "neon")] | |
2746 | #[cfg_attr(test, assert_instr(fcvtps))] | |
2747 | pub unsafe fn vcvtp_s64_f64(a: float64x1_t) -> int64x1_t { | |
2748 | #[allow(improper_ctypes)] | |
2749 | extern "C" { | |
2750 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtps.v1i64.v1f64")] | |
2751 | fn vcvtp_s64_f64_(a: float64x1_t) -> int64x1_t; | |
2752 | } | |
2753 | vcvtp_s64_f64_(a) | |
2754 | } | |
2755 | ||
2756 | /// Floating-point convert to signed integer, rounding toward plus infinity | |
2757 | #[inline] | |
2758 | #[target_feature(enable = "neon")] | |
2759 | #[cfg_attr(test, assert_instr(fcvtps))] | |
2760 | pub unsafe fn vcvtpq_s64_f64(a: float64x2_t) -> int64x2_t { | |
2761 | #[allow(improper_ctypes)] | |
2762 | extern "C" { | |
2763 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtps.v2i64.v2f64")] | |
2764 | fn vcvtpq_s64_f64_(a: float64x2_t) -> int64x2_t; | |
2765 | } | |
2766 | vcvtpq_s64_f64_(a) | |
2767 | } | |
2768 | ||
2769 | /// Floating-point convert to signed integer, rounding toward plus infinity | |
2770 | #[inline] | |
2771 | #[target_feature(enable = "neon")] | |
2772 | #[cfg_attr(test, assert_instr(fcvtps))] | |
2773 | pub unsafe fn vcvtps_s32_f32(a: f32) -> i32 { | |
2774 | #[allow(improper_ctypes)] | |
2775 | extern "C" { | |
2776 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtps.i32.f32")] | |
2777 | fn vcvtps_s32_f32_(a: f32) -> i32; | |
2778 | } | |
2779 | vcvtps_s32_f32_(a) | |
2780 | } | |
2781 | ||
2782 | /// Floating-point convert to signed integer, rounding toward plus infinity | |
2783 | #[inline] | |
2784 | #[target_feature(enable = "neon")] | |
2785 | #[cfg_attr(test, assert_instr(fcvtps))] | |
2786 | pub unsafe fn vcvtpd_s64_f64(a: f64) -> i64 { | |
2787 | #[allow(improper_ctypes)] | |
2788 | extern "C" { | |
2789 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtps.i64.f64")] | |
2790 | fn vcvtpd_s64_f64_(a: f64) -> i64; | |
2791 | } | |
2792 | vcvtpd_s64_f64_(a) | |
2793 | } | |
2794 | ||
2795 | /// Floating-point convert to unsigned integer, rounding to nearest with ties to away | |
2796 | #[inline] | |
2797 | #[target_feature(enable = "neon")] | |
2798 | #[cfg_attr(test, assert_instr(fcvtau))] | |
2799 | pub unsafe fn vcvta_u32_f32(a: float32x2_t) -> uint32x2_t { | |
2800 | #[allow(improper_ctypes)] | |
2801 | extern "C" { | |
2802 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtau.v2i32.v2f32")] | |
2803 | fn vcvta_u32_f32_(a: float32x2_t) -> uint32x2_t; | |
2804 | } | |
2805 | vcvta_u32_f32_(a) | |
2806 | } | |
2807 | ||
2808 | /// Floating-point convert to unsigned integer, rounding to nearest with ties to away | |
2809 | #[inline] | |
2810 | #[target_feature(enable = "neon")] | |
2811 | #[cfg_attr(test, assert_instr(fcvtau))] | |
2812 | pub unsafe fn vcvtaq_u32_f32(a: float32x4_t) -> uint32x4_t { | |
2813 | #[allow(improper_ctypes)] | |
2814 | extern "C" { | |
2815 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtau.v4i32.v4f32")] | |
2816 | fn vcvtaq_u32_f32_(a: float32x4_t) -> uint32x4_t; | |
2817 | } | |
2818 | vcvtaq_u32_f32_(a) | |
2819 | } | |
2820 | ||
2821 | /// Floating-point convert to unsigned integer, rounding to nearest with ties to away | |
2822 | #[inline] | |
2823 | #[target_feature(enable = "neon")] | |
2824 | #[cfg_attr(test, assert_instr(fcvtau))] | |
2825 | pub unsafe fn vcvta_u64_f64(a: float64x1_t) -> uint64x1_t { | |
2826 | #[allow(improper_ctypes)] | |
2827 | extern "C" { | |
2828 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtau.v1i64.v1f64")] | |
2829 | fn vcvta_u64_f64_(a: float64x1_t) -> uint64x1_t; | |
2830 | } | |
2831 | vcvta_u64_f64_(a) | |
2832 | } | |
2833 | ||
2834 | /// Floating-point convert to unsigned integer, rounding to nearest with ties to away | |
2835 | #[inline] | |
2836 | #[target_feature(enable = "neon")] | |
2837 | #[cfg_attr(test, assert_instr(fcvtau))] | |
2838 | pub unsafe fn vcvtaq_u64_f64(a: float64x2_t) -> uint64x2_t { | |
2839 | #[allow(improper_ctypes)] | |
2840 | extern "C" { | |
2841 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtau.v2i64.v2f64")] | |
2842 | fn vcvtaq_u64_f64_(a: float64x2_t) -> uint64x2_t; | |
2843 | } | |
2844 | vcvtaq_u64_f64_(a) | |
2845 | } | |
2846 | ||
2847 | /// Floating-point convert to unsigned integer, rounding to nearest with ties to even | |
2848 | #[inline] | |
2849 | #[target_feature(enable = "neon")] | |
2850 | #[cfg_attr(test, assert_instr(fcvtnu))] | |
2851 | pub unsafe fn vcvtn_u32_f32(a: float32x2_t) -> uint32x2_t { | |
2852 | #[allow(improper_ctypes)] | |
2853 | extern "C" { | |
2854 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtnu.v2i32.v2f32")] | |
2855 | fn vcvtn_u32_f32_(a: float32x2_t) -> uint32x2_t; | |
2856 | } | |
2857 | vcvtn_u32_f32_(a) | |
2858 | } | |
2859 | ||
2860 | /// Floating-point convert to unsigned integer, rounding to nearest with ties to even | |
2861 | #[inline] | |
2862 | #[target_feature(enable = "neon")] | |
2863 | #[cfg_attr(test, assert_instr(fcvtnu))] | |
2864 | pub unsafe fn vcvtnq_u32_f32(a: float32x4_t) -> uint32x4_t { | |
2865 | #[allow(improper_ctypes)] | |
2866 | extern "C" { | |
2867 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtnu.v4i32.v4f32")] | |
2868 | fn vcvtnq_u32_f32_(a: float32x4_t) -> uint32x4_t; | |
2869 | } | |
2870 | vcvtnq_u32_f32_(a) | |
2871 | } | |
2872 | ||
2873 | /// Floating-point convert to unsigned integer, rounding to nearest with ties to even | |
2874 | #[inline] | |
2875 | #[target_feature(enable = "neon")] | |
2876 | #[cfg_attr(test, assert_instr(fcvtnu))] | |
2877 | pub unsafe fn vcvtn_u64_f64(a: float64x1_t) -> uint64x1_t { | |
2878 | #[allow(improper_ctypes)] | |
2879 | extern "C" { | |
2880 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtnu.v1i64.v1f64")] | |
2881 | fn vcvtn_u64_f64_(a: float64x1_t) -> uint64x1_t; | |
2882 | } | |
2883 | vcvtn_u64_f64_(a) | |
2884 | } | |
2885 | ||
2886 | /// Floating-point convert to unsigned integer, rounding to nearest with ties to even | |
2887 | #[inline] | |
2888 | #[target_feature(enable = "neon")] | |
2889 | #[cfg_attr(test, assert_instr(fcvtnu))] | |
2890 | pub unsafe fn vcvtnq_u64_f64(a: float64x2_t) -> uint64x2_t { | |
2891 | #[allow(improper_ctypes)] | |
2892 | extern "C" { | |
2893 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtnu.v2i64.v2f64")] | |
2894 | fn vcvtnq_u64_f64_(a: float64x2_t) -> uint64x2_t; | |
2895 | } | |
2896 | vcvtnq_u64_f64_(a) | |
2897 | } | |
2898 | ||
2899 | /// Floating-point convert to unsigned integer, rounding to nearest with ties to even | |
2900 | #[inline] | |
2901 | #[target_feature(enable = "neon")] | |
2902 | #[cfg_attr(test, assert_instr(fcvtnu))] | |
2903 | pub unsafe fn vcvtns_u32_f32(a: f32) -> u32 { | |
2904 | #[allow(improper_ctypes)] | |
2905 | extern "C" { | |
2906 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtnu.i32.f32")] | |
2907 | fn vcvtns_u32_f32_(a: f32) -> u32; | |
2908 | } | |
2909 | vcvtns_u32_f32_(a) | |
2910 | } | |
2911 | ||
2912 | /// Floating-point convert to unsigned integer, rounding to nearest with ties to even | |
2913 | #[inline] | |
2914 | #[target_feature(enable = "neon")] | |
2915 | #[cfg_attr(test, assert_instr(fcvtnu))] | |
2916 | pub unsafe fn vcvtnd_u64_f64(a: f64) -> u64 { | |
2917 | #[allow(improper_ctypes)] | |
2918 | extern "C" { | |
2919 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtnu.i64.f64")] | |
2920 | fn vcvtnd_u64_f64_(a: f64) -> u64; | |
2921 | } | |
2922 | vcvtnd_u64_f64_(a) | |
2923 | } | |
2924 | ||
2925 | /// Floating-point convert to unsigned integer, rounding toward minus infinity | |
2926 | #[inline] | |
2927 | #[target_feature(enable = "neon")] | |
2928 | #[cfg_attr(test, assert_instr(fcvtmu))] | |
2929 | pub unsafe fn vcvtm_u32_f32(a: float32x2_t) -> uint32x2_t { | |
2930 | #[allow(improper_ctypes)] | |
2931 | extern "C" { | |
2932 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtmu.v2i32.v2f32")] | |
2933 | fn vcvtm_u32_f32_(a: float32x2_t) -> uint32x2_t; | |
2934 | } | |
2935 | vcvtm_u32_f32_(a) | |
2936 | } | |
2937 | ||
2938 | /// Floating-point convert to unsigned integer, rounding toward minus infinity | |
2939 | #[inline] | |
2940 | #[target_feature(enable = "neon")] | |
2941 | #[cfg_attr(test, assert_instr(fcvtmu))] | |
2942 | pub unsafe fn vcvtmq_u32_f32(a: float32x4_t) -> uint32x4_t { | |
2943 | #[allow(improper_ctypes)] | |
2944 | extern "C" { | |
2945 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtmu.v4i32.v4f32")] | |
2946 | fn vcvtmq_u32_f32_(a: float32x4_t) -> uint32x4_t; | |
2947 | } | |
2948 | vcvtmq_u32_f32_(a) | |
2949 | } | |
2950 | ||
2951 | /// Floating-point convert to unsigned integer, rounding toward minus infinity | |
2952 | #[inline] | |
2953 | #[target_feature(enable = "neon")] | |
2954 | #[cfg_attr(test, assert_instr(fcvtmu))] | |
2955 | pub unsafe fn vcvtm_u64_f64(a: float64x1_t) -> uint64x1_t { | |
2956 | #[allow(improper_ctypes)] | |
2957 | extern "C" { | |
2958 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtmu.v1i64.v1f64")] | |
2959 | fn vcvtm_u64_f64_(a: float64x1_t) -> uint64x1_t; | |
2960 | } | |
2961 | vcvtm_u64_f64_(a) | |
2962 | } | |
2963 | ||
2964 | /// Floating-point convert to unsigned integer, rounding toward minus infinity | |
2965 | #[inline] | |
2966 | #[target_feature(enable = "neon")] | |
2967 | #[cfg_attr(test, assert_instr(fcvtmu))] | |
2968 | pub unsafe fn vcvtmq_u64_f64(a: float64x2_t) -> uint64x2_t { | |
2969 | #[allow(improper_ctypes)] | |
2970 | extern "C" { | |
2971 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtmu.v2i64.v2f64")] | |
2972 | fn vcvtmq_u64_f64_(a: float64x2_t) -> uint64x2_t; | |
2973 | } | |
2974 | vcvtmq_u64_f64_(a) | |
2975 | } | |
2976 | ||
2977 | /// Floating-point convert to unsigned integer, rounding toward minus infinity | |
2978 | #[inline] | |
2979 | #[target_feature(enable = "neon")] | |
2980 | #[cfg_attr(test, assert_instr(fcvtmu))] | |
2981 | pub unsafe fn vcvtms_u32_f32(a: f32) -> u32 { | |
2982 | #[allow(improper_ctypes)] | |
2983 | extern "C" { | |
2984 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtmu.i32.f32")] | |
2985 | fn vcvtms_u32_f32_(a: f32) -> u32; | |
2986 | } | |
2987 | vcvtms_u32_f32_(a) | |
2988 | } | |
2989 | ||
2990 | /// Floating-point convert to unsigned integer, rounding toward minus infinity | |
2991 | #[inline] | |
2992 | #[target_feature(enable = "neon")] | |
2993 | #[cfg_attr(test, assert_instr(fcvtmu))] | |
2994 | pub unsafe fn vcvtmd_u64_f64(a: f64) -> u64 { | |
2995 | #[allow(improper_ctypes)] | |
2996 | extern "C" { | |
2997 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtmu.i64.f64")] | |
2998 | fn vcvtmd_u64_f64_(a: f64) -> u64; | |
2999 | } | |
3000 | vcvtmd_u64_f64_(a) | |
3001 | } | |
3002 | ||
3003 | /// Floating-point convert to unsigned integer, rounding toward plus infinity | |
3004 | #[inline] | |
3005 | #[target_feature(enable = "neon")] | |
3006 | #[cfg_attr(test, assert_instr(fcvtpu))] | |
3007 | pub unsafe fn vcvtp_u32_f32(a: float32x2_t) -> uint32x2_t { | |
3008 | #[allow(improper_ctypes)] | |
3009 | extern "C" { | |
3010 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtpu.v2i32.v2f32")] | |
3011 | fn vcvtp_u32_f32_(a: float32x2_t) -> uint32x2_t; | |
3012 | } | |
3013 | vcvtp_u32_f32_(a) | |
3014 | } | |
3015 | ||
3016 | /// Floating-point convert to unsigned integer, rounding toward plus infinity | |
3017 | #[inline] | |
3018 | #[target_feature(enable = "neon")] | |
3019 | #[cfg_attr(test, assert_instr(fcvtpu))] | |
3020 | pub unsafe fn vcvtpq_u32_f32(a: float32x4_t) -> uint32x4_t { | |
3021 | #[allow(improper_ctypes)] | |
3022 | extern "C" { | |
3023 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtpu.v4i32.v4f32")] | |
3024 | fn vcvtpq_u32_f32_(a: float32x4_t) -> uint32x4_t; | |
3025 | } | |
3026 | vcvtpq_u32_f32_(a) | |
3027 | } | |
3028 | ||
3029 | /// Floating-point convert to unsigned integer, rounding toward plus infinity | |
3030 | #[inline] | |
3031 | #[target_feature(enable = "neon")] | |
3032 | #[cfg_attr(test, assert_instr(fcvtpu))] | |
3033 | pub unsafe fn vcvtp_u64_f64(a: float64x1_t) -> uint64x1_t { | |
3034 | #[allow(improper_ctypes)] | |
3035 | extern "C" { | |
3036 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtpu.v1i64.v1f64")] | |
3037 | fn vcvtp_u64_f64_(a: float64x1_t) -> uint64x1_t; | |
3038 | } | |
3039 | vcvtp_u64_f64_(a) | |
3040 | } | |
3041 | ||
3042 | /// Floating-point convert to unsigned integer, rounding toward plus infinity | |
3043 | #[inline] | |
3044 | #[target_feature(enable = "neon")] | |
3045 | #[cfg_attr(test, assert_instr(fcvtpu))] | |
3046 | pub unsafe fn vcvtpq_u64_f64(a: float64x2_t) -> uint64x2_t { | |
3047 | #[allow(improper_ctypes)] | |
3048 | extern "C" { | |
3049 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtpu.v2i64.v2f64")] | |
3050 | fn vcvtpq_u64_f64_(a: float64x2_t) -> uint64x2_t; | |
3051 | } | |
3052 | vcvtpq_u64_f64_(a) | |
3053 | } | |
3054 | ||
3055 | /// Floating-point convert to unsigned integer, rounding toward plus infinity | |
3056 | #[inline] | |
3057 | #[target_feature(enable = "neon")] | |
3058 | #[cfg_attr(test, assert_instr(fcvtpu))] | |
3059 | pub unsafe fn vcvtps_u32_f32(a: f32) -> u32 { | |
3060 | #[allow(improper_ctypes)] | |
3061 | extern "C" { | |
3062 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtpu.i32.f32")] | |
3063 | fn vcvtps_u32_f32_(a: f32) -> u32; | |
3064 | } | |
3065 | vcvtps_u32_f32_(a) | |
3066 | } | |
3067 | ||
3068 | /// Floating-point convert to unsigned integer, rounding toward plus infinity | |
3069 | #[inline] | |
3070 | #[target_feature(enable = "neon")] | |
3071 | #[cfg_attr(test, assert_instr(fcvtpu))] | |
3072 | pub unsafe fn vcvtpd_u64_f64(a: f64) -> u64 { | |
3073 | #[allow(improper_ctypes)] | |
3074 | extern "C" { | |
3075 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtpu.i64.f64")] | |
3076 | fn vcvtpd_u64_f64_(a: f64) -> u64; | |
3077 | } | |
3078 | vcvtpd_u64_f64_(a) | |
3079 | } | |
3080 | ||
3081 | /// Set all vector lanes to the same value | |
3082 | #[inline] | |
3083 | #[target_feature(enable = "neon")] | |
3084 | #[cfg_attr(test, assert_instr(dup, N = 1))] | |
3085 | #[rustc_legacy_const_generics(1)] | |
3086 | pub unsafe fn vdupq_laneq_p64<const N: i32>(a: poly64x2_t) -> poly64x2_t { | |
3087 | static_assert_imm1!(N); | |
3088 | simd_shuffle2!(a, a, <const N: i32> [N as u32, N as u32]) | |
3089 | } | |
3090 | ||
3091 | /// Set all vector lanes to the same value | |
3092 | #[inline] | |
3093 | #[target_feature(enable = "neon")] | |
3094 | #[cfg_attr(test, assert_instr(dup, N = 0))] | |
3095 | #[rustc_legacy_const_generics(1)] | |
3096 | pub unsafe fn vdupq_lane_p64<const N: i32>(a: poly64x1_t) -> poly64x2_t { | |
3097 | static_assert!(N : i32 where N == 0); | |
3098 | simd_shuffle2!(a, a, <const N: i32> [N as u32, N as u32]) | |
3099 | } | |
3100 | ||
3101 | /// Set all vector lanes to the same value | |
3102 | #[inline] | |
3103 | #[target_feature(enable = "neon")] | |
3104 | #[cfg_attr(test, assert_instr(dup, N = 1))] | |
3105 | #[rustc_legacy_const_generics(1)] | |
3106 | pub unsafe fn vdupq_laneq_f64<const N: i32>(a: float64x2_t) -> float64x2_t { | |
3107 | static_assert_imm1!(N); | |
3108 | simd_shuffle2!(a, a, <const N: i32> [N as u32, N as u32]) | |
3109 | } | |
3110 | ||
3111 | /// Set all vector lanes to the same value | |
3112 | #[inline] | |
3113 | #[target_feature(enable = "neon")] | |
3114 | #[cfg_attr(test, assert_instr(dup, N = 0))] | |
3115 | #[rustc_legacy_const_generics(1)] | |
3116 | pub unsafe fn vdupq_lane_f64<const N: i32>(a: float64x1_t) -> float64x2_t { | |
3117 | static_assert!(N : i32 where N == 0); | |
3118 | simd_shuffle2!(a, a, <const N: i32> [N as u32, N as u32]) | |
3119 | } | |
3120 | ||
3121 | /// Set all vector lanes to the same value | |
3122 | #[inline] | |
3123 | #[target_feature(enable = "neon")] | |
3124 | #[cfg_attr(test, assert_instr(nop, N = 0))] | |
3125 | #[rustc_legacy_const_generics(1)] | |
3126 | pub unsafe fn vdup_lane_p64<const N: i32>(a: poly64x1_t) -> poly64x1_t { | |
3127 | static_assert!(N : i32 where N == 0); | |
3128 | a | |
3129 | } | |
3130 | ||
3131 | /// Set all vector lanes to the same value | |
3132 | #[inline] | |
3133 | #[target_feature(enable = "neon")] | |
3134 | #[cfg_attr(test, assert_instr(nop, N = 0))] | |
3135 | #[rustc_legacy_const_generics(1)] | |
3136 | pub unsafe fn vdup_lane_f64<const N: i32>(a: float64x1_t) -> float64x1_t { | |
3137 | static_assert!(N : i32 where N == 0); | |
3138 | a | |
3139 | } | |
3140 | ||
3141 | /// Set all vector lanes to the same value | |
3142 | #[inline] | |
3143 | #[target_feature(enable = "neon")] | |
3144 | #[cfg_attr(test, assert_instr(nop, N = 1))] | |
3145 | #[rustc_legacy_const_generics(1)] | |
3146 | pub unsafe fn vdup_laneq_p64<const N: i32>(a: poly64x2_t) -> poly64x1_t { | |
3147 | static_assert_imm1!(N); | |
3148 | transmute::<u64, _>(simd_extract(a, N as u32)) | |
3149 | } | |
3150 | ||
3151 | /// Set all vector lanes to the same value | |
3152 | #[inline] | |
3153 | #[target_feature(enable = "neon")] | |
3154 | #[cfg_attr(test, assert_instr(nop, N = 1))] | |
3155 | #[rustc_legacy_const_generics(1)] | |
3156 | pub unsafe fn vdup_laneq_f64<const N: i32>(a: float64x2_t) -> float64x1_t { | |
3157 | static_assert_imm1!(N); | |
3158 | transmute::<f64, _>(simd_extract(a, N as u32)) | |
3159 | } | |
3160 | ||
3161 | /// Set all vector lanes to the same value | |
3162 | #[inline] | |
3163 | #[target_feature(enable = "neon")] | |
3164 | #[cfg_attr(test, assert_instr(nop, N = 4))] | |
3165 | #[rustc_legacy_const_generics(1)] | |
3166 | pub unsafe fn vdupb_lane_s8<const N: i32>(a: int8x8_t) -> i8 { | |
3167 | static_assert_imm3!(N); | |
3168 | simd_extract(a, N as u32) | |
3169 | } | |
3170 | ||
3171 | /// Set all vector lanes to the same value | |
3172 | #[inline] | |
3173 | #[target_feature(enable = "neon")] | |
3174 | #[cfg_attr(test, assert_instr(nop, N = 8))] | |
3175 | #[rustc_legacy_const_generics(1)] | |
3176 | pub unsafe fn vdupb_laneq_s8<const N: i32>(a: int8x16_t) -> i8 { | |
3177 | static_assert_imm4!(N); | |
3178 | simd_extract(a, N as u32) | |
3179 | } | |
3180 | ||
3181 | /// Set all vector lanes to the same value | |
3182 | #[inline] | |
3183 | #[target_feature(enable = "neon")] | |
3184 | #[cfg_attr(test, assert_instr(nop, N = 2))] | |
3185 | #[rustc_legacy_const_generics(1)] | |
3186 | pub unsafe fn vduph_lane_s16<const N: i32>(a: int16x4_t) -> i16 { | |
3187 | static_assert_imm2!(N); | |
3188 | simd_extract(a, N as u32) | |
3189 | } | |
3190 | ||
3191 | /// Set all vector lanes to the same value | |
3192 | #[inline] | |
3193 | #[target_feature(enable = "neon")] | |
3194 | #[cfg_attr(test, assert_instr(nop, N = 4))] | |
3195 | #[rustc_legacy_const_generics(1)] | |
3196 | pub unsafe fn vduph_laneq_s16<const N: i32>(a: int16x8_t) -> i16 { | |
3197 | static_assert_imm3!(N); | |
3198 | simd_extract(a, N as u32) | |
3199 | } | |
3200 | ||
3201 | /// Set all vector lanes to the same value | |
3202 | #[inline] | |
3203 | #[target_feature(enable = "neon")] | |
3204 | #[cfg_attr(test, assert_instr(nop, N = 1))] | |
3205 | #[rustc_legacy_const_generics(1)] | |
3206 | pub unsafe fn vdups_lane_s32<const N: i32>(a: int32x2_t) -> i32 { | |
3207 | static_assert_imm1!(N); | |
3208 | simd_extract(a, N as u32) | |
3209 | } | |
3210 | ||
3211 | /// Set all vector lanes to the same value | |
3212 | #[inline] | |
3213 | #[target_feature(enable = "neon")] | |
3214 | #[cfg_attr(test, assert_instr(nop, N = 2))] | |
3215 | #[rustc_legacy_const_generics(1)] | |
3216 | pub unsafe fn vdups_laneq_s32<const N: i32>(a: int32x4_t) -> i32 { | |
3217 | static_assert_imm2!(N); | |
3218 | simd_extract(a, N as u32) | |
3219 | } | |
3220 | ||
3221 | /// Set all vector lanes to the same value | |
3222 | #[inline] | |
3223 | #[target_feature(enable = "neon")] | |
3224 | #[cfg_attr(test, assert_instr(nop, N = 0))] | |
3225 | #[rustc_legacy_const_generics(1)] | |
3226 | pub unsafe fn vdupd_lane_s64<const N: i32>(a: int64x1_t) -> i64 { | |
3227 | static_assert!(N : i32 where N == 0); | |
3228 | simd_extract(a, N as u32) | |
3229 | } | |
3230 | ||
3231 | /// Set all vector lanes to the same value | |
3232 | #[inline] | |
3233 | #[target_feature(enable = "neon")] | |
3234 | #[cfg_attr(test, assert_instr(nop, N = 1))] | |
3235 | #[rustc_legacy_const_generics(1)] | |
3236 | pub unsafe fn vdupd_laneq_s64<const N: i32>(a: int64x2_t) -> i64 { | |
3237 | static_assert_imm1!(N); | |
3238 | simd_extract(a, N as u32) | |
3239 | } | |
3240 | ||
3241 | /// Set all vector lanes to the same value | |
3242 | #[inline] | |
3243 | #[target_feature(enable = "neon")] | |
3244 | #[cfg_attr(test, assert_instr(nop, N = 4))] | |
3245 | #[rustc_legacy_const_generics(1)] | |
3246 | pub unsafe fn vdupb_lane_u8<const N: i32>(a: uint8x8_t) -> u8 { | |
3247 | static_assert_imm3!(N); | |
3248 | simd_extract(a, N as u32) | |
3249 | } | |
3250 | ||
3251 | /// Set all vector lanes to the same value | |
3252 | #[inline] | |
3253 | #[target_feature(enable = "neon")] | |
3254 | #[cfg_attr(test, assert_instr(nop, N = 8))] | |
3255 | #[rustc_legacy_const_generics(1)] | |
3256 | pub unsafe fn vdupb_laneq_u8<const N: i32>(a: uint8x16_t) -> u8 { | |
3257 | static_assert_imm4!(N); | |
3258 | simd_extract(a, N as u32) | |
3259 | } | |
3260 | ||
3261 | /// Set all vector lanes to the same value | |
3262 | #[inline] | |
3263 | #[target_feature(enable = "neon")] | |
3264 | #[cfg_attr(test, assert_instr(nop, N = 2))] | |
3265 | #[rustc_legacy_const_generics(1)] | |
3266 | pub unsafe fn vduph_lane_u16<const N: i32>(a: uint16x4_t) -> u16 { | |
3267 | static_assert_imm2!(N); | |
3268 | simd_extract(a, N as u32) | |
3269 | } | |
3270 | ||
3271 | /// Set all vector lanes to the same value | |
3272 | #[inline] | |
3273 | #[target_feature(enable = "neon")] | |
3274 | #[cfg_attr(test, assert_instr(nop, N = 4))] | |
3275 | #[rustc_legacy_const_generics(1)] | |
3276 | pub unsafe fn vduph_laneq_u16<const N: i32>(a: uint16x8_t) -> u16 { | |
3277 | static_assert_imm3!(N); | |
3278 | simd_extract(a, N as u32) | |
3279 | } | |
3280 | ||
3281 | /// Set all vector lanes to the same value | |
3282 | #[inline] | |
3283 | #[target_feature(enable = "neon")] | |
3284 | #[cfg_attr(test, assert_instr(nop, N = 1))] | |
3285 | #[rustc_legacy_const_generics(1)] | |
3286 | pub unsafe fn vdups_lane_u32<const N: i32>(a: uint32x2_t) -> u32 { | |
3287 | static_assert_imm1!(N); | |
3288 | simd_extract(a, N as u32) | |
3289 | } | |
3290 | ||
3291 | /// Set all vector lanes to the same value | |
3292 | #[inline] | |
3293 | #[target_feature(enable = "neon")] | |
3294 | #[cfg_attr(test, assert_instr(nop, N = 2))] | |
3295 | #[rustc_legacy_const_generics(1)] | |
3296 | pub unsafe fn vdups_laneq_u32<const N: i32>(a: uint32x4_t) -> u32 { | |
3297 | static_assert_imm2!(N); | |
3298 | simd_extract(a, N as u32) | |
3299 | } | |
3300 | ||
3301 | /// Set all vector lanes to the same value | |
3302 | #[inline] | |
3303 | #[target_feature(enable = "neon")] | |
3304 | #[cfg_attr(test, assert_instr(nop, N = 0))] | |
3305 | #[rustc_legacy_const_generics(1)] | |
3306 | pub unsafe fn vdupd_lane_u64<const N: i32>(a: uint64x1_t) -> u64 { | |
3307 | static_assert!(N : i32 where N == 0); | |
3308 | simd_extract(a, N as u32) | |
3309 | } | |
3310 | ||
3311 | /// Set all vector lanes to the same value | |
3312 | #[inline] | |
3313 | #[target_feature(enable = "neon")] | |
3314 | #[cfg_attr(test, assert_instr(nop, N = 1))] | |
3315 | #[rustc_legacy_const_generics(1)] | |
3316 | pub unsafe fn vdupd_laneq_u64<const N: i32>(a: uint64x2_t) -> u64 { | |
3317 | static_assert_imm1!(N); | |
3318 | simd_extract(a, N as u32) | |
3319 | } | |
3320 | ||
3321 | /// Set all vector lanes to the same value | |
3322 | #[inline] | |
3323 | #[target_feature(enable = "neon")] | |
3324 | #[cfg_attr(test, assert_instr(nop, N = 4))] | |
3325 | #[rustc_legacy_const_generics(1)] | |
3326 | pub unsafe fn vdupb_lane_p8<const N: i32>(a: poly8x8_t) -> p8 { | |
3327 | static_assert_imm3!(N); | |
3328 | simd_extract(a, N as u32) | |
3329 | } | |
3330 | ||
3331 | /// Set all vector lanes to the same value | |
3332 | #[inline] | |
3333 | #[target_feature(enable = "neon")] | |
3334 | #[cfg_attr(test, assert_instr(nop, N = 8))] | |
3335 | #[rustc_legacy_const_generics(1)] | |
3336 | pub unsafe fn vdupb_laneq_p8<const N: i32>(a: poly8x16_t) -> p8 { | |
3337 | static_assert_imm4!(N); | |
3338 | simd_extract(a, N as u32) | |
3339 | } | |
3340 | ||
3341 | /// Set all vector lanes to the same value | |
3342 | #[inline] | |
3343 | #[target_feature(enable = "neon")] | |
3344 | #[cfg_attr(test, assert_instr(nop, N = 2))] | |
3345 | #[rustc_legacy_const_generics(1)] | |
3346 | pub unsafe fn vduph_lane_p16<const N: i32>(a: poly16x4_t) -> p16 { | |
3347 | static_assert_imm2!(N); | |
3348 | simd_extract(a, N as u32) | |
3349 | } | |
3350 | ||
3351 | /// Set all vector lanes to the same value | |
3352 | #[inline] | |
3353 | #[target_feature(enable = "neon")] | |
3354 | #[cfg_attr(test, assert_instr(nop, N = 4))] | |
3355 | #[rustc_legacy_const_generics(1)] | |
3356 | pub unsafe fn vduph_laneq_p16<const N: i32>(a: poly16x8_t) -> p16 { | |
3357 | static_assert_imm3!(N); | |
3358 | simd_extract(a, N as u32) | |
3359 | } | |
3360 | ||
3361 | /// Set all vector lanes to the same value | |
3362 | #[inline] | |
3363 | #[target_feature(enable = "neon")] | |
3364 | #[cfg_attr(test, assert_instr(nop, N = 1))] | |
3365 | #[rustc_legacy_const_generics(1)] | |
3366 | pub unsafe fn vdups_lane_f32<const N: i32>(a: float32x2_t) -> f32 { | |
3367 | static_assert_imm1!(N); | |
3368 | simd_extract(a, N as u32) | |
3369 | } | |
3370 | ||
3371 | /// Set all vector lanes to the same value | |
3372 | #[inline] | |
3373 | #[target_feature(enable = "neon")] | |
3374 | #[cfg_attr(test, assert_instr(nop, N = 2))] | |
3375 | #[rustc_legacy_const_generics(1)] | |
3376 | pub unsafe fn vdups_laneq_f32<const N: i32>(a: float32x4_t) -> f32 { | |
3377 | static_assert_imm2!(N); | |
3378 | simd_extract(a, N as u32) | |
3379 | } | |
3380 | ||
3381 | /// Set all vector lanes to the same value | |
3382 | #[inline] | |
3383 | #[target_feature(enable = "neon")] | |
3384 | #[cfg_attr(test, assert_instr(nop, N = 0))] | |
3385 | #[rustc_legacy_const_generics(1)] | |
3386 | pub unsafe fn vdupd_lane_f64<const N: i32>(a: float64x1_t) -> f64 { | |
3387 | static_assert!(N : i32 where N == 0); | |
3388 | simd_extract(a, N as u32) | |
3389 | } | |
3390 | ||
3391 | /// Set all vector lanes to the same value | |
3392 | #[inline] | |
3393 | #[target_feature(enable = "neon")] | |
3394 | #[cfg_attr(test, assert_instr(nop, N = 1))] | |
3395 | #[rustc_legacy_const_generics(1)] | |
3396 | pub unsafe fn vdupd_laneq_f64<const N: i32>(a: float64x2_t) -> f64 { | |
3397 | static_assert_imm1!(N); | |
3398 | simd_extract(a, N as u32) | |
3399 | } | |
3400 | ||
3401 | /// Extract vector from pair of vectors | |
3402 | #[inline] | |
3403 | #[target_feature(enable = "neon")] | |
3404 | #[cfg_attr(test, assert_instr(ext, N = 1))] | |
3405 | #[rustc_legacy_const_generics(2)] | |
3406 | pub unsafe fn vextq_p64<const N: i32>(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { | |
3407 | static_assert_imm1!(N); | |
3408 | match N & 0b1 { | |
3409 | 0 => simd_shuffle2!(a, b, [0, 1]), | |
3410 | 1 => simd_shuffle2!(a, b, [1, 2]), | |
3411 | _ => unreachable_unchecked(), | |
3412 | } | |
3413 | } | |
3414 | ||
3415 | /// Extract vector from pair of vectors | |
3416 | #[inline] | |
3417 | #[target_feature(enable = "neon")] | |
3418 | #[cfg_attr(test, assert_instr(ext, N = 1))] | |
3419 | #[rustc_legacy_const_generics(2)] | |
3420 | pub unsafe fn vextq_f64<const N: i32>(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
3421 | static_assert_imm1!(N); | |
3422 | match N & 0b1 { | |
3423 | 0 => simd_shuffle2!(a, b, [0, 1]), | |
3424 | 1 => simd_shuffle2!(a, b, [1, 2]), | |
3425 | _ => unreachable_unchecked(), | |
3426 | } | |
3427 | } | |
3428 | ||
3429 | /// Floating-point multiply-add to accumulator | |
3430 | #[inline] | |
3431 | #[target_feature(enable = "neon")] | |
3432 | #[cfg_attr(test, assert_instr(fmul))] | |
3433 | pub unsafe fn vmla_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { | |
3434 | simd_add(a, simd_mul(b, c)) | |
3435 | } | |
3436 | ||
3437 | /// Floating-point multiply-add to accumulator | |
3438 | #[inline] | |
3439 | #[target_feature(enable = "neon")] | |
3440 | #[cfg_attr(test, assert_instr(fmul))] | |
3441 | pub unsafe fn vmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { | |
3442 | simd_add(a, simd_mul(b, c)) | |
3443 | } | |
3444 | ||
3445 | /// Signed multiply-add long | |
3446 | #[inline] | |
3447 | #[target_feature(enable = "neon")] | |
3448 | #[cfg_attr(test, assert_instr(smlal2))] | |
3449 | pub unsafe fn vmlal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { | |
3450 | let b: int8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
3451 | let c: int8x8_t = simd_shuffle8!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); | |
3452 | vmlal_s8(a, b, c) | |
3453 | } | |
3454 | ||
3455 | /// Signed multiply-add long | |
3456 | #[inline] | |
3457 | #[target_feature(enable = "neon")] | |
3458 | #[cfg_attr(test, assert_instr(smlal2))] | |
3459 | pub unsafe fn vmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { | |
3460 | let b: int16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
3461 | let c: int16x4_t = simd_shuffle4!(c, c, [4, 5, 6, 7]); | |
3462 | vmlal_s16(a, b, c) | |
3463 | } | |
3464 | ||
3465 | /// Signed multiply-add long | |
3466 | #[inline] | |
3467 | #[target_feature(enable = "neon")] | |
3468 | #[cfg_attr(test, assert_instr(smlal2))] | |
3469 | pub unsafe fn vmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { | |
3470 | let b: int32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
3471 | let c: int32x2_t = simd_shuffle2!(c, c, [2, 3]); | |
3472 | vmlal_s32(a, b, c) | |
3473 | } | |
3474 | ||
3475 | /// Unsigned multiply-add long | |
3476 | #[inline] | |
3477 | #[target_feature(enable = "neon")] | |
3478 | #[cfg_attr(test, assert_instr(umlal2))] | |
3479 | pub unsafe fn vmlal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { | |
3480 | let b: uint8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
3481 | let c: uint8x8_t = simd_shuffle8!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); | |
3482 | vmlal_u8(a, b, c) | |
3483 | } | |
3484 | ||
3485 | /// Unsigned multiply-add long | |
3486 | #[inline] | |
3487 | #[target_feature(enable = "neon")] | |
3488 | #[cfg_attr(test, assert_instr(umlal2))] | |
3489 | pub unsafe fn vmlal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { | |
3490 | let b: uint16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
3491 | let c: uint16x4_t = simd_shuffle4!(c, c, [4, 5, 6, 7]); | |
3492 | vmlal_u16(a, b, c) | |
3493 | } | |
3494 | ||
3495 | /// Unsigned multiply-add long | |
3496 | #[inline] | |
3497 | #[target_feature(enable = "neon")] | |
3498 | #[cfg_attr(test, assert_instr(umlal2))] | |
3499 | pub unsafe fn vmlal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { | |
3500 | let b: uint32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
3501 | let c: uint32x2_t = simd_shuffle2!(c, c, [2, 3]); | |
3502 | vmlal_u32(a, b, c) | |
3503 | } | |
3504 | ||
3505 | /// Multiply-add long | |
3506 | #[inline] | |
3507 | #[target_feature(enable = "neon")] | |
3508 | #[cfg_attr(test, assert_instr(smlal2))] | |
3509 | pub unsafe fn vmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { | |
3510 | vmlal_high_s16(a, b, vdupq_n_s16(c)) | |
3511 | } | |
3512 | ||
3513 | /// Multiply-add long | |
3514 | #[inline] | |
3515 | #[target_feature(enable = "neon")] | |
3516 | #[cfg_attr(test, assert_instr(smlal2))] | |
3517 | pub unsafe fn vmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { | |
3518 | vmlal_high_s32(a, b, vdupq_n_s32(c)) | |
3519 | } | |
3520 | ||
3521 | /// Multiply-add long | |
3522 | #[inline] | |
3523 | #[target_feature(enable = "neon")] | |
3524 | #[cfg_attr(test, assert_instr(umlal2))] | |
3525 | pub unsafe fn vmlal_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t { | |
3526 | vmlal_high_u16(a, b, vdupq_n_u16(c)) | |
3527 | } | |
3528 | ||
3529 | /// Multiply-add long | |
3530 | #[inline] | |
3531 | #[target_feature(enable = "neon")] | |
3532 | #[cfg_attr(test, assert_instr(umlal2))] | |
3533 | pub unsafe fn vmlal_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t { | |
3534 | vmlal_high_u32(a, b, vdupq_n_u32(c)) | |
3535 | } | |
3536 | ||
3537 | /// Multiply-add long | |
3538 | #[inline] | |
3539 | #[target_feature(enable = "neon")] | |
3540 | #[cfg_attr(test, assert_instr(smlal2, LANE = 1))] | |
3541 | #[rustc_legacy_const_generics(3)] | |
3542 | pub unsafe fn vmlal_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { | |
3543 | static_assert_imm2!(LANE); | |
3544 | vmlal_high_s16(a, b, simd_shuffle8!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3545 | } | |
3546 | ||
3547 | /// Multiply-add long | |
3548 | #[inline] | |
3549 | #[target_feature(enable = "neon")] | |
3550 | #[cfg_attr(test, assert_instr(smlal2, LANE = 1))] | |
3551 | #[rustc_legacy_const_generics(3)] | |
3552 | pub unsafe fn vmlal_high_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { | |
3553 | static_assert_imm3!(LANE); | |
3554 | vmlal_high_s16(a, b, simd_shuffle8!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3555 | } | |
3556 | ||
3557 | /// Multiply-add long | |
3558 | #[inline] | |
3559 | #[target_feature(enable = "neon")] | |
3560 | #[cfg_attr(test, assert_instr(smlal2, LANE = 1))] | |
3561 | #[rustc_legacy_const_generics(3)] | |
3562 | pub unsafe fn vmlal_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { | |
3563 | static_assert_imm1!(LANE); | |
3564 | vmlal_high_s32(a, b, simd_shuffle4!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3565 | } | |
3566 | ||
3567 | /// Multiply-add long | |
3568 | #[inline] | |
3569 | #[target_feature(enable = "neon")] | |
3570 | #[cfg_attr(test, assert_instr(smlal2, LANE = 1))] | |
3571 | #[rustc_legacy_const_generics(3)] | |
3572 | pub unsafe fn vmlal_high_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { | |
3573 | static_assert_imm2!(LANE); | |
3574 | vmlal_high_s32(a, b, simd_shuffle4!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3575 | } | |
3576 | ||
3577 | /// Multiply-add long | |
3578 | #[inline] | |
3579 | #[target_feature(enable = "neon")] | |
3580 | #[cfg_attr(test, assert_instr(umlal2, LANE = 1))] | |
3581 | #[rustc_legacy_const_generics(3)] | |
3582 | pub unsafe fn vmlal_high_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x8_t, c: uint16x4_t) -> uint32x4_t { | |
3583 | static_assert_imm2!(LANE); | |
3584 | vmlal_high_u16(a, b, simd_shuffle8!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3585 | } | |
3586 | ||
3587 | /// Multiply-add long | |
3588 | #[inline] | |
3589 | #[target_feature(enable = "neon")] | |
3590 | #[cfg_attr(test, assert_instr(umlal2, LANE = 1))] | |
3591 | #[rustc_legacy_const_generics(3)] | |
3592 | pub unsafe fn vmlal_high_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { | |
3593 | static_assert_imm3!(LANE); | |
3594 | vmlal_high_u16(a, b, simd_shuffle8!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3595 | } | |
3596 | ||
3597 | /// Multiply-add long | |
3598 | #[inline] | |
3599 | #[target_feature(enable = "neon")] | |
3600 | #[cfg_attr(test, assert_instr(umlal2, LANE = 1))] | |
3601 | #[rustc_legacy_const_generics(3)] | |
3602 | pub unsafe fn vmlal_high_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x4_t, c: uint32x2_t) -> uint64x2_t { | |
3603 | static_assert_imm1!(LANE); | |
3604 | vmlal_high_u32(a, b, simd_shuffle4!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3605 | } | |
3606 | ||
3607 | /// Multiply-add long | |
3608 | #[inline] | |
3609 | #[target_feature(enable = "neon")] | |
3610 | #[cfg_attr(test, assert_instr(umlal2, LANE = 1))] | |
3611 | #[rustc_legacy_const_generics(3)] | |
3612 | pub unsafe fn vmlal_high_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { | |
3613 | static_assert_imm2!(LANE); | |
3614 | vmlal_high_u32(a, b, simd_shuffle4!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3615 | } | |
3616 | ||
3617 | /// Floating-point multiply-subtract from accumulator | |
3618 | #[inline] | |
3619 | #[target_feature(enable = "neon")] | |
3620 | #[cfg_attr(test, assert_instr(fmul))] | |
3621 | pub unsafe fn vmls_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { | |
3622 | simd_sub(a, simd_mul(b, c)) | |
3623 | } | |
3624 | ||
3625 | /// Floating-point multiply-subtract from accumulator | |
3626 | #[inline] | |
3627 | #[target_feature(enable = "neon")] | |
3628 | #[cfg_attr(test, assert_instr(fmul))] | |
3629 | pub unsafe fn vmlsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { | |
3630 | simd_sub(a, simd_mul(b, c)) | |
3631 | } | |
3632 | ||
3633 | /// Signed multiply-subtract long | |
3634 | #[inline] | |
3635 | #[target_feature(enable = "neon")] | |
3636 | #[cfg_attr(test, assert_instr(smlsl2))] | |
3637 | pub unsafe fn vmlsl_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { | |
3638 | let b: int8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
3639 | let c: int8x8_t = simd_shuffle8!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); | |
3640 | vmlsl_s8(a, b, c) | |
3641 | } | |
3642 | ||
3643 | /// Signed multiply-subtract long | |
3644 | #[inline] | |
3645 | #[target_feature(enable = "neon")] | |
3646 | #[cfg_attr(test, assert_instr(smlsl2))] | |
3647 | pub unsafe fn vmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { | |
3648 | let b: int16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
3649 | let c: int16x4_t = simd_shuffle4!(c, c, [4, 5, 6, 7]); | |
3650 | vmlsl_s16(a, b, c) | |
3651 | } | |
3652 | ||
3653 | /// Signed multiply-subtract long | |
3654 | #[inline] | |
3655 | #[target_feature(enable = "neon")] | |
3656 | #[cfg_attr(test, assert_instr(smlsl2))] | |
3657 | pub unsafe fn vmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { | |
3658 | let b: int32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
3659 | let c: int32x2_t = simd_shuffle2!(c, c, [2, 3]); | |
3660 | vmlsl_s32(a, b, c) | |
3661 | } | |
3662 | ||
3663 | /// Unsigned multiply-subtract long | |
3664 | #[inline] | |
3665 | #[target_feature(enable = "neon")] | |
3666 | #[cfg_attr(test, assert_instr(umlsl2))] | |
3667 | pub unsafe fn vmlsl_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { | |
3668 | let b: uint8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
3669 | let c: uint8x8_t = simd_shuffle8!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); | |
3670 | vmlsl_u8(a, b, c) | |
3671 | } | |
3672 | ||
3673 | /// Unsigned multiply-subtract long | |
3674 | #[inline] | |
3675 | #[target_feature(enable = "neon")] | |
3676 | #[cfg_attr(test, assert_instr(umlsl2))] | |
3677 | pub unsafe fn vmlsl_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { | |
3678 | let b: uint16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
3679 | let c: uint16x4_t = simd_shuffle4!(c, c, [4, 5, 6, 7]); | |
3680 | vmlsl_u16(a, b, c) | |
3681 | } | |
3682 | ||
3683 | /// Unsigned multiply-subtract long | |
3684 | #[inline] | |
3685 | #[target_feature(enable = "neon")] | |
3686 | #[cfg_attr(test, assert_instr(umlsl2))] | |
3687 | pub unsafe fn vmlsl_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { | |
3688 | let b: uint32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
3689 | let c: uint32x2_t = simd_shuffle2!(c, c, [2, 3]); | |
3690 | vmlsl_u32(a, b, c) | |
3691 | } | |
3692 | ||
3693 | /// Multiply-subtract long | |
3694 | #[inline] | |
3695 | #[target_feature(enable = "neon")] | |
3696 | #[cfg_attr(test, assert_instr(smlsl2))] | |
3697 | pub unsafe fn vmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { | |
3698 | vmlsl_high_s16(a, b, vdupq_n_s16(c)) | |
3699 | } | |
3700 | ||
3701 | /// Multiply-subtract long | |
3702 | #[inline] | |
3703 | #[target_feature(enable = "neon")] | |
3704 | #[cfg_attr(test, assert_instr(smlsl2))] | |
3705 | pub unsafe fn vmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { | |
3706 | vmlsl_high_s32(a, b, vdupq_n_s32(c)) | |
3707 | } | |
3708 | ||
3709 | /// Multiply-subtract long | |
3710 | #[inline] | |
3711 | #[target_feature(enable = "neon")] | |
3712 | #[cfg_attr(test, assert_instr(umlsl2))] | |
3713 | pub unsafe fn vmlsl_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t { | |
3714 | vmlsl_high_u16(a, b, vdupq_n_u16(c)) | |
3715 | } | |
3716 | ||
3717 | /// Multiply-subtract long | |
3718 | #[inline] | |
3719 | #[target_feature(enable = "neon")] | |
3720 | #[cfg_attr(test, assert_instr(umlsl2))] | |
3721 | pub unsafe fn vmlsl_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t { | |
3722 | vmlsl_high_u32(a, b, vdupq_n_u32(c)) | |
3723 | } | |
3724 | ||
3725 | /// Multiply-subtract long | |
3726 | #[inline] | |
3727 | #[target_feature(enable = "neon")] | |
3728 | #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] | |
3729 | #[rustc_legacy_const_generics(3)] | |
3730 | pub unsafe fn vmlsl_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { | |
3731 | static_assert_imm2!(LANE); | |
3732 | vmlsl_high_s16(a, b, simd_shuffle8!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3733 | } | |
3734 | ||
3735 | /// Multiply-subtract long | |
3736 | #[inline] | |
3737 | #[target_feature(enable = "neon")] | |
3738 | #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] | |
3739 | #[rustc_legacy_const_generics(3)] | |
3740 | pub unsafe fn vmlsl_high_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { | |
3741 | static_assert_imm3!(LANE); | |
3742 | vmlsl_high_s16(a, b, simd_shuffle8!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3743 | } | |
3744 | ||
3745 | /// Multiply-subtract long | |
3746 | #[inline] | |
3747 | #[target_feature(enable = "neon")] | |
3748 | #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] | |
3749 | #[rustc_legacy_const_generics(3)] | |
3750 | pub unsafe fn vmlsl_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { | |
3751 | static_assert_imm1!(LANE); | |
3752 | vmlsl_high_s32(a, b, simd_shuffle4!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3753 | } | |
3754 | ||
3755 | /// Multiply-subtract long | |
3756 | #[inline] | |
3757 | #[target_feature(enable = "neon")] | |
3758 | #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] | |
3759 | #[rustc_legacy_const_generics(3)] | |
3760 | pub unsafe fn vmlsl_high_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { | |
3761 | static_assert_imm2!(LANE); | |
3762 | vmlsl_high_s32(a, b, simd_shuffle4!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3763 | } | |
3764 | ||
3765 | /// Multiply-subtract long | |
3766 | #[inline] | |
3767 | #[target_feature(enable = "neon")] | |
3768 | #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] | |
3769 | #[rustc_legacy_const_generics(3)] | |
3770 | pub unsafe fn vmlsl_high_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x8_t, c: uint16x4_t) -> uint32x4_t { | |
3771 | static_assert_imm2!(LANE); | |
3772 | vmlsl_high_u16(a, b, simd_shuffle8!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3773 | } | |
3774 | ||
3775 | /// Multiply-subtract long | |
3776 | #[inline] | |
3777 | #[target_feature(enable = "neon")] | |
3778 | #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] | |
3779 | #[rustc_legacy_const_generics(3)] | |
3780 | pub unsafe fn vmlsl_high_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { | |
3781 | static_assert_imm3!(LANE); | |
3782 | vmlsl_high_u16(a, b, simd_shuffle8!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3783 | } | |
3784 | ||
3785 | /// Multiply-subtract long | |
3786 | #[inline] | |
3787 | #[target_feature(enable = "neon")] | |
3788 | #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] | |
3789 | #[rustc_legacy_const_generics(3)] | |
3790 | pub unsafe fn vmlsl_high_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x4_t, c: uint32x2_t) -> uint64x2_t { | |
3791 | static_assert_imm1!(LANE); | |
3792 | vmlsl_high_u32(a, b, simd_shuffle4!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3793 | } | |
3794 | ||
3795 | /// Multiply-subtract long | |
3796 | #[inline] | |
3797 | #[target_feature(enable = "neon")] | |
3798 | #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] | |
3799 | #[rustc_legacy_const_generics(3)] | |
3800 | pub unsafe fn vmlsl_high_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { | |
3801 | static_assert_imm2!(LANE); | |
3802 | vmlsl_high_u32(a, b, simd_shuffle4!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3803 | } | |
3804 | ||
3805 | /// Extract narrow | |
3806 | #[inline] | |
3807 | #[target_feature(enable = "neon")] | |
3808 | #[cfg_attr(test, assert_instr(xtn2))] | |
3809 | pub unsafe fn vmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { | |
3810 | let c: int8x8_t = simd_cast(b); | |
3811 | simd_shuffle16!(a, c, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
3812 | } | |
3813 | ||
3814 | /// Extract narrow | |
3815 | #[inline] | |
3816 | #[target_feature(enable = "neon")] | |
3817 | #[cfg_attr(test, assert_instr(xtn2))] | |
3818 | pub unsafe fn vmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { | |
3819 | let c: int16x4_t = simd_cast(b); | |
3820 | simd_shuffle8!(a, c, [0, 1, 2, 3, 4, 5, 6, 7]) | |
3821 | } | |
3822 | ||
3823 | /// Extract narrow | |
3824 | #[inline] | |
3825 | #[target_feature(enable = "neon")] | |
3826 | #[cfg_attr(test, assert_instr(xtn2))] | |
3827 | pub unsafe fn vmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { | |
3828 | let c: int32x2_t = simd_cast(b); | |
3829 | simd_shuffle4!(a, c, [0, 1, 2, 3]) | |
3830 | } | |
3831 | ||
3832 | /// Extract narrow | |
3833 | #[inline] | |
3834 | #[target_feature(enable = "neon")] | |
3835 | #[cfg_attr(test, assert_instr(xtn2))] | |
3836 | pub unsafe fn vmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { | |
3837 | let c: uint8x8_t = simd_cast(b); | |
3838 | simd_shuffle16!(a, c, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
3839 | } | |
3840 | ||
3841 | /// Extract narrow | |
3842 | #[inline] | |
3843 | #[target_feature(enable = "neon")] | |
3844 | #[cfg_attr(test, assert_instr(xtn2))] | |
3845 | pub unsafe fn vmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { | |
3846 | let c: uint16x4_t = simd_cast(b); | |
3847 | simd_shuffle8!(a, c, [0, 1, 2, 3, 4, 5, 6, 7]) | |
3848 | } | |
3849 | ||
3850 | /// Extract narrow | |
3851 | #[inline] | |
3852 | #[target_feature(enable = "neon")] | |
3853 | #[cfg_attr(test, assert_instr(xtn2))] | |
3854 | pub unsafe fn vmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { | |
3855 | let c: uint32x2_t = simd_cast(b); | |
3856 | simd_shuffle4!(a, c, [0, 1, 2, 3]) | |
3857 | } | |
3858 | ||
3859 | /// Negate | |
3860 | #[inline] | |
3861 | #[target_feature(enable = "neon")] | |
3862 | #[cfg_attr(test, assert_instr(neg))] | |
3863 | pub unsafe fn vneg_s64(a: int64x1_t) -> int64x1_t { | |
3864 | simd_neg(a) | |
3865 | } | |
3866 | ||
3867 | /// Negate | |
3868 | #[inline] | |
3869 | #[target_feature(enable = "neon")] | |
3870 | #[cfg_attr(test, assert_instr(neg))] | |
3871 | pub unsafe fn vnegq_s64(a: int64x2_t) -> int64x2_t { | |
3872 | simd_neg(a) | |
3873 | } | |
3874 | ||
3875 | /// Negate | |
3876 | #[inline] | |
3877 | #[target_feature(enable = "neon")] | |
3878 | #[cfg_attr(test, assert_instr(fneg))] | |
3879 | pub unsafe fn vneg_f64(a: float64x1_t) -> float64x1_t { | |
3880 | simd_neg(a) | |
3881 | } | |
3882 | ||
3883 | /// Negate | |
3884 | #[inline] | |
3885 | #[target_feature(enable = "neon")] | |
3886 | #[cfg_attr(test, assert_instr(fneg))] | |
3887 | pub unsafe fn vnegq_f64(a: float64x2_t) -> float64x2_t { | |
3888 | simd_neg(a) | |
3889 | } | |
3890 | ||
3891 | /// Signed saturating negate | |
3892 | #[inline] | |
3893 | #[target_feature(enable = "neon")] | |
3894 | #[cfg_attr(test, assert_instr(sqneg))] | |
3895 | pub unsafe fn vqneg_s64(a: int64x1_t) -> int64x1_t { | |
3896 | #[allow(improper_ctypes)] | |
3897 | extern "C" { | |
3898 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqneg.v1i64")] | |
3899 | fn vqneg_s64_(a: int64x1_t) -> int64x1_t; | |
3900 | } | |
3901 | vqneg_s64_(a) | |
3902 | } | |
3903 | ||
3904 | /// Signed saturating negate | |
3905 | #[inline] | |
3906 | #[target_feature(enable = "neon")] | |
3907 | #[cfg_attr(test, assert_instr(sqneg))] | |
3908 | pub unsafe fn vqnegq_s64(a: int64x2_t) -> int64x2_t { | |
3909 | #[allow(improper_ctypes)] | |
3910 | extern "C" { | |
3911 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqneg.v2i64")] | |
3912 | fn vqnegq_s64_(a: int64x2_t) -> int64x2_t; | |
3913 | } | |
3914 | vqnegq_s64_(a) | |
3915 | } | |
3916 | ||
3917 | /// Saturating subtract | |
3918 | #[inline] | |
3919 | #[target_feature(enable = "neon")] | |
3920 | #[cfg_attr(test, assert_instr(sqsub))] | |
3921 | pub unsafe fn vqsubb_s8(a: i8, b: i8) -> i8 { | |
3922 | let a: int8x8_t = vdup_n_s8(a); | |
3923 | let b: int8x8_t = vdup_n_s8(b); | |
3924 | simd_extract(vqsub_s8(a, b), 0) | |
3925 | } | |
3926 | ||
3927 | /// Saturating subtract | |
3928 | #[inline] | |
3929 | #[target_feature(enable = "neon")] | |
3930 | #[cfg_attr(test, assert_instr(sqsub))] | |
3931 | pub unsafe fn vqsubh_s16(a: i16, b: i16) -> i16 { | |
3932 | let a: int16x4_t = vdup_n_s16(a); | |
3933 | let b: int16x4_t = vdup_n_s16(b); | |
3934 | simd_extract(vqsub_s16(a, b), 0) | |
3935 | } | |
3936 | ||
3937 | /// Saturating subtract | |
3938 | #[inline] | |
3939 | #[target_feature(enable = "neon")] | |
3940 | #[cfg_attr(test, assert_instr(uqsub))] | |
3941 | pub unsafe fn vqsubb_u8(a: u8, b: u8) -> u8 { | |
3942 | let a: uint8x8_t = vdup_n_u8(a); | |
3943 | let b: uint8x8_t = vdup_n_u8(b); | |
3944 | simd_extract(vqsub_u8(a, b), 0) | |
3945 | } | |
3946 | ||
3947 | /// Saturating subtract | |
3948 | #[inline] | |
3949 | #[target_feature(enable = "neon")] | |
3950 | #[cfg_attr(test, assert_instr(uqsub))] | |
3951 | pub unsafe fn vqsubh_u16(a: u16, b: u16) -> u16 { | |
3952 | let a: uint16x4_t = vdup_n_u16(a); | |
3953 | let b: uint16x4_t = vdup_n_u16(b); | |
3954 | simd_extract(vqsub_u16(a, b), 0) | |
3955 | } | |
3956 | ||
3957 | /// Saturating subtract | |
3958 | #[inline] | |
3959 | #[target_feature(enable = "neon")] | |
3960 | #[cfg_attr(test, assert_instr(uqsub))] | |
3961 | pub unsafe fn vqsubs_u32(a: u32, b: u32) -> u32 { | |
3962 | #[allow(improper_ctypes)] | |
3963 | extern "C" { | |
3964 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqsub.i32")] | |
3965 | fn vqsubs_u32_(a: u32, b: u32) -> u32; | |
3966 | } | |
3967 | vqsubs_u32_(a, b) | |
3968 | } | |
3969 | ||
3970 | /// Saturating subtract | |
3971 | #[inline] | |
3972 | #[target_feature(enable = "neon")] | |
3973 | #[cfg_attr(test, assert_instr(uqsub))] | |
3974 | pub unsafe fn vqsubd_u64(a: u64, b: u64) -> u64 { | |
3975 | #[allow(improper_ctypes)] | |
3976 | extern "C" { | |
3977 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqsub.i64")] | |
3978 | fn vqsubd_u64_(a: u64, b: u64) -> u64; | |
3979 | } | |
3980 | vqsubd_u64_(a, b) | |
3981 | } | |
3982 | ||
3983 | /// Saturating subtract | |
3984 | #[inline] | |
3985 | #[target_feature(enable = "neon")] | |
3986 | #[cfg_attr(test, assert_instr(sqsub))] | |
3987 | pub unsafe fn vqsubs_s32(a: i32, b: i32) -> i32 { | |
3988 | #[allow(improper_ctypes)] | |
3989 | extern "C" { | |
3990 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqsub.i32")] | |
3991 | fn vqsubs_s32_(a: i32, b: i32) -> i32; | |
3992 | } | |
3993 | vqsubs_s32_(a, b) | |
3994 | } | |
3995 | ||
3996 | /// Saturating subtract | |
3997 | #[inline] | |
3998 | #[target_feature(enable = "neon")] | |
3999 | #[cfg_attr(test, assert_instr(sqsub))] | |
4000 | pub unsafe fn vqsubd_s64(a: i64, b: i64) -> i64 { | |
4001 | #[allow(improper_ctypes)] | |
4002 | extern "C" { | |
4003 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqsub.i64")] | |
4004 | fn vqsubd_s64_(a: i64, b: i64) -> i64; | |
4005 | } | |
4006 | vqsubd_s64_(a, b) | |
4007 | } | |
4008 | ||
4009 | /// Reverse bit order | |
4010 | #[inline] | |
4011 | #[target_feature(enable = "neon")] | |
4012 | #[cfg_attr(test, assert_instr(rbit))] | |
4013 | pub unsafe fn vrbit_s8(a: int8x8_t) -> int8x8_t { | |
4014 | #[allow(improper_ctypes)] | |
4015 | extern "C" { | |
4016 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.rbit.v8i8")] | |
4017 | fn vrbit_s8_(a: int8x8_t) -> int8x8_t; | |
4018 | } | |
4019 | vrbit_s8_(a) | |
4020 | } | |
4021 | ||
4022 | /// Reverse bit order | |
4023 | #[inline] | |
4024 | #[target_feature(enable = "neon")] | |
4025 | #[cfg_attr(test, assert_instr(rbit))] | |
4026 | pub unsafe fn vrbitq_s8(a: int8x16_t) -> int8x16_t { | |
4027 | #[allow(improper_ctypes)] | |
4028 | extern "C" { | |
4029 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.rbit.v16i8")] | |
4030 | fn vrbitq_s8_(a: int8x16_t) -> int8x16_t; | |
4031 | } | |
4032 | vrbitq_s8_(a) | |
4033 | } | |
4034 | ||
4035 | /// Reverse bit order | |
4036 | #[inline] | |
4037 | #[target_feature(enable = "neon")] | |
4038 | #[cfg_attr(test, assert_instr(rbit))] | |
4039 | pub unsafe fn vrbit_u8(a: uint8x8_t) -> uint8x8_t { | |
4040 | transmute(vrbit_s8(transmute(a))) | |
4041 | } | |
4042 | ||
4043 | /// Reverse bit order | |
4044 | #[inline] | |
4045 | #[target_feature(enable = "neon")] | |
4046 | #[cfg_attr(test, assert_instr(rbit))] | |
4047 | pub unsafe fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t { | |
4048 | transmute(vrbitq_s8(transmute(a))) | |
4049 | } | |
4050 | ||
4051 | /// Reverse bit order | |
4052 | #[inline] | |
4053 | #[target_feature(enable = "neon")] | |
4054 | #[cfg_attr(test, assert_instr(rbit))] | |
4055 | pub unsafe fn vrbit_p8(a: poly8x8_t) -> poly8x8_t { | |
4056 | transmute(vrbit_s8(transmute(a))) | |
4057 | } | |
4058 | ||
4059 | /// Reverse bit order | |
4060 | #[inline] | |
4061 | #[target_feature(enable = "neon")] | |
4062 | #[cfg_attr(test, assert_instr(rbit))] | |
4063 | pub unsafe fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t { | |
4064 | transmute(vrbitq_s8(transmute(a))) | |
4065 | } | |
4066 | ||
4067 | /// Floating-point round to integral exact, using current rounding mode | |
4068 | #[inline] | |
4069 | #[target_feature(enable = "neon")] | |
4070 | #[cfg_attr(test, assert_instr(frintx))] | |
4071 | pub unsafe fn vrndx_f32(a: float32x2_t) -> float32x2_t { | |
4072 | #[allow(improper_ctypes)] | |
4073 | extern "C" { | |
4074 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.rint.v2f32")] | |
4075 | fn vrndx_f32_(a: float32x2_t) -> float32x2_t; | |
4076 | } | |
4077 | vrndx_f32_(a) | |
4078 | } | |
4079 | ||
4080 | /// Floating-point round to integral exact, using current rounding mode | |
4081 | #[inline] | |
4082 | #[target_feature(enable = "neon")] | |
4083 | #[cfg_attr(test, assert_instr(frintx))] | |
4084 | pub unsafe fn vrndxq_f32(a: float32x4_t) -> float32x4_t { | |
4085 | #[allow(improper_ctypes)] | |
4086 | extern "C" { | |
4087 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.rint.v4f32")] | |
4088 | fn vrndxq_f32_(a: float32x4_t) -> float32x4_t; | |
4089 | } | |
4090 | vrndxq_f32_(a) | |
4091 | } | |
4092 | ||
4093 | /// Floating-point round to integral exact, using current rounding mode | |
4094 | #[inline] | |
4095 | #[target_feature(enable = "neon")] | |
4096 | #[cfg_attr(test, assert_instr(frintx))] | |
4097 | pub unsafe fn vrndx_f64(a: float64x1_t) -> float64x1_t { | |
4098 | #[allow(improper_ctypes)] | |
4099 | extern "C" { | |
4100 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.rint.v1f64")] | |
4101 | fn vrndx_f64_(a: float64x1_t) -> float64x1_t; | |
4102 | } | |
4103 | vrndx_f64_(a) | |
4104 | } | |
4105 | ||
4106 | /// Floating-point round to integral exact, using current rounding mode | |
4107 | #[inline] | |
4108 | #[target_feature(enable = "neon")] | |
4109 | #[cfg_attr(test, assert_instr(frintx))] | |
4110 | pub unsafe fn vrndxq_f64(a: float64x2_t) -> float64x2_t { | |
4111 | #[allow(improper_ctypes)] | |
4112 | extern "C" { | |
4113 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.rint.v2f64")] | |
4114 | fn vrndxq_f64_(a: float64x2_t) -> float64x2_t; | |
4115 | } | |
4116 | vrndxq_f64_(a) | |
4117 | } | |
4118 | ||
4119 | /// Floating-point round to integral, to nearest with ties to away | |
4120 | #[inline] | |
4121 | #[target_feature(enable = "neon")] | |
4122 | #[cfg_attr(test, assert_instr(frinta))] | |
4123 | pub unsafe fn vrnda_f32(a: float32x2_t) -> float32x2_t { | |
4124 | #[allow(improper_ctypes)] | |
4125 | extern "C" { | |
4126 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.round.v2f32")] | |
4127 | fn vrnda_f32_(a: float32x2_t) -> float32x2_t; | |
4128 | } | |
4129 | vrnda_f32_(a) | |
4130 | } | |
4131 | ||
4132 | /// Floating-point round to integral, to nearest with ties to away | |
4133 | #[inline] | |
4134 | #[target_feature(enable = "neon")] | |
4135 | #[cfg_attr(test, assert_instr(frinta))] | |
4136 | pub unsafe fn vrndaq_f32(a: float32x4_t) -> float32x4_t { | |
4137 | #[allow(improper_ctypes)] | |
4138 | extern "C" { | |
4139 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.round.v4f32")] | |
4140 | fn vrndaq_f32_(a: float32x4_t) -> float32x4_t; | |
4141 | } | |
4142 | vrndaq_f32_(a) | |
4143 | } | |
4144 | ||
4145 | /// Floating-point round to integral, to nearest with ties to away | |
4146 | #[inline] | |
4147 | #[target_feature(enable = "neon")] | |
4148 | #[cfg_attr(test, assert_instr(frinta))] | |
4149 | pub unsafe fn vrnda_f64(a: float64x1_t) -> float64x1_t { | |
4150 | #[allow(improper_ctypes)] | |
4151 | extern "C" { | |
4152 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.round.v1f64")] | |
4153 | fn vrnda_f64_(a: float64x1_t) -> float64x1_t; | |
4154 | } | |
4155 | vrnda_f64_(a) | |
4156 | } | |
4157 | ||
4158 | /// Floating-point round to integral, to nearest with ties to away | |
4159 | #[inline] | |
4160 | #[target_feature(enable = "neon")] | |
4161 | #[cfg_attr(test, assert_instr(frinta))] | |
4162 | pub unsafe fn vrndaq_f64(a: float64x2_t) -> float64x2_t { | |
4163 | #[allow(improper_ctypes)] | |
4164 | extern "C" { | |
4165 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.round.v2f64")] | |
4166 | fn vrndaq_f64_(a: float64x2_t) -> float64x2_t; | |
4167 | } | |
4168 | vrndaq_f64_(a) | |
4169 | } | |
4170 | ||
4171 | /// Floating-point round to integral, to nearest with ties to even | |
4172 | #[inline] | |
4173 | #[target_feature(enable = "neon")] | |
4174 | #[cfg_attr(test, assert_instr(frintn))] | |
4175 | pub unsafe fn vrndn_f64(a: float64x1_t) -> float64x1_t { | |
4176 | #[allow(improper_ctypes)] | |
4177 | extern "C" { | |
4178 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.frintn.v1f64")] | |
4179 | fn vrndn_f64_(a: float64x1_t) -> float64x1_t; | |
4180 | } | |
4181 | vrndn_f64_(a) | |
4182 | } | |
4183 | ||
4184 | /// Floating-point round to integral, to nearest with ties to even | |
4185 | #[inline] | |
4186 | #[target_feature(enable = "neon")] | |
4187 | #[cfg_attr(test, assert_instr(frintn))] | |
4188 | pub unsafe fn vrndnq_f64(a: float64x2_t) -> float64x2_t { | |
4189 | #[allow(improper_ctypes)] | |
4190 | extern "C" { | |
4191 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.frintn.v2f64")] | |
4192 | fn vrndnq_f64_(a: float64x2_t) -> float64x2_t; | |
4193 | } | |
4194 | vrndnq_f64_(a) | |
4195 | } | |
4196 | ||
4197 | /// Floating-point round to integral, toward minus infinity | |
4198 | #[inline] | |
4199 | #[target_feature(enable = "neon")] | |
4200 | #[cfg_attr(test, assert_instr(frintm))] | |
4201 | pub unsafe fn vrndm_f32(a: float32x2_t) -> float32x2_t { | |
4202 | #[allow(improper_ctypes)] | |
4203 | extern "C" { | |
4204 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.floor.v2f32")] | |
4205 | fn vrndm_f32_(a: float32x2_t) -> float32x2_t; | |
4206 | } | |
4207 | vrndm_f32_(a) | |
4208 | } | |
4209 | ||
4210 | /// Floating-point round to integral, toward minus infinity | |
4211 | #[inline] | |
4212 | #[target_feature(enable = "neon")] | |
4213 | #[cfg_attr(test, assert_instr(frintm))] | |
4214 | pub unsafe fn vrndmq_f32(a: float32x4_t) -> float32x4_t { | |
4215 | #[allow(improper_ctypes)] | |
4216 | extern "C" { | |
4217 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.floor.v4f32")] | |
4218 | fn vrndmq_f32_(a: float32x4_t) -> float32x4_t; | |
4219 | } | |
4220 | vrndmq_f32_(a) | |
4221 | } | |
4222 | ||
4223 | /// Floating-point round to integral, toward minus infinity | |
4224 | #[inline] | |
4225 | #[target_feature(enable = "neon")] | |
4226 | #[cfg_attr(test, assert_instr(frintm))] | |
4227 | pub unsafe fn vrndm_f64(a: float64x1_t) -> float64x1_t { | |
4228 | #[allow(improper_ctypes)] | |
4229 | extern "C" { | |
4230 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.floor.v1f64")] | |
4231 | fn vrndm_f64_(a: float64x1_t) -> float64x1_t; | |
4232 | } | |
4233 | vrndm_f64_(a) | |
4234 | } | |
4235 | ||
4236 | /// Floating-point round to integral, toward minus infinity | |
4237 | #[inline] | |
4238 | #[target_feature(enable = "neon")] | |
4239 | #[cfg_attr(test, assert_instr(frintm))] | |
4240 | pub unsafe fn vrndmq_f64(a: float64x2_t) -> float64x2_t { | |
4241 | #[allow(improper_ctypes)] | |
4242 | extern "C" { | |
4243 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.floor.v2f64")] | |
4244 | fn vrndmq_f64_(a: float64x2_t) -> float64x2_t; | |
4245 | } | |
4246 | vrndmq_f64_(a) | |
4247 | } | |
4248 | ||
4249 | /// Floating-point round to integral, toward plus infinity | |
4250 | #[inline] | |
4251 | #[target_feature(enable = "neon")] | |
4252 | #[cfg_attr(test, assert_instr(frintp))] | |
4253 | pub unsafe fn vrndp_f32(a: float32x2_t) -> float32x2_t { | |
4254 | #[allow(improper_ctypes)] | |
4255 | extern "C" { | |
4256 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.ceil.v2f32")] | |
4257 | fn vrndp_f32_(a: float32x2_t) -> float32x2_t; | |
4258 | } | |
4259 | vrndp_f32_(a) | |
4260 | } | |
4261 | ||
4262 | /// Floating-point round to integral, toward plus infinity | |
4263 | #[inline] | |
4264 | #[target_feature(enable = "neon")] | |
4265 | #[cfg_attr(test, assert_instr(frintp))] | |
4266 | pub unsafe fn vrndpq_f32(a: float32x4_t) -> float32x4_t { | |
4267 | #[allow(improper_ctypes)] | |
4268 | extern "C" { | |
4269 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.ceil.v4f32")] | |
4270 | fn vrndpq_f32_(a: float32x4_t) -> float32x4_t; | |
4271 | } | |
4272 | vrndpq_f32_(a) | |
4273 | } | |
4274 | ||
4275 | /// Floating-point round to integral, toward plus infinity | |
4276 | #[inline] | |
4277 | #[target_feature(enable = "neon")] | |
4278 | #[cfg_attr(test, assert_instr(frintp))] | |
4279 | pub unsafe fn vrndp_f64(a: float64x1_t) -> float64x1_t { | |
4280 | #[allow(improper_ctypes)] | |
4281 | extern "C" { | |
4282 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.ceil.v1f64")] | |
4283 | fn vrndp_f64_(a: float64x1_t) -> float64x1_t; | |
4284 | } | |
4285 | vrndp_f64_(a) | |
4286 | } | |
4287 | ||
4288 | /// Floating-point round to integral, toward plus infinity | |
4289 | #[inline] | |
4290 | #[target_feature(enable = "neon")] | |
4291 | #[cfg_attr(test, assert_instr(frintp))] | |
4292 | pub unsafe fn vrndpq_f64(a: float64x2_t) -> float64x2_t { | |
4293 | #[allow(improper_ctypes)] | |
4294 | extern "C" { | |
4295 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.ceil.v2f64")] | |
4296 | fn vrndpq_f64_(a: float64x2_t) -> float64x2_t; | |
4297 | } | |
4298 | vrndpq_f64_(a) | |
4299 | } | |
4300 | ||
4301 | /// Floating-point round to integral, toward zero | |
4302 | #[inline] | |
4303 | #[target_feature(enable = "neon")] | |
4304 | #[cfg_attr(test, assert_instr(frintz))] | |
4305 | pub unsafe fn vrnd_f32(a: float32x2_t) -> float32x2_t { | |
4306 | #[allow(improper_ctypes)] | |
4307 | extern "C" { | |
4308 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.trunc.v2f32")] | |
4309 | fn vrnd_f32_(a: float32x2_t) -> float32x2_t; | |
4310 | } | |
4311 | vrnd_f32_(a) | |
4312 | } | |
4313 | ||
4314 | /// Floating-point round to integral, toward zero | |
4315 | #[inline] | |
4316 | #[target_feature(enable = "neon")] | |
4317 | #[cfg_attr(test, assert_instr(frintz))] | |
4318 | pub unsafe fn vrndq_f32(a: float32x4_t) -> float32x4_t { | |
4319 | #[allow(improper_ctypes)] | |
4320 | extern "C" { | |
4321 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.trunc.v4f32")] | |
4322 | fn vrndq_f32_(a: float32x4_t) -> float32x4_t; | |
4323 | } | |
4324 | vrndq_f32_(a) | |
4325 | } | |
4326 | ||
4327 | /// Floating-point round to integral, toward zero | |
4328 | #[inline] | |
4329 | #[target_feature(enable = "neon")] | |
4330 | #[cfg_attr(test, assert_instr(frintz))] | |
4331 | pub unsafe fn vrnd_f64(a: float64x1_t) -> float64x1_t { | |
4332 | #[allow(improper_ctypes)] | |
4333 | extern "C" { | |
4334 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.trunc.v1f64")] | |
4335 | fn vrnd_f64_(a: float64x1_t) -> float64x1_t; | |
4336 | } | |
4337 | vrnd_f64_(a) | |
4338 | } | |
4339 | ||
4340 | /// Floating-point round to integral, toward zero | |
4341 | #[inline] | |
4342 | #[target_feature(enable = "neon")] | |
4343 | #[cfg_attr(test, assert_instr(frintz))] | |
4344 | pub unsafe fn vrndq_f64(a: float64x2_t) -> float64x2_t { | |
4345 | #[allow(improper_ctypes)] | |
4346 | extern "C" { | |
4347 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.trunc.v2f64")] | |
4348 | fn vrndq_f64_(a: float64x2_t) -> float64x2_t; | |
4349 | } | |
4350 | vrndq_f64_(a) | |
4351 | } | |
4352 | ||
4353 | /// Floating-point round to integral, using current rounding mode | |
4354 | #[inline] | |
4355 | #[target_feature(enable = "neon")] | |
4356 | #[cfg_attr(test, assert_instr(frinti))] | |
4357 | pub unsafe fn vrndi_f32(a: float32x2_t) -> float32x2_t { | |
4358 | #[allow(improper_ctypes)] | |
4359 | extern "C" { | |
4360 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.nearbyint.v2f32")] | |
4361 | fn vrndi_f32_(a: float32x2_t) -> float32x2_t; | |
4362 | } | |
4363 | vrndi_f32_(a) | |
4364 | } | |
4365 | ||
4366 | /// Floating-point round to integral, using current rounding mode | |
4367 | #[inline] | |
4368 | #[target_feature(enable = "neon")] | |
4369 | #[cfg_attr(test, assert_instr(frinti))] | |
4370 | pub unsafe fn vrndiq_f32(a: float32x4_t) -> float32x4_t { | |
4371 | #[allow(improper_ctypes)] | |
4372 | extern "C" { | |
4373 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.nearbyint.v4f32")] | |
4374 | fn vrndiq_f32_(a: float32x4_t) -> float32x4_t; | |
4375 | } | |
4376 | vrndiq_f32_(a) | |
4377 | } | |
4378 | ||
4379 | /// Floating-point round to integral, using current rounding mode | |
4380 | #[inline] | |
4381 | #[target_feature(enable = "neon")] | |
4382 | #[cfg_attr(test, assert_instr(frinti))] | |
4383 | pub unsafe fn vrndi_f64(a: float64x1_t) -> float64x1_t { | |
4384 | #[allow(improper_ctypes)] | |
4385 | extern "C" { | |
4386 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.nearbyint.v1f64")] | |
4387 | fn vrndi_f64_(a: float64x1_t) -> float64x1_t; | |
4388 | } | |
4389 | vrndi_f64_(a) | |
4390 | } | |
4391 | ||
4392 | /// Floating-point round to integral, using current rounding mode | |
4393 | #[inline] | |
4394 | #[target_feature(enable = "neon")] | |
4395 | #[cfg_attr(test, assert_instr(frinti))] | |
4396 | pub unsafe fn vrndiq_f64(a: float64x2_t) -> float64x2_t { | |
4397 | #[allow(improper_ctypes)] | |
4398 | extern "C" { | |
4399 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.nearbyint.v2f64")] | |
4400 | fn vrndiq_f64_(a: float64x2_t) -> float64x2_t; | |
4401 | } | |
4402 | vrndiq_f64_(a) | |
4403 | } | |
4404 | ||
4405 | /// Saturating add | |
4406 | #[inline] | |
4407 | #[target_feature(enable = "neon")] | |
4408 | #[cfg_attr(test, assert_instr(sqadd))] | |
4409 | pub unsafe fn vqaddb_s8(a: i8, b: i8) -> i8 { | |
4410 | let a: int8x8_t = vdup_n_s8(a); | |
4411 | let b: int8x8_t = vdup_n_s8(b); | |
4412 | simd_extract(vqadd_s8(a, b), 0) | |
4413 | } | |
4414 | ||
4415 | /// Saturating add | |
4416 | #[inline] | |
4417 | #[target_feature(enable = "neon")] | |
4418 | #[cfg_attr(test, assert_instr(sqadd))] | |
4419 | pub unsafe fn vqaddh_s16(a: i16, b: i16) -> i16 { | |
4420 | let a: int16x4_t = vdup_n_s16(a); | |
4421 | let b: int16x4_t = vdup_n_s16(b); | |
4422 | simd_extract(vqadd_s16(a, b), 0) | |
4423 | } | |
4424 | ||
4425 | /// Saturating add | |
4426 | #[inline] | |
4427 | #[target_feature(enable = "neon")] | |
4428 | #[cfg_attr(test, assert_instr(uqadd))] | |
4429 | pub unsafe fn vqaddb_u8(a: u8, b: u8) -> u8 { | |
4430 | let a: uint8x8_t = vdup_n_u8(a); | |
4431 | let b: uint8x8_t = vdup_n_u8(b); | |
4432 | simd_extract(vqadd_u8(a, b), 0) | |
4433 | } | |
4434 | ||
4435 | /// Saturating add | |
4436 | #[inline] | |
4437 | #[target_feature(enable = "neon")] | |
4438 | #[cfg_attr(test, assert_instr(uqadd))] | |
4439 | pub unsafe fn vqaddh_u16(a: u16, b: u16) -> u16 { | |
4440 | let a: uint16x4_t = vdup_n_u16(a); | |
4441 | let b: uint16x4_t = vdup_n_u16(b); | |
4442 | simd_extract(vqadd_u16(a, b), 0) | |
4443 | } | |
4444 | ||
4445 | /// Saturating add | |
4446 | #[inline] | |
4447 | #[target_feature(enable = "neon")] | |
4448 | #[cfg_attr(test, assert_instr(uqadd))] | |
4449 | pub unsafe fn vqadds_u32(a: u32, b: u32) -> u32 { | |
4450 | #[allow(improper_ctypes)] | |
4451 | extern "C" { | |
4452 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqadd.i32")] | |
4453 | fn vqadds_u32_(a: u32, b: u32) -> u32; | |
4454 | } | |
4455 | vqadds_u32_(a, b) | |
4456 | } | |
4457 | ||
4458 | /// Saturating add | |
4459 | #[inline] | |
4460 | #[target_feature(enable = "neon")] | |
4461 | #[cfg_attr(test, assert_instr(uqadd))] | |
4462 | pub unsafe fn vqaddd_u64(a: u64, b: u64) -> u64 { | |
4463 | #[allow(improper_ctypes)] | |
4464 | extern "C" { | |
4465 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqadd.i64")] | |
4466 | fn vqaddd_u64_(a: u64, b: u64) -> u64; | |
4467 | } | |
4468 | vqaddd_u64_(a, b) | |
4469 | } | |
4470 | ||
4471 | /// Saturating add | |
4472 | #[inline] | |
4473 | #[target_feature(enable = "neon")] | |
4474 | #[cfg_attr(test, assert_instr(sqadd))] | |
4475 | pub unsafe fn vqadds_s32(a: i32, b: i32) -> i32 { | |
4476 | #[allow(improper_ctypes)] | |
4477 | extern "C" { | |
4478 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqadd.i32")] | |
4479 | fn vqadds_s32_(a: i32, b: i32) -> i32; | |
4480 | } | |
4481 | vqadds_s32_(a, b) | |
4482 | } | |
4483 | ||
4484 | /// Saturating add | |
4485 | #[inline] | |
4486 | #[target_feature(enable = "neon")] | |
4487 | #[cfg_attr(test, assert_instr(sqadd))] | |
4488 | pub unsafe fn vqaddd_s64(a: i64, b: i64) -> i64 { | |
4489 | #[allow(improper_ctypes)] | |
4490 | extern "C" { | |
4491 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqadd.i64")] | |
4492 | fn vqaddd_s64_(a: i64, b: i64) -> i64; | |
4493 | } | |
4494 | vqaddd_s64_(a, b) | |
4495 | } | |
4496 | ||
4497 | /// Multiply | |
4498 | #[inline] | |
4499 | #[target_feature(enable = "neon")] | |
4500 | #[cfg_attr(test, assert_instr(fmul))] | |
4501 | pub unsafe fn vmul_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
4502 | simd_mul(a, b) | |
4503 | } | |
4504 | ||
4505 | /// Multiply | |
4506 | #[inline] | |
4507 | #[target_feature(enable = "neon")] | |
4508 | #[cfg_attr(test, assert_instr(fmul))] | |
4509 | pub unsafe fn vmulq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
4510 | simd_mul(a, b) | |
4511 | } | |
4512 | ||
4513 | /// Vector multiply by scalar | |
4514 | #[inline] | |
4515 | #[target_feature(enable = "neon")] | |
4516 | #[cfg_attr(test, assert_instr(fmul))] | |
4517 | pub unsafe fn vmul_n_f64(a: float64x1_t, b: f64) -> float64x1_t { | |
4518 | simd_mul(a, vdup_n_f64(b)) | |
4519 | } | |
4520 | ||
4521 | /// Vector multiply by scalar | |
4522 | #[inline] | |
4523 | #[target_feature(enable = "neon")] | |
4524 | #[cfg_attr(test, assert_instr(fmul))] | |
4525 | pub unsafe fn vmulq_n_f64(a: float64x2_t, b: f64) -> float64x2_t { | |
4526 | simd_mul(a, vdupq_n_f64(b)) | |
4527 | } | |
4528 | ||
4529 | /// Floating-point multiply | |
4530 | #[inline] | |
4531 | #[target_feature(enable = "neon")] | |
4532 | #[cfg_attr(test, assert_instr(fmul, LANE = 0))] | |
4533 | #[rustc_legacy_const_generics(2)] | |
4534 | pub unsafe fn vmul_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
4535 | static_assert!(LANE : i32 where LANE == 0); | |
4536 | simd_mul(a, transmute::<f64, _>(simd_extract(b, LANE as u32))) | |
4537 | } | |
4538 | ||
4539 | /// Floating-point multiply | |
4540 | #[inline] | |
4541 | #[target_feature(enable = "neon")] | |
4542 | #[cfg_attr(test, assert_instr(fmul, LANE = 0))] | |
4543 | #[rustc_legacy_const_generics(2)] | |
4544 | pub unsafe fn vmul_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x2_t) -> float64x1_t { | |
4545 | static_assert_imm1!(LANE); | |
4546 | simd_mul(a, transmute::<f64, _>(simd_extract(b, LANE as u32))) | |
4547 | } | |
4548 | ||
4549 | /// Floating-point multiply | |
4550 | #[inline] | |
4551 | #[target_feature(enable = "neon")] | |
4552 | #[cfg_attr(test, assert_instr(fmul, LANE = 0))] | |
4553 | #[rustc_legacy_const_generics(2)] | |
4554 | pub unsafe fn vmulq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x1_t) -> float64x2_t { | |
4555 | static_assert!(LANE : i32 where LANE == 0); | |
4556 | simd_mul(a, simd_shuffle2!(b, b, <const LANE: i32> [LANE as u32, LANE as u32])) | |
4557 | } | |
4558 | ||
4559 | /// Floating-point multiply | |
4560 | #[inline] | |
4561 | #[target_feature(enable = "neon")] | |
4562 | #[cfg_attr(test, assert_instr(fmul, LANE = 0))] | |
4563 | #[rustc_legacy_const_generics(2)] | |
4564 | pub unsafe fn vmulq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
4565 | static_assert_imm1!(LANE); | |
4566 | simd_mul(a, simd_shuffle2!(b, b, <const LANE: i32> [LANE as u32, LANE as u32])) | |
4567 | } | |
4568 | ||
4569 | /// Floating-point multiply | |
4570 | #[inline] | |
4571 | #[target_feature(enable = "neon")] | |
4572 | #[cfg_attr(test, assert_instr(fmul, LANE = 0))] | |
4573 | #[rustc_legacy_const_generics(2)] | |
4574 | pub unsafe fn vmuls_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> f32 { | |
4575 | static_assert_imm1!(LANE); | |
4576 | let b: f32 = simd_extract(b, LANE as u32); | |
4577 | a * b | |
4578 | } | |
4579 | ||
4580 | /// Floating-point multiply | |
4581 | #[inline] | |
4582 | #[target_feature(enable = "neon")] | |
4583 | #[cfg_attr(test, assert_instr(fmul, LANE = 0))] | |
4584 | #[rustc_legacy_const_generics(2)] | |
4585 | pub unsafe fn vmuls_laneq_f32<const LANE: i32>(a: f32, b: float32x4_t) -> f32 { | |
4586 | static_assert_imm2!(LANE); | |
4587 | let b: f32 = simd_extract(b, LANE as u32); | |
4588 | a * b | |
4589 | } | |
4590 | ||
4591 | /// Floating-point multiply | |
4592 | #[inline] | |
4593 | #[target_feature(enable = "neon")] | |
4594 | #[cfg_attr(test, assert_instr(fmul, LANE = 0))] | |
4595 | #[rustc_legacy_const_generics(2)] | |
4596 | pub unsafe fn vmuld_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> f64 { | |
4597 | static_assert!(LANE : i32 where LANE == 0); | |
4598 | let b: f64 = simd_extract(b, LANE as u32); | |
4599 | a * b | |
4600 | } | |
4601 | ||
4602 | /// Floating-point multiply | |
4603 | #[inline] | |
4604 | #[target_feature(enable = "neon")] | |
4605 | #[cfg_attr(test, assert_instr(fmul, LANE = 0))] | |
4606 | #[rustc_legacy_const_generics(2)] | |
4607 | pub unsafe fn vmuld_laneq_f64<const LANE: i32>(a: f64, b: float64x2_t) -> f64 { | |
4608 | static_assert_imm1!(LANE); | |
4609 | let b: f64 = simd_extract(b, LANE as u32); | |
4610 | a * b | |
4611 | } | |
4612 | ||
4613 | /// Signed multiply long | |
4614 | #[inline] | |
4615 | #[target_feature(enable = "neon")] | |
4616 | #[cfg_attr(test, assert_instr(smull2))] | |
4617 | pub unsafe fn vmull_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { | |
4618 | let a: int8x8_t = simd_shuffle8!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); | |
4619 | let b: int8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
4620 | vmull_s8(a, b) | |
4621 | } | |
4622 | ||
4623 | /// Signed multiply long | |
4624 | #[inline] | |
4625 | #[target_feature(enable = "neon")] | |
4626 | #[cfg_attr(test, assert_instr(smull2))] | |
4627 | pub unsafe fn vmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { | |
4628 | let a: int16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
4629 | let b: int16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
4630 | vmull_s16(a, b) | |
4631 | } | |
4632 | ||
4633 | /// Signed multiply long | |
4634 | #[inline] | |
4635 | #[target_feature(enable = "neon")] | |
4636 | #[cfg_attr(test, assert_instr(smull2))] | |
4637 | pub unsafe fn vmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { | |
4638 | let a: int32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
4639 | let b: int32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
4640 | vmull_s32(a, b) | |
4641 | } | |
4642 | ||
4643 | /// Unsigned multiply long | |
4644 | #[inline] | |
4645 | #[target_feature(enable = "neon")] | |
4646 | #[cfg_attr(test, assert_instr(umull2))] | |
4647 | pub unsafe fn vmull_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { | |
4648 | let a: uint8x8_t = simd_shuffle8!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); | |
4649 | let b: uint8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
4650 | vmull_u8(a, b) | |
4651 | } | |
4652 | ||
4653 | /// Unsigned multiply long | |
4654 | #[inline] | |
4655 | #[target_feature(enable = "neon")] | |
4656 | #[cfg_attr(test, assert_instr(umull2))] | |
4657 | pub unsafe fn vmull_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { | |
4658 | let a: uint16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
4659 | let b: uint16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
4660 | vmull_u16(a, b) | |
4661 | } | |
4662 | ||
4663 | /// Unsigned multiply long | |
4664 | #[inline] | |
4665 | #[target_feature(enable = "neon")] | |
4666 | #[cfg_attr(test, assert_instr(umull2))] | |
4667 | pub unsafe fn vmull_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { | |
4668 | let a: uint32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
4669 | let b: uint32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
4670 | vmull_u32(a, b) | |
4671 | } | |
4672 | ||
4673 | /// Polynomial multiply long | |
4674 | #[inline] | |
4675 | #[target_feature(enable = "neon,crypto")] | |
4676 | #[cfg_attr(test, assert_instr(pmull))] | |
4677 | pub unsafe fn vmull_p64(a: p64, b: p64) -> p128 { | |
4678 | #[allow(improper_ctypes)] | |
4679 | extern "C" { | |
4680 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.pmull64")] | |
4681 | fn vmull_p64_(a: p64, b: p64) -> int8x16_t; | |
4682 | } | |
4683 | transmute(vmull_p64_(a, b)) | |
4684 | } | |
4685 | ||
4686 | /// Polynomial multiply long | |
4687 | #[inline] | |
4688 | #[target_feature(enable = "neon")] | |
4689 | #[cfg_attr(test, assert_instr(pmull))] | |
4690 | pub unsafe fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t { | |
4691 | let a: poly8x8_t = simd_shuffle8!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); | |
4692 | let b: poly8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
4693 | vmull_p8(a, b) | |
4694 | } | |
4695 | ||
4696 | /// Polynomial multiply long | |
4697 | #[inline] | |
4698 | #[target_feature(enable = "neon,crypto")] | |
4699 | #[cfg_attr(test, assert_instr(pmull))] | |
4700 | pub unsafe fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 { | |
4701 | vmull_p64(simd_extract(a, 1), simd_extract(b, 1)) | |
4702 | } | |
4703 | ||
4704 | /// Multiply long | |
4705 | #[inline] | |
4706 | #[target_feature(enable = "neon")] | |
4707 | #[cfg_attr(test, assert_instr(smull2))] | |
4708 | pub unsafe fn vmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t { | |
4709 | vmull_high_s16(a, vdupq_n_s16(b)) | |
4710 | } | |
4711 | ||
4712 | /// Multiply long | |
4713 | #[inline] | |
4714 | #[target_feature(enable = "neon")] | |
4715 | #[cfg_attr(test, assert_instr(smull2))] | |
4716 | pub unsafe fn vmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t { | |
4717 | vmull_high_s32(a, vdupq_n_s32(b)) | |
4718 | } | |
4719 | ||
4720 | /// Multiply long | |
4721 | #[inline] | |
4722 | #[target_feature(enable = "neon")] | |
4723 | #[cfg_attr(test, assert_instr(umull2))] | |
4724 | pub unsafe fn vmull_high_n_u16(a: uint16x8_t, b: u16) -> uint32x4_t { | |
4725 | vmull_high_u16(a, vdupq_n_u16(b)) | |
4726 | } | |
4727 | ||
4728 | /// Multiply long | |
4729 | #[inline] | |
4730 | #[target_feature(enable = "neon")] | |
4731 | #[cfg_attr(test, assert_instr(umull2))] | |
4732 | pub unsafe fn vmull_high_n_u32(a: uint32x4_t, b: u32) -> uint64x2_t { | |
4733 | vmull_high_u32(a, vdupq_n_u32(b)) | |
4734 | } | |
4735 | ||
4736 | /// Multiply long | |
4737 | #[inline] | |
4738 | #[target_feature(enable = "neon")] | |
4739 | #[cfg_attr(test, assert_instr(smull2, LANE = 1))] | |
4740 | #[rustc_legacy_const_generics(2)] | |
4741 | pub unsafe fn vmull_high_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int32x4_t { | |
4742 | static_assert_imm2!(LANE); | |
4743 | vmull_high_s16(a, simd_shuffle8!(b, b, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
4744 | } | |
4745 | ||
4746 | /// Multiply long | |
4747 | #[inline] | |
4748 | #[target_feature(enable = "neon")] | |
4749 | #[cfg_attr(test, assert_instr(smull2, LANE = 1))] | |
4750 | #[rustc_legacy_const_generics(2)] | |
4751 | pub unsafe fn vmull_high_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int32x4_t { | |
4752 | static_assert_imm3!(LANE); | |
4753 | vmull_high_s16(a, simd_shuffle8!(b, b, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
4754 | } | |
4755 | ||
4756 | /// Multiply long | |
4757 | #[inline] | |
4758 | #[target_feature(enable = "neon")] | |
4759 | #[cfg_attr(test, assert_instr(smull2, LANE = 1))] | |
4760 | #[rustc_legacy_const_generics(2)] | |
4761 | pub unsafe fn vmull_high_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int64x2_t { | |
4762 | static_assert_imm1!(LANE); | |
4763 | vmull_high_s32(a, simd_shuffle4!(b, b, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
4764 | } | |
4765 | ||
4766 | /// Multiply long | |
4767 | #[inline] | |
4768 | #[target_feature(enable = "neon")] | |
4769 | #[cfg_attr(test, assert_instr(smull2, LANE = 1))] | |
4770 | #[rustc_legacy_const_generics(2)] | |
4771 | pub unsafe fn vmull_high_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int64x2_t { | |
4772 | static_assert_imm2!(LANE); | |
4773 | vmull_high_s32(a, simd_shuffle4!(b, b, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
4774 | } | |
4775 | ||
4776 | /// Multiply long | |
4777 | #[inline] | |
4778 | #[target_feature(enable = "neon")] | |
4779 | #[cfg_attr(test, assert_instr(umull2, LANE = 1))] | |
4780 | #[rustc_legacy_const_generics(2)] | |
4781 | pub unsafe fn vmull_high_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uint32x4_t { | |
4782 | static_assert_imm2!(LANE); | |
4783 | vmull_high_u16(a, simd_shuffle8!(b, b, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
4784 | } | |
4785 | ||
4786 | /// Multiply long | |
4787 | #[inline] | |
4788 | #[target_feature(enable = "neon")] | |
4789 | #[cfg_attr(test, assert_instr(umull2, LANE = 1))] | |
4790 | #[rustc_legacy_const_generics(2)] | |
4791 | pub unsafe fn vmull_high_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { | |
4792 | static_assert_imm3!(LANE); | |
4793 | vmull_high_u16(a, simd_shuffle8!(b, b, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
4794 | } | |
4795 | ||
4796 | /// Multiply long | |
4797 | #[inline] | |
4798 | #[target_feature(enable = "neon")] | |
4799 | #[cfg_attr(test, assert_instr(umull2, LANE = 1))] | |
4800 | #[rustc_legacy_const_generics(2)] | |
4801 | pub unsafe fn vmull_high_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uint64x2_t { | |
4802 | static_assert_imm1!(LANE); | |
4803 | vmull_high_u32(a, simd_shuffle4!(b, b, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
4804 | } | |
4805 | ||
4806 | /// Multiply long | |
4807 | #[inline] | |
4808 | #[target_feature(enable = "neon")] | |
4809 | #[cfg_attr(test, assert_instr(umull2, LANE = 1))] | |
4810 | #[rustc_legacy_const_generics(2)] | |
4811 | pub unsafe fn vmull_high_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { | |
4812 | static_assert_imm2!(LANE); | |
4813 | vmull_high_u32(a, simd_shuffle4!(b, b, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
4814 | } | |
4815 | ||
4816 | /// Floating-point multiply extended | |
4817 | #[inline] | |
4818 | #[target_feature(enable = "neon")] | |
4819 | #[cfg_attr(test, assert_instr(fmulx))] | |
4820 | pub unsafe fn vmulx_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
4821 | #[allow(improper_ctypes)] | |
4822 | extern "C" { | |
4823 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmulx.v2f32")] | |
4824 | fn vmulx_f32_(a: float32x2_t, b: float32x2_t) -> float32x2_t; | |
4825 | } | |
4826 | vmulx_f32_(a, b) | |
4827 | } | |
4828 | ||
4829 | /// Floating-point multiply extended | |
4830 | #[inline] | |
4831 | #[target_feature(enable = "neon")] | |
4832 | #[cfg_attr(test, assert_instr(fmulx))] | |
4833 | pub unsafe fn vmulxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
4834 | #[allow(improper_ctypes)] | |
4835 | extern "C" { | |
4836 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmulx.v4f32")] | |
4837 | fn vmulxq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t; | |
4838 | } | |
4839 | vmulxq_f32_(a, b) | |
4840 | } | |
4841 | ||
4842 | /// Floating-point multiply extended | |
4843 | #[inline] | |
4844 | #[target_feature(enable = "neon")] | |
4845 | #[cfg_attr(test, assert_instr(fmulx))] | |
4846 | pub unsafe fn vmulx_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
4847 | #[allow(improper_ctypes)] | |
4848 | extern "C" { | |
4849 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmulx.v1f64")] | |
4850 | fn vmulx_f64_(a: float64x1_t, b: float64x1_t) -> float64x1_t; | |
4851 | } | |
4852 | vmulx_f64_(a, b) | |
4853 | } | |
4854 | ||
4855 | /// Floating-point multiply extended | |
4856 | #[inline] | |
4857 | #[target_feature(enable = "neon")] | |
4858 | #[cfg_attr(test, assert_instr(fmulx))] | |
4859 | pub unsafe fn vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
4860 | #[allow(improper_ctypes)] | |
4861 | extern "C" { | |
4862 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmulx.v2f64")] | |
4863 | fn vmulxq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; | |
4864 | } | |
4865 | vmulxq_f64_(a, b) | |
4866 | } | |
4867 | ||
4868 | /// Floating-point multiply extended | |
4869 | #[inline] | |
4870 | #[target_feature(enable = "neon")] | |
4871 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
4872 | #[rustc_legacy_const_generics(2)] | |
4873 | pub unsafe fn vmulx_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
4874 | static_assert!(LANE : i32 where LANE == 0); | |
4875 | vmulx_f64(a, transmute::<f64, _>(simd_extract(b, LANE as u32))) | |
4876 | } | |
4877 | ||
4878 | /// Floating-point multiply extended | |
4879 | #[inline] | |
4880 | #[target_feature(enable = "neon")] | |
4881 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
4882 | #[rustc_legacy_const_generics(2)] | |
4883 | pub unsafe fn vmulx_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x2_t) -> float64x1_t { | |
4884 | static_assert_imm1!(LANE); | |
4885 | vmulx_f64(a, transmute::<f64, _>(simd_extract(b, LANE as u32))) | |
4886 | } | |
4887 | ||
4888 | /// Floating-point multiply extended | |
4889 | #[inline] | |
4890 | #[target_feature(enable = "neon")] | |
4891 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
4892 | #[rustc_legacy_const_generics(2)] | |
4893 | pub unsafe fn vmulx_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
4894 | static_assert_imm1!(LANE); | |
4895 | vmulx_f32(a, simd_shuffle2!(b, b, <const LANE: i32> [LANE as u32, LANE as u32])) | |
4896 | } | |
4897 | ||
4898 | /// Floating-point multiply extended | |
4899 | #[inline] | |
4900 | #[target_feature(enable = "neon")] | |
4901 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
4902 | #[rustc_legacy_const_generics(2)] | |
4903 | pub unsafe fn vmulx_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x4_t) -> float32x2_t { | |
4904 | static_assert_imm2!(LANE); | |
4905 | vmulx_f32(a, simd_shuffle2!(b, b, <const LANE: i32> [LANE as u32, LANE as u32])) | |
4906 | } | |
4907 | ||
4908 | /// Floating-point multiply extended | |
4909 | #[inline] | |
4910 | #[target_feature(enable = "neon")] | |
4911 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
4912 | #[rustc_legacy_const_generics(2)] | |
4913 | pub unsafe fn vmulxq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x2_t) -> float32x4_t { | |
4914 | static_assert_imm1!(LANE); | |
4915 | vmulxq_f32(a, simd_shuffle4!(b, b, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
4916 | } | |
4917 | ||
4918 | /// Floating-point multiply extended | |
4919 | #[inline] | |
4920 | #[target_feature(enable = "neon")] | |
4921 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
4922 | #[rustc_legacy_const_generics(2)] | |
4923 | pub unsafe fn vmulxq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
4924 | static_assert_imm2!(LANE); | |
4925 | vmulxq_f32(a, simd_shuffle4!(b, b, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
4926 | } | |
4927 | ||
4928 | /// Floating-point multiply extended | |
4929 | #[inline] | |
4930 | #[target_feature(enable = "neon")] | |
4931 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
4932 | #[rustc_legacy_const_generics(2)] | |
4933 | pub unsafe fn vmulxq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x1_t) -> float64x2_t { | |
4934 | static_assert!(LANE : i32 where LANE == 0); | |
4935 | vmulxq_f64(a, simd_shuffle2!(b, b, <const LANE: i32> [LANE as u32, LANE as u32])) | |
4936 | } | |
4937 | ||
4938 | /// Floating-point multiply extended | |
4939 | #[inline] | |
4940 | #[target_feature(enable = "neon")] | |
4941 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
4942 | #[rustc_legacy_const_generics(2)] | |
4943 | pub unsafe fn vmulxq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
4944 | static_assert_imm1!(LANE); | |
4945 | vmulxq_f64(a, simd_shuffle2!(b, b, <const LANE: i32> [LANE as u32, LANE as u32])) | |
4946 | } | |
4947 | ||
4948 | /// Floating-point multiply extended | |
4949 | #[inline] | |
4950 | #[target_feature(enable = "neon")] | |
4951 | #[cfg_attr(test, assert_instr(fmulx))] | |
4952 | pub unsafe fn vmulxs_f32(a: f32, b: f32) -> f32 { | |
4953 | #[allow(improper_ctypes)] | |
4954 | extern "C" { | |
4955 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmulx.f32")] | |
4956 | fn vmulxs_f32_(a: f32, b: f32) -> f32; | |
4957 | } | |
4958 | vmulxs_f32_(a, b) | |
4959 | } | |
4960 | ||
4961 | /// Floating-point multiply extended | |
4962 | #[inline] | |
4963 | #[target_feature(enable = "neon")] | |
4964 | #[cfg_attr(test, assert_instr(fmulx))] | |
4965 | pub unsafe fn vmulxd_f64(a: f64, b: f64) -> f64 { | |
4966 | #[allow(improper_ctypes)] | |
4967 | extern "C" { | |
4968 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmulx.f64")] | |
4969 | fn vmulxd_f64_(a: f64, b: f64) -> f64; | |
4970 | } | |
4971 | vmulxd_f64_(a, b) | |
4972 | } | |
4973 | ||
4974 | /// Floating-point multiply extended | |
4975 | #[inline] | |
4976 | #[target_feature(enable = "neon")] | |
4977 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
4978 | #[rustc_legacy_const_generics(2)] | |
4979 | pub unsafe fn vmulxs_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> f32 { | |
4980 | static_assert_imm1!(LANE); | |
4981 | vmulxs_f32(a, simd_extract(b, LANE as u32)) | |
4982 | } | |
4983 | ||
4984 | /// Floating-point multiply extended | |
4985 | #[inline] | |
4986 | #[target_feature(enable = "neon")] | |
4987 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
4988 | #[rustc_legacy_const_generics(2)] | |
4989 | pub unsafe fn vmulxs_laneq_f32<const LANE: i32>(a: f32, b: float32x4_t) -> f32 { | |
4990 | static_assert_imm2!(LANE); | |
4991 | vmulxs_f32(a, simd_extract(b, LANE as u32)) | |
4992 | } | |
4993 | ||
4994 | /// Floating-point multiply extended | |
4995 | #[inline] | |
4996 | #[target_feature(enable = "neon")] | |
4997 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
4998 | #[rustc_legacy_const_generics(2)] | |
4999 | pub unsafe fn vmulxd_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> f64 { | |
5000 | static_assert!(LANE : i32 where LANE == 0); | |
5001 | vmulxd_f64(a, simd_extract(b, LANE as u32)) | |
5002 | } | |
5003 | ||
5004 | /// Floating-point multiply extended | |
5005 | #[inline] | |
5006 | #[target_feature(enable = "neon")] | |
5007 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
5008 | #[rustc_legacy_const_generics(2)] | |
5009 | pub unsafe fn vmulxd_laneq_f64<const LANE: i32>(a: f64, b: float64x2_t) -> f64 { | |
5010 | static_assert_imm1!(LANE); | |
5011 | vmulxd_f64(a, simd_extract(b, LANE as u32)) | |
5012 | } | |
5013 | ||
5014 | /// Floating-point fused Multiply-Add to accumulator(vector) | |
5015 | #[inline] | |
5016 | #[target_feature(enable = "neon")] | |
5017 | #[cfg_attr(test, assert_instr(fmadd))] | |
5018 | pub unsafe fn vfma_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { | |
5019 | #[allow(improper_ctypes)] | |
5020 | extern "C" { | |
5021 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v1f64")] | |
5022 | fn vfma_f64_(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t; | |
5023 | } | |
5024 | vfma_f64_(b, c, a) | |
5025 | } | |
5026 | ||
5027 | /// Floating-point fused Multiply-Add to accumulator(vector) | |
5028 | #[inline] | |
5029 | #[target_feature(enable = "neon")] | |
5030 | #[cfg_attr(test, assert_instr(fmla))] | |
5031 | pub unsafe fn vfmaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { | |
5032 | #[allow(improper_ctypes)] | |
5033 | extern "C" { | |
5034 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v2f64")] | |
5035 | fn vfmaq_f64_(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; | |
5036 | } | |
5037 | vfmaq_f64_(b, c, a) | |
5038 | } | |
5039 | ||
5040 | /// Floating-point fused Multiply-Add to accumulator(vector) | |
5041 | #[inline] | |
5042 | #[target_feature(enable = "neon")] | |
5043 | #[cfg_attr(test, assert_instr(fmadd))] | |
5044 | pub unsafe fn vfma_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t { | |
5045 | vfma_f64(a, b, vdup_n_f64(c)) | |
5046 | } | |
5047 | ||
5048 | /// Floating-point fused Multiply-Add to accumulator(vector) | |
5049 | #[inline] | |
5050 | #[target_feature(enable = "neon")] | |
5051 | #[cfg_attr(test, assert_instr(fmla))] | |
5052 | pub unsafe fn vfmaq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t { | |
5053 | vfmaq_f64(a, b, vdupq_n_f64(c)) | |
5054 | } | |
5055 | ||
5056 | /// Floating-point fused multiply-add to accumulator | |
5057 | #[inline] | |
5058 | #[target_feature(enable = "neon")] | |
5059 | #[cfg_attr(test, assert_instr(fmla, LANE = 0))] | |
5060 | #[rustc_legacy_const_generics(3)] | |
5061 | pub unsafe fn vfma_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { | |
5062 | static_assert_imm1!(LANE); | |
5063 | vfma_f32(a, b, vdup_n_f32(simd_extract(c, LANE as u32))) | |
5064 | } | |
5065 | ||
5066 | /// Floating-point fused multiply-add to accumulator | |
5067 | #[inline] | |
5068 | #[target_feature(enable = "neon")] | |
5069 | #[cfg_attr(test, assert_instr(fmla, LANE = 0))] | |
5070 | #[rustc_legacy_const_generics(3)] | |
5071 | pub unsafe fn vfma_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t, c: float32x4_t) -> float32x2_t { | |
5072 | static_assert_imm2!(LANE); | |
5073 | vfma_f32(a, b, vdup_n_f32(simd_extract(c, LANE as u32))) | |
5074 | } | |
5075 | ||
5076 | /// Floating-point fused multiply-add to accumulator | |
5077 | #[inline] | |
5078 | #[target_feature(enable = "neon")] | |
5079 | #[cfg_attr(test, assert_instr(fmla, LANE = 0))] | |
5080 | #[rustc_legacy_const_generics(3)] | |
5081 | pub unsafe fn vfmaq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t, c: float32x2_t) -> float32x4_t { | |
5082 | static_assert_imm1!(LANE); | |
5083 | vfmaq_f32(a, b, vdupq_n_f32(simd_extract(c, LANE as u32))) | |
5084 | } | |
5085 | ||
5086 | /// Floating-point fused multiply-add to accumulator | |
5087 | #[inline] | |
5088 | #[target_feature(enable = "neon")] | |
5089 | #[cfg_attr(test, assert_instr(fmla, LANE = 0))] | |
5090 | #[rustc_legacy_const_generics(3)] | |
5091 | pub unsafe fn vfmaq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { | |
5092 | static_assert_imm2!(LANE); | |
5093 | vfmaq_f32(a, b, vdupq_n_f32(simd_extract(c, LANE as u32))) | |
5094 | } | |
5095 | ||
5096 | /// Floating-point fused multiply-add to accumulator | |
5097 | #[inline] | |
5098 | #[target_feature(enable = "neon")] | |
5099 | #[cfg_attr(test, assert_instr(fmadd, LANE = 0))] | |
5100 | #[rustc_legacy_const_generics(3)] | |
5101 | pub unsafe fn vfma_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { | |
5102 | static_assert!(LANE : i32 where LANE == 0); | |
5103 | vfma_f64(a, b, vdup_n_f64(simd_extract(c, LANE as u32))) | |
5104 | } | |
5105 | ||
5106 | /// Floating-point fused multiply-add to accumulator | |
5107 | #[inline] | |
5108 | #[target_feature(enable = "neon")] | |
5109 | #[cfg_attr(test, assert_instr(fmla, LANE = 0))] | |
5110 | #[rustc_legacy_const_generics(3)] | |
5111 | pub unsafe fn vfma_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t, c: float64x2_t) -> float64x1_t { | |
5112 | static_assert_imm1!(LANE); | |
5113 | vfma_f64(a, b, vdup_n_f64(simd_extract(c, LANE as u32))) | |
5114 | } | |
5115 | ||
5116 | /// Floating-point fused multiply-add to accumulator | |
5117 | #[inline] | |
5118 | #[target_feature(enable = "neon")] | |
5119 | #[cfg_attr(test, assert_instr(fmla, LANE = 0))] | |
5120 | #[rustc_legacy_const_generics(3)] | |
5121 | pub unsafe fn vfmaq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t, c: float64x1_t) -> float64x2_t { | |
5122 | static_assert!(LANE : i32 where LANE == 0); | |
5123 | vfmaq_f64(a, b, vdupq_n_f64(simd_extract(c, LANE as u32))) | |
5124 | } | |
5125 | ||
5126 | /// Floating-point fused multiply-add to accumulator | |
5127 | #[inline] | |
5128 | #[target_feature(enable = "neon")] | |
5129 | #[cfg_attr(test, assert_instr(fmla, LANE = 0))] | |
5130 | #[rustc_legacy_const_generics(3)] | |
5131 | pub unsafe fn vfmaq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { | |
5132 | static_assert_imm1!(LANE); | |
5133 | vfmaq_f64(a, b, vdupq_n_f64(simd_extract(c, LANE as u32))) | |
5134 | } | |
5135 | ||
5136 | /// Floating-point fused multiply-add to accumulator | |
5137 | #[inline] | |
5138 | #[target_feature(enable = "neon")] | |
5139 | #[cfg_attr(test, assert_instr(fmla, LANE = 0))] | |
5140 | #[rustc_legacy_const_generics(3)] | |
5141 | pub unsafe fn vfmas_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 { | |
5142 | #[allow(improper_ctypes)] | |
5143 | extern "C" { | |
5144 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.f32")] | |
5145 | fn vfmas_lane_f32_(a: f32, b: f32, c: f32) -> f32; | |
5146 | } | |
5147 | static_assert_imm1!(LANE); | |
5148 | let c: f32 = simd_extract(c, LANE as u32); | |
5149 | vfmas_lane_f32_(b, c, a) | |
5150 | } | |
5151 | ||
5152 | /// Floating-point fused multiply-add to accumulator | |
5153 | #[inline] | |
5154 | #[target_feature(enable = "neon")] | |
5155 | #[cfg_attr(test, assert_instr(fmla, LANE = 0))] | |
5156 | #[rustc_legacy_const_generics(3)] | |
5157 | pub unsafe fn vfmas_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 { | |
5158 | #[allow(improper_ctypes)] | |
5159 | extern "C" { | |
5160 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.f32")] | |
5161 | fn vfmas_laneq_f32_(a: f32, b: f32, c: f32) -> f32; | |
5162 | } | |
5163 | static_assert_imm2!(LANE); | |
5164 | let c: f32 = simd_extract(c, LANE as u32); | |
5165 | vfmas_laneq_f32_(b, c, a) | |
5166 | } | |
5167 | ||
5168 | /// Floating-point fused multiply-add to accumulator | |
5169 | #[inline] | |
5170 | #[target_feature(enable = "neon")] | |
5171 | #[cfg_attr(test, assert_instr(fmadd, LANE = 0))] | |
5172 | #[rustc_legacy_const_generics(3)] | |
5173 | pub unsafe fn vfmad_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) -> f64 { | |
5174 | #[allow(improper_ctypes)] | |
5175 | extern "C" { | |
5176 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.f64")] | |
5177 | fn vfmad_lane_f64_(a: f64, b: f64, c: f64) -> f64; | |
5178 | } | |
5179 | static_assert!(LANE : i32 where LANE == 0); | |
5180 | let c: f64 = simd_extract(c, LANE as u32); | |
5181 | vfmad_lane_f64_(b, c, a) | |
5182 | } | |
5183 | ||
5184 | /// Floating-point fused multiply-add to accumulator | |
5185 | #[inline] | |
5186 | #[target_feature(enable = "neon")] | |
5187 | #[cfg_attr(test, assert_instr(fmla, LANE = 0))] | |
5188 | #[rustc_legacy_const_generics(3)] | |
5189 | pub unsafe fn vfmad_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 { | |
5190 | #[allow(improper_ctypes)] | |
5191 | extern "C" { | |
5192 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.f64")] | |
5193 | fn vfmad_laneq_f64_(a: f64, b: f64, c: f64) -> f64; | |
5194 | } | |
5195 | static_assert_imm1!(LANE); | |
5196 | let c: f64 = simd_extract(c, LANE as u32); | |
5197 | vfmad_laneq_f64_(b, c, a) | |
5198 | } | |
5199 | ||
5200 | /// Floating-point fused multiply-subtract from accumulator | |
5201 | #[inline] | |
5202 | #[target_feature(enable = "neon")] | |
5203 | #[cfg_attr(test, assert_instr(fmsub))] | |
5204 | pub unsafe fn vfms_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { | |
5205 | let b: float64x1_t = simd_neg(b); | |
5206 | vfma_f64(a, b, c) | |
5207 | } | |
5208 | ||
5209 | /// Floating-point fused multiply-subtract from accumulator | |
5210 | #[inline] | |
5211 | #[target_feature(enable = "neon")] | |
5212 | #[cfg_attr(test, assert_instr(fmls))] | |
5213 | pub unsafe fn vfmsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { | |
5214 | let b: float64x2_t = simd_neg(b); | |
5215 | vfmaq_f64(a, b, c) | |
5216 | } | |
5217 | ||
5218 | /// Floating-point fused Multiply-subtract to accumulator(vector) | |
5219 | #[inline] | |
5220 | #[target_feature(enable = "neon")] | |
5221 | #[cfg_attr(test, assert_instr(fmsub))] | |
5222 | pub unsafe fn vfms_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t { | |
5223 | vfms_f64(a, b, vdup_n_f64(c)) | |
5224 | } | |
5225 | ||
5226 | /// Floating-point fused Multiply-subtract to accumulator(vector) | |
5227 | #[inline] | |
5228 | #[target_feature(enable = "neon")] | |
5229 | #[cfg_attr(test, assert_instr(fmls))] | |
5230 | pub unsafe fn vfmsq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t { | |
5231 | vfmsq_f64(a, b, vdupq_n_f64(c)) | |
5232 | } | |
5233 | ||
5234 | /// Floating-point fused multiply-subtract to accumulator | |
5235 | #[inline] | |
5236 | #[target_feature(enable = "neon")] | |
5237 | #[cfg_attr(test, assert_instr(fmls, LANE = 0))] | |
5238 | #[rustc_legacy_const_generics(3)] | |
5239 | pub unsafe fn vfms_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { | |
5240 | static_assert_imm1!(LANE); | |
5241 | vfms_f32(a, b, vdup_n_f32(simd_extract(c, LANE as u32))) | |
5242 | } | |
5243 | ||
5244 | /// Floating-point fused multiply-subtract to accumulator | |
5245 | #[inline] | |
5246 | #[target_feature(enable = "neon")] | |
5247 | #[cfg_attr(test, assert_instr(fmls, LANE = 0))] | |
5248 | #[rustc_legacy_const_generics(3)] | |
5249 | pub unsafe fn vfms_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t, c: float32x4_t) -> float32x2_t { | |
5250 | static_assert_imm2!(LANE); | |
5251 | vfms_f32(a, b, vdup_n_f32(simd_extract(c, LANE as u32))) | |
5252 | } | |
5253 | ||
5254 | /// Floating-point fused multiply-subtract to accumulator | |
5255 | #[inline] | |
5256 | #[target_feature(enable = "neon")] | |
5257 | #[cfg_attr(test, assert_instr(fmls, LANE = 0))] | |
5258 | #[rustc_legacy_const_generics(3)] | |
5259 | pub unsafe fn vfmsq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t, c: float32x2_t) -> float32x4_t { | |
5260 | static_assert_imm1!(LANE); | |
5261 | vfmsq_f32(a, b, vdupq_n_f32(simd_extract(c, LANE as u32))) | |
5262 | } | |
5263 | ||
5264 | /// Floating-point fused multiply-subtract to accumulator | |
5265 | #[inline] | |
5266 | #[target_feature(enable = "neon")] | |
5267 | #[cfg_attr(test, assert_instr(fmls, LANE = 0))] | |
5268 | #[rustc_legacy_const_generics(3)] | |
5269 | pub unsafe fn vfmsq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { | |
5270 | static_assert_imm2!(LANE); | |
5271 | vfmsq_f32(a, b, vdupq_n_f32(simd_extract(c, LANE as u32))) | |
5272 | } | |
5273 | ||
5274 | /// Floating-point fused multiply-subtract to accumulator | |
5275 | #[inline] | |
5276 | #[target_feature(enable = "neon")] | |
5277 | #[cfg_attr(test, assert_instr(fmsub, LANE = 0))] | |
5278 | #[rustc_legacy_const_generics(3)] | |
5279 | pub unsafe fn vfms_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { | |
5280 | static_assert!(LANE : i32 where LANE == 0); | |
5281 | vfms_f64(a, b, vdup_n_f64(simd_extract(c, LANE as u32))) | |
5282 | } | |
5283 | ||
5284 | /// Floating-point fused multiply-subtract to accumulator | |
5285 | #[inline] | |
5286 | #[target_feature(enable = "neon")] | |
5287 | #[cfg_attr(test, assert_instr(fmls, LANE = 0))] | |
5288 | #[rustc_legacy_const_generics(3)] | |
5289 | pub unsafe fn vfms_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t, c: float64x2_t) -> float64x1_t { | |
5290 | static_assert_imm1!(LANE); | |
5291 | vfms_f64(a, b, vdup_n_f64(simd_extract(c, LANE as u32))) | |
5292 | } | |
5293 | ||
5294 | /// Floating-point fused multiply-subtract to accumulator | |
5295 | #[inline] | |
5296 | #[target_feature(enable = "neon")] | |
5297 | #[cfg_attr(test, assert_instr(fmls, LANE = 0))] | |
5298 | #[rustc_legacy_const_generics(3)] | |
5299 | pub unsafe fn vfmsq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t, c: float64x1_t) -> float64x2_t { | |
5300 | static_assert!(LANE : i32 where LANE == 0); | |
5301 | vfmsq_f64(a, b, vdupq_n_f64(simd_extract(c, LANE as u32))) | |
5302 | } | |
5303 | ||
5304 | /// Floating-point fused multiply-subtract to accumulator | |
5305 | #[inline] | |
5306 | #[target_feature(enable = "neon")] | |
5307 | #[cfg_attr(test, assert_instr(fmls, LANE = 0))] | |
5308 | #[rustc_legacy_const_generics(3)] | |
5309 | pub unsafe fn vfmsq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { | |
5310 | static_assert_imm1!(LANE); | |
5311 | vfmsq_f64(a, b, vdupq_n_f64(simd_extract(c, LANE as u32))) | |
5312 | } | |
5313 | ||
5314 | /// Floating-point fused multiply-subtract to accumulator | |
5315 | #[inline] | |
5316 | #[target_feature(enable = "neon")] | |
5317 | #[cfg_attr(test, assert_instr(fmls, LANE = 0))] | |
5318 | #[rustc_legacy_const_generics(3)] | |
5319 | pub unsafe fn vfmss_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 { | |
5320 | vfmas_lane_f32::<LANE>(a, -b, c) | |
5321 | } | |
5322 | ||
5323 | /// Floating-point fused multiply-subtract to accumulator | |
5324 | #[inline] | |
5325 | #[target_feature(enable = "neon")] | |
5326 | #[cfg_attr(test, assert_instr(fmls, LANE = 0))] | |
5327 | #[rustc_legacy_const_generics(3)] | |
5328 | pub unsafe fn vfmss_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 { | |
5329 | vfmas_laneq_f32::<LANE>(a, -b, c) | |
5330 | } | |
5331 | ||
5332 | /// Floating-point fused multiply-subtract to accumulator | |
5333 | #[inline] | |
5334 | #[target_feature(enable = "neon")] | |
5335 | #[cfg_attr(test, assert_instr(fmsub, LANE = 0))] | |
5336 | #[rustc_legacy_const_generics(3)] | |
5337 | pub unsafe fn vfmsd_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) -> f64 { | |
5338 | vfmad_lane_f64::<LANE>(a, -b, c) | |
5339 | } | |
5340 | ||
5341 | /// Floating-point fused multiply-subtract to accumulator | |
5342 | #[inline] | |
5343 | #[target_feature(enable = "neon")] | |
5344 | #[cfg_attr(test, assert_instr(fmls, LANE = 0))] | |
5345 | #[rustc_legacy_const_generics(3)] | |
5346 | pub unsafe fn vfmsd_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 { | |
5347 | vfmad_laneq_f64::<LANE>(a, -b, c) | |
5348 | } | |
5349 | ||
5350 | /// Divide | |
5351 | #[inline] | |
5352 | #[target_feature(enable = "neon")] | |
5353 | #[cfg_attr(test, assert_instr(fdiv))] | |
5354 | pub unsafe fn vdiv_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
5355 | simd_div(a, b) | |
5356 | } | |
5357 | ||
5358 | /// Divide | |
5359 | #[inline] | |
5360 | #[target_feature(enable = "neon")] | |
5361 | #[cfg_attr(test, assert_instr(fdiv))] | |
5362 | pub unsafe fn vdivq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
5363 | simd_div(a, b) | |
5364 | } | |
5365 | ||
5366 | /// Divide | |
5367 | #[inline] | |
5368 | #[target_feature(enable = "neon")] | |
5369 | #[cfg_attr(test, assert_instr(fdiv))] | |
5370 | pub unsafe fn vdiv_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
5371 | simd_div(a, b) | |
5372 | } | |
5373 | ||
5374 | /// Divide | |
5375 | #[inline] | |
5376 | #[target_feature(enable = "neon")] | |
5377 | #[cfg_attr(test, assert_instr(fdiv))] | |
5378 | pub unsafe fn vdivq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
5379 | simd_div(a, b) | |
5380 | } | |
5381 | ||
5382 | /// Subtract | |
5383 | #[inline] | |
5384 | #[target_feature(enable = "neon")] | |
5385 | #[cfg_attr(test, assert_instr(fsub))] | |
5386 | pub unsafe fn vsub_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
5387 | simd_sub(a, b) | |
5388 | } | |
5389 | ||
5390 | /// Subtract | |
5391 | #[inline] | |
5392 | #[target_feature(enable = "neon")] | |
5393 | #[cfg_attr(test, assert_instr(fsub))] | |
5394 | pub unsafe fn vsubq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
5395 | simd_sub(a, b) | |
5396 | } | |
5397 | ||
5398 | /// Signed Add Long across Vector | |
5399 | #[inline] | |
5400 | #[target_feature(enable = "neon")] | |
5401 | #[cfg_attr(test, assert_instr(saddlv))] | |
5402 | pub unsafe fn vaddlv_s16(a: int16x4_t) -> i32 { | |
5403 | #[allow(improper_ctypes)] | |
5404 | extern "C" { | |
5405 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.saddlv.i32.v4i16")] | |
5406 | fn vaddlv_s16_(a: int16x4_t) -> i32; | |
5407 | } | |
5408 | vaddlv_s16_(a) | |
5409 | } | |
5410 | ||
5411 | /// Signed Add Long across Vector | |
5412 | #[inline] | |
5413 | #[target_feature(enable = "neon")] | |
5414 | #[cfg_attr(test, assert_instr(saddlv))] | |
5415 | pub unsafe fn vaddlvq_s16(a: int16x8_t) -> i32 { | |
5416 | #[allow(improper_ctypes)] | |
5417 | extern "C" { | |
5418 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.saddlv.i32.v8i16")] | |
5419 | fn vaddlvq_s16_(a: int16x8_t) -> i32; | |
5420 | } | |
5421 | vaddlvq_s16_(a) | |
5422 | } | |
5423 | ||
5424 | /// Signed Add Long across Vector | |
5425 | #[inline] | |
5426 | #[target_feature(enable = "neon")] | |
5427 | #[cfg_attr(test, assert_instr(saddlp))] | |
5428 | pub unsafe fn vaddlv_s32(a: int32x2_t) -> i64 { | |
5429 | #[allow(improper_ctypes)] | |
5430 | extern "C" { | |
5431 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.saddlv.i64.v2i32")] | |
5432 | fn vaddlv_s32_(a: int32x2_t) -> i64; | |
5433 | } | |
5434 | vaddlv_s32_(a) | |
5435 | } | |
5436 | ||
5437 | /// Signed Add Long across Vector | |
5438 | #[inline] | |
5439 | #[target_feature(enable = "neon")] | |
5440 | #[cfg_attr(test, assert_instr(saddlv))] | |
5441 | pub unsafe fn vaddlvq_s32(a: int32x4_t) -> i64 { | |
5442 | #[allow(improper_ctypes)] | |
5443 | extern "C" { | |
5444 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.saddlv.i64.v4i32")] | |
5445 | fn vaddlvq_s32_(a: int32x4_t) -> i64; | |
5446 | } | |
5447 | vaddlvq_s32_(a) | |
5448 | } | |
5449 | ||
5450 | /// Unsigned Add Long across Vector | |
5451 | #[inline] | |
5452 | #[target_feature(enable = "neon")] | |
5453 | #[cfg_attr(test, assert_instr(uaddlv))] | |
5454 | pub unsafe fn vaddlv_u16(a: uint16x4_t) -> u32 { | |
5455 | #[allow(improper_ctypes)] | |
5456 | extern "C" { | |
5457 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uaddlv.i32.v4i16")] | |
5458 | fn vaddlv_u16_(a: uint16x4_t) -> u32; | |
5459 | } | |
5460 | vaddlv_u16_(a) | |
5461 | } | |
5462 | ||
5463 | /// Unsigned Add Long across Vector | |
5464 | #[inline] | |
5465 | #[target_feature(enable = "neon")] | |
5466 | #[cfg_attr(test, assert_instr(uaddlv))] | |
5467 | pub unsafe fn vaddlvq_u16(a: uint16x8_t) -> u32 { | |
5468 | #[allow(improper_ctypes)] | |
5469 | extern "C" { | |
5470 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uaddlv.i32.v8i16")] | |
5471 | fn vaddlvq_u16_(a: uint16x8_t) -> u32; | |
5472 | } | |
5473 | vaddlvq_u16_(a) | |
5474 | } | |
5475 | ||
5476 | /// Unsigned Add Long across Vector | |
5477 | #[inline] | |
5478 | #[target_feature(enable = "neon")] | |
5479 | #[cfg_attr(test, assert_instr(uaddlp))] | |
5480 | pub unsafe fn vaddlv_u32(a: uint32x2_t) -> u64 { | |
5481 | #[allow(improper_ctypes)] | |
5482 | extern "C" { | |
5483 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uaddlv.i64.v2i32")] | |
5484 | fn vaddlv_u32_(a: uint32x2_t) -> u64; | |
5485 | } | |
5486 | vaddlv_u32_(a) | |
5487 | } | |
5488 | ||
5489 | /// Unsigned Add Long across Vector | |
5490 | #[inline] | |
5491 | #[target_feature(enable = "neon")] | |
5492 | #[cfg_attr(test, assert_instr(uaddlv))] | |
5493 | pub unsafe fn vaddlvq_u32(a: uint32x4_t) -> u64 { | |
5494 | #[allow(improper_ctypes)] | |
5495 | extern "C" { | |
5496 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uaddlv.i64.v4i32")] | |
5497 | fn vaddlvq_u32_(a: uint32x4_t) -> u64; | |
5498 | } | |
5499 | vaddlvq_u32_(a) | |
5500 | } | |
5501 | ||
5502 | /// Signed Subtract Wide | |
5503 | #[inline] | |
5504 | #[target_feature(enable = "neon")] | |
5505 | #[cfg_attr(test, assert_instr(ssubw))] | |
5506 | pub unsafe fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { | |
5507 | let c: int8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
5508 | simd_sub(a, simd_cast(c)) | |
5509 | } | |
5510 | ||
5511 | /// Signed Subtract Wide | |
5512 | #[inline] | |
5513 | #[target_feature(enable = "neon")] | |
5514 | #[cfg_attr(test, assert_instr(ssubw))] | |
5515 | pub unsafe fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { | |
5516 | let c: int16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
5517 | simd_sub(a, simd_cast(c)) | |
5518 | } | |
5519 | ||
5520 | /// Signed Subtract Wide | |
5521 | #[inline] | |
5522 | #[target_feature(enable = "neon")] | |
5523 | #[cfg_attr(test, assert_instr(ssubw))] | |
5524 | pub unsafe fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { | |
5525 | let c: int32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
5526 | simd_sub(a, simd_cast(c)) | |
5527 | } | |
5528 | ||
5529 | /// Unsigned Subtract Wide | |
5530 | #[inline] | |
5531 | #[target_feature(enable = "neon")] | |
5532 | #[cfg_attr(test, assert_instr(usubw))] | |
5533 | pub unsafe fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { | |
5534 | let c: uint8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
5535 | simd_sub(a, simd_cast(c)) | |
5536 | } | |
5537 | ||
5538 | /// Unsigned Subtract Wide | |
5539 | #[inline] | |
5540 | #[target_feature(enable = "neon")] | |
5541 | #[cfg_attr(test, assert_instr(usubw))] | |
5542 | pub unsafe fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { | |
5543 | let c: uint16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
5544 | simd_sub(a, simd_cast(c)) | |
5545 | } | |
5546 | ||
5547 | /// Unsigned Subtract Wide | |
5548 | #[inline] | |
5549 | #[target_feature(enable = "neon")] | |
5550 | #[cfg_attr(test, assert_instr(usubw))] | |
5551 | pub unsafe fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { | |
5552 | let c: uint32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
5553 | simd_sub(a, simd_cast(c)) | |
5554 | } | |
5555 | ||
5556 | /// Signed Subtract Long | |
5557 | #[inline] | |
5558 | #[target_feature(enable = "neon")] | |
5559 | #[cfg_attr(test, assert_instr(ssubl))] | |
5560 | pub unsafe fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { | |
5561 | let c: int8x8_t = simd_shuffle8!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); | |
5562 | let d: int16x8_t = simd_cast(c); | |
5563 | let e: int8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
5564 | let f: int16x8_t = simd_cast(e); | |
5565 | simd_sub(d, f) | |
5566 | } | |
5567 | ||
5568 | /// Signed Subtract Long | |
5569 | #[inline] | |
5570 | #[target_feature(enable = "neon")] | |
5571 | #[cfg_attr(test, assert_instr(ssubl))] | |
5572 | pub unsafe fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { | |
5573 | let c: int16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
5574 | let d: int32x4_t = simd_cast(c); | |
5575 | let e: int16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
5576 | let f: int32x4_t = simd_cast(e); | |
5577 | simd_sub(d, f) | |
5578 | } | |
5579 | ||
5580 | /// Signed Subtract Long | |
5581 | #[inline] | |
5582 | #[target_feature(enable = "neon")] | |
5583 | #[cfg_attr(test, assert_instr(ssubl))] | |
5584 | pub unsafe fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { | |
5585 | let c: int32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
5586 | let d: int64x2_t = simd_cast(c); | |
5587 | let e: int32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
5588 | let f: int64x2_t = simd_cast(e); | |
5589 | simd_sub(d, f) | |
5590 | } | |
5591 | ||
5592 | /// Unsigned Subtract Long | |
5593 | #[inline] | |
5594 | #[target_feature(enable = "neon")] | |
5595 | #[cfg_attr(test, assert_instr(usubl))] | |
5596 | pub unsafe fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { | |
5597 | let c: uint8x8_t = simd_shuffle8!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); | |
5598 | let d: uint16x8_t = simd_cast(c); | |
5599 | let e: uint8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
5600 | let f: uint16x8_t = simd_cast(e); | |
5601 | simd_sub(d, f) | |
5602 | } | |
5603 | ||
5604 | /// Unsigned Subtract Long | |
5605 | #[inline] | |
5606 | #[target_feature(enable = "neon")] | |
5607 | #[cfg_attr(test, assert_instr(usubl))] | |
5608 | pub unsafe fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { | |
5609 | let c: uint16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
5610 | let d: uint32x4_t = simd_cast(c); | |
5611 | let e: uint16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
5612 | let f: uint32x4_t = simd_cast(e); | |
5613 | simd_sub(d, f) | |
5614 | } | |
5615 | ||
5616 | /// Unsigned Subtract Long | |
5617 | #[inline] | |
5618 | #[target_feature(enable = "neon")] | |
5619 | #[cfg_attr(test, assert_instr(usubl))] | |
5620 | pub unsafe fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { | |
5621 | let c: uint32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
5622 | let d: uint64x2_t = simd_cast(c); | |
5623 | let e: uint32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
5624 | let f: uint64x2_t = simd_cast(e); | |
5625 | simd_sub(d, f) | |
5626 | } | |
5627 | ||
5628 | /// Maximum (vector) | |
5629 | #[inline] | |
5630 | #[target_feature(enable = "neon")] | |
5631 | #[cfg_attr(test, assert_instr(fmax))] | |
5632 | pub unsafe fn vmax_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
5633 | #[allow(improper_ctypes)] | |
5634 | extern "C" { | |
5635 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmax.v1f64")] | |
5636 | fn vmax_f64_(a: float64x1_t, b: float64x1_t) -> float64x1_t; | |
5637 | } | |
5638 | vmax_f64_(a, b) | |
5639 | } | |
5640 | ||
5641 | /// Maximum (vector) | |
5642 | #[inline] | |
5643 | #[target_feature(enable = "neon")] | |
5644 | #[cfg_attr(test, assert_instr(fmax))] | |
5645 | pub unsafe fn vmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
5646 | #[allow(improper_ctypes)] | |
5647 | extern "C" { | |
5648 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmax.v2f64")] | |
5649 | fn vmaxq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; | |
5650 | } | |
5651 | vmaxq_f64_(a, b) | |
5652 | } | |
5653 | ||
5654 | /// Floating-point Maximun Number (vector) | |
5655 | #[inline] | |
5656 | #[target_feature(enable = "neon")] | |
5657 | #[cfg_attr(test, assert_instr(fmaxnm))] | |
5658 | pub unsafe fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
5659 | #[allow(improper_ctypes)] | |
5660 | extern "C" { | |
5661 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmaxnm.v1f64")] | |
5662 | fn vmaxnm_f64_(a: float64x1_t, b: float64x1_t) -> float64x1_t; | |
5663 | } | |
5664 | vmaxnm_f64_(a, b) | |
5665 | } | |
5666 | ||
5667 | /// Floating-point Maximun Number (vector) | |
5668 | #[inline] | |
5669 | #[target_feature(enable = "neon")] | |
5670 | #[cfg_attr(test, assert_instr(fmaxnm))] | |
5671 | pub unsafe fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
5672 | #[allow(improper_ctypes)] | |
5673 | extern "C" { | |
5674 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmaxnm.v2f64")] | |
5675 | fn vmaxnmq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; | |
5676 | } | |
5677 | vmaxnmq_f64_(a, b) | |
5678 | } | |
5679 | ||
5680 | /// Floating-point Maximum Number Pairwise (vector). | |
5681 | #[inline] | |
5682 | #[target_feature(enable = "neon")] | |
5683 | #[cfg_attr(test, assert_instr(fmaxnmp))] | |
5684 | pub unsafe fn vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
5685 | #[allow(improper_ctypes)] | |
5686 | extern "C" { | |
5687 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmaxnmp.v2f32")] | |
5688 | fn vpmaxnm_f32_(a: float32x2_t, b: float32x2_t) -> float32x2_t; | |
5689 | } | |
5690 | vpmaxnm_f32_(a, b) | |
5691 | } | |
5692 | ||
5693 | /// Floating-point Maximum Number Pairwise (vector). | |
5694 | #[inline] | |
5695 | #[target_feature(enable = "neon")] | |
5696 | #[cfg_attr(test, assert_instr(fmaxnmp))] | |
5697 | pub unsafe fn vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
5698 | #[allow(improper_ctypes)] | |
5699 | extern "C" { | |
5700 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmaxnmp.v2f64")] | |
5701 | fn vpmaxnmq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; | |
5702 | } | |
5703 | vpmaxnmq_f64_(a, b) | |
5704 | } | |
5705 | ||
5706 | /// Floating-point Maximum Number Pairwise (vector). | |
5707 | #[inline] | |
5708 | #[target_feature(enable = "neon")] | |
5709 | #[cfg_attr(test, assert_instr(fmaxnmp))] | |
5710 | pub unsafe fn vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
5711 | #[allow(improper_ctypes)] | |
5712 | extern "C" { | |
5713 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmaxnmp.v4f32")] | |
5714 | fn vpmaxnmq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t; | |
5715 | } | |
5716 | vpmaxnmq_f32_(a, b) | |
5717 | } | |
5718 | ||
5719 | /// Minimum (vector) | |
5720 | #[inline] | |
5721 | #[target_feature(enable = "neon")] | |
5722 | #[cfg_attr(test, assert_instr(fmin))] | |
5723 | pub unsafe fn vmin_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
5724 | #[allow(improper_ctypes)] | |
5725 | extern "C" { | |
5726 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmin.v1f64")] | |
5727 | fn vmin_f64_(a: float64x1_t, b: float64x1_t) -> float64x1_t; | |
5728 | } | |
5729 | vmin_f64_(a, b) | |
5730 | } | |
5731 | ||
5732 | /// Minimum (vector) | |
5733 | #[inline] | |
5734 | #[target_feature(enable = "neon")] | |
5735 | #[cfg_attr(test, assert_instr(fmin))] | |
5736 | pub unsafe fn vminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
5737 | #[allow(improper_ctypes)] | |
5738 | extern "C" { | |
5739 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmin.v2f64")] | |
5740 | fn vminq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; | |
5741 | } | |
5742 | vminq_f64_(a, b) | |
5743 | } | |
5744 | ||
5745 | /// Floating-point Minimun Number (vector) | |
5746 | #[inline] | |
5747 | #[target_feature(enable = "neon")] | |
5748 | #[cfg_attr(test, assert_instr(fminnm))] | |
5749 | pub unsafe fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
5750 | #[allow(improper_ctypes)] | |
5751 | extern "C" { | |
5752 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fminnm.v1f64")] | |
5753 | fn vminnm_f64_(a: float64x1_t, b: float64x1_t) -> float64x1_t; | |
5754 | } | |
5755 | vminnm_f64_(a, b) | |
5756 | } | |
5757 | ||
5758 | /// Floating-point Minimun Number (vector) | |
5759 | #[inline] | |
5760 | #[target_feature(enable = "neon")] | |
5761 | #[cfg_attr(test, assert_instr(fminnm))] | |
5762 | pub unsafe fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
5763 | #[allow(improper_ctypes)] | |
5764 | extern "C" { | |
5765 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fminnm.v2f64")] | |
5766 | fn vminnmq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; | |
5767 | } | |
5768 | vminnmq_f64_(a, b) | |
5769 | } | |
5770 | ||
5771 | /// Floating-point Minimum Number Pairwise (vector). | |
5772 | #[inline] | |
5773 | #[target_feature(enable = "neon")] | |
5774 | #[cfg_attr(test, assert_instr(fminnmp))] | |
5775 | pub unsafe fn vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
5776 | #[allow(improper_ctypes)] | |
5777 | extern "C" { | |
5778 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fminnmp.v2f32")] | |
5779 | fn vpminnm_f32_(a: float32x2_t, b: float32x2_t) -> float32x2_t; | |
5780 | } | |
5781 | vpminnm_f32_(a, b) | |
5782 | } | |
5783 | ||
5784 | /// Floating-point Minimum Number Pairwise (vector). | |
5785 | #[inline] | |
5786 | #[target_feature(enable = "neon")] | |
5787 | #[cfg_attr(test, assert_instr(fminnmp))] | |
5788 | pub unsafe fn vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
5789 | #[allow(improper_ctypes)] | |
5790 | extern "C" { | |
5791 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fminnmp.v2f64")] | |
5792 | fn vpminnmq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; | |
5793 | } | |
5794 | vpminnmq_f64_(a, b) | |
5795 | } | |
5796 | ||
5797 | /// Floating-point Minimum Number Pairwise (vector). | |
5798 | #[inline] | |
5799 | #[target_feature(enable = "neon")] | |
5800 | #[cfg_attr(test, assert_instr(fminnmp))] | |
5801 | pub unsafe fn vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
5802 | #[allow(improper_ctypes)] | |
5803 | extern "C" { | |
5804 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fminnmp.v4f32")] | |
5805 | fn vpminnmq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t; | |
5806 | } | |
5807 | vpminnmq_f32_(a, b) | |
5808 | } | |
5809 | ||
5810 | /// Signed saturating doubling multiply long | |
5811 | #[inline] | |
5812 | #[target_feature(enable = "neon")] | |
5813 | #[cfg_attr(test, assert_instr(sqdmull))] | |
5814 | pub unsafe fn vqdmullh_s16(a: i16, b: i16) -> i32 { | |
5815 | let a: int16x4_t = vdup_n_s16(a); | |
5816 | let b: int16x4_t = vdup_n_s16(b); | |
5817 | simd_extract(vqdmull_s16(a, b), 0) | |
5818 | } | |
5819 | ||
5820 | /// Signed saturating doubling multiply long | |
5821 | #[inline] | |
5822 | #[target_feature(enable = "neon")] | |
5823 | #[cfg_attr(test, assert_instr(sqdmull))] | |
5824 | pub unsafe fn vqdmulls_s32(a: i32, b: i32) -> i64 { | |
5825 | #[allow(improper_ctypes)] | |
5826 | extern "C" { | |
5827 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqdmulls.scalar")] | |
5828 | fn vqdmulls_s32_(a: i32, b: i32) -> i64; | |
5829 | } | |
5830 | vqdmulls_s32_(a, b) | |
5831 | } | |
5832 | ||
5833 | /// Signed saturating doubling multiply long | |
5834 | #[inline] | |
5835 | #[target_feature(enable = "neon")] | |
5836 | #[cfg_attr(test, assert_instr(sqdmull2))] | |
5837 | pub unsafe fn vqdmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { | |
5838 | let a: int16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
5839 | let b: int16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
5840 | vqdmull_s16(a, b) | |
5841 | } | |
5842 | ||
5843 | /// Signed saturating doubling multiply long | |
5844 | #[inline] | |
5845 | #[target_feature(enable = "neon")] | |
5846 | #[cfg_attr(test, assert_instr(sqdmull2))] | |
5847 | pub unsafe fn vqdmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { | |
5848 | let a: int32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
5849 | let b: int32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
5850 | vqdmull_s32(a, b) | |
5851 | } | |
5852 | ||
5853 | /// Signed saturating doubling multiply long | |
5854 | #[inline] | |
5855 | #[target_feature(enable = "neon")] | |
5856 | #[cfg_attr(test, assert_instr(sqdmull2))] | |
5857 | pub unsafe fn vqdmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t { | |
5858 | let a: int16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
5859 | let b: int16x4_t = vdup_n_s16(b); | |
5860 | vqdmull_s16(a, b) | |
5861 | } | |
5862 | ||
5863 | /// Signed saturating doubling multiply long | |
5864 | #[inline] | |
5865 | #[target_feature(enable = "neon")] | |
5866 | #[cfg_attr(test, assert_instr(sqdmull2))] | |
5867 | pub unsafe fn vqdmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t { | |
5868 | let a: int32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
5869 | let b: int32x2_t = vdup_n_s32(b); | |
5870 | vqdmull_s32(a, b) | |
5871 | } | |
5872 | ||
5873 | /// Vector saturating doubling long multiply by scalar | |
5874 | #[inline] | |
5875 | #[target_feature(enable = "neon")] | |
5876 | #[cfg_attr(test, assert_instr(sqdmull, N = 4))] | |
5877 | #[rustc_legacy_const_generics(2)] | |
5878 | pub unsafe fn vqdmull_laneq_s16<const N: i32>(a: int16x4_t, b: int16x8_t) -> int32x4_t { | |
5879 | static_assert_imm3!(N); | |
5880 | let b: int16x4_t = simd_shuffle4!(b, b, <const N: i32> [N as u32, N as u32, N as u32, N as u32]); | |
5881 | vqdmull_s16(a, b) | |
5882 | } | |
5883 | ||
5884 | /// Vector saturating doubling long multiply by scalar | |
5885 | #[inline] | |
5886 | #[target_feature(enable = "neon")] | |
5887 | #[cfg_attr(test, assert_instr(sqdmull, N = 2))] | |
5888 | #[rustc_legacy_const_generics(2)] | |
5889 | pub unsafe fn vqdmull_laneq_s32<const N: i32>(a: int32x2_t, b: int32x4_t) -> int64x2_t { | |
5890 | static_assert_imm2!(N); | |
5891 | let b: int32x2_t = simd_shuffle2!(b, b, <const N: i32> [N as u32, N as u32]); | |
5892 | vqdmull_s32(a, b) | |
5893 | } | |
5894 | ||
5895 | /// Signed saturating doubling multiply long | |
5896 | #[inline] | |
5897 | #[target_feature(enable = "neon")] | |
5898 | #[cfg_attr(test, assert_instr(sqdmull, N = 2))] | |
5899 | #[rustc_legacy_const_generics(2)] | |
5900 | pub unsafe fn vqdmullh_lane_s16<const N: i32>(a: i16, b: int16x4_t) -> i32 { | |
5901 | static_assert_imm2!(N); | |
5902 | let b: i16 = simd_extract(b, N as u32); | |
5903 | vqdmullh_s16(a, b) | |
5904 | } | |
5905 | ||
5906 | /// Signed saturating doubling multiply long | |
5907 | #[inline] | |
5908 | #[target_feature(enable = "neon")] | |
5909 | #[cfg_attr(test, assert_instr(sqdmull, N = 4))] | |
5910 | #[rustc_legacy_const_generics(2)] | |
5911 | pub unsafe fn vqdmullh_laneq_s16<const N: i32>(a: i16, b: int16x8_t) -> i32 { | |
5912 | static_assert_imm3!(N); | |
5913 | let b: i16 = simd_extract(b, N as u32); | |
5914 | vqdmullh_s16(a, b) | |
5915 | } | |
5916 | ||
5917 | /// Signed saturating doubling multiply long | |
5918 | #[inline] | |
5919 | #[target_feature(enable = "neon")] | |
5920 | #[cfg_attr(test, assert_instr(sqdmull, N = 1))] | |
5921 | #[rustc_legacy_const_generics(2)] | |
5922 | pub unsafe fn vqdmulls_lane_s32<const N: i32>(a: i32, b: int32x2_t) -> i64 { | |
5923 | static_assert_imm1!(N); | |
5924 | let b: i32 = simd_extract(b, N as u32); | |
5925 | vqdmulls_s32(a, b) | |
5926 | } | |
5927 | ||
5928 | /// Signed saturating doubling multiply long | |
5929 | #[inline] | |
5930 | #[target_feature(enable = "neon")] | |
5931 | #[cfg_attr(test, assert_instr(sqdmull, N = 2))] | |
5932 | #[rustc_legacy_const_generics(2)] | |
5933 | pub unsafe fn vqdmulls_laneq_s32<const N: i32>(a: i32, b: int32x4_t) -> i64 { | |
5934 | static_assert_imm2!(N); | |
5935 | let b: i32 = simd_extract(b, N as u32); | |
5936 | vqdmulls_s32(a, b) | |
5937 | } | |
5938 | ||
5939 | /// Signed saturating doubling multiply long | |
5940 | #[inline] | |
5941 | #[target_feature(enable = "neon")] | |
5942 | #[cfg_attr(test, assert_instr(sqdmull2, N = 2))] | |
5943 | #[rustc_legacy_const_generics(2)] | |
5944 | pub unsafe fn vqdmull_high_lane_s16<const N: i32>(a: int16x8_t, b: int16x4_t) -> int32x4_t { | |
5945 | static_assert_imm2!(N); | |
5946 | let a: int16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
5947 | let b: int16x4_t = simd_shuffle4!(b, b, <const N: i32> [N as u32, N as u32, N as u32, N as u32]); | |
5948 | vqdmull_s16(a, b) | |
5949 | } | |
5950 | ||
5951 | /// Signed saturating doubling multiply long | |
5952 | #[inline] | |
5953 | #[target_feature(enable = "neon")] | |
5954 | #[cfg_attr(test, assert_instr(sqdmull2, N = 1))] | |
5955 | #[rustc_legacy_const_generics(2)] | |
5956 | pub unsafe fn vqdmull_high_lane_s32<const N: i32>(a: int32x4_t, b: int32x2_t) -> int64x2_t { | |
5957 | static_assert_imm1!(N); | |
5958 | let a: int32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
5959 | let b: int32x2_t = simd_shuffle2!(b, b, <const N: i32> [N as u32, N as u32]); | |
5960 | vqdmull_s32(a, b) | |
5961 | } | |
5962 | ||
5963 | /// Signed saturating doubling multiply long | |
5964 | #[inline] | |
5965 | #[target_feature(enable = "neon")] | |
5966 | #[cfg_attr(test, assert_instr(sqdmull2, N = 4))] | |
5967 | #[rustc_legacy_const_generics(2)] | |
5968 | pub unsafe fn vqdmull_high_laneq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int32x4_t { | |
5969 | static_assert_imm3!(N); | |
5970 | let a: int16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
5971 | let b: int16x4_t = simd_shuffle4!(b, b, <const N: i32> [N as u32, N as u32, N as u32, N as u32]); | |
5972 | vqdmull_s16(a, b) | |
5973 | } | |
5974 | ||
5975 | /// Signed saturating doubling multiply long | |
5976 | #[inline] | |
5977 | #[target_feature(enable = "neon")] | |
5978 | #[cfg_attr(test, assert_instr(sqdmull2, N = 2))] | |
5979 | #[rustc_legacy_const_generics(2)] | |
5980 | pub unsafe fn vqdmull_high_laneq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int64x2_t { | |
5981 | static_assert_imm2!(N); | |
5982 | let a: int32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
5983 | let b: int32x2_t = simd_shuffle2!(b, b, <const N: i32> [N as u32, N as u32]); | |
5984 | vqdmull_s32(a, b) | |
5985 | } | |
5986 | ||
5987 | /// Signed saturating doubling multiply-add long | |
5988 | #[inline] | |
5989 | #[target_feature(enable = "neon")] | |
5990 | #[cfg_attr(test, assert_instr(sqdmlal2))] | |
5991 | pub unsafe fn vqdmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { | |
5992 | vqaddq_s32(a, vqdmull_high_s16(b, c)) | |
5993 | } | |
5994 | ||
5995 | /// Signed saturating doubling multiply-add long | |
5996 | #[inline] | |
5997 | #[target_feature(enable = "neon")] | |
5998 | #[cfg_attr(test, assert_instr(sqdmlal2))] | |
5999 | pub unsafe fn vqdmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { | |
6000 | vqaddq_s64(a, vqdmull_high_s32(b, c)) | |
6001 | } | |
6002 | ||
6003 | /// Signed saturating doubling multiply-add long | |
6004 | #[inline] | |
6005 | #[target_feature(enable = "neon")] | |
6006 | #[cfg_attr(test, assert_instr(sqdmlal2))] | |
6007 | pub unsafe fn vqdmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { | |
6008 | vqaddq_s32(a, vqdmull_high_n_s16(b, c)) | |
6009 | } | |
6010 | ||
6011 | /// Signed saturating doubling multiply-add long | |
6012 | #[inline] | |
6013 | #[target_feature(enable = "neon")] | |
6014 | #[cfg_attr(test, assert_instr(sqdmlal2))] | |
6015 | pub unsafe fn vqdmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { | |
6016 | vqaddq_s64(a, vqdmull_high_n_s32(b, c)) | |
6017 | } | |
6018 | ||
6019 | /// Vector widening saturating doubling multiply accumulate with scalar | |
6020 | #[inline] | |
6021 | #[target_feature(enable = "neon")] | |
6022 | #[cfg_attr(test, assert_instr(sqdmlal, N = 2))] | |
6023 | #[rustc_legacy_const_generics(3)] | |
6024 | pub unsafe fn vqdmlal_laneq_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { | |
6025 | static_assert_imm3!(N); | |
6026 | vqaddq_s32(a, vqdmull_laneq_s16::<N>(b, c)) | |
6027 | } | |
6028 | ||
6029 | /// Vector widening saturating doubling multiply accumulate with scalar | |
6030 | #[inline] | |
6031 | #[target_feature(enable = "neon")] | |
6032 | #[cfg_attr(test, assert_instr(sqdmlal, N = 1))] | |
6033 | #[rustc_legacy_const_generics(3)] | |
6034 | pub unsafe fn vqdmlal_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { | |
6035 | static_assert_imm2!(N); | |
6036 | vqaddq_s64(a, vqdmull_laneq_s32::<N>(b, c)) | |
6037 | } | |
6038 | ||
6039 | /// Signed saturating doubling multiply-add long | |
6040 | #[inline] | |
6041 | #[target_feature(enable = "neon")] | |
6042 | #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] | |
6043 | #[rustc_legacy_const_generics(3)] | |
6044 | pub unsafe fn vqdmlal_high_lane_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { | |
6045 | static_assert_imm2!(N); | |
6046 | vqaddq_s32(a, vqdmull_high_lane_s16::<N>(b, c)) | |
6047 | } | |
6048 | ||
6049 | /// Signed saturating doubling multiply-add long | |
6050 | #[inline] | |
6051 | #[target_feature(enable = "neon")] | |
6052 | #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] | |
6053 | #[rustc_legacy_const_generics(3)] | |
6054 | pub unsafe fn vqdmlal_high_laneq_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { | |
6055 | static_assert_imm3!(N); | |
6056 | vqaddq_s32(a, vqdmull_high_laneq_s16::<N>(b, c)) | |
6057 | } | |
6058 | ||
6059 | /// Signed saturating doubling multiply-add long | |
6060 | #[inline] | |
6061 | #[target_feature(enable = "neon")] | |
6062 | #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] | |
6063 | #[rustc_legacy_const_generics(3)] | |
6064 | pub unsafe fn vqdmlal_high_lane_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { | |
6065 | static_assert_imm1!(N); | |
6066 | vqaddq_s64(a, vqdmull_high_lane_s32::<N>(b, c)) | |
6067 | } | |
6068 | ||
6069 | /// Signed saturating doubling multiply-add long | |
6070 | #[inline] | |
6071 | #[target_feature(enable = "neon")] | |
6072 | #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] | |
6073 | #[rustc_legacy_const_generics(3)] | |
6074 | pub unsafe fn vqdmlal_high_laneq_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { | |
6075 | static_assert_imm2!(N); | |
6076 | vqaddq_s64(a, vqdmull_high_laneq_s32::<N>(b, c)) | |
6077 | } | |
6078 | ||
6079 | /// Signed saturating doubling multiply-subtract long | |
6080 | #[inline] | |
6081 | #[target_feature(enable = "neon")] | |
6082 | #[cfg_attr(test, assert_instr(sqdmlsl2))] | |
6083 | pub unsafe fn vqdmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { | |
6084 | vqsubq_s32(a, vqdmull_high_s16(b, c)) | |
6085 | } | |
6086 | ||
6087 | /// Signed saturating doubling multiply-subtract long | |
6088 | #[inline] | |
6089 | #[target_feature(enable = "neon")] | |
6090 | #[cfg_attr(test, assert_instr(sqdmlsl2))] | |
6091 | pub unsafe fn vqdmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { | |
6092 | vqsubq_s64(a, vqdmull_high_s32(b, c)) | |
6093 | } | |
6094 | ||
6095 | /// Signed saturating doubling multiply-subtract long | |
6096 | #[inline] | |
6097 | #[target_feature(enable = "neon")] | |
6098 | #[cfg_attr(test, assert_instr(sqdmlsl2))] | |
6099 | pub unsafe fn vqdmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { | |
6100 | vqsubq_s32(a, vqdmull_high_n_s16(b, c)) | |
6101 | } | |
6102 | ||
6103 | /// Signed saturating doubling multiply-subtract long | |
6104 | #[inline] | |
6105 | #[target_feature(enable = "neon")] | |
6106 | #[cfg_attr(test, assert_instr(sqdmlsl2))] | |
6107 | pub unsafe fn vqdmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { | |
6108 | vqsubq_s64(a, vqdmull_high_n_s32(b, c)) | |
6109 | } | |
6110 | ||
6111 | /// Vector widening saturating doubling multiply subtract with scalar | |
6112 | #[inline] | |
6113 | #[target_feature(enable = "neon")] | |
6114 | #[cfg_attr(test, assert_instr(sqdmlsl, N = 2))] | |
6115 | #[rustc_legacy_const_generics(3)] | |
6116 | pub unsafe fn vqdmlsl_laneq_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { | |
6117 | static_assert_imm3!(N); | |
6118 | vqsubq_s32(a, vqdmull_laneq_s16::<N>(b, c)) | |
6119 | } | |
6120 | ||
6121 | /// Vector widening saturating doubling multiply subtract with scalar | |
6122 | #[inline] | |
6123 | #[target_feature(enable = "neon")] | |
6124 | #[cfg_attr(test, assert_instr(sqdmlsl, N = 1))] | |
6125 | #[rustc_legacy_const_generics(3)] | |
6126 | pub unsafe fn vqdmlsl_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { | |
6127 | static_assert_imm2!(N); | |
6128 | vqsubq_s64(a, vqdmull_laneq_s32::<N>(b, c)) | |
6129 | } | |
6130 | ||
6131 | /// Signed saturating doubling multiply-subtract long | |
6132 | #[inline] | |
6133 | #[target_feature(enable = "neon")] | |
6134 | #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] | |
6135 | #[rustc_legacy_const_generics(3)] | |
6136 | pub unsafe fn vqdmlsl_high_lane_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { | |
6137 | static_assert_imm2!(N); | |
6138 | vqsubq_s32(a, vqdmull_high_lane_s16::<N>(b, c)) | |
6139 | } | |
6140 | ||
6141 | /// Signed saturating doubling multiply-subtract long | |
6142 | #[inline] | |
6143 | #[target_feature(enable = "neon")] | |
6144 | #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] | |
6145 | #[rustc_legacy_const_generics(3)] | |
6146 | pub unsafe fn vqdmlsl_high_laneq_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { | |
6147 | static_assert_imm3!(N); | |
6148 | vqsubq_s32(a, vqdmull_high_laneq_s16::<N>(b, c)) | |
6149 | } | |
6150 | ||
6151 | /// Signed saturating doubling multiply-subtract long | |
6152 | #[inline] | |
6153 | #[target_feature(enable = "neon")] | |
6154 | #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] | |
6155 | #[rustc_legacy_const_generics(3)] | |
6156 | pub unsafe fn vqdmlsl_high_lane_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { | |
6157 | static_assert_imm1!(N); | |
6158 | vqsubq_s64(a, vqdmull_high_lane_s32::<N>(b, c)) | |
6159 | } | |
6160 | ||
6161 | /// Signed saturating doubling multiply-subtract long | |
6162 | #[inline] | |
6163 | #[target_feature(enable = "neon")] | |
6164 | #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] | |
6165 | #[rustc_legacy_const_generics(3)] | |
6166 | pub unsafe fn vqdmlsl_high_laneq_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { | |
6167 | static_assert_imm2!(N); | |
6168 | vqsubq_s64(a, vqdmull_high_laneq_s32::<N>(b, c)) | |
6169 | } | |
6170 | ||
6171 | /// Signed saturating doubling multiply returning high half | |
6172 | #[inline] | |
6173 | #[target_feature(enable = "neon")] | |
6174 | #[cfg_attr(test, assert_instr(sqdmulh))] | |
6175 | pub unsafe fn vqdmulhh_s16(a: i16, b: i16) -> i16 { | |
6176 | let a: int16x4_t = vdup_n_s16(a); | |
6177 | let b: int16x4_t = vdup_n_s16(b); | |
6178 | simd_extract(vqdmulh_s16(a, b), 0) | |
6179 | } | |
6180 | ||
6181 | /// Signed saturating doubling multiply returning high half | |
6182 | #[inline] | |
6183 | #[target_feature(enable = "neon")] | |
6184 | #[cfg_attr(test, assert_instr(sqdmulh))] | |
6185 | pub unsafe fn vqdmulhs_s32(a: i32, b: i32) -> i32 { | |
6186 | let a: int32x2_t = vdup_n_s32(a); | |
6187 | let b: int32x2_t = vdup_n_s32(b); | |
6188 | simd_extract(vqdmulh_s32(a, b), 0) | |
6189 | } | |
6190 | ||
6191 | /// Signed saturating doubling multiply returning high half | |
6192 | #[inline] | |
6193 | #[target_feature(enable = "neon")] | |
6194 | #[cfg_attr(test, assert_instr(sqdmulh, N = 2))] | |
6195 | #[rustc_legacy_const_generics(2)] | |
6196 | pub unsafe fn vqdmulhh_lane_s16<const N: i32>(a: i16, b: int16x4_t) -> i16 { | |
6197 | static_assert_imm2!(N); | |
6198 | let b: i16 = simd_extract(b, N as u32); | |
6199 | vqdmulhh_s16(a, b) | |
6200 | } | |
6201 | ||
6202 | /// Signed saturating doubling multiply returning high half | |
6203 | #[inline] | |
6204 | #[target_feature(enable = "neon")] | |
6205 | #[cfg_attr(test, assert_instr(sqdmulh, N = 2))] | |
6206 | #[rustc_legacy_const_generics(2)] | |
6207 | pub unsafe fn vqdmulhh_laneq_s16<const N: i32>(a: i16, b: int16x8_t) -> i16 { | |
6208 | static_assert_imm3!(N); | |
6209 | let b: i16 = simd_extract(b, N as u32); | |
6210 | vqdmulhh_s16(a, b) | |
6211 | } | |
6212 | ||
6213 | /// Signed saturating doubling multiply returning high half | |
6214 | #[inline] | |
6215 | #[target_feature(enable = "neon")] | |
6216 | #[cfg_attr(test, assert_instr(sqdmulh, N = 1))] | |
6217 | #[rustc_legacy_const_generics(2)] | |
6218 | pub unsafe fn vqdmulhs_lane_s32<const N: i32>(a: i32, b: int32x2_t) -> i32 { | |
6219 | static_assert_imm1!(N); | |
6220 | let b: i32 = simd_extract(b, N as u32); | |
6221 | vqdmulhs_s32(a, b) | |
6222 | } | |
6223 | ||
6224 | /// Signed saturating doubling multiply returning high half | |
6225 | #[inline] | |
6226 | #[target_feature(enable = "neon")] | |
6227 | #[cfg_attr(test, assert_instr(sqdmulh, N = 1))] | |
6228 | #[rustc_legacy_const_generics(2)] | |
6229 | pub unsafe fn vqdmulhs_laneq_s32<const N: i32>(a: i32, b: int32x4_t) -> i32 { | |
6230 | static_assert_imm2!(N); | |
6231 | let b: i32 = simd_extract(b, N as u32); | |
6232 | vqdmulhs_s32(a, b) | |
6233 | } | |
6234 | ||
6235 | /// Saturating extract narrow | |
6236 | #[inline] | |
6237 | #[target_feature(enable = "neon")] | |
6238 | #[cfg_attr(test, assert_instr(sqxtn))] | |
6239 | pub unsafe fn vqmovnh_s16(a: i16) -> i8 { | |
6240 | simd_extract(vqmovn_s16(vdupq_n_s16(a)), 0) | |
6241 | } | |
6242 | ||
6243 | /// Saturating extract narrow | |
6244 | #[inline] | |
6245 | #[target_feature(enable = "neon")] | |
6246 | #[cfg_attr(test, assert_instr(sqxtn))] | |
6247 | pub unsafe fn vqmovns_s32(a: i32) -> i16 { | |
6248 | simd_extract(vqmovn_s32(vdupq_n_s32(a)), 0) | |
6249 | } | |
6250 | ||
6251 | /// Saturating extract narrow | |
6252 | #[inline] | |
6253 | #[target_feature(enable = "neon")] | |
6254 | #[cfg_attr(test, assert_instr(uqxtn))] | |
6255 | pub unsafe fn vqmovnh_u16(a: u16) -> u8 { | |
6256 | simd_extract(vqmovn_u16(vdupq_n_u16(a)), 0) | |
6257 | } | |
6258 | ||
6259 | /// Saturating extract narrow | |
6260 | #[inline] | |
6261 | #[target_feature(enable = "neon")] | |
6262 | #[cfg_attr(test, assert_instr(uqxtn))] | |
6263 | pub unsafe fn vqmovns_u32(a: u32) -> u16 { | |
6264 | simd_extract(vqmovn_u32(vdupq_n_u32(a)), 0) | |
6265 | } | |
6266 | ||
6267 | /// Saturating extract narrow | |
6268 | #[inline] | |
6269 | #[target_feature(enable = "neon")] | |
6270 | #[cfg_attr(test, assert_instr(sqxtn))] | |
6271 | pub unsafe fn vqmovnd_s64(a: i64) -> i32 { | |
6272 | #[allow(improper_ctypes)] | |
6273 | extern "C" { | |
6274 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.scalar.sqxtn.i32.i64")] | |
6275 | fn vqmovnd_s64_(a: i64) -> i32; | |
6276 | } | |
6277 | vqmovnd_s64_(a) | |
6278 | } | |
6279 | ||
6280 | /// Saturating extract narrow | |
6281 | #[inline] | |
6282 | #[target_feature(enable = "neon")] | |
6283 | #[cfg_attr(test, assert_instr(uqxtn))] | |
6284 | pub unsafe fn vqmovnd_u64(a: u64) -> u32 { | |
6285 | #[allow(improper_ctypes)] | |
6286 | extern "C" { | |
6287 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.scalar.uqxtn.i32.i64")] | |
6288 | fn vqmovnd_u64_(a: u64) -> u32; | |
6289 | } | |
6290 | vqmovnd_u64_(a) | |
6291 | } | |
6292 | ||
6293 | /// Signed saturating extract narrow | |
6294 | #[inline] | |
6295 | #[target_feature(enable = "neon")] | |
6296 | #[cfg_attr(test, assert_instr(sqxtn2))] | |
6297 | pub unsafe fn vqmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { | |
6298 | simd_shuffle16!(a, vqmovn_s16(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
6299 | } | |
6300 | ||
6301 | /// Signed saturating extract narrow | |
6302 | #[inline] | |
6303 | #[target_feature(enable = "neon")] | |
6304 | #[cfg_attr(test, assert_instr(sqxtn2))] | |
6305 | pub unsafe fn vqmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { | |
6306 | simd_shuffle8!(a, vqmovn_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
6307 | } | |
6308 | ||
6309 | /// Signed saturating extract narrow | |
6310 | #[inline] | |
6311 | #[target_feature(enable = "neon")] | |
6312 | #[cfg_attr(test, assert_instr(sqxtn2))] | |
6313 | pub unsafe fn vqmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { | |
6314 | simd_shuffle4!(a, vqmovn_s64(b), [0, 1, 2, 3]) | |
6315 | } | |
6316 | ||
6317 | /// Signed saturating extract narrow | |
6318 | #[inline] | |
6319 | #[target_feature(enable = "neon")] | |
6320 | #[cfg_attr(test, assert_instr(uqxtn2))] | |
6321 | pub unsafe fn vqmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { | |
6322 | simd_shuffle16!(a, vqmovn_u16(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
6323 | } | |
6324 | ||
6325 | /// Signed saturating extract narrow | |
6326 | #[inline] | |
6327 | #[target_feature(enable = "neon")] | |
6328 | #[cfg_attr(test, assert_instr(uqxtn2))] | |
6329 | pub unsafe fn vqmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { | |
6330 | simd_shuffle8!(a, vqmovn_u32(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
6331 | } | |
6332 | ||
6333 | /// Signed saturating extract narrow | |
6334 | #[inline] | |
6335 | #[target_feature(enable = "neon")] | |
6336 | #[cfg_attr(test, assert_instr(uqxtn2))] | |
6337 | pub unsafe fn vqmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { | |
6338 | simd_shuffle4!(a, vqmovn_u64(b), [0, 1, 2, 3]) | |
6339 | } | |
6340 | ||
6341 | /// Signed saturating extract unsigned narrow | |
6342 | #[inline] | |
6343 | #[target_feature(enable = "neon")] | |
6344 | #[cfg_attr(test, assert_instr(sqxtun))] | |
6345 | pub unsafe fn vqmovunh_s16(a: i16) -> u8 { | |
6346 | simd_extract(vqmovun_s16(vdupq_n_s16(a)), 0) | |
6347 | } | |
6348 | ||
6349 | /// Signed saturating extract unsigned narrow | |
6350 | #[inline] | |
6351 | #[target_feature(enable = "neon")] | |
6352 | #[cfg_attr(test, assert_instr(sqxtun))] | |
6353 | pub unsafe fn vqmovuns_s32(a: i32) -> u16 { | |
6354 | simd_extract(vqmovun_s32(vdupq_n_s32(a)), 0) | |
6355 | } | |
6356 | ||
6357 | /// Signed saturating extract unsigned narrow | |
6358 | #[inline] | |
6359 | #[target_feature(enable = "neon")] | |
6360 | #[cfg_attr(test, assert_instr(sqxtun))] | |
6361 | pub unsafe fn vqmovund_s64(a: i64) -> u32 { | |
6362 | simd_extract(vqmovun_s64(vdupq_n_s64(a)), 0) | |
6363 | } | |
6364 | ||
6365 | /// Signed saturating extract unsigned narrow | |
6366 | #[inline] | |
6367 | #[target_feature(enable = "neon")] | |
6368 | #[cfg_attr(test, assert_instr(sqxtun2))] | |
6369 | pub unsafe fn vqmovun_high_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { | |
6370 | simd_shuffle16!(a, vqmovun_s16(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
6371 | } | |
6372 | ||
6373 | /// Signed saturating extract unsigned narrow | |
6374 | #[inline] | |
6375 | #[target_feature(enable = "neon")] | |
6376 | #[cfg_attr(test, assert_instr(sqxtun2))] | |
6377 | pub unsafe fn vqmovun_high_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { | |
6378 | simd_shuffle8!(a, vqmovun_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
6379 | } | |
6380 | ||
6381 | /// Signed saturating extract unsigned narrow | |
6382 | #[inline] | |
6383 | #[target_feature(enable = "neon")] | |
6384 | #[cfg_attr(test, assert_instr(sqxtun2))] | |
6385 | pub unsafe fn vqmovun_high_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { | |
6386 | simd_shuffle4!(a, vqmovun_s64(b), [0, 1, 2, 3]) | |
6387 | } | |
6388 | ||
6389 | /// Signed saturating rounding doubling multiply returning high half | |
6390 | #[inline] | |
6391 | #[target_feature(enable = "neon")] | |
6392 | #[cfg_attr(test, assert_instr(sqrdmulh))] | |
6393 | pub unsafe fn vqrdmulhh_s16(a: i16, b: i16) -> i16 { | |
6394 | simd_extract(vqrdmulh_s16(vdup_n_s16(a), vdup_n_s16(b)), 0) | |
6395 | } | |
6396 | ||
6397 | /// Signed saturating rounding doubling multiply returning high half | |
6398 | #[inline] | |
6399 | #[target_feature(enable = "neon")] | |
6400 | #[cfg_attr(test, assert_instr(sqrdmulh))] | |
6401 | pub unsafe fn vqrdmulhs_s32(a: i32, b: i32) -> i32 { | |
6402 | simd_extract(vqrdmulh_s32(vdup_n_s32(a), vdup_n_s32(b)), 0) | |
6403 | } | |
6404 | ||
6405 | /// Signed saturating rounding doubling multiply returning high half | |
6406 | #[inline] | |
6407 | #[target_feature(enable = "neon")] | |
6408 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6409 | #[rustc_legacy_const_generics(2)] | |
6410 | pub unsafe fn vqrdmulhh_lane_s16<const LANE: i32>(a: i16, b: int16x4_t) -> i16 { | |
6411 | static_assert_imm2!(LANE); | |
6412 | vqrdmulhh_s16(a, simd_extract(b, LANE as u32)) | |
6413 | } | |
6414 | ||
6415 | /// Signed saturating rounding doubling multiply returning high half | |
6416 | #[inline] | |
6417 | #[target_feature(enable = "neon")] | |
6418 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6419 | #[rustc_legacy_const_generics(2)] | |
6420 | pub unsafe fn vqrdmulhh_laneq_s16<const LANE: i32>(a: i16, b: int16x8_t) -> i16 { | |
6421 | static_assert_imm3!(LANE); | |
6422 | vqrdmulhh_s16(a, simd_extract(b, LANE as u32)) | |
6423 | } | |
6424 | ||
6425 | /// Signed saturating rounding doubling multiply returning high half | |
6426 | #[inline] | |
6427 | #[target_feature(enable = "neon")] | |
6428 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6429 | #[rustc_legacy_const_generics(2)] | |
6430 | pub unsafe fn vqrdmulhs_lane_s32<const LANE: i32>(a: i32, b: int32x2_t) -> i32 { | |
6431 | static_assert_imm1!(LANE); | |
6432 | vqrdmulhs_s32(a, simd_extract(b, LANE as u32)) | |
6433 | } | |
6434 | ||
6435 | /// Signed saturating rounding doubling multiply returning high half | |
6436 | #[inline] | |
6437 | #[target_feature(enable = "neon")] | |
6438 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6439 | #[rustc_legacy_const_generics(2)] | |
6440 | pub unsafe fn vqrdmulhs_laneq_s32<const LANE: i32>(a: i32, b: int32x4_t) -> i32 { | |
6441 | static_assert_imm2!(LANE); | |
6442 | vqrdmulhs_s32(a, simd_extract(b, LANE as u32)) | |
6443 | } | |
6444 | ||
6445 | /// Signed saturating rounding doubling multiply accumulate returning high half | |
6446 | #[inline] | |
6447 | #[target_feature(enable = "neon")] | |
6448 | #[cfg_attr(test, assert_instr(sqrdmulh))] | |
6449 | pub unsafe fn vqrdmlahh_s16(a: i16, b: i16, c: i16) -> i16 { | |
6450 | vqaddh_s16(a, vqrdmulhh_s16(b, c)) | |
6451 | } | |
6452 | ||
6453 | /// Signed saturating rounding doubling multiply accumulate returning high half | |
6454 | #[inline] | |
6455 | #[target_feature(enable = "neon")] | |
6456 | #[cfg_attr(test, assert_instr(sqrdmulh))] | |
6457 | pub unsafe fn vqrdmlahs_s32(a: i32, b: i32, c: i32) -> i32 { | |
6458 | vqadds_s32(a, vqrdmulhs_s32(b, c)) | |
6459 | } | |
6460 | ||
6461 | /// Signed saturating rounding doubling multiply accumulate returning high half | |
6462 | #[inline] | |
6463 | #[target_feature(enable = "neon")] | |
6464 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6465 | #[rustc_legacy_const_generics(3)] | |
6466 | pub unsafe fn vqrdmlahh_lane_s16<const LANE: i32>(a: i16, b: i16, c: int16x4_t) -> i16 { | |
6467 | static_assert_imm2!(LANE); | |
6468 | vqaddh_s16(a, vqrdmulhh_lane_s16::<LANE>(b, c)) | |
6469 | } | |
6470 | ||
6471 | /// Signed saturating rounding doubling multiply accumulate returning high half | |
6472 | #[inline] | |
6473 | #[target_feature(enable = "neon")] | |
6474 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6475 | #[rustc_legacy_const_generics(3)] | |
6476 | pub unsafe fn vqrdmlahh_laneq_s16<const LANE: i32>(a: i16, b: i16, c: int16x8_t) -> i16 { | |
6477 | static_assert_imm3!(LANE); | |
6478 | vqaddh_s16(a, vqrdmulhh_laneq_s16::<LANE>(b, c)) | |
6479 | } | |
6480 | ||
6481 | /// Signed saturating rounding doubling multiply accumulate returning high half | |
6482 | #[inline] | |
6483 | #[target_feature(enable = "neon")] | |
6484 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6485 | #[rustc_legacy_const_generics(3)] | |
6486 | pub unsafe fn vqrdmlahs_lane_s32<const LANE: i32>(a: i32, b: i32, c: int32x2_t) -> i32 { | |
6487 | static_assert_imm1!(LANE); | |
6488 | vqadds_s32(a, vqrdmulhs_lane_s32::<LANE>(b, c)) | |
6489 | } | |
6490 | ||
6491 | /// Signed saturating rounding doubling multiply accumulate returning high half | |
6492 | #[inline] | |
6493 | #[target_feature(enable = "neon")] | |
6494 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6495 | #[rustc_legacy_const_generics(3)] | |
6496 | pub unsafe fn vqrdmlahs_laneq_s32<const LANE: i32>(a: i32, b: i32, c: int32x4_t) -> i32 { | |
6497 | static_assert_imm2!(LANE); | |
6498 | vqadds_s32(a, vqrdmulhs_laneq_s32::<LANE>(b, c)) | |
6499 | } | |
6500 | ||
6501 | /// Signed saturating rounding doubling multiply subtract returning high half | |
6502 | #[inline] | |
6503 | #[target_feature(enable = "neon")] | |
6504 | #[cfg_attr(test, assert_instr(sqrdmulh))] | |
6505 | pub unsafe fn vqrdmlshh_s16(a: i16, b: i16, c: i16) -> i16 { | |
6506 | vqsubh_s16(a, vqrdmulhh_s16(b, c)) | |
6507 | } | |
6508 | ||
6509 | /// Signed saturating rounding doubling multiply subtract returning high half | |
6510 | #[inline] | |
6511 | #[target_feature(enable = "neon")] | |
6512 | #[cfg_attr(test, assert_instr(sqrdmulh))] | |
6513 | pub unsafe fn vqrdmlshs_s32(a: i32, b: i32, c: i32) -> i32 { | |
6514 | vqsubs_s32(a, vqrdmulhs_s32(b, c)) | |
6515 | } | |
6516 | ||
6517 | /// Signed saturating rounding doubling multiply subtract returning high half | |
6518 | #[inline] | |
6519 | #[target_feature(enable = "neon")] | |
6520 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6521 | #[rustc_legacy_const_generics(3)] | |
6522 | pub unsafe fn vqrdmlshh_lane_s16<const LANE: i32>(a: i16, b: i16, c: int16x4_t) -> i16 { | |
6523 | static_assert_imm2!(LANE); | |
6524 | vqsubh_s16(a, vqrdmulhh_lane_s16::<LANE>(b, c)) | |
6525 | } | |
6526 | ||
6527 | /// Signed saturating rounding doubling multiply subtract returning high half | |
6528 | #[inline] | |
6529 | #[target_feature(enable = "neon")] | |
6530 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6531 | #[rustc_legacy_const_generics(3)] | |
6532 | pub unsafe fn vqrdmlshh_laneq_s16<const LANE: i32>(a: i16, b: i16, c: int16x8_t) -> i16 { | |
6533 | static_assert_imm3!(LANE); | |
6534 | vqsubh_s16(a, vqrdmulhh_laneq_s16::<LANE>(b, c)) | |
6535 | } | |
6536 | ||
6537 | /// Signed saturating rounding doubling multiply subtract returning high half | |
6538 | #[inline] | |
6539 | #[target_feature(enable = "neon")] | |
6540 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6541 | #[rustc_legacy_const_generics(3)] | |
6542 | pub unsafe fn vqrdmlshs_lane_s32<const LANE: i32>(a: i32, b: i32, c: int32x2_t) -> i32 { | |
6543 | static_assert_imm1!(LANE); | |
6544 | vqsubs_s32(a, vqrdmulhs_lane_s32::<LANE>(b, c)) | |
6545 | } | |
6546 | ||
6547 | /// Signed saturating rounding doubling multiply subtract returning high half | |
6548 | #[inline] | |
6549 | #[target_feature(enable = "neon")] | |
6550 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6551 | #[rustc_legacy_const_generics(3)] | |
6552 | pub unsafe fn vqrdmlshs_laneq_s32<const LANE: i32>(a: i32, b: i32, c: int32x4_t) -> i32 { | |
6553 | static_assert_imm2!(LANE); | |
6554 | vqsubs_s32(a, vqrdmulhs_laneq_s32::<LANE>(b, c)) | |
6555 | } | |
6556 | ||
6557 | /// Signed saturating rounding shift left | |
6558 | #[inline] | |
6559 | #[target_feature(enable = "neon")] | |
6560 | #[cfg_attr(test, assert_instr(sqrshl))] | |
6561 | pub unsafe fn vqrshls_s32(a: i32, b: i32) -> i32 { | |
6562 | #[allow(improper_ctypes)] | |
6563 | extern "C" { | |
6564 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqrshl.i32")] | |
6565 | fn vqrshls_s32_(a: i32, b: i32) -> i32; | |
6566 | } | |
6567 | vqrshls_s32_(a, b) | |
6568 | } | |
6569 | ||
6570 | /// Signed saturating rounding shift left | |
6571 | #[inline] | |
6572 | #[target_feature(enable = "neon")] | |
6573 | #[cfg_attr(test, assert_instr(sqrshl))] | |
6574 | pub unsafe fn vqrshld_s64(a: i64, b: i64) -> i64 { | |
6575 | #[allow(improper_ctypes)] | |
6576 | extern "C" { | |
6577 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqrshl.i64")] | |
6578 | fn vqrshld_s64_(a: i64, b: i64) -> i64; | |
6579 | } | |
6580 | vqrshld_s64_(a, b) | |
6581 | } | |
6582 | ||
6583 | /// Signed saturating rounding shift left | |
6584 | #[inline] | |
6585 | #[target_feature(enable = "neon")] | |
6586 | #[cfg_attr(test, assert_instr(sqrshl))] | |
6587 | pub unsafe fn vqrshlb_s8(a: i8, b: i8) -> i8 { | |
6588 | let a: int8x8_t = vdup_n_s8(a); | |
6589 | let b: int8x8_t = vdup_n_s8(b); | |
6590 | simd_extract(vqrshl_s8(a, b), 0) | |
6591 | } | |
6592 | ||
6593 | /// Signed saturating rounding shift left | |
6594 | #[inline] | |
6595 | #[target_feature(enable = "neon")] | |
6596 | #[cfg_attr(test, assert_instr(sqrshl))] | |
6597 | pub unsafe fn vqrshlh_s16(a: i16, b: i16) -> i16 { | |
6598 | let a: int16x4_t = vdup_n_s16(a); | |
6599 | let b: int16x4_t = vdup_n_s16(b); | |
6600 | simd_extract(vqrshl_s16(a, b), 0) | |
6601 | } | |
6602 | ||
6603 | /// Unsigned signed saturating rounding shift left | |
6604 | #[inline] | |
6605 | #[target_feature(enable = "neon")] | |
6606 | #[cfg_attr(test, assert_instr(uqrshl))] | |
6607 | pub unsafe fn vqrshls_u32(a: u32, b: i32) -> u32 { | |
6608 | #[allow(improper_ctypes)] | |
6609 | extern "C" { | |
6610 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqrshl.i32")] | |
6611 | fn vqrshls_u32_(a: u32, b: i32) -> u32; | |
6612 | } | |
6613 | vqrshls_u32_(a, b) | |
6614 | } | |
6615 | ||
6616 | /// Unsigned signed saturating rounding shift left | |
6617 | #[inline] | |
6618 | #[target_feature(enable = "neon")] | |
6619 | #[cfg_attr(test, assert_instr(uqrshl))] | |
6620 | pub unsafe fn vqrshld_u64(a: u64, b: i64) -> u64 { | |
6621 | #[allow(improper_ctypes)] | |
6622 | extern "C" { | |
6623 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqrshl.i64")] | |
6624 | fn vqrshld_u64_(a: u64, b: i64) -> u64; | |
6625 | } | |
6626 | vqrshld_u64_(a, b) | |
6627 | } | |
6628 | ||
6629 | /// Unsigned signed saturating rounding shift left | |
6630 | #[inline] | |
6631 | #[target_feature(enable = "neon")] | |
6632 | #[cfg_attr(test, assert_instr(uqrshl))] | |
6633 | pub unsafe fn vqrshlb_u8(a: u8, b: i8) -> u8 { | |
6634 | let a: uint8x8_t = vdup_n_u8(a); | |
6635 | let b: int8x8_t = vdup_n_s8(b); | |
6636 | simd_extract(vqrshl_u8(a, b), 0) | |
6637 | } | |
6638 | ||
6639 | /// Unsigned signed saturating rounding shift left | |
6640 | #[inline] | |
6641 | #[target_feature(enable = "neon")] | |
6642 | #[cfg_attr(test, assert_instr(uqrshl))] | |
6643 | pub unsafe fn vqrshlh_u16(a: u16, b: i16) -> u16 { | |
6644 | let a: uint16x4_t = vdup_n_u16(a); | |
6645 | let b: int16x4_t = vdup_n_s16(b); | |
6646 | simd_extract(vqrshl_u16(a, b), 0) | |
6647 | } | |
6648 | ||
6649 | /// Signed saturating rounded shift right narrow | |
6650 | #[inline] | |
6651 | #[target_feature(enable = "neon")] | |
6652 | #[cfg_attr(test, assert_instr(sqrshrn, N = 2))] | |
6653 | #[rustc_legacy_const_generics(1)] | |
6654 | pub unsafe fn vqrshrnh_n_s16<const N: i32>(a: i16) -> i8 { | |
6655 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
6656 | let a: int16x8_t = vdupq_n_s16(a); | |
6657 | simd_extract(vqrshrn_n_s16::<N>(a), 0) | |
6658 | } | |
6659 | ||
6660 | /// Signed saturating rounded shift right narrow | |
6661 | #[inline] | |
6662 | #[target_feature(enable = "neon")] | |
6663 | #[cfg_attr(test, assert_instr(sqrshrn, N = 2))] | |
6664 | #[rustc_legacy_const_generics(1)] | |
6665 | pub unsafe fn vqrshrns_n_s32<const N: i32>(a: i32) -> i16 { | |
6666 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
6667 | let a: int32x4_t = vdupq_n_s32(a); | |
6668 | simd_extract(vqrshrn_n_s32::<N>(a), 0) | |
6669 | } | |
6670 | ||
6671 | /// Signed saturating rounded shift right narrow | |
6672 | #[inline] | |
6673 | #[target_feature(enable = "neon")] | |
6674 | #[cfg_attr(test, assert_instr(sqrshrn, N = 2))] | |
6675 | #[rustc_legacy_const_generics(1)] | |
6676 | pub unsafe fn vqrshrnd_n_s64<const N: i32>(a: i64) -> i32 { | |
6677 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
6678 | let a: int64x2_t = vdupq_n_s64(a); | |
6679 | simd_extract(vqrshrn_n_s64::<N>(a), 0) | |
6680 | } | |
6681 | ||
6682 | /// Signed saturating rounded shift right narrow | |
6683 | #[inline] | |
6684 | #[target_feature(enable = "neon")] | |
6685 | #[cfg_attr(test, assert_instr(sqrshrn2, N = 2))] | |
6686 | #[rustc_legacy_const_generics(2)] | |
6687 | pub unsafe fn vqrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t { | |
6688 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
6689 | simd_shuffle16!(a, vqrshrn_n_s16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
6690 | } | |
6691 | ||
6692 | /// Signed saturating rounded shift right narrow | |
6693 | #[inline] | |
6694 | #[target_feature(enable = "neon")] | |
6695 | #[cfg_attr(test, assert_instr(sqrshrn2, N = 2))] | |
6696 | #[rustc_legacy_const_generics(2)] | |
6697 | pub unsafe fn vqrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t { | |
6698 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
6699 | simd_shuffle8!(a, vqrshrn_n_s32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
6700 | } | |
6701 | ||
6702 | /// Signed saturating rounded shift right narrow | |
6703 | #[inline] | |
6704 | #[target_feature(enable = "neon")] | |
6705 | #[cfg_attr(test, assert_instr(sqrshrn2, N = 2))] | |
6706 | #[rustc_legacy_const_generics(2)] | |
6707 | pub unsafe fn vqrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t { | |
6708 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
6709 | simd_shuffle4!(a, vqrshrn_n_s64::<N>(b), [0, 1, 2, 3]) | |
6710 | } | |
6711 | ||
6712 | /// Unsigned saturating rounded shift right narrow | |
6713 | #[inline] | |
6714 | #[target_feature(enable = "neon")] | |
6715 | #[cfg_attr(test, assert_instr(uqrshrn, N = 2))] | |
6716 | #[rustc_legacy_const_generics(1)] | |
6717 | pub unsafe fn vqrshrnh_n_u16<const N: i32>(a: u16) -> u8 { | |
6718 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
6719 | let a: uint16x8_t = vdupq_n_u16(a); | |
6720 | simd_extract(vqrshrn_n_u16::<N>(a), 0) | |
6721 | } | |
6722 | ||
6723 | /// Unsigned saturating rounded shift right narrow | |
6724 | #[inline] | |
6725 | #[target_feature(enable = "neon")] | |
6726 | #[cfg_attr(test, assert_instr(uqrshrn, N = 2))] | |
6727 | #[rustc_legacy_const_generics(1)] | |
6728 | pub unsafe fn vqrshrns_n_u32<const N: i32>(a: u32) -> u16 { | |
6729 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
6730 | let a: uint32x4_t = vdupq_n_u32(a); | |
6731 | simd_extract(vqrshrn_n_u32::<N>(a), 0) | |
6732 | } | |
6733 | ||
6734 | /// Unsigned saturating rounded shift right narrow | |
6735 | #[inline] | |
6736 | #[target_feature(enable = "neon")] | |
6737 | #[cfg_attr(test, assert_instr(uqrshrn, N = 2))] | |
6738 | #[rustc_legacy_const_generics(1)] | |
6739 | pub unsafe fn vqrshrnd_n_u64<const N: i32>(a: u64) -> u32 { | |
6740 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
6741 | let a: uint64x2_t = vdupq_n_u64(a); | |
6742 | simd_extract(vqrshrn_n_u64::<N>(a), 0) | |
6743 | } | |
6744 | ||
6745 | /// Unsigned saturating rounded shift right narrow | |
6746 | #[inline] | |
6747 | #[target_feature(enable = "neon")] | |
6748 | #[cfg_attr(test, assert_instr(uqrshrn2, N = 2))] | |
6749 | #[rustc_legacy_const_generics(2)] | |
6750 | pub unsafe fn vqrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { | |
6751 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
6752 | simd_shuffle16!(a, vqrshrn_n_u16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
6753 | } | |
6754 | ||
6755 | /// Unsigned saturating rounded shift right narrow | |
6756 | #[inline] | |
6757 | #[target_feature(enable = "neon")] | |
6758 | #[cfg_attr(test, assert_instr(uqrshrn2, N = 2))] | |
6759 | #[rustc_legacy_const_generics(2)] | |
6760 | pub unsafe fn vqrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { | |
6761 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
6762 | simd_shuffle8!(a, vqrshrn_n_u32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
6763 | } | |
6764 | ||
6765 | /// Unsigned saturating rounded shift right narrow | |
6766 | #[inline] | |
6767 | #[target_feature(enable = "neon")] | |
6768 | #[cfg_attr(test, assert_instr(uqrshrn2, N = 2))] | |
6769 | #[rustc_legacy_const_generics(2)] | |
6770 | pub unsafe fn vqrshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { | |
6771 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
6772 | simd_shuffle4!(a, vqrshrn_n_u64::<N>(b), [0, 1, 2, 3]) | |
6773 | } | |
6774 | ||
6775 | /// Signed saturating rounded shift right unsigned narrow | |
6776 | #[inline] | |
6777 | #[target_feature(enable = "neon")] | |
6778 | #[cfg_attr(test, assert_instr(sqrshrun, N = 2))] | |
6779 | #[rustc_legacy_const_generics(1)] | |
6780 | pub unsafe fn vqrshrunh_n_s16<const N: i32>(a: i16) -> u8 { | |
6781 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
6782 | let a: int16x8_t = vdupq_n_s16(a); | |
6783 | simd_extract(vqrshrun_n_s16::<N>(a), 0) | |
6784 | } | |
6785 | ||
6786 | /// Signed saturating rounded shift right unsigned narrow | |
6787 | #[inline] | |
6788 | #[target_feature(enable = "neon")] | |
6789 | #[cfg_attr(test, assert_instr(sqrshrun, N = 2))] | |
6790 | #[rustc_legacy_const_generics(1)] | |
6791 | pub unsafe fn vqrshruns_n_s32<const N: i32>(a: i32) -> u16 { | |
6792 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
6793 | let a: int32x4_t = vdupq_n_s32(a); | |
6794 | simd_extract(vqrshrun_n_s32::<N>(a), 0) | |
6795 | } | |
6796 | ||
6797 | /// Signed saturating rounded shift right unsigned narrow | |
6798 | #[inline] | |
6799 | #[target_feature(enable = "neon")] | |
6800 | #[cfg_attr(test, assert_instr(sqrshrun, N = 2))] | |
6801 | #[rustc_legacy_const_generics(1)] | |
6802 | pub unsafe fn vqrshrund_n_s64<const N: i32>(a: i64) -> u32 { | |
6803 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
6804 | let a: int64x2_t = vdupq_n_s64(a); | |
6805 | simd_extract(vqrshrun_n_s64::<N>(a), 0) | |
6806 | } | |
6807 | ||
6808 | /// Signed saturating rounded shift right unsigned narrow | |
6809 | #[inline] | |
6810 | #[target_feature(enable = "neon")] | |
6811 | #[cfg_attr(test, assert_instr(sqrshrun2, N = 2))] | |
6812 | #[rustc_legacy_const_generics(2)] | |
6813 | pub unsafe fn vqrshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { | |
6814 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
6815 | simd_shuffle16!(a, vqrshrun_n_s16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
6816 | } | |
6817 | ||
6818 | /// Signed saturating rounded shift right unsigned narrow | |
6819 | #[inline] | |
6820 | #[target_feature(enable = "neon")] | |
6821 | #[cfg_attr(test, assert_instr(sqrshrun2, N = 2))] | |
6822 | #[rustc_legacy_const_generics(2)] | |
6823 | pub unsafe fn vqrshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { | |
6824 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
6825 | simd_shuffle8!(a, vqrshrun_n_s32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
6826 | } | |
6827 | ||
6828 | /// Signed saturating rounded shift right unsigned narrow | |
6829 | #[inline] | |
6830 | #[target_feature(enable = "neon")] | |
6831 | #[cfg_attr(test, assert_instr(sqrshrun2, N = 2))] | |
6832 | #[rustc_legacy_const_generics(2)] | |
6833 | pub unsafe fn vqrshrun_high_n_s64<const N: i32>(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { | |
6834 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
6835 | simd_shuffle4!(a, vqrshrun_n_s64::<N>(b), [0, 1, 2, 3]) | |
6836 | } | |
6837 | ||
6838 | /// Signed saturating shift left | |
6839 | #[inline] | |
6840 | #[target_feature(enable = "neon")] | |
6841 | #[cfg_attr(test, assert_instr(sqshl))] | |
6842 | pub unsafe fn vqshld_s64(a: i64, b: i64) -> i64 { | |
6843 | #[allow(improper_ctypes)] | |
6844 | extern "C" { | |
6845 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqshl.i64")] | |
6846 | fn vqshld_s64_(a: i64, b: i64) -> i64; | |
6847 | } | |
6848 | vqshld_s64_(a, b) | |
6849 | } | |
6850 | ||
6851 | /// Signed saturating shift left | |
6852 | #[inline] | |
6853 | #[target_feature(enable = "neon")] | |
6854 | #[cfg_attr(test, assert_instr(sqshl))] | |
6855 | pub unsafe fn vqshlb_s8(a: i8, b: i8) -> i8 { | |
6856 | let c: int8x8_t = vqshl_s8(vdup_n_s8(a), vdup_n_s8(b)); | |
6857 | simd_extract(c, 0) | |
6858 | } | |
6859 | ||
6860 | /// Signed saturating shift left | |
6861 | #[inline] | |
6862 | #[target_feature(enable = "neon")] | |
6863 | #[cfg_attr(test, assert_instr(sqshl))] | |
6864 | pub unsafe fn vqshlh_s16(a: i16, b: i16) -> i16 { | |
6865 | let c: int16x4_t = vqshl_s16(vdup_n_s16(a), vdup_n_s16(b)); | |
6866 | simd_extract(c, 0) | |
6867 | } | |
6868 | ||
6869 | /// Signed saturating shift left | |
6870 | #[inline] | |
6871 | #[target_feature(enable = "neon")] | |
6872 | #[cfg_attr(test, assert_instr(sqshl))] | |
6873 | pub unsafe fn vqshls_s32(a: i32, b: i32) -> i32 { | |
6874 | let c: int32x2_t = vqshl_s32(vdup_n_s32(a), vdup_n_s32(b)); | |
6875 | simd_extract(c, 0) | |
6876 | } | |
6877 | ||
6878 | /// Unsigned saturating shift left | |
6879 | #[inline] | |
6880 | #[target_feature(enable = "neon")] | |
6881 | #[cfg_attr(test, assert_instr(uqshl))] | |
6882 | pub unsafe fn vqshld_u64(a: u64, b: i64) -> u64 { | |
6883 | #[allow(improper_ctypes)] | |
6884 | extern "C" { | |
6885 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqshl.i64")] | |
6886 | fn vqshld_u64_(a: u64, b: i64) -> u64; | |
6887 | } | |
6888 | vqshld_u64_(a, b) | |
6889 | } | |
6890 | ||
6891 | /// Unsigned saturating shift left | |
6892 | #[inline] | |
6893 | #[target_feature(enable = "neon")] | |
6894 | #[cfg_attr(test, assert_instr(uqshl))] | |
6895 | pub unsafe fn vqshlb_u8(a: u8, b: i8) -> u8 { | |
6896 | let c: uint8x8_t = vqshl_u8(vdup_n_u8(a), vdup_n_s8(b)); | |
6897 | simd_extract(c, 0) | |
6898 | } | |
6899 | ||
6900 | /// Unsigned saturating shift left | |
6901 | #[inline] | |
6902 | #[target_feature(enable = "neon")] | |
6903 | #[cfg_attr(test, assert_instr(uqshl))] | |
6904 | pub unsafe fn vqshlh_u16(a: u16, b: i16) -> u16 { | |
6905 | let c: uint16x4_t = vqshl_u16(vdup_n_u16(a), vdup_n_s16(b)); | |
6906 | simd_extract(c, 0) | |
6907 | } | |
6908 | ||
6909 | /// Unsigned saturating shift left | |
6910 | #[inline] | |
6911 | #[target_feature(enable = "neon")] | |
6912 | #[cfg_attr(test, assert_instr(uqshl))] | |
6913 | pub unsafe fn vqshls_u32(a: u32, b: i32) -> u32 { | |
6914 | let c: uint32x2_t = vqshl_u32(vdup_n_u32(a), vdup_n_s32(b)); | |
6915 | simd_extract(c, 0) | |
6916 | } | |
6917 | ||
6918 | /// Signed saturating shift left | |
6919 | #[inline] | |
6920 | #[target_feature(enable = "neon")] | |
6921 | #[cfg_attr(test, assert_instr(sqshl, N = 2))] | |
6922 | #[rustc_legacy_const_generics(1)] | |
6923 | pub unsafe fn vqshlb_n_s8<const N: i32>(a: i8) -> i8 { | |
6924 | static_assert_imm3!(N); | |
6925 | simd_extract(vqshl_n_s8::<N>(vdup_n_s8(a)), 0) | |
6926 | } | |
6927 | ||
6928 | /// Signed saturating shift left | |
6929 | #[inline] | |
6930 | #[target_feature(enable = "neon")] | |
6931 | #[cfg_attr(test, assert_instr(sqshl, N = 2))] | |
6932 | #[rustc_legacy_const_generics(1)] | |
6933 | pub unsafe fn vqshlh_n_s16<const N: i32>(a: i16) -> i16 { | |
6934 | static_assert_imm4!(N); | |
6935 | simd_extract(vqshl_n_s16::<N>(vdup_n_s16(a)), 0) | |
6936 | } | |
6937 | ||
6938 | /// Signed saturating shift left | |
6939 | #[inline] | |
6940 | #[target_feature(enable = "neon")] | |
6941 | #[cfg_attr(test, assert_instr(sqshl, N = 2))] | |
6942 | #[rustc_legacy_const_generics(1)] | |
6943 | pub unsafe fn vqshls_n_s32<const N: i32>(a: i32) -> i32 { | |
6944 | static_assert_imm5!(N); | |
6945 | simd_extract(vqshl_n_s32::<N>(vdup_n_s32(a)), 0) | |
6946 | } | |
6947 | ||
6948 | /// Signed saturating shift left | |
6949 | #[inline] | |
6950 | #[target_feature(enable = "neon")] | |
6951 | #[cfg_attr(test, assert_instr(sqshl, N = 2))] | |
6952 | #[rustc_legacy_const_generics(1)] | |
6953 | pub unsafe fn vqshld_n_s64<const N: i32>(a: i64) -> i64 { | |
6954 | static_assert_imm6!(N); | |
6955 | simd_extract(vqshl_n_s64::<N>(vdup_n_s64(a)), 0) | |
6956 | } | |
6957 | ||
6958 | /// Unsigned saturating shift left | |
6959 | #[inline] | |
6960 | #[target_feature(enable = "neon")] | |
6961 | #[cfg_attr(test, assert_instr(uqshl, N = 2))] | |
6962 | #[rustc_legacy_const_generics(1)] | |
6963 | pub unsafe fn vqshlb_n_u8<const N: i32>(a: u8) -> u8 { | |
6964 | static_assert_imm3!(N); | |
6965 | simd_extract(vqshl_n_u8::<N>(vdup_n_u8(a)), 0) | |
6966 | } | |
6967 | ||
6968 | /// Unsigned saturating shift left | |
6969 | #[inline] | |
6970 | #[target_feature(enable = "neon")] | |
6971 | #[cfg_attr(test, assert_instr(uqshl, N = 2))] | |
6972 | #[rustc_legacy_const_generics(1)] | |
6973 | pub unsafe fn vqshlh_n_u16<const N: i32>(a: u16) -> u16 { | |
6974 | static_assert_imm4!(N); | |
6975 | simd_extract(vqshl_n_u16::<N>(vdup_n_u16(a)), 0) | |
6976 | } | |
6977 | ||
6978 | /// Unsigned saturating shift left | |
6979 | #[inline] | |
6980 | #[target_feature(enable = "neon")] | |
6981 | #[cfg_attr(test, assert_instr(uqshl, N = 2))] | |
6982 | #[rustc_legacy_const_generics(1)] | |
6983 | pub unsafe fn vqshls_n_u32<const N: i32>(a: u32) -> u32 { | |
6984 | static_assert_imm5!(N); | |
6985 | simd_extract(vqshl_n_u32::<N>(vdup_n_u32(a)), 0) | |
6986 | } | |
6987 | ||
6988 | /// Unsigned saturating shift left | |
6989 | #[inline] | |
6990 | #[target_feature(enable = "neon")] | |
6991 | #[cfg_attr(test, assert_instr(uqshl, N = 2))] | |
6992 | #[rustc_legacy_const_generics(1)] | |
6993 | pub unsafe fn vqshld_n_u64<const N: i32>(a: u64) -> u64 { | |
6994 | static_assert_imm6!(N); | |
6995 | simd_extract(vqshl_n_u64::<N>(vdup_n_u64(a)), 0) | |
6996 | } | |
6997 | ||
6998 | /// Signed saturating shift right narrow | |
6999 | #[inline] | |
7000 | #[target_feature(enable = "neon")] | |
7001 | #[cfg_attr(test, assert_instr(sqshrn, N = 2))] | |
7002 | #[rustc_legacy_const_generics(1)] | |
7003 | pub unsafe fn vqshrnd_n_s64<const N: i32>(a: i64) -> i32 { | |
7004 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
7005 | #[allow(improper_ctypes)] | |
7006 | extern "C" { | |
7007 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqshrn.i32")] | |
7008 | fn vqshrnd_n_s64_(a: i64, n: i32) -> i32; | |
7009 | } | |
7010 | vqshrnd_n_s64_(a, N) | |
7011 | } | |
7012 | ||
7013 | /// Signed saturating shift right narrow | |
7014 | #[inline] | |
7015 | #[target_feature(enable = "neon")] | |
7016 | #[cfg_attr(test, assert_instr(sqshrn, N = 2))] | |
7017 | #[rustc_legacy_const_generics(1)] | |
7018 | pub unsafe fn vqshrnh_n_s16<const N: i32>(a: i16) -> i8 { | |
7019 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
7020 | simd_extract(vqshrn_n_s16::<N>(vdupq_n_s16(a)), 0) | |
7021 | } | |
7022 | ||
7023 | /// Signed saturating shift right narrow | |
7024 | #[inline] | |
7025 | #[target_feature(enable = "neon")] | |
7026 | #[cfg_attr(test, assert_instr(sqshrn, N = 2))] | |
7027 | #[rustc_legacy_const_generics(1)] | |
7028 | pub unsafe fn vqshrns_n_s32<const N: i32>(a: i32) -> i16 { | |
7029 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
7030 | simd_extract(vqshrn_n_s32::<N>(vdupq_n_s32(a)), 0) | |
7031 | } | |
7032 | ||
7033 | /// Signed saturating shift right narrow | |
7034 | #[inline] | |
7035 | #[target_feature(enable = "neon")] | |
7036 | #[cfg_attr(test, assert_instr(sqshrn2, N = 2))] | |
7037 | #[rustc_legacy_const_generics(2)] | |
7038 | pub unsafe fn vqshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t { | |
7039 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
7040 | simd_shuffle16!(a, vqshrn_n_s16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
7041 | } | |
7042 | ||
7043 | /// Signed saturating shift right narrow | |
7044 | #[inline] | |
7045 | #[target_feature(enable = "neon")] | |
7046 | #[cfg_attr(test, assert_instr(sqshrn2, N = 2))] | |
7047 | #[rustc_legacy_const_generics(2)] | |
7048 | pub unsafe fn vqshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t { | |
7049 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
7050 | simd_shuffle8!(a, vqshrn_n_s32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
7051 | } | |
7052 | ||
7053 | /// Signed saturating shift right narrow | |
7054 | #[inline] | |
7055 | #[target_feature(enable = "neon")] | |
7056 | #[cfg_attr(test, assert_instr(sqshrn2, N = 2))] | |
7057 | #[rustc_legacy_const_generics(2)] | |
7058 | pub unsafe fn vqshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t { | |
7059 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
7060 | simd_shuffle4!(a, vqshrn_n_s64::<N>(b), [0, 1, 2, 3]) | |
7061 | } | |
7062 | ||
7063 | /// Unsigned saturating shift right narrow | |
7064 | #[inline] | |
7065 | #[target_feature(enable = "neon")] | |
7066 | #[cfg_attr(test, assert_instr(uqshrn, N = 2))] | |
7067 | #[rustc_legacy_const_generics(1)] | |
7068 | pub unsafe fn vqshrnd_n_u64<const N: i32>(a: u64) -> u32 { | |
7069 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
7070 | #[allow(improper_ctypes)] | |
7071 | extern "C" { | |
7072 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqshrn.i32")] | |
7073 | fn vqshrnd_n_u64_(a: u64, n: i32) -> u32; | |
7074 | } | |
7075 | vqshrnd_n_u64_(a, N) | |
7076 | } | |
7077 | ||
7078 | /// Unsigned saturating shift right narrow | |
7079 | #[inline] | |
7080 | #[target_feature(enable = "neon")] | |
7081 | #[cfg_attr(test, assert_instr(uqshrn, N = 2))] | |
7082 | #[rustc_legacy_const_generics(1)] | |
7083 | pub unsafe fn vqshrnh_n_u16<const N: i32>(a: u16) -> u8 { | |
7084 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
7085 | simd_extract(vqshrn_n_u16::<N>(vdupq_n_u16(a)), 0) | |
7086 | } | |
7087 | ||
7088 | /// Unsigned saturating shift right narrow | |
7089 | #[inline] | |
7090 | #[target_feature(enable = "neon")] | |
7091 | #[cfg_attr(test, assert_instr(uqshrn, N = 2))] | |
7092 | #[rustc_legacy_const_generics(1)] | |
7093 | pub unsafe fn vqshrns_n_u32<const N: i32>(a: u32) -> u16 { | |
7094 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
7095 | simd_extract(vqshrn_n_u32::<N>(vdupq_n_u32(a)), 0) | |
7096 | } | |
7097 | ||
7098 | /// Unsigned saturating shift right narrow | |
7099 | #[inline] | |
7100 | #[target_feature(enable = "neon")] | |
7101 | #[cfg_attr(test, assert_instr(uqshrn2, N = 2))] | |
7102 | #[rustc_legacy_const_generics(2)] | |
7103 | pub unsafe fn vqshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { | |
7104 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
7105 | simd_shuffle16!(a, vqshrn_n_u16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
7106 | } | |
7107 | ||
7108 | /// Unsigned saturating shift right narrow | |
7109 | #[inline] | |
7110 | #[target_feature(enable = "neon")] | |
7111 | #[cfg_attr(test, assert_instr(uqshrn2, N = 2))] | |
7112 | #[rustc_legacy_const_generics(2)] | |
7113 | pub unsafe fn vqshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { | |
7114 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
7115 | simd_shuffle8!(a, vqshrn_n_u32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
7116 | } | |
7117 | ||
7118 | /// Unsigned saturating shift right narrow | |
7119 | #[inline] | |
7120 | #[target_feature(enable = "neon")] | |
7121 | #[cfg_attr(test, assert_instr(uqshrn2, N = 2))] | |
7122 | #[rustc_legacy_const_generics(2)] | |
7123 | pub unsafe fn vqshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { | |
7124 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
7125 | simd_shuffle4!(a, vqshrn_n_u64::<N>(b), [0, 1, 2, 3]) | |
7126 | } | |
7127 | ||
7128 | /// Signed saturating shift right unsigned narrow | |
7129 | #[inline] | |
7130 | #[target_feature(enable = "neon")] | |
7131 | #[cfg_attr(test, assert_instr(sqshrun, N = 2))] | |
7132 | #[rustc_legacy_const_generics(1)] | |
7133 | pub unsafe fn vqshrunh_n_s16<const N: i32>(a: i16) -> u8 { | |
7134 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
7135 | simd_extract(vqshrun_n_s16::<N>(vdupq_n_s16(a)), 0) | |
7136 | } | |
7137 | ||
7138 | /// Signed saturating shift right unsigned narrow | |
7139 | #[inline] | |
7140 | #[target_feature(enable = "neon")] | |
7141 | #[cfg_attr(test, assert_instr(sqshrun, N = 2))] | |
7142 | #[rustc_legacy_const_generics(1)] | |
7143 | pub unsafe fn vqshruns_n_s32<const N: i32>(a: i32) -> u16 { | |
7144 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
7145 | simd_extract(vqshrun_n_s32::<N>(vdupq_n_s32(a)), 0) | |
7146 | } | |
7147 | ||
7148 | /// Signed saturating shift right unsigned narrow | |
7149 | #[inline] | |
7150 | #[target_feature(enable = "neon")] | |
7151 | #[cfg_attr(test, assert_instr(sqshrun, N = 2))] | |
7152 | #[rustc_legacy_const_generics(1)] | |
7153 | pub unsafe fn vqshrund_n_s64<const N: i32>(a: i64) -> u32 { | |
7154 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
7155 | simd_extract(vqshrun_n_s64::<N>(vdupq_n_s64(a)), 0) | |
7156 | } | |
7157 | ||
7158 | /// Signed saturating shift right unsigned narrow | |
7159 | #[inline] | |
7160 | #[target_feature(enable = "neon")] | |
7161 | #[cfg_attr(test, assert_instr(sqshrun2, N = 2))] | |
7162 | #[rustc_legacy_const_generics(2)] | |
7163 | pub unsafe fn vqshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { | |
7164 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
7165 | simd_shuffle16!(a, vqshrun_n_s16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
7166 | } | |
7167 | ||
7168 | /// Signed saturating shift right unsigned narrow | |
7169 | #[inline] | |
7170 | #[target_feature(enable = "neon")] | |
7171 | #[cfg_attr(test, assert_instr(sqshrun2, N = 2))] | |
7172 | #[rustc_legacy_const_generics(2)] | |
7173 | pub unsafe fn vqshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { | |
7174 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
7175 | simd_shuffle8!(a, vqshrun_n_s32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
7176 | } | |
7177 | ||
7178 | /// Signed saturating shift right unsigned narrow | |
7179 | #[inline] | |
7180 | #[target_feature(enable = "neon")] | |
7181 | #[cfg_attr(test, assert_instr(sqshrun2, N = 2))] | |
7182 | #[rustc_legacy_const_generics(2)] | |
7183 | pub unsafe fn vqshrun_high_n_s64<const N: i32>(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { | |
7184 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
7185 | simd_shuffle4!(a, vqshrun_n_s64::<N>(b), [0, 1, 2, 3]) | |
7186 | } | |
7187 | ||
7188 | /// Calculates the square root of each lane. | |
7189 | #[inline] | |
7190 | #[target_feature(enable = "neon")] | |
7191 | #[cfg_attr(test, assert_instr(fsqrt))] | |
7192 | pub unsafe fn vsqrt_f32(a: float32x2_t) -> float32x2_t { | |
7193 | simd_fsqrt(a) | |
7194 | } | |
7195 | ||
7196 | /// Calculates the square root of each lane. | |
7197 | #[inline] | |
7198 | #[target_feature(enable = "neon")] | |
7199 | #[cfg_attr(test, assert_instr(fsqrt))] | |
7200 | pub unsafe fn vsqrtq_f32(a: float32x4_t) -> float32x4_t { | |
7201 | simd_fsqrt(a) | |
7202 | } | |
7203 | ||
7204 | /// Calculates the square root of each lane. | |
7205 | #[inline] | |
7206 | #[target_feature(enable = "neon")] | |
7207 | #[cfg_attr(test, assert_instr(fsqrt))] | |
7208 | pub unsafe fn vsqrt_f64(a: float64x1_t) -> float64x1_t { | |
7209 | simd_fsqrt(a) | |
7210 | } | |
7211 | ||
7212 | /// Calculates the square root of each lane. | |
7213 | #[inline] | |
7214 | #[target_feature(enable = "neon")] | |
7215 | #[cfg_attr(test, assert_instr(fsqrt))] | |
7216 | pub unsafe fn vsqrtq_f64(a: float64x2_t) -> float64x2_t { | |
7217 | simd_fsqrt(a) | |
7218 | } | |
7219 | ||
7220 | /// Reciprocal square-root estimate. | |
7221 | #[inline] | |
7222 | #[target_feature(enable = "neon")] | |
7223 | #[cfg_attr(test, assert_instr(frsqrte))] | |
7224 | pub unsafe fn vrsqrte_f64(a: float64x1_t) -> float64x1_t { | |
7225 | #[allow(improper_ctypes)] | |
7226 | extern "C" { | |
7227 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.frsqrte.v1f64")] | |
7228 | fn vrsqrte_f64_(a: float64x1_t) -> float64x1_t; | |
7229 | } | |
7230 | vrsqrte_f64_(a) | |
7231 | } | |
7232 | ||
7233 | /// Reciprocal square-root estimate. | |
7234 | #[inline] | |
7235 | #[target_feature(enable = "neon")] | |
7236 | #[cfg_attr(test, assert_instr(frsqrte))] | |
7237 | pub unsafe fn vrsqrteq_f64(a: float64x2_t) -> float64x2_t { | |
7238 | #[allow(improper_ctypes)] | |
7239 | extern "C" { | |
7240 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.frsqrte.v2f64")] | |
7241 | fn vrsqrteq_f64_(a: float64x2_t) -> float64x2_t; | |
7242 | } | |
7243 | vrsqrteq_f64_(a) | |
7244 | } | |
7245 | ||
7246 | /// Reciprocal estimate. | |
7247 | #[inline] | |
7248 | #[target_feature(enable = "neon")] | |
7249 | #[cfg_attr(test, assert_instr(frecpe))] | |
7250 | pub unsafe fn vrecpe_f64(a: float64x1_t) -> float64x1_t { | |
7251 | #[allow(improper_ctypes)] | |
7252 | extern "C" { | |
7253 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.frecpe.v1f64")] | |
7254 | fn vrecpe_f64_(a: float64x1_t) -> float64x1_t; | |
7255 | } | |
7256 | vrecpe_f64_(a) | |
7257 | } | |
7258 | ||
7259 | /// Reciprocal estimate. | |
7260 | #[inline] | |
7261 | #[target_feature(enable = "neon")] | |
7262 | #[cfg_attr(test, assert_instr(frecpe))] | |
7263 | pub unsafe fn vrecpeq_f64(a: float64x2_t) -> float64x2_t { | |
7264 | #[allow(improper_ctypes)] | |
7265 | extern "C" { | |
7266 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.frecpe.v2f64")] | |
7267 | fn vrecpeq_f64_(a: float64x2_t) -> float64x2_t; | |
7268 | } | |
7269 | vrecpeq_f64_(a) | |
7270 | } | |
7271 | ||
7272 | /// Vector reinterpret cast operation | |
7273 | #[inline] | |
7274 | #[target_feature(enable = "neon")] | |
7275 | #[cfg_attr(test, assert_instr(str))] | |
7276 | pub unsafe fn vreinterpret_s64_p64(a: poly64x1_t) -> int64x1_t { | |
7277 | transmute(a) | |
7278 | } | |
7279 | ||
7280 | /// Vector reinterpret cast operation | |
7281 | #[inline] | |
7282 | #[target_feature(enable = "neon")] | |
7283 | #[cfg_attr(test, assert_instr(str))] | |
7284 | pub unsafe fn vreinterpret_u64_p64(a: poly64x1_t) -> uint64x1_t { | |
7285 | transmute(a) | |
7286 | } | |
7287 | ||
7288 | /// Vector reinterpret cast operation | |
7289 | #[inline] | |
7290 | #[target_feature(enable = "neon")] | |
7291 | #[cfg_attr(test, assert_instr(str))] | |
7292 | pub unsafe fn vreinterpret_p64_s64(a: int64x1_t) -> poly64x1_t { | |
7293 | transmute(a) | |
7294 | } | |
7295 | ||
7296 | /// Vector reinterpret cast operation | |
7297 | #[inline] | |
7298 | #[target_feature(enable = "neon")] | |
7299 | #[cfg_attr(test, assert_instr(str))] | |
7300 | pub unsafe fn vreinterpret_p64_u64(a: uint64x1_t) -> poly64x1_t { | |
7301 | transmute(a) | |
7302 | } | |
7303 | ||
7304 | /// Vector reinterpret cast operation | |
7305 | #[inline] | |
7306 | #[target_feature(enable = "neon")] | |
7307 | #[cfg_attr(test, assert_instr(str))] | |
7308 | pub unsafe fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t { | |
7309 | transmute(a) | |
7310 | } | |
7311 | ||
7312 | /// Vector reinterpret cast operation | |
7313 | #[inline] | |
7314 | #[target_feature(enable = "neon")] | |
7315 | #[cfg_attr(test, assert_instr(str))] | |
7316 | pub unsafe fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t { | |
7317 | transmute(a) | |
7318 | } | |
7319 | ||
7320 | /// Vector reinterpret cast operation | |
7321 | #[inline] | |
7322 | #[target_feature(enable = "neon")] | |
7323 | #[cfg_attr(test, assert_instr(str))] | |
7324 | pub unsafe fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t { | |
7325 | transmute(a) | |
7326 | } | |
7327 | ||
7328 | /// Vector reinterpret cast operation | |
7329 | #[inline] | |
7330 | #[target_feature(enable = "neon")] | |
7331 | #[cfg_attr(test, assert_instr(str))] | |
7332 | pub unsafe fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t { | |
7333 | transmute(a) | |
7334 | } | |
7335 | ||
7336 | /// Vector reinterpret cast operation | |
7337 | #[inline] | |
7338 | #[target_feature(enable = "neon")] | |
7339 | #[cfg_attr(test, assert_instr(str))] | |
7340 | pub unsafe fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { | |
7341 | transmute(a) | |
7342 | } | |
7343 | ||
7344 | /// Vector reinterpret cast operation | |
7345 | #[inline] | |
7346 | #[target_feature(enable = "neon")] | |
7347 | #[cfg_attr(test, assert_instr(str))] | |
7348 | pub unsafe fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t { | |
7349 | transmute(a) | |
7350 | } | |
7351 | ||
7352 | /// Vector reinterpret cast operation | |
7353 | #[inline] | |
7354 | #[target_feature(enable = "neon")] | |
7355 | #[cfg_attr(test, assert_instr(str))] | |
7356 | pub unsafe fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t { | |
7357 | transmute(a) | |
7358 | } | |
7359 | ||
7360 | /// Vector reinterpret cast operation | |
7361 | #[inline] | |
7362 | #[target_feature(enable = "neon")] | |
7363 | #[cfg_attr(test, assert_instr(str))] | |
7364 | pub unsafe fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t { | |
7365 | transmute(a) | |
7366 | } | |
7367 | ||
7368 | /// Vector reinterpret cast operation | |
7369 | #[inline] | |
7370 | #[target_feature(enable = "neon")] | |
7371 | #[cfg_attr(test, assert_instr(str))] | |
7372 | pub unsafe fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { | |
7373 | transmute(a) | |
7374 | } | |
7375 | ||
7376 | /// Vector reinterpret cast operation | |
7377 | #[inline] | |
7378 | #[target_feature(enable = "neon")] | |
7379 | #[cfg_attr(test, assert_instr(str))] | |
7380 | pub unsafe fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { | |
7381 | transmute(a) | |
7382 | } | |
7383 | ||
7384 | /// Vector reinterpret cast operation | |
7385 | #[inline] | |
7386 | #[target_feature(enable = "neon")] | |
7387 | #[cfg_attr(test, assert_instr(str))] | |
7388 | pub unsafe fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { | |
7389 | transmute(a) | |
7390 | } | |
7391 | ||
7392 | /// Vector reinterpret cast operation | |
7393 | #[inline] | |
7394 | #[target_feature(enable = "neon")] | |
7395 | #[cfg_attr(test, assert_instr(str))] | |
7396 | pub unsafe fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { | |
7397 | transmute(a) | |
7398 | } | |
7399 | ||
7400 | /// Vector reinterpret cast operation | |
7401 | #[inline] | |
7402 | #[target_feature(enable = "neon")] | |
7403 | #[cfg_attr(test, assert_instr(str))] | |
7404 | pub unsafe fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { | |
7405 | transmute(a) | |
7406 | } | |
7407 | ||
7408 | /// Vector reinterpret cast operation | |
7409 | #[inline] | |
7410 | #[target_feature(enable = "neon")] | |
7411 | #[cfg_attr(test, assert_instr(str))] | |
7412 | pub unsafe fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { | |
7413 | transmute(a) | |
7414 | } | |
7415 | ||
7416 | /// Vector reinterpret cast operation | |
7417 | #[inline] | |
7418 | #[target_feature(enable = "neon")] | |
7419 | #[cfg_attr(test, assert_instr(str))] | |
7420 | pub unsafe fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { | |
7421 | transmute(a) | |
7422 | } | |
7423 | ||
7424 | /// Vector reinterpret cast operation | |
7425 | #[inline] | |
7426 | #[target_feature(enable = "neon")] | |
7427 | #[cfg_attr(test, assert_instr(str))] | |
7428 | pub unsafe fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t { | |
7429 | transmute(a) | |
7430 | } | |
7431 | ||
7432 | /// Vector reinterpret cast operation | |
7433 | #[inline] | |
7434 | #[target_feature(enable = "neon")] | |
7435 | #[cfg_attr(test, assert_instr(str))] | |
7436 | pub unsafe fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t { | |
7437 | transmute(a) | |
7438 | } | |
7439 | ||
7440 | /// Vector reinterpret cast operation | |
7441 | #[inline] | |
7442 | #[target_feature(enable = "neon")] | |
7443 | #[cfg_attr(test, assert_instr(str))] | |
7444 | pub unsafe fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t { | |
7445 | transmute(a) | |
7446 | } | |
7447 | ||
7448 | /// Vector reinterpret cast operation | |
7449 | #[inline] | |
7450 | #[target_feature(enable = "neon")] | |
7451 | #[cfg_attr(test, assert_instr(str))] | |
7452 | pub unsafe fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { | |
7453 | transmute(a) | |
7454 | } | |
7455 | ||
7456 | /// Vector reinterpret cast operation | |
7457 | #[inline] | |
7458 | #[target_feature(enable = "neon")] | |
7459 | #[cfg_attr(test, assert_instr(str))] | |
7460 | pub unsafe fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { | |
7461 | transmute(a) | |
7462 | } | |
7463 | ||
7464 | /// Vector reinterpret cast operation | |
7465 | #[inline] | |
7466 | #[target_feature(enable = "neon")] | |
7467 | #[cfg_attr(test, assert_instr(str))] | |
7468 | pub unsafe fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { | |
7469 | transmute(a) | |
7470 | } | |
7471 | ||
7472 | /// Vector reinterpret cast operation | |
7473 | #[inline] | |
7474 | #[target_feature(enable = "neon")] | |
7475 | #[cfg_attr(test, assert_instr(str))] | |
7476 | pub unsafe fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { | |
7477 | transmute(a) | |
7478 | } | |
7479 | ||
7480 | /// Vector reinterpret cast operation | |
7481 | #[inline] | |
7482 | #[target_feature(enable = "neon")] | |
7483 | #[cfg_attr(test, assert_instr(str))] | |
7484 | pub unsafe fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { | |
7485 | transmute(a) | |
7486 | } | |
7487 | ||
7488 | /// Vector reinterpret cast operation | |
7489 | #[inline] | |
7490 | #[target_feature(enable = "neon")] | |
7491 | #[cfg_attr(test, assert_instr(str))] | |
7492 | pub unsafe fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { | |
7493 | transmute(a) | |
7494 | } | |
7495 | ||
7496 | /// Vector reinterpret cast operation | |
7497 | #[inline] | |
7498 | #[target_feature(enable = "neon")] | |
7499 | #[cfg_attr(test, assert_instr(str))] | |
7500 | pub unsafe fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { | |
7501 | transmute(a) | |
7502 | } | |
7503 | ||
7504 | /// Vector reinterpret cast operation | |
7505 | #[inline] | |
7506 | #[target_feature(enable = "neon")] | |
7507 | #[cfg_attr(test, assert_instr(str))] | |
7508 | pub unsafe fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { | |
7509 | transmute(a) | |
7510 | } | |
7511 | ||
7512 | /// Vector reinterpret cast operation | |
7513 | #[inline] | |
7514 | #[target_feature(enable = "neon")] | |
7515 | #[cfg_attr(test, assert_instr(str))] | |
7516 | pub unsafe fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { | |
7517 | transmute(a) | |
7518 | } | |
7519 | ||
7520 | /// Vector reinterpret cast operation | |
7521 | #[inline] | |
7522 | #[target_feature(enable = "neon")] | |
7523 | #[cfg_attr(test, assert_instr(str))] | |
7524 | pub unsafe fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t { | |
7525 | transmute(a) | |
7526 | } | |
7527 | ||
7528 | /// Vector reinterpret cast operation | |
7529 | #[inline] | |
7530 | #[target_feature(enable = "neon")] | |
7531 | #[cfg_attr(test, assert_instr(str))] | |
7532 | pub unsafe fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t { | |
7533 | transmute(a) | |
7534 | } | |
7535 | ||
7536 | /// Vector reinterpret cast operation | |
7537 | #[inline] | |
7538 | #[target_feature(enable = "neon")] | |
7539 | #[cfg_attr(test, assert_instr(str))] | |
7540 | pub unsafe fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t { | |
7541 | transmute(a) | |
7542 | } | |
7543 | ||
7544 | /// Vector reinterpret cast operation | |
7545 | #[inline] | |
7546 | #[target_feature(enable = "neon")] | |
7547 | #[cfg_attr(test, assert_instr(str))] | |
7548 | pub unsafe fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { | |
7549 | transmute(a) | |
7550 | } | |
7551 | ||
7552 | /// Vector reinterpret cast operation | |
7553 | #[inline] | |
7554 | #[target_feature(enable = "neon")] | |
7555 | #[cfg_attr(test, assert_instr(str))] | |
7556 | pub unsafe fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { | |
7557 | transmute(a) | |
7558 | } | |
7559 | ||
7560 | /// Vector reinterpret cast operation | |
7561 | #[inline] | |
7562 | #[target_feature(enable = "neon")] | |
7563 | #[cfg_attr(test, assert_instr(str))] | |
7564 | pub unsafe fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { | |
7565 | transmute(a) | |
7566 | } | |
7567 | ||
7568 | /// Vector reinterpret cast operation | |
7569 | #[inline] | |
7570 | #[target_feature(enable = "neon")] | |
7571 | #[cfg_attr(test, assert_instr(str))] | |
7572 | pub unsafe fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { | |
7573 | transmute(a) | |
7574 | } | |
7575 | ||
7576 | /// Vector reinterpret cast operation | |
7577 | #[inline] | |
7578 | #[target_feature(enable = "neon")] | |
7579 | #[cfg_attr(test, assert_instr(str))] | |
7580 | pub unsafe fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { | |
7581 | transmute(a) | |
7582 | } | |
7583 | ||
7584 | /// Vector reinterpret cast operation | |
7585 | #[inline] | |
7586 | #[target_feature(enable = "neon")] | |
7587 | #[cfg_attr(test, assert_instr(str))] | |
7588 | pub unsafe fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { | |
7589 | transmute(a) | |
7590 | } | |
7591 | ||
7592 | /// Vector reinterpret cast operation | |
7593 | #[inline] | |
7594 | #[target_feature(enable = "neon")] | |
7595 | #[cfg_attr(test, assert_instr(str))] | |
7596 | pub unsafe fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t { | |
7597 | transmute(a) | |
7598 | } | |
7599 | ||
7600 | /// Vector reinterpret cast operation | |
7601 | #[inline] | |
7602 | #[target_feature(enable = "neon")] | |
7603 | #[cfg_attr(test, assert_instr(str))] | |
7604 | pub unsafe fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t { | |
7605 | transmute(a) | |
7606 | } | |
7607 | ||
7608 | /// Vector reinterpret cast operation | |
7609 | #[inline] | |
7610 | #[target_feature(enable = "neon")] | |
7611 | #[cfg_attr(test, assert_instr(str))] | |
7612 | pub unsafe fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t { | |
7613 | transmute(a) | |
7614 | } | |
7615 | ||
7616 | /// Vector reinterpret cast operation | |
7617 | #[inline] | |
7618 | #[target_feature(enable = "neon")] | |
7619 | #[cfg_attr(test, assert_instr(str))] | |
7620 | pub unsafe fn vreinterpret_s64_f64(a: float64x1_t) -> int64x1_t { | |
7621 | transmute(a) | |
7622 | } | |
7623 | ||
7624 | /// Vector reinterpret cast operation | |
7625 | #[inline] | |
7626 | #[target_feature(enable = "neon")] | |
7627 | #[cfg_attr(test, assert_instr(str))] | |
7628 | pub unsafe fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t { | |
7629 | transmute(a) | |
7630 | } | |
7631 | ||
7632 | /// Vector reinterpret cast operation | |
7633 | #[inline] | |
7634 | #[target_feature(enable = "neon")] | |
7635 | #[cfg_attr(test, assert_instr(str))] | |
7636 | pub unsafe fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t { | |
7637 | transmute(a) | |
7638 | } | |
7639 | ||
7640 | /// Vector reinterpret cast operation | |
7641 | #[inline] | |
7642 | #[target_feature(enable = "neon")] | |
7643 | #[cfg_attr(test, assert_instr(str))] | |
7644 | pub unsafe fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t { | |
7645 | transmute(a) | |
7646 | } | |
7647 | ||
7648 | /// Vector reinterpret cast operation | |
7649 | #[inline] | |
7650 | #[target_feature(enable = "neon")] | |
7651 | #[cfg_attr(test, assert_instr(str))] | |
7652 | pub unsafe fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t { | |
7653 | transmute(a) | |
7654 | } | |
7655 | ||
7656 | /// Vector reinterpret cast operation | |
7657 | #[inline] | |
7658 | #[target_feature(enable = "neon")] | |
7659 | #[cfg_attr(test, assert_instr(str))] | |
7660 | pub unsafe fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t { | |
7661 | transmute(a) | |
7662 | } | |
7663 | ||
7664 | /// Vector reinterpret cast operation | |
7665 | #[inline] | |
7666 | #[target_feature(enable = "neon")] | |
7667 | #[cfg_attr(test, assert_instr(str))] | |
7668 | pub unsafe fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t { | |
7669 | transmute(a) | |
7670 | } | |
7671 | ||
7672 | /// Vector reinterpret cast operation | |
7673 | #[inline] | |
7674 | #[target_feature(enable = "neon")] | |
7675 | #[cfg_attr(test, assert_instr(str))] | |
7676 | pub unsafe fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t { | |
7677 | transmute(a) | |
7678 | } | |
7679 | ||
7680 | /// Vector reinterpret cast operation | |
7681 | #[inline] | |
7682 | #[target_feature(enable = "neon")] | |
7683 | #[cfg_attr(test, assert_instr(str))] | |
7684 | pub unsafe fn vreinterpret_u64_f64(a: float64x1_t) -> uint64x1_t { | |
7685 | transmute(a) | |
7686 | } | |
7687 | ||
7688 | /// Vector reinterpret cast operation | |
7689 | #[inline] | |
7690 | #[target_feature(enable = "neon")] | |
7691 | #[cfg_attr(test, assert_instr(str))] | |
7692 | pub unsafe fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t { | |
7693 | transmute(a) | |
7694 | } | |
7695 | ||
7696 | /// Vector reinterpret cast operation | |
7697 | #[inline] | |
7698 | #[target_feature(enable = "neon")] | |
7699 | #[cfg_attr(test, assert_instr(str))] | |
7700 | pub unsafe fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t { | |
7701 | transmute(a) | |
7702 | } | |
7703 | ||
7704 | /// Vector reinterpret cast operation | |
7705 | #[inline] | |
7706 | #[target_feature(enable = "neon")] | |
7707 | #[cfg_attr(test, assert_instr(str))] | |
7708 | pub unsafe fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t { | |
7709 | transmute(a) | |
7710 | } | |
7711 | ||
7712 | /// Vector reinterpret cast operation | |
7713 | #[inline] | |
7714 | #[target_feature(enable = "neon")] | |
7715 | #[cfg_attr(test, assert_instr(str))] | |
7716 | pub unsafe fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t { | |
7717 | transmute(a) | |
7718 | } | |
7719 | ||
7720 | /// Vector reinterpret cast operation | |
7721 | #[inline] | |
7722 | #[target_feature(enable = "neon")] | |
7723 | #[cfg_attr(test, assert_instr(str))] | |
7724 | pub unsafe fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t { | |
7725 | transmute(a) | |
7726 | } | |
7727 | ||
7728 | /// Vector reinterpret cast operation | |
7729 | #[inline] | |
7730 | #[target_feature(enable = "neon")] | |
7731 | #[cfg_attr(test, assert_instr(str))] | |
7732 | pub unsafe fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t { | |
7733 | transmute(a) | |
7734 | } | |
7735 | ||
7736 | /// Vector reinterpret cast operation | |
7737 | #[inline] | |
7738 | #[target_feature(enable = "neon")] | |
7739 | #[cfg_attr(test, assert_instr(str))] | |
7740 | pub unsafe fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t { | |
7741 | transmute(a) | |
7742 | } | |
7743 | ||
7744 | /// Vector reinterpret cast operation | |
7745 | #[inline] | |
7746 | #[target_feature(enable = "neon")] | |
7747 | #[cfg_attr(test, assert_instr(str))] | |
7748 | pub unsafe fn vreinterpret_p64_f64(a: float64x1_t) -> poly64x1_t { | |
7749 | transmute(a) | |
7750 | } | |
7751 | ||
7752 | /// Vector reinterpret cast operation | |
7753 | #[inline] | |
7754 | #[target_feature(enable = "neon")] | |
7755 | #[cfg_attr(test, assert_instr(str))] | |
7756 | pub unsafe fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t { | |
7757 | transmute(a) | |
7758 | } | |
7759 | ||
7760 | /// Vector reinterpret cast operation | |
7761 | #[inline] | |
7762 | #[target_feature(enable = "neon")] | |
7763 | #[cfg_attr(test, assert_instr(str))] | |
7764 | pub unsafe fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t { | |
7765 | transmute(a) | |
7766 | } | |
7767 | ||
7768 | /// Vector reinterpret cast operation | |
7769 | #[inline] | |
7770 | #[target_feature(enable = "neon")] | |
7771 | #[cfg_attr(test, assert_instr(str))] | |
7772 | pub unsafe fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t { | |
7773 | transmute(a) | |
7774 | } | |
7775 | ||
7776 | /// Vector reinterpret cast operation | |
7777 | #[inline] | |
7778 | #[target_feature(enable = "neon")] | |
7779 | #[cfg_attr(test, assert_instr(str))] | |
7780 | pub unsafe fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t { | |
7781 | transmute(a) | |
7782 | } | |
7783 | ||
7784 | /// Vector reinterpret cast operation | |
7785 | #[inline] | |
7786 | #[target_feature(enable = "neon")] | |
7787 | #[cfg_attr(test, assert_instr(str))] | |
7788 | pub unsafe fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t { | |
7789 | transmute(a) | |
7790 | } | |
7791 | ||
7792 | /// Vector reinterpret cast operation | |
7793 | #[inline] | |
7794 | #[target_feature(enable = "neon")] | |
7795 | #[cfg_attr(test, assert_instr(str))] | |
7796 | pub unsafe fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t { | |
7797 | transmute(a) | |
7798 | } | |
7799 | ||
7800 | /// Vector reinterpret cast operation | |
7801 | #[inline] | |
7802 | #[target_feature(enable = "neon")] | |
7803 | #[cfg_attr(test, assert_instr(str))] | |
7804 | pub unsafe fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t { | |
7805 | transmute(a) | |
7806 | } | |
7807 | ||
7808 | /// Vector reinterpret cast operation | |
7809 | #[inline] | |
7810 | #[target_feature(enable = "neon")] | |
7811 | #[cfg_attr(test, assert_instr(str))] | |
7812 | pub unsafe fn vreinterpret_f64_s64(a: int64x1_t) -> float64x1_t { | |
7813 | transmute(a) | |
7814 | } | |
7815 | ||
7816 | /// Vector reinterpret cast operation | |
7817 | #[inline] | |
7818 | #[target_feature(enable = "neon")] | |
7819 | #[cfg_attr(test, assert_instr(str))] | |
7820 | pub unsafe fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t { | |
7821 | transmute(a) | |
7822 | } | |
7823 | ||
7824 | /// Vector reinterpret cast operation | |
7825 | #[inline] | |
7826 | #[target_feature(enable = "neon")] | |
7827 | #[cfg_attr(test, assert_instr(str))] | |
7828 | pub unsafe fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t { | |
7829 | transmute(a) | |
7830 | } | |
7831 | ||
7832 | /// Vector reinterpret cast operation | |
7833 | #[inline] | |
7834 | #[target_feature(enable = "neon")] | |
7835 | #[cfg_attr(test, assert_instr(str))] | |
7836 | pub unsafe fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t { | |
7837 | transmute(a) | |
7838 | } | |
7839 | ||
7840 | /// Vector reinterpret cast operation | |
7841 | #[inline] | |
7842 | #[target_feature(enable = "neon")] | |
7843 | #[cfg_attr(test, assert_instr(str))] | |
7844 | pub unsafe fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t { | |
7845 | transmute(a) | |
7846 | } | |
7847 | ||
7848 | /// Vector reinterpret cast operation | |
7849 | #[inline] | |
7850 | #[target_feature(enable = "neon")] | |
7851 | #[cfg_attr(test, assert_instr(str))] | |
7852 | pub unsafe fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t { | |
7853 | transmute(a) | |
7854 | } | |
7855 | ||
7856 | /// Vector reinterpret cast operation | |
7857 | #[inline] | |
7858 | #[target_feature(enable = "neon")] | |
7859 | #[cfg_attr(test, assert_instr(str))] | |
7860 | pub unsafe fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t { | |
7861 | transmute(a) | |
7862 | } | |
7863 | ||
7864 | /// Vector reinterpret cast operation | |
7865 | #[inline] | |
7866 | #[target_feature(enable = "neon")] | |
7867 | #[cfg_attr(test, assert_instr(str))] | |
7868 | pub unsafe fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t { | |
7869 | transmute(a) | |
7870 | } | |
7871 | ||
7872 | /// Vector reinterpret cast operation | |
7873 | #[inline] | |
7874 | #[target_feature(enable = "neon")] | |
7875 | #[cfg_attr(test, assert_instr(str))] | |
7876 | pub unsafe fn vreinterpret_f64_u64(a: uint64x1_t) -> float64x1_t { | |
7877 | transmute(a) | |
7878 | } | |
7879 | ||
7880 | /// Vector reinterpret cast operation | |
7881 | #[inline] | |
7882 | #[target_feature(enable = "neon")] | |
7883 | #[cfg_attr(test, assert_instr(str))] | |
7884 | pub unsafe fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t { | |
7885 | transmute(a) | |
7886 | } | |
7887 | ||
7888 | /// Vector reinterpret cast operation | |
7889 | #[inline] | |
7890 | #[target_feature(enable = "neon")] | |
7891 | #[cfg_attr(test, assert_instr(str))] | |
7892 | pub unsafe fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t { | |
7893 | transmute(a) | |
7894 | } | |
7895 | ||
7896 | /// Vector reinterpret cast operation | |
7897 | #[inline] | |
7898 | #[target_feature(enable = "neon")] | |
7899 | #[cfg_attr(test, assert_instr(str))] | |
7900 | pub unsafe fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t { | |
7901 | transmute(a) | |
7902 | } | |
7903 | ||
7904 | /// Vector reinterpret cast operation | |
7905 | #[inline] | |
7906 | #[target_feature(enable = "neon")] | |
7907 | #[cfg_attr(test, assert_instr(str))] | |
7908 | pub unsafe fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t { | |
7909 | transmute(a) | |
7910 | } | |
7911 | ||
7912 | /// Vector reinterpret cast operation | |
7913 | #[inline] | |
7914 | #[target_feature(enable = "neon")] | |
7915 | #[cfg_attr(test, assert_instr(str))] | |
7916 | pub unsafe fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t { | |
7917 | transmute(a) | |
7918 | } | |
7919 | ||
7920 | /// Vector reinterpret cast operation | |
7921 | #[inline] | |
7922 | #[target_feature(enable = "neon")] | |
7923 | #[cfg_attr(test, assert_instr(str))] | |
7924 | pub unsafe fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t { | |
7925 | transmute(a) | |
7926 | } | |
7927 | ||
7928 | /// Vector reinterpret cast operation | |
7929 | #[inline] | |
7930 | #[target_feature(enable = "neon")] | |
7931 | #[cfg_attr(test, assert_instr(str))] | |
7932 | pub unsafe fn vreinterpret_f64_p64(a: poly64x1_t) -> float64x1_t { | |
7933 | transmute(a) | |
7934 | } | |
7935 | ||
7936 | /// Vector reinterpret cast operation | |
7937 | #[inline] | |
7938 | #[target_feature(enable = "neon")] | |
7939 | #[cfg_attr(test, assert_instr(str))] | |
7940 | pub unsafe fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t { | |
7941 | transmute(a) | |
7942 | } | |
7943 | ||
7944 | /// Vector reinterpret cast operation | |
7945 | #[inline] | |
7946 | #[target_feature(enable = "neon")] | |
7947 | #[cfg_attr(test, assert_instr(str))] | |
7948 | pub unsafe fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t { | |
7949 | transmute(a) | |
7950 | } | |
7951 | ||
7952 | /// Vector reinterpret cast operation | |
7953 | #[inline] | |
7954 | #[target_feature(enable = "neon")] | |
7955 | #[cfg_attr(test, assert_instr(str))] | |
7956 | pub unsafe fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t { | |
7957 | transmute(a) | |
7958 | } | |
7959 | ||
7960 | /// Vector reinterpret cast operation | |
7961 | #[inline] | |
7962 | #[target_feature(enable = "neon")] | |
7963 | #[cfg_attr(test, assert_instr(str))] | |
7964 | pub unsafe fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t { | |
7965 | transmute(a) | |
7966 | } | |
7967 | ||
7968 | /// Vector reinterpret cast operation | |
7969 | #[inline] | |
7970 | #[target_feature(enable = "neon")] | |
7971 | #[cfg_attr(test, assert_instr(str))] | |
7972 | pub unsafe fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t { | |
7973 | transmute(a) | |
7974 | } | |
7975 | ||
7976 | /// Vector reinterpret cast operation | |
7977 | #[inline] | |
7978 | #[target_feature(enable = "neon")] | |
7979 | #[cfg_attr(test, assert_instr(str))] | |
7980 | pub unsafe fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t { | |
7981 | transmute(a) | |
7982 | } | |
7983 | ||
7984 | /// Vector reinterpret cast operation | |
7985 | #[inline] | |
7986 | #[target_feature(enable = "neon")] | |
7987 | #[cfg_attr(test, assert_instr(str))] | |
7988 | pub unsafe fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t { | |
7989 | transmute(a) | |
7990 | } | |
7991 | ||
7992 | /// Vector reinterpret cast operation | |
7993 | #[inline] | |
7994 | #[target_feature(enable = "neon")] | |
7995 | #[cfg_attr(test, assert_instr(str))] | |
7996 | pub unsafe fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t { | |
7997 | transmute(a) | |
7998 | } | |
7999 | ||
8000 | /// Vector reinterpret cast operation | |
8001 | #[inline] | |
8002 | #[target_feature(enable = "neon")] | |
8003 | #[cfg_attr(test, assert_instr(str))] | |
8004 | pub unsafe fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t { | |
8005 | transmute(a) | |
8006 | } | |
8007 | ||
8008 | /// Signed rounding shift left | |
8009 | #[inline] | |
8010 | #[target_feature(enable = "neon")] | |
8011 | #[cfg_attr(test, assert_instr(srshl))] | |
8012 | pub unsafe fn vrshld_s64(a: i64, b: i64) -> i64 { | |
8013 | #[allow(improper_ctypes)] | |
8014 | extern "C" { | |
8015 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.srshl.i64")] | |
8016 | fn vrshld_s64_(a: i64, b: i64) -> i64; | |
8017 | } | |
8018 | vrshld_s64_(a, b) | |
8019 | } | |
8020 | ||
8021 | /// Unsigned rounding shift left | |
8022 | #[inline] | |
8023 | #[target_feature(enable = "neon")] | |
8024 | #[cfg_attr(test, assert_instr(urshl))] | |
8025 | pub unsafe fn vrshld_u64(a: u64, b: i64) -> u64 { | |
8026 | #[allow(improper_ctypes)] | |
8027 | extern "C" { | |
8028 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.urshl.i64")] | |
8029 | fn vrshld_u64_(a: u64, b: i64) -> u64; | |
8030 | } | |
8031 | vrshld_u64_(a, b) | |
8032 | } | |
8033 | ||
8034 | /// Signed rounding shift right | |
8035 | #[inline] | |
8036 | #[target_feature(enable = "neon")] | |
8037 | #[cfg_attr(test, assert_instr(srshr, N = 2))] | |
8038 | #[rustc_legacy_const_generics(1)] | |
8039 | pub unsafe fn vrshrd_n_s64<const N: i32>(a: i64) -> i64 { | |
8040 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
8041 | vrshld_s64(a, -N as i64) | |
8042 | } | |
8043 | ||
8044 | /// Unsigned rounding shift right | |
8045 | #[inline] | |
8046 | #[target_feature(enable = "neon")] | |
8047 | #[cfg_attr(test, assert_instr(urshr, N = 2))] | |
8048 | #[rustc_legacy_const_generics(1)] | |
8049 | pub unsafe fn vrshrd_n_u64<const N: i32>(a: u64) -> u64 { | |
8050 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
8051 | vrshld_u64(a, -N as i64) | |
8052 | } | |
8053 | ||
8054 | /// Rounding shift right narrow | |
8055 | #[inline] | |
8056 | #[target_feature(enable = "neon")] | |
8057 | #[cfg_attr(test, assert_instr(rshrn2, N = 2))] | |
8058 | #[rustc_legacy_const_generics(2)] | |
8059 | pub unsafe fn vrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t { | |
8060 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
8061 | simd_shuffle16!(a, vrshrn_n_s16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
8062 | } | |
8063 | ||
8064 | /// Rounding shift right narrow | |
8065 | #[inline] | |
8066 | #[target_feature(enable = "neon")] | |
8067 | #[cfg_attr(test, assert_instr(rshrn2, N = 2))] | |
8068 | #[rustc_legacy_const_generics(2)] | |
8069 | pub unsafe fn vrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t { | |
8070 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
8071 | simd_shuffle8!(a, vrshrn_n_s32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
8072 | } | |
8073 | ||
8074 | /// Rounding shift right narrow | |
8075 | #[inline] | |
8076 | #[target_feature(enable = "neon")] | |
8077 | #[cfg_attr(test, assert_instr(rshrn2, N = 2))] | |
8078 | #[rustc_legacy_const_generics(2)] | |
8079 | pub unsafe fn vrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t { | |
8080 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
8081 | simd_shuffle4!(a, vrshrn_n_s64::<N>(b), [0, 1, 2, 3]) | |
8082 | } | |
8083 | ||
8084 | /// Rounding shift right narrow | |
8085 | #[inline] | |
8086 | #[target_feature(enable = "neon")] | |
8087 | #[cfg_attr(test, assert_instr(rshrn2, N = 2))] | |
8088 | #[rustc_legacy_const_generics(2)] | |
8089 | pub unsafe fn vrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { | |
8090 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
8091 | simd_shuffle16!(a, vrshrn_n_u16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
8092 | } | |
8093 | ||
8094 | /// Rounding shift right narrow | |
8095 | #[inline] | |
8096 | #[target_feature(enable = "neon")] | |
8097 | #[cfg_attr(test, assert_instr(rshrn2, N = 2))] | |
8098 | #[rustc_legacy_const_generics(2)] | |
8099 | pub unsafe fn vrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { | |
8100 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
8101 | simd_shuffle8!(a, vrshrn_n_u32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
8102 | } | |
8103 | ||
8104 | /// Rounding shift right narrow | |
8105 | #[inline] | |
8106 | #[target_feature(enable = "neon")] | |
8107 | #[cfg_attr(test, assert_instr(rshrn2, N = 2))] | |
8108 | #[rustc_legacy_const_generics(2)] | |
8109 | pub unsafe fn vrshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { | |
8110 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
8111 | simd_shuffle4!(a, vrshrn_n_u64::<N>(b), [0, 1, 2, 3]) | |
8112 | } | |
8113 | ||
8114 | /// Signed rounding shift right and accumulate. | |
8115 | #[inline] | |
8116 | #[target_feature(enable = "neon")] | |
8117 | #[cfg_attr(test, assert_instr(srsra, N = 2))] | |
8118 | #[rustc_legacy_const_generics(2)] | |
8119 | pub unsafe fn vrsrad_n_s64<const N: i32>(a: i64, b: i64) -> i64 { | |
8120 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
8121 | let b: i64 = vrshrd_n_s64::<N>(b); | |
8122 | a + b | |
8123 | } | |
8124 | ||
8125 | /// Ungisned rounding shift right and accumulate. | |
8126 | #[inline] | |
8127 | #[target_feature(enable = "neon")] | |
8128 | #[cfg_attr(test, assert_instr(ursra, N = 2))] | |
8129 | #[rustc_legacy_const_generics(2)] | |
8130 | pub unsafe fn vrsrad_n_u64<const N: i32>(a: u64, b: u64) -> u64 { | |
8131 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
8132 | let b: u64 = vrshrd_n_u64::<N>(b); | |
8133 | a + b | |
8134 | } | |
8135 | ||
8136 | /// Insert vector element from another vector element | |
8137 | #[inline] | |
8138 | #[target_feature(enable = "neon")] | |
8139 | #[cfg_attr(test, assert_instr(nop, LANE = 0))] | |
8140 | #[rustc_legacy_const_generics(2)] | |
8141 | pub unsafe fn vset_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> float64x1_t { | |
8142 | static_assert!(LANE : i32 where LANE == 0); | |
8143 | simd_insert(b, LANE as u32, a) | |
8144 | } | |
8145 | ||
8146 | /// Insert vector element from another vector element | |
8147 | #[inline] | |
8148 | #[target_feature(enable = "neon")] | |
8149 | #[cfg_attr(test, assert_instr(nop, LANE = 0))] | |
8150 | #[rustc_legacy_const_generics(2)] | |
8151 | pub unsafe fn vsetq_lane_f64<const LANE: i32>(a: f64, b: float64x2_t) -> float64x2_t { | |
8152 | static_assert_imm1!(LANE); | |
8153 | simd_insert(b, LANE as u32, a) | |
8154 | } | |
8155 | ||
8156 | /// Signed Shift left | |
8157 | #[inline] | |
8158 | #[target_feature(enable = "neon")] | |
8159 | #[cfg_attr(test, assert_instr(sshl))] | |
8160 | pub unsafe fn vshld_s64(a: i64, b: i64) -> i64 { | |
8161 | transmute(vshl_s64(transmute(a), transmute(b))) | |
8162 | } | |
8163 | ||
8164 | /// Unsigned Shift left | |
8165 | #[inline] | |
8166 | #[target_feature(enable = "neon")] | |
8167 | #[cfg_attr(test, assert_instr(ushl))] | |
8168 | pub unsafe fn vshld_u64(a: u64, b: i64) -> u64 { | |
8169 | transmute(vshl_u64(transmute(a), transmute(b))) | |
8170 | } | |
8171 | ||
8172 | /// Signed shift left long | |
8173 | #[inline] | |
8174 | #[target_feature(enable = "neon")] | |
8175 | #[cfg_attr(test, assert_instr(sshll2, N = 2))] | |
8176 | #[rustc_legacy_const_generics(1)] | |
8177 | pub unsafe fn vshll_high_n_s8<const N: i32>(a: int8x16_t) -> int16x8_t { | |
8178 | static_assert!(N : i32 where N >= 0 && N <= 8); | |
8179 | let b: int8x8_t = simd_shuffle8!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); | |
8180 | vshll_n_s8::<N>(b) | |
8181 | } | |
8182 | ||
8183 | /// Signed shift left long | |
8184 | #[inline] | |
8185 | #[target_feature(enable = "neon")] | |
8186 | #[cfg_attr(test, assert_instr(sshll2, N = 2))] | |
8187 | #[rustc_legacy_const_generics(1)] | |
8188 | pub unsafe fn vshll_high_n_s16<const N: i32>(a: int16x8_t) -> int32x4_t { | |
8189 | static_assert!(N : i32 where N >= 0 && N <= 16); | |
8190 | let b: int16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
8191 | vshll_n_s16::<N>(b) | |
8192 | } | |
8193 | ||
8194 | /// Signed shift left long | |
8195 | #[inline] | |
8196 | #[target_feature(enable = "neon")] | |
8197 | #[cfg_attr(test, assert_instr(sshll2, N = 2))] | |
8198 | #[rustc_legacy_const_generics(1)] | |
8199 | pub unsafe fn vshll_high_n_s32<const N: i32>(a: int32x4_t) -> int64x2_t { | |
8200 | static_assert!(N : i32 where N >= 0 && N <= 32); | |
8201 | let b: int32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
8202 | vshll_n_s32::<N>(b) | |
8203 | } | |
8204 | ||
8205 | /// Signed shift left long | |
8206 | #[inline] | |
8207 | #[target_feature(enable = "neon")] | |
8208 | #[cfg_attr(test, assert_instr(ushll2, N = 2))] | |
8209 | #[rustc_legacy_const_generics(1)] | |
8210 | pub unsafe fn vshll_high_n_u8<const N: i32>(a: uint8x16_t) -> uint16x8_t { | |
8211 | static_assert!(N : i32 where N >= 0 && N <= 8); | |
8212 | let b: uint8x8_t = simd_shuffle8!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); | |
8213 | vshll_n_u8::<N>(b) | |
8214 | } | |
8215 | ||
8216 | /// Signed shift left long | |
8217 | #[inline] | |
8218 | #[target_feature(enable = "neon")] | |
8219 | #[cfg_attr(test, assert_instr(ushll2, N = 2))] | |
8220 | #[rustc_legacy_const_generics(1)] | |
8221 | pub unsafe fn vshll_high_n_u16<const N: i32>(a: uint16x8_t) -> uint32x4_t { | |
8222 | static_assert!(N : i32 where N >= 0 && N <= 16); | |
8223 | let b: uint16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
8224 | vshll_n_u16::<N>(b) | |
8225 | } | |
8226 | ||
8227 | /// Signed shift left long | |
8228 | #[inline] | |
8229 | #[target_feature(enable = "neon")] | |
8230 | #[cfg_attr(test, assert_instr(ushll2, N = 2))] | |
8231 | #[rustc_legacy_const_generics(1)] | |
8232 | pub unsafe fn vshll_high_n_u32<const N: i32>(a: uint32x4_t) -> uint64x2_t { | |
8233 | static_assert!(N : i32 where N >= 0 && N <= 32); | |
8234 | let b: uint32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
8235 | vshll_n_u32::<N>(b) | |
8236 | } | |
8237 | ||
8238 | /// Shift right narrow | |
8239 | #[inline] | |
8240 | #[target_feature(enable = "neon")] | |
8241 | #[cfg_attr(test, assert_instr(shrn2, N = 2))] | |
8242 | #[rustc_legacy_const_generics(2)] | |
8243 | pub unsafe fn vshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t { | |
8244 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
8245 | simd_shuffle16!(a, vshrn_n_s16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
8246 | } | |
8247 | ||
8248 | /// Shift right narrow | |
8249 | #[inline] | |
8250 | #[target_feature(enable = "neon")] | |
8251 | #[cfg_attr(test, assert_instr(shrn2, N = 2))] | |
8252 | #[rustc_legacy_const_generics(2)] | |
8253 | pub unsafe fn vshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t { | |
8254 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
8255 | simd_shuffle8!(a, vshrn_n_s32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
8256 | } | |
8257 | ||
8258 | /// Shift right narrow | |
8259 | #[inline] | |
8260 | #[target_feature(enable = "neon")] | |
8261 | #[cfg_attr(test, assert_instr(shrn2, N = 2))] | |
8262 | #[rustc_legacy_const_generics(2)] | |
8263 | pub unsafe fn vshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t { | |
8264 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
8265 | simd_shuffle4!(a, vshrn_n_s64::<N>(b), [0, 1, 2, 3]) | |
8266 | } | |
8267 | ||
8268 | /// Shift right narrow | |
8269 | #[inline] | |
8270 | #[target_feature(enable = "neon")] | |
8271 | #[cfg_attr(test, assert_instr(shrn2, N = 2))] | |
8272 | #[rustc_legacy_const_generics(2)] | |
8273 | pub unsafe fn vshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { | |
8274 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
8275 | simd_shuffle16!(a, vshrn_n_u16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
8276 | } | |
8277 | ||
8278 | /// Shift right narrow | |
8279 | #[inline] | |
8280 | #[target_feature(enable = "neon")] | |
8281 | #[cfg_attr(test, assert_instr(shrn2, N = 2))] | |
8282 | #[rustc_legacy_const_generics(2)] | |
8283 | pub unsafe fn vshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { | |
8284 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
8285 | simd_shuffle8!(a, vshrn_n_u32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
8286 | } | |
8287 | ||
8288 | /// Shift right narrow | |
8289 | #[inline] | |
8290 | #[target_feature(enable = "neon")] | |
8291 | #[cfg_attr(test, assert_instr(shrn2, N = 2))] | |
8292 | #[rustc_legacy_const_generics(2)] | |
8293 | pub unsafe fn vshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { | |
8294 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
8295 | simd_shuffle4!(a, vshrn_n_u64::<N>(b), [0, 1, 2, 3]) | |
8296 | } | |
8297 | ||
8298 | /// Transpose vectors | |
8299 | #[inline] | |
8300 | #[target_feature(enable = "neon")] | |
8301 | #[cfg_attr(test, assert_instr(trn1))] | |
8302 | pub unsafe fn vtrn1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { | |
8303 | simd_shuffle8!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) | |
8304 | } | |
8305 | ||
8306 | /// Transpose vectors | |
8307 | #[inline] | |
8308 | #[target_feature(enable = "neon")] | |
8309 | #[cfg_attr(test, assert_instr(trn1))] | |
8310 | pub unsafe fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { | |
8311 | simd_shuffle16!(a, b, [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]) | |
8312 | } | |
8313 | ||
8314 | /// Transpose vectors | |
8315 | #[inline] | |
8316 | #[target_feature(enable = "neon")] | |
8317 | #[cfg_attr(test, assert_instr(trn1))] | |
8318 | pub unsafe fn vtrn1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { | |
8319 | simd_shuffle4!(a, b, [0, 4, 2, 6]) | |
8320 | } | |
8321 | ||
8322 | /// Transpose vectors | |
8323 | #[inline] | |
8324 | #[target_feature(enable = "neon")] | |
8325 | #[cfg_attr(test, assert_instr(trn1))] | |
8326 | pub unsafe fn vtrn1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { | |
8327 | simd_shuffle8!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) | |
8328 | } | |
8329 | ||
8330 | /// Transpose vectors | |
8331 | #[inline] | |
8332 | #[target_feature(enable = "neon")] | |
8333 | #[cfg_attr(test, assert_instr(trn1))] | |
8334 | pub unsafe fn vtrn1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { | |
8335 | simd_shuffle4!(a, b, [0, 4, 2, 6]) | |
8336 | } | |
8337 | ||
8338 | /// Transpose vectors | |
8339 | #[inline] | |
8340 | #[target_feature(enable = "neon")] | |
8341 | #[cfg_attr(test, assert_instr(trn1))] | |
8342 | pub unsafe fn vtrn1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { | |
8343 | simd_shuffle8!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) | |
8344 | } | |
8345 | ||
8346 | /// Transpose vectors | |
8347 | #[inline] | |
8348 | #[target_feature(enable = "neon")] | |
8349 | #[cfg_attr(test, assert_instr(trn1))] | |
8350 | pub unsafe fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { | |
8351 | simd_shuffle16!(a, b, [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]) | |
8352 | } | |
8353 | ||
8354 | /// Transpose vectors | |
8355 | #[inline] | |
8356 | #[target_feature(enable = "neon")] | |
8357 | #[cfg_attr(test, assert_instr(trn1))] | |
8358 | pub unsafe fn vtrn1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { | |
8359 | simd_shuffle4!(a, b, [0, 4, 2, 6]) | |
8360 | } | |
8361 | ||
8362 | /// Transpose vectors | |
8363 | #[inline] | |
8364 | #[target_feature(enable = "neon")] | |
8365 | #[cfg_attr(test, assert_instr(trn1))] | |
8366 | pub unsafe fn vtrn1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { | |
8367 | simd_shuffle8!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) | |
8368 | } | |
8369 | ||
8370 | /// Transpose vectors | |
8371 | #[inline] | |
8372 | #[target_feature(enable = "neon")] | |
8373 | #[cfg_attr(test, assert_instr(trn1))] | |
8374 | pub unsafe fn vtrn1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { | |
8375 | simd_shuffle4!(a, b, [0, 4, 2, 6]) | |
8376 | } | |
8377 | ||
8378 | /// Transpose vectors | |
8379 | #[inline] | |
8380 | #[target_feature(enable = "neon")] | |
8381 | #[cfg_attr(test, assert_instr(trn1))] | |
8382 | pub unsafe fn vtrn1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { | |
8383 | simd_shuffle8!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) | |
8384 | } | |
8385 | ||
8386 | /// Transpose vectors | |
8387 | #[inline] | |
8388 | #[target_feature(enable = "neon")] | |
8389 | #[cfg_attr(test, assert_instr(trn1))] | |
8390 | pub unsafe fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { | |
8391 | simd_shuffle16!(a, b, [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]) | |
8392 | } | |
8393 | ||
8394 | /// Transpose vectors | |
8395 | #[inline] | |
8396 | #[target_feature(enable = "neon")] | |
8397 | #[cfg_attr(test, assert_instr(trn1))] | |
8398 | pub unsafe fn vtrn1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { | |
8399 | simd_shuffle4!(a, b, [0, 4, 2, 6]) | |
8400 | } | |
8401 | ||
8402 | /// Transpose vectors | |
8403 | #[inline] | |
8404 | #[target_feature(enable = "neon")] | |
8405 | #[cfg_attr(test, assert_instr(trn1))] | |
8406 | pub unsafe fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { | |
8407 | simd_shuffle8!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) | |
8408 | } | |
8409 | ||
8410 | /// Transpose vectors | |
8411 | #[inline] | |
8412 | #[target_feature(enable = "neon")] | |
8413 | #[cfg_attr(test, assert_instr(zip1))] | |
8414 | pub unsafe fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { | |
8415 | simd_shuffle2!(a, b, [0, 2]) | |
8416 | } | |
8417 | ||
8418 | /// Transpose vectors | |
8419 | #[inline] | |
8420 | #[target_feature(enable = "neon")] | |
8421 | #[cfg_attr(test, assert_instr(zip1))] | |
8422 | pub unsafe fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { | |
8423 | simd_shuffle2!(a, b, [0, 2]) | |
8424 | } | |
8425 | ||
8426 | /// Transpose vectors | |
8427 | #[inline] | |
8428 | #[target_feature(enable = "neon")] | |
8429 | #[cfg_attr(test, assert_instr(zip1))] | |
8430 | pub unsafe fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { | |
8431 | simd_shuffle2!(a, b, [0, 2]) | |
8432 | } | |
8433 | ||
8434 | /// Transpose vectors | |
8435 | #[inline] | |
8436 | #[target_feature(enable = "neon")] | |
8437 | #[cfg_attr(test, assert_instr(zip1))] | |
8438 | pub unsafe fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
8439 | simd_shuffle2!(a, b, [0, 2]) | |
8440 | } | |
8441 | ||
8442 | /// Transpose vectors | |
8443 | #[inline] | |
8444 | #[target_feature(enable = "neon")] | |
8445 | #[cfg_attr(test, assert_instr(zip1))] | |
8446 | pub unsafe fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { | |
8447 | simd_shuffle2!(a, b, [0, 2]) | |
8448 | } | |
8449 | ||
8450 | /// Transpose vectors | |
8451 | #[inline] | |
8452 | #[target_feature(enable = "neon")] | |
8453 | #[cfg_attr(test, assert_instr(trn1))] | |
8454 | pub unsafe fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
8455 | simd_shuffle4!(a, b, [0, 4, 2, 6]) | |
8456 | } | |
8457 | ||
8458 | /// Transpose vectors | |
8459 | #[inline] | |
8460 | #[target_feature(enable = "neon")] | |
8461 | #[cfg_attr(test, assert_instr(zip1))] | |
8462 | pub unsafe fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
8463 | simd_shuffle2!(a, b, [0, 2]) | |
8464 | } | |
8465 | ||
8466 | /// Transpose vectors | |
8467 | #[inline] | |
8468 | #[target_feature(enable = "neon")] | |
8469 | #[cfg_attr(test, assert_instr(zip1))] | |
8470 | pub unsafe fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
8471 | simd_shuffle2!(a, b, [0, 2]) | |
8472 | } | |
8473 | ||
8474 | /// Transpose vectors | |
8475 | #[inline] | |
8476 | #[target_feature(enable = "neon")] | |
8477 | #[cfg_attr(test, assert_instr(trn2))] | |
8478 | pub unsafe fn vtrn2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { | |
8479 | simd_shuffle8!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) | |
8480 | } | |
8481 | ||
8482 | /// Transpose vectors | |
8483 | #[inline] | |
8484 | #[target_feature(enable = "neon")] | |
8485 | #[cfg_attr(test, assert_instr(trn2))] | |
8486 | pub unsafe fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { | |
8487 | simd_shuffle16!(a, b, [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]) | |
8488 | } | |
8489 | ||
8490 | /// Transpose vectors | |
8491 | #[inline] | |
8492 | #[target_feature(enable = "neon")] | |
8493 | #[cfg_attr(test, assert_instr(trn2))] | |
8494 | pub unsafe fn vtrn2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { | |
8495 | simd_shuffle4!(a, b, [1, 5, 3, 7]) | |
8496 | } | |
8497 | ||
8498 | /// Transpose vectors | |
8499 | #[inline] | |
8500 | #[target_feature(enable = "neon")] | |
8501 | #[cfg_attr(test, assert_instr(trn2))] | |
8502 | pub unsafe fn vtrn2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { | |
8503 | simd_shuffle8!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) | |
8504 | } | |
8505 | ||
8506 | /// Transpose vectors | |
8507 | #[inline] | |
8508 | #[target_feature(enable = "neon")] | |
8509 | #[cfg_attr(test, assert_instr(trn2))] | |
8510 | pub unsafe fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { | |
8511 | simd_shuffle4!(a, b, [1, 5, 3, 7]) | |
8512 | } | |
8513 | ||
8514 | /// Transpose vectors | |
8515 | #[inline] | |
8516 | #[target_feature(enable = "neon")] | |
8517 | #[cfg_attr(test, assert_instr(trn2))] | |
8518 | pub unsafe fn vtrn2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { | |
8519 | simd_shuffle8!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) | |
8520 | } | |
8521 | ||
8522 | /// Transpose vectors | |
8523 | #[inline] | |
8524 | #[target_feature(enable = "neon")] | |
8525 | #[cfg_attr(test, assert_instr(trn2))] | |
8526 | pub unsafe fn vtrn2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { | |
8527 | simd_shuffle16!(a, b, [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]) | |
8528 | } | |
8529 | ||
8530 | /// Transpose vectors | |
8531 | #[inline] | |
8532 | #[target_feature(enable = "neon")] | |
8533 | #[cfg_attr(test, assert_instr(trn2))] | |
8534 | pub unsafe fn vtrn2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { | |
8535 | simd_shuffle4!(a, b, [1, 5, 3, 7]) | |
8536 | } | |
8537 | ||
8538 | /// Transpose vectors | |
8539 | #[inline] | |
8540 | #[target_feature(enable = "neon")] | |
8541 | #[cfg_attr(test, assert_instr(trn2))] | |
8542 | pub unsafe fn vtrn2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { | |
8543 | simd_shuffle8!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) | |
8544 | } | |
8545 | ||
8546 | /// Transpose vectors | |
8547 | #[inline] | |
8548 | #[target_feature(enable = "neon")] | |
8549 | #[cfg_attr(test, assert_instr(trn2))] | |
8550 | pub unsafe fn vtrn2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { | |
8551 | simd_shuffle4!(a, b, [1, 5, 3, 7]) | |
8552 | } | |
8553 | ||
8554 | /// Transpose vectors | |
8555 | #[inline] | |
8556 | #[target_feature(enable = "neon")] | |
8557 | #[cfg_attr(test, assert_instr(trn2))] | |
8558 | pub unsafe fn vtrn2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { | |
8559 | simd_shuffle8!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) | |
8560 | } | |
8561 | ||
8562 | /// Transpose vectors | |
8563 | #[inline] | |
8564 | #[target_feature(enable = "neon")] | |
8565 | #[cfg_attr(test, assert_instr(trn2))] | |
8566 | pub unsafe fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { | |
8567 | simd_shuffle16!(a, b, [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]) | |
8568 | } | |
8569 | ||
8570 | /// Transpose vectors | |
8571 | #[inline] | |
8572 | #[target_feature(enable = "neon")] | |
8573 | #[cfg_attr(test, assert_instr(trn2))] | |
8574 | pub unsafe fn vtrn2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { | |
8575 | simd_shuffle4!(a, b, [1, 5, 3, 7]) | |
8576 | } | |
8577 | ||
8578 | /// Transpose vectors | |
8579 | #[inline] | |
8580 | #[target_feature(enable = "neon")] | |
8581 | #[cfg_attr(test, assert_instr(trn2))] | |
8582 | pub unsafe fn vtrn2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { | |
8583 | simd_shuffle8!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) | |
8584 | } | |
8585 | ||
8586 | /// Transpose vectors | |
8587 | #[inline] | |
8588 | #[target_feature(enable = "neon")] | |
8589 | #[cfg_attr(test, assert_instr(zip2))] | |
8590 | pub unsafe fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { | |
8591 | simd_shuffle2!(a, b, [1, 3]) | |
8592 | } | |
8593 | ||
8594 | /// Transpose vectors | |
8595 | #[inline] | |
8596 | #[target_feature(enable = "neon")] | |
8597 | #[cfg_attr(test, assert_instr(zip2))] | |
8598 | pub unsafe fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { | |
8599 | simd_shuffle2!(a, b, [1, 3]) | |
8600 | } | |
8601 | ||
8602 | /// Transpose vectors | |
8603 | #[inline] | |
8604 | #[target_feature(enable = "neon")] | |
8605 | #[cfg_attr(test, assert_instr(zip2))] | |
8606 | pub unsafe fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { | |
8607 | simd_shuffle2!(a, b, [1, 3]) | |
8608 | } | |
8609 | ||
8610 | /// Transpose vectors | |
8611 | #[inline] | |
8612 | #[target_feature(enable = "neon")] | |
8613 | #[cfg_attr(test, assert_instr(zip2))] | |
8614 | pub unsafe fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
8615 | simd_shuffle2!(a, b, [1, 3]) | |
8616 | } | |
8617 | ||
8618 | /// Transpose vectors | |
8619 | #[inline] | |
8620 | #[target_feature(enable = "neon")] | |
8621 | #[cfg_attr(test, assert_instr(zip2))] | |
8622 | pub unsafe fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { | |
8623 | simd_shuffle2!(a, b, [1, 3]) | |
8624 | } | |
8625 | ||
8626 | /// Transpose vectors | |
8627 | #[inline] | |
8628 | #[target_feature(enable = "neon")] | |
8629 | #[cfg_attr(test, assert_instr(trn2))] | |
8630 | pub unsafe fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
8631 | simd_shuffle4!(a, b, [1, 5, 3, 7]) | |
8632 | } | |
8633 | ||
8634 | /// Transpose vectors | |
8635 | #[inline] | |
8636 | #[target_feature(enable = "neon")] | |
8637 | #[cfg_attr(test, assert_instr(zip2))] | |
8638 | pub unsafe fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
8639 | simd_shuffle2!(a, b, [1, 3]) | |
8640 | } | |
8641 | ||
8642 | /// Transpose vectors | |
8643 | #[inline] | |
8644 | #[target_feature(enable = "neon")] | |
8645 | #[cfg_attr(test, assert_instr(zip2))] | |
8646 | pub unsafe fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
8647 | simd_shuffle2!(a, b, [1, 3]) | |
8648 | } | |
8649 | ||
8650 | /// Zip vectors | |
8651 | #[inline] | |
8652 | #[target_feature(enable = "neon")] | |
8653 | #[cfg_attr(test, assert_instr(zip1))] | |
8654 | pub unsafe fn vzip1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { | |
8655 | simd_shuffle8!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) | |
8656 | } | |
8657 | ||
8658 | /// Zip vectors | |
8659 | #[inline] | |
8660 | #[target_feature(enable = "neon")] | |
8661 | #[cfg_attr(test, assert_instr(zip1))] | |
8662 | pub unsafe fn vzip1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { | |
8663 | simd_shuffle16!(a, b, [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]) | |
8664 | } | |
8665 | ||
8666 | /// Zip vectors | |
8667 | #[inline] | |
8668 | #[target_feature(enable = "neon")] | |
8669 | #[cfg_attr(test, assert_instr(zip1))] | |
8670 | pub unsafe fn vzip1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { | |
8671 | simd_shuffle4!(a, b, [0, 4, 1, 5]) | |
8672 | } | |
8673 | ||
8674 | /// Zip vectors | |
8675 | #[inline] | |
8676 | #[target_feature(enable = "neon")] | |
8677 | #[cfg_attr(test, assert_instr(zip1))] | |
8678 | pub unsafe fn vzip1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { | |
8679 | simd_shuffle8!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) | |
8680 | } | |
8681 | ||
8682 | /// Zip vectors | |
8683 | #[inline] | |
8684 | #[target_feature(enable = "neon")] | |
8685 | #[cfg_attr(test, assert_instr(zip1))] | |
8686 | pub unsafe fn vzip1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { | |
8687 | simd_shuffle2!(a, b, [0, 2]) | |
8688 | } | |
8689 | ||
8690 | /// Zip vectors | |
8691 | #[inline] | |
8692 | #[target_feature(enable = "neon")] | |
8693 | #[cfg_attr(test, assert_instr(zip1))] | |
8694 | pub unsafe fn vzip1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { | |
8695 | simd_shuffle4!(a, b, [0, 4, 1, 5]) | |
8696 | } | |
8697 | ||
8698 | /// Zip vectors | |
8699 | #[inline] | |
8700 | #[target_feature(enable = "neon")] | |
8701 | #[cfg_attr(test, assert_instr(zip1))] | |
8702 | pub unsafe fn vzip1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { | |
8703 | simd_shuffle2!(a, b, [0, 2]) | |
8704 | } | |
8705 | ||
8706 | /// Zip vectors | |
8707 | #[inline] | |
8708 | #[target_feature(enable = "neon")] | |
8709 | #[cfg_attr(test, assert_instr(zip1))] | |
8710 | pub unsafe fn vzip1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { | |
8711 | simd_shuffle8!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) | |
8712 | } | |
8713 | ||
8714 | /// Zip vectors | |
8715 | #[inline] | |
8716 | #[target_feature(enable = "neon")] | |
8717 | #[cfg_attr(test, assert_instr(zip1))] | |
8718 | pub unsafe fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { | |
8719 | simd_shuffle16!(a, b, [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]) | |
8720 | } | |
8721 | ||
8722 | /// Zip vectors | |
8723 | #[inline] | |
8724 | #[target_feature(enable = "neon")] | |
8725 | #[cfg_attr(test, assert_instr(zip1))] | |
8726 | pub unsafe fn vzip1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { | |
8727 | simd_shuffle4!(a, b, [0, 4, 1, 5]) | |
8728 | } | |
8729 | ||
8730 | /// Zip vectors | |
8731 | #[inline] | |
8732 | #[target_feature(enable = "neon")] | |
8733 | #[cfg_attr(test, assert_instr(zip1))] | |
8734 | pub unsafe fn vzip1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { | |
8735 | simd_shuffle8!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) | |
8736 | } | |
8737 | ||
8738 | /// Zip vectors | |
8739 | #[inline] | |
8740 | #[target_feature(enable = "neon")] | |
8741 | #[cfg_attr(test, assert_instr(zip1))] | |
8742 | pub unsafe fn vzip1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { | |
8743 | simd_shuffle2!(a, b, [0, 2]) | |
8744 | } | |
8745 | ||
8746 | /// Zip vectors | |
8747 | #[inline] | |
8748 | #[target_feature(enable = "neon")] | |
8749 | #[cfg_attr(test, assert_instr(zip1))] | |
8750 | pub unsafe fn vzip1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { | |
8751 | simd_shuffle4!(a, b, [0, 4, 1, 5]) | |
8752 | } | |
8753 | ||
8754 | /// Zip vectors | |
8755 | #[inline] | |
8756 | #[target_feature(enable = "neon")] | |
8757 | #[cfg_attr(test, assert_instr(zip1))] | |
8758 | pub unsafe fn vzip1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
8759 | simd_shuffle2!(a, b, [0, 2]) | |
8760 | } | |
8761 | ||
8762 | /// Zip vectors | |
8763 | #[inline] | |
8764 | #[target_feature(enable = "neon")] | |
8765 | #[cfg_attr(test, assert_instr(zip1))] | |
8766 | pub unsafe fn vzip1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { | |
8767 | simd_shuffle8!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) | |
8768 | } | |
8769 | ||
8770 | /// Zip vectors | |
8771 | #[inline] | |
8772 | #[target_feature(enable = "neon")] | |
8773 | #[cfg_attr(test, assert_instr(zip1))] | |
8774 | pub unsafe fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { | |
8775 | simd_shuffle16!(a, b, [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]) | |
8776 | } | |
8777 | ||
8778 | /// Zip vectors | |
8779 | #[inline] | |
8780 | #[target_feature(enable = "neon")] | |
8781 | #[cfg_attr(test, assert_instr(zip1))] | |
8782 | pub unsafe fn vzip1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { | |
8783 | simd_shuffle4!(a, b, [0, 4, 1, 5]) | |
8784 | } | |
8785 | ||
8786 | /// Zip vectors | |
8787 | #[inline] | |
8788 | #[target_feature(enable = "neon")] | |
8789 | #[cfg_attr(test, assert_instr(zip1))] | |
8790 | pub unsafe fn vzip1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { | |
8791 | simd_shuffle8!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) | |
8792 | } | |
8793 | ||
8794 | /// Zip vectors | |
8795 | #[inline] | |
8796 | #[target_feature(enable = "neon")] | |
8797 | #[cfg_attr(test, assert_instr(zip1))] | |
8798 | pub unsafe fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { | |
8799 | simd_shuffle2!(a, b, [0, 2]) | |
8800 | } | |
8801 | ||
8802 | /// Zip vectors | |
8803 | #[inline] | |
8804 | #[target_feature(enable = "neon")] | |
8805 | #[cfg_attr(test, assert_instr(zip1))] | |
8806 | pub unsafe fn vzip1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
8807 | simd_shuffle2!(a, b, [0, 2]) | |
8808 | } | |
8809 | ||
8810 | /// Zip vectors | |
8811 | #[inline] | |
8812 | #[target_feature(enable = "neon")] | |
8813 | #[cfg_attr(test, assert_instr(zip1))] | |
8814 | pub unsafe fn vzip1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
8815 | simd_shuffle4!(a, b, [0, 4, 1, 5]) | |
8816 | } | |
8817 | ||
8818 | /// Zip vectors | |
8819 | #[inline] | |
8820 | #[target_feature(enable = "neon")] | |
8821 | #[cfg_attr(test, assert_instr(zip1))] | |
8822 | pub unsafe fn vzip1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
8823 | simd_shuffle2!(a, b, [0, 2]) | |
8824 | } | |
8825 | ||
8826 | /// Zip vectors | |
8827 | #[inline] | |
8828 | #[target_feature(enable = "neon")] | |
8829 | #[cfg_attr(test, assert_instr(zip2))] | |
8830 | pub unsafe fn vzip2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { | |
8831 | simd_shuffle8!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) | |
8832 | } | |
8833 | ||
8834 | /// Zip vectors | |
8835 | #[inline] | |
8836 | #[target_feature(enable = "neon")] | |
8837 | #[cfg_attr(test, assert_instr(zip2))] | |
8838 | pub unsafe fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { | |
8839 | simd_shuffle16!(a, b, [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]) | |
8840 | } | |
8841 | ||
8842 | /// Zip vectors | |
8843 | #[inline] | |
8844 | #[target_feature(enable = "neon")] | |
8845 | #[cfg_attr(test, assert_instr(zip2))] | |
8846 | pub unsafe fn vzip2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { | |
8847 | simd_shuffle4!(a, b, [2, 6, 3, 7]) | |
8848 | } | |
8849 | ||
8850 | /// Zip vectors | |
8851 | #[inline] | |
8852 | #[target_feature(enable = "neon")] | |
8853 | #[cfg_attr(test, assert_instr(zip2))] | |
8854 | pub unsafe fn vzip2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { | |
8855 | simd_shuffle8!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) | |
8856 | } | |
8857 | ||
8858 | /// Zip vectors | |
8859 | #[inline] | |
8860 | #[target_feature(enable = "neon")] | |
8861 | #[cfg_attr(test, assert_instr(zip2))] | |
8862 | pub unsafe fn vzip2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { | |
8863 | simd_shuffle2!(a, b, [1, 3]) | |
8864 | } | |
8865 | ||
8866 | /// Zip vectors | |
8867 | #[inline] | |
8868 | #[target_feature(enable = "neon")] | |
8869 | #[cfg_attr(test, assert_instr(zip2))] | |
8870 | pub unsafe fn vzip2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { | |
8871 | simd_shuffle4!(a, b, [2, 6, 3, 7]) | |
8872 | } | |
8873 | ||
8874 | /// Zip vectors | |
8875 | #[inline] | |
8876 | #[target_feature(enable = "neon")] | |
8877 | #[cfg_attr(test, assert_instr(zip2))] | |
8878 | pub unsafe fn vzip2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { | |
8879 | simd_shuffle2!(a, b, [1, 3]) | |
8880 | } | |
8881 | ||
8882 | /// Zip vectors | |
8883 | #[inline] | |
8884 | #[target_feature(enable = "neon")] | |
8885 | #[cfg_attr(test, assert_instr(zip2))] | |
8886 | pub unsafe fn vzip2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { | |
8887 | simd_shuffle8!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) | |
8888 | } | |
8889 | ||
8890 | /// Zip vectors | |
8891 | #[inline] | |
8892 | #[target_feature(enable = "neon")] | |
8893 | #[cfg_attr(test, assert_instr(zip2))] | |
8894 | pub unsafe fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { | |
8895 | simd_shuffle16!(a, b, [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]) | |
8896 | } | |
8897 | ||
8898 | /// Zip vectors | |
8899 | #[inline] | |
8900 | #[target_feature(enable = "neon")] | |
8901 | #[cfg_attr(test, assert_instr(zip2))] | |
8902 | pub unsafe fn vzip2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { | |
8903 | simd_shuffle4!(a, b, [2, 6, 3, 7]) | |
8904 | } | |
8905 | ||
8906 | /// Zip vectors | |
8907 | #[inline] | |
8908 | #[target_feature(enable = "neon")] | |
8909 | #[cfg_attr(test, assert_instr(zip2))] | |
8910 | pub unsafe fn vzip2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { | |
8911 | simd_shuffle8!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) | |
8912 | } | |
8913 | ||
8914 | /// Zip vectors | |
8915 | #[inline] | |
8916 | #[target_feature(enable = "neon")] | |
8917 | #[cfg_attr(test, assert_instr(zip2))] | |
8918 | pub unsafe fn vzip2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { | |
8919 | simd_shuffle2!(a, b, [1, 3]) | |
8920 | } | |
8921 | ||
8922 | /// Zip vectors | |
8923 | #[inline] | |
8924 | #[target_feature(enable = "neon")] | |
8925 | #[cfg_attr(test, assert_instr(zip2))] | |
8926 | pub unsafe fn vzip2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { | |
8927 | simd_shuffle4!(a, b, [2, 6, 3, 7]) | |
8928 | } | |
8929 | ||
8930 | /// Zip vectors | |
8931 | #[inline] | |
8932 | #[target_feature(enable = "neon")] | |
8933 | #[cfg_attr(test, assert_instr(zip2))] | |
8934 | pub unsafe fn vzip2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
8935 | simd_shuffle2!(a, b, [1, 3]) | |
8936 | } | |
8937 | ||
8938 | /// Zip vectors | |
8939 | #[inline] | |
8940 | #[target_feature(enable = "neon")] | |
8941 | #[cfg_attr(test, assert_instr(zip2))] | |
8942 | pub unsafe fn vzip2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { | |
8943 | simd_shuffle8!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) | |
8944 | } | |
8945 | ||
8946 | /// Zip vectors | |
8947 | #[inline] | |
8948 | #[target_feature(enable = "neon")] | |
8949 | #[cfg_attr(test, assert_instr(zip2))] | |
8950 | pub unsafe fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { | |
8951 | simd_shuffle16!(a, b, [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]) | |
8952 | } | |
8953 | ||
8954 | /// Zip vectors | |
8955 | #[inline] | |
8956 | #[target_feature(enable = "neon")] | |
8957 | #[cfg_attr(test, assert_instr(zip2))] | |
8958 | pub unsafe fn vzip2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { | |
8959 | simd_shuffle4!(a, b, [2, 6, 3, 7]) | |
8960 | } | |
8961 | ||
8962 | /// Zip vectors | |
8963 | #[inline] | |
8964 | #[target_feature(enable = "neon")] | |
8965 | #[cfg_attr(test, assert_instr(zip2))] | |
8966 | pub unsafe fn vzip2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { | |
8967 | simd_shuffle8!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) | |
8968 | } | |
8969 | ||
8970 | /// Zip vectors | |
8971 | #[inline] | |
8972 | #[target_feature(enable = "neon")] | |
8973 | #[cfg_attr(test, assert_instr(zip2))] | |
8974 | pub unsafe fn vzip2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { | |
8975 | simd_shuffle2!(a, b, [1, 3]) | |
8976 | } | |
8977 | ||
8978 | /// Zip vectors | |
8979 | #[inline] | |
8980 | #[target_feature(enable = "neon")] | |
8981 | #[cfg_attr(test, assert_instr(zip2))] | |
8982 | pub unsafe fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
8983 | simd_shuffle2!(a, b, [1, 3]) | |
8984 | } | |
8985 | ||
8986 | /// Zip vectors | |
8987 | #[inline] | |
8988 | #[target_feature(enable = "neon")] | |
8989 | #[cfg_attr(test, assert_instr(zip2))] | |
8990 | pub unsafe fn vzip2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
8991 | simd_shuffle4!(a, b, [2, 6, 3, 7]) | |
8992 | } | |
8993 | ||
8994 | /// Zip vectors | |
8995 | #[inline] | |
8996 | #[target_feature(enable = "neon")] | |
8997 | #[cfg_attr(test, assert_instr(zip2))] | |
8998 | pub unsafe fn vzip2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
8999 | simd_shuffle2!(a, b, [1, 3]) | |
9000 | } | |
9001 | ||
9002 | /// Unzip vectors | |
9003 | #[inline] | |
9004 | #[target_feature(enable = "neon")] | |
9005 | #[cfg_attr(test, assert_instr(uzp1))] | |
9006 | pub unsafe fn vuzp1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { | |
9007 | simd_shuffle8!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) | |
9008 | } | |
9009 | ||
9010 | /// Unzip vectors | |
9011 | #[inline] | |
9012 | #[target_feature(enable = "neon")] | |
9013 | #[cfg_attr(test, assert_instr(uzp1))] | |
9014 | pub unsafe fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { | |
9015 | simd_shuffle16!(a, b, [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]) | |
9016 | } | |
9017 | ||
9018 | /// Unzip vectors | |
9019 | #[inline] | |
9020 | #[target_feature(enable = "neon")] | |
9021 | #[cfg_attr(test, assert_instr(uzp1))] | |
9022 | pub unsafe fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { | |
9023 | simd_shuffle4!(a, b, [0, 2, 4, 6]) | |
9024 | } | |
9025 | ||
9026 | /// Unzip vectors | |
9027 | #[inline] | |
9028 | #[target_feature(enable = "neon")] | |
9029 | #[cfg_attr(test, assert_instr(uzp1))] | |
9030 | pub unsafe fn vuzp1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { | |
9031 | simd_shuffle8!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) | |
9032 | } | |
9033 | ||
9034 | /// Unzip vectors | |
9035 | #[inline] | |
9036 | #[target_feature(enable = "neon")] | |
9037 | #[cfg_attr(test, assert_instr(uzp1))] | |
9038 | pub unsafe fn vuzp1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { | |
9039 | simd_shuffle4!(a, b, [0, 2, 4, 6]) | |
9040 | } | |
9041 | ||
9042 | /// Unzip vectors | |
9043 | #[inline] | |
9044 | #[target_feature(enable = "neon")] | |
9045 | #[cfg_attr(test, assert_instr(uzp1))] | |
9046 | pub unsafe fn vuzp1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { | |
9047 | simd_shuffle8!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) | |
9048 | } | |
9049 | ||
9050 | /// Unzip vectors | |
9051 | #[inline] | |
9052 | #[target_feature(enable = "neon")] | |
9053 | #[cfg_attr(test, assert_instr(uzp1))] | |
9054 | pub unsafe fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { | |
9055 | simd_shuffle16!(a, b, [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]) | |
9056 | } | |
9057 | ||
9058 | /// Unzip vectors | |
9059 | #[inline] | |
9060 | #[target_feature(enable = "neon")] | |
9061 | #[cfg_attr(test, assert_instr(uzp1))] | |
9062 | pub unsafe fn vuzp1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { | |
9063 | simd_shuffle4!(a, b, [0, 2, 4, 6]) | |
9064 | } | |
9065 | ||
9066 | /// Unzip vectors | |
9067 | #[inline] | |
9068 | #[target_feature(enable = "neon")] | |
9069 | #[cfg_attr(test, assert_instr(uzp1))] | |
9070 | pub unsafe fn vuzp1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { | |
9071 | simd_shuffle8!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) | |
9072 | } | |
9073 | ||
9074 | /// Unzip vectors | |
9075 | #[inline] | |
9076 | #[target_feature(enable = "neon")] | |
9077 | #[cfg_attr(test, assert_instr(uzp1))] | |
9078 | pub unsafe fn vuzp1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { | |
9079 | simd_shuffle4!(a, b, [0, 2, 4, 6]) | |
9080 | } | |
9081 | ||
9082 | /// Unzip vectors | |
9083 | #[inline] | |
9084 | #[target_feature(enable = "neon")] | |
9085 | #[cfg_attr(test, assert_instr(uzp1))] | |
9086 | pub unsafe fn vuzp1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { | |
9087 | simd_shuffle8!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) | |
9088 | } | |
9089 | ||
9090 | /// Unzip vectors | |
9091 | #[inline] | |
9092 | #[target_feature(enable = "neon")] | |
9093 | #[cfg_attr(test, assert_instr(uzp1))] | |
9094 | pub unsafe fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { | |
9095 | simd_shuffle16!(a, b, [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]) | |
9096 | } | |
9097 | ||
9098 | /// Unzip vectors | |
9099 | #[inline] | |
9100 | #[target_feature(enable = "neon")] | |
9101 | #[cfg_attr(test, assert_instr(uzp1))] | |
9102 | pub unsafe fn vuzp1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { | |
9103 | simd_shuffle4!(a, b, [0, 2, 4, 6]) | |
9104 | } | |
9105 | ||
9106 | /// Unzip vectors | |
9107 | #[inline] | |
9108 | #[target_feature(enable = "neon")] | |
9109 | #[cfg_attr(test, assert_instr(uzp1))] | |
9110 | pub unsafe fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { | |
9111 | simd_shuffle8!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) | |
9112 | } | |
9113 | ||
9114 | /// Unzip vectors | |
9115 | #[inline] | |
9116 | #[target_feature(enable = "neon")] | |
9117 | #[cfg_attr(test, assert_instr(zip1))] | |
9118 | pub unsafe fn vuzp1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { | |
9119 | simd_shuffle2!(a, b, [0, 2]) | |
9120 | } | |
9121 | ||
9122 | /// Unzip vectors | |
9123 | #[inline] | |
9124 | #[target_feature(enable = "neon")] | |
9125 | #[cfg_attr(test, assert_instr(zip1))] | |
9126 | pub unsafe fn vuzp1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { | |
9127 | simd_shuffle2!(a, b, [0, 2]) | |
9128 | } | |
9129 | ||
9130 | /// Unzip vectors | |
9131 | #[inline] | |
9132 | #[target_feature(enable = "neon")] | |
9133 | #[cfg_attr(test, assert_instr(zip1))] | |
9134 | pub unsafe fn vuzp1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { | |
9135 | simd_shuffle2!(a, b, [0, 2]) | |
9136 | } | |
9137 | ||
9138 | /// Unzip vectors | |
9139 | #[inline] | |
9140 | #[target_feature(enable = "neon")] | |
9141 | #[cfg_attr(test, assert_instr(zip1))] | |
9142 | pub unsafe fn vuzp1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
9143 | simd_shuffle2!(a, b, [0, 2]) | |
9144 | } | |
9145 | ||
9146 | /// Unzip vectors | |
9147 | #[inline] | |
9148 | #[target_feature(enable = "neon")] | |
9149 | #[cfg_attr(test, assert_instr(zip1))] | |
9150 | pub unsafe fn vuzp1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { | |
9151 | simd_shuffle2!(a, b, [0, 2]) | |
9152 | } | |
9153 | ||
9154 | /// Unzip vectors | |
9155 | #[inline] | |
9156 | #[target_feature(enable = "neon")] | |
9157 | #[cfg_attr(test, assert_instr(uzp1))] | |
9158 | pub unsafe fn vuzp1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
9159 | simd_shuffle4!(a, b, [0, 2, 4, 6]) | |
9160 | } | |
9161 | ||
9162 | /// Unzip vectors | |
9163 | #[inline] | |
9164 | #[target_feature(enable = "neon")] | |
9165 | #[cfg_attr(test, assert_instr(zip1))] | |
9166 | pub unsafe fn vuzp1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
9167 | simd_shuffle2!(a, b, [0, 2]) | |
9168 | } | |
9169 | ||
9170 | /// Unzip vectors | |
9171 | #[inline] | |
9172 | #[target_feature(enable = "neon")] | |
9173 | #[cfg_attr(test, assert_instr(zip1))] | |
9174 | pub unsafe fn vuzp1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
9175 | simd_shuffle2!(a, b, [0, 2]) | |
9176 | } | |
9177 | ||
9178 | /// Unzip vectors | |
9179 | #[inline] | |
9180 | #[target_feature(enable = "neon")] | |
9181 | #[cfg_attr(test, assert_instr(uzp2))] | |
9182 | pub unsafe fn vuzp2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { | |
9183 | simd_shuffle8!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) | |
9184 | } | |
9185 | ||
9186 | /// Unzip vectors | |
9187 | #[inline] | |
9188 | #[target_feature(enable = "neon")] | |
9189 | #[cfg_attr(test, assert_instr(uzp2))] | |
9190 | pub unsafe fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { | |
9191 | simd_shuffle16!(a, b, [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]) | |
9192 | } | |
9193 | ||
9194 | /// Unzip vectors | |
9195 | #[inline] | |
9196 | #[target_feature(enable = "neon")] | |
9197 | #[cfg_attr(test, assert_instr(uzp2))] | |
9198 | pub unsafe fn vuzp2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { | |
9199 | simd_shuffle4!(a, b, [1, 3, 5, 7]) | |
9200 | } | |
9201 | ||
9202 | /// Unzip vectors | |
9203 | #[inline] | |
9204 | #[target_feature(enable = "neon")] | |
9205 | #[cfg_attr(test, assert_instr(uzp2))] | |
9206 | pub unsafe fn vuzp2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { | |
9207 | simd_shuffle8!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) | |
9208 | } | |
9209 | ||
9210 | /// Unzip vectors | |
9211 | #[inline] | |
9212 | #[target_feature(enable = "neon")] | |
9213 | #[cfg_attr(test, assert_instr(uzp2))] | |
9214 | pub unsafe fn vuzp2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { | |
9215 | simd_shuffle4!(a, b, [1, 3, 5, 7]) | |
9216 | } | |
9217 | ||
9218 | /// Unzip vectors | |
9219 | #[inline] | |
9220 | #[target_feature(enable = "neon")] | |
9221 | #[cfg_attr(test, assert_instr(uzp2))] | |
9222 | pub unsafe fn vuzp2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { | |
9223 | simd_shuffle8!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) | |
9224 | } | |
9225 | ||
9226 | /// Unzip vectors | |
9227 | #[inline] | |
9228 | #[target_feature(enable = "neon")] | |
9229 | #[cfg_attr(test, assert_instr(uzp2))] | |
9230 | pub unsafe fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { | |
9231 | simd_shuffle16!(a, b, [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]) | |
9232 | } | |
9233 | ||
9234 | /// Unzip vectors | |
9235 | #[inline] | |
9236 | #[target_feature(enable = "neon")] | |
9237 | #[cfg_attr(test, assert_instr(uzp2))] | |
9238 | pub unsafe fn vuzp2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { | |
9239 | simd_shuffle4!(a, b, [1, 3, 5, 7]) | |
9240 | } | |
9241 | ||
9242 | /// Unzip vectors | |
9243 | #[inline] | |
9244 | #[target_feature(enable = "neon")] | |
9245 | #[cfg_attr(test, assert_instr(uzp2))] | |
9246 | pub unsafe fn vuzp2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { | |
9247 | simd_shuffle8!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) | |
9248 | } | |
9249 | ||
9250 | /// Unzip vectors | |
9251 | #[inline] | |
9252 | #[target_feature(enable = "neon")] | |
9253 | #[cfg_attr(test, assert_instr(uzp2))] | |
9254 | pub unsafe fn vuzp2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { | |
9255 | simd_shuffle4!(a, b, [1, 3, 5, 7]) | |
9256 | } | |
9257 | ||
9258 | /// Unzip vectors | |
9259 | #[inline] | |
9260 | #[target_feature(enable = "neon")] | |
9261 | #[cfg_attr(test, assert_instr(uzp2))] | |
9262 | pub unsafe fn vuzp2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { | |
9263 | simd_shuffle8!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) | |
9264 | } | |
9265 | ||
9266 | /// Unzip vectors | |
9267 | #[inline] | |
9268 | #[target_feature(enable = "neon")] | |
9269 | #[cfg_attr(test, assert_instr(uzp2))] | |
9270 | pub unsafe fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { | |
9271 | simd_shuffle16!(a, b, [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]) | |
9272 | } | |
9273 | ||
9274 | /// Unzip vectors | |
9275 | #[inline] | |
9276 | #[target_feature(enable = "neon")] | |
9277 | #[cfg_attr(test, assert_instr(uzp2))] | |
9278 | pub unsafe fn vuzp2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { | |
9279 | simd_shuffle4!(a, b, [1, 3, 5, 7]) | |
9280 | } | |
9281 | ||
9282 | /// Unzip vectors | |
9283 | #[inline] | |
9284 | #[target_feature(enable = "neon")] | |
9285 | #[cfg_attr(test, assert_instr(uzp2))] | |
9286 | pub unsafe fn vuzp2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { | |
9287 | simd_shuffle8!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) | |
9288 | } | |
9289 | ||
9290 | /// Unzip vectors | |
9291 | #[inline] | |
9292 | #[target_feature(enable = "neon")] | |
9293 | #[cfg_attr(test, assert_instr(zip2))] | |
9294 | pub unsafe fn vuzp2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { | |
9295 | simd_shuffle2!(a, b, [1, 3]) | |
9296 | } | |
9297 | ||
9298 | /// Unzip vectors | |
9299 | #[inline] | |
9300 | #[target_feature(enable = "neon")] | |
9301 | #[cfg_attr(test, assert_instr(zip2))] | |
9302 | pub unsafe fn vuzp2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { | |
9303 | simd_shuffle2!(a, b, [1, 3]) | |
9304 | } | |
9305 | ||
9306 | /// Unzip vectors | |
9307 | #[inline] | |
9308 | #[target_feature(enable = "neon")] | |
9309 | #[cfg_attr(test, assert_instr(zip2))] | |
9310 | pub unsafe fn vuzp2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { | |
9311 | simd_shuffle2!(a, b, [1, 3]) | |
9312 | } | |
9313 | ||
9314 | /// Unzip vectors | |
9315 | #[inline] | |
9316 | #[target_feature(enable = "neon")] | |
9317 | #[cfg_attr(test, assert_instr(zip2))] | |
9318 | pub unsafe fn vuzp2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
9319 | simd_shuffle2!(a, b, [1, 3]) | |
9320 | } | |
9321 | ||
9322 | /// Unzip vectors | |
9323 | #[inline] | |
9324 | #[target_feature(enable = "neon")] | |
9325 | #[cfg_attr(test, assert_instr(zip2))] | |
9326 | pub unsafe fn vuzp2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { | |
9327 | simd_shuffle2!(a, b, [1, 3]) | |
9328 | } | |
9329 | ||
9330 | /// Unzip vectors | |
9331 | #[inline] | |
9332 | #[target_feature(enable = "neon")] | |
9333 | #[cfg_attr(test, assert_instr(uzp2))] | |
9334 | pub unsafe fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
9335 | simd_shuffle4!(a, b, [1, 3, 5, 7]) | |
9336 | } | |
9337 | ||
9338 | /// Unzip vectors | |
9339 | #[inline] | |
9340 | #[target_feature(enable = "neon")] | |
9341 | #[cfg_attr(test, assert_instr(zip2))] | |
9342 | pub unsafe fn vuzp2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
9343 | simd_shuffle2!(a, b, [1, 3]) | |
9344 | } | |
9345 | ||
9346 | /// Unzip vectors | |
9347 | #[inline] | |
9348 | #[target_feature(enable = "neon")] | |
9349 | #[cfg_attr(test, assert_instr(zip2))] | |
9350 | pub unsafe fn vuzp2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
9351 | simd_shuffle2!(a, b, [1, 3]) | |
9352 | } | |
9353 | ||
9354 | /// Unsigned Absolute difference and Accumulate Long | |
9355 | #[inline] | |
9356 | #[target_feature(enable = "neon")] | |
9357 | #[cfg_attr(test, assert_instr(uabal))] | |
9358 | pub unsafe fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { | |
9359 | let d: uint8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
9360 | let e: uint8x8_t = simd_shuffle8!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); | |
9361 | let f: uint8x8_t = vabd_u8(d, e); | |
9362 | simd_add(a, simd_cast(f)) | |
9363 | } | |
9364 | ||
9365 | /// Unsigned Absolute difference and Accumulate Long | |
9366 | #[inline] | |
9367 | #[target_feature(enable = "neon")] | |
9368 | #[cfg_attr(test, assert_instr(uabal))] | |
9369 | pub unsafe fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { | |
9370 | let d: uint16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
9371 | let e: uint16x4_t = simd_shuffle4!(c, c, [4, 5, 6, 7]); | |
9372 | let f: uint16x4_t = vabd_u16(d, e); | |
9373 | simd_add(a, simd_cast(f)) | |
9374 | } | |
9375 | ||
9376 | /// Unsigned Absolute difference and Accumulate Long | |
9377 | #[inline] | |
9378 | #[target_feature(enable = "neon")] | |
9379 | #[cfg_attr(test, assert_instr(uabal))] | |
9380 | pub unsafe fn vabal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { | |
9381 | let d: uint32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
9382 | let e: uint32x2_t = simd_shuffle2!(c, c, [2, 3]); | |
9383 | let f: uint32x2_t = vabd_u32(d, e); | |
9384 | simd_add(a, simd_cast(f)) | |
9385 | } | |
9386 | ||
9387 | /// Signed Absolute difference and Accumulate Long | |
9388 | #[inline] | |
9389 | #[target_feature(enable = "neon")] | |
9390 | #[cfg_attr(test, assert_instr(sabal))] | |
9391 | pub unsafe fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { | |
9392 | let d: int8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
9393 | let e: int8x8_t = simd_shuffle8!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); | |
9394 | let f: int8x8_t = vabd_s8(d, e); | |
9395 | let f: uint8x8_t = simd_cast(f); | |
9396 | simd_add(a, simd_cast(f)) | |
9397 | } | |
9398 | ||
9399 | /// Signed Absolute difference and Accumulate Long | |
9400 | #[inline] | |
9401 | #[target_feature(enable = "neon")] | |
9402 | #[cfg_attr(test, assert_instr(sabal))] | |
9403 | pub unsafe fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { | |
9404 | let d: int16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
9405 | let e: int16x4_t = simd_shuffle4!(c, c, [4, 5, 6, 7]); | |
9406 | let f: int16x4_t = vabd_s16(d, e); | |
9407 | let f: uint16x4_t = simd_cast(f); | |
9408 | simd_add(a, simd_cast(f)) | |
9409 | } | |
9410 | ||
9411 | /// Signed Absolute difference and Accumulate Long | |
9412 | #[inline] | |
9413 | #[target_feature(enable = "neon")] | |
9414 | #[cfg_attr(test, assert_instr(sabal))] | |
9415 | pub unsafe fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { | |
9416 | let d: int32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
9417 | let e: int32x2_t = simd_shuffle2!(c, c, [2, 3]); | |
9418 | let f: int32x2_t = vabd_s32(d, e); | |
9419 | let f: uint32x2_t = simd_cast(f); | |
9420 | simd_add(a, simd_cast(f)) | |
9421 | } | |
9422 | ||
9423 | /// Singned saturating Absolute value | |
9424 | #[inline] | |
9425 | #[target_feature(enable = "neon")] | |
9426 | #[cfg_attr(test, assert_instr(sqabs))] | |
9427 | pub unsafe fn vqabs_s64(a: int64x1_t) -> int64x1_t { | |
9428 | #[allow(improper_ctypes)] | |
9429 | extern "C" { | |
9430 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqabs.v1i64")] | |
9431 | fn vqabs_s64_(a: int64x1_t) -> int64x1_t; | |
9432 | } | |
9433 | vqabs_s64_(a) | |
9434 | } | |
9435 | ||
9436 | /// Singned saturating Absolute value | |
9437 | #[inline] | |
9438 | #[target_feature(enable = "neon")] | |
9439 | #[cfg_attr(test, assert_instr(sqabs))] | |
9440 | pub unsafe fn vqabsq_s64(a: int64x2_t) -> int64x2_t { | |
9441 | #[allow(improper_ctypes)] | |
9442 | extern "C" { | |
9443 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqabs.v2i64")] | |
9444 | fn vqabsq_s64_(a: int64x2_t) -> int64x2_t; | |
9445 | } | |
9446 | vqabsq_s64_(a) | |
9447 | } | |
9448 | ||
9449 | #[cfg(test)] | |
9450 | mod test { | |
9451 | use super::*; | |
9452 | use crate::core_arch::simd::*; | |
9453 | use std::mem::transmute; | |
9454 | use stdarch_test::simd_test; | |
9455 | ||
9456 | #[simd_test(enable = "neon")] | |
9457 | unsafe fn test_vabd_f64() { | |
9458 | let a: f64 = 1.0; | |
9459 | let b: f64 = 9.0; | |
9460 | let e: f64 = 8.0; | |
9461 | let r: f64 = transmute(vabd_f64(transmute(a), transmute(b))); | |
9462 | assert_eq!(r, e); | |
9463 | } | |
9464 | ||
9465 | #[simd_test(enable = "neon")] | |
9466 | unsafe fn test_vabdq_f64() { | |
9467 | let a: f64x2 = f64x2::new(1.0, 2.0); | |
9468 | let b: f64x2 = f64x2::new(9.0, 3.0); | |
9469 | let e: f64x2 = f64x2::new(8.0, 1.0); | |
9470 | let r: f64x2 = transmute(vabdq_f64(transmute(a), transmute(b))); | |
9471 | assert_eq!(r, e); | |
9472 | } | |
9473 | ||
9474 | #[simd_test(enable = "neon")] | |
9475 | unsafe fn test_vabdl_high_u8() { | |
9476 | let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
9477 | let b: u8x16 = u8x16::new(10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10); | |
9478 | let e: u16x8 = u16x8::new(1, 0, 1, 2, 3, 4, 5, 6); | |
9479 | let r: u16x8 = transmute(vabdl_high_u8(transmute(a), transmute(b))); | |
9480 | assert_eq!(r, e); | |
9481 | } | |
9482 | ||
9483 | #[simd_test(enable = "neon")] | |
9484 | unsafe fn test_vabdl_high_u16() { | |
9485 | let a: u16x8 = u16x8::new(1, 2, 3, 4, 8, 9, 11, 12); | |
9486 | let b: u16x8 = u16x8::new(10, 10, 10, 10, 10, 10, 10, 10); | |
9487 | let e: u32x4 = u32x4::new(2, 1, 1, 2); | |
9488 | let r: u32x4 = transmute(vabdl_high_u16(transmute(a), transmute(b))); | |
9489 | assert_eq!(r, e); | |
9490 | } | |
9491 | ||
9492 | #[simd_test(enable = "neon")] | |
9493 | unsafe fn test_vabdl_high_u32() { | |
9494 | let a: u32x4 = u32x4::new(1, 2, 3, 4); | |
9495 | let b: u32x4 = u32x4::new(10, 10, 10, 10); | |
9496 | let e: u64x2 = u64x2::new(7, 6); | |
9497 | let r: u64x2 = transmute(vabdl_high_u32(transmute(a), transmute(b))); | |
9498 | assert_eq!(r, e); | |
9499 | } | |
9500 | ||
9501 | #[simd_test(enable = "neon")] | |
9502 | unsafe fn test_vabdl_high_s8() { | |
9503 | let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
9504 | let b: i8x16 = i8x16::new(10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10); | |
9505 | let e: i16x8 = i16x8::new(1, 0, 1, 2, 3, 4, 5, 6); | |
9506 | let r: i16x8 = transmute(vabdl_high_s8(transmute(a), transmute(b))); | |
9507 | assert_eq!(r, e); | |
9508 | } | |
9509 | ||
9510 | #[simd_test(enable = "neon")] | |
9511 | unsafe fn test_vabdl_high_s16() { | |
9512 | let a: i16x8 = i16x8::new(1, 2, 3, 4, 9, 10, 11, 12); | |
9513 | let b: i16x8 = i16x8::new(10, 10, 10, 10, 10, 10, 10, 10); | |
9514 | let e: i32x4 = i32x4::new(1, 0, 1, 2); | |
9515 | let r: i32x4 = transmute(vabdl_high_s16(transmute(a), transmute(b))); | |
9516 | assert_eq!(r, e); | |
9517 | } | |
9518 | ||
9519 | #[simd_test(enable = "neon")] | |
9520 | unsafe fn test_vabdl_high_s32() { | |
9521 | let a: i32x4 = i32x4::new(1, 2, 3, 4); | |
9522 | let b: i32x4 = i32x4::new(10, 10, 10, 10); | |
9523 | let e: i64x2 = i64x2::new(7, 6); | |
9524 | let r: i64x2 = transmute(vabdl_high_s32(transmute(a), transmute(b))); | |
9525 | assert_eq!(r, e); | |
9526 | } | |
9527 | ||
9528 | #[simd_test(enable = "neon")] | |
9529 | unsafe fn test_vceq_u64() { | |
9530 | let a: u64x1 = u64x1::new(0); | |
9531 | let b: u64x1 = u64x1::new(0); | |
9532 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9533 | let r: u64x1 = transmute(vceq_u64(transmute(a), transmute(b))); | |
9534 | assert_eq!(r, e); | |
9535 | ||
9536 | let a: u64x1 = u64x1::new(0); | |
9537 | let b: u64x1 = u64x1::new(0); | |
9538 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9539 | let r: u64x1 = transmute(vceq_u64(transmute(a), transmute(b))); | |
9540 | assert_eq!(r, e); | |
9541 | } | |
9542 | ||
9543 | #[simd_test(enable = "neon")] | |
9544 | unsafe fn test_vceqq_u64() { | |
9545 | let a: u64x2 = u64x2::new(0, 0x01); | |
9546 | let b: u64x2 = u64x2::new(0, 0x01); | |
9547 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9548 | let r: u64x2 = transmute(vceqq_u64(transmute(a), transmute(b))); | |
9549 | assert_eq!(r, e); | |
9550 | ||
9551 | let a: u64x2 = u64x2::new(0, 0); | |
9552 | let b: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9553 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); | |
9554 | let r: u64x2 = transmute(vceqq_u64(transmute(a), transmute(b))); | |
9555 | assert_eq!(r, e); | |
9556 | } | |
9557 | ||
9558 | #[simd_test(enable = "neon")] | |
9559 | unsafe fn test_vceq_s64() { | |
9560 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
9561 | let b: i64x1 = i64x1::new(-9223372036854775808); | |
9562 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9563 | let r: u64x1 = transmute(vceq_s64(transmute(a), transmute(b))); | |
9564 | assert_eq!(r, e); | |
9565 | ||
9566 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
9567 | let b: i64x1 = i64x1::new(-9223372036854775808); | |
9568 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9569 | let r: u64x1 = transmute(vceq_s64(transmute(a), transmute(b))); | |
9570 | assert_eq!(r, e); | |
9571 | } | |
9572 | ||
9573 | #[simd_test(enable = "neon")] | |
9574 | unsafe fn test_vceqq_s64() { | |
9575 | let a: i64x2 = i64x2::new(-9223372036854775808, 0x01); | |
9576 | let b: i64x2 = i64x2::new(-9223372036854775808, 0x01); | |
9577 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9578 | let r: u64x2 = transmute(vceqq_s64(transmute(a), transmute(b))); | |
9579 | assert_eq!(r, e); | |
9580 | ||
9581 | let a: i64x2 = i64x2::new(-9223372036854775808, -9223372036854775808); | |
9582 | let b: i64x2 = i64x2::new(-9223372036854775808, 0x7F_FF_FF_FF_FF_FF_FF_FF); | |
9583 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); | |
9584 | let r: u64x2 = transmute(vceqq_s64(transmute(a), transmute(b))); | |
9585 | assert_eq!(r, e); | |
9586 | } | |
9587 | ||
9588 | #[simd_test(enable = "neon")] | |
9589 | unsafe fn test_vceq_p64() { | |
9590 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
9591 | let b: i64x1 = i64x1::new(-9223372036854775808); | |
9592 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9593 | let r: u64x1 = transmute(vceq_p64(transmute(a), transmute(b))); | |
9594 | assert_eq!(r, e); | |
9595 | ||
9596 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
9597 | let b: i64x1 = i64x1::new(-9223372036854775808); | |
9598 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9599 | let r: u64x1 = transmute(vceq_p64(transmute(a), transmute(b))); | |
9600 | assert_eq!(r, e); | |
9601 | } | |
9602 | ||
9603 | #[simd_test(enable = "neon")] | |
9604 | unsafe fn test_vceqq_p64() { | |
9605 | let a: i64x2 = i64x2::new(-9223372036854775808, 0x01); | |
9606 | let b: i64x2 = i64x2::new(-9223372036854775808, 0x01); | |
9607 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9608 | let r: u64x2 = transmute(vceqq_p64(transmute(a), transmute(b))); | |
9609 | assert_eq!(r, e); | |
9610 | ||
9611 | let a: i64x2 = i64x2::new(-9223372036854775808, -9223372036854775808); | |
9612 | let b: i64x2 = i64x2::new(-9223372036854775808, 0x7F_FF_FF_FF_FF_FF_FF_FF); | |
9613 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); | |
9614 | let r: u64x2 = transmute(vceqq_p64(transmute(a), transmute(b))); | |
9615 | assert_eq!(r, e); | |
9616 | } | |
9617 | ||
9618 | #[simd_test(enable = "neon")] | |
9619 | unsafe fn test_vceq_f64() { | |
9620 | let a: f64 = 1.2; | |
9621 | let b: f64 = 1.2; | |
9622 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9623 | let r: u64x1 = transmute(vceq_f64(transmute(a), transmute(b))); | |
9624 | assert_eq!(r, e); | |
9625 | } | |
9626 | ||
9627 | #[simd_test(enable = "neon")] | |
9628 | unsafe fn test_vceqq_f64() { | |
9629 | let a: f64x2 = f64x2::new(1.2, 3.4); | |
9630 | let b: f64x2 = f64x2::new(1.2, 3.4); | |
9631 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9632 | let r: u64x2 = transmute(vceqq_f64(transmute(a), transmute(b))); | |
9633 | assert_eq!(r, e); | |
9634 | } | |
9635 | ||
9636 | #[simd_test(enable = "neon")] | |
9637 | unsafe fn test_vceqz_s8() { | |
9638 | let a: i8x8 = i8x8::new(-128, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); | |
9639 | let e: u8x8 = u8x8::new(0, 0xFF, 0, 0, 0, 0, 0, 0); | |
9640 | let r: u8x8 = transmute(vceqz_s8(transmute(a))); | |
9641 | assert_eq!(r, e); | |
9642 | } | |
9643 | ||
9644 | #[simd_test(enable = "neon")] | |
9645 | unsafe fn test_vceqzq_s8() { | |
9646 | let a: i8x16 = i8x16::new(-128, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x7F); | |
9647 | let e: u8x16 = u8x16::new(0, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
9648 | let r: u8x16 = transmute(vceqzq_s8(transmute(a))); | |
9649 | assert_eq!(r, e); | |
9650 | } | |
9651 | ||
9652 | #[simd_test(enable = "neon")] | |
9653 | unsafe fn test_vceqz_s16() { | |
9654 | let a: i16x4 = i16x4::new(-32768, 0x00, 0x01, 0x02); | |
9655 | let e: u16x4 = u16x4::new(0, 0xFF_FF, 0, 0); | |
9656 | let r: u16x4 = transmute(vceqz_s16(transmute(a))); | |
9657 | assert_eq!(r, e); | |
9658 | } | |
9659 | ||
9660 | #[simd_test(enable = "neon")] | |
9661 | unsafe fn test_vceqzq_s16() { | |
9662 | let a: i16x8 = i16x8::new(-32768, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); | |
9663 | let e: u16x8 = u16x8::new(0, 0xFF_FF, 0, 0, 0, 0, 0, 0); | |
9664 | let r: u16x8 = transmute(vceqzq_s16(transmute(a))); | |
9665 | assert_eq!(r, e); | |
9666 | } | |
9667 | ||
9668 | #[simd_test(enable = "neon")] | |
9669 | unsafe fn test_vceqz_s32() { | |
9670 | let a: i32x2 = i32x2::new(-2147483648, 0x00); | |
9671 | let e: u32x2 = u32x2::new(0, 0xFF_FF_FF_FF); | |
9672 | let r: u32x2 = transmute(vceqz_s32(transmute(a))); | |
9673 | assert_eq!(r, e); | |
9674 | } | |
9675 | ||
9676 | #[simd_test(enable = "neon")] | |
9677 | unsafe fn test_vceqzq_s32() { | |
9678 | let a: i32x4 = i32x4::new(-2147483648, 0x00, 0x01, 0x02); | |
9679 | let e: u32x4 = u32x4::new(0, 0xFF_FF_FF_FF, 0, 0); | |
9680 | let r: u32x4 = transmute(vceqzq_s32(transmute(a))); | |
9681 | assert_eq!(r, e); | |
9682 | } | |
9683 | ||
9684 | #[simd_test(enable = "neon")] | |
9685 | unsafe fn test_vceqz_s64() { | |
9686 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
9687 | let e: u64x1 = u64x1::new(0); | |
9688 | let r: u64x1 = transmute(vceqz_s64(transmute(a))); | |
9689 | assert_eq!(r, e); | |
9690 | } | |
9691 | ||
9692 | #[simd_test(enable = "neon")] | |
9693 | unsafe fn test_vceqzq_s64() { | |
9694 | let a: i64x2 = i64x2::new(-9223372036854775808, 0x00); | |
9695 | let e: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9696 | let r: u64x2 = transmute(vceqzq_s64(transmute(a))); | |
9697 | assert_eq!(r, e); | |
9698 | } | |
9699 | ||
9700 | #[simd_test(enable = "neon")] | |
9701 | unsafe fn test_vceqz_p8() { | |
9702 | let a: i8x8 = i8x8::new(-128, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); | |
9703 | let e: u8x8 = u8x8::new(0, 0xFF, 0, 0, 0, 0, 0, 0); | |
9704 | let r: u8x8 = transmute(vceqz_p8(transmute(a))); | |
9705 | assert_eq!(r, e); | |
9706 | } | |
9707 | ||
9708 | #[simd_test(enable = "neon")] | |
9709 | unsafe fn test_vceqzq_p8() { | |
9710 | let a: i8x16 = i8x16::new(-128, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x7F); | |
9711 | let e: u8x16 = u8x16::new(0, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
9712 | let r: u8x16 = transmute(vceqzq_p8(transmute(a))); | |
9713 | assert_eq!(r, e); | |
9714 | } | |
9715 | ||
9716 | #[simd_test(enable = "neon")] | |
9717 | unsafe fn test_vceqz_p64() { | |
9718 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
9719 | let e: u64x1 = u64x1::new(0); | |
9720 | let r: u64x1 = transmute(vceqz_p64(transmute(a))); | |
9721 | assert_eq!(r, e); | |
9722 | } | |
9723 | ||
9724 | #[simd_test(enable = "neon")] | |
9725 | unsafe fn test_vceqzq_p64() { | |
9726 | let a: i64x2 = i64x2::new(-9223372036854775808, 0x00); | |
9727 | let e: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9728 | let r: u64x2 = transmute(vceqzq_p64(transmute(a))); | |
9729 | assert_eq!(r, e); | |
9730 | } | |
9731 | ||
9732 | #[simd_test(enable = "neon")] | |
9733 | unsafe fn test_vceqz_u8() { | |
9734 | let a: u8x8 = u8x8::new(0, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); | |
9735 | let e: u8x8 = u8x8::new(0xFF, 0xFF, 0, 0, 0, 0, 0, 0); | |
9736 | let r: u8x8 = transmute(vceqz_u8(transmute(a))); | |
9737 | assert_eq!(r, e); | |
9738 | } | |
9739 | ||
9740 | #[simd_test(enable = "neon")] | |
9741 | unsafe fn test_vceqzq_u8() { | |
9742 | let a: u8x16 = u8x16::new(0, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0xFF); | |
9743 | let e: u8x16 = u8x16::new(0xFF, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
9744 | let r: u8x16 = transmute(vceqzq_u8(transmute(a))); | |
9745 | assert_eq!(r, e); | |
9746 | } | |
9747 | ||
9748 | #[simd_test(enable = "neon")] | |
9749 | unsafe fn test_vceqz_u16() { | |
9750 | let a: u16x4 = u16x4::new(0, 0x00, 0x01, 0x02); | |
9751 | let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0, 0); | |
9752 | let r: u16x4 = transmute(vceqz_u16(transmute(a))); | |
9753 | assert_eq!(r, e); | |
9754 | } | |
9755 | ||
9756 | #[simd_test(enable = "neon")] | |
9757 | unsafe fn test_vceqzq_u16() { | |
9758 | let a: u16x8 = u16x8::new(0, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); | |
9759 | let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0, 0, 0, 0, 0, 0); | |
9760 | let r: u16x8 = transmute(vceqzq_u16(transmute(a))); | |
9761 | assert_eq!(r, e); | |
9762 | } | |
9763 | ||
9764 | #[simd_test(enable = "neon")] | |
9765 | unsafe fn test_vceqz_u32() { | |
9766 | let a: u32x2 = u32x2::new(0, 0x00); | |
9767 | let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); | |
9768 | let r: u32x2 = transmute(vceqz_u32(transmute(a))); | |
9769 | assert_eq!(r, e); | |
9770 | } | |
9771 | ||
9772 | #[simd_test(enable = "neon")] | |
9773 | unsafe fn test_vceqzq_u32() { | |
9774 | let a: u32x4 = u32x4::new(0, 0x00, 0x01, 0x02); | |
9775 | let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0, 0); | |
9776 | let r: u32x4 = transmute(vceqzq_u32(transmute(a))); | |
9777 | assert_eq!(r, e); | |
9778 | } | |
9779 | ||
9780 | #[simd_test(enable = "neon")] | |
9781 | unsafe fn test_vceqz_u64() { | |
9782 | let a: u64x1 = u64x1::new(0); | |
9783 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9784 | let r: u64x1 = transmute(vceqz_u64(transmute(a))); | |
9785 | assert_eq!(r, e); | |
9786 | } | |
9787 | ||
9788 | #[simd_test(enable = "neon")] | |
9789 | unsafe fn test_vceqzq_u64() { | |
9790 | let a: u64x2 = u64x2::new(0, 0x00); | |
9791 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9792 | let r: u64x2 = transmute(vceqzq_u64(transmute(a))); | |
9793 | assert_eq!(r, e); | |
9794 | } | |
9795 | ||
9796 | #[simd_test(enable = "neon")] | |
9797 | unsafe fn test_vceqz_f32() { | |
9798 | let a: f32x2 = f32x2::new(0.0, 1.2); | |
9799 | let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0); | |
9800 | let r: u32x2 = transmute(vceqz_f32(transmute(a))); | |
9801 | assert_eq!(r, e); | |
9802 | } | |
9803 | ||
9804 | #[simd_test(enable = "neon")] | |
9805 | unsafe fn test_vceqzq_f32() { | |
9806 | let a: f32x4 = f32x4::new(0.0, 1.2, 3.4, 5.6); | |
9807 | let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0, 0, 0); | |
9808 | let r: u32x4 = transmute(vceqzq_f32(transmute(a))); | |
9809 | assert_eq!(r, e); | |
9810 | } | |
9811 | ||
9812 | #[simd_test(enable = "neon")] | |
9813 | unsafe fn test_vceqz_f64() { | |
9814 | let a: f64 = 0.0; | |
9815 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9816 | let r: u64x1 = transmute(vceqz_f64(transmute(a))); | |
9817 | assert_eq!(r, e); | |
9818 | } | |
9819 | ||
9820 | #[simd_test(enable = "neon")] | |
9821 | unsafe fn test_vceqzq_f64() { | |
9822 | let a: f64x2 = f64x2::new(0.0, 1.2); | |
9823 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); | |
9824 | let r: u64x2 = transmute(vceqzq_f64(transmute(a))); | |
9825 | assert_eq!(r, e); | |
9826 | } | |
9827 | ||
9828 | #[simd_test(enable = "neon")] | |
9829 | unsafe fn test_vtst_s64() { | |
9830 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
9831 | let b: i64x1 = i64x1::new(-9223372036854775808); | |
9832 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9833 | let r: u64x1 = transmute(vtst_s64(transmute(a), transmute(b))); | |
9834 | assert_eq!(r, e); | |
9835 | } | |
9836 | ||
9837 | #[simd_test(enable = "neon")] | |
9838 | unsafe fn test_vtstq_s64() { | |
9839 | let a: i64x2 = i64x2::new(-9223372036854775808, 0x00); | |
9840 | let b: i64x2 = i64x2::new(-9223372036854775808, 0x00); | |
9841 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); | |
9842 | let r: u64x2 = transmute(vtstq_s64(transmute(a), transmute(b))); | |
9843 | assert_eq!(r, e); | |
9844 | } | |
9845 | ||
9846 | #[simd_test(enable = "neon")] | |
9847 | unsafe fn test_vtst_p64() { | |
9848 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
9849 | let b: i64x1 = i64x1::new(-9223372036854775808); | |
9850 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9851 | let r: u64x1 = transmute(vtst_p64(transmute(a), transmute(b))); | |
9852 | assert_eq!(r, e); | |
9853 | } | |
9854 | ||
9855 | #[simd_test(enable = "neon")] | |
9856 | unsafe fn test_vtstq_p64() { | |
9857 | let a: i64x2 = i64x2::new(-9223372036854775808, 0x00); | |
9858 | let b: i64x2 = i64x2::new(-9223372036854775808, 0x00); | |
9859 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); | |
9860 | let r: u64x2 = transmute(vtstq_p64(transmute(a), transmute(b))); | |
9861 | assert_eq!(r, e); | |
9862 | } | |
9863 | ||
9864 | #[simd_test(enable = "neon")] | |
9865 | unsafe fn test_vtst_u64() { | |
9866 | let a: u64x1 = u64x1::new(0); | |
9867 | let b: u64x1 = u64x1::new(0); | |
9868 | let e: u64x1 = u64x1::new(0); | |
9869 | let r: u64x1 = transmute(vtst_u64(transmute(a), transmute(b))); | |
9870 | assert_eq!(r, e); | |
9871 | } | |
9872 | ||
9873 | #[simd_test(enable = "neon")] | |
9874 | unsafe fn test_vtstq_u64() { | |
9875 | let a: u64x2 = u64x2::new(0, 0x00); | |
9876 | let b: u64x2 = u64x2::new(0, 0x00); | |
9877 | let e: u64x2 = u64x2::new(0, 0); | |
9878 | let r: u64x2 = transmute(vtstq_u64(transmute(a), transmute(b))); | |
9879 | assert_eq!(r, e); | |
9880 | } | |
9881 | ||
9882 | #[simd_test(enable = "neon")] | |
9883 | unsafe fn test_vabs_f64() { | |
9884 | let a: f64 = -0.1; | |
9885 | let e: f64 = 0.1; | |
9886 | let r: f64 = transmute(vabs_f64(transmute(a))); | |
9887 | assert_eq!(r, e); | |
9888 | } | |
9889 | ||
9890 | #[simd_test(enable = "neon")] | |
9891 | unsafe fn test_vabsq_f64() { | |
9892 | let a: f64x2 = f64x2::new(-0.1, -2.2); | |
9893 | let e: f64x2 = f64x2::new(0.1, 2.2); | |
9894 | let r: f64x2 = transmute(vabsq_f64(transmute(a))); | |
9895 | assert_eq!(r, e); | |
9896 | } | |
9897 | ||
9898 | #[simd_test(enable = "neon")] | |
9899 | unsafe fn test_vcgt_s64() { | |
9900 | let a: i64x1 = i64x1::new(1); | |
9901 | let b: i64x1 = i64x1::new(0); | |
9902 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9903 | let r: u64x1 = transmute(vcgt_s64(transmute(a), transmute(b))); | |
9904 | assert_eq!(r, e); | |
9905 | } | |
9906 | ||
9907 | #[simd_test(enable = "neon")] | |
9908 | unsafe fn test_vcgtq_s64() { | |
9909 | let a: i64x2 = i64x2::new(1, 2); | |
9910 | let b: i64x2 = i64x2::new(0, 1); | |
9911 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9912 | let r: u64x2 = transmute(vcgtq_s64(transmute(a), transmute(b))); | |
9913 | assert_eq!(r, e); | |
9914 | } | |
9915 | ||
9916 | #[simd_test(enable = "neon")] | |
9917 | unsafe fn test_vcgt_u64() { | |
9918 | let a: u64x1 = u64x1::new(1); | |
9919 | let b: u64x1 = u64x1::new(0); | |
9920 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9921 | let r: u64x1 = transmute(vcgt_u64(transmute(a), transmute(b))); | |
9922 | assert_eq!(r, e); | |
9923 | } | |
9924 | ||
9925 | #[simd_test(enable = "neon")] | |
9926 | unsafe fn test_vcgtq_u64() { | |
9927 | let a: u64x2 = u64x2::new(1, 2); | |
9928 | let b: u64x2 = u64x2::new(0, 1); | |
9929 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9930 | let r: u64x2 = transmute(vcgtq_u64(transmute(a), transmute(b))); | |
9931 | assert_eq!(r, e); | |
9932 | } | |
9933 | ||
9934 | #[simd_test(enable = "neon")] | |
9935 | unsafe fn test_vcgt_f64() { | |
9936 | let a: f64 = 1.2; | |
9937 | let b: f64 = 0.1; | |
9938 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9939 | let r: u64x1 = transmute(vcgt_f64(transmute(a), transmute(b))); | |
9940 | assert_eq!(r, e); | |
9941 | } | |
9942 | ||
9943 | #[simd_test(enable = "neon")] | |
9944 | unsafe fn test_vcgtq_f64() { | |
9945 | let a: f64x2 = f64x2::new(1.2, 2.3); | |
9946 | let b: f64x2 = f64x2::new(0.1, 1.2); | |
9947 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9948 | let r: u64x2 = transmute(vcgtq_f64(transmute(a), transmute(b))); | |
9949 | assert_eq!(r, e); | |
9950 | } | |
9951 | ||
9952 | #[simd_test(enable = "neon")] | |
9953 | unsafe fn test_vclt_s64() { | |
9954 | let a: i64x1 = i64x1::new(0); | |
9955 | let b: i64x1 = i64x1::new(1); | |
9956 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9957 | let r: u64x1 = transmute(vclt_s64(transmute(a), transmute(b))); | |
9958 | assert_eq!(r, e); | |
9959 | } | |
9960 | ||
9961 | #[simd_test(enable = "neon")] | |
9962 | unsafe fn test_vcltq_s64() { | |
9963 | let a: i64x2 = i64x2::new(0, 1); | |
9964 | let b: i64x2 = i64x2::new(1, 2); | |
9965 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9966 | let r: u64x2 = transmute(vcltq_s64(transmute(a), transmute(b))); | |
9967 | assert_eq!(r, e); | |
9968 | } | |
9969 | ||
9970 | #[simd_test(enable = "neon")] | |
9971 | unsafe fn test_vclt_u64() { | |
9972 | let a: u64x1 = u64x1::new(0); | |
9973 | let b: u64x1 = u64x1::new(1); | |
9974 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9975 | let r: u64x1 = transmute(vclt_u64(transmute(a), transmute(b))); | |
9976 | assert_eq!(r, e); | |
9977 | } | |
9978 | ||
9979 | #[simd_test(enable = "neon")] | |
9980 | unsafe fn test_vcltq_u64() { | |
9981 | let a: u64x2 = u64x2::new(0, 1); | |
9982 | let b: u64x2 = u64x2::new(1, 2); | |
9983 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9984 | let r: u64x2 = transmute(vcltq_u64(transmute(a), transmute(b))); | |
9985 | assert_eq!(r, e); | |
9986 | } | |
9987 | ||
9988 | #[simd_test(enable = "neon")] | |
9989 | unsafe fn test_vclt_f64() { | |
9990 | let a: f64 = 0.1; | |
9991 | let b: f64 = 1.2; | |
9992 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9993 | let r: u64x1 = transmute(vclt_f64(transmute(a), transmute(b))); | |
9994 | assert_eq!(r, e); | |
9995 | } | |
9996 | ||
9997 | #[simd_test(enable = "neon")] | |
9998 | unsafe fn test_vcltq_f64() { | |
9999 | let a: f64x2 = f64x2::new(0.1, 1.2); | |
10000 | let b: f64x2 = f64x2::new(1.2, 2.3); | |
10001 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10002 | let r: u64x2 = transmute(vcltq_f64(transmute(a), transmute(b))); | |
10003 | assert_eq!(r, e); | |
10004 | } | |
10005 | ||
10006 | #[simd_test(enable = "neon")] | |
10007 | unsafe fn test_vcle_s64() { | |
10008 | let a: i64x1 = i64x1::new(0); | |
10009 | let b: i64x1 = i64x1::new(1); | |
10010 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10011 | let r: u64x1 = transmute(vcle_s64(transmute(a), transmute(b))); | |
10012 | assert_eq!(r, e); | |
10013 | } | |
10014 | ||
10015 | #[simd_test(enable = "neon")] | |
10016 | unsafe fn test_vcleq_s64() { | |
10017 | let a: i64x2 = i64x2::new(0, 1); | |
10018 | let b: i64x2 = i64x2::new(1, 2); | |
10019 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10020 | let r: u64x2 = transmute(vcleq_s64(transmute(a), transmute(b))); | |
10021 | assert_eq!(r, e); | |
10022 | } | |
10023 | ||
10024 | #[simd_test(enable = "neon")] | |
10025 | unsafe fn test_vcle_u64() { | |
10026 | let a: u64x1 = u64x1::new(0); | |
10027 | let b: u64x1 = u64x1::new(1); | |
10028 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10029 | let r: u64x1 = transmute(vcle_u64(transmute(a), transmute(b))); | |
10030 | assert_eq!(r, e); | |
10031 | } | |
10032 | ||
10033 | #[simd_test(enable = "neon")] | |
10034 | unsafe fn test_vcleq_u64() { | |
10035 | let a: u64x2 = u64x2::new(0, 1); | |
10036 | let b: u64x2 = u64x2::new(1, 2); | |
10037 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10038 | let r: u64x2 = transmute(vcleq_u64(transmute(a), transmute(b))); | |
10039 | assert_eq!(r, e); | |
10040 | } | |
10041 | ||
10042 | #[simd_test(enable = "neon")] | |
10043 | unsafe fn test_vcle_f64() { | |
10044 | let a: f64 = 0.1; | |
10045 | let b: f64 = 1.2; | |
10046 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10047 | let r: u64x1 = transmute(vcle_f64(transmute(a), transmute(b))); | |
10048 | assert_eq!(r, e); | |
10049 | } | |
10050 | ||
10051 | #[simd_test(enable = "neon")] | |
10052 | unsafe fn test_vcleq_f64() { | |
10053 | let a: f64x2 = f64x2::new(0.1, 1.2); | |
10054 | let b: f64x2 = f64x2::new(1.2, 2.3); | |
10055 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10056 | let r: u64x2 = transmute(vcleq_f64(transmute(a), transmute(b))); | |
10057 | assert_eq!(r, e); | |
10058 | } | |
10059 | ||
10060 | #[simd_test(enable = "neon")] | |
10061 | unsafe fn test_vcge_s64() { | |
10062 | let a: i64x1 = i64x1::new(1); | |
10063 | let b: i64x1 = i64x1::new(0); | |
10064 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10065 | let r: u64x1 = transmute(vcge_s64(transmute(a), transmute(b))); | |
10066 | assert_eq!(r, e); | |
10067 | } | |
10068 | ||
10069 | #[simd_test(enable = "neon")] | |
10070 | unsafe fn test_vcgeq_s64() { | |
10071 | let a: i64x2 = i64x2::new(1, 2); | |
10072 | let b: i64x2 = i64x2::new(0, 1); | |
10073 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10074 | let r: u64x2 = transmute(vcgeq_s64(transmute(a), transmute(b))); | |
10075 | assert_eq!(r, e); | |
10076 | } | |
10077 | ||
10078 | #[simd_test(enable = "neon")] | |
10079 | unsafe fn test_vcge_u64() { | |
10080 | let a: u64x1 = u64x1::new(1); | |
10081 | let b: u64x1 = u64x1::new(0); | |
10082 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10083 | let r: u64x1 = transmute(vcge_u64(transmute(a), transmute(b))); | |
10084 | assert_eq!(r, e); | |
10085 | } | |
10086 | ||
10087 | #[simd_test(enable = "neon")] | |
10088 | unsafe fn test_vcgeq_u64() { | |
10089 | let a: u64x2 = u64x2::new(1, 2); | |
10090 | let b: u64x2 = u64x2::new(0, 1); | |
10091 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10092 | let r: u64x2 = transmute(vcgeq_u64(transmute(a), transmute(b))); | |
10093 | assert_eq!(r, e); | |
10094 | } | |
10095 | ||
10096 | #[simd_test(enable = "neon")] | |
10097 | unsafe fn test_vcge_f64() { | |
10098 | let a: f64 = 1.2; | |
10099 | let b: f64 = 0.1; | |
10100 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10101 | let r: u64x1 = transmute(vcge_f64(transmute(a), transmute(b))); | |
10102 | assert_eq!(r, e); | |
10103 | } | |
10104 | ||
10105 | #[simd_test(enable = "neon")] | |
10106 | unsafe fn test_vcgeq_f64() { | |
10107 | let a: f64x2 = f64x2::new(1.2, 2.3); | |
10108 | let b: f64x2 = f64x2::new(0.1, 1.2); | |
10109 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10110 | let r: u64x2 = transmute(vcgeq_f64(transmute(a), transmute(b))); | |
10111 | assert_eq!(r, e); | |
10112 | } | |
10113 | ||
10114 | #[simd_test(enable = "neon")] | |
10115 | unsafe fn test_vcgez_s8() { | |
10116 | let a: i8x8 = i8x8::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); | |
10117 | let e: u8x8 = u8x8::new(0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); | |
10118 | let r: u8x8 = transmute(vcgez_s8(transmute(a))); | |
10119 | assert_eq!(r, e); | |
10120 | } | |
10121 | ||
10122 | #[simd_test(enable = "neon")] | |
10123 | unsafe fn test_vcgezq_s8() { | |
10124 | let a: i8x16 = i8x16::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x7F); | |
10125 | let e: u8x16 = u8x16::new(0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); | |
10126 | let r: u8x16 = transmute(vcgezq_s8(transmute(a))); | |
10127 | assert_eq!(r, e); | |
10128 | } | |
10129 | ||
10130 | #[simd_test(enable = "neon")] | |
10131 | unsafe fn test_vcgez_s16() { | |
10132 | let a: i16x4 = i16x4::new(-32768, -1, 0x00, 0x01); | |
10133 | let e: u16x4 = u16x4::new(0, 0, 0xFF_FF, 0xFF_FF); | |
10134 | let r: u16x4 = transmute(vcgez_s16(transmute(a))); | |
10135 | assert_eq!(r, e); | |
10136 | } | |
10137 | ||
10138 | #[simd_test(enable = "neon")] | |
10139 | unsafe fn test_vcgezq_s16() { | |
10140 | let a: i16x8 = i16x8::new(-32768, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); | |
10141 | let e: u16x8 = u16x8::new(0, 0, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); | |
10142 | let r: u16x8 = transmute(vcgezq_s16(transmute(a))); | |
10143 | assert_eq!(r, e); | |
10144 | } | |
10145 | ||
10146 | #[simd_test(enable = "neon")] | |
10147 | unsafe fn test_vcgez_s32() { | |
10148 | let a: i32x2 = i32x2::new(-2147483648, -1); | |
10149 | let e: u32x2 = u32x2::new(0, 0); | |
10150 | let r: u32x2 = transmute(vcgez_s32(transmute(a))); | |
10151 | assert_eq!(r, e); | |
10152 | } | |
10153 | ||
10154 | #[simd_test(enable = "neon")] | |
10155 | unsafe fn test_vcgezq_s32() { | |
10156 | let a: i32x4 = i32x4::new(-2147483648, -1, 0x00, 0x01); | |
10157 | let e: u32x4 = u32x4::new(0, 0, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); | |
10158 | let r: u32x4 = transmute(vcgezq_s32(transmute(a))); | |
10159 | assert_eq!(r, e); | |
10160 | } | |
10161 | ||
10162 | #[simd_test(enable = "neon")] | |
10163 | unsafe fn test_vcgez_s64() { | |
10164 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
10165 | let e: u64x1 = u64x1::new(0); | |
10166 | let r: u64x1 = transmute(vcgez_s64(transmute(a))); | |
10167 | assert_eq!(r, e); | |
10168 | } | |
10169 | ||
10170 | #[simd_test(enable = "neon")] | |
10171 | unsafe fn test_vcgezq_s64() { | |
10172 | let a: i64x2 = i64x2::new(-9223372036854775808, -1); | |
10173 | let e: u64x2 = u64x2::new(0, 0); | |
10174 | let r: u64x2 = transmute(vcgezq_s64(transmute(a))); | |
10175 | assert_eq!(r, e); | |
10176 | } | |
10177 | ||
10178 | #[simd_test(enable = "neon")] | |
10179 | unsafe fn test_vcgez_f32() { | |
10180 | let a: f32x2 = f32x2::new(-1.2, 0.0); | |
10181 | let e: u32x2 = u32x2::new(0, 0xFF_FF_FF_FF); | |
10182 | let r: u32x2 = transmute(vcgez_f32(transmute(a))); | |
10183 | assert_eq!(r, e); | |
10184 | } | |
10185 | ||
10186 | #[simd_test(enable = "neon")] | |
10187 | unsafe fn test_vcgezq_f32() { | |
10188 | let a: f32x4 = f32x4::new(-1.2, 0.0, 1.2, 2.3); | |
10189 | let e: u32x4 = u32x4::new(0, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); | |
10190 | let r: u32x4 = transmute(vcgezq_f32(transmute(a))); | |
10191 | assert_eq!(r, e); | |
10192 | } | |
10193 | ||
10194 | #[simd_test(enable = "neon")] | |
10195 | unsafe fn test_vcgez_f64() { | |
10196 | let a: f64 = -1.2; | |
10197 | let e: u64x1 = u64x1::new(0); | |
10198 | let r: u64x1 = transmute(vcgez_f64(transmute(a))); | |
10199 | assert_eq!(r, e); | |
10200 | } | |
10201 | ||
10202 | #[simd_test(enable = "neon")] | |
10203 | unsafe fn test_vcgezq_f64() { | |
10204 | let a: f64x2 = f64x2::new(-1.2, 0.0); | |
10205 | let e: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10206 | let r: u64x2 = transmute(vcgezq_f64(transmute(a))); | |
10207 | assert_eq!(r, e); | |
10208 | } | |
10209 | ||
10210 | #[simd_test(enable = "neon")] | |
10211 | unsafe fn test_vcgtz_s8() { | |
10212 | let a: i8x8 = i8x8::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); | |
10213 | let e: u8x8 = u8x8::new(0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); | |
10214 | let r: u8x8 = transmute(vcgtz_s8(transmute(a))); | |
10215 | assert_eq!(r, e); | |
10216 | } | |
10217 | ||
10218 | #[simd_test(enable = "neon")] | |
10219 | unsafe fn test_vcgtzq_s8() { | |
10220 | let a: i8x16 = i8x16::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x7F); | |
10221 | let e: u8x16 = u8x16::new(0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); | |
10222 | let r: u8x16 = transmute(vcgtzq_s8(transmute(a))); | |
10223 | assert_eq!(r, e); | |
10224 | } | |
10225 | ||
10226 | #[simd_test(enable = "neon")] | |
10227 | unsafe fn test_vcgtz_s16() { | |
10228 | let a: i16x4 = i16x4::new(-32768, -1, 0x00, 0x01); | |
10229 | let e: u16x4 = u16x4::new(0, 0, 0, 0xFF_FF); | |
10230 | let r: u16x4 = transmute(vcgtz_s16(transmute(a))); | |
10231 | assert_eq!(r, e); | |
10232 | } | |
10233 | ||
10234 | #[simd_test(enable = "neon")] | |
10235 | unsafe fn test_vcgtzq_s16() { | |
10236 | let a: i16x8 = i16x8::new(-32768, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); | |
10237 | let e: u16x8 = u16x8::new(0, 0, 0, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); | |
10238 | let r: u16x8 = transmute(vcgtzq_s16(transmute(a))); | |
10239 | assert_eq!(r, e); | |
10240 | } | |
10241 | ||
10242 | #[simd_test(enable = "neon")] | |
10243 | unsafe fn test_vcgtz_s32() { | |
10244 | let a: i32x2 = i32x2::new(-2147483648, -1); | |
10245 | let e: u32x2 = u32x2::new(0, 0); | |
10246 | let r: u32x2 = transmute(vcgtz_s32(transmute(a))); | |
10247 | assert_eq!(r, e); | |
10248 | } | |
10249 | ||
10250 | #[simd_test(enable = "neon")] | |
10251 | unsafe fn test_vcgtzq_s32() { | |
10252 | let a: i32x4 = i32x4::new(-2147483648, -1, 0x00, 0x01); | |
10253 | let e: u32x4 = u32x4::new(0, 0, 0, 0xFF_FF_FF_FF); | |
10254 | let r: u32x4 = transmute(vcgtzq_s32(transmute(a))); | |
10255 | assert_eq!(r, e); | |
10256 | } | |
10257 | ||
10258 | #[simd_test(enable = "neon")] | |
10259 | unsafe fn test_vcgtz_s64() { | |
10260 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
10261 | let e: u64x1 = u64x1::new(0); | |
10262 | let r: u64x1 = transmute(vcgtz_s64(transmute(a))); | |
10263 | assert_eq!(r, e); | |
10264 | } | |
10265 | ||
10266 | #[simd_test(enable = "neon")] | |
10267 | unsafe fn test_vcgtzq_s64() { | |
10268 | let a: i64x2 = i64x2::new(-9223372036854775808, -1); | |
10269 | let e: u64x2 = u64x2::new(0, 0); | |
10270 | let r: u64x2 = transmute(vcgtzq_s64(transmute(a))); | |
10271 | assert_eq!(r, e); | |
10272 | } | |
10273 | ||
10274 | #[simd_test(enable = "neon")] | |
10275 | unsafe fn test_vcgtz_f32() { | |
10276 | let a: f32x2 = f32x2::new(-1.2, 0.0); | |
10277 | let e: u32x2 = u32x2::new(0, 0); | |
10278 | let r: u32x2 = transmute(vcgtz_f32(transmute(a))); | |
10279 | assert_eq!(r, e); | |
10280 | } | |
10281 | ||
10282 | #[simd_test(enable = "neon")] | |
10283 | unsafe fn test_vcgtzq_f32() { | |
10284 | let a: f32x4 = f32x4::new(-1.2, 0.0, 1.2, 2.3); | |
10285 | let e: u32x4 = u32x4::new(0, 0, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); | |
10286 | let r: u32x4 = transmute(vcgtzq_f32(transmute(a))); | |
10287 | assert_eq!(r, e); | |
10288 | } | |
10289 | ||
10290 | #[simd_test(enable = "neon")] | |
10291 | unsafe fn test_vcgtz_f64() { | |
10292 | let a: f64 = -1.2; | |
10293 | let e: u64x1 = u64x1::new(0); | |
10294 | let r: u64x1 = transmute(vcgtz_f64(transmute(a))); | |
10295 | assert_eq!(r, e); | |
10296 | } | |
10297 | ||
10298 | #[simd_test(enable = "neon")] | |
10299 | unsafe fn test_vcgtzq_f64() { | |
10300 | let a: f64x2 = f64x2::new(-1.2, 0.0); | |
10301 | let e: u64x2 = u64x2::new(0, 0); | |
10302 | let r: u64x2 = transmute(vcgtzq_f64(transmute(a))); | |
10303 | assert_eq!(r, e); | |
10304 | } | |
10305 | ||
10306 | #[simd_test(enable = "neon")] | |
10307 | unsafe fn test_vclez_s8() { | |
10308 | let a: i8x8 = i8x8::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); | |
10309 | let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0, 0, 0, 0, 0); | |
10310 | let r: u8x8 = transmute(vclez_s8(transmute(a))); | |
10311 | assert_eq!(r, e); | |
10312 | } | |
10313 | ||
10314 | #[simd_test(enable = "neon")] | |
10315 | unsafe fn test_vclezq_s8() { | |
10316 | let a: i8x16 = i8x16::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x7F); | |
10317 | let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
10318 | let r: u8x16 = transmute(vclezq_s8(transmute(a))); | |
10319 | assert_eq!(r, e); | |
10320 | } | |
10321 | ||
10322 | #[simd_test(enable = "neon")] | |
10323 | unsafe fn test_vclez_s16() { | |
10324 | let a: i16x4 = i16x4::new(-32768, -1, 0x00, 0x01); | |
10325 | let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0); | |
10326 | let r: u16x4 = transmute(vclez_s16(transmute(a))); | |
10327 | assert_eq!(r, e); | |
10328 | } | |
10329 | ||
10330 | #[simd_test(enable = "neon")] | |
10331 | unsafe fn test_vclezq_s16() { | |
10332 | let a: i16x8 = i16x8::new(-32768, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); | |
10333 | let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0, 0, 0, 0, 0); | |
10334 | let r: u16x8 = transmute(vclezq_s16(transmute(a))); | |
10335 | assert_eq!(r, e); | |
10336 | } | |
10337 | ||
10338 | #[simd_test(enable = "neon")] | |
10339 | unsafe fn test_vclez_s32() { | |
10340 | let a: i32x2 = i32x2::new(-2147483648, -1); | |
10341 | let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); | |
10342 | let r: u32x2 = transmute(vclez_s32(transmute(a))); | |
10343 | assert_eq!(r, e); | |
10344 | } | |
10345 | ||
10346 | #[simd_test(enable = "neon")] | |
10347 | unsafe fn test_vclezq_s32() { | |
10348 | let a: i32x4 = i32x4::new(-2147483648, -1, 0x00, 0x01); | |
10349 | let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0); | |
10350 | let r: u32x4 = transmute(vclezq_s32(transmute(a))); | |
10351 | assert_eq!(r, e); | |
10352 | } | |
10353 | ||
10354 | #[simd_test(enable = "neon")] | |
10355 | unsafe fn test_vclez_s64() { | |
10356 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
10357 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10358 | let r: u64x1 = transmute(vclez_s64(transmute(a))); | |
10359 | assert_eq!(r, e); | |
10360 | } | |
10361 | ||
10362 | #[simd_test(enable = "neon")] | |
10363 | unsafe fn test_vclezq_s64() { | |
10364 | let a: i64x2 = i64x2::new(-9223372036854775808, -1); | |
10365 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10366 | let r: u64x2 = transmute(vclezq_s64(transmute(a))); | |
10367 | assert_eq!(r, e); | |
10368 | } | |
10369 | ||
10370 | #[simd_test(enable = "neon")] | |
10371 | unsafe fn test_vclez_f32() { | |
10372 | let a: f32x2 = f32x2::new(-1.2, 0.0); | |
10373 | let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); | |
10374 | let r: u32x2 = transmute(vclez_f32(transmute(a))); | |
10375 | assert_eq!(r, e); | |
10376 | } | |
10377 | ||
10378 | #[simd_test(enable = "neon")] | |
10379 | unsafe fn test_vclezq_f32() { | |
10380 | let a: f32x4 = f32x4::new(-1.2, 0.0, 1.2, 2.3); | |
10381 | let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0, 0); | |
10382 | let r: u32x4 = transmute(vclezq_f32(transmute(a))); | |
10383 | assert_eq!(r, e); | |
10384 | } | |
10385 | ||
10386 | #[simd_test(enable = "neon")] | |
10387 | unsafe fn test_vclez_f64() { | |
10388 | let a: f64 = -1.2; | |
10389 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10390 | let r: u64x1 = transmute(vclez_f64(transmute(a))); | |
10391 | assert_eq!(r, e); | |
10392 | } | |
10393 | ||
10394 | #[simd_test(enable = "neon")] | |
10395 | unsafe fn test_vclezq_f64() { | |
10396 | let a: f64x2 = f64x2::new(-1.2, 0.0); | |
10397 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10398 | let r: u64x2 = transmute(vclezq_f64(transmute(a))); | |
10399 | assert_eq!(r, e); | |
10400 | } | |
10401 | ||
10402 | #[simd_test(enable = "neon")] | |
10403 | unsafe fn test_vcltz_s8() { | |
10404 | let a: i8x8 = i8x8::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); | |
10405 | let e: u8x8 = u8x8::new(0xFF, 0xFF, 0, 0, 0, 0, 0, 0); | |
10406 | let r: u8x8 = transmute(vcltz_s8(transmute(a))); | |
10407 | assert_eq!(r, e); | |
10408 | } | |
10409 | ||
10410 | #[simd_test(enable = "neon")] | |
10411 | unsafe fn test_vcltzq_s8() { | |
10412 | let a: i8x16 = i8x16::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x7F); | |
10413 | let e: u8x16 = u8x16::new(0xFF, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
10414 | let r: u8x16 = transmute(vcltzq_s8(transmute(a))); | |
10415 | assert_eq!(r, e); | |
10416 | } | |
10417 | ||
10418 | #[simd_test(enable = "neon")] | |
10419 | unsafe fn test_vcltz_s16() { | |
10420 | let a: i16x4 = i16x4::new(-32768, -1, 0x00, 0x01); | |
10421 | let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0, 0); | |
10422 | let r: u16x4 = transmute(vcltz_s16(transmute(a))); | |
10423 | assert_eq!(r, e); | |
10424 | } | |
10425 | ||
10426 | #[simd_test(enable = "neon")] | |
10427 | unsafe fn test_vcltzq_s16() { | |
10428 | let a: i16x8 = i16x8::new(-32768, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); | |
10429 | let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0, 0, 0, 0, 0, 0); | |
10430 | let r: u16x8 = transmute(vcltzq_s16(transmute(a))); | |
10431 | assert_eq!(r, e); | |
10432 | } | |
10433 | ||
10434 | #[simd_test(enable = "neon")] | |
10435 | unsafe fn test_vcltz_s32() { | |
10436 | let a: i32x2 = i32x2::new(-2147483648, -1); | |
10437 | let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); | |
10438 | let r: u32x2 = transmute(vcltz_s32(transmute(a))); | |
10439 | assert_eq!(r, e); | |
10440 | } | |
10441 | ||
10442 | #[simd_test(enable = "neon")] | |
10443 | unsafe fn test_vcltzq_s32() { | |
10444 | let a: i32x4 = i32x4::new(-2147483648, -1, 0x00, 0x01); | |
10445 | let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0, 0); | |
10446 | let r: u32x4 = transmute(vcltzq_s32(transmute(a))); | |
10447 | assert_eq!(r, e); | |
10448 | } | |
10449 | ||
10450 | #[simd_test(enable = "neon")] | |
10451 | unsafe fn test_vcltz_s64() { | |
10452 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
10453 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10454 | let r: u64x1 = transmute(vcltz_s64(transmute(a))); | |
10455 | assert_eq!(r, e); | |
10456 | } | |
10457 | ||
10458 | #[simd_test(enable = "neon")] | |
10459 | unsafe fn test_vcltzq_s64() { | |
10460 | let a: i64x2 = i64x2::new(-9223372036854775808, -1); | |
10461 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10462 | let r: u64x2 = transmute(vcltzq_s64(transmute(a))); | |
10463 | assert_eq!(r, e); | |
10464 | } | |
10465 | ||
10466 | #[simd_test(enable = "neon")] | |
10467 | unsafe fn test_vcltz_f32() { | |
10468 | let a: f32x2 = f32x2::new(-1.2, 0.0); | |
10469 | let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0); | |
10470 | let r: u32x2 = transmute(vcltz_f32(transmute(a))); | |
10471 | assert_eq!(r, e); | |
10472 | } | |
10473 | ||
10474 | #[simd_test(enable = "neon")] | |
10475 | unsafe fn test_vcltzq_f32() { | |
10476 | let a: f32x4 = f32x4::new(-1.2, 0.0, 1.2, 2.3); | |
10477 | let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0, 0, 0); | |
10478 | let r: u32x4 = transmute(vcltzq_f32(transmute(a))); | |
10479 | assert_eq!(r, e); | |
10480 | } | |
10481 | ||
10482 | #[simd_test(enable = "neon")] | |
10483 | unsafe fn test_vcltz_f64() { | |
10484 | let a: f64 = -1.2; | |
10485 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10486 | let r: u64x1 = transmute(vcltz_f64(transmute(a))); | |
10487 | assert_eq!(r, e); | |
10488 | } | |
10489 | ||
10490 | #[simd_test(enable = "neon")] | |
10491 | unsafe fn test_vcltzq_f64() { | |
10492 | let a: f64x2 = f64x2::new(-1.2, 0.0); | |
10493 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); | |
10494 | let r: u64x2 = transmute(vcltzq_f64(transmute(a))); | |
10495 | assert_eq!(r, e); | |
10496 | } | |
10497 | ||
10498 | #[simd_test(enable = "neon")] | |
10499 | unsafe fn test_vcagt_f64() { | |
10500 | let a: f64 = -1.2; | |
10501 | let b: f64 = -1.1; | |
10502 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10503 | let r: u64x1 = transmute(vcagt_f64(transmute(a), transmute(b))); | |
10504 | assert_eq!(r, e); | |
10505 | } | |
10506 | ||
10507 | #[simd_test(enable = "neon")] | |
10508 | unsafe fn test_vcagtq_f64() { | |
10509 | let a: f64x2 = f64x2::new(-1.2, 0.0); | |
10510 | let b: f64x2 = f64x2::new(-1.1, 0.0); | |
10511 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); | |
10512 | let r: u64x2 = transmute(vcagtq_f64(transmute(a), transmute(b))); | |
10513 | assert_eq!(r, e); | |
10514 | } | |
10515 | ||
10516 | #[simd_test(enable = "neon")] | |
10517 | unsafe fn test_vcage_f64() { | |
10518 | let a: f64 = -1.2; | |
10519 | let b: f64 = -1.1; | |
10520 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10521 | let r: u64x1 = transmute(vcage_f64(transmute(a), transmute(b))); | |
10522 | assert_eq!(r, e); | |
10523 | } | |
10524 | ||
10525 | #[simd_test(enable = "neon")] | |
10526 | unsafe fn test_vcageq_f64() { | |
10527 | let a: f64x2 = f64x2::new(-1.2, 0.0); | |
10528 | let b: f64x2 = f64x2::new(-1.1, 0.0); | |
10529 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10530 | let r: u64x2 = transmute(vcageq_f64(transmute(a), transmute(b))); | |
10531 | assert_eq!(r, e); | |
10532 | } | |
10533 | ||
10534 | #[simd_test(enable = "neon")] | |
10535 | unsafe fn test_vcalt_f64() { | |
10536 | let a: f64 = -1.2; | |
10537 | let b: f64 = -1.1; | |
10538 | let e: u64x1 = u64x1::new(0); | |
10539 | let r: u64x1 = transmute(vcalt_f64(transmute(a), transmute(b))); | |
10540 | assert_eq!(r, e); | |
10541 | } | |
10542 | ||
10543 | #[simd_test(enable = "neon")] | |
10544 | unsafe fn test_vcaltq_f64() { | |
10545 | let a: f64x2 = f64x2::new(-1.2, 0.0); | |
10546 | let b: f64x2 = f64x2::new(-1.1, 0.0); | |
10547 | let e: u64x2 = u64x2::new(0, 0); | |
10548 | let r: u64x2 = transmute(vcaltq_f64(transmute(a), transmute(b))); | |
10549 | assert_eq!(r, e); | |
10550 | } | |
10551 | ||
10552 | #[simd_test(enable = "neon")] | |
10553 | unsafe fn test_vcale_f64() { | |
10554 | let a: f64 = -1.2; | |
10555 | let b: f64 = -1.1; | |
10556 | let e: u64x1 = u64x1::new(0); | |
10557 | let r: u64x1 = transmute(vcale_f64(transmute(a), transmute(b))); | |
10558 | assert_eq!(r, e); | |
10559 | } | |
10560 | ||
10561 | #[simd_test(enable = "neon")] | |
10562 | unsafe fn test_vcaleq_f64() { | |
10563 | let a: f64x2 = f64x2::new(-1.2, 0.0); | |
10564 | let b: f64x2 = f64x2::new(-1.1, 0.0); | |
10565 | let e: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10566 | let r: u64x2 = transmute(vcaleq_f64(transmute(a), transmute(b))); | |
10567 | assert_eq!(r, e); | |
10568 | } | |
10569 | ||
10570 | #[simd_test(enable = "neon")] | |
10571 | unsafe fn test_vcopy_lane_s8() { | |
10572 | let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10573 | let b: i8x8 = i8x8::new(0, 0x7F, 0, 0, 0, 0, 0, 0); | |
10574 | let e: i8x8 = i8x8::new(0x7F, 2, 3, 4, 5, 6, 7, 8); | |
10575 | let r: i8x8 = transmute(vcopy_lane_s8::<0, 1>(transmute(a), transmute(b))); | |
10576 | assert_eq!(r, e); | |
10577 | } | |
10578 | ||
10579 | #[simd_test(enable = "neon")] | |
10580 | unsafe fn test_vcopyq_laneq_s8() { | |
10581 | let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10582 | let b: i8x16 = i8x16::new(0, 0x7F, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
10583 | let e: i8x16 = i8x16::new(0x7F, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10584 | let r: i8x16 = transmute(vcopyq_laneq_s8::<0, 1>(transmute(a), transmute(b))); | |
10585 | assert_eq!(r, e); | |
10586 | } | |
10587 | ||
10588 | #[simd_test(enable = "neon")] | |
10589 | unsafe fn test_vcopy_lane_s16() { | |
10590 | let a: i16x4 = i16x4::new(1, 2, 3, 4); | |
10591 | let b: i16x4 = i16x4::new(0, 0x7F_FF, 0, 0); | |
10592 | let e: i16x4 = i16x4::new(0x7F_FF, 2, 3, 4); | |
10593 | let r: i16x4 = transmute(vcopy_lane_s16::<0, 1>(transmute(a), transmute(b))); | |
10594 | assert_eq!(r, e); | |
10595 | } | |
10596 | ||
10597 | #[simd_test(enable = "neon")] | |
10598 | unsafe fn test_vcopyq_laneq_s16() { | |
10599 | let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10600 | let b: i16x8 = i16x8::new(0, 0x7F_FF, 0, 0, 0, 0, 0, 0); | |
10601 | let e: i16x8 = i16x8::new(0x7F_FF, 2, 3, 4, 5, 6, 7, 8); | |
10602 | let r: i16x8 = transmute(vcopyq_laneq_s16::<0, 1>(transmute(a), transmute(b))); | |
10603 | assert_eq!(r, e); | |
10604 | } | |
10605 | ||
10606 | #[simd_test(enable = "neon")] | |
10607 | unsafe fn test_vcopy_lane_s32() { | |
10608 | let a: i32x2 = i32x2::new(1, 2); | |
10609 | let b: i32x2 = i32x2::new(0, 0x7F_FF_FF_FF); | |
10610 | let e: i32x2 = i32x2::new(0x7F_FF_FF_FF, 2); | |
10611 | let r: i32x2 = transmute(vcopy_lane_s32::<0, 1>(transmute(a), transmute(b))); | |
10612 | assert_eq!(r, e); | |
10613 | } | |
10614 | ||
10615 | #[simd_test(enable = "neon")] | |
10616 | unsafe fn test_vcopyq_laneq_s32() { | |
10617 | let a: i32x4 = i32x4::new(1, 2, 3, 4); | |
10618 | let b: i32x4 = i32x4::new(0, 0x7F_FF_FF_FF, 0, 0); | |
10619 | let e: i32x4 = i32x4::new(0x7F_FF_FF_FF, 2, 3, 4); | |
10620 | let r: i32x4 = transmute(vcopyq_laneq_s32::<0, 1>(transmute(a), transmute(b))); | |
10621 | assert_eq!(r, e); | |
10622 | } | |
10623 | ||
10624 | #[simd_test(enable = "neon")] | |
10625 | unsafe fn test_vcopyq_laneq_s64() { | |
10626 | let a: i64x2 = i64x2::new(1, 2); | |
10627 | let b: i64x2 = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF); | |
10628 | let e: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 2); | |
10629 | let r: i64x2 = transmute(vcopyq_laneq_s64::<0, 1>(transmute(a), transmute(b))); | |
10630 | assert_eq!(r, e); | |
10631 | } | |
10632 | ||
10633 | #[simd_test(enable = "neon")] | |
10634 | unsafe fn test_vcopy_lane_u8() { | |
10635 | let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10636 | let b: u8x8 = u8x8::new(0, 0xFF, 0, 0, 0, 0, 0, 0); | |
10637 | let e: u8x8 = u8x8::new(0xFF, 2, 3, 4, 5, 6, 7, 8); | |
10638 | let r: u8x8 = transmute(vcopy_lane_u8::<0, 1>(transmute(a), transmute(b))); | |
10639 | assert_eq!(r, e); | |
10640 | } | |
10641 | ||
10642 | #[simd_test(enable = "neon")] | |
10643 | unsafe fn test_vcopyq_laneq_u8() { | |
10644 | let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10645 | let b: u8x16 = u8x16::new(0, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
10646 | let e: u8x16 = u8x16::new(0xFF, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10647 | let r: u8x16 = transmute(vcopyq_laneq_u8::<0, 1>(transmute(a), transmute(b))); | |
10648 | assert_eq!(r, e); | |
10649 | } | |
10650 | ||
10651 | #[simd_test(enable = "neon")] | |
10652 | unsafe fn test_vcopy_lane_u16() { | |
10653 | let a: u16x4 = u16x4::new(1, 2, 3, 4); | |
10654 | let b: u16x4 = u16x4::new(0, 0xFF_FF, 0, 0); | |
10655 | let e: u16x4 = u16x4::new(0xFF_FF, 2, 3, 4); | |
10656 | let r: u16x4 = transmute(vcopy_lane_u16::<0, 1>(transmute(a), transmute(b))); | |
10657 | assert_eq!(r, e); | |
10658 | } | |
10659 | ||
10660 | #[simd_test(enable = "neon")] | |
10661 | unsafe fn test_vcopyq_laneq_u16() { | |
10662 | let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10663 | let b: u16x8 = u16x8::new(0, 0xFF_FF, 0, 0, 0, 0, 0, 0); | |
10664 | let e: u16x8 = u16x8::new(0xFF_FF, 2, 3, 4, 5, 6, 7, 8); | |
10665 | let r: u16x8 = transmute(vcopyq_laneq_u16::<0, 1>(transmute(a), transmute(b))); | |
10666 | assert_eq!(r, e); | |
10667 | } | |
10668 | ||
10669 | #[simd_test(enable = "neon")] | |
10670 | unsafe fn test_vcopy_lane_u32() { | |
10671 | let a: u32x2 = u32x2::new(1, 2); | |
10672 | let b: u32x2 = u32x2::new(0, 0xFF_FF_FF_FF); | |
10673 | let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 2); | |
10674 | let r: u32x2 = transmute(vcopy_lane_u32::<0, 1>(transmute(a), transmute(b))); | |
10675 | assert_eq!(r, e); | |
10676 | } | |
10677 | ||
10678 | #[simd_test(enable = "neon")] | |
10679 | unsafe fn test_vcopyq_laneq_u32() { | |
10680 | let a: u32x4 = u32x4::new(1, 2, 3, 4); | |
10681 | let b: u32x4 = u32x4::new(0, 0xFF_FF_FF_FF, 0, 0); | |
10682 | let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 2, 3, 4); | |
10683 | let r: u32x4 = transmute(vcopyq_laneq_u32::<0, 1>(transmute(a), transmute(b))); | |
10684 | assert_eq!(r, e); | |
10685 | } | |
10686 | ||
10687 | #[simd_test(enable = "neon")] | |
10688 | unsafe fn test_vcopyq_laneq_u64() { | |
10689 | let a: u64x2 = u64x2::new(1, 2); | |
10690 | let b: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10691 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 2); | |
10692 | let r: u64x2 = transmute(vcopyq_laneq_u64::<0, 1>(transmute(a), transmute(b))); | |
10693 | assert_eq!(r, e); | |
10694 | } | |
10695 | ||
10696 | #[simd_test(enable = "neon")] | |
10697 | unsafe fn test_vcopy_lane_p8() { | |
10698 | let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10699 | let b: i8x8 = i8x8::new(0, 0x7F, 0, 0, 0, 0, 0, 0); | |
10700 | let e: i8x8 = i8x8::new(0x7F, 2, 3, 4, 5, 6, 7, 8); | |
10701 | let r: i8x8 = transmute(vcopy_lane_p8::<0, 1>(transmute(a), transmute(b))); | |
10702 | assert_eq!(r, e); | |
10703 | } | |
10704 | ||
10705 | #[simd_test(enable = "neon")] | |
10706 | unsafe fn test_vcopyq_laneq_p8() { | |
10707 | let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10708 | let b: i8x16 = i8x16::new(0, 0x7F, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
10709 | let e: i8x16 = i8x16::new(0x7F, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10710 | let r: i8x16 = transmute(vcopyq_laneq_p8::<0, 1>(transmute(a), transmute(b))); | |
10711 | assert_eq!(r, e); | |
10712 | } | |
10713 | ||
10714 | #[simd_test(enable = "neon")] | |
10715 | unsafe fn test_vcopy_lane_p16() { | |
10716 | let a: i16x4 = i16x4::new(1, 2, 3, 4); | |
10717 | let b: i16x4 = i16x4::new(0, 0x7F_FF, 0, 0); | |
10718 | let e: i16x4 = i16x4::new(0x7F_FF, 2, 3, 4); | |
10719 | let r: i16x4 = transmute(vcopy_lane_p16::<0, 1>(transmute(a), transmute(b))); | |
10720 | assert_eq!(r, e); | |
10721 | } | |
10722 | ||
10723 | #[simd_test(enable = "neon")] | |
10724 | unsafe fn test_vcopyq_laneq_p16() { | |
10725 | let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10726 | let b: i16x8 = i16x8::new(0, 0x7F_FF, 0, 0, 0, 0, 0, 0); | |
10727 | let e: i16x8 = i16x8::new(0x7F_FF, 2, 3, 4, 5, 6, 7, 8); | |
10728 | let r: i16x8 = transmute(vcopyq_laneq_p16::<0, 1>(transmute(a), transmute(b))); | |
10729 | assert_eq!(r, e); | |
10730 | } | |
10731 | ||
10732 | #[simd_test(enable = "neon")] | |
10733 | unsafe fn test_vcopyq_laneq_p64() { | |
10734 | let a: i64x2 = i64x2::new(1, 2); | |
10735 | let b: i64x2 = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF); | |
10736 | let e: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 2); | |
10737 | let r: i64x2 = transmute(vcopyq_laneq_p64::<0, 1>(transmute(a), transmute(b))); | |
10738 | assert_eq!(r, e); | |
10739 | } | |
10740 | ||
10741 | #[simd_test(enable = "neon")] | |
10742 | unsafe fn test_vcopy_lane_f32() { | |
10743 | let a: f32x2 = f32x2::new(1., 2.); | |
10744 | let b: f32x2 = f32x2::new(0., 0.5); | |
10745 | let e: f32x2 = f32x2::new(0.5, 2.); | |
10746 | let r: f32x2 = transmute(vcopy_lane_f32::<0, 1>(transmute(a), transmute(b))); | |
10747 | assert_eq!(r, e); | |
10748 | } | |
10749 | ||
10750 | #[simd_test(enable = "neon")] | |
10751 | unsafe fn test_vcopyq_laneq_f32() { | |
10752 | let a: f32x4 = f32x4::new(1., 2., 3., 4.); | |
10753 | let b: f32x4 = f32x4::new(0., 0.5, 0., 0.); | |
10754 | let e: f32x4 = f32x4::new(0.5, 2., 3., 4.); | |
10755 | let r: f32x4 = transmute(vcopyq_laneq_f32::<0, 1>(transmute(a), transmute(b))); | |
10756 | assert_eq!(r, e); | |
10757 | } | |
10758 | ||
10759 | #[simd_test(enable = "neon")] | |
10760 | unsafe fn test_vcopyq_laneq_f64() { | |
10761 | let a: f64x2 = f64x2::new(1., 2.); | |
10762 | let b: f64x2 = f64x2::new(0., 0.5); | |
10763 | let e: f64x2 = f64x2::new(0.5, 2.); | |
10764 | let r: f64x2 = transmute(vcopyq_laneq_f64::<0, 1>(transmute(a), transmute(b))); | |
10765 | assert_eq!(r, e); | |
10766 | } | |
10767 | ||
10768 | #[simd_test(enable = "neon")] | |
10769 | unsafe fn test_vcopy_laneq_s8() { | |
10770 | let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10771 | let b: i8x16 = i8x16::new(0, 0x7F, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
10772 | let e: i8x8 = i8x8::new(0x7F, 2, 3, 4, 5, 6, 7, 8); | |
10773 | let r: i8x8 = transmute(vcopy_laneq_s8::<0, 1>(transmute(a), transmute(b))); | |
10774 | assert_eq!(r, e); | |
10775 | } | |
10776 | ||
10777 | #[simd_test(enable = "neon")] | |
10778 | unsafe fn test_vcopy_laneq_s16() { | |
10779 | let a: i16x4 = i16x4::new(1, 2, 3, 4); | |
10780 | let b: i16x8 = i16x8::new(0, 0x7F_FF, 0, 0, 0, 0, 0, 0); | |
10781 | let e: i16x4 = i16x4::new(0x7F_FF, 2, 3, 4); | |
10782 | let r: i16x4 = transmute(vcopy_laneq_s16::<0, 1>(transmute(a), transmute(b))); | |
10783 | assert_eq!(r, e); | |
10784 | } | |
10785 | ||
10786 | #[simd_test(enable = "neon")] | |
10787 | unsafe fn test_vcopy_laneq_s32() { | |
10788 | let a: i32x2 = i32x2::new(1, 2); | |
10789 | let b: i32x4 = i32x4::new(0, 0x7F_FF_FF_FF, 0, 0); | |
10790 | let e: i32x2 = i32x2::new(0x7F_FF_FF_FF, 2); | |
10791 | let r: i32x2 = transmute(vcopy_laneq_s32::<0, 1>(transmute(a), transmute(b))); | |
10792 | assert_eq!(r, e); | |
10793 | } | |
10794 | ||
10795 | #[simd_test(enable = "neon")] | |
10796 | unsafe fn test_vcopy_laneq_u8() { | |
10797 | let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10798 | let b: u8x16 = u8x16::new(0, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
10799 | let e: u8x8 = u8x8::new(0xFF, 2, 3, 4, 5, 6, 7, 8); | |
10800 | let r: u8x8 = transmute(vcopy_laneq_u8::<0, 1>(transmute(a), transmute(b))); | |
10801 | assert_eq!(r, e); | |
10802 | } | |
10803 | ||
10804 | #[simd_test(enable = "neon")] | |
10805 | unsafe fn test_vcopy_laneq_u16() { | |
10806 | let a: u16x4 = u16x4::new(1, 2, 3, 4); | |
10807 | let b: u16x8 = u16x8::new(0, 0xFF_FF, 0, 0, 0, 0, 0, 0); | |
10808 | let e: u16x4 = u16x4::new(0xFF_FF, 2, 3, 4); | |
10809 | let r: u16x4 = transmute(vcopy_laneq_u16::<0, 1>(transmute(a), transmute(b))); | |
10810 | assert_eq!(r, e); | |
10811 | } | |
10812 | ||
10813 | #[simd_test(enable = "neon")] | |
10814 | unsafe fn test_vcopy_laneq_u32() { | |
10815 | let a: u32x2 = u32x2::new(1, 2); | |
10816 | let b: u32x4 = u32x4::new(0, 0xFF_FF_FF_FF, 0, 0); | |
10817 | let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 2); | |
10818 | let r: u32x2 = transmute(vcopy_laneq_u32::<0, 1>(transmute(a), transmute(b))); | |
10819 | assert_eq!(r, e); | |
10820 | } | |
10821 | ||
10822 | #[simd_test(enable = "neon")] | |
10823 | unsafe fn test_vcopy_laneq_p8() { | |
10824 | let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10825 | let b: i8x16 = i8x16::new(0, 0x7F, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
10826 | let e: i8x8 = i8x8::new(0x7F, 2, 3, 4, 5, 6, 7, 8); | |
10827 | let r: i8x8 = transmute(vcopy_laneq_p8::<0, 1>(transmute(a), transmute(b))); | |
10828 | assert_eq!(r, e); | |
10829 | } | |
10830 | ||
10831 | #[simd_test(enable = "neon")] | |
10832 | unsafe fn test_vcopy_laneq_p16() { | |
10833 | let a: i16x4 = i16x4::new(1, 2, 3, 4); | |
10834 | let b: i16x8 = i16x8::new(0, 0x7F_FF, 0, 0, 0, 0, 0, 0); | |
10835 | let e: i16x4 = i16x4::new(0x7F_FF, 2, 3, 4); | |
10836 | let r: i16x4 = transmute(vcopy_laneq_p16::<0, 1>(transmute(a), transmute(b))); | |
10837 | assert_eq!(r, e); | |
10838 | } | |
10839 | ||
10840 | #[simd_test(enable = "neon")] | |
10841 | unsafe fn test_vcopy_laneq_f32() { | |
10842 | let a: f32x2 = f32x2::new(1., 2.); | |
10843 | let b: f32x4 = f32x4::new(0., 0.5, 0., 0.); | |
10844 | let e: f32x2 = f32x2::new(0.5, 2.); | |
10845 | let r: f32x2 = transmute(vcopy_laneq_f32::<0, 1>(transmute(a), transmute(b))); | |
10846 | assert_eq!(r, e); | |
10847 | } | |
10848 | ||
10849 | #[simd_test(enable = "neon")] | |
10850 | unsafe fn test_vcopyq_lane_s8() { | |
10851 | let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10852 | let b: i8x8 = i8x8::new(0, 0x7F, 0, 0, 0, 0, 0, 0); | |
10853 | let e: i8x16 = i8x16::new(0x7F, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10854 | let r: i8x16 = transmute(vcopyq_lane_s8::<0, 1>(transmute(a), transmute(b))); | |
10855 | assert_eq!(r, e); | |
10856 | } | |
10857 | ||
10858 | #[simd_test(enable = "neon")] | |
10859 | unsafe fn test_vcopyq_lane_s16() { | |
10860 | let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10861 | let b: i16x4 = i16x4::new(0, 0x7F_FF, 0, 0); | |
10862 | let e: i16x8 = i16x8::new(0x7F_FF, 2, 3, 4, 5, 6, 7, 8); | |
10863 | let r: i16x8 = transmute(vcopyq_lane_s16::<0, 1>(transmute(a), transmute(b))); | |
10864 | assert_eq!(r, e); | |
10865 | } | |
10866 | ||
10867 | #[simd_test(enable = "neon")] | |
10868 | unsafe fn test_vcopyq_lane_s32() { | |
10869 | let a: i32x4 = i32x4::new(1, 2, 3, 4); | |
10870 | let b: i32x2 = i32x2::new(0, 0x7F_FF_FF_FF); | |
10871 | let e: i32x4 = i32x4::new(0x7F_FF_FF_FF, 2, 3, 4); | |
10872 | let r: i32x4 = transmute(vcopyq_lane_s32::<0, 1>(transmute(a), transmute(b))); | |
10873 | assert_eq!(r, e); | |
10874 | } | |
10875 | ||
10876 | #[simd_test(enable = "neon")] | |
10877 | unsafe fn test_vcopyq_lane_u8() { | |
10878 | let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10879 | let b: u8x8 = u8x8::new(0, 0xFF, 0, 0, 0, 0, 0, 0); | |
10880 | let e: u8x16 = u8x16::new(0xFF, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10881 | let r: u8x16 = transmute(vcopyq_lane_u8::<0, 1>(transmute(a), transmute(b))); | |
10882 | assert_eq!(r, e); | |
10883 | } | |
10884 | ||
10885 | #[simd_test(enable = "neon")] | |
10886 | unsafe fn test_vcopyq_lane_u16() { | |
10887 | let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10888 | let b: u16x4 = u16x4::new(0, 0xFF_FF, 0, 0); | |
10889 | let e: u16x8 = u16x8::new(0xFF_FF, 2, 3, 4, 5, 6, 7, 8); | |
10890 | let r: u16x8 = transmute(vcopyq_lane_u16::<0, 1>(transmute(a), transmute(b))); | |
10891 | assert_eq!(r, e); | |
10892 | } | |
10893 | ||
10894 | #[simd_test(enable = "neon")] | |
10895 | unsafe fn test_vcopyq_lane_u32() { | |
10896 | let a: u32x4 = u32x4::new(1, 2, 3, 4); | |
10897 | let b: u32x2 = u32x2::new(0, 0xFF_FF_FF_FF); | |
10898 | let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 2, 3, 4); | |
10899 | let r: u32x4 = transmute(vcopyq_lane_u32::<0, 1>(transmute(a), transmute(b))); | |
10900 | assert_eq!(r, e); | |
10901 | } | |
10902 | ||
10903 | #[simd_test(enable = "neon")] | |
10904 | unsafe fn test_vcopyq_lane_p8() { | |
10905 | let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10906 | let b: i8x8 = i8x8::new(0, 0x7F, 0, 0, 0, 0, 0, 0); | |
10907 | let e: i8x16 = i8x16::new(0x7F, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10908 | let r: i8x16 = transmute(vcopyq_lane_p8::<0, 1>(transmute(a), transmute(b))); | |
10909 | assert_eq!(r, e); | |
10910 | } | |
10911 | ||
10912 | #[simd_test(enable = "neon")] | |
10913 | unsafe fn test_vcopyq_lane_p16() { | |
10914 | let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10915 | let b: i16x4 = i16x4::new(0, 0x7F_FF, 0, 0); | |
10916 | let e: i16x8 = i16x8::new(0x7F_FF, 2, 3, 4, 5, 6, 7, 8); | |
10917 | let r: i16x8 = transmute(vcopyq_lane_p16::<0, 1>(transmute(a), transmute(b))); | |
10918 | assert_eq!(r, e); | |
10919 | } | |
10920 | ||
10921 | #[simd_test(enable = "neon")] | |
10922 | unsafe fn test_vcopyq_lane_s64() { | |
10923 | let a: i64x2 = i64x2::new(1, 2); | |
10924 | let b: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); | |
10925 | let e: i64x2 = i64x2::new(1, 0x7F_FF_FF_FF_FF_FF_FF_FF); | |
10926 | let r: i64x2 = transmute(vcopyq_lane_s64::<1, 0>(transmute(a), transmute(b))); | |
10927 | assert_eq!(r, e); | |
10928 | } | |
10929 | ||
10930 | #[simd_test(enable = "neon")] | |
10931 | unsafe fn test_vcopyq_lane_u64() { | |
10932 | let a: u64x2 = u64x2::new(1, 2); | |
10933 | let b: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10934 | let e: u64x2 = u64x2::new(1, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10935 | let r: u64x2 = transmute(vcopyq_lane_u64::<1, 0>(transmute(a), transmute(b))); | |
10936 | assert_eq!(r, e); | |
10937 | } | |
10938 | ||
10939 | #[simd_test(enable = "neon")] | |
10940 | unsafe fn test_vcopyq_lane_p64() { | |
10941 | let a: i64x2 = i64x2::new(1, 2); | |
10942 | let b: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); | |
10943 | let e: i64x2 = i64x2::new(1, 0x7F_FF_FF_FF_FF_FF_FF_FF); | |
10944 | let r: i64x2 = transmute(vcopyq_lane_p64::<1, 0>(transmute(a), transmute(b))); | |
10945 | assert_eq!(r, e); | |
10946 | } | |
10947 | ||
10948 | #[simd_test(enable = "neon")] | |
10949 | unsafe fn test_vcopyq_lane_f32() { | |
10950 | let a: f32x4 = f32x4::new(1., 2., 3., 4.); | |
10951 | let b: f32x2 = f32x2::new(0.5, 0.); | |
10952 | let e: f32x4 = f32x4::new(1., 0.5, 3., 4.); | |
10953 | let r: f32x4 = transmute(vcopyq_lane_f32::<1, 0>(transmute(a), transmute(b))); | |
10954 | assert_eq!(r, e); | |
10955 | } | |
10956 | ||
10957 | #[simd_test(enable = "neon")] | |
10958 | unsafe fn test_vcopyq_lane_f64() { | |
10959 | let a: f64x2 = f64x2::new(1., 2.); | |
10960 | let b: f64 = 0.5; | |
10961 | let e: f64x2 = f64x2::new(1., 0.5); | |
10962 | let r: f64x2 = transmute(vcopyq_lane_f64::<1, 0>(transmute(a), transmute(b))); | |
10963 | assert_eq!(r, e); | |
10964 | } | |
10965 | ||
10966 | #[simd_test(enable = "neon")] | |
10967 | unsafe fn test_vcreate_f64() { | |
10968 | let a: u64 = 0; | |
10969 | let e: f64 = 0.; | |
10970 | let r: f64 = transmute(vcreate_f64(transmute(a))); | |
10971 | assert_eq!(r, e); | |
10972 | } | |
10973 | ||
10974 | #[simd_test(enable = "neon")] | |
10975 | unsafe fn test_vcvt_f64_s64() { | |
10976 | let a: i64x1 = i64x1::new(1); | |
10977 | let e: f64 = 1.; | |
10978 | let r: f64 = transmute(vcvt_f64_s64(transmute(a))); | |
10979 | assert_eq!(r, e); | |
10980 | } | |
10981 | ||
10982 | #[simd_test(enable = "neon")] | |
10983 | unsafe fn test_vcvtq_f64_s64() { | |
10984 | let a: i64x2 = i64x2::new(1, 2); | |
10985 | let e: f64x2 = f64x2::new(1., 2.); | |
10986 | let r: f64x2 = transmute(vcvtq_f64_s64(transmute(a))); | |
10987 | assert_eq!(r, e); | |
10988 | } | |
10989 | ||
10990 | #[simd_test(enable = "neon")] | |
10991 | unsafe fn test_vcvt_f64_u64() { | |
10992 | let a: u64x1 = u64x1::new(1); | |
10993 | let e: f64 = 1.; | |
10994 | let r: f64 = transmute(vcvt_f64_u64(transmute(a))); | |
10995 | assert_eq!(r, e); | |
10996 | } | |
10997 | ||
10998 | #[simd_test(enable = "neon")] | |
10999 | unsafe fn test_vcvtq_f64_u64() { | |
11000 | let a: u64x2 = u64x2::new(1, 2); | |
11001 | let e: f64x2 = f64x2::new(1., 2.); | |
11002 | let r: f64x2 = transmute(vcvtq_f64_u64(transmute(a))); | |
11003 | assert_eq!(r, e); | |
11004 | } | |
11005 | ||
11006 | #[simd_test(enable = "neon")] | |
11007 | unsafe fn test_vcvt_f64_f32() { | |
11008 | let a: f32x2 = f32x2::new(-1.2, 1.2); | |
11009 | let e: f64x2 = f64x2::new(-1.2f32 as f64, 1.2f32 as f64); | |
11010 | let r: f64x2 = transmute(vcvt_f64_f32(transmute(a))); | |
11011 | assert_eq!(r, e); | |
11012 | } | |
11013 | ||
11014 | #[simd_test(enable = "neon")] | |
11015 | unsafe fn test_vcvt_high_f64_f32() { | |
11016 | let a: f32x4 = f32x4::new(-1.2, 1.2, 2.3, 3.4); | |
11017 | let e: f64x2 = f64x2::new(2.3f32 as f64, 3.4f32 as f64); | |
11018 | let r: f64x2 = transmute(vcvt_high_f64_f32(transmute(a))); | |
11019 | assert_eq!(r, e); | |
11020 | } | |
11021 | ||
11022 | #[simd_test(enable = "neon")] | |
11023 | unsafe fn test_vcvt_f32_f64() { | |
11024 | let a: f64x2 = f64x2::new(-1.2, 1.2); | |
11025 | let e: f32x2 = f32x2::new(-1.2f64 as f32, 1.2f64 as f32); | |
11026 | let r: f32x2 = transmute(vcvt_f32_f64(transmute(a))); | |
11027 | assert_eq!(r, e); | |
11028 | } | |
11029 | ||
11030 | #[simd_test(enable = "neon")] | |
11031 | unsafe fn test_vcvt_high_f32_f64() { | |
11032 | let a: f32x2 = f32x2::new(-1.2, 1.2); | |
11033 | let b: f64x2 = f64x2::new(-2.3, 3.4); | |
11034 | let e: f32x4 = f32x4::new(-1.2, 1.2, -2.3f64 as f32, 3.4f64 as f32); | |
11035 | let r: f32x4 = transmute(vcvt_high_f32_f64(transmute(a), transmute(b))); | |
11036 | assert_eq!(r, e); | |
11037 | } | |
11038 | ||
11039 | #[simd_test(enable = "neon")] | |
11040 | unsafe fn test_vcvtx_f32_f64() { | |
11041 | let a: f64x2 = f64x2::new(-1.0, 2.0); | |
11042 | let e: f32x2 = f32x2::new(-1.0, 2.0); | |
11043 | let r: f32x2 = transmute(vcvtx_f32_f64(transmute(a))); | |
11044 | assert_eq!(r, e); | |
11045 | } | |
11046 | ||
11047 | #[simd_test(enable = "neon")] | |
11048 | unsafe fn test_vcvtx_high_f32_f64() { | |
11049 | let a: f32x2 = f32x2::new(-1.0, 2.0); | |
11050 | let b: f64x2 = f64x2::new(-3.0, 4.0); | |
11051 | let e: f32x4 = f32x4::new(-1.0, 2.0, -3.0, 4.0); | |
11052 | let r: f32x4 = transmute(vcvtx_high_f32_f64(transmute(a), transmute(b))); | |
11053 | assert_eq!(r, e); | |
11054 | } | |
11055 | ||
11056 | #[simd_test(enable = "neon")] | |
11057 | unsafe fn test_vcvt_n_f64_s64() { | |
11058 | let a: i64x1 = i64x1::new(1); | |
11059 | let e: f64 = 0.25; | |
11060 | let r: f64 = transmute(vcvt_n_f64_s64::<2>(transmute(a))); | |
11061 | assert_eq!(r, e); | |
11062 | } | |
11063 | ||
11064 | #[simd_test(enable = "neon")] | |
11065 | unsafe fn test_vcvtq_n_f64_s64() { | |
11066 | let a: i64x2 = i64x2::new(1, 2); | |
11067 | let e: f64x2 = f64x2::new(0.25, 0.5); | |
11068 | let r: f64x2 = transmute(vcvtq_n_f64_s64::<2>(transmute(a))); | |
11069 | assert_eq!(r, e); | |
11070 | } | |
11071 | ||
11072 | #[simd_test(enable = "neon")] | |
11073 | unsafe fn test_vcvts_n_f32_s32() { | |
11074 | let a: i32 = 1; | |
11075 | let e: f32 = 0.25; | |
11076 | let r: f32 = transmute(vcvts_n_f32_s32::<2>(transmute(a))); | |
11077 | assert_eq!(r, e); | |
11078 | } | |
11079 | ||
11080 | #[simd_test(enable = "neon")] | |
11081 | unsafe fn test_vcvtd_n_f64_s64() { | |
11082 | let a: i64 = 1; | |
11083 | let e: f64 = 0.25; | |
11084 | let r: f64 = transmute(vcvtd_n_f64_s64::<2>(transmute(a))); | |
11085 | assert_eq!(r, e); | |
11086 | } | |
11087 | ||
11088 | #[simd_test(enable = "neon")] | |
11089 | unsafe fn test_vcvt_n_f64_u64() { | |
11090 | let a: u64x1 = u64x1::new(1); | |
11091 | let e: f64 = 0.25; | |
11092 | let r: f64 = transmute(vcvt_n_f64_u64::<2>(transmute(a))); | |
11093 | assert_eq!(r, e); | |
11094 | } | |
11095 | ||
11096 | #[simd_test(enable = "neon")] | |
11097 | unsafe fn test_vcvtq_n_f64_u64() { | |
11098 | let a: u64x2 = u64x2::new(1, 2); | |
11099 | let e: f64x2 = f64x2::new(0.25, 0.5); | |
11100 | let r: f64x2 = transmute(vcvtq_n_f64_u64::<2>(transmute(a))); | |
11101 | assert_eq!(r, e); | |
11102 | } | |
11103 | ||
11104 | #[simd_test(enable = "neon")] | |
11105 | unsafe fn test_vcvts_n_f32_u32() { | |
11106 | let a: u32 = 1; | |
11107 | let e: f32 = 0.25; | |
11108 | let r: f32 = transmute(vcvts_n_f32_u32::<2>(transmute(a))); | |
11109 | assert_eq!(r, e); | |
11110 | } | |
11111 | ||
11112 | #[simd_test(enable = "neon")] | |
11113 | unsafe fn test_vcvtd_n_f64_u64() { | |
11114 | let a: u64 = 1; | |
11115 | let e: f64 = 0.25; | |
11116 | let r: f64 = transmute(vcvtd_n_f64_u64::<2>(transmute(a))); | |
11117 | assert_eq!(r, e); | |
11118 | } | |
11119 | ||
11120 | #[simd_test(enable = "neon")] | |
11121 | unsafe fn test_vcvt_n_s64_f64() { | |
11122 | let a: f64 = 0.25; | |
11123 | let e: i64x1 = i64x1::new(1); | |
11124 | let r: i64x1 = transmute(vcvt_n_s64_f64::<2>(transmute(a))); | |
11125 | assert_eq!(r, e); | |
11126 | } | |
11127 | ||
11128 | #[simd_test(enable = "neon")] | |
11129 | unsafe fn test_vcvtq_n_s64_f64() { | |
11130 | let a: f64x2 = f64x2::new(0.25, 0.5); | |
11131 | let e: i64x2 = i64x2::new(1, 2); | |
11132 | let r: i64x2 = transmute(vcvtq_n_s64_f64::<2>(transmute(a))); | |
11133 | assert_eq!(r, e); | |
11134 | } | |
11135 | ||
11136 | #[simd_test(enable = "neon")] | |
11137 | unsafe fn test_vcvts_n_s32_f32() { | |
11138 | let a: f32 = 0.25; | |
11139 | let e: i32 = 1; | |
11140 | let r: i32 = transmute(vcvts_n_s32_f32::<2>(transmute(a))); | |
11141 | assert_eq!(r, e); | |
11142 | } | |
11143 | ||
11144 | #[simd_test(enable = "neon")] | |
11145 | unsafe fn test_vcvtd_n_s64_f64() { | |
11146 | let a: f64 = 0.25; | |
11147 | let e: i64 = 1; | |
11148 | let r: i64 = transmute(vcvtd_n_s64_f64::<2>(transmute(a))); | |
11149 | assert_eq!(r, e); | |
11150 | } | |
11151 | ||
11152 | #[simd_test(enable = "neon")] | |
11153 | unsafe fn test_vcvt_n_u64_f64() { | |
11154 | let a: f64 = 0.25; | |
11155 | let e: u64x1 = u64x1::new(1); | |
11156 | let r: u64x1 = transmute(vcvt_n_u64_f64::<2>(transmute(a))); | |
11157 | assert_eq!(r, e); | |
11158 | } | |
11159 | ||
11160 | #[simd_test(enable = "neon")] | |
11161 | unsafe fn test_vcvtq_n_u64_f64() { | |
11162 | let a: f64x2 = f64x2::new(0.25, 0.5); | |
11163 | let e: u64x2 = u64x2::new(1, 2); | |
11164 | let r: u64x2 = transmute(vcvtq_n_u64_f64::<2>(transmute(a))); | |
11165 | assert_eq!(r, e); | |
11166 | } | |
11167 | ||
11168 | #[simd_test(enable = "neon")] | |
11169 | unsafe fn test_vcvts_n_u32_f32() { | |
11170 | let a: f32 = 0.25; | |
11171 | let e: u32 = 1; | |
11172 | let r: u32 = transmute(vcvts_n_u32_f32::<2>(transmute(a))); | |
11173 | assert_eq!(r, e); | |
11174 | } | |
11175 | ||
11176 | #[simd_test(enable = "neon")] | |
11177 | unsafe fn test_vcvtd_n_u64_f64() { | |
11178 | let a: f64 = 0.25; | |
11179 | let e: u64 = 1; | |
11180 | let r: u64 = transmute(vcvtd_n_u64_f64::<2>(transmute(a))); | |
11181 | assert_eq!(r, e); | |
11182 | } | |
11183 | ||
11184 | #[simd_test(enable = "neon")] | |
11185 | unsafe fn test_vcvts_f32_s32() { | |
11186 | let a: i32 = 1; | |
11187 | let e: f32 = 1.; | |
11188 | let r: f32 = transmute(vcvts_f32_s32(transmute(a))); | |
11189 | assert_eq!(r, e); | |
11190 | } | |
11191 | ||
11192 | #[simd_test(enable = "neon")] | |
11193 | unsafe fn test_vcvtd_f64_s64() { | |
11194 | let a: i64 = 1; | |
11195 | let e: f64 = 1.; | |
11196 | let r: f64 = transmute(vcvtd_f64_s64(transmute(a))); | |
11197 | assert_eq!(r, e); | |
11198 | } | |
11199 | ||
11200 | #[simd_test(enable = "neon")] | |
11201 | unsafe fn test_vcvts_f32_u32() { | |
11202 | let a: u32 = 1; | |
11203 | let e: f32 = 1.; | |
11204 | let r: f32 = transmute(vcvts_f32_u32(transmute(a))); | |
11205 | assert_eq!(r, e); | |
11206 | } | |
11207 | ||
11208 | #[simd_test(enable = "neon")] | |
11209 | unsafe fn test_vcvtd_f64_u64() { | |
11210 | let a: u64 = 1; | |
11211 | let e: f64 = 1.; | |
11212 | let r: f64 = transmute(vcvtd_f64_u64(transmute(a))); | |
11213 | assert_eq!(r, e); | |
11214 | } | |
11215 | ||
11216 | #[simd_test(enable = "neon")] | |
11217 | unsafe fn test_vcvts_s32_f32() { | |
11218 | let a: f32 = 1.; | |
11219 | let e: i32 = 1; | |
11220 | let r: i32 = transmute(vcvts_s32_f32(transmute(a))); | |
11221 | assert_eq!(r, e); | |
11222 | } | |
11223 | ||
11224 | #[simd_test(enable = "neon")] | |
11225 | unsafe fn test_vcvtd_s64_f64() { | |
11226 | let a: f64 = 1.; | |
11227 | let e: i64 = 1; | |
11228 | let r: i64 = transmute(vcvtd_s64_f64(transmute(a))); | |
11229 | assert_eq!(r, e); | |
11230 | } | |
11231 | ||
11232 | #[simd_test(enable = "neon")] | |
11233 | unsafe fn test_vcvts_u32_f32() { | |
11234 | let a: f32 = 1.; | |
11235 | let e: u32 = 1; | |
11236 | let r: u32 = transmute(vcvts_u32_f32(transmute(a))); | |
11237 | assert_eq!(r, e); | |
11238 | } | |
11239 | ||
11240 | #[simd_test(enable = "neon")] | |
11241 | unsafe fn test_vcvtd_u64_f64() { | |
11242 | let a: f64 = 1.; | |
11243 | let e: u64 = 1; | |
11244 | let r: u64 = transmute(vcvtd_u64_f64(transmute(a))); | |
11245 | assert_eq!(r, e); | |
11246 | } | |
11247 | ||
11248 | #[simd_test(enable = "neon")] | |
11249 | unsafe fn test_vcvt_s64_f64() { | |
11250 | let a: f64 = -1.1; | |
11251 | let e: i64x1 = i64x1::new(-1); | |
11252 | let r: i64x1 = transmute(vcvt_s64_f64(transmute(a))); | |
11253 | assert_eq!(r, e); | |
11254 | } | |
11255 | ||
11256 | #[simd_test(enable = "neon")] | |
11257 | unsafe fn test_vcvtq_s64_f64() { | |
11258 | let a: f64x2 = f64x2::new(-1.1, 2.1); | |
11259 | let e: i64x2 = i64x2::new(-1, 2); | |
11260 | let r: i64x2 = transmute(vcvtq_s64_f64(transmute(a))); | |
11261 | assert_eq!(r, e); | |
11262 | } | |
11263 | ||
11264 | #[simd_test(enable = "neon")] | |
11265 | unsafe fn test_vcvt_u64_f64() { | |
11266 | let a: f64 = 1.1; | |
11267 | let e: u64x1 = u64x1::new(1); | |
11268 | let r: u64x1 = transmute(vcvt_u64_f64(transmute(a))); | |
11269 | assert_eq!(r, e); | |
11270 | } | |
11271 | ||
11272 | #[simd_test(enable = "neon")] | |
11273 | unsafe fn test_vcvtq_u64_f64() { | |
11274 | let a: f64x2 = f64x2::new(1.1, 2.1); | |
11275 | let e: u64x2 = u64x2::new(1, 2); | |
11276 | let r: u64x2 = transmute(vcvtq_u64_f64(transmute(a))); | |
11277 | assert_eq!(r, e); | |
11278 | } | |
11279 | ||
11280 | #[simd_test(enable = "neon")] | |
11281 | unsafe fn test_vcvta_s32_f32() { | |
11282 | let a: f32x2 = f32x2::new(-1.1, 2.1); | |
11283 | let e: i32x2 = i32x2::new(-1, 2); | |
11284 | let r: i32x2 = transmute(vcvta_s32_f32(transmute(a))); | |
11285 | assert_eq!(r, e); | |
11286 | } | |
11287 | ||
11288 | #[simd_test(enable = "neon")] | |
11289 | unsafe fn test_vcvtaq_s32_f32() { | |
11290 | let a: f32x4 = f32x4::new(-1.1, 2.1, -2.9, 3.9); | |
11291 | let e: i32x4 = i32x4::new(-1, 2, -3, 4); | |
11292 | let r: i32x4 = transmute(vcvtaq_s32_f32(transmute(a))); | |
11293 | assert_eq!(r, e); | |
11294 | } | |
11295 | ||
11296 | #[simd_test(enable = "neon")] | |
11297 | unsafe fn test_vcvta_s64_f64() { | |
11298 | let a: f64 = -1.1; | |
11299 | let e: i64x1 = i64x1::new(-1); | |
11300 | let r: i64x1 = transmute(vcvta_s64_f64(transmute(a))); | |
11301 | assert_eq!(r, e); | |
11302 | } | |
11303 | ||
11304 | #[simd_test(enable = "neon")] | |
11305 | unsafe fn test_vcvtaq_s64_f64() { | |
11306 | let a: f64x2 = f64x2::new(-1.1, 2.1); | |
11307 | let e: i64x2 = i64x2::new(-1, 2); | |
11308 | let r: i64x2 = transmute(vcvtaq_s64_f64(transmute(a))); | |
11309 | assert_eq!(r, e); | |
11310 | } | |
11311 | ||
11312 | #[simd_test(enable = "neon")] | |
11313 | unsafe fn test_vcvtas_s32_f32() { | |
11314 | let a: f32 = 2.9; | |
11315 | let e: i32 = 3; | |
11316 | let r: i32 = transmute(vcvtas_s32_f32(transmute(a))); | |
11317 | assert_eq!(r, e); | |
11318 | } | |
11319 | ||
11320 | #[simd_test(enable = "neon")] | |
11321 | unsafe fn test_vcvtad_s64_f64() { | |
11322 | let a: f64 = 2.9; | |
11323 | let e: i64 = 3; | |
11324 | let r: i64 = transmute(vcvtad_s64_f64(transmute(a))); | |
11325 | assert_eq!(r, e); | |
11326 | } | |
11327 | ||
11328 | #[simd_test(enable = "neon")] | |
11329 | unsafe fn test_vcvtas_u32_f32() { | |
11330 | let a: f32 = 2.9; | |
11331 | let e: u32 = 3; | |
11332 | let r: u32 = transmute(vcvtas_u32_f32(transmute(a))); | |
11333 | assert_eq!(r, e); | |
11334 | } | |
11335 | ||
11336 | #[simd_test(enable = "neon")] | |
11337 | unsafe fn test_vcvtad_u64_f64() { | |
11338 | let a: f64 = 2.9; | |
11339 | let e: u64 = 3; | |
11340 | let r: u64 = transmute(vcvtad_u64_f64(transmute(a))); | |
11341 | assert_eq!(r, e); | |
11342 | } | |
11343 | ||
11344 | #[simd_test(enable = "neon")] | |
11345 | unsafe fn test_vcvtn_s32_f32() { | |
11346 | let a: f32x2 = f32x2::new(-1.5, 2.1); | |
11347 | let e: i32x2 = i32x2::new(-2, 2); | |
11348 | let r: i32x2 = transmute(vcvtn_s32_f32(transmute(a))); | |
11349 | assert_eq!(r, e); | |
11350 | } | |
11351 | ||
11352 | #[simd_test(enable = "neon")] | |
11353 | unsafe fn test_vcvtnq_s32_f32() { | |
11354 | let a: f32x4 = f32x4::new(-1.5, 2.1, -2.9, 3.9); | |
11355 | let e: i32x4 = i32x4::new(-2, 2, -3, 4); | |
11356 | let r: i32x4 = transmute(vcvtnq_s32_f32(transmute(a))); | |
11357 | assert_eq!(r, e); | |
11358 | } | |
11359 | ||
11360 | #[simd_test(enable = "neon")] | |
11361 | unsafe fn test_vcvtn_s64_f64() { | |
11362 | let a: f64 = -1.5; | |
11363 | let e: i64x1 = i64x1::new(-2); | |
11364 | let r: i64x1 = transmute(vcvtn_s64_f64(transmute(a))); | |
11365 | assert_eq!(r, e); | |
11366 | } | |
11367 | ||
11368 | #[simd_test(enable = "neon")] | |
11369 | unsafe fn test_vcvtnq_s64_f64() { | |
11370 | let a: f64x2 = f64x2::new(-1.5, 2.1); | |
11371 | let e: i64x2 = i64x2::new(-2, 2); | |
11372 | let r: i64x2 = transmute(vcvtnq_s64_f64(transmute(a))); | |
11373 | assert_eq!(r, e); | |
11374 | } | |
11375 | ||
11376 | #[simd_test(enable = "neon")] | |
11377 | unsafe fn test_vcvtns_s32_f32() { | |
11378 | let a: f32 = -1.5; | |
11379 | let e: i32 = -2; | |
11380 | let r: i32 = transmute(vcvtns_s32_f32(transmute(a))); | |
11381 | assert_eq!(r, e); | |
11382 | } | |
11383 | ||
11384 | #[simd_test(enable = "neon")] | |
11385 | unsafe fn test_vcvtnd_s64_f64() { | |
11386 | let a: f64 = -1.5; | |
11387 | let e: i64 = -2; | |
11388 | let r: i64 = transmute(vcvtnd_s64_f64(transmute(a))); | |
11389 | assert_eq!(r, e); | |
11390 | } | |
11391 | ||
11392 | #[simd_test(enable = "neon")] | |
11393 | unsafe fn test_vcvtm_s32_f32() { | |
11394 | let a: f32x2 = f32x2::new(-1.1, 2.1); | |
11395 | let e: i32x2 = i32x2::new(-2, 2); | |
11396 | let r: i32x2 = transmute(vcvtm_s32_f32(transmute(a))); | |
11397 | assert_eq!(r, e); | |
11398 | } | |
11399 | ||
11400 | #[simd_test(enable = "neon")] | |
11401 | unsafe fn test_vcvtmq_s32_f32() { | |
11402 | let a: f32x4 = f32x4::new(-1.1, 2.1, -2.9, 3.9); | |
11403 | let e: i32x4 = i32x4::new(-2, 2, -3, 3); | |
11404 | let r: i32x4 = transmute(vcvtmq_s32_f32(transmute(a))); | |
11405 | assert_eq!(r, e); | |
11406 | } | |
11407 | ||
11408 | #[simd_test(enable = "neon")] | |
11409 | unsafe fn test_vcvtm_s64_f64() { | |
11410 | let a: f64 = -1.1; | |
11411 | let e: i64x1 = i64x1::new(-2); | |
11412 | let r: i64x1 = transmute(vcvtm_s64_f64(transmute(a))); | |
11413 | assert_eq!(r, e); | |
11414 | } | |
11415 | ||
11416 | #[simd_test(enable = "neon")] | |
11417 | unsafe fn test_vcvtmq_s64_f64() { | |
11418 | let a: f64x2 = f64x2::new(-1.1, 2.1); | |
11419 | let e: i64x2 = i64x2::new(-2, 2); | |
11420 | let r: i64x2 = transmute(vcvtmq_s64_f64(transmute(a))); | |
11421 | assert_eq!(r, e); | |
11422 | } | |
11423 | ||
11424 | #[simd_test(enable = "neon")] | |
11425 | unsafe fn test_vcvtms_s32_f32() { | |
11426 | let a: f32 = -1.1; | |
11427 | let e: i32 = -2; | |
11428 | let r: i32 = transmute(vcvtms_s32_f32(transmute(a))); | |
11429 | assert_eq!(r, e); | |
11430 | } | |
11431 | ||
11432 | #[simd_test(enable = "neon")] | |
11433 | unsafe fn test_vcvtmd_s64_f64() { | |
11434 | let a: f64 = -1.1; | |
11435 | let e: i64 = -2; | |
11436 | let r: i64 = transmute(vcvtmd_s64_f64(transmute(a))); | |
11437 | assert_eq!(r, e); | |
11438 | } | |
11439 | ||
11440 | #[simd_test(enable = "neon")] | |
11441 | unsafe fn test_vcvtp_s32_f32() { | |
11442 | let a: f32x2 = f32x2::new(-1.1, 2.1); | |
11443 | let e: i32x2 = i32x2::new(-1, 3); | |
11444 | let r: i32x2 = transmute(vcvtp_s32_f32(transmute(a))); | |
11445 | assert_eq!(r, e); | |
11446 | } | |
11447 | ||
11448 | #[simd_test(enable = "neon")] | |
11449 | unsafe fn test_vcvtpq_s32_f32() { | |
11450 | let a: f32x4 = f32x4::new(-1.1, 2.1, -2.9, 3.9); | |
11451 | let e: i32x4 = i32x4::new(-1, 3, -2, 4); | |
11452 | let r: i32x4 = transmute(vcvtpq_s32_f32(transmute(a))); | |
11453 | assert_eq!(r, e); | |
11454 | } | |
11455 | ||
11456 | #[simd_test(enable = "neon")] | |
11457 | unsafe fn test_vcvtp_s64_f64() { | |
11458 | let a: f64 = -1.1; | |
11459 | let e: i64x1 = i64x1::new(-1); | |
11460 | let r: i64x1 = transmute(vcvtp_s64_f64(transmute(a))); | |
11461 | assert_eq!(r, e); | |
11462 | } | |
11463 | ||
11464 | #[simd_test(enable = "neon")] | |
11465 | unsafe fn test_vcvtpq_s64_f64() { | |
11466 | let a: f64x2 = f64x2::new(-1.1, 2.1); | |
11467 | let e: i64x2 = i64x2::new(-1, 3); | |
11468 | let r: i64x2 = transmute(vcvtpq_s64_f64(transmute(a))); | |
11469 | assert_eq!(r, e); | |
11470 | } | |
11471 | ||
11472 | #[simd_test(enable = "neon")] | |
11473 | unsafe fn test_vcvtps_s32_f32() { | |
11474 | let a: f32 = -1.1; | |
11475 | let e: i32 = -1; | |
11476 | let r: i32 = transmute(vcvtps_s32_f32(transmute(a))); | |
11477 | assert_eq!(r, e); | |
11478 | } | |
11479 | ||
11480 | #[simd_test(enable = "neon")] | |
11481 | unsafe fn test_vcvtpd_s64_f64() { | |
11482 | let a: f64 = -1.1; | |
11483 | let e: i64 = -1; | |
11484 | let r: i64 = transmute(vcvtpd_s64_f64(transmute(a))); | |
11485 | assert_eq!(r, e); | |
11486 | } | |
11487 | ||
11488 | #[simd_test(enable = "neon")] | |
11489 | unsafe fn test_vcvta_u32_f32() { | |
11490 | let a: f32x2 = f32x2::new(1.1, 2.1); | |
11491 | let e: u32x2 = u32x2::new(1, 2); | |
11492 | let r: u32x2 = transmute(vcvta_u32_f32(transmute(a))); | |
11493 | assert_eq!(r, e); | |
11494 | } | |
11495 | ||
11496 | #[simd_test(enable = "neon")] | |
11497 | unsafe fn test_vcvtaq_u32_f32() { | |
11498 | let a: f32x4 = f32x4::new(1.1, 2.1, 2.9, 3.9); | |
11499 | let e: u32x4 = u32x4::new(1, 2, 3, 4); | |
11500 | let r: u32x4 = transmute(vcvtaq_u32_f32(transmute(a))); | |
11501 | assert_eq!(r, e); | |
11502 | } | |
11503 | ||
11504 | #[simd_test(enable = "neon")] | |
11505 | unsafe fn test_vcvta_u64_f64() { | |
11506 | let a: f64 = 1.1; | |
11507 | let e: u64x1 = u64x1::new(1); | |
11508 | let r: u64x1 = transmute(vcvta_u64_f64(transmute(a))); | |
11509 | assert_eq!(r, e); | |
11510 | } | |
11511 | ||
11512 | #[simd_test(enable = "neon")] | |
11513 | unsafe fn test_vcvtaq_u64_f64() { | |
11514 | let a: f64x2 = f64x2::new(1.1, 2.1); | |
11515 | let e: u64x2 = u64x2::new(1, 2); | |
11516 | let r: u64x2 = transmute(vcvtaq_u64_f64(transmute(a))); | |
11517 | assert_eq!(r, e); | |
11518 | } | |
11519 | ||
11520 | #[simd_test(enable = "neon")] | |
11521 | unsafe fn test_vcvtn_u32_f32() { | |
11522 | let a: f32x2 = f32x2::new(1.5, 2.1); | |
11523 | let e: u32x2 = u32x2::new(2, 2); | |
11524 | let r: u32x2 = transmute(vcvtn_u32_f32(transmute(a))); | |
11525 | assert_eq!(r, e); | |
11526 | } | |
11527 | ||
11528 | #[simd_test(enable = "neon")] | |
11529 | unsafe fn test_vcvtnq_u32_f32() { | |
11530 | let a: f32x4 = f32x4::new(1.5, 2.1, 2.9, 3.9); | |
11531 | let e: u32x4 = u32x4::new(2, 2, 3, 4); | |
11532 | let r: u32x4 = transmute(vcvtnq_u32_f32(transmute(a))); | |
11533 | assert_eq!(r, e); | |
11534 | } | |
11535 | ||
11536 | #[simd_test(enable = "neon")] | |
11537 | unsafe fn test_vcvtn_u64_f64() { | |
11538 | let a: f64 = 1.5; | |
11539 | let e: u64x1 = u64x1::new(2); | |
11540 | let r: u64x1 = transmute(vcvtn_u64_f64(transmute(a))); | |
11541 | assert_eq!(r, e); | |
11542 | } | |
11543 | ||
11544 | #[simd_test(enable = "neon")] | |
11545 | unsafe fn test_vcvtnq_u64_f64() { | |
11546 | let a: f64x2 = f64x2::new(1.5, 2.1); | |
11547 | let e: u64x2 = u64x2::new(2, 2); | |
11548 | let r: u64x2 = transmute(vcvtnq_u64_f64(transmute(a))); | |
11549 | assert_eq!(r, e); | |
11550 | } | |
11551 | ||
11552 | #[simd_test(enable = "neon")] | |
11553 | unsafe fn test_vcvtns_u32_f32() { | |
11554 | let a: f32 = 1.5; | |
11555 | let e: u32 = 2; | |
11556 | let r: u32 = transmute(vcvtns_u32_f32(transmute(a))); | |
11557 | assert_eq!(r, e); | |
11558 | } | |
11559 | ||
11560 | #[simd_test(enable = "neon")] | |
11561 | unsafe fn test_vcvtnd_u64_f64() { | |
11562 | let a: f64 = 1.5; | |
11563 | let e: u64 = 2; | |
11564 | let r: u64 = transmute(vcvtnd_u64_f64(transmute(a))); | |
11565 | assert_eq!(r, e); | |
11566 | } | |
11567 | ||
11568 | #[simd_test(enable = "neon")] | |
11569 | unsafe fn test_vcvtm_u32_f32() { | |
11570 | let a: f32x2 = f32x2::new(1.1, 2.1); | |
11571 | let e: u32x2 = u32x2::new(1, 2); | |
11572 | let r: u32x2 = transmute(vcvtm_u32_f32(transmute(a))); | |
11573 | assert_eq!(r, e); | |
11574 | } | |
11575 | ||
11576 | #[simd_test(enable = "neon")] | |
11577 | unsafe fn test_vcvtmq_u32_f32() { | |
11578 | let a: f32x4 = f32x4::new(1.1, 2.1, 2.9, 3.9); | |
11579 | let e: u32x4 = u32x4::new(1, 2, 2, 3); | |
11580 | let r: u32x4 = transmute(vcvtmq_u32_f32(transmute(a))); | |
11581 | assert_eq!(r, e); | |
11582 | } | |
11583 | ||
11584 | #[simd_test(enable = "neon")] | |
11585 | unsafe fn test_vcvtm_u64_f64() { | |
11586 | let a: f64 = 1.1; | |
11587 | let e: u64x1 = u64x1::new(1); | |
11588 | let r: u64x1 = transmute(vcvtm_u64_f64(transmute(a))); | |
11589 | assert_eq!(r, e); | |
11590 | } | |
11591 | ||
11592 | #[simd_test(enable = "neon")] | |
11593 | unsafe fn test_vcvtmq_u64_f64() { | |
11594 | let a: f64x2 = f64x2::new(1.1, 2.1); | |
11595 | let e: u64x2 = u64x2::new(1, 2); | |
11596 | let r: u64x2 = transmute(vcvtmq_u64_f64(transmute(a))); | |
11597 | assert_eq!(r, e); | |
11598 | } | |
11599 | ||
11600 | #[simd_test(enable = "neon")] | |
11601 | unsafe fn test_vcvtms_u32_f32() { | |
11602 | let a: f32 = 1.1; | |
11603 | let e: u32 = 1; | |
11604 | let r: u32 = transmute(vcvtms_u32_f32(transmute(a))); | |
11605 | assert_eq!(r, e); | |
11606 | } | |
11607 | ||
11608 | #[simd_test(enable = "neon")] | |
11609 | unsafe fn test_vcvtmd_u64_f64() { | |
11610 | let a: f64 = 1.1; | |
11611 | let e: u64 = 1; | |
11612 | let r: u64 = transmute(vcvtmd_u64_f64(transmute(a))); | |
11613 | assert_eq!(r, e); | |
11614 | } | |
11615 | ||
11616 | #[simd_test(enable = "neon")] | |
11617 | unsafe fn test_vcvtp_u32_f32() { | |
11618 | let a: f32x2 = f32x2::new(1.1, 2.1); | |
11619 | let e: u32x2 = u32x2::new(2, 3); | |
11620 | let r: u32x2 = transmute(vcvtp_u32_f32(transmute(a))); | |
11621 | assert_eq!(r, e); | |
11622 | } | |
11623 | ||
11624 | #[simd_test(enable = "neon")] | |
11625 | unsafe fn test_vcvtpq_u32_f32() { | |
11626 | let a: f32x4 = f32x4::new(1.1, 2.1, 2.9, 3.9); | |
11627 | let e: u32x4 = u32x4::new(2, 3, 3, 4); | |
11628 | let r: u32x4 = transmute(vcvtpq_u32_f32(transmute(a))); | |
11629 | assert_eq!(r, e); | |
11630 | } | |
11631 | ||
11632 | #[simd_test(enable = "neon")] | |
11633 | unsafe fn test_vcvtp_u64_f64() { | |
11634 | let a: f64 = 1.1; | |
11635 | let e: u64x1 = u64x1::new(2); | |
11636 | let r: u64x1 = transmute(vcvtp_u64_f64(transmute(a))); | |
11637 | assert_eq!(r, e); | |
11638 | } | |
11639 | ||
11640 | #[simd_test(enable = "neon")] | |
11641 | unsafe fn test_vcvtpq_u64_f64() { | |
11642 | let a: f64x2 = f64x2::new(1.1, 2.1); | |
11643 | let e: u64x2 = u64x2::new(2, 3); | |
11644 | let r: u64x2 = transmute(vcvtpq_u64_f64(transmute(a))); | |
11645 | assert_eq!(r, e); | |
11646 | } | |
11647 | ||
11648 | #[simd_test(enable = "neon")] | |
11649 | unsafe fn test_vcvtps_u32_f32() { | |
11650 | let a: f32 = 1.1; | |
11651 | let e: u32 = 2; | |
11652 | let r: u32 = transmute(vcvtps_u32_f32(transmute(a))); | |
11653 | assert_eq!(r, e); | |
11654 | } | |
11655 | ||
11656 | #[simd_test(enable = "neon")] | |
11657 | unsafe fn test_vcvtpd_u64_f64() { | |
11658 | let a: f64 = 1.1; | |
11659 | let e: u64 = 2; | |
11660 | let r: u64 = transmute(vcvtpd_u64_f64(transmute(a))); | |
11661 | assert_eq!(r, e); | |
11662 | } | |
11663 | ||
11664 | #[simd_test(enable = "neon")] | |
11665 | unsafe fn test_vdupq_laneq_p64() { | |
11666 | let a: i64x2 = i64x2::new(1, 1); | |
11667 | let e: i64x2 = i64x2::new(1, 1); | |
11668 | let r: i64x2 = transmute(vdupq_laneq_p64::<1>(transmute(a))); | |
11669 | assert_eq!(r, e); | |
11670 | } | |
11671 | ||
11672 | #[simd_test(enable = "neon")] | |
11673 | unsafe fn test_vdupq_lane_p64() { | |
11674 | let a: i64x1 = i64x1::new(1); | |
11675 | let e: i64x2 = i64x2::new(1, 1); | |
11676 | let r: i64x2 = transmute(vdupq_lane_p64::<0>(transmute(a))); | |
11677 | assert_eq!(r, e); | |
11678 | } | |
11679 | ||
11680 | #[simd_test(enable = "neon")] | |
11681 | unsafe fn test_vdupq_laneq_f64() { | |
11682 | let a: f64x2 = f64x2::new(1., 1.); | |
11683 | let e: f64x2 = f64x2::new(1., 1.); | |
11684 | let r: f64x2 = transmute(vdupq_laneq_f64::<1>(transmute(a))); | |
11685 | assert_eq!(r, e); | |
11686 | } | |
11687 | ||
11688 | #[simd_test(enable = "neon")] | |
11689 | unsafe fn test_vdupq_lane_f64() { | |
11690 | let a: f64 = 1.; | |
11691 | let e: f64x2 = f64x2::new(1., 1.); | |
11692 | let r: f64x2 = transmute(vdupq_lane_f64::<0>(transmute(a))); | |
11693 | assert_eq!(r, e); | |
11694 | } | |
11695 | ||
11696 | #[simd_test(enable = "neon")] | |
11697 | unsafe fn test_vdup_lane_p64() { | |
11698 | let a: i64x1 = i64x1::new(0); | |
11699 | let e: i64x1 = i64x1::new(0); | |
11700 | let r: i64x1 = transmute(vdup_lane_p64::<0>(transmute(a))); | |
11701 | assert_eq!(r, e); | |
11702 | } | |
11703 | ||
11704 | #[simd_test(enable = "neon")] | |
11705 | unsafe fn test_vdup_lane_f64() { | |
11706 | let a: f64 = 0.; | |
11707 | let e: f64 = 0.; | |
11708 | let r: f64 = transmute(vdup_lane_f64::<0>(transmute(a))); | |
11709 | assert_eq!(r, e); | |
11710 | } | |
11711 | ||
11712 | #[simd_test(enable = "neon")] | |
11713 | unsafe fn test_vdup_laneq_p64() { | |
11714 | let a: i64x2 = i64x2::new(0, 1); | |
11715 | let e: i64x1 = i64x1::new(1); | |
11716 | let r: i64x1 = transmute(vdup_laneq_p64::<1>(transmute(a))); | |
11717 | assert_eq!(r, e); | |
11718 | } | |
11719 | ||
11720 | #[simd_test(enable = "neon")] | |
11721 | unsafe fn test_vdup_laneq_f64() { | |
11722 | let a: f64x2 = f64x2::new(0., 1.); | |
11723 | let e: f64 = 1.; | |
11724 | let r: f64 = transmute(vdup_laneq_f64::<1>(transmute(a))); | |
11725 | assert_eq!(r, e); | |
11726 | } | |
11727 | ||
11728 | #[simd_test(enable = "neon")] | |
11729 | unsafe fn test_vdupb_lane_s8() { | |
11730 | let a: i8x8 = i8x8::new(1, 1, 1, 4, 1, 6, 7, 8); | |
11731 | let e: i8 = 1; | |
11732 | let r: i8 = transmute(vdupb_lane_s8::<4>(transmute(a))); | |
11733 | assert_eq!(r, e); | |
11734 | } | |
11735 | ||
11736 | #[simd_test(enable = "neon")] | |
11737 | unsafe fn test_vdupb_laneq_s8() { | |
11738 | let a: i8x16 = i8x16::new(1, 1, 1, 4, 1, 6, 7, 8, 1, 10, 11, 12, 13, 14, 15, 16); | |
11739 | let e: i8 = 1; | |
11740 | let r: i8 = transmute(vdupb_laneq_s8::<8>(transmute(a))); | |
11741 | assert_eq!(r, e); | |
11742 | } | |
11743 | ||
11744 | #[simd_test(enable = "neon")] | |
11745 | unsafe fn test_vduph_lane_s16() { | |
11746 | let a: i16x4 = i16x4::new(1, 1, 1, 4); | |
11747 | let e: i16 = 1; | |
11748 | let r: i16 = transmute(vduph_lane_s16::<2>(transmute(a))); | |
11749 | assert_eq!(r, e); | |
11750 | } | |
11751 | ||
11752 | #[simd_test(enable = "neon")] | |
11753 | unsafe fn test_vduph_laneq_s16() { | |
11754 | let a: i16x8 = i16x8::new(1, 1, 1, 4, 1, 6, 7, 8); | |
11755 | let e: i16 = 1; | |
11756 | let r: i16 = transmute(vduph_laneq_s16::<4>(transmute(a))); | |
11757 | assert_eq!(r, e); | |
11758 | } | |
11759 | ||
11760 | #[simd_test(enable = "neon")] | |
11761 | unsafe fn test_vdups_lane_s32() { | |
11762 | let a: i32x2 = i32x2::new(1, 1); | |
11763 | let e: i32 = 1; | |
11764 | let r: i32 = transmute(vdups_lane_s32::<1>(transmute(a))); | |
11765 | assert_eq!(r, e); | |
11766 | } | |
11767 | ||
11768 | #[simd_test(enable = "neon")] | |
11769 | unsafe fn test_vdups_laneq_s32() { | |
11770 | let a: i32x4 = i32x4::new(1, 1, 1, 4); | |
11771 | let e: i32 = 1; | |
11772 | let r: i32 = transmute(vdups_laneq_s32::<2>(transmute(a))); | |
11773 | assert_eq!(r, e); | |
11774 | } | |
11775 | ||
11776 | #[simd_test(enable = "neon")] | |
11777 | unsafe fn test_vdupd_lane_s64() { | |
11778 | let a: i64x1 = i64x1::new(1); | |
11779 | let e: i64 = 1; | |
11780 | let r: i64 = transmute(vdupd_lane_s64::<0>(transmute(a))); | |
11781 | assert_eq!(r, e); | |
11782 | } | |
11783 | ||
11784 | #[simd_test(enable = "neon")] | |
11785 | unsafe fn test_vdupd_laneq_s64() { | |
11786 | let a: i64x2 = i64x2::new(1, 1); | |
11787 | let e: i64 = 1; | |
11788 | let r: i64 = transmute(vdupd_laneq_s64::<1>(transmute(a))); | |
11789 | assert_eq!(r, e); | |
11790 | } | |
11791 | ||
11792 | #[simd_test(enable = "neon")] | |
11793 | unsafe fn test_vdupb_lane_u8() { | |
11794 | let a: u8x8 = u8x8::new(1, 1, 1, 4, 1, 6, 7, 8); | |
11795 | let e: u8 = 1; | |
11796 | let r: u8 = transmute(vdupb_lane_u8::<4>(transmute(a))); | |
11797 | assert_eq!(r, e); | |
11798 | } | |
11799 | ||
11800 | #[simd_test(enable = "neon")] | |
11801 | unsafe fn test_vdupb_laneq_u8() { | |
11802 | let a: u8x16 = u8x16::new(1, 1, 1, 4, 1, 6, 7, 8, 1, 10, 11, 12, 13, 14, 15, 16); | |
11803 | let e: u8 = 1; | |
11804 | let r: u8 = transmute(vdupb_laneq_u8::<8>(transmute(a))); | |
11805 | assert_eq!(r, e); | |
11806 | } | |
11807 | ||
11808 | #[simd_test(enable = "neon")] | |
11809 | unsafe fn test_vduph_lane_u16() { | |
11810 | let a: u16x4 = u16x4::new(1, 1, 1, 4); | |
11811 | let e: u16 = 1; | |
11812 | let r: u16 = transmute(vduph_lane_u16::<2>(transmute(a))); | |
11813 | assert_eq!(r, e); | |
11814 | } | |
11815 | ||
11816 | #[simd_test(enable = "neon")] | |
11817 | unsafe fn test_vduph_laneq_u16() { | |
11818 | let a: u16x8 = u16x8::new(1, 1, 1, 4, 1, 6, 7, 8); | |
11819 | let e: u16 = 1; | |
11820 | let r: u16 = transmute(vduph_laneq_u16::<4>(transmute(a))); | |
11821 | assert_eq!(r, e); | |
11822 | } | |
11823 | ||
11824 | #[simd_test(enable = "neon")] | |
11825 | unsafe fn test_vdups_lane_u32() { | |
11826 | let a: u32x2 = u32x2::new(1, 1); | |
11827 | let e: u32 = 1; | |
11828 | let r: u32 = transmute(vdups_lane_u32::<1>(transmute(a))); | |
11829 | assert_eq!(r, e); | |
11830 | } | |
11831 | ||
11832 | #[simd_test(enable = "neon")] | |
11833 | unsafe fn test_vdups_laneq_u32() { | |
11834 | let a: u32x4 = u32x4::new(1, 1, 1, 4); | |
11835 | let e: u32 = 1; | |
11836 | let r: u32 = transmute(vdups_laneq_u32::<2>(transmute(a))); | |
11837 | assert_eq!(r, e); | |
11838 | } | |
11839 | ||
11840 | #[simd_test(enable = "neon")] | |
11841 | unsafe fn test_vdupd_lane_u64() { | |
11842 | let a: u64x1 = u64x1::new(1); | |
11843 | let e: u64 = 1; | |
11844 | let r: u64 = transmute(vdupd_lane_u64::<0>(transmute(a))); | |
11845 | assert_eq!(r, e); | |
11846 | } | |
11847 | ||
11848 | #[simd_test(enable = "neon")] | |
11849 | unsafe fn test_vdupd_laneq_u64() { | |
11850 | let a: u64x2 = u64x2::new(1, 1); | |
11851 | let e: u64 = 1; | |
11852 | let r: u64 = transmute(vdupd_laneq_u64::<1>(transmute(a))); | |
11853 | assert_eq!(r, e); | |
11854 | } | |
11855 | ||
11856 | #[simd_test(enable = "neon")] | |
11857 | unsafe fn test_vdupb_lane_p8() { | |
11858 | let a: i8x8 = i8x8::new(1, 1, 1, 4, 1, 6, 7, 8); | |
11859 | let e: p8 = 1; | |
11860 | let r: p8 = transmute(vdupb_lane_p8::<4>(transmute(a))); | |
11861 | assert_eq!(r, e); | |
11862 | } | |
11863 | ||
11864 | #[simd_test(enable = "neon")] | |
11865 | unsafe fn test_vdupb_laneq_p8() { | |
11866 | let a: i8x16 = i8x16::new(1, 1, 1, 4, 1, 6, 7, 8, 1, 10, 11, 12, 13, 14, 15, 16); | |
11867 | let e: p8 = 1; | |
11868 | let r: p8 = transmute(vdupb_laneq_p8::<8>(transmute(a))); | |
11869 | assert_eq!(r, e); | |
11870 | } | |
11871 | ||
11872 | #[simd_test(enable = "neon")] | |
11873 | unsafe fn test_vduph_lane_p16() { | |
11874 | let a: i16x4 = i16x4::new(1, 1, 1, 4); | |
11875 | let e: p16 = 1; | |
11876 | let r: p16 = transmute(vduph_lane_p16::<2>(transmute(a))); | |
11877 | assert_eq!(r, e); | |
11878 | } | |
11879 | ||
11880 | #[simd_test(enable = "neon")] | |
11881 | unsafe fn test_vduph_laneq_p16() { | |
11882 | let a: i16x8 = i16x8::new(1, 1, 1, 4, 1, 6, 7, 8); | |
11883 | let e: p16 = 1; | |
11884 | let r: p16 = transmute(vduph_laneq_p16::<4>(transmute(a))); | |
11885 | assert_eq!(r, e); | |
11886 | } | |
11887 | ||
11888 | #[simd_test(enable = "neon")] | |
11889 | unsafe fn test_vdups_lane_f32() { | |
11890 | let a: f32x2 = f32x2::new(1., 1.); | |
11891 | let e: f32 = 1.; | |
11892 | let r: f32 = transmute(vdups_lane_f32::<1>(transmute(a))); | |
11893 | assert_eq!(r, e); | |
11894 | } | |
11895 | ||
11896 | #[simd_test(enable = "neon")] | |
11897 | unsafe fn test_vdups_laneq_f32() { | |
11898 | let a: f32x4 = f32x4::new(1., 1., 1., 4.); | |
11899 | let e: f32 = 1.; | |
11900 | let r: f32 = transmute(vdups_laneq_f32::<2>(transmute(a))); | |
11901 | assert_eq!(r, e); | |
11902 | } | |
11903 | ||
11904 | #[simd_test(enable = "neon")] | |
11905 | unsafe fn test_vdupd_lane_f64() { | |
11906 | let a: f64 = 1.; | |
11907 | let e: f64 = 1.; | |
11908 | let r: f64 = transmute(vdupd_lane_f64::<0>(transmute(a))); | |
11909 | assert_eq!(r, e); | |
11910 | } | |
11911 | ||
11912 | #[simd_test(enable = "neon")] | |
11913 | unsafe fn test_vdupd_laneq_f64() { | |
11914 | let a: f64x2 = f64x2::new(1., 1.); | |
11915 | let e: f64 = 1.; | |
11916 | let r: f64 = transmute(vdupd_laneq_f64::<1>(transmute(a))); | |
11917 | assert_eq!(r, e); | |
11918 | } | |
11919 | ||
11920 | #[simd_test(enable = "neon")] | |
11921 | unsafe fn test_vextq_p64() { | |
11922 | let a: i64x2 = i64x2::new(0, 8); | |
11923 | let b: i64x2 = i64x2::new(9, 11); | |
11924 | let e: i64x2 = i64x2::new(8, 9); | |
11925 | let r: i64x2 = transmute(vextq_p64::<1>(transmute(a), transmute(b))); | |
11926 | assert_eq!(r, e); | |
11927 | } | |
11928 | ||
11929 | #[simd_test(enable = "neon")] | |
11930 | unsafe fn test_vextq_f64() { | |
11931 | let a: f64x2 = f64x2::new(0., 2.); | |
11932 | let b: f64x2 = f64x2::new(3., 4.); | |
11933 | let e: f64x2 = f64x2::new(2., 3.); | |
11934 | let r: f64x2 = transmute(vextq_f64::<1>(transmute(a), transmute(b))); | |
11935 | assert_eq!(r, e); | |
11936 | } | |
11937 | ||
11938 | #[simd_test(enable = "neon")] | |
11939 | unsafe fn test_vmla_f64() { | |
11940 | let a: f64 = 0.; | |
11941 | let b: f64 = 2.; | |
11942 | let c: f64 = 3.; | |
11943 | let e: f64 = 6.; | |
11944 | let r: f64 = transmute(vmla_f64(transmute(a), transmute(b), transmute(c))); | |
11945 | assert_eq!(r, e); | |
11946 | } | |
11947 | ||
11948 | #[simd_test(enable = "neon")] | |
11949 | unsafe fn test_vmlaq_f64() { | |
11950 | let a: f64x2 = f64x2::new(0., 1.); | |
11951 | let b: f64x2 = f64x2::new(2., 2.); | |
11952 | let c: f64x2 = f64x2::new(3., 3.); | |
11953 | let e: f64x2 = f64x2::new(6., 7.); | |
11954 | let r: f64x2 = transmute(vmlaq_f64(transmute(a), transmute(b), transmute(c))); | |
11955 | assert_eq!(r, e); | |
11956 | } | |
11957 | ||
11958 | #[simd_test(enable = "neon")] | |
11959 | unsafe fn test_vmlal_high_s8() { | |
11960 | let a: i16x8 = i16x8::new(8, 7, 6, 5, 4, 3, 2, 1); | |
11961 | let b: i8x16 = i8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); | |
11962 | let c: i8x16 = i8x16::new(3, 3, 0, 1, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7); | |
11963 | let e: i16x8 = i16x8::new(8, 9, 10, 11, 12, 13, 14, 15); | |
11964 | let r: i16x8 = transmute(vmlal_high_s8(transmute(a), transmute(b), transmute(c))); | |
11965 | assert_eq!(r, e); | |
11966 | } | |
11967 | ||
11968 | #[simd_test(enable = "neon")] | |
11969 | unsafe fn test_vmlal_high_s16() { | |
11970 | let a: i32x4 = i32x4::new(8, 7, 6, 5); | |
11971 | let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); | |
11972 | let c: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
11973 | let e: i32x4 = i32x4::new(8, 9, 10, 11); | |
11974 | let r: i32x4 = transmute(vmlal_high_s16(transmute(a), transmute(b), transmute(c))); | |
11975 | assert_eq!(r, e); | |
11976 | } | |
11977 | ||
11978 | #[simd_test(enable = "neon")] | |
11979 | unsafe fn test_vmlal_high_s32() { | |
11980 | let a: i64x2 = i64x2::new(8, 7); | |
11981 | let b: i32x4 = i32x4::new(2, 2, 2, 2); | |
11982 | let c: i32x4 = i32x4::new(3, 3, 0, 1); | |
11983 | let e: i64x2 = i64x2::new(8, 9); | |
11984 | let r: i64x2 = transmute(vmlal_high_s32(transmute(a), transmute(b), transmute(c))); | |
11985 | assert_eq!(r, e); | |
11986 | } | |
11987 | ||
11988 | #[simd_test(enable = "neon")] | |
11989 | unsafe fn test_vmlal_high_u8() { | |
11990 | let a: u16x8 = u16x8::new(8, 7, 6, 5, 4, 3, 2, 1); | |
11991 | let b: u8x16 = u8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); | |
11992 | let c: u8x16 = u8x16::new(3, 3, 0, 1, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7); | |
11993 | let e: u16x8 = u16x8::new(8, 9, 10, 11, 12, 13, 14, 15); | |
11994 | let r: u16x8 = transmute(vmlal_high_u8(transmute(a), transmute(b), transmute(c))); | |
11995 | assert_eq!(r, e); | |
11996 | } | |
11997 | ||
11998 | #[simd_test(enable = "neon")] | |
11999 | unsafe fn test_vmlal_high_u16() { | |
12000 | let a: u32x4 = u32x4::new(8, 7, 6, 5); | |
12001 | let b: u16x8 = u16x8::new(2, 2, 2, 2, 2, 2, 2, 2); | |
12002 | let c: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12003 | let e: u32x4 = u32x4::new(8, 9, 10, 11); | |
12004 | let r: u32x4 = transmute(vmlal_high_u16(transmute(a), transmute(b), transmute(c))); | |
12005 | assert_eq!(r, e); | |
12006 | } | |
12007 | ||
12008 | #[simd_test(enable = "neon")] | |
12009 | unsafe fn test_vmlal_high_u32() { | |
12010 | let a: u64x2 = u64x2::new(8, 7); | |
12011 | let b: u32x4 = u32x4::new(2, 2, 2, 2); | |
12012 | let c: u32x4 = u32x4::new(3, 3, 0, 1); | |
12013 | let e: u64x2 = u64x2::new(8, 9); | |
12014 | let r: u64x2 = transmute(vmlal_high_u32(transmute(a), transmute(b), transmute(c))); | |
12015 | assert_eq!(r, e); | |
12016 | } | |
12017 | ||
12018 | #[simd_test(enable = "neon")] | |
12019 | unsafe fn test_vmlal_high_n_s16() { | |
12020 | let a: i32x4 = i32x4::new(8, 7, 6, 5); | |
12021 | let b: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12022 | let c: i16 = 2; | |
12023 | let e: i32x4 = i32x4::new(8, 9, 10, 11); | |
12024 | let r: i32x4 = transmute(vmlal_high_n_s16(transmute(a), transmute(b), transmute(c))); | |
12025 | assert_eq!(r, e); | |
12026 | } | |
12027 | ||
12028 | #[simd_test(enable = "neon")] | |
12029 | unsafe fn test_vmlal_high_n_s32() { | |
12030 | let a: i64x2 = i64x2::new(8, 7); | |
12031 | let b: i32x4 = i32x4::new(3, 3, 0, 1); | |
12032 | let c: i32 = 2; | |
12033 | let e: i64x2 = i64x2::new(8, 9); | |
12034 | let r: i64x2 = transmute(vmlal_high_n_s32(transmute(a), transmute(b), transmute(c))); | |
12035 | assert_eq!(r, e); | |
12036 | } | |
12037 | ||
12038 | #[simd_test(enable = "neon")] | |
12039 | unsafe fn test_vmlal_high_n_u16() { | |
12040 | let a: u32x4 = u32x4::new(8, 7, 6, 5); | |
12041 | let b: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12042 | let c: u16 = 2; | |
12043 | let e: u32x4 = u32x4::new(8, 9, 10, 11); | |
12044 | let r: u32x4 = transmute(vmlal_high_n_u16(transmute(a), transmute(b), transmute(c))); | |
12045 | assert_eq!(r, e); | |
12046 | } | |
12047 | ||
12048 | #[simd_test(enable = "neon")] | |
12049 | unsafe fn test_vmlal_high_n_u32() { | |
12050 | let a: u64x2 = u64x2::new(8, 7); | |
12051 | let b: u32x4 = u32x4::new(3, 3, 0, 1); | |
12052 | let c: u32 = 2; | |
12053 | let e: u64x2 = u64x2::new(8, 9); | |
12054 | let r: u64x2 = transmute(vmlal_high_n_u32(transmute(a), transmute(b), transmute(c))); | |
12055 | assert_eq!(r, e); | |
12056 | } | |
12057 | ||
12058 | #[simd_test(enable = "neon")] | |
12059 | unsafe fn test_vmlal_high_lane_s16() { | |
12060 | let a: i32x4 = i32x4::new(8, 7, 6, 5); | |
12061 | let b: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12062 | let c: i16x4 = i16x4::new(0, 2, 0, 0); | |
12063 | let e: i32x4 = i32x4::new(8, 9, 10, 11); | |
12064 | let r: i32x4 = transmute(vmlal_high_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
12065 | assert_eq!(r, e); | |
12066 | } | |
12067 | ||
12068 | #[simd_test(enable = "neon")] | |
12069 | unsafe fn test_vmlal_high_laneq_s16() { | |
12070 | let a: i32x4 = i32x4::new(8, 7, 6, 5); | |
12071 | let b: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12072 | let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
12073 | let e: i32x4 = i32x4::new(8, 9, 10, 11); | |
12074 | let r: i32x4 = transmute(vmlal_high_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
12075 | assert_eq!(r, e); | |
12076 | } | |
12077 | ||
12078 | #[simd_test(enable = "neon")] | |
12079 | unsafe fn test_vmlal_high_lane_s32() { | |
12080 | let a: i64x2 = i64x2::new(8, 7); | |
12081 | let b: i32x4 = i32x4::new(3, 3, 0, 1); | |
12082 | let c: i32x2 = i32x2::new(0, 2); | |
12083 | let e: i64x2 = i64x2::new(8, 9); | |
12084 | let r: i64x2 = transmute(vmlal_high_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
12085 | assert_eq!(r, e); | |
12086 | } | |
12087 | ||
12088 | #[simd_test(enable = "neon")] | |
12089 | unsafe fn test_vmlal_high_laneq_s32() { | |
12090 | let a: i64x2 = i64x2::new(8, 7); | |
12091 | let b: i32x4 = i32x4::new(3, 3, 0, 1); | |
12092 | let c: i32x4 = i32x4::new(0, 2, 0, 0); | |
12093 | let e: i64x2 = i64x2::new(8, 9); | |
12094 | let r: i64x2 = transmute(vmlal_high_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
12095 | assert_eq!(r, e); | |
12096 | } | |
12097 | ||
12098 | #[simd_test(enable = "neon")] | |
12099 | unsafe fn test_vmlal_high_lane_u16() { | |
12100 | let a: u32x4 = u32x4::new(8, 7, 6, 5); | |
12101 | let b: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12102 | let c: u16x4 = u16x4::new(0, 2, 0, 0); | |
12103 | let e: u32x4 = u32x4::new(8, 9, 10, 11); | |
12104 | let r: u32x4 = transmute(vmlal_high_lane_u16::<1>(transmute(a), transmute(b), transmute(c))); | |
12105 | assert_eq!(r, e); | |
12106 | } | |
12107 | ||
12108 | #[simd_test(enable = "neon")] | |
12109 | unsafe fn test_vmlal_high_laneq_u16() { | |
12110 | let a: u32x4 = u32x4::new(8, 7, 6, 5); | |
12111 | let b: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12112 | let c: u16x8 = u16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
12113 | let e: u32x4 = u32x4::new(8, 9, 10, 11); | |
12114 | let r: u32x4 = transmute(vmlal_high_laneq_u16::<1>(transmute(a), transmute(b), transmute(c))); | |
12115 | assert_eq!(r, e); | |
12116 | } | |
12117 | ||
12118 | #[simd_test(enable = "neon")] | |
12119 | unsafe fn test_vmlal_high_lane_u32() { | |
12120 | let a: u64x2 = u64x2::new(8, 7); | |
12121 | let b: u32x4 = u32x4::new(3, 3, 0, 1); | |
12122 | let c: u32x2 = u32x2::new(0, 2); | |
12123 | let e: u64x2 = u64x2::new(8, 9); | |
12124 | let r: u64x2 = transmute(vmlal_high_lane_u32::<1>(transmute(a), transmute(b), transmute(c))); | |
12125 | assert_eq!(r, e); | |
12126 | } | |
12127 | ||
12128 | #[simd_test(enable = "neon")] | |
12129 | unsafe fn test_vmlal_high_laneq_u32() { | |
12130 | let a: u64x2 = u64x2::new(8, 7); | |
12131 | let b: u32x4 = u32x4::new(3, 3, 0, 1); | |
12132 | let c: u32x4 = u32x4::new(0, 2, 0, 0); | |
12133 | let e: u64x2 = u64x2::new(8, 9); | |
12134 | let r: u64x2 = transmute(vmlal_high_laneq_u32::<1>(transmute(a), transmute(b), transmute(c))); | |
12135 | assert_eq!(r, e); | |
12136 | } | |
12137 | ||
12138 | #[simd_test(enable = "neon")] | |
12139 | unsafe fn test_vmls_f64() { | |
12140 | let a: f64 = 6.; | |
12141 | let b: f64 = 2.; | |
12142 | let c: f64 = 3.; | |
12143 | let e: f64 = 0.; | |
12144 | let r: f64 = transmute(vmls_f64(transmute(a), transmute(b), transmute(c))); | |
12145 | assert_eq!(r, e); | |
12146 | } | |
12147 | ||
12148 | #[simd_test(enable = "neon")] | |
12149 | unsafe fn test_vmlsq_f64() { | |
12150 | let a: f64x2 = f64x2::new(6., 7.); | |
12151 | let b: f64x2 = f64x2::new(2., 2.); | |
12152 | let c: f64x2 = f64x2::new(3., 3.); | |
12153 | let e: f64x2 = f64x2::new(0., 1.); | |
12154 | let r: f64x2 = transmute(vmlsq_f64(transmute(a), transmute(b), transmute(c))); | |
12155 | assert_eq!(r, e); | |
12156 | } | |
12157 | ||
12158 | #[simd_test(enable = "neon")] | |
12159 | unsafe fn test_vmlsl_high_s8() { | |
12160 | let a: i16x8 = i16x8::new(14, 15, 16, 17, 18, 19, 20, 21); | |
12161 | let b: i8x16 = i8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); | |
12162 | let c: i8x16 = i8x16::new(3, 3, 0, 1, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7); | |
12163 | let e: i16x8 = i16x8::new(14, 13, 12, 11, 10, 9, 8, 7); | |
12164 | let r: i16x8 = transmute(vmlsl_high_s8(transmute(a), transmute(b), transmute(c))); | |
12165 | assert_eq!(r, e); | |
12166 | } | |
12167 | ||
12168 | #[simd_test(enable = "neon")] | |
12169 | unsafe fn test_vmlsl_high_s16() { | |
12170 | let a: i32x4 = i32x4::new(14, 15, 16, 17); | |
12171 | let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); | |
12172 | let c: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12173 | let e: i32x4 = i32x4::new(14, 13, 12, 11); | |
12174 | let r: i32x4 = transmute(vmlsl_high_s16(transmute(a), transmute(b), transmute(c))); | |
12175 | assert_eq!(r, e); | |
12176 | } | |
12177 | ||
12178 | #[simd_test(enable = "neon")] | |
12179 | unsafe fn test_vmlsl_high_s32() { | |
12180 | let a: i64x2 = i64x2::new(14, 15); | |
12181 | let b: i32x4 = i32x4::new(2, 2, 2, 2); | |
12182 | let c: i32x4 = i32x4::new(3, 3, 0, 1); | |
12183 | let e: i64x2 = i64x2::new(14, 13); | |
12184 | let r: i64x2 = transmute(vmlsl_high_s32(transmute(a), transmute(b), transmute(c))); | |
12185 | assert_eq!(r, e); | |
12186 | } | |
12187 | ||
12188 | #[simd_test(enable = "neon")] | |
12189 | unsafe fn test_vmlsl_high_u8() { | |
12190 | let a: u16x8 = u16x8::new(14, 15, 16, 17, 18, 19, 20, 21); | |
12191 | let b: u8x16 = u8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); | |
12192 | let c: u8x16 = u8x16::new(3, 3, 0, 1, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7); | |
12193 | let e: u16x8 = u16x8::new(14, 13, 12, 11, 10, 9, 8, 7); | |
12194 | let r: u16x8 = transmute(vmlsl_high_u8(transmute(a), transmute(b), transmute(c))); | |
12195 | assert_eq!(r, e); | |
12196 | } | |
12197 | ||
12198 | #[simd_test(enable = "neon")] | |
12199 | unsafe fn test_vmlsl_high_u16() { | |
12200 | let a: u32x4 = u32x4::new(14, 15, 16, 17); | |
12201 | let b: u16x8 = u16x8::new(2, 2, 2, 2, 2, 2, 2, 2); | |
12202 | let c: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12203 | let e: u32x4 = u32x4::new(14, 13, 12, 11); | |
12204 | let r: u32x4 = transmute(vmlsl_high_u16(transmute(a), transmute(b), transmute(c))); | |
12205 | assert_eq!(r, e); | |
12206 | } | |
12207 | ||
12208 | #[simd_test(enable = "neon")] | |
12209 | unsafe fn test_vmlsl_high_u32() { | |
12210 | let a: u64x2 = u64x2::new(14, 15); | |
12211 | let b: u32x4 = u32x4::new(2, 2, 2, 2); | |
12212 | let c: u32x4 = u32x4::new(3, 3, 0, 1); | |
12213 | let e: u64x2 = u64x2::new(14, 13); | |
12214 | let r: u64x2 = transmute(vmlsl_high_u32(transmute(a), transmute(b), transmute(c))); | |
12215 | assert_eq!(r, e); | |
12216 | } | |
12217 | ||
12218 | #[simd_test(enable = "neon")] | |
12219 | unsafe fn test_vmlsl_high_n_s16() { | |
12220 | let a: i32x4 = i32x4::new(14, 15, 16, 17); | |
12221 | let b: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12222 | let c: i16 = 2; | |
12223 | let e: i32x4 = i32x4::new(14, 13, 12, 11); | |
12224 | let r: i32x4 = transmute(vmlsl_high_n_s16(transmute(a), transmute(b), transmute(c))); | |
12225 | assert_eq!(r, e); | |
12226 | } | |
12227 | ||
12228 | #[simd_test(enable = "neon")] | |
12229 | unsafe fn test_vmlsl_high_n_s32() { | |
12230 | let a: i64x2 = i64x2::new(14, 15); | |
12231 | let b: i32x4 = i32x4::new(3, 3, 0, 1); | |
12232 | let c: i32 = 2; | |
12233 | let e: i64x2 = i64x2::new(14, 13); | |
12234 | let r: i64x2 = transmute(vmlsl_high_n_s32(transmute(a), transmute(b), transmute(c))); | |
12235 | assert_eq!(r, e); | |
12236 | } | |
12237 | ||
12238 | #[simd_test(enable = "neon")] | |
12239 | unsafe fn test_vmlsl_high_n_u16() { | |
12240 | let a: u32x4 = u32x4::new(14, 15, 16, 17); | |
12241 | let b: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12242 | let c: u16 = 2; | |
12243 | let e: u32x4 = u32x4::new(14, 13, 12, 11); | |
12244 | let r: u32x4 = transmute(vmlsl_high_n_u16(transmute(a), transmute(b), transmute(c))); | |
12245 | assert_eq!(r, e); | |
12246 | } | |
12247 | ||
12248 | #[simd_test(enable = "neon")] | |
12249 | unsafe fn test_vmlsl_high_n_u32() { | |
12250 | let a: u64x2 = u64x2::new(14, 15); | |
12251 | let b: u32x4 = u32x4::new(3, 3, 0, 1); | |
12252 | let c: u32 = 2; | |
12253 | let e: u64x2 = u64x2::new(14, 13); | |
12254 | let r: u64x2 = transmute(vmlsl_high_n_u32(transmute(a), transmute(b), transmute(c))); | |
12255 | assert_eq!(r, e); | |
12256 | } | |
12257 | ||
12258 | #[simd_test(enable = "neon")] | |
12259 | unsafe fn test_vmlsl_high_lane_s16() { | |
12260 | let a: i32x4 = i32x4::new(14, 15, 16, 17); | |
12261 | let b: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12262 | let c: i16x4 = i16x4::new(0, 2, 0, 0); | |
12263 | let e: i32x4 = i32x4::new(14, 13, 12, 11); | |
12264 | let r: i32x4 = transmute(vmlsl_high_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
12265 | assert_eq!(r, e); | |
12266 | } | |
12267 | ||
12268 | #[simd_test(enable = "neon")] | |
12269 | unsafe fn test_vmlsl_high_laneq_s16() { | |
12270 | let a: i32x4 = i32x4::new(14, 15, 16, 17); | |
12271 | let b: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12272 | let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
12273 | let e: i32x4 = i32x4::new(14, 13, 12, 11); | |
12274 | let r: i32x4 = transmute(vmlsl_high_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
12275 | assert_eq!(r, e); | |
12276 | } | |
12277 | ||
12278 | #[simd_test(enable = "neon")] | |
12279 | unsafe fn test_vmlsl_high_lane_s32() { | |
12280 | let a: i64x2 = i64x2::new(14, 15); | |
12281 | let b: i32x4 = i32x4::new(3, 3, 0, 1); | |
12282 | let c: i32x2 = i32x2::new(0, 2); | |
12283 | let e: i64x2 = i64x2::new(14, 13); | |
12284 | let r: i64x2 = transmute(vmlsl_high_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
12285 | assert_eq!(r, e); | |
12286 | } | |
12287 | ||
12288 | #[simd_test(enable = "neon")] | |
12289 | unsafe fn test_vmlsl_high_laneq_s32() { | |
12290 | let a: i64x2 = i64x2::new(14, 15); | |
12291 | let b: i32x4 = i32x4::new(3, 3, 0, 1); | |
12292 | let c: i32x4 = i32x4::new(0, 2, 0, 0); | |
12293 | let e: i64x2 = i64x2::new(14, 13); | |
12294 | let r: i64x2 = transmute(vmlsl_high_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
12295 | assert_eq!(r, e); | |
12296 | } | |
12297 | ||
12298 | #[simd_test(enable = "neon")] | |
12299 | unsafe fn test_vmlsl_high_lane_u16() { | |
12300 | let a: u32x4 = u32x4::new(14, 15, 16, 17); | |
12301 | let b: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12302 | let c: u16x4 = u16x4::new(0, 2, 0, 0); | |
12303 | let e: u32x4 = u32x4::new(14, 13, 12, 11); | |
12304 | let r: u32x4 = transmute(vmlsl_high_lane_u16::<1>(transmute(a), transmute(b), transmute(c))); | |
12305 | assert_eq!(r, e); | |
12306 | } | |
12307 | ||
12308 | #[simd_test(enable = "neon")] | |
12309 | unsafe fn test_vmlsl_high_laneq_u16() { | |
12310 | let a: u32x4 = u32x4::new(14, 15, 16, 17); | |
12311 | let b: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12312 | let c: u16x8 = u16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
12313 | let e: u32x4 = u32x4::new(14, 13, 12, 11); | |
12314 | let r: u32x4 = transmute(vmlsl_high_laneq_u16::<1>(transmute(a), transmute(b), transmute(c))); | |
12315 | assert_eq!(r, e); | |
12316 | } | |
12317 | ||
12318 | #[simd_test(enable = "neon")] | |
12319 | unsafe fn test_vmlsl_high_lane_u32() { | |
12320 | let a: u64x2 = u64x2::new(14, 15); | |
12321 | let b: u32x4 = u32x4::new(3, 3, 0, 1); | |
12322 | let c: u32x2 = u32x2::new(0, 2); | |
12323 | let e: u64x2 = u64x2::new(14, 13); | |
12324 | let r: u64x2 = transmute(vmlsl_high_lane_u32::<1>(transmute(a), transmute(b), transmute(c))); | |
12325 | assert_eq!(r, e); | |
12326 | } | |
12327 | ||
12328 | #[simd_test(enable = "neon")] | |
12329 | unsafe fn test_vmlsl_high_laneq_u32() { | |
12330 | let a: u64x2 = u64x2::new(14, 15); | |
12331 | let b: u32x4 = u32x4::new(3, 3, 0, 1); | |
12332 | let c: u32x4 = u32x4::new(0, 2, 0, 0); | |
12333 | let e: u64x2 = u64x2::new(14, 13); | |
12334 | let r: u64x2 = transmute(vmlsl_high_laneq_u32::<1>(transmute(a), transmute(b), transmute(c))); | |
12335 | assert_eq!(r, e); | |
12336 | } | |
12337 | ||
12338 | #[simd_test(enable = "neon")] | |
12339 | unsafe fn test_vmovn_high_s16() { | |
12340 | let a: i8x8 = i8x8::new(0, 1, 2, 3, 2, 3, 4, 5); | |
12341 | let b: i16x8 = i16x8::new(2, 3, 4, 5, 12, 13, 14, 15); | |
12342 | let e: i8x16 = i8x16::new(0, 1, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 12, 13, 14, 15); | |
12343 | let r: i8x16 = transmute(vmovn_high_s16(transmute(a), transmute(b))); | |
12344 | assert_eq!(r, e); | |
12345 | } | |
12346 | ||
12347 | #[simd_test(enable = "neon")] | |
12348 | unsafe fn test_vmovn_high_s32() { | |
12349 | let a: i16x4 = i16x4::new(0, 1, 2, 3); | |
12350 | let b: i32x4 = i32x4::new(2, 3, 4, 5); | |
12351 | let e: i16x8 = i16x8::new(0, 1, 2, 3, 2, 3, 4, 5); | |
12352 | let r: i16x8 = transmute(vmovn_high_s32(transmute(a), transmute(b))); | |
12353 | assert_eq!(r, e); | |
12354 | } | |
12355 | ||
12356 | #[simd_test(enable = "neon")] | |
12357 | unsafe fn test_vmovn_high_s64() { | |
12358 | let a: i32x2 = i32x2::new(0, 1); | |
12359 | let b: i64x2 = i64x2::new(2, 3); | |
12360 | let e: i32x4 = i32x4::new(0, 1, 2, 3); | |
12361 | let r: i32x4 = transmute(vmovn_high_s64(transmute(a), transmute(b))); | |
12362 | assert_eq!(r, e); | |
12363 | } | |
12364 | ||
12365 | #[simd_test(enable = "neon")] | |
12366 | unsafe fn test_vmovn_high_u16() { | |
12367 | let a: u8x8 = u8x8::new(0, 1, 2, 3, 2, 3, 4, 5); | |
12368 | let b: u16x8 = u16x8::new(2, 3, 4, 5, 12, 13, 14, 15); | |
12369 | let e: u8x16 = u8x16::new(0, 1, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 12, 13, 14, 15); | |
12370 | let r: u8x16 = transmute(vmovn_high_u16(transmute(a), transmute(b))); | |
12371 | assert_eq!(r, e); | |
12372 | } | |
12373 | ||
12374 | #[simd_test(enable = "neon")] | |
12375 | unsafe fn test_vmovn_high_u32() { | |
12376 | let a: u16x4 = u16x4::new(0, 1, 2, 3); | |
12377 | let b: u32x4 = u32x4::new(2, 3, 4, 5); | |
12378 | let e: u16x8 = u16x8::new(0, 1, 2, 3, 2, 3, 4, 5); | |
12379 | let r: u16x8 = transmute(vmovn_high_u32(transmute(a), transmute(b))); | |
12380 | assert_eq!(r, e); | |
12381 | } | |
12382 | ||
12383 | #[simd_test(enable = "neon")] | |
12384 | unsafe fn test_vmovn_high_u64() { | |
12385 | let a: u32x2 = u32x2::new(0, 1); | |
12386 | let b: u64x2 = u64x2::new(2, 3); | |
12387 | let e: u32x4 = u32x4::new(0, 1, 2, 3); | |
12388 | let r: u32x4 = transmute(vmovn_high_u64(transmute(a), transmute(b))); | |
12389 | assert_eq!(r, e); | |
12390 | } | |
12391 | ||
12392 | #[simd_test(enable = "neon")] | |
12393 | unsafe fn test_vneg_s64() { | |
12394 | let a: i64x1 = i64x1::new(0); | |
12395 | let e: i64x1 = i64x1::new(0); | |
12396 | let r: i64x1 = transmute(vneg_s64(transmute(a))); | |
12397 | assert_eq!(r, e); | |
12398 | } | |
12399 | ||
12400 | #[simd_test(enable = "neon")] | |
12401 | unsafe fn test_vnegq_s64() { | |
12402 | let a: i64x2 = i64x2::new(0, 1); | |
12403 | let e: i64x2 = i64x2::new(0, -1); | |
12404 | let r: i64x2 = transmute(vnegq_s64(transmute(a))); | |
12405 | assert_eq!(r, e); | |
12406 | } | |
12407 | ||
12408 | #[simd_test(enable = "neon")] | |
12409 | unsafe fn test_vneg_f64() { | |
12410 | let a: f64 = 0.; | |
12411 | let e: f64 = 0.; | |
12412 | let r: f64 = transmute(vneg_f64(transmute(a))); | |
12413 | assert_eq!(r, e); | |
12414 | } | |
12415 | ||
12416 | #[simd_test(enable = "neon")] | |
12417 | unsafe fn test_vnegq_f64() { | |
12418 | let a: f64x2 = f64x2::new(0., 1.); | |
12419 | let e: f64x2 = f64x2::new(0., -1.); | |
12420 | let r: f64x2 = transmute(vnegq_f64(transmute(a))); | |
12421 | assert_eq!(r, e); | |
12422 | } | |
12423 | ||
12424 | #[simd_test(enable = "neon")] | |
12425 | unsafe fn test_vqneg_s64() { | |
12426 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
12427 | let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); | |
12428 | let r: i64x1 = transmute(vqneg_s64(transmute(a))); | |
12429 | assert_eq!(r, e); | |
12430 | } | |
12431 | ||
12432 | #[simd_test(enable = "neon")] | |
12433 | unsafe fn test_vqnegq_s64() { | |
12434 | let a: i64x2 = i64x2::new(-9223372036854775808, 0); | |
12435 | let e: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 0); | |
12436 | let r: i64x2 = transmute(vqnegq_s64(transmute(a))); | |
12437 | assert_eq!(r, e); | |
12438 | } | |
12439 | ||
12440 | #[simd_test(enable = "neon")] | |
12441 | unsafe fn test_vqsubb_s8() { | |
12442 | let a: i8 = 42; | |
12443 | let b: i8 = 1; | |
12444 | let e: i8 = 41; | |
12445 | let r: i8 = transmute(vqsubb_s8(transmute(a), transmute(b))); | |
12446 | assert_eq!(r, e); | |
12447 | } | |
12448 | ||
12449 | #[simd_test(enable = "neon")] | |
12450 | unsafe fn test_vqsubh_s16() { | |
12451 | let a: i16 = 42; | |
12452 | let b: i16 = 1; | |
12453 | let e: i16 = 41; | |
12454 | let r: i16 = transmute(vqsubh_s16(transmute(a), transmute(b))); | |
12455 | assert_eq!(r, e); | |
12456 | } | |
12457 | ||
12458 | #[simd_test(enable = "neon")] | |
12459 | unsafe fn test_vqsubb_u8() { | |
12460 | let a: u8 = 42; | |
12461 | let b: u8 = 1; | |
12462 | let e: u8 = 41; | |
12463 | let r: u8 = transmute(vqsubb_u8(transmute(a), transmute(b))); | |
12464 | assert_eq!(r, e); | |
12465 | } | |
12466 | ||
12467 | #[simd_test(enable = "neon")] | |
12468 | unsafe fn test_vqsubh_u16() { | |
12469 | let a: u16 = 42; | |
12470 | let b: u16 = 1; | |
12471 | let e: u16 = 41; | |
12472 | let r: u16 = transmute(vqsubh_u16(transmute(a), transmute(b))); | |
12473 | assert_eq!(r, e); | |
12474 | } | |
12475 | ||
12476 | #[simd_test(enable = "neon")] | |
12477 | unsafe fn test_vqsubs_u32() { | |
12478 | let a: u32 = 42; | |
12479 | let b: u32 = 1; | |
12480 | let e: u32 = 41; | |
12481 | let r: u32 = transmute(vqsubs_u32(transmute(a), transmute(b))); | |
12482 | assert_eq!(r, e); | |
12483 | } | |
12484 | ||
12485 | #[simd_test(enable = "neon")] | |
12486 | unsafe fn test_vqsubd_u64() { | |
12487 | let a: u64 = 42; | |
12488 | let b: u64 = 1; | |
12489 | let e: u64 = 41; | |
12490 | let r: u64 = transmute(vqsubd_u64(transmute(a), transmute(b))); | |
12491 | assert_eq!(r, e); | |
12492 | } | |
12493 | ||
12494 | #[simd_test(enable = "neon")] | |
12495 | unsafe fn test_vqsubs_s32() { | |
12496 | let a: i32 = 42; | |
12497 | let b: i32 = 1; | |
12498 | let e: i32 = 41; | |
12499 | let r: i32 = transmute(vqsubs_s32(transmute(a), transmute(b))); | |
12500 | assert_eq!(r, e); | |
12501 | } | |
12502 | ||
12503 | #[simd_test(enable = "neon")] | |
12504 | unsafe fn test_vqsubd_s64() { | |
12505 | let a: i64 = 42; | |
12506 | let b: i64 = 1; | |
12507 | let e: i64 = 41; | |
12508 | let r: i64 = transmute(vqsubd_s64(transmute(a), transmute(b))); | |
12509 | assert_eq!(r, e); | |
12510 | } | |
12511 | ||
12512 | #[simd_test(enable = "neon")] | |
12513 | unsafe fn test_vrbit_s8() { | |
12514 | let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
12515 | let e: i8x8 = i8x8::new(0, 64, 32, 96, 16, 80, 48, 112); | |
12516 | let r: i8x8 = transmute(vrbit_s8(transmute(a))); | |
12517 | assert_eq!(r, e); | |
12518 | } | |
12519 | ||
12520 | #[simd_test(enable = "neon")] | |
12521 | unsafe fn test_vrbitq_s8() { | |
12522 | let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
12523 | let e: i8x16 = i8x16::new(0, 64, 32, 96, 16, 80, 48, 112, 8, 72, 40, 104, 24, 88, 56, 120); | |
12524 | let r: i8x16 = transmute(vrbitq_s8(transmute(a))); | |
12525 | assert_eq!(r, e); | |
12526 | } | |
12527 | ||
12528 | #[simd_test(enable = "neon")] | |
12529 | unsafe fn test_vrbit_u8() { | |
12530 | let a: u8x8 = u8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
12531 | let e: u8x8 = u8x8::new(0, 64, 32, 96, 16, 80, 48, 112); | |
12532 | let r: u8x8 = transmute(vrbit_u8(transmute(a))); | |
12533 | assert_eq!(r, e); | |
12534 | } | |
12535 | ||
12536 | #[simd_test(enable = "neon")] | |
12537 | unsafe fn test_vrbitq_u8() { | |
12538 | let a: u8x16 = u8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
12539 | let e: u8x16 = u8x16::new(0, 64, 32, 96, 16, 80, 48, 112, 8, 72, 40, 104, 24, 88, 56, 120); | |
12540 | let r: u8x16 = transmute(vrbitq_u8(transmute(a))); | |
12541 | assert_eq!(r, e); | |
12542 | } | |
12543 | ||
12544 | #[simd_test(enable = "neon")] | |
12545 | unsafe fn test_vrbit_p8() { | |
12546 | let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
12547 | let e: i8x8 = i8x8::new(0, 64, 32, 96, 16, 80, 48, 112); | |
12548 | let r: i8x8 = transmute(vrbit_p8(transmute(a))); | |
12549 | assert_eq!(r, e); | |
12550 | } | |
12551 | ||
12552 | #[simd_test(enable = "neon")] | |
12553 | unsafe fn test_vrbitq_p8() { | |
12554 | let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
12555 | let e: i8x16 = i8x16::new(0, 64, 32, 96, 16, 80, 48, 112, 8, 72, 40, 104, 24, 88, 56, 120); | |
12556 | let r: i8x16 = transmute(vrbitq_p8(transmute(a))); | |
12557 | assert_eq!(r, e); | |
12558 | } | |
12559 | ||
12560 | #[simd_test(enable = "neon")] | |
12561 | unsafe fn test_vrndx_f32() { | |
12562 | let a: f32x2 = f32x2::new(-1.5, 0.5); | |
12563 | let e: f32x2 = f32x2::new(-2.0, 0.0); | |
12564 | let r: f32x2 = transmute(vrndx_f32(transmute(a))); | |
12565 | assert_eq!(r, e); | |
12566 | } | |
12567 | ||
12568 | #[simd_test(enable = "neon")] | |
12569 | unsafe fn test_vrndxq_f32() { | |
12570 | let a: f32x4 = f32x4::new(-1.5, 0.5, 1.5, 2.5); | |
12571 | let e: f32x4 = f32x4::new(-2.0, 0.0, 2.0, 2.0); | |
12572 | let r: f32x4 = transmute(vrndxq_f32(transmute(a))); | |
12573 | assert_eq!(r, e); | |
12574 | } | |
12575 | ||
12576 | #[simd_test(enable = "neon")] | |
12577 | unsafe fn test_vrndx_f64() { | |
12578 | let a: f64 = -1.5; | |
12579 | let e: f64 = -2.0; | |
12580 | let r: f64 = transmute(vrndx_f64(transmute(a))); | |
12581 | assert_eq!(r, e); | |
12582 | } | |
12583 | ||
12584 | #[simd_test(enable = "neon")] | |
12585 | unsafe fn test_vrndxq_f64() { | |
12586 | let a: f64x2 = f64x2::new(-1.5, 0.5); | |
12587 | let e: f64x2 = f64x2::new(-2.0, 0.0); | |
12588 | let r: f64x2 = transmute(vrndxq_f64(transmute(a))); | |
12589 | assert_eq!(r, e); | |
12590 | } | |
12591 | ||
12592 | #[simd_test(enable = "neon")] | |
12593 | unsafe fn test_vrnda_f32() { | |
12594 | let a: f32x2 = f32x2::new(-1.5, 0.5); | |
12595 | let e: f32x2 = f32x2::new(-2.0, 1.0); | |
12596 | let r: f32x2 = transmute(vrnda_f32(transmute(a))); | |
12597 | assert_eq!(r, e); | |
12598 | } | |
12599 | ||
12600 | #[simd_test(enable = "neon")] | |
12601 | unsafe fn test_vrndaq_f32() { | |
12602 | let a: f32x4 = f32x4::new(-1.5, 0.5, 1.5, 2.5); | |
12603 | let e: f32x4 = f32x4::new(-2.0, 1.0, 2.0, 3.0); | |
12604 | let r: f32x4 = transmute(vrndaq_f32(transmute(a))); | |
12605 | assert_eq!(r, e); | |
12606 | } | |
12607 | ||
12608 | #[simd_test(enable = "neon")] | |
12609 | unsafe fn test_vrnda_f64() { | |
12610 | let a: f64 = -1.5; | |
12611 | let e: f64 = -2.0; | |
12612 | let r: f64 = transmute(vrnda_f64(transmute(a))); | |
12613 | assert_eq!(r, e); | |
12614 | } | |
12615 | ||
12616 | #[simd_test(enable = "neon")] | |
12617 | unsafe fn test_vrndaq_f64() { | |
12618 | let a: f64x2 = f64x2::new(-1.5, 0.5); | |
12619 | let e: f64x2 = f64x2::new(-2.0, 1.0); | |
12620 | let r: f64x2 = transmute(vrndaq_f64(transmute(a))); | |
12621 | assert_eq!(r, e); | |
12622 | } | |
12623 | ||
12624 | #[simd_test(enable = "neon")] | |
12625 | unsafe fn test_vrndn_f64() { | |
12626 | let a: f64 = -1.5; | |
12627 | let e: f64 = -2.0; | |
12628 | let r: f64 = transmute(vrndn_f64(transmute(a))); | |
12629 | assert_eq!(r, e); | |
12630 | } | |
12631 | ||
12632 | #[simd_test(enable = "neon")] | |
12633 | unsafe fn test_vrndnq_f64() { | |
12634 | let a: f64x2 = f64x2::new(-1.5, 0.5); | |
12635 | let e: f64x2 = f64x2::new(-2.0, 0.0); | |
12636 | let r: f64x2 = transmute(vrndnq_f64(transmute(a))); | |
12637 | assert_eq!(r, e); | |
12638 | } | |
12639 | ||
12640 | #[simd_test(enable = "neon")] | |
12641 | unsafe fn test_vrndm_f32() { | |
12642 | let a: f32x2 = f32x2::new(-1.5, 0.5); | |
12643 | let e: f32x2 = f32x2::new(-2.0, 0.0); | |
12644 | let r: f32x2 = transmute(vrndm_f32(transmute(a))); | |
12645 | assert_eq!(r, e); | |
12646 | } | |
12647 | ||
12648 | #[simd_test(enable = "neon")] | |
12649 | unsafe fn test_vrndmq_f32() { | |
12650 | let a: f32x4 = f32x4::new(-1.5, 0.5, 1.5, 2.5); | |
12651 | let e: f32x4 = f32x4::new(-2.0, 0.0, 1.0, 2.0); | |
12652 | let r: f32x4 = transmute(vrndmq_f32(transmute(a))); | |
12653 | assert_eq!(r, e); | |
12654 | } | |
12655 | ||
12656 | #[simd_test(enable = "neon")] | |
12657 | unsafe fn test_vrndm_f64() { | |
12658 | let a: f64 = -1.5; | |
12659 | let e: f64 = -2.0; | |
12660 | let r: f64 = transmute(vrndm_f64(transmute(a))); | |
12661 | assert_eq!(r, e); | |
12662 | } | |
12663 | ||
12664 | #[simd_test(enable = "neon")] | |
12665 | unsafe fn test_vrndmq_f64() { | |
12666 | let a: f64x2 = f64x2::new(-1.5, 0.5); | |
12667 | let e: f64x2 = f64x2::new(-2.0, 0.0); | |
12668 | let r: f64x2 = transmute(vrndmq_f64(transmute(a))); | |
12669 | assert_eq!(r, e); | |
12670 | } | |
12671 | ||
12672 | #[simd_test(enable = "neon")] | |
12673 | unsafe fn test_vrndp_f32() { | |
12674 | let a: f32x2 = f32x2::new(-1.5, 0.5); | |
12675 | let e: f32x2 = f32x2::new(-1.0, 1.0); | |
12676 | let r: f32x2 = transmute(vrndp_f32(transmute(a))); | |
12677 | assert_eq!(r, e); | |
12678 | } | |
12679 | ||
12680 | #[simd_test(enable = "neon")] | |
12681 | unsafe fn test_vrndpq_f32() { | |
12682 | let a: f32x4 = f32x4::new(-1.5, 0.5, 1.5, 2.5); | |
12683 | let e: f32x4 = f32x4::new(-1.0, 1.0, 2.0, 3.0); | |
12684 | let r: f32x4 = transmute(vrndpq_f32(transmute(a))); | |
12685 | assert_eq!(r, e); | |
12686 | } | |
12687 | ||
12688 | #[simd_test(enable = "neon")] | |
12689 | unsafe fn test_vrndp_f64() { | |
12690 | let a: f64 = -1.5; | |
12691 | let e: f64 = -1.0; | |
12692 | let r: f64 = transmute(vrndp_f64(transmute(a))); | |
12693 | assert_eq!(r, e); | |
12694 | } | |
12695 | ||
12696 | #[simd_test(enable = "neon")] | |
12697 | unsafe fn test_vrndpq_f64() { | |
12698 | let a: f64x2 = f64x2::new(-1.5, 0.5); | |
12699 | let e: f64x2 = f64x2::new(-1.0, 1.0); | |
12700 | let r: f64x2 = transmute(vrndpq_f64(transmute(a))); | |
12701 | assert_eq!(r, e); | |
12702 | } | |
12703 | ||
12704 | #[simd_test(enable = "neon")] | |
12705 | unsafe fn test_vrnd_f32() { | |
12706 | let a: f32x2 = f32x2::new(-1.5, 0.5); | |
12707 | let e: f32x2 = f32x2::new(-1.0, 0.0); | |
12708 | let r: f32x2 = transmute(vrnd_f32(transmute(a))); | |
12709 | assert_eq!(r, e); | |
12710 | } | |
12711 | ||
12712 | #[simd_test(enable = "neon")] | |
12713 | unsafe fn test_vrndq_f32() { | |
12714 | let a: f32x4 = f32x4::new(-1.5, 0.5, 1.5, 2.5); | |
12715 | let e: f32x4 = f32x4::new(-1.0, 0.0, 1.0, 2.0); | |
12716 | let r: f32x4 = transmute(vrndq_f32(transmute(a))); | |
12717 | assert_eq!(r, e); | |
12718 | } | |
12719 | ||
12720 | #[simd_test(enable = "neon")] | |
12721 | unsafe fn test_vrnd_f64() { | |
12722 | let a: f64 = -1.5; | |
12723 | let e: f64 = -1.0; | |
12724 | let r: f64 = transmute(vrnd_f64(transmute(a))); | |
12725 | assert_eq!(r, e); | |
12726 | } | |
12727 | ||
12728 | #[simd_test(enable = "neon")] | |
12729 | unsafe fn test_vrndq_f64() { | |
12730 | let a: f64x2 = f64x2::new(-1.5, 0.5); | |
12731 | let e: f64x2 = f64x2::new(-1.0, 0.0); | |
12732 | let r: f64x2 = transmute(vrndq_f64(transmute(a))); | |
12733 | assert_eq!(r, e); | |
12734 | } | |
12735 | ||
12736 | #[simd_test(enable = "neon")] | |
12737 | unsafe fn test_vrndi_f32() { | |
12738 | let a: f32x2 = f32x2::new(-1.5, 0.5); | |
12739 | let e: f32x2 = f32x2::new(-2.0, 0.0); | |
12740 | let r: f32x2 = transmute(vrndi_f32(transmute(a))); | |
12741 | assert_eq!(r, e); | |
12742 | } | |
12743 | ||
12744 | #[simd_test(enable = "neon")] | |
12745 | unsafe fn test_vrndiq_f32() { | |
12746 | let a: f32x4 = f32x4::new(-1.5, 0.5, 1.5, 2.5); | |
12747 | let e: f32x4 = f32x4::new(-2.0, 0.0, 2.0, 2.0); | |
12748 | let r: f32x4 = transmute(vrndiq_f32(transmute(a))); | |
12749 | assert_eq!(r, e); | |
12750 | } | |
12751 | ||
12752 | #[simd_test(enable = "neon")] | |
12753 | unsafe fn test_vrndi_f64() { | |
12754 | let a: f64 = -1.5; | |
12755 | let e: f64 = -2.0; | |
12756 | let r: f64 = transmute(vrndi_f64(transmute(a))); | |
12757 | assert_eq!(r, e); | |
12758 | } | |
12759 | ||
12760 | #[simd_test(enable = "neon")] | |
12761 | unsafe fn test_vrndiq_f64() { | |
12762 | let a: f64x2 = f64x2::new(-1.5, 0.5); | |
12763 | let e: f64x2 = f64x2::new(-2.0, 0.0); | |
12764 | let r: f64x2 = transmute(vrndiq_f64(transmute(a))); | |
12765 | assert_eq!(r, e); | |
12766 | } | |
12767 | ||
12768 | #[simd_test(enable = "neon")] | |
12769 | unsafe fn test_vqaddb_s8() { | |
12770 | let a: i8 = 42; | |
12771 | let b: i8 = 1; | |
12772 | let e: i8 = 43; | |
12773 | let r: i8 = transmute(vqaddb_s8(transmute(a), transmute(b))); | |
12774 | assert_eq!(r, e); | |
12775 | } | |
12776 | ||
12777 | #[simd_test(enable = "neon")] | |
12778 | unsafe fn test_vqaddh_s16() { | |
12779 | let a: i16 = 42; | |
12780 | let b: i16 = 1; | |
12781 | let e: i16 = 43; | |
12782 | let r: i16 = transmute(vqaddh_s16(transmute(a), transmute(b))); | |
12783 | assert_eq!(r, e); | |
12784 | } | |
12785 | ||
12786 | #[simd_test(enable = "neon")] | |
12787 | unsafe fn test_vqaddb_u8() { | |
12788 | let a: u8 = 42; | |
12789 | let b: u8 = 1; | |
12790 | let e: u8 = 43; | |
12791 | let r: u8 = transmute(vqaddb_u8(transmute(a), transmute(b))); | |
12792 | assert_eq!(r, e); | |
12793 | } | |
12794 | ||
12795 | #[simd_test(enable = "neon")] | |
12796 | unsafe fn test_vqaddh_u16() { | |
12797 | let a: u16 = 42; | |
12798 | let b: u16 = 1; | |
12799 | let e: u16 = 43; | |
12800 | let r: u16 = transmute(vqaddh_u16(transmute(a), transmute(b))); | |
12801 | assert_eq!(r, e); | |
12802 | } | |
12803 | ||
12804 | #[simd_test(enable = "neon")] | |
12805 | unsafe fn test_vqadds_u32() { | |
12806 | let a: u32 = 42; | |
12807 | let b: u32 = 1; | |
12808 | let e: u32 = 43; | |
12809 | let r: u32 = transmute(vqadds_u32(transmute(a), transmute(b))); | |
12810 | assert_eq!(r, e); | |
12811 | } | |
12812 | ||
12813 | #[simd_test(enable = "neon")] | |
12814 | unsafe fn test_vqaddd_u64() { | |
12815 | let a: u64 = 42; | |
12816 | let b: u64 = 1; | |
12817 | let e: u64 = 43; | |
12818 | let r: u64 = transmute(vqaddd_u64(transmute(a), transmute(b))); | |
12819 | assert_eq!(r, e); | |
12820 | } | |
12821 | ||
12822 | #[simd_test(enable = "neon")] | |
12823 | unsafe fn test_vqadds_s32() { | |
12824 | let a: i32 = 42; | |
12825 | let b: i32 = 1; | |
12826 | let e: i32 = 43; | |
12827 | let r: i32 = transmute(vqadds_s32(transmute(a), transmute(b))); | |
12828 | assert_eq!(r, e); | |
12829 | } | |
12830 | ||
12831 | #[simd_test(enable = "neon")] | |
12832 | unsafe fn test_vqaddd_s64() { | |
12833 | let a: i64 = 42; | |
12834 | let b: i64 = 1; | |
12835 | let e: i64 = 43; | |
12836 | let r: i64 = transmute(vqaddd_s64(transmute(a), transmute(b))); | |
12837 | assert_eq!(r, e); | |
12838 | } | |
12839 | ||
12840 | #[simd_test(enable = "neon")] | |
12841 | unsafe fn test_vmul_f64() { | |
12842 | let a: f64 = 1.0; | |
12843 | let b: f64 = 2.0; | |
12844 | let e: f64 = 2.0; | |
12845 | let r: f64 = transmute(vmul_f64(transmute(a), transmute(b))); | |
12846 | assert_eq!(r, e); | |
12847 | } | |
12848 | ||
12849 | #[simd_test(enable = "neon")] | |
12850 | unsafe fn test_vmulq_f64() { | |
12851 | let a: f64x2 = f64x2::new(1.0, 2.0); | |
12852 | let b: f64x2 = f64x2::new(2.0, 3.0); | |
12853 | let e: f64x2 = f64x2::new(2.0, 6.0); | |
12854 | let r: f64x2 = transmute(vmulq_f64(transmute(a), transmute(b))); | |
12855 | assert_eq!(r, e); | |
12856 | } | |
12857 | ||
12858 | #[simd_test(enable = "neon")] | |
12859 | unsafe fn test_vmul_n_f64() { | |
12860 | let a: f64 = 1.; | |
12861 | let b: f64 = 2.; | |
12862 | let e: f64 = 2.; | |
12863 | let r: f64 = transmute(vmul_n_f64(transmute(a), transmute(b))); | |
12864 | assert_eq!(r, e); | |
12865 | } | |
12866 | ||
12867 | #[simd_test(enable = "neon")] | |
12868 | unsafe fn test_vmulq_n_f64() { | |
12869 | let a: f64x2 = f64x2::new(1., 2.); | |
12870 | let b: f64 = 2.; | |
12871 | let e: f64x2 = f64x2::new(2., 4.); | |
12872 | let r: f64x2 = transmute(vmulq_n_f64(transmute(a), transmute(b))); | |
12873 | assert_eq!(r, e); | |
12874 | } | |
12875 | ||
12876 | #[simd_test(enable = "neon")] | |
12877 | unsafe fn test_vmul_lane_f64() { | |
12878 | let a: f64 = 1.; | |
12879 | let b: f64 = 2.; | |
12880 | let e: f64 = 2.; | |
12881 | let r: f64 = transmute(vmul_lane_f64::<0>(transmute(a), transmute(b))); | |
12882 | assert_eq!(r, e); | |
12883 | } | |
12884 | ||
12885 | #[simd_test(enable = "neon")] | |
12886 | unsafe fn test_vmul_laneq_f64() { | |
12887 | let a: f64 = 1.; | |
12888 | let b: f64x2 = f64x2::new(2., 0.); | |
12889 | let e: f64 = 2.; | |
12890 | let r: f64 = transmute(vmul_laneq_f64::<0>(transmute(a), transmute(b))); | |
12891 | assert_eq!(r, e); | |
12892 | } | |
12893 | ||
12894 | #[simd_test(enable = "neon")] | |
12895 | unsafe fn test_vmulq_lane_f64() { | |
12896 | let a: f64x2 = f64x2::new(1., 2.); | |
12897 | let b: f64 = 2.; | |
12898 | let e: f64x2 = f64x2::new(2., 4.); | |
12899 | let r: f64x2 = transmute(vmulq_lane_f64::<0>(transmute(a), transmute(b))); | |
12900 | assert_eq!(r, e); | |
12901 | } | |
12902 | ||
12903 | #[simd_test(enable = "neon")] | |
12904 | unsafe fn test_vmulq_laneq_f64() { | |
12905 | let a: f64x2 = f64x2::new(1., 2.); | |
12906 | let b: f64x2 = f64x2::new(2., 0.); | |
12907 | let e: f64x2 = f64x2::new(2., 4.); | |
12908 | let r: f64x2 = transmute(vmulq_laneq_f64::<0>(transmute(a), transmute(b))); | |
12909 | assert_eq!(r, e); | |
12910 | } | |
12911 | ||
12912 | #[simd_test(enable = "neon")] | |
12913 | unsafe fn test_vmuls_lane_f32() { | |
12914 | let a: f32 = 1.; | |
12915 | let b: f32x2 = f32x2::new(2., 0.); | |
12916 | let e: f32 = 2.; | |
12917 | let r: f32 = transmute(vmuls_lane_f32::<0>(transmute(a), transmute(b))); | |
12918 | assert_eq!(r, e); | |
12919 | } | |
12920 | ||
12921 | #[simd_test(enable = "neon")] | |
12922 | unsafe fn test_vmuls_laneq_f32() { | |
12923 | let a: f32 = 1.; | |
12924 | let b: f32x4 = f32x4::new(2., 0., 0., 0.); | |
12925 | let e: f32 = 2.; | |
12926 | let r: f32 = transmute(vmuls_laneq_f32::<0>(transmute(a), transmute(b))); | |
12927 | assert_eq!(r, e); | |
12928 | } | |
12929 | ||
12930 | #[simd_test(enable = "neon")] | |
12931 | unsafe fn test_vmuld_lane_f64() { | |
12932 | let a: f64 = 1.; | |
12933 | let b: f64 = 2.; | |
12934 | let e: f64 = 2.; | |
12935 | let r: f64 = transmute(vmuld_lane_f64::<0>(transmute(a), transmute(b))); | |
12936 | assert_eq!(r, e); | |
12937 | } | |
12938 | ||
12939 | #[simd_test(enable = "neon")] | |
12940 | unsafe fn test_vmuld_laneq_f64() { | |
12941 | let a: f64 = 1.; | |
12942 | let b: f64x2 = f64x2::new(2., 0.); | |
12943 | let e: f64 = 2.; | |
12944 | let r: f64 = transmute(vmuld_laneq_f64::<0>(transmute(a), transmute(b))); | |
12945 | assert_eq!(r, e); | |
12946 | } | |
12947 | ||
12948 | #[simd_test(enable = "neon")] | |
12949 | unsafe fn test_vmull_high_s8() { | |
12950 | let a: i8x16 = i8x16::new(1, 2, 9, 10, 9, 10, 11, 12, 9, 10, 11, 12, 13, 14, 15, 16); | |
12951 | let b: i8x16 = i8x16::new(1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2); | |
12952 | let e: i16x8 = i16x8::new(9, 20, 11, 24, 13, 28, 15, 32); | |
12953 | let r: i16x8 = transmute(vmull_high_s8(transmute(a), transmute(b))); | |
12954 | assert_eq!(r, e); | |
12955 | } | |
12956 | ||
12957 | #[simd_test(enable = "neon")] | |
12958 | unsafe fn test_vmull_high_s16() { | |
12959 | let a: i16x8 = i16x8::new(1, 2, 9, 10, 9, 10, 11, 12); | |
12960 | let b: i16x8 = i16x8::new(1, 2, 1, 2, 1, 2, 1, 2); | |
12961 | let e: i32x4 = i32x4::new(9, 20, 11, 24); | |
12962 | let r: i32x4 = transmute(vmull_high_s16(transmute(a), transmute(b))); | |
12963 | assert_eq!(r, e); | |
12964 | } | |
12965 | ||
12966 | #[simd_test(enable = "neon")] | |
12967 | unsafe fn test_vmull_high_s32() { | |
12968 | let a: i32x4 = i32x4::new(1, 2, 9, 10); | |
12969 | let b: i32x4 = i32x4::new(1, 2, 1, 2); | |
12970 | let e: i64x2 = i64x2::new(9, 20); | |
12971 | let r: i64x2 = transmute(vmull_high_s32(transmute(a), transmute(b))); | |
12972 | assert_eq!(r, e); | |
12973 | } | |
12974 | ||
12975 | #[simd_test(enable = "neon")] | |
12976 | unsafe fn test_vmull_high_u8() { | |
12977 | let a: u8x16 = u8x16::new(1, 2, 9, 10, 9, 10, 11, 12, 9, 10, 11, 12, 13, 14, 15, 16); | |
12978 | let b: u8x16 = u8x16::new(1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2); | |
12979 | let e: u16x8 = u16x8::new(9, 20, 11, 24, 13, 28, 15, 32); | |
12980 | let r: u16x8 = transmute(vmull_high_u8(transmute(a), transmute(b))); | |
12981 | assert_eq!(r, e); | |
12982 | } | |
12983 | ||
12984 | #[simd_test(enable = "neon")] | |
12985 | unsafe fn test_vmull_high_u16() { | |
12986 | let a: u16x8 = u16x8::new(1, 2, 9, 10, 9, 10, 11, 12); | |
12987 | let b: u16x8 = u16x8::new(1, 2, 1, 2, 1, 2, 1, 2); | |
12988 | let e: u32x4 = u32x4::new(9, 20, 11, 24); | |
12989 | let r: u32x4 = transmute(vmull_high_u16(transmute(a), transmute(b))); | |
12990 | assert_eq!(r, e); | |
12991 | } | |
12992 | ||
12993 | #[simd_test(enable = "neon")] | |
12994 | unsafe fn test_vmull_high_u32() { | |
12995 | let a: u32x4 = u32x4::new(1, 2, 9, 10); | |
12996 | let b: u32x4 = u32x4::new(1, 2, 1, 2); | |
12997 | let e: u64x2 = u64x2::new(9, 20); | |
12998 | let r: u64x2 = transmute(vmull_high_u32(transmute(a), transmute(b))); | |
12999 | assert_eq!(r, e); | |
13000 | } | |
13001 | ||
13002 | #[simd_test(enable = "neon")] | |
13003 | unsafe fn test_vmull_p64() { | |
13004 | let a: p64 = 15; | |
13005 | let b: p64 = 3; | |
13006 | let e: p128 = 17; | |
13007 | let r: p128 = transmute(vmull_p64(transmute(a), transmute(b))); | |
13008 | assert_eq!(r, e); | |
13009 | } | |
13010 | ||
13011 | #[simd_test(enable = "neon")] | |
13012 | unsafe fn test_vmull_high_p8() { | |
13013 | let a: i8x16 = i8x16::new(1, 2, 9, 10, 9, 10, 11, 12, 9, 10, 11, 12, 13, 14, 15, 16); | |
13014 | let b: i8x16 = i8x16::new(1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3); | |
13015 | let e: i16x8 = i16x8::new(9, 30, 11, 20, 13, 18, 15, 48); | |
13016 | let r: i16x8 = transmute(vmull_high_p8(transmute(a), transmute(b))); | |
13017 | assert_eq!(r, e); | |
13018 | } | |
13019 | ||
13020 | #[simd_test(enable = "neon")] | |
13021 | unsafe fn test_vmull_high_p64() { | |
13022 | let a: i64x2 = i64x2::new(1, 15); | |
13023 | let b: i64x2 = i64x2::new(1, 3); | |
13024 | let e: p128 = 17; | |
13025 | let r: p128 = transmute(vmull_high_p64(transmute(a), transmute(b))); | |
13026 | assert_eq!(r, e); | |
13027 | } | |
13028 | ||
13029 | #[simd_test(enable = "neon")] | |
13030 | unsafe fn test_vmull_high_n_s16() { | |
13031 | let a: i16x8 = i16x8::new(1, 2, 9, 10, 9, 10, 11, 12); | |
13032 | let b: i16 = 2; | |
13033 | let e: i32x4 = i32x4::new(18, 20, 22, 24); | |
13034 | let r: i32x4 = transmute(vmull_high_n_s16(transmute(a), transmute(b))); | |
13035 | assert_eq!(r, e); | |
13036 | } | |
13037 | ||
13038 | #[simd_test(enable = "neon")] | |
13039 | unsafe fn test_vmull_high_n_s32() { | |
13040 | let a: i32x4 = i32x4::new(1, 2, 9, 10); | |
13041 | let b: i32 = 2; | |
13042 | let e: i64x2 = i64x2::new(18, 20); | |
13043 | let r: i64x2 = transmute(vmull_high_n_s32(transmute(a), transmute(b))); | |
13044 | assert_eq!(r, e); | |
13045 | } | |
13046 | ||
13047 | #[simd_test(enable = "neon")] | |
13048 | unsafe fn test_vmull_high_n_u16() { | |
13049 | let a: u16x8 = u16x8::new(1, 2, 9, 10, 9, 10, 11, 12); | |
13050 | let b: u16 = 2; | |
13051 | let e: u32x4 = u32x4::new(18, 20, 22, 24); | |
13052 | let r: u32x4 = transmute(vmull_high_n_u16(transmute(a), transmute(b))); | |
13053 | assert_eq!(r, e); | |
13054 | } | |
13055 | ||
13056 | #[simd_test(enable = "neon")] | |
13057 | unsafe fn test_vmull_high_n_u32() { | |
13058 | let a: u32x4 = u32x4::new(1, 2, 9, 10); | |
13059 | let b: u32 = 2; | |
13060 | let e: u64x2 = u64x2::new(18, 20); | |
13061 | let r: u64x2 = transmute(vmull_high_n_u32(transmute(a), transmute(b))); | |
13062 | assert_eq!(r, e); | |
13063 | } | |
13064 | ||
13065 | #[simd_test(enable = "neon")] | |
13066 | unsafe fn test_vmull_high_lane_s16() { | |
13067 | let a: i16x8 = i16x8::new(1, 2, 9, 10, 9, 10, 11, 12); | |
13068 | let b: i16x4 = i16x4::new(0, 2, 0, 0); | |
13069 | let e: i32x4 = i32x4::new(18, 20, 22, 24); | |
13070 | let r: i32x4 = transmute(vmull_high_lane_s16::<1>(transmute(a), transmute(b))); | |
13071 | assert_eq!(r, e); | |
13072 | } | |
13073 | ||
13074 | #[simd_test(enable = "neon")] | |
13075 | unsafe fn test_vmull_high_laneq_s16() { | |
13076 | let a: i16x8 = i16x8::new(1, 2, 9, 10, 9, 10, 11, 12); | |
13077 | let b: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
13078 | let e: i32x4 = i32x4::new(18, 20, 22, 24); | |
13079 | let r: i32x4 = transmute(vmull_high_laneq_s16::<1>(transmute(a), transmute(b))); | |
13080 | assert_eq!(r, e); | |
13081 | } | |
13082 | ||
13083 | #[simd_test(enable = "neon")] | |
13084 | unsafe fn test_vmull_high_lane_s32() { | |
13085 | let a: i32x4 = i32x4::new(1, 2, 9, 10); | |
13086 | let b: i32x2 = i32x2::new(0, 2); | |
13087 | let e: i64x2 = i64x2::new(18, 20); | |
13088 | let r: i64x2 = transmute(vmull_high_lane_s32::<1>(transmute(a), transmute(b))); | |
13089 | assert_eq!(r, e); | |
13090 | } | |
13091 | ||
13092 | #[simd_test(enable = "neon")] | |
13093 | unsafe fn test_vmull_high_laneq_s32() { | |
13094 | let a: i32x4 = i32x4::new(1, 2, 9, 10); | |
13095 | let b: i32x4 = i32x4::new(0, 2, 0, 0); | |
13096 | let e: i64x2 = i64x2::new(18, 20); | |
13097 | let r: i64x2 = transmute(vmull_high_laneq_s32::<1>(transmute(a), transmute(b))); | |
13098 | assert_eq!(r, e); | |
13099 | } | |
13100 | ||
13101 | #[simd_test(enable = "neon")] | |
13102 | unsafe fn test_vmull_high_lane_u16() { | |
13103 | let a: u16x8 = u16x8::new(1, 2, 9, 10, 9, 10, 11, 12); | |
13104 | let b: u16x4 = u16x4::new(0, 2, 0, 0); | |
13105 | let e: u32x4 = u32x4::new(18, 20, 22, 24); | |
13106 | let r: u32x4 = transmute(vmull_high_lane_u16::<1>(transmute(a), transmute(b))); | |
13107 | assert_eq!(r, e); | |
13108 | } | |
13109 | ||
13110 | #[simd_test(enable = "neon")] | |
13111 | unsafe fn test_vmull_high_laneq_u16() { | |
13112 | let a: u16x8 = u16x8::new(1, 2, 9, 10, 9, 10, 11, 12); | |
13113 | let b: u16x8 = u16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
13114 | let e: u32x4 = u32x4::new(18, 20, 22, 24); | |
13115 | let r: u32x4 = transmute(vmull_high_laneq_u16::<1>(transmute(a), transmute(b))); | |
13116 | assert_eq!(r, e); | |
13117 | } | |
13118 | ||
13119 | #[simd_test(enable = "neon")] | |
13120 | unsafe fn test_vmull_high_lane_u32() { | |
13121 | let a: u32x4 = u32x4::new(1, 2, 9, 10); | |
13122 | let b: u32x2 = u32x2::new(0, 2); | |
13123 | let e: u64x2 = u64x2::new(18, 20); | |
13124 | let r: u64x2 = transmute(vmull_high_lane_u32::<1>(transmute(a), transmute(b))); | |
13125 | assert_eq!(r, e); | |
13126 | } | |
13127 | ||
13128 | #[simd_test(enable = "neon")] | |
13129 | unsafe fn test_vmull_high_laneq_u32() { | |
13130 | let a: u32x4 = u32x4::new(1, 2, 9, 10); | |
13131 | let b: u32x4 = u32x4::new(0, 2, 0, 0); | |
13132 | let e: u64x2 = u64x2::new(18, 20); | |
13133 | let r: u64x2 = transmute(vmull_high_laneq_u32::<1>(transmute(a), transmute(b))); | |
13134 | assert_eq!(r, e); | |
13135 | } | |
13136 | ||
13137 | #[simd_test(enable = "neon")] | |
13138 | unsafe fn test_vmulx_f32() { | |
13139 | let a: f32x2 = f32x2::new(1., 2.); | |
13140 | let b: f32x2 = f32x2::new(2., 2.); | |
13141 | let e: f32x2 = f32x2::new(2., 4.); | |
13142 | let r: f32x2 = transmute(vmulx_f32(transmute(a), transmute(b))); | |
13143 | assert_eq!(r, e); | |
13144 | } | |
13145 | ||
13146 | #[simd_test(enable = "neon")] | |
13147 | unsafe fn test_vmulxq_f32() { | |
13148 | let a: f32x4 = f32x4::new(1., 2., 3., 4.); | |
13149 | let b: f32x4 = f32x4::new(2., 2., 2., 2.); | |
13150 | let e: f32x4 = f32x4::new(2., 4., 6., 8.); | |
13151 | let r: f32x4 = transmute(vmulxq_f32(transmute(a), transmute(b))); | |
13152 | assert_eq!(r, e); | |
13153 | } | |
13154 | ||
13155 | #[simd_test(enable = "neon")] | |
13156 | unsafe fn test_vmulx_f64() { | |
13157 | let a: f64 = 1.; | |
13158 | let b: f64 = 2.; | |
13159 | let e: f64 = 2.; | |
13160 | let r: f64 = transmute(vmulx_f64(transmute(a), transmute(b))); | |
13161 | assert_eq!(r, e); | |
13162 | } | |
13163 | ||
13164 | #[simd_test(enable = "neon")] | |
13165 | unsafe fn test_vmulxq_f64() { | |
13166 | let a: f64x2 = f64x2::new(1., 2.); | |
13167 | let b: f64x2 = f64x2::new(2., 2.); | |
13168 | let e: f64x2 = f64x2::new(2., 4.); | |
13169 | let r: f64x2 = transmute(vmulxq_f64(transmute(a), transmute(b))); | |
13170 | assert_eq!(r, e); | |
13171 | } | |
13172 | ||
13173 | #[simd_test(enable = "neon")] | |
13174 | unsafe fn test_vmulx_lane_f64() { | |
13175 | let a: f64 = 1.; | |
13176 | let b: f64 = 2.; | |
13177 | let e: f64 = 2.; | |
13178 | let r: f64 = transmute(vmulx_lane_f64::<0>(transmute(a), transmute(b))); | |
13179 | assert_eq!(r, e); | |
13180 | } | |
13181 | ||
13182 | #[simd_test(enable = "neon")] | |
13183 | unsafe fn test_vmulx_laneq_f64() { | |
13184 | let a: f64 = 1.; | |
13185 | let b: f64x2 = f64x2::new(2., 0.); | |
13186 | let e: f64 = 2.; | |
13187 | let r: f64 = transmute(vmulx_laneq_f64::<0>(transmute(a), transmute(b))); | |
13188 | assert_eq!(r, e); | |
13189 | } | |
13190 | ||
13191 | #[simd_test(enable = "neon")] | |
13192 | unsafe fn test_vmulx_lane_f32() { | |
13193 | let a: f32x2 = f32x2::new(1., 2.); | |
13194 | let b: f32x2 = f32x2::new(2., 0.); | |
13195 | let e: f32x2 = f32x2::new(2., 4.); | |
13196 | let r: f32x2 = transmute(vmulx_lane_f32::<0>(transmute(a), transmute(b))); | |
13197 | assert_eq!(r, e); | |
13198 | } | |
13199 | ||
13200 | #[simd_test(enable = "neon")] | |
13201 | unsafe fn test_vmulx_laneq_f32() { | |
13202 | let a: f32x2 = f32x2::new(1., 2.); | |
13203 | let b: f32x4 = f32x4::new(2., 0., 0., 0.); | |
13204 | let e: f32x2 = f32x2::new(2., 4.); | |
13205 | let r: f32x2 = transmute(vmulx_laneq_f32::<0>(transmute(a), transmute(b))); | |
13206 | assert_eq!(r, e); | |
13207 | } | |
13208 | ||
13209 | #[simd_test(enable = "neon")] | |
13210 | unsafe fn test_vmulxq_lane_f32() { | |
13211 | let a: f32x4 = f32x4::new(1., 2., 3., 4.); | |
13212 | let b: f32x2 = f32x2::new(2., 0.); | |
13213 | let e: f32x4 = f32x4::new(2., 4., 6., 8.); | |
13214 | let r: f32x4 = transmute(vmulxq_lane_f32::<0>(transmute(a), transmute(b))); | |
13215 | assert_eq!(r, e); | |
13216 | } | |
13217 | ||
13218 | #[simd_test(enable = "neon")] | |
13219 | unsafe fn test_vmulxq_laneq_f32() { | |
13220 | let a: f32x4 = f32x4::new(1., 2., 3., 4.); | |
13221 | let b: f32x4 = f32x4::new(2., 0., 0., 0.); | |
13222 | let e: f32x4 = f32x4::new(2., 4., 6., 8.); | |
13223 | let r: f32x4 = transmute(vmulxq_laneq_f32::<0>(transmute(a), transmute(b))); | |
13224 | assert_eq!(r, e); | |
13225 | } | |
13226 | ||
13227 | #[simd_test(enable = "neon")] | |
13228 | unsafe fn test_vmulxq_lane_f64() { | |
13229 | let a: f64x2 = f64x2::new(1., 2.); | |
13230 | let b: f64 = 2.; | |
13231 | let e: f64x2 = f64x2::new(2., 4.); | |
13232 | let r: f64x2 = transmute(vmulxq_lane_f64::<0>(transmute(a), transmute(b))); | |
13233 | assert_eq!(r, e); | |
13234 | } | |
13235 | ||
13236 | #[simd_test(enable = "neon")] | |
13237 | unsafe fn test_vmulxq_laneq_f64() { | |
13238 | let a: f64x2 = f64x2::new(1., 2.); | |
13239 | let b: f64x2 = f64x2::new(2., 0.); | |
13240 | let e: f64x2 = f64x2::new(2., 4.); | |
13241 | let r: f64x2 = transmute(vmulxq_laneq_f64::<0>(transmute(a), transmute(b))); | |
13242 | assert_eq!(r, e); | |
13243 | } | |
13244 | ||
13245 | #[simd_test(enable = "neon")] | |
13246 | unsafe fn test_vmulxs_f32() { | |
13247 | let a: f32 = 2.; | |
13248 | let b: f32 = 3.; | |
13249 | let e: f32 = 6.; | |
13250 | let r: f32 = transmute(vmulxs_f32(transmute(a), transmute(b))); | |
13251 | assert_eq!(r, e); | |
13252 | } | |
13253 | ||
13254 | #[simd_test(enable = "neon")] | |
13255 | unsafe fn test_vmulxd_f64() { | |
13256 | let a: f64 = 2.; | |
13257 | let b: f64 = 3.; | |
13258 | let e: f64 = 6.; | |
13259 | let r: f64 = transmute(vmulxd_f64(transmute(a), transmute(b))); | |
13260 | assert_eq!(r, e); | |
13261 | } | |
13262 | ||
13263 | #[simd_test(enable = "neon")] | |
13264 | unsafe fn test_vmulxs_lane_f32() { | |
13265 | let a: f32 = 2.; | |
13266 | let b: f32x2 = f32x2::new(3., 0.); | |
13267 | let e: f32 = 6.; | |
13268 | let r: f32 = transmute(vmulxs_lane_f32::<0>(transmute(a), transmute(b))); | |
13269 | assert_eq!(r, e); | |
13270 | } | |
13271 | ||
13272 | #[simd_test(enable = "neon")] | |
13273 | unsafe fn test_vmulxs_laneq_f32() { | |
13274 | let a: f32 = 2.; | |
13275 | let b: f32x4 = f32x4::new(3., 0., 0., 0.); | |
13276 | let e: f32 = 6.; | |
13277 | let r: f32 = transmute(vmulxs_laneq_f32::<0>(transmute(a), transmute(b))); | |
13278 | assert_eq!(r, e); | |
13279 | } | |
13280 | ||
13281 | #[simd_test(enable = "neon")] | |
13282 | unsafe fn test_vmulxd_lane_f64() { | |
13283 | let a: f64 = 2.; | |
13284 | let b: f64 = 3.; | |
13285 | let e: f64 = 6.; | |
13286 | let r: f64 = transmute(vmulxd_lane_f64::<0>(transmute(a), transmute(b))); | |
13287 | assert_eq!(r, e); | |
13288 | } | |
13289 | ||
13290 | #[simd_test(enable = "neon")] | |
13291 | unsafe fn test_vmulxd_laneq_f64() { | |
13292 | let a: f64 = 2.; | |
13293 | let b: f64x2 = f64x2::new(3., 0.); | |
13294 | let e: f64 = 6.; | |
13295 | let r: f64 = transmute(vmulxd_laneq_f64::<0>(transmute(a), transmute(b))); | |
13296 | assert_eq!(r, e); | |
13297 | } | |
13298 | ||
13299 | #[simd_test(enable = "neon")] | |
13300 | unsafe fn test_vfma_f64() { | |
13301 | let a: f64 = 8.0; | |
13302 | let b: f64 = 6.0; | |
13303 | let c: f64 = 2.0; | |
13304 | let e: f64 = 20.0; | |
13305 | let r: f64 = transmute(vfma_f64(transmute(a), transmute(b), transmute(c))); | |
13306 | assert_eq!(r, e); | |
13307 | } | |
13308 | ||
13309 | #[simd_test(enable = "neon")] | |
13310 | unsafe fn test_vfmaq_f64() { | |
13311 | let a: f64x2 = f64x2::new(8.0, 18.0); | |
13312 | let b: f64x2 = f64x2::new(6.0, 4.0); | |
13313 | let c: f64x2 = f64x2::new(2.0, 3.0); | |
13314 | let e: f64x2 = f64x2::new(20.0, 30.0); | |
13315 | let r: f64x2 = transmute(vfmaq_f64(transmute(a), transmute(b), transmute(c))); | |
13316 | assert_eq!(r, e); | |
13317 | } | |
13318 | ||
13319 | #[simd_test(enable = "neon")] | |
13320 | unsafe fn test_vfma_n_f64() { | |
13321 | let a: f64 = 2.0; | |
13322 | let b: f64 = 6.0; | |
13323 | let c: f64 = 8.0; | |
13324 | let e: f64 = 50.0; | |
13325 | let r: f64 = transmute(vfma_n_f64(transmute(a), transmute(b), transmute(c))); | |
13326 | assert_eq!(r, e); | |
13327 | } | |
13328 | ||
13329 | #[simd_test(enable = "neon")] | |
13330 | unsafe fn test_vfmaq_n_f64() { | |
13331 | let a: f64x2 = f64x2::new(2.0, 3.0); | |
13332 | let b: f64x2 = f64x2::new(6.0, 4.0); | |
13333 | let c: f64 = 8.0; | |
13334 | let e: f64x2 = f64x2::new(50.0, 35.0); | |
13335 | let r: f64x2 = transmute(vfmaq_n_f64(transmute(a), transmute(b), transmute(c))); | |
13336 | assert_eq!(r, e); | |
13337 | } | |
13338 | ||
13339 | #[simd_test(enable = "neon")] | |
13340 | unsafe fn test_vfma_lane_f32() { | |
13341 | let a: f32x2 = f32x2::new(2., 3.); | |
13342 | let b: f32x2 = f32x2::new(6., 4.); | |
13343 | let c: f32x2 = f32x2::new(2., 0.); | |
13344 | let e: f32x2 = f32x2::new(14., 11.); | |
13345 | let r: f32x2 = transmute(vfma_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13346 | assert_eq!(r, e); | |
13347 | } | |
13348 | ||
13349 | #[simd_test(enable = "neon")] | |
13350 | unsafe fn test_vfma_laneq_f32() { | |
13351 | let a: f32x2 = f32x2::new(2., 3.); | |
13352 | let b: f32x2 = f32x2::new(6., 4.); | |
13353 | let c: f32x4 = f32x4::new(2., 0., 0., 0.); | |
13354 | let e: f32x2 = f32x2::new(14., 11.); | |
13355 | let r: f32x2 = transmute(vfma_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13356 | assert_eq!(r, e); | |
13357 | } | |
13358 | ||
13359 | #[simd_test(enable = "neon")] | |
13360 | unsafe fn test_vfmaq_lane_f32() { | |
13361 | let a: f32x4 = f32x4::new(2., 3., 4., 5.); | |
13362 | let b: f32x4 = f32x4::new(6., 4., 7., 8.); | |
13363 | let c: f32x2 = f32x2::new(2., 0.); | |
13364 | let e: f32x4 = f32x4::new(14., 11., 18., 21.); | |
13365 | let r: f32x4 = transmute(vfmaq_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13366 | assert_eq!(r, e); | |
13367 | } | |
13368 | ||
13369 | #[simd_test(enable = "neon")] | |
13370 | unsafe fn test_vfmaq_laneq_f32() { | |
13371 | let a: f32x4 = f32x4::new(2., 3., 4., 5.); | |
13372 | let b: f32x4 = f32x4::new(6., 4., 7., 8.); | |
13373 | let c: f32x4 = f32x4::new(2., 0., 0., 0.); | |
13374 | let e: f32x4 = f32x4::new(14., 11., 18., 21.); | |
13375 | let r: f32x4 = transmute(vfmaq_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13376 | assert_eq!(r, e); | |
13377 | } | |
13378 | ||
13379 | #[simd_test(enable = "neon")] | |
13380 | unsafe fn test_vfma_lane_f64() { | |
13381 | let a: f64 = 2.; | |
13382 | let b: f64 = 6.; | |
13383 | let c: f64 = 2.; | |
13384 | let e: f64 = 14.; | |
13385 | let r: f64 = transmute(vfma_lane_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13386 | assert_eq!(r, e); | |
13387 | } | |
13388 | ||
13389 | #[simd_test(enable = "neon")] | |
13390 | unsafe fn test_vfma_laneq_f64() { | |
13391 | let a: f64 = 2.; | |
13392 | let b: f64 = 6.; | |
13393 | let c: f64x2 = f64x2::new(2., 0.); | |
13394 | let e: f64 = 14.; | |
13395 | let r: f64 = transmute(vfma_laneq_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13396 | assert_eq!(r, e); | |
13397 | } | |
13398 | ||
13399 | #[simd_test(enable = "neon")] | |
13400 | unsafe fn test_vfmaq_lane_f64() { | |
13401 | let a: f64x2 = f64x2::new(2., 3.); | |
13402 | let b: f64x2 = f64x2::new(6., 4.); | |
13403 | let c: f64 = 2.; | |
13404 | let e: f64x2 = f64x2::new(14., 11.); | |
13405 | let r: f64x2 = transmute(vfmaq_lane_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13406 | assert_eq!(r, e); | |
13407 | } | |
13408 | ||
13409 | #[simd_test(enable = "neon")] | |
13410 | unsafe fn test_vfmaq_laneq_f64() { | |
13411 | let a: f64x2 = f64x2::new(2., 3.); | |
13412 | let b: f64x2 = f64x2::new(6., 4.); | |
13413 | let c: f64x2 = f64x2::new(2., 0.); | |
13414 | let e: f64x2 = f64x2::new(14., 11.); | |
13415 | let r: f64x2 = transmute(vfmaq_laneq_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13416 | assert_eq!(r, e); | |
13417 | } | |
13418 | ||
13419 | #[simd_test(enable = "neon")] | |
13420 | unsafe fn test_vfmas_lane_f32() { | |
13421 | let a: f32 = 2.; | |
13422 | let b: f32 = 6.; | |
13423 | let c: f32x2 = f32x2::new(3., 0.); | |
13424 | let e: f32 = 20.; | |
13425 | let r: f32 = transmute(vfmas_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13426 | assert_eq!(r, e); | |
13427 | } | |
13428 | ||
13429 | #[simd_test(enable = "neon")] | |
13430 | unsafe fn test_vfmas_laneq_f32() { | |
13431 | let a: f32 = 2.; | |
13432 | let b: f32 = 6.; | |
13433 | let c: f32x4 = f32x4::new(3., 0., 0., 0.); | |
13434 | let e: f32 = 20.; | |
13435 | let r: f32 = transmute(vfmas_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13436 | assert_eq!(r, e); | |
13437 | } | |
13438 | ||
13439 | #[simd_test(enable = "neon")] | |
13440 | unsafe fn test_vfmad_lane_f64() { | |
13441 | let a: f64 = 2.; | |
13442 | let b: f64 = 6.; | |
13443 | let c: f64 = 3.; | |
13444 | let e: f64 = 20.; | |
13445 | let r: f64 = transmute(vfmad_lane_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13446 | assert_eq!(r, e); | |
13447 | } | |
13448 | ||
13449 | #[simd_test(enable = "neon")] | |
13450 | unsafe fn test_vfmad_laneq_f64() { | |
13451 | let a: f64 = 2.; | |
13452 | let b: f64 = 6.; | |
13453 | let c: f64x2 = f64x2::new(3., 0.); | |
13454 | let e: f64 = 20.; | |
13455 | let r: f64 = transmute(vfmad_laneq_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13456 | assert_eq!(r, e); | |
13457 | } | |
13458 | ||
13459 | #[simd_test(enable = "neon")] | |
13460 | unsafe fn test_vfms_f64() { | |
13461 | let a: f64 = 20.0; | |
13462 | let b: f64 = 6.0; | |
13463 | let c: f64 = 2.0; | |
13464 | let e: f64 = 8.0; | |
13465 | let r: f64 = transmute(vfms_f64(transmute(a), transmute(b), transmute(c))); | |
13466 | assert_eq!(r, e); | |
13467 | } | |
13468 | ||
13469 | #[simd_test(enable = "neon")] | |
13470 | unsafe fn test_vfmsq_f64() { | |
13471 | let a: f64x2 = f64x2::new(20.0, 30.0); | |
13472 | let b: f64x2 = f64x2::new(6.0, 4.0); | |
13473 | let c: f64x2 = f64x2::new(2.0, 3.0); | |
13474 | let e: f64x2 = f64x2::new(8.0, 18.0); | |
13475 | let r: f64x2 = transmute(vfmsq_f64(transmute(a), transmute(b), transmute(c))); | |
13476 | assert_eq!(r, e); | |
13477 | } | |
13478 | ||
13479 | #[simd_test(enable = "neon")] | |
13480 | unsafe fn test_vfms_n_f64() { | |
13481 | let a: f64 = 50.0; | |
13482 | let b: f64 = 6.0; | |
13483 | let c: f64 = 8.0; | |
13484 | let e: f64 = 2.0; | |
13485 | let r: f64 = transmute(vfms_n_f64(transmute(a), transmute(b), transmute(c))); | |
13486 | assert_eq!(r, e); | |
13487 | } | |
13488 | ||
13489 | #[simd_test(enable = "neon")] | |
13490 | unsafe fn test_vfmsq_n_f64() { | |
13491 | let a: f64x2 = f64x2::new(50.0, 35.0); | |
13492 | let b: f64x2 = f64x2::new(6.0, 4.0); | |
13493 | let c: f64 = 8.0; | |
13494 | let e: f64x2 = f64x2::new(2.0, 3.0); | |
13495 | let r: f64x2 = transmute(vfmsq_n_f64(transmute(a), transmute(b), transmute(c))); | |
13496 | assert_eq!(r, e); | |
13497 | } | |
13498 | ||
13499 | #[simd_test(enable = "neon")] | |
13500 | unsafe fn test_vfms_lane_f32() { | |
13501 | let a: f32x2 = f32x2::new(14., 11.); | |
13502 | let b: f32x2 = f32x2::new(6., 4.); | |
13503 | let c: f32x2 = f32x2::new(2., 0.); | |
13504 | let e: f32x2 = f32x2::new(2., 3.); | |
13505 | let r: f32x2 = transmute(vfms_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13506 | assert_eq!(r, e); | |
13507 | } | |
13508 | ||
13509 | #[simd_test(enable = "neon")] | |
13510 | unsafe fn test_vfms_laneq_f32() { | |
13511 | let a: f32x2 = f32x2::new(14., 11.); | |
13512 | let b: f32x2 = f32x2::new(6., 4.); | |
13513 | let c: f32x4 = f32x4::new(2., 0., 0., 0.); | |
13514 | let e: f32x2 = f32x2::new(2., 3.); | |
13515 | let r: f32x2 = transmute(vfms_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13516 | assert_eq!(r, e); | |
13517 | } | |
13518 | ||
13519 | #[simd_test(enable = "neon")] | |
13520 | unsafe fn test_vfmsq_lane_f32() { | |
13521 | let a: f32x4 = f32x4::new(14., 11., 18., 21.); | |
13522 | let b: f32x4 = f32x4::new(6., 4., 7., 8.); | |
13523 | let c: f32x2 = f32x2::new(2., 0.); | |
13524 | let e: f32x4 = f32x4::new(2., 3., 4., 5.); | |
13525 | let r: f32x4 = transmute(vfmsq_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13526 | assert_eq!(r, e); | |
13527 | } | |
13528 | ||
13529 | #[simd_test(enable = "neon")] | |
13530 | unsafe fn test_vfmsq_laneq_f32() { | |
13531 | let a: f32x4 = f32x4::new(14., 11., 18., 21.); | |
13532 | let b: f32x4 = f32x4::new(6., 4., 7., 8.); | |
13533 | let c: f32x4 = f32x4::new(2., 0., 0., 0.); | |
13534 | let e: f32x4 = f32x4::new(2., 3., 4., 5.); | |
13535 | let r: f32x4 = transmute(vfmsq_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13536 | assert_eq!(r, e); | |
13537 | } | |
13538 | ||
13539 | #[simd_test(enable = "neon")] | |
13540 | unsafe fn test_vfms_lane_f64() { | |
13541 | let a: f64 = 14.; | |
13542 | let b: f64 = 6.; | |
13543 | let c: f64 = 2.; | |
13544 | let e: f64 = 2.; | |
13545 | let r: f64 = transmute(vfms_lane_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13546 | assert_eq!(r, e); | |
13547 | } | |
13548 | ||
13549 | #[simd_test(enable = "neon")] | |
13550 | unsafe fn test_vfms_laneq_f64() { | |
13551 | let a: f64 = 14.; | |
13552 | let b: f64 = 6.; | |
13553 | let c: f64x2 = f64x2::new(2., 0.); | |
13554 | let e: f64 = 2.; | |
13555 | let r: f64 = transmute(vfms_laneq_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13556 | assert_eq!(r, e); | |
13557 | } | |
13558 | ||
13559 | #[simd_test(enable = "neon")] | |
13560 | unsafe fn test_vfmsq_lane_f64() { | |
13561 | let a: f64x2 = f64x2::new(14., 11.); | |
13562 | let b: f64x2 = f64x2::new(6., 4.); | |
13563 | let c: f64 = 2.; | |
13564 | let e: f64x2 = f64x2::new(2., 3.); | |
13565 | let r: f64x2 = transmute(vfmsq_lane_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13566 | assert_eq!(r, e); | |
13567 | } | |
13568 | ||
13569 | #[simd_test(enable = "neon")] | |
13570 | unsafe fn test_vfmsq_laneq_f64() { | |
13571 | let a: f64x2 = f64x2::new(14., 11.); | |
13572 | let b: f64x2 = f64x2::new(6., 4.); | |
13573 | let c: f64x2 = f64x2::new(2., 0.); | |
13574 | let e: f64x2 = f64x2::new(2., 3.); | |
13575 | let r: f64x2 = transmute(vfmsq_laneq_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13576 | assert_eq!(r, e); | |
13577 | } | |
13578 | ||
13579 | #[simd_test(enable = "neon")] | |
13580 | unsafe fn test_vfmss_lane_f32() { | |
13581 | let a: f32 = 14.; | |
13582 | let b: f32 = 6.; | |
13583 | let c: f32x2 = f32x2::new(2., 0.); | |
13584 | let e: f32 = 2.; | |
13585 | let r: f32 = transmute(vfmss_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13586 | assert_eq!(r, e); | |
13587 | } | |
13588 | ||
13589 | #[simd_test(enable = "neon")] | |
13590 | unsafe fn test_vfmss_laneq_f32() { | |
13591 | let a: f32 = 14.; | |
13592 | let b: f32 = 6.; | |
13593 | let c: f32x4 = f32x4::new(2., 0., 0., 0.); | |
13594 | let e: f32 = 2.; | |
13595 | let r: f32 = transmute(vfmss_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13596 | assert_eq!(r, e); | |
13597 | } | |
13598 | ||
13599 | #[simd_test(enable = "neon")] | |
13600 | unsafe fn test_vfmsd_lane_f64() { | |
13601 | let a: f64 = 14.; | |
13602 | let b: f64 = 6.; | |
13603 | let c: f64 = 2.; | |
13604 | let e: f64 = 2.; | |
13605 | let r: f64 = transmute(vfmsd_lane_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13606 | assert_eq!(r, e); | |
13607 | } | |
13608 | ||
13609 | #[simd_test(enable = "neon")] | |
13610 | unsafe fn test_vfmsd_laneq_f64() { | |
13611 | let a: f64 = 14.; | |
13612 | let b: f64 = 6.; | |
13613 | let c: f64x2 = f64x2::new(2., 0.); | |
13614 | let e: f64 = 2.; | |
13615 | let r: f64 = transmute(vfmsd_laneq_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13616 | assert_eq!(r, e); | |
13617 | } | |
13618 | ||
13619 | #[simd_test(enable = "neon")] | |
13620 | unsafe fn test_vdiv_f32() { | |
13621 | let a: f32x2 = f32x2::new(2.0, 6.0); | |
13622 | let b: f32x2 = f32x2::new(1.0, 2.0); | |
13623 | let e: f32x2 = f32x2::new(2.0, 3.0); | |
13624 | let r: f32x2 = transmute(vdiv_f32(transmute(a), transmute(b))); | |
13625 | assert_eq!(r, e); | |
13626 | } | |
13627 | ||
13628 | #[simd_test(enable = "neon")] | |
13629 | unsafe fn test_vdivq_f32() { | |
13630 | let a: f32x4 = f32x4::new(2.0, 6.0, 4.0, 10.0); | |
13631 | let b: f32x4 = f32x4::new(1.0, 2.0, 1.0, 2.0); | |
13632 | let e: f32x4 = f32x4::new(2.0, 3.0, 4.0, 5.0); | |
13633 | let r: f32x4 = transmute(vdivq_f32(transmute(a), transmute(b))); | |
13634 | assert_eq!(r, e); | |
13635 | } | |
13636 | ||
13637 | #[simd_test(enable = "neon")] | |
13638 | unsafe fn test_vdiv_f64() { | |
13639 | let a: f64 = 2.0; | |
13640 | let b: f64 = 1.0; | |
13641 | let e: f64 = 2.0; | |
13642 | let r: f64 = transmute(vdiv_f64(transmute(a), transmute(b))); | |
13643 | assert_eq!(r, e); | |
13644 | } | |
13645 | ||
13646 | #[simd_test(enable = "neon")] | |
13647 | unsafe fn test_vdivq_f64() { | |
13648 | let a: f64x2 = f64x2::new(2.0, 6.0); | |
13649 | let b: f64x2 = f64x2::new(1.0, 2.0); | |
13650 | let e: f64x2 = f64x2::new(2.0, 3.0); | |
13651 | let r: f64x2 = transmute(vdivq_f64(transmute(a), transmute(b))); | |
13652 | assert_eq!(r, e); | |
13653 | } | |
13654 | ||
13655 | #[simd_test(enable = "neon")] | |
13656 | unsafe fn test_vsub_f64() { | |
13657 | let a: f64 = 1.0; | |
13658 | let b: f64 = 1.0; | |
13659 | let e: f64 = 0.0; | |
13660 | let r: f64 = transmute(vsub_f64(transmute(a), transmute(b))); | |
13661 | assert_eq!(r, e); | |
13662 | } | |
13663 | ||
13664 | #[simd_test(enable = "neon")] | |
13665 | unsafe fn test_vsubq_f64() { | |
13666 | let a: f64x2 = f64x2::new(1.0, 4.0); | |
13667 | let b: f64x2 = f64x2::new(1.0, 2.0); | |
13668 | let e: f64x2 = f64x2::new(0.0, 2.0); | |
13669 | let r: f64x2 = transmute(vsubq_f64(transmute(a), transmute(b))); | |
13670 | assert_eq!(r, e); | |
13671 | } | |
13672 | ||
13673 | #[simd_test(enable = "neon")] | |
13674 | unsafe fn test_vaddlv_s16() { | |
13675 | let a: i16x4 = i16x4::new(1, 2, 3, 4); | |
13676 | let e: i32 = 10; | |
13677 | let r: i32 = transmute(vaddlv_s16(transmute(a))); | |
13678 | assert_eq!(r, e); | |
13679 | } | |
13680 | ||
13681 | #[simd_test(enable = "neon")] | |
13682 | unsafe fn test_vaddlvq_s16() { | |
13683 | let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
13684 | let e: i32 = 36; | |
13685 | let r: i32 = transmute(vaddlvq_s16(transmute(a))); | |
13686 | assert_eq!(r, e); | |
13687 | } | |
13688 | ||
13689 | #[simd_test(enable = "neon")] | |
13690 | unsafe fn test_vaddlv_s32() { | |
13691 | let a: i32x2 = i32x2::new(1, 2); | |
13692 | let e: i64 = 3; | |
13693 | let r: i64 = transmute(vaddlv_s32(transmute(a))); | |
13694 | assert_eq!(r, e); | |
13695 | } | |
13696 | ||
13697 | #[simd_test(enable = "neon")] | |
13698 | unsafe fn test_vaddlvq_s32() { | |
13699 | let a: i32x4 = i32x4::new(1, 2, 3, 4); | |
13700 | let e: i64 = 10; | |
13701 | let r: i64 = transmute(vaddlvq_s32(transmute(a))); | |
13702 | assert_eq!(r, e); | |
13703 | } | |
13704 | ||
13705 | #[simd_test(enable = "neon")] | |
13706 | unsafe fn test_vaddlv_u16() { | |
13707 | let a: u16x4 = u16x4::new(1, 2, 3, 4); | |
13708 | let e: u32 = 10; | |
13709 | let r: u32 = transmute(vaddlv_u16(transmute(a))); | |
13710 | assert_eq!(r, e); | |
13711 | } | |
13712 | ||
13713 | #[simd_test(enable = "neon")] | |
13714 | unsafe fn test_vaddlvq_u16() { | |
13715 | let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
13716 | let e: u32 = 36; | |
13717 | let r: u32 = transmute(vaddlvq_u16(transmute(a))); | |
13718 | assert_eq!(r, e); | |
13719 | } | |
13720 | ||
13721 | #[simd_test(enable = "neon")] | |
13722 | unsafe fn test_vaddlv_u32() { | |
13723 | let a: u32x2 = u32x2::new(1, 2); | |
13724 | let e: u64 = 3; | |
13725 | let r: u64 = transmute(vaddlv_u32(transmute(a))); | |
13726 | assert_eq!(r, e); | |
13727 | } | |
13728 | ||
13729 | #[simd_test(enable = "neon")] | |
13730 | unsafe fn test_vaddlvq_u32() { | |
13731 | let a: u32x4 = u32x4::new(1, 2, 3, 4); | |
13732 | let e: u64 = 10; | |
13733 | let r: u64 = transmute(vaddlvq_u32(transmute(a))); | |
13734 | assert_eq!(r, e); | |
13735 | } | |
13736 | ||
13737 | #[simd_test(enable = "neon")] | |
13738 | unsafe fn test_vsubw_high_s8() { | |
13739 | let a: i16x8 = i16x8::new(8, 9, 10, 12, 13, 14, 15, 16); | |
13740 | let b: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16); | |
13741 | let e: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
13742 | let r: i16x8 = transmute(vsubw_high_s8(transmute(a), transmute(b))); | |
13743 | assert_eq!(r, e); | |
13744 | } | |
13745 | ||
13746 | #[simd_test(enable = "neon")] | |
13747 | unsafe fn test_vsubw_high_s16() { | |
13748 | let a: i32x4 = i32x4::new(8, 9, 10, 11); | |
13749 | let b: i16x8 = i16x8::new(0, 1, 2, 3, 8, 9, 10, 11); | |
13750 | let e: i32x4 = i32x4::new(0, 0, 0, 0); | |
13751 | let r: i32x4 = transmute(vsubw_high_s16(transmute(a), transmute(b))); | |
13752 | assert_eq!(r, e); | |
13753 | } | |
13754 | ||
13755 | #[simd_test(enable = "neon")] | |
13756 | unsafe fn test_vsubw_high_s32() { | |
13757 | let a: i64x2 = i64x2::new(8, 9); | |
13758 | let b: i32x4 = i32x4::new(6, 7, 8, 9); | |
13759 | let e: i64x2 = i64x2::new(0, 0); | |
13760 | let r: i64x2 = transmute(vsubw_high_s32(transmute(a), transmute(b))); | |
13761 | assert_eq!(r, e); | |
13762 | } | |
13763 | ||
13764 | #[simd_test(enable = "neon")] | |
13765 | unsafe fn test_vsubw_high_u8() { | |
13766 | let a: u16x8 = u16x8::new(8, 9, 10, 11, 12, 13, 14, 15); | |
13767 | let b: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); | |
13768 | let e: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
13769 | let r: u16x8 = transmute(vsubw_high_u8(transmute(a), transmute(b))); | |
13770 | assert_eq!(r, e); | |
13771 | } | |
13772 | ||
13773 | #[simd_test(enable = "neon")] | |
13774 | unsafe fn test_vsubw_high_u16() { | |
13775 | let a: u32x4 = u32x4::new(8, 9, 10, 11); | |
13776 | let b: u16x8 = u16x8::new(0, 1, 2, 3, 8, 9, 10, 11); | |
13777 | let e: u32x4 = u32x4::new(0, 0, 0, 0); | |
13778 | let r: u32x4 = transmute(vsubw_high_u16(transmute(a), transmute(b))); | |
13779 | assert_eq!(r, e); | |
13780 | } | |
13781 | ||
13782 | #[simd_test(enable = "neon")] | |
13783 | unsafe fn test_vsubw_high_u32() { | |
13784 | let a: u64x2 = u64x2::new(8, 9); | |
13785 | let b: u32x4 = u32x4::new(6, 7, 8, 9); | |
13786 | let e: u64x2 = u64x2::new(0, 0); | |
13787 | let r: u64x2 = transmute(vsubw_high_u32(transmute(a), transmute(b))); | |
13788 | assert_eq!(r, e); | |
13789 | } | |
13790 | ||
13791 | #[simd_test(enable = "neon")] | |
13792 | unsafe fn test_vsubl_high_s8() { | |
13793 | let a: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); | |
13794 | let b: i8x16 = i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2); | |
13795 | let e: i16x8 = i16x8::new(6, 7, 8, 9, 10, 11, 12, 13); | |
13796 | let r: i16x8 = transmute(vsubl_high_s8(transmute(a), transmute(b))); | |
13797 | assert_eq!(r, e); | |
13798 | } | |
13799 | ||
13800 | #[simd_test(enable = "neon")] | |
13801 | unsafe fn test_vsubl_high_s16() { | |
13802 | let a: i16x8 = i16x8::new(8, 9, 10, 11, 12, 13, 14, 15); | |
13803 | let b: i16x8 = i16x8::new(6, 6, 6, 6, 8, 8, 8, 8); | |
13804 | let e: i32x4 = i32x4::new(4, 5, 6, 7); | |
13805 | let r: i32x4 = transmute(vsubl_high_s16(transmute(a), transmute(b))); | |
13806 | assert_eq!(r, e); | |
13807 | } | |
13808 | ||
13809 | #[simd_test(enable = "neon")] | |
13810 | unsafe fn test_vsubl_high_s32() { | |
13811 | let a: i32x4 = i32x4::new(12, 13, 14, 15); | |
13812 | let b: i32x4 = i32x4::new(6, 6, 8, 8); | |
13813 | let e: i64x2 = i64x2::new(6, 7); | |
13814 | let r: i64x2 = transmute(vsubl_high_s32(transmute(a), transmute(b))); | |
13815 | assert_eq!(r, e); | |
13816 | } | |
13817 | ||
13818 | #[simd_test(enable = "neon")] | |
13819 | unsafe fn test_vsubl_high_u8() { | |
13820 | let a: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); | |
13821 | let b: u8x16 = u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2); | |
13822 | let e: u16x8 = u16x8::new(6, 7, 8, 9, 10, 11, 12, 13); | |
13823 | let r: u16x8 = transmute(vsubl_high_u8(transmute(a), transmute(b))); | |
13824 | assert_eq!(r, e); | |
13825 | } | |
13826 | ||
13827 | #[simd_test(enable = "neon")] | |
13828 | unsafe fn test_vsubl_high_u16() { | |
13829 | let a: u16x8 = u16x8::new(8, 9, 10, 11, 12, 13, 14, 15); | |
13830 | let b: u16x8 = u16x8::new(6, 6, 6, 6, 8, 8, 8, 8); | |
13831 | let e: u32x4 = u32x4::new(4, 5, 6, 7); | |
13832 | let r: u32x4 = transmute(vsubl_high_u16(transmute(a), transmute(b))); | |
13833 | assert_eq!(r, e); | |
13834 | } | |
13835 | ||
13836 | #[simd_test(enable = "neon")] | |
13837 | unsafe fn test_vsubl_high_u32() { | |
13838 | let a: u32x4 = u32x4::new(12, 13, 14, 15); | |
13839 | let b: u32x4 = u32x4::new(6, 6, 8, 8); | |
13840 | let e: u64x2 = u64x2::new(6, 7); | |
13841 | let r: u64x2 = transmute(vsubl_high_u32(transmute(a), transmute(b))); | |
13842 | assert_eq!(r, e); | |
13843 | } | |
13844 | ||
13845 | #[simd_test(enable = "neon")] | |
13846 | unsafe fn test_vmax_f64() { | |
13847 | let a: f64 = 1.0; | |
13848 | let b: f64 = 0.0; | |
13849 | let e: f64 = 1.0; | |
13850 | let r: f64 = transmute(vmax_f64(transmute(a), transmute(b))); | |
13851 | assert_eq!(r, e); | |
13852 | } | |
13853 | ||
13854 | #[simd_test(enable = "neon")] | |
13855 | unsafe fn test_vmaxq_f64() { | |
13856 | let a: f64x2 = f64x2::new(1.0, -2.0); | |
13857 | let b: f64x2 = f64x2::new(0.0, 3.0); | |
13858 | let e: f64x2 = f64x2::new(1.0, 3.0); | |
13859 | let r: f64x2 = transmute(vmaxq_f64(transmute(a), transmute(b))); | |
13860 | assert_eq!(r, e); | |
13861 | } | |
13862 | ||
13863 | #[simd_test(enable = "neon")] | |
13864 | unsafe fn test_vmaxnm_f64() { | |
13865 | let a: f64 = 1.0; | |
13866 | let b: f64 = 8.0; | |
13867 | let e: f64 = 8.0; | |
13868 | let r: f64 = transmute(vmaxnm_f64(transmute(a), transmute(b))); | |
13869 | assert_eq!(r, e); | |
13870 | } | |
13871 | ||
13872 | #[simd_test(enable = "neon")] | |
13873 | unsafe fn test_vmaxnmq_f64() { | |
13874 | let a: f64x2 = f64x2::new(1.0, 2.0); | |
13875 | let b: f64x2 = f64x2::new(8.0, 16.0); | |
13876 | let e: f64x2 = f64x2::new(8.0, 16.0); | |
13877 | let r: f64x2 = transmute(vmaxnmq_f64(transmute(a), transmute(b))); | |
13878 | assert_eq!(r, e); | |
13879 | } | |
13880 | ||
13881 | #[simd_test(enable = "neon")] | |
13882 | unsafe fn test_vpmaxnm_f32() { | |
13883 | let a: f32x2 = f32x2::new(1.0, 2.0); | |
13884 | let b: f32x2 = f32x2::new(6.0, -3.0); | |
13885 | let e: f32x2 = f32x2::new(2.0, 6.0); | |
13886 | let r: f32x2 = transmute(vpmaxnm_f32(transmute(a), transmute(b))); | |
13887 | assert_eq!(r, e); | |
13888 | } | |
13889 | ||
13890 | #[simd_test(enable = "neon")] | |
13891 | unsafe fn test_vpmaxnmq_f64() { | |
13892 | let a: f64x2 = f64x2::new(1.0, 2.0); | |
13893 | let b: f64x2 = f64x2::new(6.0, -3.0); | |
13894 | let e: f64x2 = f64x2::new(2.0, 6.0); | |
13895 | let r: f64x2 = transmute(vpmaxnmq_f64(transmute(a), transmute(b))); | |
13896 | assert_eq!(r, e); | |
13897 | } | |
13898 | ||
13899 | #[simd_test(enable = "neon")] | |
13900 | unsafe fn test_vpmaxnmq_f32() { | |
13901 | let a: f32x4 = f32x4::new(1.0, 2.0, 3.0, -4.0); | |
13902 | let b: f32x4 = f32x4::new(8.0, 16.0, -1.0, 6.0); | |
13903 | let e: f32x4 = f32x4::new(2.0, 3.0, 16.0, 6.0); | |
13904 | let r: f32x4 = transmute(vpmaxnmq_f32(transmute(a), transmute(b))); | |
13905 | assert_eq!(r, e); | |
13906 | } | |
13907 | ||
13908 | #[simd_test(enable = "neon")] | |
13909 | unsafe fn test_vmin_f64() { | |
13910 | let a: f64 = 1.0; | |
13911 | let b: f64 = 0.0; | |
13912 | let e: f64 = 0.0; | |
13913 | let r: f64 = transmute(vmin_f64(transmute(a), transmute(b))); | |
13914 | assert_eq!(r, e); | |
13915 | } | |
13916 | ||
13917 | #[simd_test(enable = "neon")] | |
13918 | unsafe fn test_vminq_f64() { | |
13919 | let a: f64x2 = f64x2::new(1.0, -2.0); | |
13920 | let b: f64x2 = f64x2::new(0.0, 3.0); | |
13921 | let e: f64x2 = f64x2::new(0.0, -2.0); | |
13922 | let r: f64x2 = transmute(vminq_f64(transmute(a), transmute(b))); | |
13923 | assert_eq!(r, e); | |
13924 | } | |
13925 | ||
13926 | #[simd_test(enable = "neon")] | |
13927 | unsafe fn test_vminnm_f64() { | |
13928 | let a: f64 = 1.0; | |
13929 | let b: f64 = 8.0; | |
13930 | let e: f64 = 1.0; | |
13931 | let r: f64 = transmute(vminnm_f64(transmute(a), transmute(b))); | |
13932 | assert_eq!(r, e); | |
13933 | } | |
13934 | ||
13935 | #[simd_test(enable = "neon")] | |
13936 | unsafe fn test_vminnmq_f64() { | |
13937 | let a: f64x2 = f64x2::new(1.0, 2.0); | |
13938 | let b: f64x2 = f64x2::new(8.0, 16.0); | |
13939 | let e: f64x2 = f64x2::new(1.0, 2.0); | |
13940 | let r: f64x2 = transmute(vminnmq_f64(transmute(a), transmute(b))); | |
13941 | assert_eq!(r, e); | |
13942 | } | |
13943 | ||
13944 | #[simd_test(enable = "neon")] | |
13945 | unsafe fn test_vpminnm_f32() { | |
13946 | let a: f32x2 = f32x2::new(1.0, 2.0); | |
13947 | let b: f32x2 = f32x2::new(6.0, -3.0); | |
13948 | let e: f32x2 = f32x2::new(1.0, -3.0); | |
13949 | let r: f32x2 = transmute(vpminnm_f32(transmute(a), transmute(b))); | |
13950 | assert_eq!(r, e); | |
13951 | } | |
13952 | ||
13953 | #[simd_test(enable = "neon")] | |
13954 | unsafe fn test_vpminnmq_f64() { | |
13955 | let a: f64x2 = f64x2::new(1.0, 2.0); | |
13956 | let b: f64x2 = f64x2::new(6.0, -3.0); | |
13957 | let e: f64x2 = f64x2::new(1.0, -3.0); | |
13958 | let r: f64x2 = transmute(vpminnmq_f64(transmute(a), transmute(b))); | |
13959 | assert_eq!(r, e); | |
13960 | } | |
13961 | ||
13962 | #[simd_test(enable = "neon")] | |
13963 | unsafe fn test_vpminnmq_f32() { | |
13964 | let a: f32x4 = f32x4::new(1.0, 2.0, 3.0, -4.0); | |
13965 | let b: f32x4 = f32x4::new(8.0, 16.0, -1.0, 6.0); | |
13966 | let e: f32x4 = f32x4::new(1.0, -4.0, 8.0, -1.0); | |
13967 | let r: f32x4 = transmute(vpminnmq_f32(transmute(a), transmute(b))); | |
13968 | assert_eq!(r, e); | |
13969 | } | |
13970 | ||
13971 | #[simd_test(enable = "neon")] | |
13972 | unsafe fn test_vqdmullh_s16() { | |
13973 | let a: i16 = 2; | |
13974 | let b: i16 = 3; | |
13975 | let e: i32 = 12; | |
13976 | let r: i32 = transmute(vqdmullh_s16(transmute(a), transmute(b))); | |
13977 | assert_eq!(r, e); | |
13978 | } | |
13979 | ||
13980 | #[simd_test(enable = "neon")] | |
13981 | unsafe fn test_vqdmulls_s32() { | |
13982 | let a: i32 = 2; | |
13983 | let b: i32 = 3; | |
13984 | let e: i64 = 12; | |
13985 | let r: i64 = transmute(vqdmulls_s32(transmute(a), transmute(b))); | |
13986 | assert_eq!(r, e); | |
13987 | } | |
13988 | ||
13989 | #[simd_test(enable = "neon")] | |
13990 | unsafe fn test_vqdmull_high_s16() { | |
13991 | let a: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); | |
13992 | let b: i16x8 = i16x8::new(1, 2, 5, 6, 5, 6, 7, 8); | |
13993 | let e: i32x4 = i32x4::new(40, 60, 84, 112); | |
13994 | let r: i32x4 = transmute(vqdmull_high_s16(transmute(a), transmute(b))); | |
13995 | assert_eq!(r, e); | |
13996 | } | |
13997 | ||
13998 | #[simd_test(enable = "neon")] | |
13999 | unsafe fn test_vqdmull_high_s32() { | |
14000 | let a: i32x4 = i32x4::new(0, 1, 4, 5); | |
14001 | let b: i32x4 = i32x4::new(1, 2, 5, 6); | |
14002 | let e: i64x2 = i64x2::new(40, 60); | |
14003 | let r: i64x2 = transmute(vqdmull_high_s32(transmute(a), transmute(b))); | |
14004 | assert_eq!(r, e); | |
14005 | } | |
14006 | ||
14007 | #[simd_test(enable = "neon")] | |
14008 | unsafe fn test_vqdmull_high_n_s16() { | |
14009 | let a: i16x8 = i16x8::new(0, 2, 8, 10, 8, 10, 12, 14); | |
14010 | let b: i16 = 2; | |
14011 | let e: i32x4 = i32x4::new(32, 40, 48, 56); | |
14012 | let r: i32x4 = transmute(vqdmull_high_n_s16(transmute(a), transmute(b))); | |
14013 | assert_eq!(r, e); | |
14014 | } | |
14015 | ||
14016 | #[simd_test(enable = "neon")] | |
14017 | unsafe fn test_vqdmull_high_n_s32() { | |
14018 | let a: i32x4 = i32x4::new(0, 2, 8, 10); | |
14019 | let b: i32 = 2; | |
14020 | let e: i64x2 = i64x2::new(32, 40); | |
14021 | let r: i64x2 = transmute(vqdmull_high_n_s32(transmute(a), transmute(b))); | |
14022 | assert_eq!(r, e); | |
14023 | } | |
14024 | ||
14025 | #[simd_test(enable = "neon")] | |
14026 | unsafe fn test_vqdmull_laneq_s16() { | |
14027 | let a: i16x4 = i16x4::new(1, 2, 3, 4); | |
14028 | let b: i16x8 = i16x8::new(0, 2, 2, 0, 2, 0, 0, 0); | |
14029 | let e: i32x4 = i32x4::new(4, 8, 12, 16); | |
14030 | let r: i32x4 = transmute(vqdmull_laneq_s16::<4>(transmute(a), transmute(b))); | |
14031 | assert_eq!(r, e); | |
14032 | } | |
14033 | ||
14034 | #[simd_test(enable = "neon")] | |
14035 | unsafe fn test_vqdmull_laneq_s32() { | |
14036 | let a: i32x2 = i32x2::new(1, 2); | |
14037 | let b: i32x4 = i32x4::new(0, 2, 2, 0); | |
14038 | let e: i64x2 = i64x2::new(4, 8); | |
14039 | let r: i64x2 = transmute(vqdmull_laneq_s32::<2>(transmute(a), transmute(b))); | |
14040 | assert_eq!(r, e); | |
14041 | } | |
14042 | ||
14043 | #[simd_test(enable = "neon")] | |
14044 | unsafe fn test_vqdmullh_lane_s16() { | |
14045 | let a: i16 = 2; | |
14046 | let b: i16x4 = i16x4::new(0, 2, 2, 0); | |
14047 | let e: i32 = 8; | |
14048 | let r: i32 = transmute(vqdmullh_lane_s16::<2>(transmute(a), transmute(b))); | |
14049 | assert_eq!(r, e); | |
14050 | } | |
14051 | ||
14052 | #[simd_test(enable = "neon")] | |
14053 | unsafe fn test_vqdmullh_laneq_s16() { | |
14054 | let a: i16 = 2; | |
14055 | let b: i16x8 = i16x8::new(0, 2, 2, 0, 2, 0, 0, 0); | |
14056 | let e: i32 = 8; | |
14057 | let r: i32 = transmute(vqdmullh_laneq_s16::<4>(transmute(a), transmute(b))); | |
14058 | assert_eq!(r, e); | |
14059 | } | |
14060 | ||
14061 | #[simd_test(enable = "neon")] | |
14062 | unsafe fn test_vqdmulls_lane_s32() { | |
14063 | let a: i32 = 2; | |
14064 | let b: i32x2 = i32x2::new(0, 2); | |
14065 | let e: i64 = 8; | |
14066 | let r: i64 = transmute(vqdmulls_lane_s32::<1>(transmute(a), transmute(b))); | |
14067 | assert_eq!(r, e); | |
14068 | } | |
14069 | ||
14070 | #[simd_test(enable = "neon")] | |
14071 | unsafe fn test_vqdmulls_laneq_s32() { | |
14072 | let a: i32 = 2; | |
14073 | let b: i32x4 = i32x4::new(0, 2, 2, 0); | |
14074 | let e: i64 = 8; | |
14075 | let r: i64 = transmute(vqdmulls_laneq_s32::<2>(transmute(a), transmute(b))); | |
14076 | assert_eq!(r, e); | |
14077 | } | |
14078 | ||
14079 | #[simd_test(enable = "neon")] | |
14080 | unsafe fn test_vqdmull_high_lane_s16() { | |
14081 | let a: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); | |
14082 | let b: i16x4 = i16x4::new(0, 2, 2, 0); | |
14083 | let e: i32x4 = i32x4::new(16, 20, 24, 28); | |
14084 | let r: i32x4 = transmute(vqdmull_high_lane_s16::<2>(transmute(a), transmute(b))); | |
14085 | assert_eq!(r, e); | |
14086 | } | |
14087 | ||
14088 | #[simd_test(enable = "neon")] | |
14089 | unsafe fn test_vqdmull_high_lane_s32() { | |
14090 | let a: i32x4 = i32x4::new(0, 1, 4, 5); | |
14091 | let b: i32x2 = i32x2::new(0, 2); | |
14092 | let e: i64x2 = i64x2::new(16, 20); | |
14093 | let r: i64x2 = transmute(vqdmull_high_lane_s32::<1>(transmute(a), transmute(b))); | |
14094 | assert_eq!(r, e); | |
14095 | } | |
14096 | ||
14097 | #[simd_test(enable = "neon")] | |
14098 | unsafe fn test_vqdmull_high_laneq_s16() { | |
14099 | let a: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); | |
14100 | let b: i16x8 = i16x8::new(0, 2, 2, 0, 2, 0, 0, 0); | |
14101 | let e: i32x4 = i32x4::new(16, 20, 24, 28); | |
14102 | let r: i32x4 = transmute(vqdmull_high_laneq_s16::<4>(transmute(a), transmute(b))); | |
14103 | assert_eq!(r, e); | |
14104 | } | |
14105 | ||
14106 | #[simd_test(enable = "neon")] | |
14107 | unsafe fn test_vqdmull_high_laneq_s32() { | |
14108 | let a: i32x4 = i32x4::new(0, 1, 4, 5); | |
14109 | let b: i32x4 = i32x4::new(0, 2, 2, 0); | |
14110 | let e: i64x2 = i64x2::new(16, 20); | |
14111 | let r: i64x2 = transmute(vqdmull_high_laneq_s32::<2>(transmute(a), transmute(b))); | |
14112 | assert_eq!(r, e); | |
14113 | } | |
14114 | ||
14115 | #[simd_test(enable = "neon")] | |
14116 | unsafe fn test_vqdmlal_high_s16() { | |
14117 | let a: i32x4 = i32x4::new(1, 2, 3, 4); | |
14118 | let b: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); | |
14119 | let c: i16x8 = i16x8::new(1, 2, 5, 6, 5, 6, 7, 8); | |
14120 | let e: i32x4 = i32x4::new(41, 62, 87, 116); | |
14121 | let r: i32x4 = transmute(vqdmlal_high_s16(transmute(a), transmute(b), transmute(c))); | |
14122 | assert_eq!(r, e); | |
14123 | } | |
14124 | ||
14125 | #[simd_test(enable = "neon")] | |
14126 | unsafe fn test_vqdmlal_high_s32() { | |
14127 | let a: i64x2 = i64x2::new(1, 2); | |
14128 | let b: i32x4 = i32x4::new(0, 1, 4, 5); | |
14129 | let c: i32x4 = i32x4::new(1, 2, 5, 6); | |
14130 | let e: i64x2 = i64x2::new(41, 62); | |
14131 | let r: i64x2 = transmute(vqdmlal_high_s32(transmute(a), transmute(b), transmute(c))); | |
14132 | assert_eq!(r, e); | |
14133 | } | |
14134 | ||
14135 | #[simd_test(enable = "neon")] | |
14136 | unsafe fn test_vqdmlal_high_n_s16() { | |
14137 | let a: i32x4 = i32x4::new(1, 2, 3, 4); | |
14138 | let b: i16x8 = i16x8::new(0, 2, 8, 10, 8, 10, 12, 14); | |
14139 | let c: i16 = 2; | |
14140 | let e: i32x4 = i32x4::new(33, 42, 51, 60); | |
14141 | let r: i32x4 = transmute(vqdmlal_high_n_s16(transmute(a), transmute(b), transmute(c))); | |
14142 | assert_eq!(r, e); | |
14143 | } | |
14144 | ||
14145 | #[simd_test(enable = "neon")] | |
14146 | unsafe fn test_vqdmlal_high_n_s32() { | |
14147 | let a: i64x2 = i64x2::new(1, 2); | |
14148 | let b: i32x4 = i32x4::new(0, 2, 8, 10); | |
14149 | let c: i32 = 2; | |
14150 | let e: i64x2 = i64x2::new(33, 42); | |
14151 | let r: i64x2 = transmute(vqdmlal_high_n_s32(transmute(a), transmute(b), transmute(c))); | |
14152 | assert_eq!(r, e); | |
14153 | } | |
14154 | ||
14155 | #[simd_test(enable = "neon")] | |
14156 | unsafe fn test_vqdmlal_laneq_s16() { | |
14157 | let a: i32x4 = i32x4::new(1, 2, 3, 4); | |
14158 | let b: i16x4 = i16x4::new(1, 2, 3, 4); | |
14159 | let c: i16x8 = i16x8::new(0, 2, 2, 0, 2, 0, 0, 0); | |
14160 | let e: i32x4 = i32x4::new(5, 10, 15, 20); | |
14161 | let r: i32x4 = transmute(vqdmlal_laneq_s16::<2>(transmute(a), transmute(b), transmute(c))); | |
14162 | assert_eq!(r, e); | |
14163 | } | |
14164 | ||
14165 | #[simd_test(enable = "neon")] | |
14166 | unsafe fn test_vqdmlal_laneq_s32() { | |
14167 | let a: i64x2 = i64x2::new(1, 2); | |
14168 | let b: i32x2 = i32x2::new(1, 2); | |
14169 | let c: i32x4 = i32x4::new(0, 2, 2, 0); | |
14170 | let e: i64x2 = i64x2::new(5, 10); | |
14171 | let r: i64x2 = transmute(vqdmlal_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
14172 | assert_eq!(r, e); | |
14173 | } | |
14174 | ||
14175 | #[simd_test(enable = "neon")] | |
14176 | unsafe fn test_vqdmlal_high_lane_s16() { | |
14177 | let a: i32x4 = i32x4::new(1, 2, 3, 4); | |
14178 | let b: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); | |
14179 | let c: i16x4 = i16x4::new(0, 2, 0, 0); | |
14180 | let e: i32x4 = i32x4::new(17, 22, 27, 32); | |
14181 | let r: i32x4 = transmute(vqdmlal_high_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
14182 | assert_eq!(r, e); | |
14183 | } | |
14184 | ||
14185 | #[simd_test(enable = "neon")] | |
14186 | unsafe fn test_vqdmlal_high_laneq_s16() { | |
14187 | let a: i32x4 = i32x4::new(1, 2, 3, 4); | |
14188 | let b: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); | |
14189 | let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
14190 | let e: i32x4 = i32x4::new(17, 22, 27, 32); | |
14191 | let r: i32x4 = transmute(vqdmlal_high_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
14192 | assert_eq!(r, e); | |
14193 | } | |
14194 | ||
14195 | #[simd_test(enable = "neon")] | |
14196 | unsafe fn test_vqdmlal_high_lane_s32() { | |
14197 | let a: i64x2 = i64x2::new(1, 2); | |
14198 | let b: i32x4 = i32x4::new(0, 1, 4, 5); | |
14199 | let c: i32x2 = i32x2::new(0, 2); | |
14200 | let e: i64x2 = i64x2::new(17, 22); | |
14201 | let r: i64x2 = transmute(vqdmlal_high_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
14202 | assert_eq!(r, e); | |
14203 | } | |
14204 | ||
14205 | #[simd_test(enable = "neon")] | |
14206 | unsafe fn test_vqdmlal_high_laneq_s32() { | |
14207 | let a: i64x2 = i64x2::new(1, 2); | |
14208 | let b: i32x4 = i32x4::new(0, 1, 4, 5); | |
14209 | let c: i32x4 = i32x4::new(0, 2, 0, 0); | |
14210 | let e: i64x2 = i64x2::new(17, 22); | |
14211 | let r: i64x2 = transmute(vqdmlal_high_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
14212 | assert_eq!(r, e); | |
14213 | } | |
14214 | ||
14215 | #[simd_test(enable = "neon")] | |
14216 | unsafe fn test_vqdmlsl_high_s16() { | |
14217 | let a: i32x4 = i32x4::new(39, 58, 81, 108); | |
14218 | let b: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); | |
14219 | let c: i16x8 = i16x8::new(1, 2, 5, 6, 5, 6, 7, 8); | |
14220 | let e: i32x4 = i32x4::new(-1, -2, -3, -4); | |
14221 | let r: i32x4 = transmute(vqdmlsl_high_s16(transmute(a), transmute(b), transmute(c))); | |
14222 | assert_eq!(r, e); | |
14223 | } | |
14224 | ||
14225 | #[simd_test(enable = "neon")] | |
14226 | unsafe fn test_vqdmlsl_high_s32() { | |
14227 | let a: i64x2 = i64x2::new(39, 58); | |
14228 | let b: i32x4 = i32x4::new(0, 1, 4, 5); | |
14229 | let c: i32x4 = i32x4::new(1, 2, 5, 6); | |
14230 | let e: i64x2 = i64x2::new(-1, -2); | |
14231 | let r: i64x2 = transmute(vqdmlsl_high_s32(transmute(a), transmute(b), transmute(c))); | |
14232 | assert_eq!(r, e); | |
14233 | } | |
14234 | ||
14235 | #[simd_test(enable = "neon")] | |
14236 | unsafe fn test_vqdmlsl_high_n_s16() { | |
14237 | let a: i32x4 = i32x4::new(31, 38, 45, 52); | |
14238 | let b: i16x8 = i16x8::new(0, 2, 8, 10, 8, 10, 12, 14); | |
14239 | let c: i16 = 2; | |
14240 | let e: i32x4 = i32x4::new(-1, -2, -3, -4); | |
14241 | let r: i32x4 = transmute(vqdmlsl_high_n_s16(transmute(a), transmute(b), transmute(c))); | |
14242 | assert_eq!(r, e); | |
14243 | } | |
14244 | ||
14245 | #[simd_test(enable = "neon")] | |
14246 | unsafe fn test_vqdmlsl_high_n_s32() { | |
14247 | let a: i64x2 = i64x2::new(31, 38); | |
14248 | let b: i32x4 = i32x4::new(0, 2, 8, 10); | |
14249 | let c: i32 = 2; | |
14250 | let e: i64x2 = i64x2::new(-1, -2); | |
14251 | let r: i64x2 = transmute(vqdmlsl_high_n_s32(transmute(a), transmute(b), transmute(c))); | |
14252 | assert_eq!(r, e); | |
14253 | } | |
14254 | ||
14255 | #[simd_test(enable = "neon")] | |
14256 | unsafe fn test_vqdmlsl_laneq_s16() { | |
14257 | let a: i32x4 = i32x4::new(3, 6, 9, 12); | |
14258 | let b: i16x4 = i16x4::new(1, 2, 3, 4); | |
14259 | let c: i16x8 = i16x8::new(0, 2, 2, 0, 2, 0, 0, 0); | |
14260 | let e: i32x4 = i32x4::new(-1, -2, -3, -4); | |
14261 | let r: i32x4 = transmute(vqdmlsl_laneq_s16::<2>(transmute(a), transmute(b), transmute(c))); | |
14262 | assert_eq!(r, e); | |
14263 | } | |
14264 | ||
14265 | #[simd_test(enable = "neon")] | |
14266 | unsafe fn test_vqdmlsl_laneq_s32() { | |
14267 | let a: i64x2 = i64x2::new(3, 6); | |
14268 | let b: i32x2 = i32x2::new(1, 2); | |
14269 | let c: i32x4 = i32x4::new(0, 2, 2, 0); | |
14270 | let e: i64x2 = i64x2::new(-1, -2); | |
14271 | let r: i64x2 = transmute(vqdmlsl_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
14272 | assert_eq!(r, e); | |
14273 | } | |
14274 | ||
14275 | #[simd_test(enable = "neon")] | |
14276 | unsafe fn test_vqdmlsl_high_lane_s16() { | |
14277 | let a: i32x4 = i32x4::new(15, 18, 21, 24); | |
14278 | let b: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); | |
14279 | let c: i16x4 = i16x4::new(0, 2, 0, 0); | |
14280 | let e: i32x4 = i32x4::new(-1, -2, -3, -4); | |
14281 | let r: i32x4 = transmute(vqdmlsl_high_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
14282 | assert_eq!(r, e); | |
14283 | } | |
14284 | ||
14285 | #[simd_test(enable = "neon")] | |
14286 | unsafe fn test_vqdmlsl_high_laneq_s16() { | |
14287 | let a: i32x4 = i32x4::new(15, 18, 21, 24); | |
14288 | let b: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); | |
14289 | let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
14290 | let e: i32x4 = i32x4::new(-1, -2, -3, -4); | |
14291 | let r: i32x4 = transmute(vqdmlsl_high_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
14292 | assert_eq!(r, e); | |
14293 | } | |
14294 | ||
14295 | #[simd_test(enable = "neon")] | |
14296 | unsafe fn test_vqdmlsl_high_lane_s32() { | |
14297 | let a: i64x2 = i64x2::new(15, 18); | |
14298 | let b: i32x4 = i32x4::new(0, 1, 4, 5); | |
14299 | let c: i32x2 = i32x2::new(0, 2); | |
14300 | let e: i64x2 = i64x2::new(-1, -2); | |
14301 | let r: i64x2 = transmute(vqdmlsl_high_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
14302 | assert_eq!(r, e); | |
14303 | } | |
14304 | ||
14305 | #[simd_test(enable = "neon")] | |
14306 | unsafe fn test_vqdmlsl_high_laneq_s32() { | |
14307 | let a: i64x2 = i64x2::new(15, 18); | |
14308 | let b: i32x4 = i32x4::new(0, 1, 4, 5); | |
14309 | let c: i32x4 = i32x4::new(0, 2, 0, 0); | |
14310 | let e: i64x2 = i64x2::new(-1, -2); | |
14311 | let r: i64x2 = transmute(vqdmlsl_high_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
14312 | assert_eq!(r, e); | |
14313 | } | |
14314 | ||
14315 | #[simd_test(enable = "neon")] | |
14316 | unsafe fn test_vqdmulhh_s16() { | |
14317 | let a: i16 = 1; | |
14318 | let b: i16 = 2; | |
14319 | let e: i16 = 0; | |
14320 | let r: i16 = transmute(vqdmulhh_s16(transmute(a), transmute(b))); | |
14321 | assert_eq!(r, e); | |
14322 | } | |
14323 | ||
14324 | #[simd_test(enable = "neon")] | |
14325 | unsafe fn test_vqdmulhs_s32() { | |
14326 | let a: i32 = 1; | |
14327 | let b: i32 = 2; | |
14328 | let e: i32 = 0; | |
14329 | let r: i32 = transmute(vqdmulhs_s32(transmute(a), transmute(b))); | |
14330 | assert_eq!(r, e); | |
14331 | } | |
14332 | ||
14333 | #[simd_test(enable = "neon")] | |
14334 | unsafe fn test_vqdmulhh_lane_s16() { | |
14335 | let a: i16 = 2; | |
14336 | let b: i16x4 = i16x4::new(0, 0, 0x7F_FF, 0); | |
14337 | let e: i16 = 1; | |
14338 | let r: i16 = transmute(vqdmulhh_lane_s16::<2>(transmute(a), transmute(b))); | |
14339 | assert_eq!(r, e); | |
14340 | } | |
14341 | ||
14342 | #[simd_test(enable = "neon")] | |
14343 | unsafe fn test_vqdmulhh_laneq_s16() { | |
14344 | let a: i16 = 2; | |
14345 | let b: i16x8 = i16x8::new(0, 0, 0x7F_FF, 0, 0, 0, 0, 0); | |
14346 | let e: i16 = 1; | |
14347 | let r: i16 = transmute(vqdmulhh_laneq_s16::<2>(transmute(a), transmute(b))); | |
14348 | assert_eq!(r, e); | |
14349 | } | |
14350 | ||
14351 | #[simd_test(enable = "neon")] | |
14352 | unsafe fn test_vqdmulhs_lane_s32() { | |
14353 | let a: i32 = 2; | |
14354 | let b: i32x2 = i32x2::new(0, 0x7F_FF_FF_FF); | |
14355 | let e: i32 = 1; | |
14356 | let r: i32 = transmute(vqdmulhs_lane_s32::<1>(transmute(a), transmute(b))); | |
14357 | assert_eq!(r, e); | |
14358 | } | |
14359 | ||
14360 | #[simd_test(enable = "neon")] | |
14361 | unsafe fn test_vqdmulhs_laneq_s32() { | |
14362 | let a: i32 = 2; | |
14363 | let b: i32x4 = i32x4::new(0, 0x7F_FF_FF_FF, 0, 0); | |
14364 | let e: i32 = 1; | |
14365 | let r: i32 = transmute(vqdmulhs_laneq_s32::<1>(transmute(a), transmute(b))); | |
14366 | assert_eq!(r, e); | |
14367 | } | |
14368 | ||
14369 | #[simd_test(enable = "neon")] | |
14370 | unsafe fn test_vqmovnh_s16() { | |
14371 | let a: i16 = 1; | |
14372 | let e: i8 = 1; | |
14373 | let r: i8 = transmute(vqmovnh_s16(transmute(a))); | |
14374 | assert_eq!(r, e); | |
14375 | } | |
14376 | ||
14377 | #[simd_test(enable = "neon")] | |
14378 | unsafe fn test_vqmovns_s32() { | |
14379 | let a: i32 = 1; | |
14380 | let e: i16 = 1; | |
14381 | let r: i16 = transmute(vqmovns_s32(transmute(a))); | |
14382 | assert_eq!(r, e); | |
14383 | } | |
14384 | ||
14385 | #[simd_test(enable = "neon")] | |
14386 | unsafe fn test_vqmovnh_u16() { | |
14387 | let a: u16 = 1; | |
14388 | let e: u8 = 1; | |
14389 | let r: u8 = transmute(vqmovnh_u16(transmute(a))); | |
14390 | assert_eq!(r, e); | |
14391 | } | |
14392 | ||
14393 | #[simd_test(enable = "neon")] | |
14394 | unsafe fn test_vqmovns_u32() { | |
14395 | let a: u32 = 1; | |
14396 | let e: u16 = 1; | |
14397 | let r: u16 = transmute(vqmovns_u32(transmute(a))); | |
14398 | assert_eq!(r, e); | |
14399 | } | |
14400 | ||
14401 | #[simd_test(enable = "neon")] | |
14402 | unsafe fn test_vqmovnd_s64() { | |
14403 | let a: i64 = 1; | |
14404 | let e: i32 = 1; | |
14405 | let r: i32 = transmute(vqmovnd_s64(transmute(a))); | |
14406 | assert_eq!(r, e); | |
14407 | } | |
14408 | ||
14409 | #[simd_test(enable = "neon")] | |
14410 | unsafe fn test_vqmovnd_u64() { | |
14411 | let a: u64 = 1; | |
14412 | let e: u32 = 1; | |
14413 | let r: u32 = transmute(vqmovnd_u64(transmute(a))); | |
14414 | assert_eq!(r, e); | |
14415 | } | |
14416 | ||
14417 | #[simd_test(enable = "neon")] | |
14418 | unsafe fn test_vqmovn_high_s16() { | |
14419 | let a: i8x8 = i8x8::new(0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F); | |
14420 | let b: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); | |
14421 | let e: i8x16 = i8x16::new(0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F); | |
14422 | let r: i8x16 = transmute(vqmovn_high_s16(transmute(a), transmute(b))); | |
14423 | assert_eq!(r, e); | |
14424 | } | |
14425 | ||
14426 | #[simd_test(enable = "neon")] | |
14427 | unsafe fn test_vqmovn_high_s32() { | |
14428 | let a: i16x4 = i16x4::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); | |
14429 | let b: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF); | |
14430 | let e: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); | |
14431 | let r: i16x8 = transmute(vqmovn_high_s32(transmute(a), transmute(b))); | |
14432 | assert_eq!(r, e); | |
14433 | } | |
14434 | ||
14435 | #[simd_test(enable = "neon")] | |
14436 | unsafe fn test_vqmovn_high_s64() { | |
14437 | let a: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF); | |
14438 | let b: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 0x7F_FF_FF_FF_FF_FF_FF_FF); | |
14439 | let e: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF); | |
14440 | let r: i32x4 = transmute(vqmovn_high_s64(transmute(a), transmute(b))); | |
14441 | assert_eq!(r, e); | |
14442 | } | |
14443 | ||
14444 | #[simd_test(enable = "neon")] | |
14445 | unsafe fn test_vqmovn_high_u16() { | |
14446 | let a: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); | |
14447 | let b: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); | |
14448 | let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); | |
14449 | let r: u8x16 = transmute(vqmovn_high_u16(transmute(a), transmute(b))); | |
14450 | assert_eq!(r, e); | |
14451 | } | |
14452 | ||
14453 | #[simd_test(enable = "neon")] | |
14454 | unsafe fn test_vqmovn_high_u32() { | |
14455 | let a: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); | |
14456 | let b: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); | |
14457 | let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); | |
14458 | let r: u16x8 = transmute(vqmovn_high_u32(transmute(a), transmute(b))); | |
14459 | assert_eq!(r, e); | |
14460 | } | |
14461 | ||
14462 | #[simd_test(enable = "neon")] | |
14463 | unsafe fn test_vqmovn_high_u64() { | |
14464 | let a: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); | |
14465 | let b: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
14466 | let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); | |
14467 | let r: u32x4 = transmute(vqmovn_high_u64(transmute(a), transmute(b))); | |
14468 | assert_eq!(r, e); | |
14469 | } | |
14470 | ||
14471 | #[simd_test(enable = "neon")] | |
14472 | unsafe fn test_vqmovunh_s16() { | |
14473 | let a: i16 = 1; | |
14474 | let e: u8 = 1; | |
14475 | let r: u8 = transmute(vqmovunh_s16(transmute(a))); | |
14476 | assert_eq!(r, e); | |
14477 | } | |
14478 | ||
14479 | #[simd_test(enable = "neon")] | |
14480 | unsafe fn test_vqmovuns_s32() { | |
14481 | let a: i32 = 1; | |
14482 | let e: u16 = 1; | |
14483 | let r: u16 = transmute(vqmovuns_s32(transmute(a))); | |
14484 | assert_eq!(r, e); | |
14485 | } | |
14486 | ||
14487 | #[simd_test(enable = "neon")] | |
14488 | unsafe fn test_vqmovund_s64() { | |
14489 | let a: i64 = 1; | |
14490 | let e: u32 = 1; | |
14491 | let r: u32 = transmute(vqmovund_s64(transmute(a))); | |
14492 | assert_eq!(r, e); | |
14493 | } | |
14494 | ||
14495 | #[simd_test(enable = "neon")] | |
14496 | unsafe fn test_vqmovun_high_s16() { | |
14497 | let a: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
14498 | let b: i16x8 = i16x8::new(-1, -1, -1, -1, -1, -1, -1, -1); | |
14499 | let e: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
14500 | let r: u8x16 = transmute(vqmovun_high_s16(transmute(a), transmute(b))); | |
14501 | assert_eq!(r, e); | |
14502 | } | |
14503 | ||
14504 | #[simd_test(enable = "neon")] | |
14505 | unsafe fn test_vqmovun_high_s32() { | |
14506 | let a: u16x4 = u16x4::new(0, 0, 0, 0); | |
14507 | let b: i32x4 = i32x4::new(-1, -1, -1, -1); | |
14508 | let e: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
14509 | let r: u16x8 = transmute(vqmovun_high_s32(transmute(a), transmute(b))); | |
14510 | assert_eq!(r, e); | |
14511 | } | |
14512 | ||
14513 | #[simd_test(enable = "neon")] | |
14514 | unsafe fn test_vqmovun_high_s64() { | |
14515 | let a: u32x2 = u32x2::new(0, 0); | |
14516 | let b: i64x2 = i64x2::new(-1, -1); | |
14517 | let e: u32x4 = u32x4::new(0, 0, 0, 0); | |
14518 | let r: u32x4 = transmute(vqmovun_high_s64(transmute(a), transmute(b))); | |
14519 | assert_eq!(r, e); | |
14520 | } | |
14521 | ||
14522 | #[simd_test(enable = "neon")] | |
14523 | unsafe fn test_vqrdmulhh_s16() { | |
14524 | let a: i16 = 1; | |
14525 | let b: i16 = 2; | |
14526 | let e: i16 = 0; | |
14527 | let r: i16 = transmute(vqrdmulhh_s16(transmute(a), transmute(b))); | |
14528 | assert_eq!(r, e); | |
14529 | } | |
14530 | ||
14531 | #[simd_test(enable = "neon")] | |
14532 | unsafe fn test_vqrdmulhs_s32() { | |
14533 | let a: i32 = 1; | |
14534 | let b: i32 = 2; | |
14535 | let e: i32 = 0; | |
14536 | let r: i32 = transmute(vqrdmulhs_s32(transmute(a), transmute(b))); | |
14537 | assert_eq!(r, e); | |
14538 | } | |
14539 | ||
14540 | #[simd_test(enable = "neon")] | |
14541 | unsafe fn test_vqrdmulhh_lane_s16() { | |
14542 | let a: i16 = 1; | |
14543 | let b: i16x4 = i16x4::new(0, 2, 0, 0); | |
14544 | let e: i16 = 0; | |
14545 | let r: i16 = transmute(vqrdmulhh_lane_s16::<1>(transmute(a), transmute(b))); | |
14546 | assert_eq!(r, e); | |
14547 | } | |
14548 | ||
14549 | #[simd_test(enable = "neon")] | |
14550 | unsafe fn test_vqrdmulhh_laneq_s16() { | |
14551 | let a: i16 = 1; | |
14552 | let b: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
14553 | let e: i16 = 0; | |
14554 | let r: i16 = transmute(vqrdmulhh_laneq_s16::<1>(transmute(a), transmute(b))); | |
14555 | assert_eq!(r, e); | |
14556 | } | |
14557 | ||
14558 | #[simd_test(enable = "neon")] | |
14559 | unsafe fn test_vqrdmulhs_lane_s32() { | |
14560 | let a: i32 = 1; | |
14561 | let b: i32x2 = i32x2::new(0, 2); | |
14562 | let e: i32 = 0; | |
14563 | let r: i32 = transmute(vqrdmulhs_lane_s32::<1>(transmute(a), transmute(b))); | |
14564 | assert_eq!(r, e); | |
14565 | } | |
14566 | ||
14567 | #[simd_test(enable = "neon")] | |
14568 | unsafe fn test_vqrdmulhs_laneq_s32() { | |
14569 | let a: i32 = 1; | |
14570 | let b: i32x4 = i32x4::new(0, 2, 0, 0); | |
14571 | let e: i32 = 0; | |
14572 | let r: i32 = transmute(vqrdmulhs_laneq_s32::<1>(transmute(a), transmute(b))); | |
14573 | assert_eq!(r, e); | |
14574 | } | |
14575 | ||
14576 | #[simd_test(enable = "neon")] | |
14577 | unsafe fn test_vqrdmlahh_s16() { | |
14578 | let a: i16 = 1; | |
14579 | let b: i16 = 1; | |
14580 | let c: i16 = 2; | |
14581 | let e: i16 = 1; | |
14582 | let r: i16 = transmute(vqrdmlahh_s16(transmute(a), transmute(b), transmute(c))); | |
14583 | assert_eq!(r, e); | |
14584 | } | |
14585 | ||
14586 | #[simd_test(enable = "neon")] | |
14587 | unsafe fn test_vqrdmlahs_s32() { | |
14588 | let a: i32 = 1; | |
14589 | let b: i32 = 1; | |
14590 | let c: i32 = 2; | |
14591 | let e: i32 = 1; | |
14592 | let r: i32 = transmute(vqrdmlahs_s32(transmute(a), transmute(b), transmute(c))); | |
14593 | assert_eq!(r, e); | |
14594 | } | |
14595 | ||
14596 | #[simd_test(enable = "neon")] | |
14597 | unsafe fn test_vqrdmlahh_lane_s16() { | |
14598 | let a: i16 = 1; | |
14599 | let b: i16 = 1; | |
14600 | let c: i16x4 = i16x4::new(0, 2, 0, 0); | |
14601 | let e: i16 = 1; | |
14602 | let r: i16 = transmute(vqrdmlahh_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
14603 | assert_eq!(r, e); | |
14604 | } | |
14605 | ||
14606 | #[simd_test(enable = "neon")] | |
14607 | unsafe fn test_vqrdmlahh_laneq_s16() { | |
14608 | let a: i16 = 1; | |
14609 | let b: i16 = 1; | |
14610 | let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
14611 | let e: i16 = 1; | |
14612 | let r: i16 = transmute(vqrdmlahh_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
14613 | assert_eq!(r, e); | |
14614 | } | |
14615 | ||
14616 | #[simd_test(enable = "neon")] | |
14617 | unsafe fn test_vqrdmlahs_lane_s32() { | |
14618 | let a: i32 = 1; | |
14619 | let b: i32 = 1; | |
14620 | let c: i32x2 = i32x2::new(0, 2); | |
14621 | let e: i32 = 1; | |
14622 | let r: i32 = transmute(vqrdmlahs_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
14623 | assert_eq!(r, e); | |
14624 | } | |
14625 | ||
14626 | #[simd_test(enable = "neon")] | |
14627 | unsafe fn test_vqrdmlahs_laneq_s32() { | |
14628 | let a: i32 = 1; | |
14629 | let b: i32 = 1; | |
14630 | let c: i32x4 = i32x4::new(0, 2, 0, 0); | |
14631 | let e: i32 = 1; | |
14632 | let r: i32 = transmute(vqrdmlahs_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
14633 | assert_eq!(r, e); | |
14634 | } | |
14635 | ||
14636 | #[simd_test(enable = "neon")] | |
14637 | unsafe fn test_vqrdmlshh_s16() { | |
14638 | let a: i16 = 1; | |
14639 | let b: i16 = 1; | |
14640 | let c: i16 = 2; | |
14641 | let e: i16 = 1; | |
14642 | let r: i16 = transmute(vqrdmlshh_s16(transmute(a), transmute(b), transmute(c))); | |
14643 | assert_eq!(r, e); | |
14644 | } | |
14645 | ||
14646 | #[simd_test(enable = "neon")] | |
14647 | unsafe fn test_vqrdmlshs_s32() { | |
14648 | let a: i32 = 1; | |
14649 | let b: i32 = 1; | |
14650 | let c: i32 = 2; | |
14651 | let e: i32 = 1; | |
14652 | let r: i32 = transmute(vqrdmlshs_s32(transmute(a), transmute(b), transmute(c))); | |
14653 | assert_eq!(r, e); | |
14654 | } | |
14655 | ||
14656 | #[simd_test(enable = "neon")] | |
14657 | unsafe fn test_vqrdmlshh_lane_s16() { | |
14658 | let a: i16 = 1; | |
14659 | let b: i16 = 1; | |
14660 | let c: i16x4 = i16x4::new(0, 2, 0, 0); | |
14661 | let e: i16 = 1; | |
14662 | let r: i16 = transmute(vqrdmlshh_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
14663 | assert_eq!(r, e); | |
14664 | } | |
14665 | ||
14666 | #[simd_test(enable = "neon")] | |
14667 | unsafe fn test_vqrdmlshh_laneq_s16() { | |
14668 | let a: i16 = 1; | |
14669 | let b: i16 = 1; | |
14670 | let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
14671 | let e: i16 = 1; | |
14672 | let r: i16 = transmute(vqrdmlshh_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
14673 | assert_eq!(r, e); | |
14674 | } | |
14675 | ||
14676 | #[simd_test(enable = "neon")] | |
14677 | unsafe fn test_vqrdmlshs_lane_s32() { | |
14678 | let a: i32 = 1; | |
14679 | let b: i32 = 1; | |
14680 | let c: i32x2 = i32x2::new(0, 2); | |
14681 | let e: i32 = 1; | |
14682 | let r: i32 = transmute(vqrdmlshs_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
14683 | assert_eq!(r, e); | |
14684 | } | |
14685 | ||
14686 | #[simd_test(enable = "neon")] | |
14687 | unsafe fn test_vqrdmlshs_laneq_s32() { | |
14688 | let a: i32 = 1; | |
14689 | let b: i32 = 1; | |
14690 | let c: i32x4 = i32x4::new(0, 2, 0, 0); | |
14691 | let e: i32 = 1; | |
14692 | let r: i32 = transmute(vqrdmlshs_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
14693 | assert_eq!(r, e); | |
14694 | } | |
14695 | ||
14696 | #[simd_test(enable = "neon")] | |
14697 | unsafe fn test_vqrshls_s32() { | |
14698 | let a: i32 = 2; | |
14699 | let b: i32 = 2; | |
14700 | let e: i32 = 8; | |
14701 | let r: i32 = transmute(vqrshls_s32(transmute(a), transmute(b))); | |
14702 | assert_eq!(r, e); | |
14703 | } | |
14704 | ||
14705 | #[simd_test(enable = "neon")] | |
14706 | unsafe fn test_vqrshld_s64() { | |
14707 | let a: i64 = 2; | |
14708 | let b: i64 = 2; | |
14709 | let e: i64 = 8; | |
14710 | let r: i64 = transmute(vqrshld_s64(transmute(a), transmute(b))); | |
14711 | assert_eq!(r, e); | |
14712 | } | |
14713 | ||
14714 | #[simd_test(enable = "neon")] | |
14715 | unsafe fn test_vqrshlb_s8() { | |
14716 | let a: i8 = 1; | |
14717 | let b: i8 = 2; | |
14718 | let e: i8 = 4; | |
14719 | let r: i8 = transmute(vqrshlb_s8(transmute(a), transmute(b))); | |
14720 | assert_eq!(r, e); | |
14721 | } | |
14722 | ||
14723 | #[simd_test(enable = "neon")] | |
14724 | unsafe fn test_vqrshlh_s16() { | |
14725 | let a: i16 = 1; | |
14726 | let b: i16 = 2; | |
14727 | let e: i16 = 4; | |
14728 | let r: i16 = transmute(vqrshlh_s16(transmute(a), transmute(b))); | |
14729 | assert_eq!(r, e); | |
14730 | } | |
14731 | ||
14732 | #[simd_test(enable = "neon")] | |
14733 | unsafe fn test_vqrshls_u32() { | |
14734 | let a: u32 = 2; | |
14735 | let b: i32 = 2; | |
14736 | let e: u32 = 8; | |
14737 | let r: u32 = transmute(vqrshls_u32(transmute(a), transmute(b))); | |
14738 | assert_eq!(r, e); | |
14739 | } | |
14740 | ||
14741 | #[simd_test(enable = "neon")] | |
14742 | unsafe fn test_vqrshld_u64() { | |
14743 | let a: u64 = 2; | |
14744 | let b: i64 = 2; | |
14745 | let e: u64 = 8; | |
14746 | let r: u64 = transmute(vqrshld_u64(transmute(a), transmute(b))); | |
14747 | assert_eq!(r, e); | |
14748 | } | |
14749 | ||
14750 | #[simd_test(enable = "neon")] | |
14751 | unsafe fn test_vqrshlb_u8() { | |
14752 | let a: u8 = 1; | |
14753 | let b: i8 = 2; | |
14754 | let e: u8 = 4; | |
14755 | let r: u8 = transmute(vqrshlb_u8(transmute(a), transmute(b))); | |
14756 | assert_eq!(r, e); | |
14757 | } | |
14758 | ||
14759 | #[simd_test(enable = "neon")] | |
14760 | unsafe fn test_vqrshlh_u16() { | |
14761 | let a: u16 = 1; | |
14762 | let b: i16 = 2; | |
14763 | let e: u16 = 4; | |
14764 | let r: u16 = transmute(vqrshlh_u16(transmute(a), transmute(b))); | |
14765 | assert_eq!(r, e); | |
14766 | } | |
14767 | ||
14768 | #[simd_test(enable = "neon")] | |
14769 | unsafe fn test_vqrshrnh_n_s16() { | |
14770 | let a: i16 = 4; | |
14771 | let e: i8 = 1; | |
14772 | let r: i8 = transmute(vqrshrnh_n_s16::<2>(transmute(a))); | |
14773 | assert_eq!(r, e); | |
14774 | } | |
14775 | ||
14776 | #[simd_test(enable = "neon")] | |
14777 | unsafe fn test_vqrshrns_n_s32() { | |
14778 | let a: i32 = 4; | |
14779 | let e: i16 = 1; | |
14780 | let r: i16 = transmute(vqrshrns_n_s32::<2>(transmute(a))); | |
14781 | assert_eq!(r, e); | |
14782 | } | |
14783 | ||
14784 | #[simd_test(enable = "neon")] | |
14785 | unsafe fn test_vqrshrnd_n_s64() { | |
14786 | let a: i64 = 4; | |
14787 | let e: i32 = 1; | |
14788 | let r: i32 = transmute(vqrshrnd_n_s64::<2>(transmute(a))); | |
14789 | assert_eq!(r, e); | |
14790 | } | |
14791 | ||
14792 | #[simd_test(enable = "neon")] | |
14793 | unsafe fn test_vqrshrn_high_n_s16() { | |
14794 | let a: i8x8 = i8x8::new(0, 1, 2, 3, 2, 3, 6, 7); | |
14795 | let b: i16x8 = i16x8::new(8, 12, 24, 28, 48, 52, 56, 60); | |
14796 | let e: i8x16 = i8x16::new(0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 12, 13, 14, 15); | |
14797 | let r: i8x16 = transmute(vqrshrn_high_n_s16::<2>(transmute(a), transmute(b))); | |
14798 | assert_eq!(r, e); | |
14799 | } | |
14800 | ||
14801 | #[simd_test(enable = "neon")] | |
14802 | unsafe fn test_vqrshrn_high_n_s32() { | |
14803 | let a: i16x4 = i16x4::new(0, 1, 2, 3); | |
14804 | let b: i32x4 = i32x4::new(8, 12, 24, 28); | |
14805 | let e: i16x8 = i16x8::new(0, 1, 2, 3, 2, 3, 6, 7); | |
14806 | let r: i16x8 = transmute(vqrshrn_high_n_s32::<2>(transmute(a), transmute(b))); | |
14807 | assert_eq!(r, e); | |
14808 | } | |
14809 | ||
14810 | #[simd_test(enable = "neon")] | |
14811 | unsafe fn test_vqrshrn_high_n_s64() { | |
14812 | let a: i32x2 = i32x2::new(0, 1); | |
14813 | let b: i64x2 = i64x2::new(8, 12); | |
14814 | let e: i32x4 = i32x4::new(0, 1, 2, 3); | |
14815 | let r: i32x4 = transmute(vqrshrn_high_n_s64::<2>(transmute(a), transmute(b))); | |
14816 | assert_eq!(r, e); | |
14817 | } | |
14818 | ||
14819 | #[simd_test(enable = "neon")] | |
14820 | unsafe fn test_vqrshrnh_n_u16() { | |
14821 | let a: u16 = 4; | |
14822 | let e: u8 = 1; | |
14823 | let r: u8 = transmute(vqrshrnh_n_u16::<2>(transmute(a))); | |
14824 | assert_eq!(r, e); | |
14825 | } | |
14826 | ||
14827 | #[simd_test(enable = "neon")] | |
14828 | unsafe fn test_vqrshrns_n_u32() { | |
14829 | let a: u32 = 4; | |
14830 | let e: u16 = 1; | |
14831 | let r: u16 = transmute(vqrshrns_n_u32::<2>(transmute(a))); | |
14832 | assert_eq!(r, e); | |
14833 | } | |
14834 | ||
14835 | #[simd_test(enable = "neon")] | |
14836 | unsafe fn test_vqrshrnd_n_u64() { | |
14837 | let a: u64 = 4; | |
14838 | let e: u32 = 1; | |
14839 | let r: u32 = transmute(vqrshrnd_n_u64::<2>(transmute(a))); | |
14840 | assert_eq!(r, e); | |
14841 | } | |
14842 | ||
14843 | #[simd_test(enable = "neon")] | |
14844 | unsafe fn test_vqrshrn_high_n_u16() { | |
14845 | let a: u8x8 = u8x8::new(0, 1, 2, 3, 2, 3, 6, 7); | |
14846 | let b: u16x8 = u16x8::new(8, 12, 24, 28, 48, 52, 56, 60); | |
14847 | let e: u8x16 = u8x16::new(0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 12, 13, 14, 15); | |
14848 | let r: u8x16 = transmute(vqrshrn_high_n_u16::<2>(transmute(a), transmute(b))); | |
14849 | assert_eq!(r, e); | |
14850 | } | |
14851 | ||
14852 | #[simd_test(enable = "neon")] | |
14853 | unsafe fn test_vqrshrn_high_n_u32() { | |
14854 | let a: u16x4 = u16x4::new(0, 1, 2, 3); | |
14855 | let b: u32x4 = u32x4::new(8, 12, 24, 28); | |
14856 | let e: u16x8 = u16x8::new(0, 1, 2, 3, 2, 3, 6, 7); | |
14857 | let r: u16x8 = transmute(vqrshrn_high_n_u32::<2>(transmute(a), transmute(b))); | |
14858 | assert_eq!(r, e); | |
14859 | } | |
14860 | ||
14861 | #[simd_test(enable = "neon")] | |
14862 | unsafe fn test_vqrshrn_high_n_u64() { | |
14863 | let a: u32x2 = u32x2::new(0, 1); | |
14864 | let b: u64x2 = u64x2::new(8, 12); | |
14865 | let e: u32x4 = u32x4::new(0, 1, 2, 3); | |
14866 | let r: u32x4 = transmute(vqrshrn_high_n_u64::<2>(transmute(a), transmute(b))); | |
14867 | assert_eq!(r, e); | |
14868 | } | |
14869 | ||
14870 | #[simd_test(enable = "neon")] | |
14871 | unsafe fn test_vqrshrunh_n_s16() { | |
14872 | let a: i16 = 4; | |
14873 | let e: u8 = 1; | |
14874 | let r: u8 = transmute(vqrshrunh_n_s16::<2>(transmute(a))); | |
14875 | assert_eq!(r, e); | |
14876 | } | |
14877 | ||
14878 | #[simd_test(enable = "neon")] | |
14879 | unsafe fn test_vqrshruns_n_s32() { | |
14880 | let a: i32 = 4; | |
14881 | let e: u16 = 1; | |
14882 | let r: u16 = transmute(vqrshruns_n_s32::<2>(transmute(a))); | |
14883 | assert_eq!(r, e); | |
14884 | } | |
14885 | ||
14886 | #[simd_test(enable = "neon")] | |
14887 | unsafe fn test_vqrshrund_n_s64() { | |
14888 | let a: i64 = 4; | |
14889 | let e: u32 = 1; | |
14890 | let r: u32 = transmute(vqrshrund_n_s64::<2>(transmute(a))); | |
14891 | assert_eq!(r, e); | |
14892 | } | |
14893 | ||
14894 | #[simd_test(enable = "neon")] | |
14895 | unsafe fn test_vqrshrun_high_n_s16() { | |
14896 | let a: u8x8 = u8x8::new(0, 1, 2, 3, 2, 3, 6, 7); | |
14897 | let b: i16x8 = i16x8::new(8, 12, 24, 28, 48, 52, 56, 60); | |
14898 | let e: u8x16 = u8x16::new(0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 12, 13, 14, 15); | |
14899 | let r: u8x16 = transmute(vqrshrun_high_n_s16::<2>(transmute(a), transmute(b))); | |
14900 | assert_eq!(r, e); | |
14901 | } | |
14902 | ||
14903 | #[simd_test(enable = "neon")] | |
14904 | unsafe fn test_vqrshrun_high_n_s32() { | |
14905 | let a: u16x4 = u16x4::new(0, 1, 2, 3); | |
14906 | let b: i32x4 = i32x4::new(8, 12, 24, 28); | |
14907 | let e: u16x8 = u16x8::new(0, 1, 2, 3, 2, 3, 6, 7); | |
14908 | let r: u16x8 = transmute(vqrshrun_high_n_s32::<2>(transmute(a), transmute(b))); | |
14909 | assert_eq!(r, e); | |
14910 | } | |
14911 | ||
14912 | #[simd_test(enable = "neon")] | |
14913 | unsafe fn test_vqrshrun_high_n_s64() { | |
14914 | let a: u32x2 = u32x2::new(0, 1); | |
14915 | let b: i64x2 = i64x2::new(8, 12); | |
14916 | let e: u32x4 = u32x4::new(0, 1, 2, 3); | |
14917 | let r: u32x4 = transmute(vqrshrun_high_n_s64::<2>(transmute(a), transmute(b))); | |
14918 | assert_eq!(r, e); | |
14919 | } | |
14920 | ||
14921 | #[simd_test(enable = "neon")] | |
14922 | unsafe fn test_vqshld_s64() { | |
14923 | let a: i64 = 0; | |
14924 | let b: i64 = 2; | |
14925 | let e: i64 = 0; | |
14926 | let r: i64 = transmute(vqshld_s64(transmute(a), transmute(b))); | |
14927 | assert_eq!(r, e); | |
14928 | } | |
14929 | ||
14930 | #[simd_test(enable = "neon")] | |
14931 | unsafe fn test_vqshlb_s8() { | |
14932 | let a: i8 = 1; | |
14933 | let b: i8 = 2; | |
14934 | let e: i8 = 4; | |
14935 | let r: i8 = transmute(vqshlb_s8(transmute(a), transmute(b))); | |
14936 | assert_eq!(r, e); | |
14937 | } | |
14938 | ||
14939 | #[simd_test(enable = "neon")] | |
14940 | unsafe fn test_vqshlh_s16() { | |
14941 | let a: i16 = 1; | |
14942 | let b: i16 = 2; | |
14943 | let e: i16 = 4; | |
14944 | let r: i16 = transmute(vqshlh_s16(transmute(a), transmute(b))); | |
14945 | assert_eq!(r, e); | |
14946 | } | |
14947 | ||
14948 | #[simd_test(enable = "neon")] | |
14949 | unsafe fn test_vqshls_s32() { | |
14950 | let a: i32 = 1; | |
14951 | let b: i32 = 2; | |
14952 | let e: i32 = 4; | |
14953 | let r: i32 = transmute(vqshls_s32(transmute(a), transmute(b))); | |
14954 | assert_eq!(r, e); | |
14955 | } | |
14956 | ||
14957 | #[simd_test(enable = "neon")] | |
14958 | unsafe fn test_vqshld_u64() { | |
14959 | let a: u64 = 0; | |
14960 | let b: i64 = 2; | |
14961 | let e: u64 = 0; | |
14962 | let r: u64 = transmute(vqshld_u64(transmute(a), transmute(b))); | |
14963 | assert_eq!(r, e); | |
14964 | } | |
14965 | ||
14966 | #[simd_test(enable = "neon")] | |
14967 | unsafe fn test_vqshlb_u8() { | |
14968 | let a: u8 = 1; | |
14969 | let b: i8 = 2; | |
14970 | let e: u8 = 4; | |
14971 | let r: u8 = transmute(vqshlb_u8(transmute(a), transmute(b))); | |
14972 | assert_eq!(r, e); | |
14973 | } | |
14974 | ||
14975 | #[simd_test(enable = "neon")] | |
14976 | unsafe fn test_vqshlh_u16() { | |
14977 | let a: u16 = 1; | |
14978 | let b: i16 = 2; | |
14979 | let e: u16 = 4; | |
14980 | let r: u16 = transmute(vqshlh_u16(transmute(a), transmute(b))); | |
14981 | assert_eq!(r, e); | |
14982 | } | |
14983 | ||
14984 | #[simd_test(enable = "neon")] | |
14985 | unsafe fn test_vqshls_u32() { | |
14986 | let a: u32 = 1; | |
14987 | let b: i32 = 2; | |
14988 | let e: u32 = 4; | |
14989 | let r: u32 = transmute(vqshls_u32(transmute(a), transmute(b))); | |
14990 | assert_eq!(r, e); | |
14991 | } | |
14992 | ||
14993 | #[simd_test(enable = "neon")] | |
14994 | unsafe fn test_vqshlb_n_s8() { | |
14995 | let a: i8 = 1; | |
14996 | let e: i8 = 4; | |
14997 | let r: i8 = transmute(vqshlb_n_s8::<2>(transmute(a))); | |
14998 | assert_eq!(r, e); | |
14999 | } | |
15000 | ||
15001 | #[simd_test(enable = "neon")] | |
15002 | unsafe fn test_vqshlh_n_s16() { | |
15003 | let a: i16 = 1; | |
15004 | let e: i16 = 4; | |
15005 | let r: i16 = transmute(vqshlh_n_s16::<2>(transmute(a))); | |
15006 | assert_eq!(r, e); | |
15007 | } | |
15008 | ||
15009 | #[simd_test(enable = "neon")] | |
15010 | unsafe fn test_vqshls_n_s32() { | |
15011 | let a: i32 = 1; | |
15012 | let e: i32 = 4; | |
15013 | let r: i32 = transmute(vqshls_n_s32::<2>(transmute(a))); | |
15014 | assert_eq!(r, e); | |
15015 | } | |
15016 | ||
15017 | #[simd_test(enable = "neon")] | |
15018 | unsafe fn test_vqshld_n_s64() { | |
15019 | let a: i64 = 1; | |
15020 | let e: i64 = 4; | |
15021 | let r: i64 = transmute(vqshld_n_s64::<2>(transmute(a))); | |
15022 | assert_eq!(r, e); | |
15023 | } | |
15024 | ||
15025 | #[simd_test(enable = "neon")] | |
15026 | unsafe fn test_vqshlb_n_u8() { | |
15027 | let a: u8 = 1; | |
15028 | let e: u8 = 4; | |
15029 | let r: u8 = transmute(vqshlb_n_u8::<2>(transmute(a))); | |
15030 | assert_eq!(r, e); | |
15031 | } | |
15032 | ||
15033 | #[simd_test(enable = "neon")] | |
15034 | unsafe fn test_vqshlh_n_u16() { | |
15035 | let a: u16 = 1; | |
15036 | let e: u16 = 4; | |
15037 | let r: u16 = transmute(vqshlh_n_u16::<2>(transmute(a))); | |
15038 | assert_eq!(r, e); | |
15039 | } | |
15040 | ||
15041 | #[simd_test(enable = "neon")] | |
15042 | unsafe fn test_vqshls_n_u32() { | |
15043 | let a: u32 = 1; | |
15044 | let e: u32 = 4; | |
15045 | let r: u32 = transmute(vqshls_n_u32::<2>(transmute(a))); | |
15046 | assert_eq!(r, e); | |
15047 | } | |
15048 | ||
15049 | #[simd_test(enable = "neon")] | |
15050 | unsafe fn test_vqshld_n_u64() { | |
15051 | let a: u64 = 1; | |
15052 | let e: u64 = 4; | |
15053 | let r: u64 = transmute(vqshld_n_u64::<2>(transmute(a))); | |
15054 | assert_eq!(r, e); | |
15055 | } | |
15056 | ||
15057 | #[simd_test(enable = "neon")] | |
15058 | unsafe fn test_vqshrnd_n_s64() { | |
15059 | let a: i64 = 0; | |
15060 | let e: i32 = 0; | |
15061 | let r: i32 = transmute(vqshrnd_n_s64::<2>(transmute(a))); | |
15062 | assert_eq!(r, e); | |
15063 | } | |
15064 | ||
15065 | #[simd_test(enable = "neon")] | |
15066 | unsafe fn test_vqshrnh_n_s16() { | |
15067 | let a: i16 = 4; | |
15068 | let e: i8 = 1; | |
15069 | let r: i8 = transmute(vqshrnh_n_s16::<2>(transmute(a))); | |
15070 | assert_eq!(r, e); | |
15071 | } | |
15072 | ||
15073 | #[simd_test(enable = "neon")] | |
15074 | unsafe fn test_vqshrns_n_s32() { | |
15075 | let a: i32 = 4; | |
15076 | let e: i16 = 1; | |
15077 | let r: i16 = transmute(vqshrns_n_s32::<2>(transmute(a))); | |
15078 | assert_eq!(r, e); | |
15079 | } | |
15080 | ||
15081 | #[simd_test(enable = "neon")] | |
15082 | unsafe fn test_vqshrn_high_n_s16() { | |
15083 | let a: i8x8 = i8x8::new(0, 1, 8, 9, 8, 9, 10, 11); | |
15084 | let b: i16x8 = i16x8::new(32, 36, 40, 44, 48, 52, 56, 60); | |
15085 | let e: i8x16 = i8x16::new(0, 1, 8, 9, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15); | |
15086 | let r: i8x16 = transmute(vqshrn_high_n_s16::<2>(transmute(a), transmute(b))); | |
15087 | assert_eq!(r, e); | |
15088 | } | |
15089 | ||
15090 | #[simd_test(enable = "neon")] | |
15091 | unsafe fn test_vqshrn_high_n_s32() { | |
15092 | let a: i16x4 = i16x4::new(0, 1, 8, 9); | |
15093 | let b: i32x4 = i32x4::new(32, 36, 40, 44); | |
15094 | let e: i16x8 = i16x8::new(0, 1, 8, 9, 8, 9, 10, 11); | |
15095 | let r: i16x8 = transmute(vqshrn_high_n_s32::<2>(transmute(a), transmute(b))); | |
15096 | assert_eq!(r, e); | |
15097 | } | |
15098 | ||
15099 | #[simd_test(enable = "neon")] | |
15100 | unsafe fn test_vqshrn_high_n_s64() { | |
15101 | let a: i32x2 = i32x2::new(0, 1); | |
15102 | let b: i64x2 = i64x2::new(32, 36); | |
15103 | let e: i32x4 = i32x4::new(0, 1, 8, 9); | |
15104 | let r: i32x4 = transmute(vqshrn_high_n_s64::<2>(transmute(a), transmute(b))); | |
15105 | assert_eq!(r, e); | |
15106 | } | |
15107 | ||
15108 | #[simd_test(enable = "neon")] | |
15109 | unsafe fn test_vqshrnd_n_u64() { | |
15110 | let a: u64 = 0; | |
15111 | let e: u32 = 0; | |
15112 | let r: u32 = transmute(vqshrnd_n_u64::<2>(transmute(a))); | |
15113 | assert_eq!(r, e); | |
15114 | } | |
15115 | ||
15116 | #[simd_test(enable = "neon")] | |
15117 | unsafe fn test_vqshrnh_n_u16() { | |
15118 | let a: u16 = 4; | |
15119 | let e: u8 = 1; | |
15120 | let r: u8 = transmute(vqshrnh_n_u16::<2>(transmute(a))); | |
15121 | assert_eq!(r, e); | |
15122 | } | |
15123 | ||
15124 | #[simd_test(enable = "neon")] | |
15125 | unsafe fn test_vqshrns_n_u32() { | |
15126 | let a: u32 = 4; | |
15127 | let e: u16 = 1; | |
15128 | let r: u16 = transmute(vqshrns_n_u32::<2>(transmute(a))); | |
15129 | assert_eq!(r, e); | |
15130 | } | |
15131 | ||
15132 | #[simd_test(enable = "neon")] | |
15133 | unsafe fn test_vqshrn_high_n_u16() { | |
15134 | let a: u8x8 = u8x8::new(0, 1, 8, 9, 8, 9, 10, 11); | |
15135 | let b: u16x8 = u16x8::new(32, 36, 40, 44, 48, 52, 56, 60); | |
15136 | let e: u8x16 = u8x16::new(0, 1, 8, 9, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15); | |
15137 | let r: u8x16 = transmute(vqshrn_high_n_u16::<2>(transmute(a), transmute(b))); | |
15138 | assert_eq!(r, e); | |
15139 | } | |
15140 | ||
15141 | #[simd_test(enable = "neon")] | |
15142 | unsafe fn test_vqshrn_high_n_u32() { | |
15143 | let a: u16x4 = u16x4::new(0, 1, 8, 9); | |
15144 | let b: u32x4 = u32x4::new(32, 36, 40, 44); | |
15145 | let e: u16x8 = u16x8::new(0, 1, 8, 9, 8, 9, 10, 11); | |
15146 | let r: u16x8 = transmute(vqshrn_high_n_u32::<2>(transmute(a), transmute(b))); | |
15147 | assert_eq!(r, e); | |
15148 | } | |
15149 | ||
15150 | #[simd_test(enable = "neon")] | |
15151 | unsafe fn test_vqshrn_high_n_u64() { | |
15152 | let a: u32x2 = u32x2::new(0, 1); | |
15153 | let b: u64x2 = u64x2::new(32, 36); | |
15154 | let e: u32x4 = u32x4::new(0, 1, 8, 9); | |
15155 | let r: u32x4 = transmute(vqshrn_high_n_u64::<2>(transmute(a), transmute(b))); | |
15156 | assert_eq!(r, e); | |
15157 | } | |
15158 | ||
15159 | #[simd_test(enable = "neon")] | |
15160 | unsafe fn test_vqshrunh_n_s16() { | |
15161 | let a: i16 = 4; | |
15162 | let e: u8 = 1; | |
15163 | let r: u8 = transmute(vqshrunh_n_s16::<2>(transmute(a))); | |
15164 | assert_eq!(r, e); | |
15165 | } | |
15166 | ||
15167 | #[simd_test(enable = "neon")] | |
15168 | unsafe fn test_vqshruns_n_s32() { | |
15169 | let a: i32 = 4; | |
15170 | let e: u16 = 1; | |
15171 | let r: u16 = transmute(vqshruns_n_s32::<2>(transmute(a))); | |
15172 | assert_eq!(r, e); | |
15173 | } | |
15174 | ||
15175 | #[simd_test(enable = "neon")] | |
15176 | unsafe fn test_vqshrund_n_s64() { | |
15177 | let a: i64 = 4; | |
15178 | let e: u32 = 1; | |
15179 | let r: u32 = transmute(vqshrund_n_s64::<2>(transmute(a))); | |
15180 | assert_eq!(r, e); | |
15181 | } | |
15182 | ||
15183 | #[simd_test(enable = "neon")] | |
15184 | unsafe fn test_vqshrun_high_n_s16() { | |
15185 | let a: u8x8 = u8x8::new(0, 1, 8, 9, 8, 9, 10, 11); | |
15186 | let b: i16x8 = i16x8::new(32, 36, 40, 44, 48, 52, 56, 60); | |
15187 | let e: u8x16 = u8x16::new(0, 1, 8, 9, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15); | |
15188 | let r: u8x16 = transmute(vqshrun_high_n_s16::<2>(transmute(a), transmute(b))); | |
15189 | assert_eq!(r, e); | |
15190 | } | |
15191 | ||
15192 | #[simd_test(enable = "neon")] | |
15193 | unsafe fn test_vqshrun_high_n_s32() { | |
15194 | let a: u16x4 = u16x4::new(0, 1, 8, 9); | |
15195 | let b: i32x4 = i32x4::new(32, 36, 40, 44); | |
15196 | let e: u16x8 = u16x8::new(0, 1, 8, 9, 8, 9, 10, 11); | |
15197 | let r: u16x8 = transmute(vqshrun_high_n_s32::<2>(transmute(a), transmute(b))); | |
15198 | assert_eq!(r, e); | |
15199 | } | |
15200 | ||
15201 | #[simd_test(enable = "neon")] | |
15202 | unsafe fn test_vqshrun_high_n_s64() { | |
15203 | let a: u32x2 = u32x2::new(0, 1); | |
15204 | let b: i64x2 = i64x2::new(32, 36); | |
15205 | let e: u32x4 = u32x4::new(0, 1, 8, 9); | |
15206 | let r: u32x4 = transmute(vqshrun_high_n_s64::<2>(transmute(a), transmute(b))); | |
15207 | assert_eq!(r, e); | |
15208 | } | |
15209 | ||
15210 | #[simd_test(enable = "neon")] | |
15211 | unsafe fn test_vsqrt_f32() { | |
15212 | let a: f32x2 = f32x2::new(4.0, 9.0); | |
15213 | let e: f32x2 = f32x2::new(2.0, 3.0); | |
15214 | let r: f32x2 = transmute(vsqrt_f32(transmute(a))); | |
15215 | assert_eq!(r, e); | |
15216 | } | |
15217 | ||
15218 | #[simd_test(enable = "neon")] | |
15219 | unsafe fn test_vsqrtq_f32() { | |
15220 | let a: f32x4 = f32x4::new(4.0, 9.0, 16.0, 25.0); | |
15221 | let e: f32x4 = f32x4::new(2.0, 3.0, 4.0, 5.0); | |
15222 | let r: f32x4 = transmute(vsqrtq_f32(transmute(a))); | |
15223 | assert_eq!(r, e); | |
15224 | } | |
15225 | ||
15226 | #[simd_test(enable = "neon")] | |
15227 | unsafe fn test_vsqrt_f64() { | |
15228 | let a: f64 = 4.0; | |
15229 | let e: f64 = 2.0; | |
15230 | let r: f64 = transmute(vsqrt_f64(transmute(a))); | |
15231 | assert_eq!(r, e); | |
15232 | } | |
15233 | ||
15234 | #[simd_test(enable = "neon")] | |
15235 | unsafe fn test_vsqrtq_f64() { | |
15236 | let a: f64x2 = f64x2::new(4.0, 9.0); | |
15237 | let e: f64x2 = f64x2::new(2.0, 3.0); | |
15238 | let r: f64x2 = transmute(vsqrtq_f64(transmute(a))); | |
15239 | assert_eq!(r, e); | |
15240 | } | |
15241 | ||
15242 | #[simd_test(enable = "neon")] | |
15243 | unsafe fn test_vrsqrte_f64() { | |
15244 | let a: f64 = 1.0; | |
15245 | let e: f64 = 0.998046875; | |
15246 | let r: f64 = transmute(vrsqrte_f64(transmute(a))); | |
15247 | assert_eq!(r, e); | |
15248 | } | |
15249 | ||
15250 | #[simd_test(enable = "neon")] | |
15251 | unsafe fn test_vrsqrteq_f64() { | |
15252 | let a: f64x2 = f64x2::new(1.0, 2.0); | |
15253 | let e: f64x2 = f64x2::new(0.998046875, 0.705078125); | |
15254 | let r: f64x2 = transmute(vrsqrteq_f64(transmute(a))); | |
15255 | assert_eq!(r, e); | |
15256 | } | |
15257 | ||
15258 | #[simd_test(enable = "neon")] | |
15259 | unsafe fn test_vrecpe_f64() { | |
15260 | let a: f64 = 4.0; | |
15261 | let e: f64 = 0.24951171875; | |
15262 | let r: f64 = transmute(vrecpe_f64(transmute(a))); | |
15263 | assert_eq!(r, e); | |
15264 | } | |
15265 | ||
15266 | #[simd_test(enable = "neon")] | |
15267 | unsafe fn test_vrecpeq_f64() { | |
15268 | let a: f64x2 = f64x2::new(4.0, 3.0); | |
15269 | let e: f64x2 = f64x2::new(0.24951171875, 0.3330078125); | |
15270 | let r: f64x2 = transmute(vrecpeq_f64(transmute(a))); | |
15271 | assert_eq!(r, e); | |
15272 | } | |
15273 | ||
15274 | #[simd_test(enable = "neon")] | |
15275 | unsafe fn test_vreinterpret_s64_p64() { | |
15276 | let a: i64x1 = i64x1::new(0); | |
15277 | let e: i64x1 = i64x1::new(0); | |
15278 | let r: i64x1 = transmute(vreinterpret_s64_p64(transmute(a))); | |
15279 | assert_eq!(r, e); | |
15280 | } | |
15281 | ||
15282 | #[simd_test(enable = "neon")] | |
15283 | unsafe fn test_vreinterpret_u64_p64() { | |
15284 | let a: i64x1 = i64x1::new(0); | |
15285 | let e: u64x1 = u64x1::new(0); | |
15286 | let r: u64x1 = transmute(vreinterpret_u64_p64(transmute(a))); | |
15287 | assert_eq!(r, e); | |
15288 | } | |
15289 | ||
15290 | #[simd_test(enable = "neon")] | |
15291 | unsafe fn test_vreinterpret_p64_s64() { | |
15292 | let a: i64x1 = i64x1::new(0); | |
15293 | let e: i64x1 = i64x1::new(0); | |
15294 | let r: i64x1 = transmute(vreinterpret_p64_s64(transmute(a))); | |
15295 | assert_eq!(r, e); | |
15296 | } | |
15297 | ||
15298 | #[simd_test(enable = "neon")] | |
15299 | unsafe fn test_vreinterpret_p64_u64() { | |
15300 | let a: u64x1 = u64x1::new(0); | |
15301 | let e: i64x1 = i64x1::new(0); | |
15302 | let r: i64x1 = transmute(vreinterpret_p64_u64(transmute(a))); | |
15303 | assert_eq!(r, e); | |
15304 | } | |
15305 | ||
15306 | #[simd_test(enable = "neon")] | |
15307 | unsafe fn test_vreinterpretq_s64_p64() { | |
15308 | let a: i64x2 = i64x2::new(0, 1); | |
15309 | let e: i64x2 = i64x2::new(0, 1); | |
15310 | let r: i64x2 = transmute(vreinterpretq_s64_p64(transmute(a))); | |
15311 | assert_eq!(r, e); | |
15312 | } | |
15313 | ||
15314 | #[simd_test(enable = "neon")] | |
15315 | unsafe fn test_vreinterpretq_u64_p64() { | |
15316 | let a: i64x2 = i64x2::new(0, 1); | |
15317 | let e: u64x2 = u64x2::new(0, 1); | |
15318 | let r: u64x2 = transmute(vreinterpretq_u64_p64(transmute(a))); | |
15319 | assert_eq!(r, e); | |
15320 | } | |
15321 | ||
15322 | #[simd_test(enable = "neon")] | |
15323 | unsafe fn test_vreinterpretq_p64_s64() { | |
15324 | let a: i64x2 = i64x2::new(0, 1); | |
15325 | let e: i64x2 = i64x2::new(0, 1); | |
15326 | let r: i64x2 = transmute(vreinterpretq_p64_s64(transmute(a))); | |
15327 | assert_eq!(r, e); | |
15328 | } | |
15329 | ||
15330 | #[simd_test(enable = "neon")] | |
15331 | unsafe fn test_vreinterpretq_p64_u64() { | |
15332 | let a: u64x2 = u64x2::new(0, 1); | |
15333 | let e: i64x2 = i64x2::new(0, 1); | |
15334 | let r: i64x2 = transmute(vreinterpretq_p64_u64(transmute(a))); | |
15335 | assert_eq!(r, e); | |
15336 | } | |
15337 | ||
15338 | #[simd_test(enable = "neon")] | |
15339 | unsafe fn test_vreinterpret_s32_p64() { | |
15340 | let a: i64x1 = i64x1::new(0); | |
15341 | let e: i32x2 = i32x2::new(0, 0); | |
15342 | let r: i32x2 = transmute(vreinterpret_s32_p64(transmute(a))); | |
15343 | assert_eq!(r, e); | |
15344 | } | |
15345 | ||
15346 | #[simd_test(enable = "neon")] | |
15347 | unsafe fn test_vreinterpret_u32_p64() { | |
15348 | let a: i64x1 = i64x1::new(0); | |
15349 | let e: u32x2 = u32x2::new(0, 0); | |
15350 | let r: u32x2 = transmute(vreinterpret_u32_p64(transmute(a))); | |
15351 | assert_eq!(r, e); | |
15352 | } | |
15353 | ||
15354 | #[simd_test(enable = "neon")] | |
15355 | unsafe fn test_vreinterpretq_s32_p64() { | |
15356 | let a: i64x2 = i64x2::new(0, 1); | |
15357 | let e: i32x4 = i32x4::new(0, 0, 1, 0); | |
15358 | let r: i32x4 = transmute(vreinterpretq_s32_p64(transmute(a))); | |
15359 | assert_eq!(r, e); | |
15360 | } | |
15361 | ||
15362 | #[simd_test(enable = "neon")] | |
15363 | unsafe fn test_vreinterpretq_u32_p64() { | |
15364 | let a: i64x2 = i64x2::new(0, 1); | |
15365 | let e: u32x4 = u32x4::new(0, 0, 1, 0); | |
15366 | let r: u32x4 = transmute(vreinterpretq_u32_p64(transmute(a))); | |
15367 | assert_eq!(r, e); | |
15368 | } | |
15369 | ||
15370 | #[simd_test(enable = "neon")] | |
15371 | unsafe fn test_vreinterpret_p64_s32() { | |
15372 | let a: i32x2 = i32x2::new(0, 0); | |
15373 | let e: i64x1 = i64x1::new(0); | |
15374 | let r: i64x1 = transmute(vreinterpret_p64_s32(transmute(a))); | |
15375 | assert_eq!(r, e); | |
15376 | } | |
15377 | ||
15378 | #[simd_test(enable = "neon")] | |
15379 | unsafe fn test_vreinterpret_p64_u32() { | |
15380 | let a: u32x2 = u32x2::new(0, 0); | |
15381 | let e: i64x1 = i64x1::new(0); | |
15382 | let r: i64x1 = transmute(vreinterpret_p64_u32(transmute(a))); | |
15383 | assert_eq!(r, e); | |
15384 | } | |
15385 | ||
15386 | #[simd_test(enable = "neon")] | |
15387 | unsafe fn test_vreinterpretq_p64_s32() { | |
15388 | let a: i32x4 = i32x4::new(0, 0, 1, 0); | |
15389 | let e: i64x2 = i64x2::new(0, 1); | |
15390 | let r: i64x2 = transmute(vreinterpretq_p64_s32(transmute(a))); | |
15391 | assert_eq!(r, e); | |
15392 | } | |
15393 | ||
15394 | #[simd_test(enable = "neon")] | |
15395 | unsafe fn test_vreinterpretq_p64_u32() { | |
15396 | let a: u32x4 = u32x4::new(0, 0, 1, 0); | |
15397 | let e: i64x2 = i64x2::new(0, 1); | |
15398 | let r: i64x2 = transmute(vreinterpretq_p64_u32(transmute(a))); | |
15399 | assert_eq!(r, e); | |
15400 | } | |
15401 | ||
15402 | #[simd_test(enable = "neon")] | |
15403 | unsafe fn test_vreinterpret_s16_p64() { | |
15404 | let a: i64x1 = i64x1::new(0); | |
15405 | let e: i16x4 = i16x4::new(0, 0, 0, 0); | |
15406 | let r: i16x4 = transmute(vreinterpret_s16_p64(transmute(a))); | |
15407 | assert_eq!(r, e); | |
15408 | } | |
15409 | ||
15410 | #[simd_test(enable = "neon")] | |
15411 | unsafe fn test_vreinterpret_u16_p64() { | |
15412 | let a: i64x1 = i64x1::new(0); | |
15413 | let e: u16x4 = u16x4::new(0, 0, 0, 0); | |
15414 | let r: u16x4 = transmute(vreinterpret_u16_p64(transmute(a))); | |
15415 | assert_eq!(r, e); | |
15416 | } | |
15417 | ||
15418 | #[simd_test(enable = "neon")] | |
15419 | unsafe fn test_vreinterpret_p16_p64() { | |
15420 | let a: i64x1 = i64x1::new(0); | |
15421 | let e: i16x4 = i16x4::new(0, 0, 0, 0); | |
15422 | let r: i16x4 = transmute(vreinterpret_p16_p64(transmute(a))); | |
15423 | assert_eq!(r, e); | |
15424 | } | |
15425 | ||
15426 | #[simd_test(enable = "neon")] | |
15427 | unsafe fn test_vreinterpretq_s16_p64() { | |
15428 | let a: i64x2 = i64x2::new(0, 1); | |
15429 | let e: i16x8 = i16x8::new(0, 0, 0, 0, 1, 0, 0, 0); | |
15430 | let r: i16x8 = transmute(vreinterpretq_s16_p64(transmute(a))); | |
15431 | assert_eq!(r, e); | |
15432 | } | |
15433 | ||
15434 | #[simd_test(enable = "neon")] | |
15435 | unsafe fn test_vreinterpretq_u16_p64() { | |
15436 | let a: i64x2 = i64x2::new(0, 1); | |
15437 | let e: u16x8 = u16x8::new(0, 0, 0, 0, 1, 0, 0, 0); | |
15438 | let r: u16x8 = transmute(vreinterpretq_u16_p64(transmute(a))); | |
15439 | assert_eq!(r, e); | |
15440 | } | |
15441 | ||
15442 | #[simd_test(enable = "neon")] | |
15443 | unsafe fn test_vreinterpretq_p16_p64() { | |
15444 | let a: i64x2 = i64x2::new(0, 1); | |
15445 | let e: i16x8 = i16x8::new(0, 0, 0, 0, 1, 0, 0, 0); | |
15446 | let r: i16x8 = transmute(vreinterpretq_p16_p64(transmute(a))); | |
15447 | assert_eq!(r, e); | |
15448 | } | |
15449 | ||
15450 | #[simd_test(enable = "neon")] | |
15451 | unsafe fn test_vreinterpret_p64_p16() { | |
15452 | let a: i16x4 = i16x4::new(0, 0, 0, 0); | |
15453 | let e: i64x1 = i64x1::new(0); | |
15454 | let r: i64x1 = transmute(vreinterpret_p64_p16(transmute(a))); | |
15455 | assert_eq!(r, e); | |
15456 | } | |
15457 | ||
15458 | #[simd_test(enable = "neon")] | |
15459 | unsafe fn test_vreinterpret_p64_s16() { | |
15460 | let a: i16x4 = i16x4::new(0, 0, 0, 0); | |
15461 | let e: i64x1 = i64x1::new(0); | |
15462 | let r: i64x1 = transmute(vreinterpret_p64_s16(transmute(a))); | |
15463 | assert_eq!(r, e); | |
15464 | } | |
15465 | ||
15466 | #[simd_test(enable = "neon")] | |
15467 | unsafe fn test_vreinterpret_p64_u16() { | |
15468 | let a: u16x4 = u16x4::new(0, 0, 0, 0); | |
15469 | let e: i64x1 = i64x1::new(0); | |
15470 | let r: i64x1 = transmute(vreinterpret_p64_u16(transmute(a))); | |
15471 | assert_eq!(r, e); | |
15472 | } | |
15473 | ||
15474 | #[simd_test(enable = "neon")] | |
15475 | unsafe fn test_vreinterpretq_p64_p16() { | |
15476 | let a: i16x8 = i16x8::new(0, 0, 0, 0, 1, 0, 0, 0); | |
15477 | let e: i64x2 = i64x2::new(0, 1); | |
15478 | let r: i64x2 = transmute(vreinterpretq_p64_p16(transmute(a))); | |
15479 | assert_eq!(r, e); | |
15480 | } | |
15481 | ||
15482 | #[simd_test(enable = "neon")] | |
15483 | unsafe fn test_vreinterpretq_p64_s16() { | |
15484 | let a: i16x8 = i16x8::new(0, 0, 0, 0, 1, 0, 0, 0); | |
15485 | let e: i64x2 = i64x2::new(0, 1); | |
15486 | let r: i64x2 = transmute(vreinterpretq_p64_s16(transmute(a))); | |
15487 | assert_eq!(r, e); | |
15488 | } | |
15489 | ||
15490 | #[simd_test(enable = "neon")] | |
15491 | unsafe fn test_vreinterpretq_p64_u16() { | |
15492 | let a: u16x8 = u16x8::new(0, 0, 0, 0, 1, 0, 0, 0); | |
15493 | let e: i64x2 = i64x2::new(0, 1); | |
15494 | let r: i64x2 = transmute(vreinterpretq_p64_u16(transmute(a))); | |
15495 | assert_eq!(r, e); | |
15496 | } | |
15497 | ||
15498 | #[simd_test(enable = "neon")] | |
15499 | unsafe fn test_vreinterpret_s8_p64() { | |
15500 | let a: i64x1 = i64x1::new(0); | |
15501 | let e: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15502 | let r: i8x8 = transmute(vreinterpret_s8_p64(transmute(a))); | |
15503 | assert_eq!(r, e); | |
15504 | } | |
15505 | ||
15506 | #[simd_test(enable = "neon")] | |
15507 | unsafe fn test_vreinterpret_u8_p64() { | |
15508 | let a: i64x1 = i64x1::new(0); | |
15509 | let e: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15510 | let r: u8x8 = transmute(vreinterpret_u8_p64(transmute(a))); | |
15511 | assert_eq!(r, e); | |
15512 | } | |
15513 | ||
15514 | #[simd_test(enable = "neon")] | |
15515 | unsafe fn test_vreinterpret_p8_p64() { | |
15516 | let a: i64x1 = i64x1::new(0); | |
15517 | let e: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15518 | let r: i8x8 = transmute(vreinterpret_p8_p64(transmute(a))); | |
15519 | assert_eq!(r, e); | |
15520 | } | |
15521 | ||
15522 | #[simd_test(enable = "neon")] | |
15523 | unsafe fn test_vreinterpretq_s8_p64() { | |
15524 | let a: i64x2 = i64x2::new(0, 1); | |
15525 | let e: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); | |
15526 | let r: i8x16 = transmute(vreinterpretq_s8_p64(transmute(a))); | |
15527 | assert_eq!(r, e); | |
15528 | } | |
15529 | ||
15530 | #[simd_test(enable = "neon")] | |
15531 | unsafe fn test_vreinterpretq_u8_p64() { | |
15532 | let a: i64x2 = i64x2::new(0, 1); | |
15533 | let e: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); | |
15534 | let r: u8x16 = transmute(vreinterpretq_u8_p64(transmute(a))); | |
15535 | assert_eq!(r, e); | |
15536 | } | |
15537 | ||
15538 | #[simd_test(enable = "neon")] | |
15539 | unsafe fn test_vreinterpretq_p8_p64() { | |
15540 | let a: i64x2 = i64x2::new(0, 1); | |
15541 | let e: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); | |
15542 | let r: i8x16 = transmute(vreinterpretq_p8_p64(transmute(a))); | |
15543 | assert_eq!(r, e); | |
15544 | } | |
15545 | ||
15546 | #[simd_test(enable = "neon")] | |
15547 | unsafe fn test_vreinterpret_p64_p8() { | |
15548 | let a: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15549 | let e: i64x1 = i64x1::new(0); | |
15550 | let r: i64x1 = transmute(vreinterpret_p64_p8(transmute(a))); | |
15551 | assert_eq!(r, e); | |
15552 | } | |
15553 | ||
15554 | #[simd_test(enable = "neon")] | |
15555 | unsafe fn test_vreinterpret_p64_s8() { | |
15556 | let a: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15557 | let e: i64x1 = i64x1::new(0); | |
15558 | let r: i64x1 = transmute(vreinterpret_p64_s8(transmute(a))); | |
15559 | assert_eq!(r, e); | |
15560 | } | |
15561 | ||
15562 | #[simd_test(enable = "neon")] | |
15563 | unsafe fn test_vreinterpret_p64_u8() { | |
15564 | let a: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15565 | let e: i64x1 = i64x1::new(0); | |
15566 | let r: i64x1 = transmute(vreinterpret_p64_u8(transmute(a))); | |
15567 | assert_eq!(r, e); | |
15568 | } | |
15569 | ||
15570 | #[simd_test(enable = "neon")] | |
15571 | unsafe fn test_vreinterpretq_p64_p8() { | |
15572 | let a: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); | |
15573 | let e: i64x2 = i64x2::new(0, 1); | |
15574 | let r: i64x2 = transmute(vreinterpretq_p64_p8(transmute(a))); | |
15575 | assert_eq!(r, e); | |
15576 | } | |
15577 | ||
15578 | #[simd_test(enable = "neon")] | |
15579 | unsafe fn test_vreinterpretq_p64_s8() { | |
15580 | let a: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); | |
15581 | let e: i64x2 = i64x2::new(0, 1); | |
15582 | let r: i64x2 = transmute(vreinterpretq_p64_s8(transmute(a))); | |
15583 | assert_eq!(r, e); | |
15584 | } | |
15585 | ||
15586 | #[simd_test(enable = "neon")] | |
15587 | unsafe fn test_vreinterpretq_p64_u8() { | |
15588 | let a: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); | |
15589 | let e: i64x2 = i64x2::new(0, 1); | |
15590 | let r: i64x2 = transmute(vreinterpretq_p64_u8(transmute(a))); | |
15591 | assert_eq!(r, e); | |
15592 | } | |
15593 | ||
15594 | #[simd_test(enable = "neon")] | |
15595 | unsafe fn test_vreinterpret_s8_f64() { | |
15596 | let a: f64 = 0.; | |
15597 | let e: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15598 | let r: i8x8 = transmute(vreinterpret_s8_f64(transmute(a))); | |
15599 | assert_eq!(r, e); | |
15600 | } | |
15601 | ||
15602 | #[simd_test(enable = "neon")] | |
15603 | unsafe fn test_vreinterpret_s16_f64() { | |
15604 | let a: f64 = 0.; | |
15605 | let e: i16x4 = i16x4::new(0, 0, 0, 0); | |
15606 | let r: i16x4 = transmute(vreinterpret_s16_f64(transmute(a))); | |
15607 | assert_eq!(r, e); | |
15608 | } | |
15609 | ||
15610 | #[simd_test(enable = "neon")] | |
15611 | unsafe fn test_vreinterpret_s32_f64() { | |
15612 | let a: f64 = 0.; | |
15613 | let e: i32x2 = i32x2::new(0, 0); | |
15614 | let r: i32x2 = transmute(vreinterpret_s32_f64(transmute(a))); | |
15615 | assert_eq!(r, e); | |
15616 | } | |
15617 | ||
15618 | #[simd_test(enable = "neon")] | |
15619 | unsafe fn test_vreinterpret_s64_f64() { | |
15620 | let a: f64 = 0.; | |
15621 | let e: i64x1 = i64x1::new(0); | |
15622 | let r: i64x1 = transmute(vreinterpret_s64_f64(transmute(a))); | |
15623 | assert_eq!(r, e); | |
15624 | } | |
15625 | ||
15626 | #[simd_test(enable = "neon")] | |
15627 | unsafe fn test_vreinterpretq_s8_f64() { | |
15628 | let a: f64x2 = f64x2::new(0., 0.); | |
15629 | let e: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
15630 | let r: i8x16 = transmute(vreinterpretq_s8_f64(transmute(a))); | |
15631 | assert_eq!(r, e); | |
15632 | } | |
15633 | ||
15634 | #[simd_test(enable = "neon")] | |
15635 | unsafe fn test_vreinterpretq_s16_f64() { | |
15636 | let a: f64x2 = f64x2::new(0., 0.); | |
15637 | let e: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15638 | let r: i16x8 = transmute(vreinterpretq_s16_f64(transmute(a))); | |
15639 | assert_eq!(r, e); | |
15640 | } | |
15641 | ||
15642 | #[simd_test(enable = "neon")] | |
15643 | unsafe fn test_vreinterpretq_s32_f64() { | |
15644 | let a: f64x2 = f64x2::new(0., 0.); | |
15645 | let e: i32x4 = i32x4::new(0, 0, 0, 0); | |
15646 | let r: i32x4 = transmute(vreinterpretq_s32_f64(transmute(a))); | |
15647 | assert_eq!(r, e); | |
15648 | } | |
15649 | ||
15650 | #[simd_test(enable = "neon")] | |
15651 | unsafe fn test_vreinterpretq_s64_f64() { | |
15652 | let a: f64x2 = f64x2::new(0., 0.); | |
15653 | let e: i64x2 = i64x2::new(0, 0); | |
15654 | let r: i64x2 = transmute(vreinterpretq_s64_f64(transmute(a))); | |
15655 | assert_eq!(r, e); | |
15656 | } | |
15657 | ||
15658 | #[simd_test(enable = "neon")] | |
15659 | unsafe fn test_vreinterpret_u8_f64() { | |
15660 | let a: f64 = 0.; | |
15661 | let e: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15662 | let r: u8x8 = transmute(vreinterpret_u8_f64(transmute(a))); | |
15663 | assert_eq!(r, e); | |
15664 | } | |
15665 | ||
15666 | #[simd_test(enable = "neon")] | |
15667 | unsafe fn test_vreinterpret_u16_f64() { | |
15668 | let a: f64 = 0.; | |
15669 | let e: u16x4 = u16x4::new(0, 0, 0, 0); | |
15670 | let r: u16x4 = transmute(vreinterpret_u16_f64(transmute(a))); | |
15671 | assert_eq!(r, e); | |
15672 | } | |
15673 | ||
15674 | #[simd_test(enable = "neon")] | |
15675 | unsafe fn test_vreinterpret_u32_f64() { | |
15676 | let a: f64 = 0.; | |
15677 | let e: u32x2 = u32x2::new(0, 0); | |
15678 | let r: u32x2 = transmute(vreinterpret_u32_f64(transmute(a))); | |
15679 | assert_eq!(r, e); | |
15680 | } | |
15681 | ||
15682 | #[simd_test(enable = "neon")] | |
15683 | unsafe fn test_vreinterpret_u64_f64() { | |
15684 | let a: f64 = 0.; | |
15685 | let e: u64x1 = u64x1::new(0); | |
15686 | let r: u64x1 = transmute(vreinterpret_u64_f64(transmute(a))); | |
15687 | assert_eq!(r, e); | |
15688 | } | |
15689 | ||
15690 | #[simd_test(enable = "neon")] | |
15691 | unsafe fn test_vreinterpretq_u8_f64() { | |
15692 | let a: f64x2 = f64x2::new(0., 0.); | |
15693 | let e: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
15694 | let r: u8x16 = transmute(vreinterpretq_u8_f64(transmute(a))); | |
15695 | assert_eq!(r, e); | |
15696 | } | |
15697 | ||
15698 | #[simd_test(enable = "neon")] | |
15699 | unsafe fn test_vreinterpretq_u16_f64() { | |
15700 | let a: f64x2 = f64x2::new(0., 0.); | |
15701 | let e: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15702 | let r: u16x8 = transmute(vreinterpretq_u16_f64(transmute(a))); | |
15703 | assert_eq!(r, e); | |
15704 | } | |
15705 | ||
15706 | #[simd_test(enable = "neon")] | |
15707 | unsafe fn test_vreinterpretq_u32_f64() { | |
15708 | let a: f64x2 = f64x2::new(0., 0.); | |
15709 | let e: u32x4 = u32x4::new(0, 0, 0, 0); | |
15710 | let r: u32x4 = transmute(vreinterpretq_u32_f64(transmute(a))); | |
15711 | assert_eq!(r, e); | |
15712 | } | |
15713 | ||
15714 | #[simd_test(enable = "neon")] | |
15715 | unsafe fn test_vreinterpretq_u64_f64() { | |
15716 | let a: f64x2 = f64x2::new(0., 0.); | |
15717 | let e: u64x2 = u64x2::new(0, 0); | |
15718 | let r: u64x2 = transmute(vreinterpretq_u64_f64(transmute(a))); | |
15719 | assert_eq!(r, e); | |
15720 | } | |
15721 | ||
15722 | #[simd_test(enable = "neon")] | |
15723 | unsafe fn test_vreinterpret_p8_f64() { | |
15724 | let a: f64 = 0.; | |
15725 | let e: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15726 | let r: i8x8 = transmute(vreinterpret_p8_f64(transmute(a))); | |
15727 | assert_eq!(r, e); | |
15728 | } | |
15729 | ||
15730 | #[simd_test(enable = "neon")] | |
15731 | unsafe fn test_vreinterpret_p16_f64() { | |
15732 | let a: f64 = 0.; | |
15733 | let e: i16x4 = i16x4::new(0, 0, 0, 0); | |
15734 | let r: i16x4 = transmute(vreinterpret_p16_f64(transmute(a))); | |
15735 | assert_eq!(r, e); | |
15736 | } | |
15737 | ||
15738 | #[simd_test(enable = "neon")] | |
15739 | unsafe fn test_vreinterpret_p64_f32() { | |
15740 | let a: f32x2 = f32x2::new(0., 0.); | |
15741 | let e: i64x1 = i64x1::new(0); | |
15742 | let r: i64x1 = transmute(vreinterpret_p64_f32(transmute(a))); | |
15743 | assert_eq!(r, e); | |
15744 | } | |
15745 | ||
15746 | #[simd_test(enable = "neon")] | |
15747 | unsafe fn test_vreinterpret_p64_f64() { | |
15748 | let a: f64 = 0.; | |
15749 | let e: i64x1 = i64x1::new(0); | |
15750 | let r: i64x1 = transmute(vreinterpret_p64_f64(transmute(a))); | |
15751 | assert_eq!(r, e); | |
15752 | } | |
15753 | ||
15754 | #[simd_test(enable = "neon")] | |
15755 | unsafe fn test_vreinterpretq_p8_f64() { | |
15756 | let a: f64x2 = f64x2::new(0., 0.); | |
15757 | let e: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
15758 | let r: i8x16 = transmute(vreinterpretq_p8_f64(transmute(a))); | |
15759 | assert_eq!(r, e); | |
15760 | } | |
15761 | ||
15762 | #[simd_test(enable = "neon")] | |
15763 | unsafe fn test_vreinterpretq_p16_f64() { | |
15764 | let a: f64x2 = f64x2::new(0., 0.); | |
15765 | let e: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15766 | let r: i16x8 = transmute(vreinterpretq_p16_f64(transmute(a))); | |
15767 | assert_eq!(r, e); | |
15768 | } | |
15769 | ||
15770 | #[simd_test(enable = "neon")] | |
15771 | unsafe fn test_vreinterpretq_p64_f32() { | |
15772 | let a: f32x4 = f32x4::new(0., 0., 0., 0.); | |
15773 | let e: i64x2 = i64x2::new(0, 0); | |
15774 | let r: i64x2 = transmute(vreinterpretq_p64_f32(transmute(a))); | |
15775 | assert_eq!(r, e); | |
15776 | } | |
15777 | ||
15778 | #[simd_test(enable = "neon")] | |
15779 | unsafe fn test_vreinterpretq_p64_f64() { | |
15780 | let a: f64x2 = f64x2::new(0., 0.); | |
15781 | let e: i64x2 = i64x2::new(0, 0); | |
15782 | let r: i64x2 = transmute(vreinterpretq_p64_f64(transmute(a))); | |
15783 | assert_eq!(r, e); | |
15784 | } | |
15785 | ||
15786 | #[simd_test(enable = "neon")] | |
15787 | unsafe fn test_vreinterpret_f64_s8() { | |
15788 | let a: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15789 | let e: f64 = 0.; | |
15790 | let r: f64 = transmute(vreinterpret_f64_s8(transmute(a))); | |
15791 | assert_eq!(r, e); | |
15792 | } | |
15793 | ||
15794 | #[simd_test(enable = "neon")] | |
15795 | unsafe fn test_vreinterpret_f64_s16() { | |
15796 | let a: i16x4 = i16x4::new(0, 0, 0, 0); | |
15797 | let e: f64 = 0.; | |
15798 | let r: f64 = transmute(vreinterpret_f64_s16(transmute(a))); | |
15799 | assert_eq!(r, e); | |
15800 | } | |
15801 | ||
15802 | #[simd_test(enable = "neon")] | |
15803 | unsafe fn test_vreinterpret_f64_s32() { | |
15804 | let a: i32x2 = i32x2::new(0, 0); | |
15805 | let e: f64 = 0.; | |
15806 | let r: f64 = transmute(vreinterpret_f64_s32(transmute(a))); | |
15807 | assert_eq!(r, e); | |
15808 | } | |
15809 | ||
15810 | #[simd_test(enable = "neon")] | |
15811 | unsafe fn test_vreinterpret_f64_s64() { | |
15812 | let a: i64x1 = i64x1::new(0); | |
15813 | let e: f64 = 0.; | |
15814 | let r: f64 = transmute(vreinterpret_f64_s64(transmute(a))); | |
15815 | assert_eq!(r, e); | |
15816 | } | |
15817 | ||
15818 | #[simd_test(enable = "neon")] | |
15819 | unsafe fn test_vreinterpretq_f64_s8() { | |
15820 | let a: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
15821 | let e: f64x2 = f64x2::new(0., 0.); | |
15822 | let r: f64x2 = transmute(vreinterpretq_f64_s8(transmute(a))); | |
15823 | assert_eq!(r, e); | |
15824 | } | |
15825 | ||
15826 | #[simd_test(enable = "neon")] | |
15827 | unsafe fn test_vreinterpretq_f64_s16() { | |
15828 | let a: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15829 | let e: f64x2 = f64x2::new(0., 0.); | |
15830 | let r: f64x2 = transmute(vreinterpretq_f64_s16(transmute(a))); | |
15831 | assert_eq!(r, e); | |
15832 | } | |
15833 | ||
15834 | #[simd_test(enable = "neon")] | |
15835 | unsafe fn test_vreinterpretq_f64_s32() { | |
15836 | let a: i32x4 = i32x4::new(0, 0, 0, 0); | |
15837 | let e: f64x2 = f64x2::new(0., 0.); | |
15838 | let r: f64x2 = transmute(vreinterpretq_f64_s32(transmute(a))); | |
15839 | assert_eq!(r, e); | |
15840 | } | |
15841 | ||
15842 | #[simd_test(enable = "neon")] | |
15843 | unsafe fn test_vreinterpretq_f64_s64() { | |
15844 | let a: i64x2 = i64x2::new(0, 0); | |
15845 | let e: f64x2 = f64x2::new(0., 0.); | |
15846 | let r: f64x2 = transmute(vreinterpretq_f64_s64(transmute(a))); | |
15847 | assert_eq!(r, e); | |
15848 | } | |
15849 | ||
15850 | #[simd_test(enable = "neon")] | |
15851 | unsafe fn test_vreinterpret_f64_p8() { | |
15852 | let a: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15853 | let e: f64 = 0.; | |
15854 | let r: f64 = transmute(vreinterpret_f64_p8(transmute(a))); | |
15855 | assert_eq!(r, e); | |
15856 | } | |
15857 | ||
15858 | #[simd_test(enable = "neon")] | |
15859 | unsafe fn test_vreinterpret_f64_u16() { | |
15860 | let a: u16x4 = u16x4::new(0, 0, 0, 0); | |
15861 | let e: f64 = 0.; | |
15862 | let r: f64 = transmute(vreinterpret_f64_u16(transmute(a))); | |
15863 | assert_eq!(r, e); | |
15864 | } | |
15865 | ||
15866 | #[simd_test(enable = "neon")] | |
15867 | unsafe fn test_vreinterpret_f64_u32() { | |
15868 | let a: u32x2 = u32x2::new(0, 0); | |
15869 | let e: f64 = 0.; | |
15870 | let r: f64 = transmute(vreinterpret_f64_u32(transmute(a))); | |
15871 | assert_eq!(r, e); | |
15872 | } | |
15873 | ||
15874 | #[simd_test(enable = "neon")] | |
15875 | unsafe fn test_vreinterpret_f64_u64() { | |
15876 | let a: u64x1 = u64x1::new(0); | |
15877 | let e: f64 = 0.; | |
15878 | let r: f64 = transmute(vreinterpret_f64_u64(transmute(a))); | |
15879 | assert_eq!(r, e); | |
15880 | } | |
15881 | ||
15882 | #[simd_test(enable = "neon")] | |
15883 | unsafe fn test_vreinterpretq_f64_p8() { | |
15884 | let a: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
15885 | let e: f64x2 = f64x2::new(0., 0.); | |
15886 | let r: f64x2 = transmute(vreinterpretq_f64_p8(transmute(a))); | |
15887 | assert_eq!(r, e); | |
15888 | } | |
15889 | ||
15890 | #[simd_test(enable = "neon")] | |
15891 | unsafe fn test_vreinterpretq_f64_u16() { | |
15892 | let a: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15893 | let e: f64x2 = f64x2::new(0., 0.); | |
15894 | let r: f64x2 = transmute(vreinterpretq_f64_u16(transmute(a))); | |
15895 | assert_eq!(r, e); | |
15896 | } | |
15897 | ||
15898 | #[simd_test(enable = "neon")] | |
15899 | unsafe fn test_vreinterpretq_f64_u32() { | |
15900 | let a: u32x4 = u32x4::new(0, 0, 0, 0); | |
15901 | let e: f64x2 = f64x2::new(0., 0.); | |
15902 | let r: f64x2 = transmute(vreinterpretq_f64_u32(transmute(a))); | |
15903 | assert_eq!(r, e); | |
15904 | } | |
15905 | ||
15906 | #[simd_test(enable = "neon")] | |
15907 | unsafe fn test_vreinterpretq_f64_u64() { | |
15908 | let a: u64x2 = u64x2::new(0, 0); | |
15909 | let e: f64x2 = f64x2::new(0., 0.); | |
15910 | let r: f64x2 = transmute(vreinterpretq_f64_u64(transmute(a))); | |
15911 | assert_eq!(r, e); | |
15912 | } | |
15913 | ||
15914 | #[simd_test(enable = "neon")] | |
15915 | unsafe fn test_vreinterpret_f64_u8() { | |
15916 | let a: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15917 | let e: f64 = 0.; | |
15918 | let r: f64 = transmute(vreinterpret_f64_u8(transmute(a))); | |
15919 | assert_eq!(r, e); | |
15920 | } | |
15921 | ||
15922 | #[simd_test(enable = "neon")] | |
15923 | unsafe fn test_vreinterpret_f64_p16() { | |
15924 | let a: i16x4 = i16x4::new(0, 0, 0, 0); | |
15925 | let e: f64 = 0.; | |
15926 | let r: f64 = transmute(vreinterpret_f64_p16(transmute(a))); | |
15927 | assert_eq!(r, e); | |
15928 | } | |
15929 | ||
15930 | #[simd_test(enable = "neon")] | |
15931 | unsafe fn test_vreinterpret_f64_p64() { | |
15932 | let a: i64x1 = i64x1::new(0); | |
15933 | let e: f64 = 0.; | |
15934 | let r: f64 = transmute(vreinterpret_f64_p64(transmute(a))); | |
15935 | assert_eq!(r, e); | |
15936 | } | |
15937 | ||
15938 | #[simd_test(enable = "neon")] | |
15939 | unsafe fn test_vreinterpret_f32_p64() { | |
15940 | let a: i64x1 = i64x1::new(0); | |
15941 | let e: f32x2 = f32x2::new(0., 0.); | |
15942 | let r: f32x2 = transmute(vreinterpret_f32_p64(transmute(a))); | |
15943 | assert_eq!(r, e); | |
15944 | } | |
15945 | ||
15946 | #[simd_test(enable = "neon")] | |
15947 | unsafe fn test_vreinterpretq_f64_u8() { | |
15948 | let a: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
15949 | let e: f64x2 = f64x2::new(0., 0.); | |
15950 | let r: f64x2 = transmute(vreinterpretq_f64_u8(transmute(a))); | |
15951 | assert_eq!(r, e); | |
15952 | } | |
15953 | ||
15954 | #[simd_test(enable = "neon")] | |
15955 | unsafe fn test_vreinterpretq_f64_p16() { | |
15956 | let a: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15957 | let e: f64x2 = f64x2::new(0., 0.); | |
15958 | let r: f64x2 = transmute(vreinterpretq_f64_p16(transmute(a))); | |
15959 | assert_eq!(r, e); | |
15960 | } | |
15961 | ||
15962 | #[simd_test(enable = "neon")] | |
15963 | unsafe fn test_vreinterpretq_f64_p64() { | |
15964 | let a: i64x2 = i64x2::new(0, 0); | |
15965 | let e: f64x2 = f64x2::new(0., 0.); | |
15966 | let r: f64x2 = transmute(vreinterpretq_f64_p64(transmute(a))); | |
15967 | assert_eq!(r, e); | |
15968 | } | |
15969 | ||
15970 | #[simd_test(enable = "neon")] | |
15971 | unsafe fn test_vreinterpretq_f32_p64() { | |
15972 | let a: i64x2 = i64x2::new(0, 0); | |
15973 | let e: f32x4 = f32x4::new(0., 0., 0., 0.); | |
15974 | let r: f32x4 = transmute(vreinterpretq_f32_p64(transmute(a))); | |
15975 | assert_eq!(r, e); | |
15976 | } | |
15977 | ||
15978 | #[simd_test(enable = "neon")] | |
15979 | unsafe fn test_vreinterpret_f64_f32() { | |
15980 | let a: f32x2 = f32x2::new(0., 0.); | |
15981 | let e: f64 = 0.; | |
15982 | let r: f64 = transmute(vreinterpret_f64_f32(transmute(a))); | |
15983 | assert_eq!(r, e); | |
15984 | } | |
15985 | ||
15986 | #[simd_test(enable = "neon")] | |
15987 | unsafe fn test_vreinterpret_f32_f64() { | |
15988 | let a: f64 = 0.; | |
15989 | let e: f32x2 = f32x2::new(0., 0.); | |
15990 | let r: f32x2 = transmute(vreinterpret_f32_f64(transmute(a))); | |
15991 | assert_eq!(r, e); | |
15992 | } | |
15993 | ||
15994 | #[simd_test(enable = "neon")] | |
15995 | unsafe fn test_vreinterpretq_f64_f32() { | |
15996 | let a: f32x4 = f32x4::new(0., 0., 0., 0.); | |
15997 | let e: f64x2 = f64x2::new(0., 0.); | |
15998 | let r: f64x2 = transmute(vreinterpretq_f64_f32(transmute(a))); | |
15999 | assert_eq!(r, e); | |
16000 | } | |
16001 | ||
16002 | #[simd_test(enable = "neon")] | |
16003 | unsafe fn test_vreinterpretq_f32_f64() { | |
16004 | let a: f64x2 = f64x2::new(0., 0.); | |
16005 | let e: f32x4 = f32x4::new(0., 0., 0., 0.); | |
16006 | let r: f32x4 = transmute(vreinterpretq_f32_f64(transmute(a))); | |
16007 | assert_eq!(r, e); | |
16008 | } | |
16009 | ||
16010 | #[simd_test(enable = "neon")] | |
16011 | unsafe fn test_vrshld_s64() { | |
16012 | let a: i64 = 1; | |
16013 | let b: i64 = 2; | |
16014 | let e: i64 = 4; | |
16015 | let r: i64 = transmute(vrshld_s64(transmute(a), transmute(b))); | |
16016 | assert_eq!(r, e); | |
16017 | } | |
16018 | ||
16019 | #[simd_test(enable = "neon")] | |
16020 | unsafe fn test_vrshld_u64() { | |
16021 | let a: u64 = 1; | |
16022 | let b: i64 = 2; | |
16023 | let e: u64 = 4; | |
16024 | let r: u64 = transmute(vrshld_u64(transmute(a), transmute(b))); | |
16025 | assert_eq!(r, e); | |
16026 | } | |
16027 | ||
16028 | #[simd_test(enable = "neon")] | |
16029 | unsafe fn test_vrshrd_n_s64() { | |
16030 | let a: i64 = 4; | |
16031 | let e: i64 = 1; | |
16032 | let r: i64 = transmute(vrshrd_n_s64::<2>(transmute(a))); | |
16033 | assert_eq!(r, e); | |
16034 | } | |
16035 | ||
16036 | #[simd_test(enable = "neon")] | |
16037 | unsafe fn test_vrshrd_n_u64() { | |
16038 | let a: u64 = 4; | |
16039 | let e: u64 = 1; | |
16040 | let r: u64 = transmute(vrshrd_n_u64::<2>(transmute(a))); | |
16041 | assert_eq!(r, e); | |
16042 | } | |
16043 | ||
16044 | #[simd_test(enable = "neon")] | |
16045 | unsafe fn test_vrshrn_high_n_s16() { | |
16046 | let a: i8x8 = i8x8::new(0, 1, 8, 9, 8, 9, 10, 11); | |
16047 | let b: i16x8 = i16x8::new(32, 36, 40, 44, 48, 52, 56, 60); | |
16048 | let e: i8x16 = i8x16::new(0, 1, 8, 9, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15); | |
16049 | let r: i8x16 = transmute(vrshrn_high_n_s16::<2>(transmute(a), transmute(b))); | |
16050 | assert_eq!(r, e); | |
16051 | } | |
16052 | ||
16053 | #[simd_test(enable = "neon")] | |
16054 | unsafe fn test_vrshrn_high_n_s32() { | |
16055 | let a: i16x4 = i16x4::new(0, 1, 8, 9); | |
16056 | let b: i32x4 = i32x4::new(32, 36, 40, 44); | |
16057 | let e: i16x8 = i16x8::new(0, 1, 8, 9, 8, 9, 10, 11); | |
16058 | let r: i16x8 = transmute(vrshrn_high_n_s32::<2>(transmute(a), transmute(b))); | |
16059 | assert_eq!(r, e); | |
16060 | } | |
16061 | ||
16062 | #[simd_test(enable = "neon")] | |
16063 | unsafe fn test_vrshrn_high_n_s64() { | |
16064 | let a: i32x2 = i32x2::new(0, 1); | |
16065 | let b: i64x2 = i64x2::new(32, 36); | |
16066 | let e: i32x4 = i32x4::new(0, 1, 8, 9); | |
16067 | let r: i32x4 = transmute(vrshrn_high_n_s64::<2>(transmute(a), transmute(b))); | |
16068 | assert_eq!(r, e); | |
16069 | } | |
16070 | ||
16071 | #[simd_test(enable = "neon")] | |
16072 | unsafe fn test_vrshrn_high_n_u16() { | |
16073 | let a: u8x8 = u8x8::new(0, 1, 8, 9, 8, 9, 10, 11); | |
16074 | let b: u16x8 = u16x8::new(32, 36, 40, 44, 48, 52, 56, 60); | |
16075 | let e: u8x16 = u8x16::new(0, 1, 8, 9, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15); | |
16076 | let r: u8x16 = transmute(vrshrn_high_n_u16::<2>(transmute(a), transmute(b))); | |
16077 | assert_eq!(r, e); | |
16078 | } | |
16079 | ||
16080 | #[simd_test(enable = "neon")] | |
16081 | unsafe fn test_vrshrn_high_n_u32() { | |
16082 | let a: u16x4 = u16x4::new(0, 1, 8, 9); | |
16083 | let b: u32x4 = u32x4::new(32, 36, 40, 44); | |
16084 | let e: u16x8 = u16x8::new(0, 1, 8, 9, 8, 9, 10, 11); | |
16085 | let r: u16x8 = transmute(vrshrn_high_n_u32::<2>(transmute(a), transmute(b))); | |
16086 | assert_eq!(r, e); | |
16087 | } | |
16088 | ||
16089 | #[simd_test(enable = "neon")] | |
16090 | unsafe fn test_vrshrn_high_n_u64() { | |
16091 | let a: u32x2 = u32x2::new(0, 1); | |
16092 | let b: u64x2 = u64x2::new(32, 36); | |
16093 | let e: u32x4 = u32x4::new(0, 1, 8, 9); | |
16094 | let r: u32x4 = transmute(vrshrn_high_n_u64::<2>(transmute(a), transmute(b))); | |
16095 | assert_eq!(r, e); | |
16096 | } | |
16097 | ||
16098 | #[simd_test(enable = "neon")] | |
16099 | unsafe fn test_vrsrad_n_s64() { | |
16100 | let a: i64 = 1; | |
16101 | let b: i64 = 4; | |
16102 | let e: i64 = 2; | |
16103 | let r: i64 = transmute(vrsrad_n_s64::<2>(transmute(a), transmute(b))); | |
16104 | assert_eq!(r, e); | |
16105 | } | |
16106 | ||
16107 | #[simd_test(enable = "neon")] | |
16108 | unsafe fn test_vrsrad_n_u64() { | |
16109 | let a: u64 = 1; | |
16110 | let b: u64 = 4; | |
16111 | let e: u64 = 2; | |
16112 | let r: u64 = transmute(vrsrad_n_u64::<2>(transmute(a), transmute(b))); | |
16113 | assert_eq!(r, e); | |
16114 | } | |
16115 | ||
16116 | #[simd_test(enable = "neon")] | |
16117 | unsafe fn test_vset_lane_f64() { | |
16118 | let a: f64 = 1.; | |
16119 | let b: f64 = 0.; | |
16120 | let e: f64 = 1.; | |
16121 | let r: f64 = transmute(vset_lane_f64::<0>(transmute(a), transmute(b))); | |
16122 | assert_eq!(r, e); | |
16123 | } | |
16124 | ||
16125 | #[simd_test(enable = "neon")] | |
16126 | unsafe fn test_vsetq_lane_f64() { | |
16127 | let a: f64 = 1.; | |
16128 | let b: f64x2 = f64x2::new(0., 2.); | |
16129 | let e: f64x2 = f64x2::new(1., 2.); | |
16130 | let r: f64x2 = transmute(vsetq_lane_f64::<0>(transmute(a), transmute(b))); | |
16131 | assert_eq!(r, e); | |
16132 | } | |
16133 | ||
16134 | #[simd_test(enable = "neon")] | |
16135 | unsafe fn test_vshld_s64() { | |
16136 | let a: i64 = 1; | |
16137 | let b: i64 = 2; | |
16138 | let e: i64 = 4; | |
16139 | let r: i64 = transmute(vshld_s64(transmute(a), transmute(b))); | |
16140 | assert_eq!(r, e); | |
16141 | } | |
16142 | ||
16143 | #[simd_test(enable = "neon")] | |
16144 | unsafe fn test_vshld_u64() { | |
16145 | let a: u64 = 1; | |
16146 | let b: i64 = 2; | |
16147 | let e: u64 = 4; | |
16148 | let r: u64 = transmute(vshld_u64(transmute(a), transmute(b))); | |
16149 | assert_eq!(r, e); | |
16150 | } | |
16151 | ||
16152 | #[simd_test(enable = "neon")] | |
16153 | unsafe fn test_vshll_high_n_s8() { | |
16154 | let a: i8x16 = i8x16::new(0, 0, 1, 2, 1, 2, 3, 4, 1, 2, 3, 4, 5, 6, 7, 8); | |
16155 | let e: i16x8 = i16x8::new(4, 8, 12, 16, 20, 24, 28, 32); | |
16156 | let r: i16x8 = transmute(vshll_high_n_s8::<2>(transmute(a))); | |
16157 | assert_eq!(r, e); | |
16158 | } | |
16159 | ||
16160 | #[simd_test(enable = "neon")] | |
16161 | unsafe fn test_vshll_high_n_s16() { | |
16162 | let a: i16x8 = i16x8::new(0, 0, 1, 2, 1, 2, 3, 4); | |
16163 | let e: i32x4 = i32x4::new(4, 8, 12, 16); | |
16164 | let r: i32x4 = transmute(vshll_high_n_s16::<2>(transmute(a))); | |
16165 | assert_eq!(r, e); | |
16166 | } | |
16167 | ||
16168 | #[simd_test(enable = "neon")] | |
16169 | unsafe fn test_vshll_high_n_s32() { | |
16170 | let a: i32x4 = i32x4::new(0, 0, 1, 2); | |
16171 | let e: i64x2 = i64x2::new(4, 8); | |
16172 | let r: i64x2 = transmute(vshll_high_n_s32::<2>(transmute(a))); | |
16173 | assert_eq!(r, e); | |
16174 | } | |
16175 | ||
16176 | #[simd_test(enable = "neon")] | |
16177 | unsafe fn test_vshll_high_n_u8() { | |
16178 | let a: u8x16 = u8x16::new(0, 0, 1, 2, 1, 2, 3, 4, 1, 2, 3, 4, 5, 6, 7, 8); | |
16179 | let e: u16x8 = u16x8::new(4, 8, 12, 16, 20, 24, 28, 32); | |
16180 | let r: u16x8 = transmute(vshll_high_n_u8::<2>(transmute(a))); | |
16181 | assert_eq!(r, e); | |
16182 | } | |
16183 | ||
16184 | #[simd_test(enable = "neon")] | |
16185 | unsafe fn test_vshll_high_n_u16() { | |
16186 | let a: u16x8 = u16x8::new(0, 0, 1, 2, 1, 2, 3, 4); | |
16187 | let e: u32x4 = u32x4::new(4, 8, 12, 16); | |
16188 | let r: u32x4 = transmute(vshll_high_n_u16::<2>(transmute(a))); | |
16189 | assert_eq!(r, e); | |
16190 | } | |
16191 | ||
16192 | #[simd_test(enable = "neon")] | |
16193 | unsafe fn test_vshll_high_n_u32() { | |
16194 | let a: u32x4 = u32x4::new(0, 0, 1, 2); | |
16195 | let e: u64x2 = u64x2::new(4, 8); | |
16196 | let r: u64x2 = transmute(vshll_high_n_u32::<2>(transmute(a))); | |
16197 | assert_eq!(r, e); | |
16198 | } | |
16199 | ||
16200 | #[simd_test(enable = "neon")] | |
16201 | unsafe fn test_vshrn_high_n_s16() { | |
16202 | let a: i8x8 = i8x8::new(1, 2, 5, 6, 5, 6, 7, 8); | |
16203 | let b: i16x8 = i16x8::new(20, 24, 28, 32, 52, 56, 60, 64); | |
16204 | let e: i8x16 = i8x16::new(1, 2, 5, 6, 5, 6, 7, 8, 5, 6, 7, 8, 13, 14, 15, 16); | |
16205 | let r: i8x16 = transmute(vshrn_high_n_s16::<2>(transmute(a), transmute(b))); | |
16206 | assert_eq!(r, e); | |
16207 | } | |
16208 | ||
16209 | #[simd_test(enable = "neon")] | |
16210 | unsafe fn test_vshrn_high_n_s32() { | |
16211 | let a: i16x4 = i16x4::new(1, 2, 5, 6); | |
16212 | let b: i32x4 = i32x4::new(20, 24, 28, 32); | |
16213 | let e: i16x8 = i16x8::new(1, 2, 5, 6, 5, 6, 7, 8); | |
16214 | let r: i16x8 = transmute(vshrn_high_n_s32::<2>(transmute(a), transmute(b))); | |
16215 | assert_eq!(r, e); | |
16216 | } | |
16217 | ||
16218 | #[simd_test(enable = "neon")] | |
16219 | unsafe fn test_vshrn_high_n_s64() { | |
16220 | let a: i32x2 = i32x2::new(1, 2); | |
16221 | let b: i64x2 = i64x2::new(20, 24); | |
16222 | let e: i32x4 = i32x4::new(1, 2, 5, 6); | |
16223 | let r: i32x4 = transmute(vshrn_high_n_s64::<2>(transmute(a), transmute(b))); | |
16224 | assert_eq!(r, e); | |
16225 | } | |
16226 | ||
16227 | #[simd_test(enable = "neon")] | |
16228 | unsafe fn test_vshrn_high_n_u16() { | |
16229 | let a: u8x8 = u8x8::new(1, 2, 5, 6, 5, 6, 7, 8); | |
16230 | let b: u16x8 = u16x8::new(20, 24, 28, 32, 52, 56, 60, 64); | |
16231 | let e: u8x16 = u8x16::new(1, 2, 5, 6, 5, 6, 7, 8, 5, 6, 7, 8, 13, 14, 15, 16); | |
16232 | let r: u8x16 = transmute(vshrn_high_n_u16::<2>(transmute(a), transmute(b))); | |
16233 | assert_eq!(r, e); | |
16234 | } | |
16235 | ||
16236 | #[simd_test(enable = "neon")] | |
16237 | unsafe fn test_vshrn_high_n_u32() { | |
16238 | let a: u16x4 = u16x4::new(1, 2, 5, 6); | |
16239 | let b: u32x4 = u32x4::new(20, 24, 28, 32); | |
16240 | let e: u16x8 = u16x8::new(1, 2, 5, 6, 5, 6, 7, 8); | |
16241 | let r: u16x8 = transmute(vshrn_high_n_u32::<2>(transmute(a), transmute(b))); | |
16242 | assert_eq!(r, e); | |
16243 | } | |
16244 | ||
16245 | #[simd_test(enable = "neon")] | |
16246 | unsafe fn test_vshrn_high_n_u64() { | |
16247 | let a: u32x2 = u32x2::new(1, 2); | |
16248 | let b: u64x2 = u64x2::new(20, 24); | |
16249 | let e: u32x4 = u32x4::new(1, 2, 5, 6); | |
16250 | let r: u32x4 = transmute(vshrn_high_n_u64::<2>(transmute(a), transmute(b))); | |
16251 | assert_eq!(r, e); | |
16252 | } | |
16253 | ||
16254 | #[simd_test(enable = "neon")] | |
16255 | unsafe fn test_vtrn1_s8() { | |
16256 | let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16257 | let b: i8x8 = i8x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16258 | let e: i8x8 = i8x8::new(0, 1, 4, 5, 8, 9, 12, 13); | |
16259 | let r: i8x8 = transmute(vtrn1_s8(transmute(a), transmute(b))); | |
16260 | assert_eq!(r, e); | |
16261 | } | |
16262 | ||
16263 | #[simd_test(enable = "neon")] | |
16264 | unsafe fn test_vtrn1q_s8() { | |
16265 | let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
16266 | let b: i8x16 = i8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); | |
16267 | let e: i8x16 = i8x16::new(0, 1, 4, 5, 8, 9, 12, 13, 16, 17, 20, 21, 24, 25, 28, 29); | |
16268 | let r: i8x16 = transmute(vtrn1q_s8(transmute(a), transmute(b))); | |
16269 | assert_eq!(r, e); | |
16270 | } | |
16271 | ||
16272 | #[simd_test(enable = "neon")] | |
16273 | unsafe fn test_vtrn1_s16() { | |
16274 | let a: i16x4 = i16x4::new(0, 2, 4, 6); | |
16275 | let b: i16x4 = i16x4::new(1, 3, 5, 7); | |
16276 | let e: i16x4 = i16x4::new(0, 1, 4, 5); | |
16277 | let r: i16x4 = transmute(vtrn1_s16(transmute(a), transmute(b))); | |
16278 | assert_eq!(r, e); | |
16279 | } | |
16280 | ||
16281 | #[simd_test(enable = "neon")] | |
16282 | unsafe fn test_vtrn1q_s16() { | |
16283 | let a: i16x8 = i16x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16284 | let b: i16x8 = i16x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16285 | let e: i16x8 = i16x8::new(0, 1, 4, 5, 8, 9, 12, 13); | |
16286 | let r: i16x8 = transmute(vtrn1q_s16(transmute(a), transmute(b))); | |
16287 | assert_eq!(r, e); | |
16288 | } | |
16289 | ||
16290 | #[simd_test(enable = "neon")] | |
16291 | unsafe fn test_vtrn1q_s32() { | |
16292 | let a: i32x4 = i32x4::new(0, 2, 4, 6); | |
16293 | let b: i32x4 = i32x4::new(1, 3, 5, 7); | |
16294 | let e: i32x4 = i32x4::new(0, 1, 4, 5); | |
16295 | let r: i32x4 = transmute(vtrn1q_s32(transmute(a), transmute(b))); | |
16296 | assert_eq!(r, e); | |
16297 | } | |
16298 | ||
16299 | #[simd_test(enable = "neon")] | |
16300 | unsafe fn test_vtrn1_u8() { | |
16301 | let a: u8x8 = u8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16302 | let b: u8x8 = u8x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16303 | let e: u8x8 = u8x8::new(0, 1, 4, 5, 8, 9, 12, 13); | |
16304 | let r: u8x8 = transmute(vtrn1_u8(transmute(a), transmute(b))); | |
16305 | assert_eq!(r, e); | |
16306 | } | |
16307 | ||
16308 | #[simd_test(enable = "neon")] | |
16309 | unsafe fn test_vtrn1q_u8() { | |
16310 | let a: u8x16 = u8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
16311 | let b: u8x16 = u8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); | |
16312 | let e: u8x16 = u8x16::new(0, 1, 4, 5, 8, 9, 12, 13, 16, 17, 20, 21, 24, 25, 28, 29); | |
16313 | let r: u8x16 = transmute(vtrn1q_u8(transmute(a), transmute(b))); | |
16314 | assert_eq!(r, e); | |
16315 | } | |
16316 | ||
16317 | #[simd_test(enable = "neon")] | |
16318 | unsafe fn test_vtrn1_u16() { | |
16319 | let a: u16x4 = u16x4::new(0, 2, 4, 6); | |
16320 | let b: u16x4 = u16x4::new(1, 3, 5, 7); | |
16321 | let e: u16x4 = u16x4::new(0, 1, 4, 5); | |
16322 | let r: u16x4 = transmute(vtrn1_u16(transmute(a), transmute(b))); | |
16323 | assert_eq!(r, e); | |
16324 | } | |
16325 | ||
16326 | #[simd_test(enable = "neon")] | |
16327 | unsafe fn test_vtrn1q_u16() { | |
16328 | let a: u16x8 = u16x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16329 | let b: u16x8 = u16x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16330 | let e: u16x8 = u16x8::new(0, 1, 4, 5, 8, 9, 12, 13); | |
16331 | let r: u16x8 = transmute(vtrn1q_u16(transmute(a), transmute(b))); | |
16332 | assert_eq!(r, e); | |
16333 | } | |
16334 | ||
16335 | #[simd_test(enable = "neon")] | |
16336 | unsafe fn test_vtrn1q_u32() { | |
16337 | let a: u32x4 = u32x4::new(0, 2, 4, 6); | |
16338 | let b: u32x4 = u32x4::new(1, 3, 5, 7); | |
16339 | let e: u32x4 = u32x4::new(0, 1, 4, 5); | |
16340 | let r: u32x4 = transmute(vtrn1q_u32(transmute(a), transmute(b))); | |
16341 | assert_eq!(r, e); | |
16342 | } | |
16343 | ||
16344 | #[simd_test(enable = "neon")] | |
16345 | unsafe fn test_vtrn1_p8() { | |
16346 | let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16347 | let b: i8x8 = i8x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16348 | let e: i8x8 = i8x8::new(0, 1, 4, 5, 8, 9, 12, 13); | |
16349 | let r: i8x8 = transmute(vtrn1_p8(transmute(a), transmute(b))); | |
16350 | assert_eq!(r, e); | |
16351 | } | |
16352 | ||
16353 | #[simd_test(enable = "neon")] | |
16354 | unsafe fn test_vtrn1q_p8() { | |
16355 | let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
16356 | let b: i8x16 = i8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); | |
16357 | let e: i8x16 = i8x16::new(0, 1, 4, 5, 8, 9, 12, 13, 16, 17, 20, 21, 24, 25, 28, 29); | |
16358 | let r: i8x16 = transmute(vtrn1q_p8(transmute(a), transmute(b))); | |
16359 | assert_eq!(r, e); | |
16360 | } | |
16361 | ||
16362 | #[simd_test(enable = "neon")] | |
16363 | unsafe fn test_vtrn1_p16() { | |
16364 | let a: i16x4 = i16x4::new(0, 2, 4, 6); | |
16365 | let b: i16x4 = i16x4::new(1, 3, 5, 7); | |
16366 | let e: i16x4 = i16x4::new(0, 1, 4, 5); | |
16367 | let r: i16x4 = transmute(vtrn1_p16(transmute(a), transmute(b))); | |
16368 | assert_eq!(r, e); | |
16369 | } | |
16370 | ||
16371 | #[simd_test(enable = "neon")] | |
16372 | unsafe fn test_vtrn1q_p16() { | |
16373 | let a: i16x8 = i16x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16374 | let b: i16x8 = i16x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16375 | let e: i16x8 = i16x8::new(0, 1, 4, 5, 8, 9, 12, 13); | |
16376 | let r: i16x8 = transmute(vtrn1q_p16(transmute(a), transmute(b))); | |
16377 | assert_eq!(r, e); | |
16378 | } | |
16379 | ||
16380 | #[simd_test(enable = "neon")] | |
16381 | unsafe fn test_vtrn1_s32() { | |
16382 | let a: i32x2 = i32x2::new(0, 2); | |
16383 | let b: i32x2 = i32x2::new(1, 3); | |
16384 | let e: i32x2 = i32x2::new(0, 1); | |
16385 | let r: i32x2 = transmute(vtrn1_s32(transmute(a), transmute(b))); | |
16386 | assert_eq!(r, e); | |
16387 | } | |
16388 | ||
16389 | #[simd_test(enable = "neon")] | |
16390 | unsafe fn test_vtrn1q_s64() { | |
16391 | let a: i64x2 = i64x2::new(0, 2); | |
16392 | let b: i64x2 = i64x2::new(1, 3); | |
16393 | let e: i64x2 = i64x2::new(0, 1); | |
16394 | let r: i64x2 = transmute(vtrn1q_s64(transmute(a), transmute(b))); | |
16395 | assert_eq!(r, e); | |
16396 | } | |
16397 | ||
16398 | #[simd_test(enable = "neon")] | |
16399 | unsafe fn test_vtrn1_u32() { | |
16400 | let a: u32x2 = u32x2::new(0, 2); | |
16401 | let b: u32x2 = u32x2::new(1, 3); | |
16402 | let e: u32x2 = u32x2::new(0, 1); | |
16403 | let r: u32x2 = transmute(vtrn1_u32(transmute(a), transmute(b))); | |
16404 | assert_eq!(r, e); | |
16405 | } | |
16406 | ||
16407 | #[simd_test(enable = "neon")] | |
16408 | unsafe fn test_vtrn1q_u64() { | |
16409 | let a: u64x2 = u64x2::new(0, 2); | |
16410 | let b: u64x2 = u64x2::new(1, 3); | |
16411 | let e: u64x2 = u64x2::new(0, 1); | |
16412 | let r: u64x2 = transmute(vtrn1q_u64(transmute(a), transmute(b))); | |
16413 | assert_eq!(r, e); | |
16414 | } | |
16415 | ||
16416 | #[simd_test(enable = "neon")] | |
16417 | unsafe fn test_vtrn1q_p64() { | |
16418 | let a: i64x2 = i64x2::new(0, 2); | |
16419 | let b: i64x2 = i64x2::new(1, 3); | |
16420 | let e: i64x2 = i64x2::new(0, 1); | |
16421 | let r: i64x2 = transmute(vtrn1q_p64(transmute(a), transmute(b))); | |
16422 | assert_eq!(r, e); | |
16423 | } | |
16424 | ||
16425 | #[simd_test(enable = "neon")] | |
16426 | unsafe fn test_vtrn1q_f32() { | |
16427 | let a: f32x4 = f32x4::new(0., 2., 4., 6.); | |
16428 | let b: f32x4 = f32x4::new(1., 3., 5., 7.); | |
16429 | let e: f32x4 = f32x4::new(0., 1., 4., 5.); | |
16430 | let r: f32x4 = transmute(vtrn1q_f32(transmute(a), transmute(b))); | |
16431 | assert_eq!(r, e); | |
16432 | } | |
16433 | ||
16434 | #[simd_test(enable = "neon")] | |
16435 | unsafe fn test_vtrn1_f32() { | |
16436 | let a: f32x2 = f32x2::new(0., 2.); | |
16437 | let b: f32x2 = f32x2::new(1., 3.); | |
16438 | let e: f32x2 = f32x2::new(0., 1.); | |
16439 | let r: f32x2 = transmute(vtrn1_f32(transmute(a), transmute(b))); | |
16440 | assert_eq!(r, e); | |
16441 | } | |
16442 | ||
16443 | #[simd_test(enable = "neon")] | |
16444 | unsafe fn test_vtrn1q_f64() { | |
16445 | let a: f64x2 = f64x2::new(0., 2.); | |
16446 | let b: f64x2 = f64x2::new(1., 3.); | |
16447 | let e: f64x2 = f64x2::new(0., 1.); | |
16448 | let r: f64x2 = transmute(vtrn1q_f64(transmute(a), transmute(b))); | |
16449 | assert_eq!(r, e); | |
16450 | } | |
16451 | ||
16452 | #[simd_test(enable = "neon")] | |
16453 | unsafe fn test_vtrn2_s8() { | |
16454 | let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16455 | let b: i8x8 = i8x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16456 | let e: i8x8 = i8x8::new(2, 3, 6, 7, 10, 11, 14, 15); | |
16457 | let r: i8x8 = transmute(vtrn2_s8(transmute(a), transmute(b))); | |
16458 | assert_eq!(r, e); | |
16459 | } | |
16460 | ||
16461 | #[simd_test(enable = "neon")] | |
16462 | unsafe fn test_vtrn2q_s8() { | |
16463 | let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
16464 | let b: i8x16 = i8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); | |
16465 | let e: i8x16 = i8x16::new(2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31); | |
16466 | let r: i8x16 = transmute(vtrn2q_s8(transmute(a), transmute(b))); | |
16467 | assert_eq!(r, e); | |
16468 | } | |
16469 | ||
16470 | #[simd_test(enable = "neon")] | |
16471 | unsafe fn test_vtrn2_s16() { | |
16472 | let a: i16x4 = i16x4::new(0, 2, 4, 6); | |
16473 | let b: i16x4 = i16x4::new(1, 3, 5, 7); | |
16474 | let e: i16x4 = i16x4::new(2, 3, 6, 7); | |
16475 | let r: i16x4 = transmute(vtrn2_s16(transmute(a), transmute(b))); | |
16476 | assert_eq!(r, e); | |
16477 | } | |
16478 | ||
16479 | #[simd_test(enable = "neon")] | |
16480 | unsafe fn test_vtrn2q_s16() { | |
16481 | let a: i16x8 = i16x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16482 | let b: i16x8 = i16x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16483 | let e: i16x8 = i16x8::new(2, 3, 6, 7, 10, 11, 14, 15); | |
16484 | let r: i16x8 = transmute(vtrn2q_s16(transmute(a), transmute(b))); | |
16485 | assert_eq!(r, e); | |
16486 | } | |
16487 | ||
16488 | #[simd_test(enable = "neon")] | |
16489 | unsafe fn test_vtrn2q_s32() { | |
16490 | let a: i32x4 = i32x4::new(0, 2, 4, 6); | |
16491 | let b: i32x4 = i32x4::new(1, 3, 5, 7); | |
16492 | let e: i32x4 = i32x4::new(2, 3, 6, 7); | |
16493 | let r: i32x4 = transmute(vtrn2q_s32(transmute(a), transmute(b))); | |
16494 | assert_eq!(r, e); | |
16495 | } | |
16496 | ||
16497 | #[simd_test(enable = "neon")] | |
16498 | unsafe fn test_vtrn2_u8() { | |
16499 | let a: u8x8 = u8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16500 | let b: u8x8 = u8x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16501 | let e: u8x8 = u8x8::new(2, 3, 6, 7, 10, 11, 14, 15); | |
16502 | let r: u8x8 = transmute(vtrn2_u8(transmute(a), transmute(b))); | |
16503 | assert_eq!(r, e); | |
16504 | } | |
16505 | ||
16506 | #[simd_test(enable = "neon")] | |
16507 | unsafe fn test_vtrn2q_u8() { | |
16508 | let a: u8x16 = u8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
16509 | let b: u8x16 = u8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); | |
16510 | let e: u8x16 = u8x16::new(2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31); | |
16511 | let r: u8x16 = transmute(vtrn2q_u8(transmute(a), transmute(b))); | |
16512 | assert_eq!(r, e); | |
16513 | } | |
16514 | ||
16515 | #[simd_test(enable = "neon")] | |
16516 | unsafe fn test_vtrn2_u16() { | |
16517 | let a: u16x4 = u16x4::new(0, 2, 4, 6); | |
16518 | let b: u16x4 = u16x4::new(1, 3, 5, 7); | |
16519 | let e: u16x4 = u16x4::new(2, 3, 6, 7); | |
16520 | let r: u16x4 = transmute(vtrn2_u16(transmute(a), transmute(b))); | |
16521 | assert_eq!(r, e); | |
16522 | } | |
16523 | ||
16524 | #[simd_test(enable = "neon")] | |
16525 | unsafe fn test_vtrn2q_u16() { | |
16526 | let a: u16x8 = u16x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16527 | let b: u16x8 = u16x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16528 | let e: u16x8 = u16x8::new(2, 3, 6, 7, 10, 11, 14, 15); | |
16529 | let r: u16x8 = transmute(vtrn2q_u16(transmute(a), transmute(b))); | |
16530 | assert_eq!(r, e); | |
16531 | } | |
16532 | ||
16533 | #[simd_test(enable = "neon")] | |
16534 | unsafe fn test_vtrn2q_u32() { | |
16535 | let a: u32x4 = u32x4::new(0, 2, 4, 6); | |
16536 | let b: u32x4 = u32x4::new(1, 3, 5, 7); | |
16537 | let e: u32x4 = u32x4::new(2, 3, 6, 7); | |
16538 | let r: u32x4 = transmute(vtrn2q_u32(transmute(a), transmute(b))); | |
16539 | assert_eq!(r, e); | |
16540 | } | |
16541 | ||
16542 | #[simd_test(enable = "neon")] | |
16543 | unsafe fn test_vtrn2_p8() { | |
16544 | let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16545 | let b: i8x8 = i8x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16546 | let e: i8x8 = i8x8::new(2, 3, 6, 7, 10, 11, 14, 15); | |
16547 | let r: i8x8 = transmute(vtrn2_p8(transmute(a), transmute(b))); | |
16548 | assert_eq!(r, e); | |
16549 | } | |
16550 | ||
16551 | #[simd_test(enable = "neon")] | |
16552 | unsafe fn test_vtrn2q_p8() { | |
16553 | let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
16554 | let b: i8x16 = i8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); | |
16555 | let e: i8x16 = i8x16::new(2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31); | |
16556 | let r: i8x16 = transmute(vtrn2q_p8(transmute(a), transmute(b))); | |
16557 | assert_eq!(r, e); | |
16558 | } | |
16559 | ||
16560 | #[simd_test(enable = "neon")] | |
16561 | unsafe fn test_vtrn2_p16() { | |
16562 | let a: i16x4 = i16x4::new(0, 2, 4, 6); | |
16563 | let b: i16x4 = i16x4::new(1, 3, 5, 7); | |
16564 | let e: i16x4 = i16x4::new(2, 3, 6, 7); | |
16565 | let r: i16x4 = transmute(vtrn2_p16(transmute(a), transmute(b))); | |
16566 | assert_eq!(r, e); | |
16567 | } | |
16568 | ||
16569 | #[simd_test(enable = "neon")] | |
16570 | unsafe fn test_vtrn2q_p16() { | |
16571 | let a: i16x8 = i16x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16572 | let b: i16x8 = i16x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16573 | let e: i16x8 = i16x8::new(2, 3, 6, 7, 10, 11, 14, 15); | |
16574 | let r: i16x8 = transmute(vtrn2q_p16(transmute(a), transmute(b))); | |
16575 | assert_eq!(r, e); | |
16576 | } | |
16577 | ||
16578 | #[simd_test(enable = "neon")] | |
16579 | unsafe fn test_vtrn2_s32() { | |
16580 | let a: i32x2 = i32x2::new(0, 2); | |
16581 | let b: i32x2 = i32x2::new(1, 3); | |
16582 | let e: i32x2 = i32x2::new(2, 3); | |
16583 | let r: i32x2 = transmute(vtrn2_s32(transmute(a), transmute(b))); | |
16584 | assert_eq!(r, e); | |
16585 | } | |
16586 | ||
16587 | #[simd_test(enable = "neon")] | |
16588 | unsafe fn test_vtrn2q_s64() { | |
16589 | let a: i64x2 = i64x2::new(0, 2); | |
16590 | let b: i64x2 = i64x2::new(1, 3); | |
16591 | let e: i64x2 = i64x2::new(2, 3); | |
16592 | let r: i64x2 = transmute(vtrn2q_s64(transmute(a), transmute(b))); | |
16593 | assert_eq!(r, e); | |
16594 | } | |
16595 | ||
16596 | #[simd_test(enable = "neon")] | |
16597 | unsafe fn test_vtrn2_u32() { | |
16598 | let a: u32x2 = u32x2::new(0, 2); | |
16599 | let b: u32x2 = u32x2::new(1, 3); | |
16600 | let e: u32x2 = u32x2::new(2, 3); | |
16601 | let r: u32x2 = transmute(vtrn2_u32(transmute(a), transmute(b))); | |
16602 | assert_eq!(r, e); | |
16603 | } | |
16604 | ||
16605 | #[simd_test(enable = "neon")] | |
16606 | unsafe fn test_vtrn2q_u64() { | |
16607 | let a: u64x2 = u64x2::new(0, 2); | |
16608 | let b: u64x2 = u64x2::new(1, 3); | |
16609 | let e: u64x2 = u64x2::new(2, 3); | |
16610 | let r: u64x2 = transmute(vtrn2q_u64(transmute(a), transmute(b))); | |
16611 | assert_eq!(r, e); | |
16612 | } | |
16613 | ||
16614 | #[simd_test(enable = "neon")] | |
16615 | unsafe fn test_vtrn2q_p64() { | |
16616 | let a: i64x2 = i64x2::new(0, 2); | |
16617 | let b: i64x2 = i64x2::new(1, 3); | |
16618 | let e: i64x2 = i64x2::new(2, 3); | |
16619 | let r: i64x2 = transmute(vtrn2q_p64(transmute(a), transmute(b))); | |
16620 | assert_eq!(r, e); | |
16621 | } | |
16622 | ||
16623 | #[simd_test(enable = "neon")] | |
16624 | unsafe fn test_vtrn2q_f32() { | |
16625 | let a: f32x4 = f32x4::new(0., 2., 4., 6.); | |
16626 | let b: f32x4 = f32x4::new(1., 3., 5., 7.); | |
16627 | let e: f32x4 = f32x4::new(2., 3., 6., 7.); | |
16628 | let r: f32x4 = transmute(vtrn2q_f32(transmute(a), transmute(b))); | |
16629 | assert_eq!(r, e); | |
16630 | } | |
16631 | ||
16632 | #[simd_test(enable = "neon")] | |
16633 | unsafe fn test_vtrn2_f32() { | |
16634 | let a: f32x2 = f32x2::new(0., 2.); | |
16635 | let b: f32x2 = f32x2::new(1., 3.); | |
16636 | let e: f32x2 = f32x2::new(2., 3.); | |
16637 | let r: f32x2 = transmute(vtrn2_f32(transmute(a), transmute(b))); | |
16638 | assert_eq!(r, e); | |
16639 | } | |
16640 | ||
16641 | #[simd_test(enable = "neon")] | |
16642 | unsafe fn test_vtrn2q_f64() { | |
16643 | let a: f64x2 = f64x2::new(0., 2.); | |
16644 | let b: f64x2 = f64x2::new(1., 3.); | |
16645 | let e: f64x2 = f64x2::new(2., 3.); | |
16646 | let r: f64x2 = transmute(vtrn2q_f64(transmute(a), transmute(b))); | |
16647 | assert_eq!(r, e); | |
16648 | } | |
16649 | ||
16650 | #[simd_test(enable = "neon")] | |
16651 | unsafe fn test_vzip1_s8() { | |
16652 | let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16653 | let b: i8x8 = i8x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16654 | let e: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); | |
16655 | let r: i8x8 = transmute(vzip1_s8(transmute(a), transmute(b))); | |
16656 | assert_eq!(r, e); | |
16657 | } | |
16658 | ||
16659 | #[simd_test(enable = "neon")] | |
16660 | unsafe fn test_vzip1q_s8() { | |
16661 | let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
16662 | let b: i8x16 = i8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); | |
16663 | let e: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); | |
16664 | let r: i8x16 = transmute(vzip1q_s8(transmute(a), transmute(b))); | |
16665 | assert_eq!(r, e); | |
16666 | } | |
16667 | ||
16668 | #[simd_test(enable = "neon")] | |
16669 | unsafe fn test_vzip1_s16() { | |
16670 | let a: i16x4 = i16x4::new(0, 2, 4, 6); | |
16671 | let b: i16x4 = i16x4::new(1, 3, 5, 7); | |
16672 | let e: i16x4 = i16x4::new(0, 1, 2, 3); | |
16673 | let r: i16x4 = transmute(vzip1_s16(transmute(a), transmute(b))); | |
16674 | assert_eq!(r, e); | |
16675 | } | |
16676 | ||
16677 | #[simd_test(enable = "neon")] | |
16678 | unsafe fn test_vzip1q_s16() { | |
16679 | let a: i16x8 = i16x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16680 | let b: i16x8 = i16x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16681 | let e: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); | |
16682 | let r: i16x8 = transmute(vzip1q_s16(transmute(a), transmute(b))); | |
16683 | assert_eq!(r, e); | |
16684 | } | |
16685 | ||
16686 | #[simd_test(enable = "neon")] | |
16687 | unsafe fn test_vzip1_s32() { | |
16688 | let a: i32x2 = i32x2::new(0, 2); | |
16689 | let b: i32x2 = i32x2::new(1, 3); | |
16690 | let e: i32x2 = i32x2::new(0, 1); | |
16691 | let r: i32x2 = transmute(vzip1_s32(transmute(a), transmute(b))); | |
16692 | assert_eq!(r, e); | |
16693 | } | |
16694 | ||
16695 | #[simd_test(enable = "neon")] | |
16696 | unsafe fn test_vzip1q_s32() { | |
16697 | let a: i32x4 = i32x4::new(0, 2, 4, 6); | |
16698 | let b: i32x4 = i32x4::new(1, 3, 5, 7); | |
16699 | let e: i32x4 = i32x4::new(0, 1, 2, 3); | |
16700 | let r: i32x4 = transmute(vzip1q_s32(transmute(a), transmute(b))); | |
16701 | assert_eq!(r, e); | |
16702 | } | |
16703 | ||
16704 | #[simd_test(enable = "neon")] | |
16705 | unsafe fn test_vzip1q_s64() { | |
16706 | let a: i64x2 = i64x2::new(0, 2); | |
16707 | let b: i64x2 = i64x2::new(1, 3); | |
16708 | let e: i64x2 = i64x2::new(0, 1); | |
16709 | let r: i64x2 = transmute(vzip1q_s64(transmute(a), transmute(b))); | |
16710 | assert_eq!(r, e); | |
16711 | } | |
16712 | ||
16713 | #[simd_test(enable = "neon")] | |
16714 | unsafe fn test_vzip1_u8() { | |
16715 | let a: u8x8 = u8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16716 | let b: u8x8 = u8x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16717 | let e: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); | |
16718 | let r: u8x8 = transmute(vzip1_u8(transmute(a), transmute(b))); | |
16719 | assert_eq!(r, e); | |
16720 | } | |
16721 | ||
16722 | #[simd_test(enable = "neon")] | |
16723 | unsafe fn test_vzip1q_u8() { | |
16724 | let a: u8x16 = u8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
16725 | let b: u8x16 = u8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); | |
16726 | let e: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); | |
16727 | let r: u8x16 = transmute(vzip1q_u8(transmute(a), transmute(b))); | |
16728 | assert_eq!(r, e); | |
16729 | } | |
16730 | ||
16731 | #[simd_test(enable = "neon")] | |
16732 | unsafe fn test_vzip1_u16() { | |
16733 | let a: u16x4 = u16x4::new(0, 2, 4, 6); | |
16734 | let b: u16x4 = u16x4::new(1, 3, 5, 7); | |
16735 | let e: u16x4 = u16x4::new(0, 1, 2, 3); | |
16736 | let r: u16x4 = transmute(vzip1_u16(transmute(a), transmute(b))); | |
16737 | assert_eq!(r, e); | |
16738 | } | |
16739 | ||
16740 | #[simd_test(enable = "neon")] | |
16741 | unsafe fn test_vzip1q_u16() { | |
16742 | let a: u16x8 = u16x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16743 | let b: u16x8 = u16x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16744 | let e: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); | |
16745 | let r: u16x8 = transmute(vzip1q_u16(transmute(a), transmute(b))); | |
16746 | assert_eq!(r, e); | |
16747 | } | |
16748 | ||
16749 | #[simd_test(enable = "neon")] | |
16750 | unsafe fn test_vzip1_u32() { | |
16751 | let a: u32x2 = u32x2::new(0, 2); | |
16752 | let b: u32x2 = u32x2::new(1, 3); | |
16753 | let e: u32x2 = u32x2::new(0, 1); | |
16754 | let r: u32x2 = transmute(vzip1_u32(transmute(a), transmute(b))); | |
16755 | assert_eq!(r, e); | |
16756 | } | |
16757 | ||
16758 | #[simd_test(enable = "neon")] | |
16759 | unsafe fn test_vzip1q_u32() { | |
16760 | let a: u32x4 = u32x4::new(0, 2, 4, 6); | |
16761 | let b: u32x4 = u32x4::new(1, 3, 5, 7); | |
16762 | let e: u32x4 = u32x4::new(0, 1, 2, 3); | |
16763 | let r: u32x4 = transmute(vzip1q_u32(transmute(a), transmute(b))); | |
16764 | assert_eq!(r, e); | |
16765 | } | |
16766 | ||
16767 | #[simd_test(enable = "neon")] | |
16768 | unsafe fn test_vzip1q_u64() { | |
16769 | let a: u64x2 = u64x2::new(0, 2); | |
16770 | let b: u64x2 = u64x2::new(1, 3); | |
16771 | let e: u64x2 = u64x2::new(0, 1); | |
16772 | let r: u64x2 = transmute(vzip1q_u64(transmute(a), transmute(b))); | |
16773 | assert_eq!(r, e); | |
16774 | } | |
16775 | ||
16776 | #[simd_test(enable = "neon")] | |
16777 | unsafe fn test_vzip1_p8() { | |
16778 | let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16779 | let b: i8x8 = i8x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16780 | let e: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); | |
16781 | let r: i8x8 = transmute(vzip1_p8(transmute(a), transmute(b))); | |
16782 | assert_eq!(r, e); | |
16783 | } | |
16784 | ||
16785 | #[simd_test(enable = "neon")] | |
16786 | unsafe fn test_vzip1q_p8() { | |
16787 | let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
16788 | let b: i8x16 = i8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); | |
16789 | let e: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); | |
16790 | let r: i8x16 = transmute(vzip1q_p8(transmute(a), transmute(b))); | |
16791 | assert_eq!(r, e); | |
16792 | } | |
16793 | ||
16794 | #[simd_test(enable = "neon")] | |
16795 | unsafe fn test_vzip1_p16() { | |
16796 | let a: i16x4 = i16x4::new(0, 2, 4, 6); | |
16797 | let b: i16x4 = i16x4::new(1, 3, 5, 7); | |
16798 | let e: i16x4 = i16x4::new(0, 1, 2, 3); | |
16799 | let r: i16x4 = transmute(vzip1_p16(transmute(a), transmute(b))); | |
16800 | assert_eq!(r, e); | |
16801 | } | |
16802 | ||
16803 | #[simd_test(enable = "neon")] | |
16804 | unsafe fn test_vzip1q_p16() { | |
16805 | let a: i16x8 = i16x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16806 | let b: i16x8 = i16x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16807 | let e: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); | |
16808 | let r: i16x8 = transmute(vzip1q_p16(transmute(a), transmute(b))); | |
16809 | assert_eq!(r, e); | |
16810 | } | |
16811 | ||
16812 | #[simd_test(enable = "neon")] | |
16813 | unsafe fn test_vzip1q_p64() { | |
16814 | let a: i64x2 = i64x2::new(0, 2); | |
16815 | let b: i64x2 = i64x2::new(1, 3); | |
16816 | let e: i64x2 = i64x2::new(0, 1); | |
16817 | let r: i64x2 = transmute(vzip1q_p64(transmute(a), transmute(b))); | |
16818 | assert_eq!(r, e); | |
16819 | } | |
16820 | ||
16821 | #[simd_test(enable = "neon")] | |
16822 | unsafe fn test_vzip1_f32() { | |
16823 | let a: f32x2 = f32x2::new(0., 2.); | |
16824 | let b: f32x2 = f32x2::new(1., 3.); | |
16825 | let e: f32x2 = f32x2::new(0., 1.); | |
16826 | let r: f32x2 = transmute(vzip1_f32(transmute(a), transmute(b))); | |
16827 | assert_eq!(r, e); | |
16828 | } | |
16829 | ||
16830 | #[simd_test(enable = "neon")] | |
16831 | unsafe fn test_vzip1q_f32() { | |
16832 | let a: f32x4 = f32x4::new(0., 2., 4., 6.); | |
16833 | let b: f32x4 = f32x4::new(1., 3., 5., 7.); | |
16834 | let e: f32x4 = f32x4::new(0., 1., 2., 3.); | |
16835 | let r: f32x4 = transmute(vzip1q_f32(transmute(a), transmute(b))); | |
16836 | assert_eq!(r, e); | |
16837 | } | |
16838 | ||
16839 | #[simd_test(enable = "neon")] | |
16840 | unsafe fn test_vzip1q_f64() { | |
16841 | let a: f64x2 = f64x2::new(0., 2.); | |
16842 | let b: f64x2 = f64x2::new(1., 3.); | |
16843 | let e: f64x2 = f64x2::new(0., 1.); | |
16844 | let r: f64x2 = transmute(vzip1q_f64(transmute(a), transmute(b))); | |
16845 | assert_eq!(r, e); | |
16846 | } | |
16847 | ||
16848 | #[simd_test(enable = "neon")] | |
16849 | unsafe fn test_vzip2_s8() { | |
16850 | let a: i8x8 = i8x8::new(0, 16, 16, 18, 16, 18, 20, 22); | |
16851 | let b: i8x8 = i8x8::new(1, 17, 17, 19, 17, 19, 21, 23); | |
16852 | let e: i8x8 = i8x8::new(16, 17, 18, 19, 20, 21, 22, 23); | |
16853 | let r: i8x8 = transmute(vzip2_s8(transmute(a), transmute(b))); | |
16854 | assert_eq!(r, e); | |
16855 | } | |
16856 | ||
16857 | #[simd_test(enable = "neon")] | |
16858 | unsafe fn test_vzip2q_s8() { | |
16859 | let a: i8x16 = i8x16::new(0, 16, 16, 18, 16, 18, 20, 22, 16, 18, 20, 22, 24, 26, 28, 30); | |
16860 | let b: i8x16 = i8x16::new(1, 17, 17, 19, 17, 19, 21, 23, 17, 19, 21, 23, 25, 27, 29, 31); | |
16861 | let e: i8x16 = i8x16::new(16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31); | |
16862 | let r: i8x16 = transmute(vzip2q_s8(transmute(a), transmute(b))); | |
16863 | assert_eq!(r, e); | |
16864 | } | |
16865 | ||
16866 | #[simd_test(enable = "neon")] | |
16867 | unsafe fn test_vzip2_s16() { | |
16868 | let a: i16x4 = i16x4::new(0, 16, 16, 18); | |
16869 | let b: i16x4 = i16x4::new(1, 17, 17, 19); | |
16870 | let e: i16x4 = i16x4::new(16, 17, 18, 19); | |
16871 | let r: i16x4 = transmute(vzip2_s16(transmute(a), transmute(b))); | |
16872 | assert_eq!(r, e); | |
16873 | } | |
16874 | ||
16875 | #[simd_test(enable = "neon")] | |
16876 | unsafe fn test_vzip2q_s16() { | |
16877 | let a: i16x8 = i16x8::new(0, 16, 16, 18, 16, 18, 20, 22); | |
16878 | let b: i16x8 = i16x8::new(1, 17, 17, 19, 17, 19, 21, 23); | |
16879 | let e: i16x8 = i16x8::new(16, 17, 18, 19, 20, 21, 22, 23); | |
16880 | let r: i16x8 = transmute(vzip2q_s16(transmute(a), transmute(b))); | |
16881 | assert_eq!(r, e); | |
16882 | } | |
16883 | ||
16884 | #[simd_test(enable = "neon")] | |
16885 | unsafe fn test_vzip2_s32() { | |
16886 | let a: i32x2 = i32x2::new(0, 16); | |
16887 | let b: i32x2 = i32x2::new(1, 17); | |
16888 | let e: i32x2 = i32x2::new(16, 17); | |
16889 | let r: i32x2 = transmute(vzip2_s32(transmute(a), transmute(b))); | |
16890 | assert_eq!(r, e); | |
16891 | } | |
16892 | ||
16893 | #[simd_test(enable = "neon")] | |
16894 | unsafe fn test_vzip2q_s32() { | |
16895 | let a: i32x4 = i32x4::new(0, 16, 16, 18); | |
16896 | let b: i32x4 = i32x4::new(1, 17, 17, 19); | |
16897 | let e: i32x4 = i32x4::new(16, 17, 18, 19); | |
16898 | let r: i32x4 = transmute(vzip2q_s32(transmute(a), transmute(b))); | |
16899 | assert_eq!(r, e); | |
16900 | } | |
16901 | ||
16902 | #[simd_test(enable = "neon")] | |
16903 | unsafe fn test_vzip2q_s64() { | |
16904 | let a: i64x2 = i64x2::new(0, 16); | |
16905 | let b: i64x2 = i64x2::new(1, 17); | |
16906 | let e: i64x2 = i64x2::new(16, 17); | |
16907 | let r: i64x2 = transmute(vzip2q_s64(transmute(a), transmute(b))); | |
16908 | assert_eq!(r, e); | |
16909 | } | |
16910 | ||
16911 | #[simd_test(enable = "neon")] | |
16912 | unsafe fn test_vzip2_u8() { | |
16913 | let a: u8x8 = u8x8::new(0, 16, 16, 18, 16, 18, 20, 22); | |
16914 | let b: u8x8 = u8x8::new(1, 17, 17, 19, 17, 19, 21, 23); | |
16915 | let e: u8x8 = u8x8::new(16, 17, 18, 19, 20, 21, 22, 23); | |
16916 | let r: u8x8 = transmute(vzip2_u8(transmute(a), transmute(b))); | |
16917 | assert_eq!(r, e); | |
16918 | } | |
16919 | ||
16920 | #[simd_test(enable = "neon")] | |
16921 | unsafe fn test_vzip2q_u8() { | |
16922 | let a: u8x16 = u8x16::new(0, 16, 16, 18, 16, 18, 20, 22, 16, 18, 20, 22, 24, 26, 28, 30); | |
16923 | let b: u8x16 = u8x16::new(1, 17, 17, 19, 17, 19, 21, 23, 17, 19, 21, 23, 25, 27, 29, 31); | |
16924 | let e: u8x16 = u8x16::new(16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31); | |
16925 | let r: u8x16 = transmute(vzip2q_u8(transmute(a), transmute(b))); | |
16926 | assert_eq!(r, e); | |
16927 | } | |
16928 | ||
16929 | #[simd_test(enable = "neon")] | |
16930 | unsafe fn test_vzip2_u16() { | |
16931 | let a: u16x4 = u16x4::new(0, 16, 16, 18); | |
16932 | let b: u16x4 = u16x4::new(1, 17, 17, 19); | |
16933 | let e: u16x4 = u16x4::new(16, 17, 18, 19); | |
16934 | let r: u16x4 = transmute(vzip2_u16(transmute(a), transmute(b))); | |
16935 | assert_eq!(r, e); | |
16936 | } | |
16937 | ||
16938 | #[simd_test(enable = "neon")] | |
16939 | unsafe fn test_vzip2q_u16() { | |
16940 | let a: u16x8 = u16x8::new(0, 16, 16, 18, 16, 18, 20, 22); | |
16941 | let b: u16x8 = u16x8::new(1, 17, 17, 19, 17, 19, 21, 23); | |
16942 | let e: u16x8 = u16x8::new(16, 17, 18, 19, 20, 21, 22, 23); | |
16943 | let r: u16x8 = transmute(vzip2q_u16(transmute(a), transmute(b))); | |
16944 | assert_eq!(r, e); | |
16945 | } | |
16946 | ||
16947 | #[simd_test(enable = "neon")] | |
16948 | unsafe fn test_vzip2_u32() { | |
16949 | let a: u32x2 = u32x2::new(0, 16); | |
16950 | let b: u32x2 = u32x2::new(1, 17); | |
16951 | let e: u32x2 = u32x2::new(16, 17); | |
16952 | let r: u32x2 = transmute(vzip2_u32(transmute(a), transmute(b))); | |
16953 | assert_eq!(r, e); | |
16954 | } | |
16955 | ||
16956 | #[simd_test(enable = "neon")] | |
16957 | unsafe fn test_vzip2q_u32() { | |
16958 | let a: u32x4 = u32x4::new(0, 16, 16, 18); | |
16959 | let b: u32x4 = u32x4::new(1, 17, 17, 19); | |
16960 | let e: u32x4 = u32x4::new(16, 17, 18, 19); | |
16961 | let r: u32x4 = transmute(vzip2q_u32(transmute(a), transmute(b))); | |
16962 | assert_eq!(r, e); | |
16963 | } | |
16964 | ||
16965 | #[simd_test(enable = "neon")] | |
16966 | unsafe fn test_vzip2q_u64() { | |
16967 | let a: u64x2 = u64x2::new(0, 16); | |
16968 | let b: u64x2 = u64x2::new(1, 17); | |
16969 | let e: u64x2 = u64x2::new(16, 17); | |
16970 | let r: u64x2 = transmute(vzip2q_u64(transmute(a), transmute(b))); | |
16971 | assert_eq!(r, e); | |
16972 | } | |
16973 | ||
16974 | #[simd_test(enable = "neon")] | |
16975 | unsafe fn test_vzip2_p8() { | |
16976 | let a: i8x8 = i8x8::new(0, 16, 16, 18, 16, 18, 20, 22); | |
16977 | let b: i8x8 = i8x8::new(1, 17, 17, 19, 17, 19, 21, 23); | |
16978 | let e: i8x8 = i8x8::new(16, 17, 18, 19, 20, 21, 22, 23); | |
16979 | let r: i8x8 = transmute(vzip2_p8(transmute(a), transmute(b))); | |
16980 | assert_eq!(r, e); | |
16981 | } | |
16982 | ||
16983 | #[simd_test(enable = "neon")] | |
16984 | unsafe fn test_vzip2q_p8() { | |
16985 | let a: i8x16 = i8x16::new(0, 16, 16, 18, 16, 18, 20, 22, 16, 18, 20, 22, 24, 26, 28, 30); | |
16986 | let b: i8x16 = i8x16::new(1, 17, 17, 19, 17, 19, 21, 23, 17, 19, 21, 23, 25, 27, 29, 31); | |
16987 | let e: i8x16 = i8x16::new(16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31); | |
16988 | let r: i8x16 = transmute(vzip2q_p8(transmute(a), transmute(b))); | |
16989 | assert_eq!(r, e); | |
16990 | } | |
16991 | ||
16992 | #[simd_test(enable = "neon")] | |
16993 | unsafe fn test_vzip2_p16() { | |
16994 | let a: i16x4 = i16x4::new(0, 16, 16, 18); | |
16995 | let b: i16x4 = i16x4::new(1, 17, 17, 19); | |
16996 | let e: i16x4 = i16x4::new(16, 17, 18, 19); | |
16997 | let r: i16x4 = transmute(vzip2_p16(transmute(a), transmute(b))); | |
16998 | assert_eq!(r, e); | |
16999 | } | |
17000 | ||
17001 | #[simd_test(enable = "neon")] | |
17002 | unsafe fn test_vzip2q_p16() { | |
17003 | let a: i16x8 = i16x8::new(0, 16, 16, 18, 16, 18, 20, 22); | |
17004 | let b: i16x8 = i16x8::new(1, 17, 17, 19, 17, 19, 21, 23); | |
17005 | let e: i16x8 = i16x8::new(16, 17, 18, 19, 20, 21, 22, 23); | |
17006 | let r: i16x8 = transmute(vzip2q_p16(transmute(a), transmute(b))); | |
17007 | assert_eq!(r, e); | |
17008 | } | |
17009 | ||
17010 | #[simd_test(enable = "neon")] | |
17011 | unsafe fn test_vzip2q_p64() { | |
17012 | let a: i64x2 = i64x2::new(0, 16); | |
17013 | let b: i64x2 = i64x2::new(1, 17); | |
17014 | let e: i64x2 = i64x2::new(16, 17); | |
17015 | let r: i64x2 = transmute(vzip2q_p64(transmute(a), transmute(b))); | |
17016 | assert_eq!(r, e); | |
17017 | } | |
ba9703b0 XL |
17018 | |
17019 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17020 | unsafe fn test_vzip2_f32() { |
17021 | let a: f32x2 = f32x2::new(0., 8.); | |
17022 | let b: f32x2 = f32x2::new(1., 9.); | |
17023 | let e: f32x2 = f32x2::new(8., 9.); | |
17024 | let r: f32x2 = transmute(vzip2_f32(transmute(a), transmute(b))); | |
ba9703b0 | 17025 | assert_eq!(r, e); |
17df50a5 | 17026 | } |
ba9703b0 | 17027 | |
17df50a5 XL |
17028 | #[simd_test(enable = "neon")] |
17029 | unsafe fn test_vzip2q_f32() { | |
17030 | let a: f32x4 = f32x4::new(0., 8., 8., 10.); | |
17031 | let b: f32x4 = f32x4::new(1., 9., 9., 11.); | |
17032 | let e: f32x4 = f32x4::new(8., 9., 10., 11.); | |
17033 | let r: f32x4 = transmute(vzip2q_f32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17034 | assert_eq!(r, e); |
17035 | } | |
17036 | ||
17037 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17038 | unsafe fn test_vzip2q_f64() { |
17039 | let a: f64x2 = f64x2::new(0., 8.); | |
17040 | let b: f64x2 = f64x2::new(1., 9.); | |
17041 | let e: f64x2 = f64x2::new(8., 9.); | |
17042 | let r: f64x2 = transmute(vzip2q_f64(transmute(a), transmute(b))); | |
ba9703b0 | 17043 | assert_eq!(r, e); |
17df50a5 | 17044 | } |
ba9703b0 | 17045 | |
17df50a5 XL |
17046 | #[simd_test(enable = "neon")] |
17047 | unsafe fn test_vuzp1_s8() { | |
17048 | let a: i8x8 = i8x8::new(1, 0, 2, 0, 2, 0, 3, 0); | |
17049 | let b: i8x8 = i8x8::new(2, 0, 3, 0, 7, 0, 8, 0); | |
17050 | let e: i8x8 = i8x8::new(1, 2, 2, 3, 2, 3, 7, 8); | |
17051 | let r: i8x8 = transmute(vuzp1_s8(transmute(a), transmute(b))); | |
ba9703b0 XL |
17052 | assert_eq!(r, e); |
17053 | } | |
17054 | ||
17055 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17056 | unsafe fn test_vuzp1q_s8() { |
17057 | let a: i8x16 = i8x16::new(1, 0, 2, 0, 2, 0, 3, 0, 2, 0, 3, 0, 7, 0, 8, 0); | |
17058 | let b: i8x16 = i8x16::new(2, 0, 3, 0, 7, 0, 8, 0, 13, 0, 14, 0, 15, 0, 16, 0); | |
17059 | let e: i8x16 = i8x16::new(1, 2, 2, 3, 2, 3, 7, 8, 2, 3, 7, 8, 13, 14, 15, 16); | |
17060 | let r: i8x16 = transmute(vuzp1q_s8(transmute(a), transmute(b))); | |
ba9703b0 | 17061 | assert_eq!(r, e); |
17df50a5 | 17062 | } |
ba9703b0 | 17063 | |
17df50a5 XL |
17064 | #[simd_test(enable = "neon")] |
17065 | unsafe fn test_vuzp1_s16() { | |
17066 | let a: i16x4 = i16x4::new(1, 0, 2, 0); | |
17067 | let b: i16x4 = i16x4::new(2, 0, 3, 0); | |
17068 | let e: i16x4 = i16x4::new(1, 2, 2, 3); | |
17069 | let r: i16x4 = transmute(vuzp1_s16(transmute(a), transmute(b))); | |
ba9703b0 XL |
17070 | assert_eq!(r, e); |
17071 | } | |
17072 | ||
17073 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17074 | unsafe fn test_vuzp1q_s16() { |
17075 | let a: i16x8 = i16x8::new(1, 0, 2, 0, 2, 0, 3, 0); | |
17076 | let b: i16x8 = i16x8::new(2, 0, 3, 0, 7, 0, 8, 0); | |
17077 | let e: i16x8 = i16x8::new(1, 2, 2, 3, 2, 3, 7, 8); | |
17078 | let r: i16x8 = transmute(vuzp1q_s16(transmute(a), transmute(b))); | |
ba9703b0 | 17079 | assert_eq!(r, e); |
17df50a5 | 17080 | } |
ba9703b0 | 17081 | |
17df50a5 XL |
17082 | #[simd_test(enable = "neon")] |
17083 | unsafe fn test_vuzp1q_s32() { | |
17084 | let a: i32x4 = i32x4::new(1, 0, 2, 0); | |
17085 | let b: i32x4 = i32x4::new(2, 0, 3, 0); | |
17086 | let e: i32x4 = i32x4::new(1, 2, 2, 3); | |
17087 | let r: i32x4 = transmute(vuzp1q_s32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17088 | assert_eq!(r, e); |
17089 | } | |
17090 | ||
17091 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17092 | unsafe fn test_vuzp1_u8() { |
17093 | let a: u8x8 = u8x8::new(1, 0, 2, 0, 2, 0, 3, 0); | |
17094 | let b: u8x8 = u8x8::new(2, 0, 3, 0, 7, 0, 8, 0); | |
17095 | let e: u8x8 = u8x8::new(1, 2, 2, 3, 2, 3, 7, 8); | |
17096 | let r: u8x8 = transmute(vuzp1_u8(transmute(a), transmute(b))); | |
ba9703b0 | 17097 | assert_eq!(r, e); |
17df50a5 | 17098 | } |
ba9703b0 | 17099 | |
17df50a5 XL |
17100 | #[simd_test(enable = "neon")] |
17101 | unsafe fn test_vuzp1q_u8() { | |
17102 | let a: u8x16 = u8x16::new(1, 0, 2, 0, 2, 0, 3, 0, 2, 0, 3, 0, 7, 0, 8, 0); | |
17103 | let b: u8x16 = u8x16::new(2, 0, 3, 0, 7, 0, 8, 0, 13, 0, 14, 0, 15, 0, 16, 0); | |
17104 | let e: u8x16 = u8x16::new(1, 2, 2, 3, 2, 3, 7, 8, 2, 3, 7, 8, 13, 14, 15, 16); | |
17105 | let r: u8x16 = transmute(vuzp1q_u8(transmute(a), transmute(b))); | |
ba9703b0 XL |
17106 | assert_eq!(r, e); |
17107 | } | |
17108 | ||
17109 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17110 | unsafe fn test_vuzp1_u16() { |
17111 | let a: u16x4 = u16x4::new(1, 0, 2, 0); | |
17112 | let b: u16x4 = u16x4::new(2, 0, 3, 0); | |
17113 | let e: u16x4 = u16x4::new(1, 2, 2, 3); | |
17114 | let r: u16x4 = transmute(vuzp1_u16(transmute(a), transmute(b))); | |
ba9703b0 | 17115 | assert_eq!(r, e); |
17df50a5 | 17116 | } |
ba9703b0 | 17117 | |
17df50a5 XL |
17118 | #[simd_test(enable = "neon")] |
17119 | unsafe fn test_vuzp1q_u16() { | |
17120 | let a: u16x8 = u16x8::new(1, 0, 2, 0, 2, 0, 3, 0); | |
17121 | let b: u16x8 = u16x8::new(2, 0, 3, 0, 7, 0, 8, 0); | |
17122 | let e: u16x8 = u16x8::new(1, 2, 2, 3, 2, 3, 7, 8); | |
17123 | let r: u16x8 = transmute(vuzp1q_u16(transmute(a), transmute(b))); | |
ba9703b0 XL |
17124 | assert_eq!(r, e); |
17125 | } | |
17126 | ||
17127 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17128 | unsafe fn test_vuzp1q_u32() { |
17129 | let a: u32x4 = u32x4::new(1, 0, 2, 0); | |
17130 | let b: u32x4 = u32x4::new(2, 0, 3, 0); | |
17131 | let e: u32x4 = u32x4::new(1, 2, 2, 3); | |
17132 | let r: u32x4 = transmute(vuzp1q_u32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17133 | assert_eq!(r, e); |
17134 | } | |
17135 | ||
17136 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17137 | unsafe fn test_vuzp1_p8() { |
17138 | let a: i8x8 = i8x8::new(1, 0, 2, 0, 2, 0, 3, 0); | |
17139 | let b: i8x8 = i8x8::new(2, 0, 3, 0, 7, 0, 8, 0); | |
17140 | let e: i8x8 = i8x8::new(1, 2, 2, 3, 2, 3, 7, 8); | |
17141 | let r: i8x8 = transmute(vuzp1_p8(transmute(a), transmute(b))); | |
ba9703b0 XL |
17142 | assert_eq!(r, e); |
17143 | } | |
17144 | ||
17145 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17146 | unsafe fn test_vuzp1q_p8() { |
17147 | let a: i8x16 = i8x16::new(1, 0, 2, 0, 2, 0, 3, 0, 2, 0, 3, 0, 7, 0, 8, 0); | |
17148 | let b: i8x16 = i8x16::new(2, 0, 3, 0, 7, 0, 8, 0, 13, 0, 14, 0, 15, 0, 16, 0); | |
17149 | let e: i8x16 = i8x16::new(1, 2, 2, 3, 2, 3, 7, 8, 2, 3, 7, 8, 13, 14, 15, 16); | |
17150 | let r: i8x16 = transmute(vuzp1q_p8(transmute(a), transmute(b))); | |
ba9703b0 XL |
17151 | assert_eq!(r, e); |
17152 | } | |
17153 | ||
17154 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17155 | unsafe fn test_vuzp1_p16() { |
17156 | let a: i16x4 = i16x4::new(1, 0, 2, 0); | |
17157 | let b: i16x4 = i16x4::new(2, 0, 3, 0); | |
17158 | let e: i16x4 = i16x4::new(1, 2, 2, 3); | |
17159 | let r: i16x4 = transmute(vuzp1_p16(transmute(a), transmute(b))); | |
ba9703b0 XL |
17160 | assert_eq!(r, e); |
17161 | } | |
17162 | ||
17163 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17164 | unsafe fn test_vuzp1q_p16() { |
17165 | let a: i16x8 = i16x8::new(1, 0, 2, 0, 2, 0, 3, 0); | |
17166 | let b: i16x8 = i16x8::new(2, 0, 3, 0, 7, 0, 8, 0); | |
17167 | let e: i16x8 = i16x8::new(1, 2, 2, 3, 2, 3, 7, 8); | |
17168 | let r: i16x8 = transmute(vuzp1q_p16(transmute(a), transmute(b))); | |
ba9703b0 XL |
17169 | assert_eq!(r, e); |
17170 | } | |
17171 | ||
17172 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17173 | unsafe fn test_vuzp1_s32() { |
17174 | let a: i32x2 = i32x2::new(1, 0); | |
17175 | let b: i32x2 = i32x2::new(2, 0); | |
17176 | let e: i32x2 = i32x2::new(1, 2); | |
17177 | let r: i32x2 = transmute(vuzp1_s32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17178 | assert_eq!(r, e); |
17179 | } | |
17180 | ||
17181 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17182 | unsafe fn test_vuzp1q_s64() { |
17183 | let a: i64x2 = i64x2::new(1, 0); | |
17184 | let b: i64x2 = i64x2::new(2, 0); | |
17185 | let e: i64x2 = i64x2::new(1, 2); | |
17186 | let r: i64x2 = transmute(vuzp1q_s64(transmute(a), transmute(b))); | |
ba9703b0 XL |
17187 | assert_eq!(r, e); |
17188 | } | |
17189 | ||
17190 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17191 | unsafe fn test_vuzp1_u32() { |
17192 | let a: u32x2 = u32x2::new(1, 0); | |
17193 | let b: u32x2 = u32x2::new(2, 0); | |
17194 | let e: u32x2 = u32x2::new(1, 2); | |
17195 | let r: u32x2 = transmute(vuzp1_u32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17196 | assert_eq!(r, e); |
17197 | } | |
17198 | ||
17199 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17200 | unsafe fn test_vuzp1q_u64() { |
17201 | let a: u64x2 = u64x2::new(1, 0); | |
17202 | let b: u64x2 = u64x2::new(2, 0); | |
17203 | let e: u64x2 = u64x2::new(1, 2); | |
17204 | let r: u64x2 = transmute(vuzp1q_u64(transmute(a), transmute(b))); | |
ba9703b0 XL |
17205 | assert_eq!(r, e); |
17206 | } | |
17207 | ||
17208 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17209 | unsafe fn test_vuzp1q_p64() { |
17210 | let a: i64x2 = i64x2::new(1, 0); | |
17211 | let b: i64x2 = i64x2::new(2, 0); | |
17212 | let e: i64x2 = i64x2::new(1, 2); | |
17213 | let r: i64x2 = transmute(vuzp1q_p64(transmute(a), transmute(b))); | |
ba9703b0 XL |
17214 | assert_eq!(r, e); |
17215 | } | |
17216 | ||
17217 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17218 | unsafe fn test_vuzp1q_f32() { |
17219 | let a: f32x4 = f32x4::new(0., 8., 1., 9.); | |
17220 | let b: f32x4 = f32x4::new(1., 10., 3., 11.); | |
17221 | let e: f32x4 = f32x4::new(0., 1., 1., 3.); | |
17222 | let r: f32x4 = transmute(vuzp1q_f32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17223 | assert_eq!(r, e); |
17224 | } | |
17225 | ||
17226 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17227 | unsafe fn test_vuzp1_f32() { |
17228 | let a: f32x2 = f32x2::new(0., 8.); | |
17229 | let b: f32x2 = f32x2::new(1., 10.); | |
17230 | let e: f32x2 = f32x2::new(0., 1.); | |
17231 | let r: f32x2 = transmute(vuzp1_f32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17232 | assert_eq!(r, e); |
17233 | } | |
17234 | ||
17235 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17236 | unsafe fn test_vuzp1q_f64() { |
17237 | let a: f64x2 = f64x2::new(0., 8.); | |
17238 | let b: f64x2 = f64x2::new(1., 10.); | |
17239 | let e: f64x2 = f64x2::new(0., 1.); | |
17240 | let r: f64x2 = transmute(vuzp1q_f64(transmute(a), transmute(b))); | |
ba9703b0 XL |
17241 | assert_eq!(r, e); |
17242 | } | |
17243 | ||
17244 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17245 | unsafe fn test_vuzp2_s8() { |
17246 | let a: i8x8 = i8x8::new(0, 17, 0, 18, 0, 18, 0, 19); | |
17247 | let b: i8x8 = i8x8::new(0, 18, 0, 19, 0, 23, 0, 24); | |
17248 | let e: i8x8 = i8x8::new(17, 18, 18, 19, 18, 19, 23, 24); | |
17249 | let r: i8x8 = transmute(vuzp2_s8(transmute(a), transmute(b))); | |
ba9703b0 XL |
17250 | assert_eq!(r, e); |
17251 | } | |
17252 | ||
17253 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17254 | unsafe fn test_vuzp2q_s8() { |
17255 | let a: i8x16 = i8x16::new(0, 17, 0, 18, 0, 18, 0, 19, 0, 18, 0, 19, 0, 23, 0, 24); | |
17256 | let b: i8x16 = i8x16::new(0, 18, 0, 19, 0, 23, 0, 24, 0, 29, 0, 30, 0, 31, 0, 32); | |
17257 | let e: i8x16 = i8x16::new(17, 18, 18, 19, 18, 19, 23, 24, 18, 19, 23, 24, 29, 30, 31, 32); | |
17258 | let r: i8x16 = transmute(vuzp2q_s8(transmute(a), transmute(b))); | |
ba9703b0 XL |
17259 | assert_eq!(r, e); |
17260 | } | |
17261 | ||
17262 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17263 | unsafe fn test_vuzp2_s16() { |
17264 | let a: i16x4 = i16x4::new(0, 17, 0, 18); | |
17265 | let b: i16x4 = i16x4::new(0, 18, 0, 19); | |
17266 | let e: i16x4 = i16x4::new(17, 18, 18, 19); | |
17267 | let r: i16x4 = transmute(vuzp2_s16(transmute(a), transmute(b))); | |
ba9703b0 XL |
17268 | assert_eq!(r, e); |
17269 | } | |
17270 | ||
17271 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17272 | unsafe fn test_vuzp2q_s16() { |
17273 | let a: i16x8 = i16x8::new(0, 17, 0, 18, 0, 18, 0, 19); | |
17274 | let b: i16x8 = i16x8::new(0, 18, 0, 19, 0, 23, 0, 24); | |
17275 | let e: i16x8 = i16x8::new(17, 18, 18, 19, 18, 19, 23, 24); | |
17276 | let r: i16x8 = transmute(vuzp2q_s16(transmute(a), transmute(b))); | |
ba9703b0 XL |
17277 | assert_eq!(r, e); |
17278 | } | |
17279 | ||
17280 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17281 | unsafe fn test_vuzp2q_s32() { |
17282 | let a: i32x4 = i32x4::new(0, 17, 0, 18); | |
17283 | let b: i32x4 = i32x4::new(0, 18, 0, 19); | |
17284 | let e: i32x4 = i32x4::new(17, 18, 18, 19); | |
17285 | let r: i32x4 = transmute(vuzp2q_s32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17286 | assert_eq!(r, e); |
17287 | } | |
17288 | ||
17289 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17290 | unsafe fn test_vuzp2_u8() { |
17291 | let a: u8x8 = u8x8::new(0, 17, 0, 18, 0, 18, 0, 19); | |
17292 | let b: u8x8 = u8x8::new(0, 18, 0, 19, 0, 23, 0, 24); | |
17293 | let e: u8x8 = u8x8::new(17, 18, 18, 19, 18, 19, 23, 24); | |
17294 | let r: u8x8 = transmute(vuzp2_u8(transmute(a), transmute(b))); | |
ba9703b0 XL |
17295 | assert_eq!(r, e); |
17296 | } | |
17297 | ||
17298 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17299 | unsafe fn test_vuzp2q_u8() { |
17300 | let a: u8x16 = u8x16::new(0, 17, 0, 18, 0, 18, 0, 19, 0, 18, 0, 19, 0, 23, 0, 24); | |
17301 | let b: u8x16 = u8x16::new(0, 18, 0, 19, 0, 23, 0, 24, 0, 29, 0, 30, 0, 31, 0, 32); | |
17302 | let e: u8x16 = u8x16::new(17, 18, 18, 19, 18, 19, 23, 24, 18, 19, 23, 24, 29, 30, 31, 32); | |
17303 | let r: u8x16 = transmute(vuzp2q_u8(transmute(a), transmute(b))); | |
ba9703b0 XL |
17304 | assert_eq!(r, e); |
17305 | } | |
17306 | ||
17307 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17308 | unsafe fn test_vuzp2_u16() { |
17309 | let a: u16x4 = u16x4::new(0, 17, 0, 18); | |
17310 | let b: u16x4 = u16x4::new(0, 18, 0, 19); | |
17311 | let e: u16x4 = u16x4::new(17, 18, 18, 19); | |
17312 | let r: u16x4 = transmute(vuzp2_u16(transmute(a), transmute(b))); | |
ba9703b0 XL |
17313 | assert_eq!(r, e); |
17314 | } | |
17315 | ||
17316 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17317 | unsafe fn test_vuzp2q_u16() { |
17318 | let a: u16x8 = u16x8::new(0, 17, 0, 18, 0, 18, 0, 19); | |
17319 | let b: u16x8 = u16x8::new(0, 18, 0, 19, 0, 23, 0, 24); | |
17320 | let e: u16x8 = u16x8::new(17, 18, 18, 19, 18, 19, 23, 24); | |
17321 | let r: u16x8 = transmute(vuzp2q_u16(transmute(a), transmute(b))); | |
ba9703b0 XL |
17322 | assert_eq!(r, e); |
17323 | } | |
17324 | ||
17325 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17326 | unsafe fn test_vuzp2q_u32() { |
17327 | let a: u32x4 = u32x4::new(0, 17, 0, 18); | |
17328 | let b: u32x4 = u32x4::new(0, 18, 0, 19); | |
17329 | let e: u32x4 = u32x4::new(17, 18, 18, 19); | |
17330 | let r: u32x4 = transmute(vuzp2q_u32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17331 | assert_eq!(r, e); |
17332 | } | |
17333 | ||
17334 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17335 | unsafe fn test_vuzp2_p8() { |
17336 | let a: i8x8 = i8x8::new(0, 17, 0, 18, 0, 18, 0, 19); | |
17337 | let b: i8x8 = i8x8::new(0, 18, 0, 19, 0, 23, 0, 24); | |
17338 | let e: i8x8 = i8x8::new(17, 18, 18, 19, 18, 19, 23, 24); | |
17339 | let r: i8x8 = transmute(vuzp2_p8(transmute(a), transmute(b))); | |
ba9703b0 XL |
17340 | assert_eq!(r, e); |
17341 | } | |
17342 | ||
17343 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17344 | unsafe fn test_vuzp2q_p8() { |
17345 | let a: i8x16 = i8x16::new(0, 17, 0, 18, 0, 18, 0, 19, 0, 18, 0, 19, 0, 23, 0, 24); | |
17346 | let b: i8x16 = i8x16::new(0, 18, 0, 19, 0, 23, 0, 24, 0, 29, 0, 30, 0, 31, 0, 32); | |
17347 | let e: i8x16 = i8x16::new(17, 18, 18, 19, 18, 19, 23, 24, 18, 19, 23, 24, 29, 30, 31, 32); | |
17348 | let r: i8x16 = transmute(vuzp2q_p8(transmute(a), transmute(b))); | |
ba9703b0 XL |
17349 | assert_eq!(r, e); |
17350 | } | |
17351 | ||
17352 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17353 | unsafe fn test_vuzp2_p16() { |
17354 | let a: i16x4 = i16x4::new(0, 17, 0, 18); | |
17355 | let b: i16x4 = i16x4::new(0, 18, 0, 19); | |
17356 | let e: i16x4 = i16x4::new(17, 18, 18, 19); | |
17357 | let r: i16x4 = transmute(vuzp2_p16(transmute(a), transmute(b))); | |
ba9703b0 XL |
17358 | assert_eq!(r, e); |
17359 | } | |
17360 | ||
17361 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17362 | unsafe fn test_vuzp2q_p16() { |
17363 | let a: i16x8 = i16x8::new(0, 17, 0, 18, 0, 18, 0, 19); | |
17364 | let b: i16x8 = i16x8::new(0, 18, 0, 19, 0, 23, 0, 24); | |
17365 | let e: i16x8 = i16x8::new(17, 18, 18, 19, 18, 19, 23, 24); | |
17366 | let r: i16x8 = transmute(vuzp2q_p16(transmute(a), transmute(b))); | |
ba9703b0 XL |
17367 | assert_eq!(r, e); |
17368 | } | |
17369 | ||
17370 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17371 | unsafe fn test_vuzp2_s32() { |
17372 | let a: i32x2 = i32x2::new(0, 17); | |
17373 | let b: i32x2 = i32x2::new(0, 18); | |
17374 | let e: i32x2 = i32x2::new(17, 18); | |
17375 | let r: i32x2 = transmute(vuzp2_s32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17376 | assert_eq!(r, e); |
17377 | } | |
17378 | ||
17379 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17380 | unsafe fn test_vuzp2q_s64() { |
17381 | let a: i64x2 = i64x2::new(0, 17); | |
17382 | let b: i64x2 = i64x2::new(0, 18); | |
17383 | let e: i64x2 = i64x2::new(17, 18); | |
17384 | let r: i64x2 = transmute(vuzp2q_s64(transmute(a), transmute(b))); | |
ba9703b0 XL |
17385 | assert_eq!(r, e); |
17386 | } | |
17387 | ||
17388 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17389 | unsafe fn test_vuzp2_u32() { |
17390 | let a: u32x2 = u32x2::new(0, 17); | |
17391 | let b: u32x2 = u32x2::new(0, 18); | |
17392 | let e: u32x2 = u32x2::new(17, 18); | |
17393 | let r: u32x2 = transmute(vuzp2_u32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17394 | assert_eq!(r, e); |
17395 | } | |
fc512014 XL |
17396 | |
17397 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17398 | unsafe fn test_vuzp2q_u64() { |
17399 | let a: u64x2 = u64x2::new(0, 17); | |
17400 | let b: u64x2 = u64x2::new(0, 18); | |
17401 | let e: u64x2 = u64x2::new(17, 18); | |
17402 | let r: u64x2 = transmute(vuzp2q_u64(transmute(a), transmute(b))); | |
fc512014 XL |
17403 | assert_eq!(r, e); |
17404 | } | |
17405 | ||
17406 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17407 | unsafe fn test_vuzp2q_p64() { |
17408 | let a: i64x2 = i64x2::new(0, 17); | |
17409 | let b: i64x2 = i64x2::new(0, 18); | |
17410 | let e: i64x2 = i64x2::new(17, 18); | |
17411 | let r: i64x2 = transmute(vuzp2q_p64(transmute(a), transmute(b))); | |
fc512014 XL |
17412 | assert_eq!(r, e); |
17413 | } | |
17414 | ||
17415 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17416 | unsafe fn test_vuzp2q_f32() { |
17417 | let a: f32x4 = f32x4::new(0., 8., 1., 9.); | |
17418 | let b: f32x4 = f32x4::new(2., 9., 3., 11.); | |
17419 | let e: f32x4 = f32x4::new(8., 9., 9., 11.); | |
17420 | let r: f32x4 = transmute(vuzp2q_f32(transmute(a), transmute(b))); | |
fc512014 XL |
17421 | assert_eq!(r, e); |
17422 | } | |
17423 | ||
17424 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17425 | unsafe fn test_vuzp2_f32() { |
17426 | let a: f32x2 = f32x2::new(0., 8.); | |
17427 | let b: f32x2 = f32x2::new(2., 9.); | |
17428 | let e: f32x2 = f32x2::new(8., 9.); | |
17429 | let r: f32x2 = transmute(vuzp2_f32(transmute(a), transmute(b))); | |
17430 | assert_eq!(r, e); | |
17431 | } | |
17432 | ||
17433 | #[simd_test(enable = "neon")] | |
17434 | unsafe fn test_vuzp2q_f64() { | |
17435 | let a: f64x2 = f64x2::new(0., 8.); | |
17436 | let b: f64x2 = f64x2::new(2., 9.); | |
17437 | let e: f64x2 = f64x2::new(8., 9.); | |
17438 | let r: f64x2 = transmute(vuzp2q_f64(transmute(a), transmute(b))); | |
17439 | assert_eq!(r, e); | |
17440 | } | |
17441 | ||
17442 | #[simd_test(enable = "neon")] | |
17443 | unsafe fn test_vabal_high_u8() { | |
17444 | let a: u16x8 = u16x8::new(9, 10, 11, 12, 13, 14, 15, 16); | |
17445 | let b: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
17446 | let c: u8x16 = u8x16::new(10, 10, 10, 10, 10, 10, 10, 10, 20, 0, 2, 4, 6, 8, 10, 12); | |
17447 | let e: u16x8 = u16x8::new(20, 20, 20, 20, 20, 20, 20, 20); | |
17448 | let r: u16x8 = transmute(vabal_high_u8(transmute(a), transmute(b), transmute(c))); | |
17449 | assert_eq!(r, e); | |
17450 | } | |
17451 | ||
17452 | #[simd_test(enable = "neon")] | |
17453 | unsafe fn test_vabal_high_u16() { | |
17454 | let a: u32x4 = u32x4::new(9, 10, 11, 12); | |
17455 | let b: u16x8 = u16x8::new(1, 2, 3, 4, 9, 10, 11, 12); | |
17456 | let c: u16x8 = u16x8::new(10, 10, 10, 10, 20, 0, 2, 4); | |
17457 | let e: u32x4 = u32x4::new(20, 20, 20, 20); | |
17458 | let r: u32x4 = transmute(vabal_high_u16(transmute(a), transmute(b), transmute(c))); | |
17459 | assert_eq!(r, e); | |
17460 | } | |
17461 | ||
17462 | #[simd_test(enable = "neon")] | |
17463 | unsafe fn test_vabal_high_u32() { | |
17464 | let a: u64x2 = u64x2::new(15, 16); | |
17465 | let b: u32x4 = u32x4::new(1, 2, 15, 16); | |
17466 | let c: u32x4 = u32x4::new(10, 10, 10, 12); | |
17467 | let e: u64x2 = u64x2::new(20, 20); | |
17468 | let r: u64x2 = transmute(vabal_high_u32(transmute(a), transmute(b), transmute(c))); | |
17469 | assert_eq!(r, e); | |
17470 | } | |
17471 | ||
17472 | #[simd_test(enable = "neon")] | |
17473 | unsafe fn test_vabal_high_s8() { | |
17474 | let a: i16x8 = i16x8::new(9, 10, 11, 12, 13, 14, 15, 16); | |
17475 | let b: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
17476 | let c: i8x16 = i8x16::new(10, 10, 10, 10, 10, 10, 10, 10, 20, 0, 2, 4, 6, 8, 10, 12); | |
17477 | let e: i16x8 = i16x8::new(20, 20, 20, 20, 20, 20, 20, 20); | |
17478 | let r: i16x8 = transmute(vabal_high_s8(transmute(a), transmute(b), transmute(c))); | |
17479 | assert_eq!(r, e); | |
17480 | } | |
17481 | ||
17482 | #[simd_test(enable = "neon")] | |
17483 | unsafe fn test_vabal_high_s16() { | |
17484 | let a: i32x4 = i32x4::new(9, 10, 11, 12); | |
17485 | let b: i16x8 = i16x8::new(1, 2, 3, 4, 9, 10, 11, 12); | |
17486 | let c: i16x8 = i16x8::new(10, 10, 10, 10, 20, 0, 2, 4); | |
17487 | let e: i32x4 = i32x4::new(20, 20, 20, 20); | |
17488 | let r: i32x4 = transmute(vabal_high_s16(transmute(a), transmute(b), transmute(c))); | |
17489 | assert_eq!(r, e); | |
17490 | } | |
17491 | ||
17492 | #[simd_test(enable = "neon")] | |
17493 | unsafe fn test_vabal_high_s32() { | |
17494 | let a: i64x2 = i64x2::new(15, 16); | |
17495 | let b: i32x4 = i32x4::new(1, 2, 15, 16); | |
17496 | let c: i32x4 = i32x4::new(10, 10, 10, 12); | |
17497 | let e: i64x2 = i64x2::new(20, 20); | |
17498 | let r: i64x2 = transmute(vabal_high_s32(transmute(a), transmute(b), transmute(c))); | |
17499 | assert_eq!(r, e); | |
17500 | } | |
17501 | ||
17502 | #[simd_test(enable = "neon")] | |
17503 | unsafe fn test_vqabs_s64() { | |
17504 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
17505 | let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); | |
17506 | let r: i64x1 = transmute(vqabs_s64(transmute(a))); | |
17507 | assert_eq!(r, e); | |
17508 | } | |
17509 | ||
17510 | #[simd_test(enable = "neon")] | |
17511 | unsafe fn test_vqabsq_s64() { | |
17512 | let a: i64x2 = i64x2::new(-9223372036854775808, -7); | |
17513 | let e: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 7); | |
17514 | let r: i64x2 = transmute(vqabsq_s64(transmute(a))); | |
fc512014 XL |
17515 | assert_eq!(r, e); |
17516 | } | |
ba9703b0 | 17517 | } |