]>
Commit | Line | Data |
---|---|---|
ba9703b0 XL |
1 | // This code is automatically generated. DO NOT MODIFY. |
2 | // | |
3 | // Instead, modify `crates/stdarch-gen/neon.spec` and run the following command to re-generate this file: | |
4 | // | |
5 | // ``` | |
6 | // OUT_DIR=`pwd`/crates/core_arch cargo run -p stdarch-gen -- crates/stdarch-gen/neon.spec | |
7 | // ``` | |
8 | use super::*; | |
9 | #[cfg(test)] | |
10 | use stdarch_test::assert_instr; | |
11 | ||
17df50a5 XL |
12 | /// Absolute difference between the arguments of Floating |
13 | #[inline] | |
14 | #[target_feature(enable = "neon")] | |
15 | #[cfg_attr(test, assert_instr(fabd))] | |
16 | pub unsafe fn vabd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
17 | #[allow(improper_ctypes)] | |
18 | extern "C" { | |
19 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fabd.v1f64")] | |
20 | fn vabd_f64_(a: float64x1_t, b: float64x1_t) -> float64x1_t; | |
21 | } | |
22 | vabd_f64_(a, b) | |
23 | } | |
24 | ||
25 | /// Absolute difference between the arguments of Floating | |
26 | #[inline] | |
27 | #[target_feature(enable = "neon")] | |
28 | #[cfg_attr(test, assert_instr(fabd))] | |
29 | pub unsafe fn vabdq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
30 | #[allow(improper_ctypes)] | |
31 | extern "C" { | |
32 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fabd.v2f64")] | |
33 | fn vabdq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; | |
34 | } | |
35 | vabdq_f64_(a, b) | |
36 | } | |
37 | ||
38 | /// Unsigned Absolute difference Long | |
39 | #[inline] | |
40 | #[target_feature(enable = "neon")] | |
41 | #[cfg_attr(test, assert_instr(uabdl))] | |
42 | pub unsafe fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { | |
43 | let c: uint8x8_t = simd_shuffle8!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); | |
44 | let d: uint8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
45 | simd_cast(vabd_u8(c, d)) | |
46 | } | |
47 | ||
48 | /// Unsigned Absolute difference Long | |
49 | #[inline] | |
50 | #[target_feature(enable = "neon")] | |
51 | #[cfg_attr(test, assert_instr(uabdl))] | |
52 | pub unsafe fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { | |
53 | let c: uint16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
54 | let d: uint16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
55 | simd_cast(vabd_u16(c, d)) | |
56 | } | |
57 | ||
58 | /// Unsigned Absolute difference Long | |
59 | #[inline] | |
60 | #[target_feature(enable = "neon")] | |
61 | #[cfg_attr(test, assert_instr(uabdl))] | |
62 | pub unsafe fn vabdl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { | |
63 | let c: uint32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
64 | let d: uint32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
65 | simd_cast(vabd_u32(c, d)) | |
66 | } | |
67 | ||
68 | /// Signed Absolute difference Long | |
69 | #[inline] | |
70 | #[target_feature(enable = "neon")] | |
71 | #[cfg_attr(test, assert_instr(sabdl))] | |
72 | pub unsafe fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { | |
73 | let c: int8x8_t = simd_shuffle8!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); | |
74 | let d: int8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
75 | let e: uint8x8_t = simd_cast(vabd_s8(c, d)); | |
76 | simd_cast(e) | |
77 | } | |
78 | ||
79 | /// Signed Absolute difference Long | |
80 | #[inline] | |
81 | #[target_feature(enable = "neon")] | |
82 | #[cfg_attr(test, assert_instr(sabdl))] | |
83 | pub unsafe fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { | |
84 | let c: int16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
85 | let d: int16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
86 | let e: uint16x4_t = simd_cast(vabd_s16(c, d)); | |
87 | simd_cast(e) | |
88 | } | |
89 | ||
90 | /// Signed Absolute difference Long | |
91 | #[inline] | |
92 | #[target_feature(enable = "neon")] | |
93 | #[cfg_attr(test, assert_instr(sabdl))] | |
94 | pub unsafe fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { | |
95 | let c: int32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
96 | let d: int32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
97 | let e: uint32x2_t = simd_cast(vabd_s32(c, d)); | |
98 | simd_cast(e) | |
99 | } | |
100 | ||
ba9703b0 XL |
101 | /// Compare bitwise Equal (vector) |
102 | #[inline] | |
103 | #[target_feature(enable = "neon")] | |
104 | #[cfg_attr(test, assert_instr(cmeq))] | |
105 | pub unsafe fn vceq_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { | |
106 | simd_eq(a, b) | |
107 | } | |
108 | ||
109 | /// Compare bitwise Equal (vector) | |
110 | #[inline] | |
111 | #[target_feature(enable = "neon")] | |
112 | #[cfg_attr(test, assert_instr(cmeq))] | |
113 | pub unsafe fn vceqq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
114 | simd_eq(a, b) | |
115 | } | |
116 | ||
117 | /// Compare bitwise Equal (vector) | |
118 | #[inline] | |
119 | #[target_feature(enable = "neon")] | |
120 | #[cfg_attr(test, assert_instr(cmeq))] | |
121 | pub unsafe fn vceq_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { | |
122 | simd_eq(a, b) | |
123 | } | |
124 | ||
125 | /// Compare bitwise Equal (vector) | |
126 | #[inline] | |
127 | #[target_feature(enable = "neon")] | |
128 | #[cfg_attr(test, assert_instr(cmeq))] | |
129 | pub unsafe fn vceqq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { | |
130 | simd_eq(a, b) | |
131 | } | |
132 | ||
133 | /// Compare bitwise Equal (vector) | |
134 | #[inline] | |
135 | #[target_feature(enable = "neon")] | |
136 | #[cfg_attr(test, assert_instr(cmeq))] | |
137 | pub unsafe fn vceq_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t { | |
138 | simd_eq(a, b) | |
139 | } | |
140 | ||
141 | /// Compare bitwise Equal (vector) | |
142 | #[inline] | |
143 | #[target_feature(enable = "neon")] | |
144 | #[cfg_attr(test, assert_instr(cmeq))] | |
145 | pub unsafe fn vceqq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t { | |
146 | simd_eq(a, b) | |
147 | } | |
148 | ||
149 | /// Floating-point compare equal | |
150 | #[inline] | |
151 | #[target_feature(enable = "neon")] | |
152 | #[cfg_attr(test, assert_instr(fcmeq))] | |
153 | pub unsafe fn vceq_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { | |
154 | simd_eq(a, b) | |
155 | } | |
156 | ||
157 | /// Floating-point compare equal | |
158 | #[inline] | |
159 | #[target_feature(enable = "neon")] | |
160 | #[cfg_attr(test, assert_instr(fcmeq))] | |
161 | pub unsafe fn vceqq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { | |
162 | simd_eq(a, b) | |
163 | } | |
164 | ||
17df50a5 XL |
165 | /// Signed compare bitwise equal to zero |
166 | #[inline] | |
167 | #[target_feature(enable = "neon")] | |
168 | #[cfg_attr(test, assert_instr(cmeq))] | |
169 | pub unsafe fn vceqz_s8(a: int8x8_t) -> uint8x8_t { | |
170 | let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
171 | simd_eq(a, transmute(b)) | |
172 | } | |
173 | ||
174 | /// Signed compare bitwise equal to zero | |
175 | #[inline] | |
176 | #[target_feature(enable = "neon")] | |
177 | #[cfg_attr(test, assert_instr(cmeq))] | |
178 | pub unsafe fn vceqzq_s8(a: int8x16_t) -> uint8x16_t { | |
179 | let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
180 | simd_eq(a, transmute(b)) | |
181 | } | |
182 | ||
183 | /// Signed compare bitwise equal to zero | |
184 | #[inline] | |
185 | #[target_feature(enable = "neon")] | |
186 | #[cfg_attr(test, assert_instr(cmeq))] | |
187 | pub unsafe fn vceqz_s16(a: int16x4_t) -> uint16x4_t { | |
188 | let b: i16x4 = i16x4::new(0, 0, 0, 0); | |
189 | simd_eq(a, transmute(b)) | |
190 | } | |
191 | ||
192 | /// Signed compare bitwise equal to zero | |
193 | #[inline] | |
194 | #[target_feature(enable = "neon")] | |
195 | #[cfg_attr(test, assert_instr(cmeq))] | |
196 | pub unsafe fn vceqzq_s16(a: int16x8_t) -> uint16x8_t { | |
197 | let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
198 | simd_eq(a, transmute(b)) | |
199 | } | |
200 | ||
201 | /// Signed compare bitwise equal to zero | |
202 | #[inline] | |
203 | #[target_feature(enable = "neon")] | |
204 | #[cfg_attr(test, assert_instr(cmeq))] | |
205 | pub unsafe fn vceqz_s32(a: int32x2_t) -> uint32x2_t { | |
206 | let b: i32x2 = i32x2::new(0, 0); | |
207 | simd_eq(a, transmute(b)) | |
208 | } | |
209 | ||
210 | /// Signed compare bitwise equal to zero | |
211 | #[inline] | |
212 | #[target_feature(enable = "neon")] | |
213 | #[cfg_attr(test, assert_instr(cmeq))] | |
214 | pub unsafe fn vceqzq_s32(a: int32x4_t) -> uint32x4_t { | |
215 | let b: i32x4 = i32x4::new(0, 0, 0, 0); | |
216 | simd_eq(a, transmute(b)) | |
217 | } | |
218 | ||
219 | /// Signed compare bitwise equal to zero | |
220 | #[inline] | |
221 | #[target_feature(enable = "neon")] | |
222 | #[cfg_attr(test, assert_instr(cmeq))] | |
223 | pub unsafe fn vceqz_s64(a: int64x1_t) -> uint64x1_t { | |
224 | let b: i64x1 = i64x1::new(0); | |
225 | simd_eq(a, transmute(b)) | |
226 | } | |
227 | ||
228 | /// Signed compare bitwise equal to zero | |
229 | #[inline] | |
230 | #[target_feature(enable = "neon")] | |
231 | #[cfg_attr(test, assert_instr(cmeq))] | |
232 | pub unsafe fn vceqzq_s64(a: int64x2_t) -> uint64x2_t { | |
233 | let b: i64x2 = i64x2::new(0, 0); | |
234 | simd_eq(a, transmute(b)) | |
235 | } | |
236 | ||
237 | /// Signed compare bitwise equal to zero | |
238 | #[inline] | |
239 | #[target_feature(enable = "neon")] | |
240 | #[cfg_attr(test, assert_instr(cmeq))] | |
241 | pub unsafe fn vceqz_p8(a: poly8x8_t) -> uint8x8_t { | |
242 | let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
243 | simd_eq(a, transmute(b)) | |
244 | } | |
245 | ||
246 | /// Signed compare bitwise equal to zero | |
247 | #[inline] | |
248 | #[target_feature(enable = "neon")] | |
249 | #[cfg_attr(test, assert_instr(cmeq))] | |
250 | pub unsafe fn vceqzq_p8(a: poly8x16_t) -> uint8x16_t { | |
251 | let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
252 | simd_eq(a, transmute(b)) | |
253 | } | |
254 | ||
255 | /// Signed compare bitwise equal to zero | |
256 | #[inline] | |
257 | #[target_feature(enable = "neon")] | |
258 | #[cfg_attr(test, assert_instr(cmeq))] | |
259 | pub unsafe fn vceqz_p64(a: poly64x1_t) -> uint64x1_t { | |
260 | let b: i64x1 = i64x1::new(0); | |
261 | simd_eq(a, transmute(b)) | |
262 | } | |
263 | ||
264 | /// Signed compare bitwise equal to zero | |
265 | #[inline] | |
266 | #[target_feature(enable = "neon")] | |
267 | #[cfg_attr(test, assert_instr(cmeq))] | |
268 | pub unsafe fn vceqzq_p64(a: poly64x2_t) -> uint64x2_t { | |
269 | let b: i64x2 = i64x2::new(0, 0); | |
270 | simd_eq(a, transmute(b)) | |
271 | } | |
272 | ||
273 | /// Unsigned compare bitwise equal to zero | |
274 | #[inline] | |
275 | #[target_feature(enable = "neon")] | |
276 | #[cfg_attr(test, assert_instr(cmeq))] | |
277 | pub unsafe fn vceqz_u8(a: uint8x8_t) -> uint8x8_t { | |
278 | let b: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
279 | simd_eq(a, transmute(b)) | |
280 | } | |
281 | ||
282 | /// Unsigned compare bitwise equal to zero | |
283 | #[inline] | |
284 | #[target_feature(enable = "neon")] | |
285 | #[cfg_attr(test, assert_instr(cmeq))] | |
286 | pub unsafe fn vceqzq_u8(a: uint8x16_t) -> uint8x16_t { | |
287 | let b: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
288 | simd_eq(a, transmute(b)) | |
289 | } | |
290 | ||
291 | /// Unsigned compare bitwise equal to zero | |
292 | #[inline] | |
293 | #[target_feature(enable = "neon")] | |
294 | #[cfg_attr(test, assert_instr(cmeq))] | |
295 | pub unsafe fn vceqz_u16(a: uint16x4_t) -> uint16x4_t { | |
296 | let b: u16x4 = u16x4::new(0, 0, 0, 0); | |
297 | simd_eq(a, transmute(b)) | |
298 | } | |
299 | ||
300 | /// Unsigned compare bitwise equal to zero | |
301 | #[inline] | |
302 | #[target_feature(enable = "neon")] | |
303 | #[cfg_attr(test, assert_instr(cmeq))] | |
304 | pub unsafe fn vceqzq_u16(a: uint16x8_t) -> uint16x8_t { | |
305 | let b: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
306 | simd_eq(a, transmute(b)) | |
307 | } | |
308 | ||
309 | /// Unsigned compare bitwise equal to zero | |
310 | #[inline] | |
311 | #[target_feature(enable = "neon")] | |
312 | #[cfg_attr(test, assert_instr(cmeq))] | |
313 | pub unsafe fn vceqz_u32(a: uint32x2_t) -> uint32x2_t { | |
314 | let b: u32x2 = u32x2::new(0, 0); | |
315 | simd_eq(a, transmute(b)) | |
316 | } | |
317 | ||
318 | /// Unsigned compare bitwise equal to zero | |
319 | #[inline] | |
320 | #[target_feature(enable = "neon")] | |
321 | #[cfg_attr(test, assert_instr(cmeq))] | |
322 | pub unsafe fn vceqzq_u32(a: uint32x4_t) -> uint32x4_t { | |
323 | let b: u32x4 = u32x4::new(0, 0, 0, 0); | |
324 | simd_eq(a, transmute(b)) | |
325 | } | |
326 | ||
327 | /// Unsigned compare bitwise equal to zero | |
328 | #[inline] | |
329 | #[target_feature(enable = "neon")] | |
330 | #[cfg_attr(test, assert_instr(cmeq))] | |
331 | pub unsafe fn vceqz_u64(a: uint64x1_t) -> uint64x1_t { | |
332 | let b: u64x1 = u64x1::new(0); | |
333 | simd_eq(a, transmute(b)) | |
334 | } | |
335 | ||
336 | /// Unsigned compare bitwise equal to zero | |
337 | #[inline] | |
338 | #[target_feature(enable = "neon")] | |
339 | #[cfg_attr(test, assert_instr(cmeq))] | |
340 | pub unsafe fn vceqzq_u64(a: uint64x2_t) -> uint64x2_t { | |
341 | let b: u64x2 = u64x2::new(0, 0); | |
342 | simd_eq(a, transmute(b)) | |
343 | } | |
344 | ||
345 | /// Floating-point compare bitwise equal to zero | |
346 | #[inline] | |
347 | #[target_feature(enable = "neon")] | |
348 | #[cfg_attr(test, assert_instr(fcmeq))] | |
349 | pub unsafe fn vceqz_f32(a: float32x2_t) -> uint32x2_t { | |
350 | let b: f32x2 = f32x2::new(0.0, 0.0); | |
351 | simd_eq(a, transmute(b)) | |
352 | } | |
353 | ||
354 | /// Floating-point compare bitwise equal to zero | |
355 | #[inline] | |
356 | #[target_feature(enable = "neon")] | |
357 | #[cfg_attr(test, assert_instr(fcmeq))] | |
358 | pub unsafe fn vceqzq_f32(a: float32x4_t) -> uint32x4_t { | |
359 | let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); | |
360 | simd_eq(a, transmute(b)) | |
361 | } | |
362 | ||
363 | /// Floating-point compare bitwise equal to zero | |
364 | #[inline] | |
365 | #[target_feature(enable = "neon")] | |
366 | #[cfg_attr(test, assert_instr(fcmeq))] | |
367 | pub unsafe fn vceqz_f64(a: float64x1_t) -> uint64x1_t { | |
368 | let b: f64 = 0.0; | |
369 | simd_eq(a, transmute(b)) | |
370 | } | |
371 | ||
372 | /// Floating-point compare bitwise equal to zero | |
373 | #[inline] | |
374 | #[target_feature(enable = "neon")] | |
375 | #[cfg_attr(test, assert_instr(fcmeq))] | |
376 | pub unsafe fn vceqzq_f64(a: float64x2_t) -> uint64x2_t { | |
377 | let b: f64x2 = f64x2::new(0.0, 0.0); | |
378 | simd_eq(a, transmute(b)) | |
379 | } | |
380 | ||
381 | /// Signed compare bitwise Test bits nonzero | |
382 | #[inline] | |
383 | #[target_feature(enable = "neon")] | |
384 | #[cfg_attr(test, assert_instr(cmtst))] | |
385 | pub unsafe fn vtst_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { | |
386 | let c: int64x1_t = simd_and(a, b); | |
387 | let d: i64x1 = i64x1::new(0); | |
388 | simd_ne(c, transmute(d)) | |
389 | } | |
390 | ||
391 | /// Signed compare bitwise Test bits nonzero | |
392 | #[inline] | |
393 | #[target_feature(enable = "neon")] | |
394 | #[cfg_attr(test, assert_instr(cmtst))] | |
395 | pub unsafe fn vtstq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { | |
396 | let c: int64x2_t = simd_and(a, b); | |
397 | let d: i64x2 = i64x2::new(0, 0); | |
398 | simd_ne(c, transmute(d)) | |
399 | } | |
400 | ||
401 | /// Signed compare bitwise Test bits nonzero | |
402 | #[inline] | |
403 | #[target_feature(enable = "neon")] | |
404 | #[cfg_attr(test, assert_instr(cmtst))] | |
405 | pub unsafe fn vtst_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t { | |
406 | let c: poly64x1_t = simd_and(a, b); | |
407 | let d: i64x1 = i64x1::new(0); | |
408 | simd_ne(c, transmute(d)) | |
409 | } | |
410 | ||
411 | /// Signed compare bitwise Test bits nonzero | |
412 | #[inline] | |
413 | #[target_feature(enable = "neon")] | |
414 | #[cfg_attr(test, assert_instr(cmtst))] | |
415 | pub unsafe fn vtstq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t { | |
416 | let c: poly64x2_t = simd_and(a, b); | |
417 | let d: i64x2 = i64x2::new(0, 0); | |
418 | simd_ne(c, transmute(d)) | |
419 | } | |
420 | ||
421 | /// Unsigned compare bitwise Test bits nonzero | |
422 | #[inline] | |
423 | #[target_feature(enable = "neon")] | |
424 | #[cfg_attr(test, assert_instr(cmtst))] | |
425 | pub unsafe fn vtst_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { | |
426 | let c: uint64x1_t = simd_and(a, b); | |
427 | let d: u64x1 = u64x1::new(0); | |
428 | simd_ne(c, transmute(d)) | |
429 | } | |
430 | ||
431 | /// Unsigned compare bitwise Test bits nonzero | |
432 | #[inline] | |
433 | #[target_feature(enable = "neon")] | |
434 | #[cfg_attr(test, assert_instr(cmtst))] | |
435 | pub unsafe fn vtstq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
436 | let c: uint64x2_t = simd_and(a, b); | |
437 | let d: u64x2 = u64x2::new(0, 0); | |
438 | simd_ne(c, transmute(d)) | |
439 | } | |
440 | ||
441 | /// Floating-point absolute value | |
442 | #[inline] | |
443 | #[target_feature(enable = "neon")] | |
444 | #[cfg_attr(test, assert_instr(fabs))] | |
445 | pub unsafe fn vabs_f64(a: float64x1_t) -> float64x1_t { | |
446 | simd_fabs(a) | |
447 | } | |
448 | ||
449 | /// Floating-point absolute value | |
450 | #[inline] | |
451 | #[target_feature(enable = "neon")] | |
452 | #[cfg_attr(test, assert_instr(fabs))] | |
453 | pub unsafe fn vabsq_f64(a: float64x2_t) -> float64x2_t { | |
454 | simd_fabs(a) | |
455 | } | |
456 | ||
ba9703b0 XL |
457 | /// Compare signed greater than |
458 | #[inline] | |
459 | #[target_feature(enable = "neon")] | |
460 | #[cfg_attr(test, assert_instr(cmgt))] | |
461 | pub unsafe fn vcgt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { | |
462 | simd_gt(a, b) | |
463 | } | |
464 | ||
465 | /// Compare signed greater than | |
466 | #[inline] | |
467 | #[target_feature(enable = "neon")] | |
468 | #[cfg_attr(test, assert_instr(cmgt))] | |
469 | pub unsafe fn vcgtq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { | |
470 | simd_gt(a, b) | |
471 | } | |
472 | ||
473 | /// Compare unsigned highe | |
474 | #[inline] | |
475 | #[target_feature(enable = "neon")] | |
476 | #[cfg_attr(test, assert_instr(cmhi))] | |
477 | pub unsafe fn vcgt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { | |
478 | simd_gt(a, b) | |
479 | } | |
480 | ||
481 | /// Compare unsigned highe | |
482 | #[inline] | |
483 | #[target_feature(enable = "neon")] | |
484 | #[cfg_attr(test, assert_instr(cmhi))] | |
485 | pub unsafe fn vcgtq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
486 | simd_gt(a, b) | |
487 | } | |
488 | ||
489 | /// Floating-point compare greater than | |
490 | #[inline] | |
491 | #[target_feature(enable = "neon")] | |
492 | #[cfg_attr(test, assert_instr(fcmgt))] | |
493 | pub unsafe fn vcgt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { | |
494 | simd_gt(a, b) | |
495 | } | |
496 | ||
497 | /// Floating-point compare greater than | |
498 | #[inline] | |
499 | #[target_feature(enable = "neon")] | |
500 | #[cfg_attr(test, assert_instr(fcmgt))] | |
501 | pub unsafe fn vcgtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { | |
502 | simd_gt(a, b) | |
503 | } | |
504 | ||
505 | /// Compare signed less than | |
506 | #[inline] | |
507 | #[target_feature(enable = "neon")] | |
508 | #[cfg_attr(test, assert_instr(cmgt))] | |
509 | pub unsafe fn vclt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { | |
510 | simd_lt(a, b) | |
511 | } | |
512 | ||
513 | /// Compare signed less than | |
514 | #[inline] | |
515 | #[target_feature(enable = "neon")] | |
516 | #[cfg_attr(test, assert_instr(cmgt))] | |
517 | pub unsafe fn vcltq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { | |
518 | simd_lt(a, b) | |
519 | } | |
520 | ||
521 | /// Compare unsigned less than | |
522 | #[inline] | |
523 | #[target_feature(enable = "neon")] | |
524 | #[cfg_attr(test, assert_instr(cmhi))] | |
525 | pub unsafe fn vclt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { | |
526 | simd_lt(a, b) | |
527 | } | |
528 | ||
529 | /// Compare unsigned less than | |
530 | #[inline] | |
531 | #[target_feature(enable = "neon")] | |
532 | #[cfg_attr(test, assert_instr(cmhi))] | |
533 | pub unsafe fn vcltq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
534 | simd_lt(a, b) | |
535 | } | |
536 | ||
537 | /// Floating-point compare less than | |
538 | #[inline] | |
539 | #[target_feature(enable = "neon")] | |
540 | #[cfg_attr(test, assert_instr(fcmgt))] | |
541 | pub unsafe fn vclt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { | |
542 | simd_lt(a, b) | |
543 | } | |
544 | ||
545 | /// Floating-point compare less than | |
546 | #[inline] | |
547 | #[target_feature(enable = "neon")] | |
548 | #[cfg_attr(test, assert_instr(fcmgt))] | |
549 | pub unsafe fn vcltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { | |
550 | simd_lt(a, b) | |
551 | } | |
552 | ||
553 | /// Compare signed less than or equal | |
554 | #[inline] | |
555 | #[target_feature(enable = "neon")] | |
556 | #[cfg_attr(test, assert_instr(cmge))] | |
557 | pub unsafe fn vcle_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { | |
558 | simd_le(a, b) | |
559 | } | |
560 | ||
561 | /// Compare signed less than or equal | |
562 | #[inline] | |
563 | #[target_feature(enable = "neon")] | |
564 | #[cfg_attr(test, assert_instr(cmge))] | |
565 | pub unsafe fn vcleq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { | |
566 | simd_le(a, b) | |
567 | } | |
568 | ||
569 | /// Compare unsigned less than or equal | |
570 | #[inline] | |
571 | #[target_feature(enable = "neon")] | |
572 | #[cfg_attr(test, assert_instr(cmhs))] | |
573 | pub unsafe fn vcle_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { | |
574 | simd_le(a, b) | |
575 | } | |
576 | ||
577 | /// Compare unsigned less than or equal | |
578 | #[inline] | |
579 | #[target_feature(enable = "neon")] | |
580 | #[cfg_attr(test, assert_instr(cmhs))] | |
581 | pub unsafe fn vcleq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
582 | simd_le(a, b) | |
583 | } | |
584 | ||
585 | /// Floating-point compare less than or equal | |
586 | #[inline] | |
587 | #[target_feature(enable = "neon")] | |
588 | #[cfg_attr(test, assert_instr(fcmge))] | |
589 | pub unsafe fn vcle_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { | |
590 | simd_le(a, b) | |
591 | } | |
592 | ||
593 | /// Floating-point compare less than or equal | |
594 | #[inline] | |
595 | #[target_feature(enable = "neon")] | |
596 | #[cfg_attr(test, assert_instr(fcmge))] | |
597 | pub unsafe fn vcleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { | |
598 | simd_le(a, b) | |
599 | } | |
600 | ||
601 | /// Compare signed greater than or equal | |
602 | #[inline] | |
603 | #[target_feature(enable = "neon")] | |
604 | #[cfg_attr(test, assert_instr(cmge))] | |
605 | pub unsafe fn vcge_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { | |
606 | simd_ge(a, b) | |
607 | } | |
608 | ||
609 | /// Compare signed greater than or equal | |
610 | #[inline] | |
611 | #[target_feature(enable = "neon")] | |
612 | #[cfg_attr(test, assert_instr(cmge))] | |
613 | pub unsafe fn vcgeq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { | |
614 | simd_ge(a, b) | |
615 | } | |
616 | ||
617 | /// Compare unsigned greater than or equal | |
618 | #[inline] | |
619 | #[target_feature(enable = "neon")] | |
620 | #[cfg_attr(test, assert_instr(cmhs))] | |
621 | pub unsafe fn vcge_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { | |
622 | simd_ge(a, b) | |
623 | } | |
624 | ||
625 | /// Compare unsigned greater than or equal | |
626 | #[inline] | |
627 | #[target_feature(enable = "neon")] | |
628 | #[cfg_attr(test, assert_instr(cmhs))] | |
629 | pub unsafe fn vcgeq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
630 | simd_ge(a, b) | |
631 | } | |
632 | ||
633 | /// Floating-point compare greater than or equal | |
634 | #[inline] | |
635 | #[target_feature(enable = "neon")] | |
636 | #[cfg_attr(test, assert_instr(fcmge))] | |
637 | pub unsafe fn vcge_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { | |
638 | simd_ge(a, b) | |
639 | } | |
640 | ||
641 | /// Floating-point compare greater than or equal | |
642 | #[inline] | |
643 | #[target_feature(enable = "neon")] | |
644 | #[cfg_attr(test, assert_instr(fcmge))] | |
645 | pub unsafe fn vcgeq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { | |
646 | simd_ge(a, b) | |
647 | } | |
648 | ||
17df50a5 | 649 | /// Compare signed greater than or equal to zero |
ba9703b0 XL |
650 | #[inline] |
651 | #[target_feature(enable = "neon")] | |
17df50a5 XL |
652 | #[cfg_attr(test, assert_instr(cmge))] |
653 | pub unsafe fn vcgez_s8(a: int8x8_t) -> uint8x8_t { | |
654 | let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
655 | simd_ge(a, transmute(b)) | |
ba9703b0 XL |
656 | } |
657 | ||
17df50a5 | 658 | /// Compare signed greater than or equal to zero |
ba9703b0 XL |
659 | #[inline] |
660 | #[target_feature(enable = "neon")] | |
17df50a5 XL |
661 | #[cfg_attr(test, assert_instr(cmge))] |
662 | pub unsafe fn vcgezq_s8(a: int8x16_t) -> uint8x16_t { | |
663 | let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
664 | simd_ge(a, transmute(b)) | |
ba9703b0 XL |
665 | } |
666 | ||
17df50a5 | 667 | /// Compare signed greater than or equal to zero |
ba9703b0 XL |
668 | #[inline] |
669 | #[target_feature(enable = "neon")] | |
17df50a5 XL |
670 | #[cfg_attr(test, assert_instr(cmge))] |
671 | pub unsafe fn vcgez_s16(a: int16x4_t) -> uint16x4_t { | |
672 | let b: i16x4 = i16x4::new(0, 0, 0, 0); | |
673 | simd_ge(a, transmute(b)) | |
ba9703b0 XL |
674 | } |
675 | ||
17df50a5 | 676 | /// Compare signed greater than or equal to zero |
ba9703b0 XL |
677 | #[inline] |
678 | #[target_feature(enable = "neon")] | |
17df50a5 XL |
679 | #[cfg_attr(test, assert_instr(cmge))] |
680 | pub unsafe fn vcgezq_s16(a: int16x8_t) -> uint16x8_t { | |
681 | let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
682 | simd_ge(a, transmute(b)) | |
ba9703b0 XL |
683 | } |
684 | ||
17df50a5 | 685 | /// Compare signed greater than or equal to zero |
fc512014 XL |
686 | #[inline] |
687 | #[target_feature(enable = "neon")] | |
17df50a5 XL |
688 | #[cfg_attr(test, assert_instr(cmge))] |
689 | pub unsafe fn vcgez_s32(a: int32x2_t) -> uint32x2_t { | |
690 | let b: i32x2 = i32x2::new(0, 0); | |
691 | simd_ge(a, transmute(b)) | |
fc512014 XL |
692 | } |
693 | ||
17df50a5 | 694 | /// Compare signed greater than or equal to zero |
fc512014 XL |
695 | #[inline] |
696 | #[target_feature(enable = "neon")] | |
17df50a5 XL |
697 | #[cfg_attr(test, assert_instr(cmge))] |
698 | pub unsafe fn vcgezq_s32(a: int32x4_t) -> uint32x4_t { | |
699 | let b: i32x4 = i32x4::new(0, 0, 0, 0); | |
700 | simd_ge(a, transmute(b)) | |
fc512014 XL |
701 | } |
702 | ||
17df50a5 | 703 | /// Compare signed greater than or equal to zero |
fc512014 XL |
704 | #[inline] |
705 | #[target_feature(enable = "neon")] | |
17df50a5 XL |
706 | #[cfg_attr(test, assert_instr(cmge))] |
707 | pub unsafe fn vcgez_s64(a: int64x1_t) -> uint64x1_t { | |
708 | let b: i64x1 = i64x1::new(0); | |
709 | simd_ge(a, transmute(b)) | |
fc512014 XL |
710 | } |
711 | ||
17df50a5 | 712 | /// Compare signed greater than or equal to zero |
fc512014 XL |
713 | #[inline] |
714 | #[target_feature(enable = "neon")] | |
17df50a5 XL |
715 | #[cfg_attr(test, assert_instr(cmge))] |
716 | pub unsafe fn vcgezq_s64(a: int64x2_t) -> uint64x2_t { | |
717 | let b: i64x2 = i64x2::new(0, 0); | |
718 | simd_ge(a, transmute(b)) | |
fc512014 XL |
719 | } |
720 | ||
17df50a5 XL |
721 | /// Floating-point compare greater than or equal to zero |
722 | #[inline] | |
723 | #[target_feature(enable = "neon")] | |
724 | #[cfg_attr(test, assert_instr(fcmge))] | |
725 | pub unsafe fn vcgez_f32(a: float32x2_t) -> uint32x2_t { | |
726 | let b: f32x2 = f32x2::new(0.0, 0.0); | |
727 | simd_ge(a, transmute(b)) | |
728 | } | |
729 | ||
730 | /// Floating-point compare greater than or equal to zero | |
731 | #[inline] | |
732 | #[target_feature(enable = "neon")] | |
733 | #[cfg_attr(test, assert_instr(fcmge))] | |
734 | pub unsafe fn vcgezq_f32(a: float32x4_t) -> uint32x4_t { | |
735 | let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); | |
736 | simd_ge(a, transmute(b)) | |
737 | } | |
738 | ||
739 | /// Floating-point compare greater than or equal to zero | |
740 | #[inline] | |
741 | #[target_feature(enable = "neon")] | |
742 | #[cfg_attr(test, assert_instr(fcmge))] | |
743 | pub unsafe fn vcgez_f64(a: float64x1_t) -> uint64x1_t { | |
744 | let b: f64 = 0.0; | |
745 | simd_ge(a, transmute(b)) | |
746 | } | |
747 | ||
748 | /// Floating-point compare greater than or equal to zero | |
749 | #[inline] | |
750 | #[target_feature(enable = "neon")] | |
751 | #[cfg_attr(test, assert_instr(fcmge))] | |
752 | pub unsafe fn vcgezq_f64(a: float64x2_t) -> uint64x2_t { | |
753 | let b: f64x2 = f64x2::new(0.0, 0.0); | |
754 | simd_ge(a, transmute(b)) | |
755 | } | |
756 | ||
757 | /// Compare signed greater than zero | |
758 | #[inline] | |
759 | #[target_feature(enable = "neon")] | |
760 | #[cfg_attr(test, assert_instr(cmgt))] | |
761 | pub unsafe fn vcgtz_s8(a: int8x8_t) -> uint8x8_t { | |
762 | let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
763 | simd_gt(a, transmute(b)) | |
764 | } | |
765 | ||
766 | /// Compare signed greater than zero | |
767 | #[inline] | |
768 | #[target_feature(enable = "neon")] | |
769 | #[cfg_attr(test, assert_instr(cmgt))] | |
770 | pub unsafe fn vcgtzq_s8(a: int8x16_t) -> uint8x16_t { | |
771 | let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
772 | simd_gt(a, transmute(b)) | |
773 | } | |
774 | ||
775 | /// Compare signed greater than zero | |
776 | #[inline] | |
777 | #[target_feature(enable = "neon")] | |
778 | #[cfg_attr(test, assert_instr(cmgt))] | |
779 | pub unsafe fn vcgtz_s16(a: int16x4_t) -> uint16x4_t { | |
780 | let b: i16x4 = i16x4::new(0, 0, 0, 0); | |
781 | simd_gt(a, transmute(b)) | |
782 | } | |
783 | ||
784 | /// Compare signed greater than zero | |
785 | #[inline] | |
786 | #[target_feature(enable = "neon")] | |
787 | #[cfg_attr(test, assert_instr(cmgt))] | |
788 | pub unsafe fn vcgtzq_s16(a: int16x8_t) -> uint16x8_t { | |
789 | let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
790 | simd_gt(a, transmute(b)) | |
791 | } | |
792 | ||
793 | /// Compare signed greater than zero | |
794 | #[inline] | |
795 | #[target_feature(enable = "neon")] | |
796 | #[cfg_attr(test, assert_instr(cmgt))] | |
797 | pub unsafe fn vcgtz_s32(a: int32x2_t) -> uint32x2_t { | |
798 | let b: i32x2 = i32x2::new(0, 0); | |
799 | simd_gt(a, transmute(b)) | |
800 | } | |
801 | ||
802 | /// Compare signed greater than zero | |
803 | #[inline] | |
804 | #[target_feature(enable = "neon")] | |
805 | #[cfg_attr(test, assert_instr(cmgt))] | |
806 | pub unsafe fn vcgtzq_s32(a: int32x4_t) -> uint32x4_t { | |
807 | let b: i32x4 = i32x4::new(0, 0, 0, 0); | |
808 | simd_gt(a, transmute(b)) | |
809 | } | |
810 | ||
811 | /// Compare signed greater than zero | |
812 | #[inline] | |
813 | #[target_feature(enable = "neon")] | |
814 | #[cfg_attr(test, assert_instr(cmgt))] | |
815 | pub unsafe fn vcgtz_s64(a: int64x1_t) -> uint64x1_t { | |
816 | let b: i64x1 = i64x1::new(0); | |
817 | simd_gt(a, transmute(b)) | |
818 | } | |
819 | ||
820 | /// Compare signed greater than zero | |
821 | #[inline] | |
822 | #[target_feature(enable = "neon")] | |
823 | #[cfg_attr(test, assert_instr(cmgt))] | |
824 | pub unsafe fn vcgtzq_s64(a: int64x2_t) -> uint64x2_t { | |
825 | let b: i64x2 = i64x2::new(0, 0); | |
826 | simd_gt(a, transmute(b)) | |
827 | } | |
828 | ||
829 | /// Floating-point compare greater than zero | |
830 | #[inline] | |
831 | #[target_feature(enable = "neon")] | |
832 | #[cfg_attr(test, assert_instr(fcmgt))] | |
833 | pub unsafe fn vcgtz_f32(a: float32x2_t) -> uint32x2_t { | |
834 | let b: f32x2 = f32x2::new(0.0, 0.0); | |
835 | simd_gt(a, transmute(b)) | |
836 | } | |
837 | ||
838 | /// Floating-point compare greater than zero | |
839 | #[inline] | |
840 | #[target_feature(enable = "neon")] | |
841 | #[cfg_attr(test, assert_instr(fcmgt))] | |
842 | pub unsafe fn vcgtzq_f32(a: float32x4_t) -> uint32x4_t { | |
843 | let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); | |
844 | simd_gt(a, transmute(b)) | |
845 | } | |
846 | ||
847 | /// Floating-point compare greater than zero | |
848 | #[inline] | |
849 | #[target_feature(enable = "neon")] | |
850 | #[cfg_attr(test, assert_instr(fcmgt))] | |
851 | pub unsafe fn vcgtz_f64(a: float64x1_t) -> uint64x1_t { | |
852 | let b: f64 = 0.0; | |
853 | simd_gt(a, transmute(b)) | |
854 | } | |
855 | ||
856 | /// Floating-point compare greater than zero | |
857 | #[inline] | |
858 | #[target_feature(enable = "neon")] | |
859 | #[cfg_attr(test, assert_instr(fcmgt))] | |
860 | pub unsafe fn vcgtzq_f64(a: float64x2_t) -> uint64x2_t { | |
861 | let b: f64x2 = f64x2::new(0.0, 0.0); | |
862 | simd_gt(a, transmute(b)) | |
863 | } | |
864 | ||
865 | /// Compare signed less than or equal to zero | |
866 | #[inline] | |
867 | #[target_feature(enable = "neon")] | |
868 | #[cfg_attr(test, assert_instr(cmgt))] | |
869 | pub unsafe fn vclez_s8(a: int8x8_t) -> uint8x8_t { | |
870 | let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
871 | simd_le(a, transmute(b)) | |
872 | } | |
873 | ||
874 | /// Compare signed less than or equal to zero | |
875 | #[inline] | |
876 | #[target_feature(enable = "neon")] | |
877 | #[cfg_attr(test, assert_instr(cmgt))] | |
878 | pub unsafe fn vclezq_s8(a: int8x16_t) -> uint8x16_t { | |
879 | let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
880 | simd_le(a, transmute(b)) | |
881 | } | |
882 | ||
883 | /// Compare signed less than or equal to zero | |
884 | #[inline] | |
885 | #[target_feature(enable = "neon")] | |
886 | #[cfg_attr(test, assert_instr(cmgt))] | |
887 | pub unsafe fn vclez_s16(a: int16x4_t) -> uint16x4_t { | |
888 | let b: i16x4 = i16x4::new(0, 0, 0, 0); | |
889 | simd_le(a, transmute(b)) | |
890 | } | |
891 | ||
892 | /// Compare signed less than or equal to zero | |
893 | #[inline] | |
894 | #[target_feature(enable = "neon")] | |
895 | #[cfg_attr(test, assert_instr(cmgt))] | |
896 | pub unsafe fn vclezq_s16(a: int16x8_t) -> uint16x8_t { | |
897 | let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
898 | simd_le(a, transmute(b)) | |
899 | } | |
900 | ||
901 | /// Compare signed less than or equal to zero | |
902 | #[inline] | |
903 | #[target_feature(enable = "neon")] | |
904 | #[cfg_attr(test, assert_instr(cmgt))] | |
905 | pub unsafe fn vclez_s32(a: int32x2_t) -> uint32x2_t { | |
906 | let b: i32x2 = i32x2::new(0, 0); | |
907 | simd_le(a, transmute(b)) | |
908 | } | |
909 | ||
910 | /// Compare signed less than or equal to zero | |
911 | #[inline] | |
912 | #[target_feature(enable = "neon")] | |
913 | #[cfg_attr(test, assert_instr(cmgt))] | |
914 | pub unsafe fn vclezq_s32(a: int32x4_t) -> uint32x4_t { | |
915 | let b: i32x4 = i32x4::new(0, 0, 0, 0); | |
916 | simd_le(a, transmute(b)) | |
917 | } | |
918 | ||
919 | /// Compare signed less than or equal to zero | |
920 | #[inline] | |
921 | #[target_feature(enable = "neon")] | |
922 | #[cfg_attr(test, assert_instr(cmgt))] | |
923 | pub unsafe fn vclez_s64(a: int64x1_t) -> uint64x1_t { | |
924 | let b: i64x1 = i64x1::new(0); | |
925 | simd_le(a, transmute(b)) | |
926 | } | |
927 | ||
928 | /// Compare signed less than or equal to zero | |
929 | #[inline] | |
930 | #[target_feature(enable = "neon")] | |
931 | #[cfg_attr(test, assert_instr(cmgt))] | |
932 | pub unsafe fn vclezq_s64(a: int64x2_t) -> uint64x2_t { | |
933 | let b: i64x2 = i64x2::new(0, 0); | |
934 | simd_le(a, transmute(b)) | |
935 | } | |
936 | ||
937 | /// Floating-point compare less than or equal to zero | |
938 | #[inline] | |
939 | #[target_feature(enable = "neon")] | |
940 | #[cfg_attr(test, assert_instr(fcmle))] | |
941 | pub unsafe fn vclez_f32(a: float32x2_t) -> uint32x2_t { | |
942 | let b: f32x2 = f32x2::new(0.0, 0.0); | |
943 | simd_le(a, transmute(b)) | |
944 | } | |
945 | ||
946 | /// Floating-point compare less than or equal to zero | |
947 | #[inline] | |
948 | #[target_feature(enable = "neon")] | |
949 | #[cfg_attr(test, assert_instr(fcmle))] | |
950 | pub unsafe fn vclezq_f32(a: float32x4_t) -> uint32x4_t { | |
951 | let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); | |
952 | simd_le(a, transmute(b)) | |
953 | } | |
954 | ||
955 | /// Floating-point compare less than or equal to zero | |
956 | #[inline] | |
957 | #[target_feature(enable = "neon")] | |
958 | #[cfg_attr(test, assert_instr(fcmle))] | |
959 | pub unsafe fn vclez_f64(a: float64x1_t) -> uint64x1_t { | |
960 | let b: f64 = 0.0; | |
961 | simd_le(a, transmute(b)) | |
962 | } | |
963 | ||
964 | /// Floating-point compare less than or equal to zero | |
965 | #[inline] | |
966 | #[target_feature(enable = "neon")] | |
967 | #[cfg_attr(test, assert_instr(fcmle))] | |
968 | pub unsafe fn vclezq_f64(a: float64x2_t) -> uint64x2_t { | |
969 | let b: f64x2 = f64x2::new(0.0, 0.0); | |
970 | simd_le(a, transmute(b)) | |
971 | } | |
972 | ||
973 | /// Compare signed less than zero | |
974 | #[inline] | |
975 | #[target_feature(enable = "neon")] | |
976 | #[cfg_attr(test, assert_instr(sshr))] | |
977 | pub unsafe fn vcltz_s8(a: int8x8_t) -> uint8x8_t { | |
978 | let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
979 | simd_lt(a, transmute(b)) | |
980 | } | |
981 | ||
982 | /// Compare signed less than zero | |
983 | #[inline] | |
984 | #[target_feature(enable = "neon")] | |
985 | #[cfg_attr(test, assert_instr(sshr))] | |
986 | pub unsafe fn vcltzq_s8(a: int8x16_t) -> uint8x16_t { | |
987 | let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
988 | simd_lt(a, transmute(b)) | |
989 | } | |
990 | ||
991 | /// Compare signed less than zero | |
992 | #[inline] | |
993 | #[target_feature(enable = "neon")] | |
994 | #[cfg_attr(test, assert_instr(sshr))] | |
995 | pub unsafe fn vcltz_s16(a: int16x4_t) -> uint16x4_t { | |
996 | let b: i16x4 = i16x4::new(0, 0, 0, 0); | |
997 | simd_lt(a, transmute(b)) | |
998 | } | |
999 | ||
1000 | /// Compare signed less than zero | |
1001 | #[inline] | |
1002 | #[target_feature(enable = "neon")] | |
1003 | #[cfg_attr(test, assert_instr(sshr))] | |
1004 | pub unsafe fn vcltzq_s16(a: int16x8_t) -> uint16x8_t { | |
1005 | let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
1006 | simd_lt(a, transmute(b)) | |
1007 | } | |
1008 | ||
1009 | /// Compare signed less than zero | |
1010 | #[inline] | |
1011 | #[target_feature(enable = "neon")] | |
1012 | #[cfg_attr(test, assert_instr(sshr))] | |
1013 | pub unsafe fn vcltz_s32(a: int32x2_t) -> uint32x2_t { | |
1014 | let b: i32x2 = i32x2::new(0, 0); | |
1015 | simd_lt(a, transmute(b)) | |
1016 | } | |
1017 | ||
1018 | /// Compare signed less than zero | |
1019 | #[inline] | |
1020 | #[target_feature(enable = "neon")] | |
1021 | #[cfg_attr(test, assert_instr(sshr))] | |
1022 | pub unsafe fn vcltzq_s32(a: int32x4_t) -> uint32x4_t { | |
1023 | let b: i32x4 = i32x4::new(0, 0, 0, 0); | |
1024 | simd_lt(a, transmute(b)) | |
1025 | } | |
1026 | ||
1027 | /// Compare signed less than zero | |
1028 | #[inline] | |
1029 | #[target_feature(enable = "neon")] | |
1030 | #[cfg_attr(test, assert_instr(sshr))] | |
1031 | pub unsafe fn vcltz_s64(a: int64x1_t) -> uint64x1_t { | |
1032 | let b: i64x1 = i64x1::new(0); | |
1033 | simd_lt(a, transmute(b)) | |
1034 | } | |
1035 | ||
1036 | /// Compare signed less than zero | |
1037 | #[inline] | |
1038 | #[target_feature(enable = "neon")] | |
1039 | #[cfg_attr(test, assert_instr(sshr))] | |
1040 | pub unsafe fn vcltzq_s64(a: int64x2_t) -> uint64x2_t { | |
1041 | let b: i64x2 = i64x2::new(0, 0); | |
1042 | simd_lt(a, transmute(b)) | |
1043 | } | |
1044 | ||
1045 | /// Floating-point compare less than zero | |
1046 | #[inline] | |
1047 | #[target_feature(enable = "neon")] | |
1048 | #[cfg_attr(test, assert_instr(fcmlt))] | |
1049 | pub unsafe fn vcltz_f32(a: float32x2_t) -> uint32x2_t { | |
1050 | let b: f32x2 = f32x2::new(0.0, 0.0); | |
1051 | simd_lt(a, transmute(b)) | |
1052 | } | |
1053 | ||
1054 | /// Floating-point compare less than zero | |
1055 | #[inline] | |
1056 | #[target_feature(enable = "neon")] | |
1057 | #[cfg_attr(test, assert_instr(fcmlt))] | |
1058 | pub unsafe fn vcltzq_f32(a: float32x4_t) -> uint32x4_t { | |
1059 | let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); | |
1060 | simd_lt(a, transmute(b)) | |
1061 | } | |
1062 | ||
1063 | /// Floating-point compare less than zero | |
1064 | #[inline] | |
1065 | #[target_feature(enable = "neon")] | |
1066 | #[cfg_attr(test, assert_instr(fcmlt))] | |
1067 | pub unsafe fn vcltz_f64(a: float64x1_t) -> uint64x1_t { | |
1068 | let b: f64 = 0.0; | |
1069 | simd_lt(a, transmute(b)) | |
1070 | } | |
1071 | ||
1072 | /// Floating-point compare less than zero | |
1073 | #[inline] | |
1074 | #[target_feature(enable = "neon")] | |
1075 | #[cfg_attr(test, assert_instr(fcmlt))] | |
1076 | pub unsafe fn vcltzq_f64(a: float64x2_t) -> uint64x2_t { | |
1077 | let b: f64x2 = f64x2::new(0.0, 0.0); | |
1078 | simd_lt(a, transmute(b)) | |
1079 | } | |
1080 | ||
1081 | /// Floating-point absolute compare greater than | |
1082 | #[inline] | |
1083 | #[target_feature(enable = "neon")] | |
1084 | #[cfg_attr(test, assert_instr(facgt))] | |
1085 | pub unsafe fn vcagt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { | |
1086 | #[allow(improper_ctypes)] | |
1087 | extern "C" { | |
1088 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.facgt.v1i64.v1f64")] | |
1089 | fn vcagt_f64_(a: float64x1_t, b: float64x1_t) -> uint64x1_t; | |
1090 | } | |
1091 | vcagt_f64_(a, b) | |
1092 | } | |
1093 | ||
1094 | /// Floating-point absolute compare greater than | |
1095 | #[inline] | |
1096 | #[target_feature(enable = "neon")] | |
1097 | #[cfg_attr(test, assert_instr(facgt))] | |
1098 | pub unsafe fn vcagtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { | |
1099 | #[allow(improper_ctypes)] | |
1100 | extern "C" { | |
1101 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.facgt.v2i64.v2f64")] | |
1102 | fn vcagtq_f64_(a: float64x2_t, b: float64x2_t) -> uint64x2_t; | |
1103 | } | |
1104 | vcagtq_f64_(a, b) | |
1105 | } | |
1106 | ||
1107 | /// Floating-point absolute compare greater than or equal | |
1108 | #[inline] | |
1109 | #[target_feature(enable = "neon")] | |
1110 | #[cfg_attr(test, assert_instr(facge))] | |
1111 | pub unsafe fn vcage_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { | |
1112 | #[allow(improper_ctypes)] | |
1113 | extern "C" { | |
1114 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.facge.v1i64.v1f64")] | |
1115 | fn vcage_f64_(a: float64x1_t, b: float64x1_t) -> uint64x1_t; | |
1116 | } | |
1117 | vcage_f64_(a, b) | |
1118 | } | |
1119 | ||
1120 | /// Floating-point absolute compare greater than or equal | |
1121 | #[inline] | |
1122 | #[target_feature(enable = "neon")] | |
1123 | #[cfg_attr(test, assert_instr(facge))] | |
1124 | pub unsafe fn vcageq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { | |
1125 | #[allow(improper_ctypes)] | |
1126 | extern "C" { | |
1127 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.facge.v2i64.v2f64")] | |
1128 | fn vcageq_f64_(a: float64x2_t, b: float64x2_t) -> uint64x2_t; | |
1129 | } | |
1130 | vcageq_f64_(a, b) | |
1131 | } | |
1132 | ||
1133 | /// Floating-point absolute compare less than | |
1134 | #[inline] | |
1135 | #[target_feature(enable = "neon")] | |
1136 | #[cfg_attr(test, assert_instr(facgt))] | |
1137 | pub unsafe fn vcalt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { | |
1138 | vcagt_f64(b, a) | |
1139 | } | |
1140 | ||
1141 | /// Floating-point absolute compare less than | |
1142 | #[inline] | |
1143 | #[target_feature(enable = "neon")] | |
1144 | #[cfg_attr(test, assert_instr(facgt))] | |
1145 | pub unsafe fn vcaltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { | |
1146 | vcagtq_f64(b, a) | |
1147 | } | |
1148 | ||
1149 | /// Floating-point absolute compare less than or equal | |
1150 | #[inline] | |
1151 | #[target_feature(enable = "neon")] | |
1152 | #[cfg_attr(test, assert_instr(facge))] | |
1153 | pub unsafe fn vcale_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { | |
1154 | vcage_f64(b, a) | |
1155 | } | |
1156 | ||
1157 | /// Floating-point absolute compare less than or equal | |
1158 | #[inline] | |
1159 | #[target_feature(enable = "neon")] | |
1160 | #[cfg_attr(test, assert_instr(facge))] | |
1161 | pub unsafe fn vcaleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { | |
1162 | vcageq_f64(b, a) | |
1163 | } | |
1164 | ||
1165 | /// Insert vector element from another vector element | |
1166 | #[inline] | |
1167 | #[target_feature(enable = "neon")] | |
1168 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1169 | #[rustc_legacy_const_generics(1, 3)] | |
1170 | pub unsafe fn vcopy_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t { | |
1171 | static_assert_imm3!(LANE1); | |
1172 | static_assert_imm3!(LANE2); | |
1173 | match LANE1 & 0b111 { | |
1174 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1175 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1176 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1177 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), | |
1178 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), | |
1179 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), | |
1180 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), | |
1181 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), | |
1182 | _ => unreachable_unchecked(), | |
1183 | } | |
1184 | } | |
1185 | ||
1186 | /// Insert vector element from another vector element | |
1187 | #[inline] | |
1188 | #[target_feature(enable = "neon")] | |
1189 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1190 | #[rustc_legacy_const_generics(1, 3)] | |
1191 | pub unsafe fn vcopyq_laneq_s8<const LANE1: i32, const LANE2: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t { | |
1192 | static_assert_imm4!(LANE1); | |
1193 | static_assert_imm4!(LANE2); | |
1194 | match LANE1 & 0b1111 { | |
1195 | 0 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1196 | 1 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1197 | 2 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1198 | 3 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1199 | 4 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1200 | 5 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1201 | 6 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1202 | 7 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1203 | 8 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), | |
1204 | 9 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), | |
1205 | 10 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), | |
1206 | 11 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), | |
1207 | 12 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), | |
1208 | 13 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), | |
1209 | 14 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), | |
1210 | 15 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), | |
1211 | _ => unreachable_unchecked(), | |
1212 | } | |
1213 | } | |
1214 | ||
1215 | /// Insert vector element from another vector element | |
1216 | #[inline] | |
1217 | #[target_feature(enable = "neon")] | |
1218 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1219 | #[rustc_legacy_const_generics(1, 3)] | |
1220 | pub unsafe fn vcopy_lane_s16<const LANE1: i32, const LANE2: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t { | |
1221 | static_assert_imm2!(LANE1); | |
1222 | static_assert_imm2!(LANE2); | |
1223 | match LANE1 & 0b11 { | |
1224 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1, 2, 3]), | |
1225 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32, 2, 3]), | |
1226 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 4 + LANE2 as u32, 3]), | |
1227 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 4 + LANE2 as u32]), | |
1228 | _ => unreachable_unchecked(), | |
1229 | } | |
1230 | } | |
1231 | ||
1232 | /// Insert vector element from another vector element | |
1233 | #[inline] | |
1234 | #[target_feature(enable = "neon")] | |
1235 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1236 | #[rustc_legacy_const_generics(1, 3)] | |
1237 | pub unsafe fn vcopyq_laneq_s16<const LANE1: i32, const LANE2: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t { | |
1238 | static_assert_imm3!(LANE1); | |
1239 | static_assert_imm3!(LANE2); | |
1240 | match LANE1 & 0b111 { | |
1241 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1242 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1243 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1244 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), | |
1245 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), | |
1246 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), | |
1247 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), | |
1248 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), | |
1249 | _ => unreachable_unchecked(), | |
1250 | } | |
1251 | } | |
1252 | ||
1253 | /// Insert vector element from another vector element | |
1254 | #[inline] | |
1255 | #[target_feature(enable = "neon")] | |
1256 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1257 | #[rustc_legacy_const_generics(1, 3)] | |
1258 | pub unsafe fn vcopy_lane_s32<const LANE1: i32, const LANE2: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t { | |
1259 | static_assert_imm1!(LANE1); | |
1260 | static_assert_imm1!(LANE2); | |
1261 | match LANE1 & 0b1 { | |
1262 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
1263 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
1264 | _ => unreachable_unchecked(), | |
1265 | } | |
1266 | } | |
1267 | ||
1268 | /// Insert vector element from another vector element | |
1269 | #[inline] | |
1270 | #[target_feature(enable = "neon")] | |
1271 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1272 | #[rustc_legacy_const_generics(1, 3)] | |
1273 | pub unsafe fn vcopyq_laneq_s32<const LANE1: i32, const LANE2: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t { | |
1274 | static_assert_imm2!(LANE1); | |
1275 | static_assert_imm2!(LANE2); | |
1276 | match LANE1 & 0b11 { | |
1277 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1, 2, 3]), | |
1278 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32, 2, 3]), | |
1279 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 4 + LANE2 as u32, 3]), | |
1280 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 4 + LANE2 as u32]), | |
1281 | _ => unreachable_unchecked(), | |
1282 | } | |
1283 | } | |
1284 | ||
1285 | /// Insert vector element from another vector element | |
1286 | #[inline] | |
1287 | #[target_feature(enable = "neon")] | |
1288 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1289 | #[rustc_legacy_const_generics(1, 3)] | |
1290 | pub unsafe fn vcopyq_laneq_s64<const LANE1: i32, const LANE2: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t { | |
1291 | static_assert_imm1!(LANE1); | |
1292 | static_assert_imm1!(LANE2); | |
1293 | match LANE1 & 0b1 { | |
1294 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
1295 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
1296 | _ => unreachable_unchecked(), | |
1297 | } | |
1298 | } | |
1299 | ||
1300 | /// Insert vector element from another vector element | |
1301 | #[inline] | |
1302 | #[target_feature(enable = "neon")] | |
1303 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1304 | #[rustc_legacy_const_generics(1, 3)] | |
1305 | pub unsafe fn vcopy_lane_u8<const LANE1: i32, const LANE2: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { | |
1306 | static_assert_imm3!(LANE1); | |
1307 | static_assert_imm3!(LANE2); | |
1308 | match LANE1 & 0b111 { | |
1309 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1310 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1311 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1312 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), | |
1313 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), | |
1314 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), | |
1315 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), | |
1316 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), | |
1317 | _ => unreachable_unchecked(), | |
1318 | } | |
1319 | } | |
1320 | ||
1321 | /// Insert vector element from another vector element | |
1322 | #[inline] | |
1323 | #[target_feature(enable = "neon")] | |
1324 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1325 | #[rustc_legacy_const_generics(1, 3)] | |
1326 | pub unsafe fn vcopyq_laneq_u8<const LANE1: i32, const LANE2: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { | |
1327 | static_assert_imm4!(LANE1); | |
1328 | static_assert_imm4!(LANE2); | |
1329 | match LANE1 & 0b1111 { | |
1330 | 0 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1331 | 1 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1332 | 2 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1333 | 3 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1334 | 4 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1335 | 5 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1336 | 6 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1337 | 7 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1338 | 8 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), | |
1339 | 9 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), | |
1340 | 10 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), | |
1341 | 11 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), | |
1342 | 12 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), | |
1343 | 13 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), | |
1344 | 14 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), | |
1345 | 15 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), | |
1346 | _ => unreachable_unchecked(), | |
1347 | } | |
1348 | } | |
1349 | ||
1350 | /// Insert vector element from another vector element | |
1351 | #[inline] | |
1352 | #[target_feature(enable = "neon")] | |
1353 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1354 | #[rustc_legacy_const_generics(1, 3)] | |
1355 | pub unsafe fn vcopy_lane_u16<const LANE1: i32, const LANE2: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { | |
1356 | static_assert_imm2!(LANE1); | |
1357 | static_assert_imm2!(LANE2); | |
1358 | match LANE1 & 0b11 { | |
1359 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1, 2, 3]), | |
1360 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32, 2, 3]), | |
1361 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 4 + LANE2 as u32, 3]), | |
1362 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 4 + LANE2 as u32]), | |
1363 | _ => unreachable_unchecked(), | |
1364 | } | |
1365 | } | |
1366 | ||
1367 | /// Insert vector element from another vector element | |
1368 | #[inline] | |
1369 | #[target_feature(enable = "neon")] | |
1370 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1371 | #[rustc_legacy_const_generics(1, 3)] | |
1372 | pub unsafe fn vcopyq_laneq_u16<const LANE1: i32, const LANE2: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { | |
1373 | static_assert_imm3!(LANE1); | |
1374 | static_assert_imm3!(LANE2); | |
1375 | match LANE1 & 0b111 { | |
1376 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1377 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1378 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1379 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), | |
1380 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), | |
1381 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), | |
1382 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), | |
1383 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), | |
1384 | _ => unreachable_unchecked(), | |
1385 | } | |
1386 | } | |
1387 | ||
1388 | /// Insert vector element from another vector element | |
1389 | #[inline] | |
1390 | #[target_feature(enable = "neon")] | |
1391 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1392 | #[rustc_legacy_const_generics(1, 3)] | |
1393 | pub unsafe fn vcopy_lane_u32<const LANE1: i32, const LANE2: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { | |
1394 | static_assert_imm1!(LANE1); | |
1395 | static_assert_imm1!(LANE2); | |
1396 | match LANE1 & 0b1 { | |
1397 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
1398 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
1399 | _ => unreachable_unchecked(), | |
1400 | } | |
1401 | } | |
1402 | ||
1403 | /// Insert vector element from another vector element | |
1404 | #[inline] | |
1405 | #[target_feature(enable = "neon")] | |
1406 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1407 | #[rustc_legacy_const_generics(1, 3)] | |
1408 | pub unsafe fn vcopyq_laneq_u32<const LANE1: i32, const LANE2: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { | |
1409 | static_assert_imm2!(LANE1); | |
1410 | static_assert_imm2!(LANE2); | |
1411 | match LANE1 & 0b11 { | |
1412 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1, 2, 3]), | |
1413 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32, 2, 3]), | |
1414 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 4 + LANE2 as u32, 3]), | |
1415 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 4 + LANE2 as u32]), | |
1416 | _ => unreachable_unchecked(), | |
1417 | } | |
1418 | } | |
1419 | ||
1420 | /// Insert vector element from another vector element | |
1421 | #[inline] | |
1422 | #[target_feature(enable = "neon")] | |
1423 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1424 | #[rustc_legacy_const_generics(1, 3)] | |
1425 | pub unsafe fn vcopyq_laneq_u64<const LANE1: i32, const LANE2: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
1426 | static_assert_imm1!(LANE1); | |
1427 | static_assert_imm1!(LANE2); | |
1428 | match LANE1 & 0b1 { | |
1429 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
1430 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
1431 | _ => unreachable_unchecked(), | |
1432 | } | |
1433 | } | |
1434 | ||
1435 | /// Insert vector element from another vector element | |
1436 | #[inline] | |
1437 | #[target_feature(enable = "neon")] | |
1438 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1439 | #[rustc_legacy_const_generics(1, 3)] | |
1440 | pub unsafe fn vcopy_lane_p8<const LANE1: i32, const LANE2: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { | |
1441 | static_assert_imm3!(LANE1); | |
1442 | static_assert_imm3!(LANE2); | |
1443 | match LANE1 & 0b111 { | |
1444 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1445 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1446 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1447 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), | |
1448 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), | |
1449 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), | |
1450 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), | |
1451 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), | |
1452 | _ => unreachable_unchecked(), | |
1453 | } | |
1454 | } | |
1455 | ||
1456 | /// Insert vector element from another vector element | |
1457 | #[inline] | |
1458 | #[target_feature(enable = "neon")] | |
1459 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1460 | #[rustc_legacy_const_generics(1, 3)] | |
1461 | pub unsafe fn vcopyq_laneq_p8<const LANE1: i32, const LANE2: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { | |
1462 | static_assert_imm4!(LANE1); | |
1463 | static_assert_imm4!(LANE2); | |
1464 | match LANE1 & 0b1111 { | |
1465 | 0 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1466 | 1 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1467 | 2 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1468 | 3 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1469 | 4 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1470 | 5 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1471 | 6 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1472 | 7 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1473 | 8 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), | |
1474 | 9 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), | |
1475 | 10 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), | |
1476 | 11 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), | |
1477 | 12 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), | |
1478 | 13 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), | |
1479 | 14 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), | |
1480 | 15 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), | |
1481 | _ => unreachable_unchecked(), | |
1482 | } | |
1483 | } | |
1484 | ||
1485 | /// Insert vector element from another vector element | |
1486 | #[inline] | |
1487 | #[target_feature(enable = "neon")] | |
1488 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1489 | #[rustc_legacy_const_generics(1, 3)] | |
1490 | pub unsafe fn vcopy_lane_p16<const LANE1: i32, const LANE2: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { | |
1491 | static_assert_imm2!(LANE1); | |
1492 | static_assert_imm2!(LANE2); | |
1493 | match LANE1 & 0b11 { | |
1494 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1, 2, 3]), | |
1495 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32, 2, 3]), | |
1496 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 4 + LANE2 as u32, 3]), | |
1497 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 4 + LANE2 as u32]), | |
1498 | _ => unreachable_unchecked(), | |
1499 | } | |
1500 | } | |
1501 | ||
1502 | /// Insert vector element from another vector element | |
1503 | #[inline] | |
1504 | #[target_feature(enable = "neon")] | |
1505 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1506 | #[rustc_legacy_const_generics(1, 3)] | |
1507 | pub unsafe fn vcopyq_laneq_p16<const LANE1: i32, const LANE2: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { | |
1508 | static_assert_imm3!(LANE1); | |
1509 | static_assert_imm3!(LANE2); | |
1510 | match LANE1 & 0b111 { | |
1511 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1512 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1513 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1514 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), | |
1515 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), | |
1516 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), | |
1517 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), | |
1518 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), | |
1519 | _ => unreachable_unchecked(), | |
1520 | } | |
1521 | } | |
1522 | ||
1523 | /// Insert vector element from another vector element | |
1524 | #[inline] | |
1525 | #[target_feature(enable = "neon")] | |
1526 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1527 | #[rustc_legacy_const_generics(1, 3)] | |
1528 | pub unsafe fn vcopyq_laneq_p64<const LANE1: i32, const LANE2: i32>(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { | |
1529 | static_assert_imm1!(LANE1); | |
1530 | static_assert_imm1!(LANE2); | |
1531 | match LANE1 & 0b1 { | |
1532 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
1533 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
1534 | _ => unreachable_unchecked(), | |
1535 | } | |
1536 | } | |
1537 | ||
1538 | /// Insert vector element from another vector element | |
1539 | #[inline] | |
1540 | #[target_feature(enable = "neon")] | |
1541 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1542 | #[rustc_legacy_const_generics(1, 3)] | |
1543 | pub unsafe fn vcopy_lane_f32<const LANE1: i32, const LANE2: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
1544 | static_assert_imm1!(LANE1); | |
1545 | static_assert_imm1!(LANE2); | |
1546 | match LANE1 & 0b1 { | |
1547 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
1548 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
1549 | _ => unreachable_unchecked(), | |
1550 | } | |
1551 | } | |
1552 | ||
1553 | /// Insert vector element from another vector element | |
1554 | #[inline] | |
1555 | #[target_feature(enable = "neon")] | |
1556 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1557 | #[rustc_legacy_const_generics(1, 3)] | |
1558 | pub unsafe fn vcopyq_laneq_f32<const LANE1: i32, const LANE2: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
1559 | static_assert_imm2!(LANE1); | |
1560 | static_assert_imm2!(LANE2); | |
1561 | match LANE1 & 0b11 { | |
1562 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1, 2, 3]), | |
1563 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32, 2, 3]), | |
1564 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 4 + LANE2 as u32, 3]), | |
1565 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 4 + LANE2 as u32]), | |
1566 | _ => unreachable_unchecked(), | |
1567 | } | |
1568 | } | |
1569 | ||
1570 | /// Insert vector element from another vector element | |
1571 | #[inline] | |
1572 | #[target_feature(enable = "neon")] | |
1573 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1574 | #[rustc_legacy_const_generics(1, 3)] | |
1575 | pub unsafe fn vcopyq_laneq_f64<const LANE1: i32, const LANE2: i32>(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
1576 | static_assert_imm1!(LANE1); | |
1577 | static_assert_imm1!(LANE2); | |
1578 | match LANE1 & 0b1 { | |
1579 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
1580 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
1581 | _ => unreachable_unchecked(), | |
1582 | } | |
1583 | } | |
1584 | ||
1585 | /// Insert vector element from another vector element | |
1586 | #[inline] | |
1587 | #[target_feature(enable = "neon")] | |
1588 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1589 | #[rustc_legacy_const_generics(1, 3)] | |
1590 | pub unsafe fn vcopy_laneq_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x16_t) -> int8x8_t { | |
1591 | static_assert_imm3!(LANE1); | |
1592 | static_assert_imm4!(LANE2); | |
1593 | let a: int8x16_t = simd_shuffle16!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); | |
1594 | match LANE1 & 0b111 { | |
1595 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1596 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1597 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1598 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), | |
1599 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), | |
1600 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), | |
1601 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), | |
1602 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), | |
1603 | _ => unreachable_unchecked(), | |
1604 | } | |
1605 | } | |
1606 | ||
1607 | /// Insert vector element from another vector element | |
1608 | #[inline] | |
1609 | #[target_feature(enable = "neon")] | |
1610 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1611 | #[rustc_legacy_const_generics(1, 3)] | |
1612 | pub unsafe fn vcopy_laneq_s16<const LANE1: i32, const LANE2: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t { | |
1613 | static_assert_imm2!(LANE1); | |
1614 | static_assert_imm3!(LANE2); | |
1615 | let a: int16x8_t = simd_shuffle8!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); | |
1616 | match LANE1 & 0b11 { | |
1617 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3]), | |
1618 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3]), | |
1619 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3]), | |
1620 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32]), | |
1621 | _ => unreachable_unchecked(), | |
1622 | } | |
1623 | } | |
1624 | ||
1625 | /// Insert vector element from another vector element | |
1626 | #[inline] | |
1627 | #[target_feature(enable = "neon")] | |
1628 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1629 | #[rustc_legacy_const_generics(1, 3)] | |
1630 | pub unsafe fn vcopy_laneq_s32<const LANE1: i32, const LANE2: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t { | |
1631 | static_assert_imm1!(LANE1); | |
1632 | static_assert_imm2!(LANE2); | |
1633 | let a: int32x4_t = simd_shuffle4!(a, a, [0, 1, 2, 3]); | |
1634 | match LANE1 & 0b1 { | |
1635 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1]), | |
1636 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32]), | |
1637 | _ => unreachable_unchecked(), | |
1638 | } | |
1639 | } | |
1640 | ||
1641 | /// Insert vector element from another vector element | |
1642 | #[inline] | |
1643 | #[target_feature(enable = "neon")] | |
1644 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1645 | #[rustc_legacy_const_generics(1, 3)] | |
1646 | pub unsafe fn vcopy_laneq_u8<const LANE1: i32, const LANE2: i32>(a: uint8x8_t, b: uint8x16_t) -> uint8x8_t { | |
1647 | static_assert_imm3!(LANE1); | |
1648 | static_assert_imm4!(LANE2); | |
1649 | let a: uint8x16_t = simd_shuffle16!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); | |
1650 | match LANE1 & 0b111 { | |
1651 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1652 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1653 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1654 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), | |
1655 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), | |
1656 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), | |
1657 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), | |
1658 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), | |
1659 | _ => unreachable_unchecked(), | |
1660 | } | |
1661 | } | |
1662 | ||
1663 | /// Insert vector element from another vector element | |
1664 | #[inline] | |
1665 | #[target_feature(enable = "neon")] | |
1666 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1667 | #[rustc_legacy_const_generics(1, 3)] | |
1668 | pub unsafe fn vcopy_laneq_u16<const LANE1: i32, const LANE2: i32>(a: uint16x4_t, b: uint16x8_t) -> uint16x4_t { | |
1669 | static_assert_imm2!(LANE1); | |
1670 | static_assert_imm3!(LANE2); | |
1671 | let a: uint16x8_t = simd_shuffle8!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); | |
1672 | match LANE1 & 0b11 { | |
1673 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3]), | |
1674 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3]), | |
1675 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3]), | |
1676 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32]), | |
1677 | _ => unreachable_unchecked(), | |
1678 | } | |
1679 | } | |
1680 | ||
1681 | /// Insert vector element from another vector element | |
1682 | #[inline] | |
1683 | #[target_feature(enable = "neon")] | |
1684 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1685 | #[rustc_legacy_const_generics(1, 3)] | |
1686 | pub unsafe fn vcopy_laneq_u32<const LANE1: i32, const LANE2: i32>(a: uint32x2_t, b: uint32x4_t) -> uint32x2_t { | |
1687 | static_assert_imm1!(LANE1); | |
1688 | static_assert_imm2!(LANE2); | |
1689 | let a: uint32x4_t = simd_shuffle4!(a, a, [0, 1, 2, 3]); | |
1690 | match LANE1 & 0b1 { | |
1691 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1]), | |
1692 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32]), | |
1693 | _ => unreachable_unchecked(), | |
1694 | } | |
1695 | } | |
1696 | ||
1697 | /// Insert vector element from another vector element | |
1698 | #[inline] | |
1699 | #[target_feature(enable = "neon")] | |
1700 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1701 | #[rustc_legacy_const_generics(1, 3)] | |
1702 | pub unsafe fn vcopy_laneq_p8<const LANE1: i32, const LANE2: i32>(a: poly8x8_t, b: poly8x16_t) -> poly8x8_t { | |
1703 | static_assert_imm3!(LANE1); | |
1704 | static_assert_imm4!(LANE2); | |
1705 | let a: poly8x16_t = simd_shuffle16!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); | |
1706 | match LANE1 & 0b111 { | |
1707 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1708 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1709 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1710 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), | |
1711 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), | |
1712 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), | |
1713 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), | |
1714 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), | |
1715 | _ => unreachable_unchecked(), | |
1716 | } | |
1717 | } | |
1718 | ||
1719 | /// Insert vector element from another vector element | |
1720 | #[inline] | |
1721 | #[target_feature(enable = "neon")] | |
1722 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1723 | #[rustc_legacy_const_generics(1, 3)] | |
1724 | pub unsafe fn vcopy_laneq_p16<const LANE1: i32, const LANE2: i32>(a: poly16x4_t, b: poly16x8_t) -> poly16x4_t { | |
1725 | static_assert_imm2!(LANE1); | |
1726 | static_assert_imm3!(LANE2); | |
1727 | let a: poly16x8_t = simd_shuffle8!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); | |
1728 | match LANE1 & 0b11 { | |
1729 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3]), | |
1730 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3]), | |
1731 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3]), | |
1732 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32]), | |
1733 | _ => unreachable_unchecked(), | |
1734 | } | |
1735 | } | |
1736 | ||
1737 | /// Insert vector element from another vector element | |
1738 | #[inline] | |
1739 | #[target_feature(enable = "neon")] | |
1740 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1741 | #[rustc_legacy_const_generics(1, 3)] | |
1742 | pub unsafe fn vcopy_laneq_f32<const LANE1: i32, const LANE2: i32>(a: float32x2_t, b: float32x4_t) -> float32x2_t { | |
1743 | static_assert_imm1!(LANE1); | |
1744 | static_assert_imm2!(LANE2); | |
1745 | let a: float32x4_t = simd_shuffle4!(a, a, [0, 1, 2, 3]); | |
1746 | match LANE1 & 0b1 { | |
1747 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1]), | |
1748 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32]), | |
1749 | _ => unreachable_unchecked(), | |
1750 | } | |
1751 | } | |
1752 | ||
1753 | /// Insert vector element from another vector element | |
1754 | #[inline] | |
1755 | #[target_feature(enable = "neon")] | |
1756 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1757 | #[rustc_legacy_const_generics(1, 3)] | |
1758 | pub unsafe fn vcopyq_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x16_t, b: int8x8_t) -> int8x16_t { | |
1759 | static_assert_imm4!(LANE1); | |
1760 | static_assert_imm3!(LANE2); | |
1761 | let b: int8x16_t = simd_shuffle16!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); | |
1762 | match LANE1 & 0b1111 { | |
1763 | 0 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1764 | 1 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1765 | 2 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1766 | 3 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1767 | 4 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1768 | 5 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1769 | 6 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1770 | 7 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1771 | 8 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), | |
1772 | 9 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), | |
1773 | 10 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), | |
1774 | 11 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), | |
1775 | 12 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), | |
1776 | 13 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), | |
1777 | 14 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), | |
1778 | 15 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), | |
1779 | _ => unreachable_unchecked(), | |
1780 | } | |
1781 | } | |
1782 | ||
1783 | /// Insert vector element from another vector element | |
1784 | #[inline] | |
1785 | #[target_feature(enable = "neon")] | |
1786 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1787 | #[rustc_legacy_const_generics(1, 3)] | |
1788 | pub unsafe fn vcopyq_lane_s16<const LANE1: i32, const LANE2: i32>(a: int16x8_t, b: int16x4_t) -> int16x8_t { | |
1789 | static_assert_imm3!(LANE1); | |
1790 | static_assert_imm2!(LANE2); | |
1791 | let b: int16x8_t = simd_shuffle8!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]); | |
1792 | match LANE1 & 0b111 { | |
1793 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1794 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1795 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1796 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), | |
1797 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), | |
1798 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), | |
1799 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), | |
1800 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), | |
1801 | _ => unreachable_unchecked(), | |
1802 | } | |
1803 | } | |
1804 | ||
1805 | /// Insert vector element from another vector element | |
1806 | #[inline] | |
1807 | #[target_feature(enable = "neon")] | |
1808 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1809 | #[rustc_legacy_const_generics(1, 3)] | |
1810 | pub unsafe fn vcopyq_lane_s32<const LANE1: i32, const LANE2: i32>(a: int32x4_t, b: int32x2_t) -> int32x4_t { | |
1811 | static_assert_imm2!(LANE1); | |
1812 | static_assert_imm1!(LANE2); | |
1813 | let b: int32x4_t = simd_shuffle4!(b, b, [0, 1, 2, 3]); | |
1814 | match LANE1 & 0b11 { | |
1815 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1, 2, 3]), | |
1816 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32, 2, 3]), | |
1817 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 4 + LANE2 as u32, 3]), | |
1818 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 4 + LANE2 as u32]), | |
1819 | _ => unreachable_unchecked(), | |
1820 | } | |
1821 | } | |
1822 | ||
1823 | /// Insert vector element from another vector element | |
1824 | #[inline] | |
1825 | #[target_feature(enable = "neon")] | |
1826 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1827 | #[rustc_legacy_const_generics(1, 3)] | |
1828 | pub unsafe fn vcopyq_lane_u8<const LANE1: i32, const LANE2: i32>(a: uint8x16_t, b: uint8x8_t) -> uint8x16_t { | |
1829 | static_assert_imm4!(LANE1); | |
1830 | static_assert_imm3!(LANE2); | |
1831 | let b: uint8x16_t = simd_shuffle16!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); | |
1832 | match LANE1 & 0b1111 { | |
1833 | 0 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1834 | 1 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1835 | 2 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1836 | 3 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1837 | 4 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1838 | 5 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1839 | 6 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1840 | 7 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1841 | 8 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), | |
1842 | 9 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), | |
1843 | 10 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), | |
1844 | 11 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), | |
1845 | 12 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), | |
1846 | 13 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), | |
1847 | 14 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), | |
1848 | 15 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), | |
1849 | _ => unreachable_unchecked(), | |
1850 | } | |
1851 | } | |
1852 | ||
1853 | /// Insert vector element from another vector element | |
1854 | #[inline] | |
1855 | #[target_feature(enable = "neon")] | |
1856 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1857 | #[rustc_legacy_const_generics(1, 3)] | |
1858 | pub unsafe fn vcopyq_lane_u16<const LANE1: i32, const LANE2: i32>(a: uint16x8_t, b: uint16x4_t) -> uint16x8_t { | |
1859 | static_assert_imm3!(LANE1); | |
1860 | static_assert_imm2!(LANE2); | |
1861 | let b: uint16x8_t = simd_shuffle8!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]); | |
1862 | match LANE1 & 0b111 { | |
1863 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1864 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1865 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1866 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), | |
1867 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), | |
1868 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), | |
1869 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), | |
1870 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), | |
1871 | _ => unreachable_unchecked(), | |
1872 | } | |
1873 | } | |
1874 | ||
1875 | /// Insert vector element from another vector element | |
1876 | #[inline] | |
1877 | #[target_feature(enable = "neon")] | |
1878 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1879 | #[rustc_legacy_const_generics(1, 3)] | |
1880 | pub unsafe fn vcopyq_lane_u32<const LANE1: i32, const LANE2: i32>(a: uint32x4_t, b: uint32x2_t) -> uint32x4_t { | |
1881 | static_assert_imm2!(LANE1); | |
1882 | static_assert_imm1!(LANE2); | |
1883 | let b: uint32x4_t = simd_shuffle4!(b, b, [0, 1, 2, 3]); | |
1884 | match LANE1 & 0b11 { | |
1885 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1, 2, 3]), | |
1886 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32, 2, 3]), | |
1887 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 4 + LANE2 as u32, 3]), | |
1888 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 4 + LANE2 as u32]), | |
1889 | _ => unreachable_unchecked(), | |
1890 | } | |
1891 | } | |
1892 | ||
1893 | /// Insert vector element from another vector element | |
1894 | #[inline] | |
1895 | #[target_feature(enable = "neon")] | |
1896 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1897 | #[rustc_legacy_const_generics(1, 3)] | |
1898 | pub unsafe fn vcopyq_lane_p8<const LANE1: i32, const LANE2: i32>(a: poly8x16_t, b: poly8x8_t) -> poly8x16_t { | |
1899 | static_assert_imm4!(LANE1); | |
1900 | static_assert_imm3!(LANE2); | |
1901 | let b: poly8x16_t = simd_shuffle16!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); | |
1902 | match LANE1 & 0b1111 { | |
1903 | 0 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1904 | 1 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1905 | 2 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1906 | 3 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1907 | 4 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1908 | 5 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1909 | 6 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1910 | 7 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), | |
1911 | 8 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), | |
1912 | 9 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), | |
1913 | 10 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), | |
1914 | 11 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), | |
1915 | 12 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), | |
1916 | 13 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), | |
1917 | 14 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), | |
1918 | 15 => simd_shuffle16!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), | |
1919 | _ => unreachable_unchecked(), | |
1920 | } | |
1921 | } | |
1922 | ||
1923 | /// Insert vector element from another vector element | |
1924 | #[inline] | |
1925 | #[target_feature(enable = "neon")] | |
1926 | #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] | |
1927 | #[rustc_legacy_const_generics(1, 3)] | |
1928 | pub unsafe fn vcopyq_lane_p16<const LANE1: i32, const LANE2: i32>(a: poly16x8_t, b: poly16x4_t) -> poly16x8_t { | |
1929 | static_assert_imm3!(LANE1); | |
1930 | static_assert_imm2!(LANE2); | |
1931 | let b: poly16x8_t = simd_shuffle8!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]); | |
1932 | match LANE1 & 0b111 { | |
1933 | 0 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), | |
1934 | 1 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), | |
1935 | 2 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), | |
1936 | 3 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), | |
1937 | 4 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), | |
1938 | 5 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), | |
1939 | 6 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), | |
1940 | 7 => simd_shuffle8!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), | |
1941 | _ => unreachable_unchecked(), | |
1942 | } | |
1943 | } | |
1944 | ||
1945 | /// Insert vector element from another vector element | |
1946 | #[inline] | |
1947 | #[target_feature(enable = "neon")] | |
1948 | #[cfg_attr(test, assert_instr(zip1, LANE1 = 1, LANE2 = 0))] | |
1949 | #[rustc_legacy_const_generics(1, 3)] | |
1950 | pub unsafe fn vcopyq_lane_s64<const LANE1: i32, const LANE2: i32>(a: int64x2_t, b: int64x1_t) -> int64x2_t { | |
1951 | static_assert_imm1!(LANE1); | |
1952 | static_assert!(LANE2 : i32 where LANE2 == 0); | |
1953 | let b: int64x2_t = simd_shuffle2!(b, b, [0, 1]); | |
1954 | match LANE1 & 0b1 { | |
1955 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
1956 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
1957 | _ => unreachable_unchecked(), | |
1958 | } | |
1959 | } | |
1960 | ||
1961 | /// Insert vector element from another vector element | |
1962 | #[inline] | |
1963 | #[target_feature(enable = "neon")] | |
1964 | #[cfg_attr(test, assert_instr(zip1, LANE1 = 1, LANE2 = 0))] | |
1965 | #[rustc_legacy_const_generics(1, 3)] | |
1966 | pub unsafe fn vcopyq_lane_u64<const LANE1: i32, const LANE2: i32>(a: uint64x2_t, b: uint64x1_t) -> uint64x2_t { | |
1967 | static_assert_imm1!(LANE1); | |
1968 | static_assert!(LANE2 : i32 where LANE2 == 0); | |
1969 | let b: uint64x2_t = simd_shuffle2!(b, b, [0, 1]); | |
1970 | match LANE1 & 0b1 { | |
1971 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
1972 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
1973 | _ => unreachable_unchecked(), | |
1974 | } | |
1975 | } | |
1976 | ||
1977 | /// Insert vector element from another vector element | |
1978 | #[inline] | |
1979 | #[target_feature(enable = "neon")] | |
1980 | #[cfg_attr(test, assert_instr(zip1, LANE1 = 1, LANE2 = 0))] | |
1981 | #[rustc_legacy_const_generics(1, 3)] | |
1982 | pub unsafe fn vcopyq_lane_p64<const LANE1: i32, const LANE2: i32>(a: poly64x2_t, b: poly64x1_t) -> poly64x2_t { | |
1983 | static_assert_imm1!(LANE1); | |
1984 | static_assert!(LANE2 : i32 where LANE2 == 0); | |
1985 | let b: poly64x2_t = simd_shuffle2!(b, b, [0, 1]); | |
1986 | match LANE1 & 0b1 { | |
1987 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
1988 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
1989 | _ => unreachable_unchecked(), | |
1990 | } | |
1991 | } | |
1992 | ||
1993 | /// Insert vector element from another vector element | |
1994 | #[inline] | |
1995 | #[target_feature(enable = "neon")] | |
1996 | #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] | |
1997 | #[rustc_legacy_const_generics(1, 3)] | |
1998 | pub unsafe fn vcopyq_lane_f32<const LANE1: i32, const LANE2: i32>(a: float32x4_t, b: float32x2_t) -> float32x4_t { | |
1999 | static_assert_imm2!(LANE1); | |
2000 | static_assert_imm1!(LANE2); | |
2001 | let b: float32x4_t = simd_shuffle4!(b, b, [0, 1, 2, 3]); | |
2002 | match LANE1 & 0b11 { | |
2003 | 0 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [4 + LANE2 as u32, 1, 2, 3]), | |
2004 | 1 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 4 + LANE2 as u32, 2, 3]), | |
2005 | 2 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 4 + LANE2 as u32, 3]), | |
2006 | 3 => simd_shuffle4!(a, b, <const LANE1: i32, const LANE2: i32> [0, 1, 2, 4 + LANE2 as u32]), | |
2007 | _ => unreachable_unchecked(), | |
2008 | } | |
2009 | } | |
2010 | ||
2011 | /// Insert vector element from another vector element | |
2012 | #[inline] | |
2013 | #[target_feature(enable = "neon")] | |
2014 | #[cfg_attr(test, assert_instr(zip1, LANE1 = 1, LANE2 = 0))] | |
2015 | #[rustc_legacy_const_generics(1, 3)] | |
2016 | pub unsafe fn vcopyq_lane_f64<const LANE1: i32, const LANE2: i32>(a: float64x2_t, b: float64x1_t) -> float64x2_t { | |
2017 | static_assert_imm1!(LANE1); | |
2018 | static_assert!(LANE2 : i32 where LANE2 == 0); | |
2019 | let b: float64x2_t = simd_shuffle2!(b, b, [0, 1]); | |
2020 | match LANE1 & 0b1 { | |
2021 | 0 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [2 + LANE2 as u32, 1]), | |
2022 | 1 => simd_shuffle2!(a, b, <const LANE1: i32, const LANE2: i32> [0, 2 + LANE2 as u32]), | |
2023 | _ => unreachable_unchecked(), | |
2024 | } | |
2025 | } | |
2026 | ||
2027 | /// Insert vector element from another vector element | |
2028 | #[inline] | |
2029 | #[target_feature(enable = "neon")] | |
2030 | #[cfg_attr(test, assert_instr(nop))] | |
2031 | pub unsafe fn vcreate_f64(a: u64) -> float64x1_t { | |
2032 | transmute(a) | |
2033 | } | |
2034 | ||
2035 | /// Fixed-point convert to floating-point | |
2036 | #[inline] | |
2037 | #[target_feature(enable = "neon")] | |
2038 | #[cfg_attr(test, assert_instr(scvtf))] | |
2039 | pub unsafe fn vcvt_f64_s64(a: int64x1_t) -> float64x1_t { | |
2040 | simd_cast(a) | |
2041 | } | |
2042 | ||
2043 | /// Fixed-point convert to floating-point | |
2044 | #[inline] | |
2045 | #[target_feature(enable = "neon")] | |
2046 | #[cfg_attr(test, assert_instr(scvtf))] | |
2047 | pub unsafe fn vcvtq_f64_s64(a: int64x2_t) -> float64x2_t { | |
2048 | simd_cast(a) | |
2049 | } | |
2050 | ||
2051 | /// Fixed-point convert to floating-point | |
2052 | #[inline] | |
2053 | #[target_feature(enable = "neon")] | |
2054 | #[cfg_attr(test, assert_instr(ucvtf))] | |
2055 | pub unsafe fn vcvt_f64_u64(a: uint64x1_t) -> float64x1_t { | |
2056 | simd_cast(a) | |
2057 | } | |
2058 | ||
2059 | /// Fixed-point convert to floating-point | |
2060 | #[inline] | |
2061 | #[target_feature(enable = "neon")] | |
2062 | #[cfg_attr(test, assert_instr(ucvtf))] | |
2063 | pub unsafe fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t { | |
2064 | simd_cast(a) | |
2065 | } | |
2066 | ||
2067 | /// Floating-point convert to higher precision long | |
2068 | #[inline] | |
2069 | #[target_feature(enable = "neon")] | |
2070 | #[cfg_attr(test, assert_instr(fcvtl))] | |
2071 | pub unsafe fn vcvt_f64_f32(a: float32x2_t) -> float64x2_t { | |
2072 | simd_cast(a) | |
2073 | } | |
2074 | ||
2075 | /// Floating-point convert to higher precision long | |
2076 | #[inline] | |
2077 | #[target_feature(enable = "neon")] | |
2078 | #[cfg_attr(test, assert_instr(fcvtl))] | |
2079 | pub unsafe fn vcvt_high_f64_f32(a: float32x4_t) -> float64x2_t { | |
2080 | let b: float32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
2081 | simd_cast(b) | |
2082 | } | |
2083 | ||
2084 | /// Floating-point convert to lower precision narrow | |
2085 | #[inline] | |
2086 | #[target_feature(enable = "neon")] | |
2087 | #[cfg_attr(test, assert_instr(fcvtn))] | |
2088 | pub unsafe fn vcvt_f32_f64(a: float64x2_t) -> float32x2_t { | |
2089 | simd_cast(a) | |
2090 | } | |
2091 | ||
2092 | /// Floating-point convert to lower precision narrow | |
2093 | #[inline] | |
2094 | #[target_feature(enable = "neon")] | |
2095 | #[cfg_attr(test, assert_instr(fcvtn))] | |
2096 | pub unsafe fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t { | |
2097 | simd_shuffle4!(a, simd_cast(b), [0, 1, 2, 3]) | |
2098 | } | |
2099 | ||
2100 | /// Floating-point convert to lower precision narrow, rounding to odd | |
2101 | #[inline] | |
2102 | #[target_feature(enable = "neon")] | |
2103 | #[cfg_attr(test, assert_instr(fcvtxn))] | |
2104 | pub unsafe fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t { | |
2105 | #[allow(improper_ctypes)] | |
2106 | extern "C" { | |
2107 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtxn.v2f32.v2f64")] | |
2108 | fn vcvtx_f32_f64_(a: float64x2_t) -> float32x2_t; | |
2109 | } | |
2110 | vcvtx_f32_f64_(a) | |
2111 | } | |
2112 | ||
2113 | /// Floating-point convert to lower precision narrow, rounding to odd | |
2114 | #[inline] | |
2115 | #[target_feature(enable = "neon")] | |
2116 | #[cfg_attr(test, assert_instr(fcvtxn))] | |
2117 | pub unsafe fn vcvtx_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t { | |
2118 | simd_shuffle4!(a, vcvtx_f32_f64(b), [0, 1, 2, 3]) | |
2119 | } | |
2120 | ||
2121 | /// Fixed-point convert to floating-point | |
2122 | #[inline] | |
2123 | #[target_feature(enable = "neon")] | |
2124 | #[cfg_attr(test, assert_instr(scvtf, N = 2))] | |
2125 | #[rustc_legacy_const_generics(1)] | |
2126 | pub unsafe fn vcvt_n_f64_s64<const N: i32>(a: int64x1_t) -> float64x1_t { | |
2127 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2128 | #[allow(improper_ctypes)] | |
2129 | extern "C" { | |
2130 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfxs2fp.v1f64.v1i64")] | |
2131 | fn vcvt_n_f64_s64_(a: int64x1_t, n: i32) -> float64x1_t; | |
2132 | } | |
2133 | vcvt_n_f64_s64_(a, N) | |
2134 | } | |
2135 | ||
2136 | /// Fixed-point convert to floating-point | |
2137 | #[inline] | |
2138 | #[target_feature(enable = "neon")] | |
2139 | #[cfg_attr(test, assert_instr(scvtf, N = 2))] | |
2140 | #[rustc_legacy_const_generics(1)] | |
2141 | pub unsafe fn vcvtq_n_f64_s64<const N: i32>(a: int64x2_t) -> float64x2_t { | |
2142 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2143 | #[allow(improper_ctypes)] | |
2144 | extern "C" { | |
2145 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64")] | |
2146 | fn vcvtq_n_f64_s64_(a: int64x2_t, n: i32) -> float64x2_t; | |
2147 | } | |
2148 | vcvtq_n_f64_s64_(a, N) | |
2149 | } | |
2150 | ||
2151 | /// Fixed-point convert to floating-point | |
2152 | #[inline] | |
2153 | #[target_feature(enable = "neon")] | |
2154 | #[cfg_attr(test, assert_instr(scvtf, N = 2))] | |
2155 | #[rustc_legacy_const_generics(1)] | |
2156 | pub unsafe fn vcvts_n_f32_s32<const N: i32>(a: i32) -> f32 { | |
2157 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
2158 | #[allow(improper_ctypes)] | |
2159 | extern "C" { | |
2160 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfxs2fp.f32.i32")] | |
2161 | fn vcvts_n_f32_s32_(a: i32, n: i32) -> f32; | |
2162 | } | |
2163 | vcvts_n_f32_s32_(a, N) | |
2164 | } | |
2165 | ||
2166 | /// Fixed-point convert to floating-point | |
2167 | #[inline] | |
2168 | #[target_feature(enable = "neon")] | |
2169 | #[cfg_attr(test, assert_instr(scvtf, N = 2))] | |
2170 | #[rustc_legacy_const_generics(1)] | |
2171 | pub unsafe fn vcvtd_n_f64_s64<const N: i32>(a: i64) -> f64 { | |
2172 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2173 | #[allow(improper_ctypes)] | |
2174 | extern "C" { | |
2175 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfxs2fp.f64.i64")] | |
2176 | fn vcvtd_n_f64_s64_(a: i64, n: i32) -> f64; | |
2177 | } | |
2178 | vcvtd_n_f64_s64_(a, N) | |
2179 | } | |
2180 | ||
2181 | /// Fixed-point convert to floating-point | |
2182 | #[inline] | |
2183 | #[target_feature(enable = "neon")] | |
2184 | #[cfg_attr(test, assert_instr(ucvtf, N = 2))] | |
2185 | #[rustc_legacy_const_generics(1)] | |
2186 | pub unsafe fn vcvt_n_f64_u64<const N: i32>(a: uint64x1_t) -> float64x1_t { | |
2187 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2188 | #[allow(improper_ctypes)] | |
2189 | extern "C" { | |
2190 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfxu2fp.v1f64.v1i64")] | |
2191 | fn vcvt_n_f64_u64_(a: uint64x1_t, n: i32) -> float64x1_t; | |
2192 | } | |
2193 | vcvt_n_f64_u64_(a, N) | |
2194 | } | |
2195 | ||
2196 | /// Fixed-point convert to floating-point | |
2197 | #[inline] | |
2198 | #[target_feature(enable = "neon")] | |
2199 | #[cfg_attr(test, assert_instr(ucvtf, N = 2))] | |
2200 | #[rustc_legacy_const_generics(1)] | |
2201 | pub unsafe fn vcvtq_n_f64_u64<const N: i32>(a: uint64x2_t) -> float64x2_t { | |
2202 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2203 | #[allow(improper_ctypes)] | |
2204 | extern "C" { | |
2205 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64")] | |
2206 | fn vcvtq_n_f64_u64_(a: uint64x2_t, n: i32) -> float64x2_t; | |
2207 | } | |
2208 | vcvtq_n_f64_u64_(a, N) | |
2209 | } | |
2210 | ||
2211 | /// Fixed-point convert to floating-point | |
2212 | #[inline] | |
2213 | #[target_feature(enable = "neon")] | |
2214 | #[cfg_attr(test, assert_instr(ucvtf, N = 2))] | |
2215 | #[rustc_legacy_const_generics(1)] | |
2216 | pub unsafe fn vcvts_n_f32_u32<const N: i32>(a: u32) -> f32 { | |
2217 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
2218 | #[allow(improper_ctypes)] | |
2219 | extern "C" { | |
2220 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfxu2fp.f32.i32")] | |
2221 | fn vcvts_n_f32_u32_(a: u32, n: i32) -> f32; | |
2222 | } | |
2223 | vcvts_n_f32_u32_(a, N) | |
2224 | } | |
2225 | ||
2226 | /// Fixed-point convert to floating-point | |
2227 | #[inline] | |
2228 | #[target_feature(enable = "neon")] | |
2229 | #[cfg_attr(test, assert_instr(ucvtf, N = 2))] | |
2230 | #[rustc_legacy_const_generics(1)] | |
2231 | pub unsafe fn vcvtd_n_f64_u64<const N: i32>(a: u64) -> f64 { | |
2232 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2233 | #[allow(improper_ctypes)] | |
2234 | extern "C" { | |
2235 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfxu2fp.f64.i64")] | |
2236 | fn vcvtd_n_f64_u64_(a: u64, n: i32) -> f64; | |
2237 | } | |
2238 | vcvtd_n_f64_u64_(a, N) | |
2239 | } | |
2240 | ||
2241 | /// Floating-point convert to fixed-point, rounding toward zero | |
2242 | #[inline] | |
2243 | #[target_feature(enable = "neon")] | |
2244 | #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] | |
2245 | #[rustc_legacy_const_generics(1)] | |
2246 | pub unsafe fn vcvt_n_s64_f64<const N: i32>(a: float64x1_t) -> int64x1_t { | |
2247 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2248 | #[allow(improper_ctypes)] | |
2249 | extern "C" { | |
2250 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfp2fxs.v1i64.v1f64")] | |
2251 | fn vcvt_n_s64_f64_(a: float64x1_t, n: i32) -> int64x1_t; | |
2252 | } | |
2253 | vcvt_n_s64_f64_(a, N) | |
2254 | } | |
2255 | ||
2256 | /// Floating-point convert to fixed-point, rounding toward zero | |
2257 | #[inline] | |
2258 | #[target_feature(enable = "neon")] | |
2259 | #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] | |
2260 | #[rustc_legacy_const_generics(1)] | |
2261 | pub unsafe fn vcvtq_n_s64_f64<const N: i32>(a: float64x2_t) -> int64x2_t { | |
2262 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2263 | #[allow(improper_ctypes)] | |
2264 | extern "C" { | |
2265 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfp2fxs.v2i64.v2f64")] | |
2266 | fn vcvtq_n_s64_f64_(a: float64x2_t, n: i32) -> int64x2_t; | |
2267 | } | |
2268 | vcvtq_n_s64_f64_(a, N) | |
2269 | } | |
2270 | ||
2271 | /// Floating-point convert to fixed-point, rounding toward zero | |
2272 | #[inline] | |
2273 | #[target_feature(enable = "neon")] | |
2274 | #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] | |
2275 | #[rustc_legacy_const_generics(1)] | |
2276 | pub unsafe fn vcvts_n_s32_f32<const N: i32>(a: f32) -> i32 { | |
2277 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
2278 | #[allow(improper_ctypes)] | |
2279 | extern "C" { | |
2280 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfp2fxs.i32.f32")] | |
2281 | fn vcvts_n_s32_f32_(a: f32, n: i32) -> i32; | |
2282 | } | |
2283 | vcvts_n_s32_f32_(a, N) | |
2284 | } | |
2285 | ||
2286 | /// Floating-point convert to fixed-point, rounding toward zero | |
2287 | #[inline] | |
2288 | #[target_feature(enable = "neon")] | |
2289 | #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] | |
2290 | #[rustc_legacy_const_generics(1)] | |
2291 | pub unsafe fn vcvtd_n_s64_f64<const N: i32>(a: f64) -> i64 { | |
2292 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2293 | #[allow(improper_ctypes)] | |
2294 | extern "C" { | |
2295 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfp2fxs.i64.f64")] | |
2296 | fn vcvtd_n_s64_f64_(a: f64, n: i32) -> i64; | |
2297 | } | |
2298 | vcvtd_n_s64_f64_(a, N) | |
2299 | } | |
2300 | ||
2301 | /// Floating-point convert to fixed-point, rounding toward zero | |
2302 | #[inline] | |
2303 | #[target_feature(enable = "neon")] | |
2304 | #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] | |
2305 | #[rustc_legacy_const_generics(1)] | |
2306 | pub unsafe fn vcvt_n_u64_f64<const N: i32>(a: float64x1_t) -> uint64x1_t { | |
2307 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2308 | #[allow(improper_ctypes)] | |
2309 | extern "C" { | |
2310 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfp2fxu.v1i64.v1f64")] | |
2311 | fn vcvt_n_u64_f64_(a: float64x1_t, n: i32) -> uint64x1_t; | |
2312 | } | |
2313 | vcvt_n_u64_f64_(a, N) | |
2314 | } | |
2315 | ||
2316 | /// Floating-point convert to fixed-point, rounding toward zero | |
2317 | #[inline] | |
2318 | #[target_feature(enable = "neon")] | |
2319 | #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] | |
2320 | #[rustc_legacy_const_generics(1)] | |
2321 | pub unsafe fn vcvtq_n_u64_f64<const N: i32>(a: float64x2_t) -> uint64x2_t { | |
2322 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2323 | #[allow(improper_ctypes)] | |
2324 | extern "C" { | |
2325 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfp2fxu.v2i64.v2f64")] | |
2326 | fn vcvtq_n_u64_f64_(a: float64x2_t, n: i32) -> uint64x2_t; | |
2327 | } | |
2328 | vcvtq_n_u64_f64_(a, N) | |
2329 | } | |
2330 | ||
2331 | /// Floating-point convert to fixed-point, rounding toward zero | |
2332 | #[inline] | |
2333 | #[target_feature(enable = "neon")] | |
2334 | #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] | |
2335 | #[rustc_legacy_const_generics(1)] | |
2336 | pub unsafe fn vcvts_n_u32_f32<const N: i32>(a: f32) -> u32 { | |
2337 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
2338 | #[allow(improper_ctypes)] | |
2339 | extern "C" { | |
2340 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfp2fxu.i32.f32")] | |
2341 | fn vcvts_n_u32_f32_(a: f32, n: i32) -> u32; | |
2342 | } | |
2343 | vcvts_n_u32_f32_(a, N) | |
2344 | } | |
2345 | ||
2346 | /// Floating-point convert to fixed-point, rounding toward zero | |
2347 | #[inline] | |
2348 | #[target_feature(enable = "neon")] | |
2349 | #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] | |
2350 | #[rustc_legacy_const_generics(1)] | |
2351 | pub unsafe fn vcvtd_n_u64_f64<const N: i32>(a: f64) -> u64 { | |
2352 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
2353 | #[allow(improper_ctypes)] | |
2354 | extern "C" { | |
2355 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.vcvtfp2fxu.i64.f64")] | |
2356 | fn vcvtd_n_u64_f64_(a: f64, n: i32) -> u64; | |
2357 | } | |
2358 | vcvtd_n_u64_f64_(a, N) | |
2359 | } | |
2360 | ||
2361 | /// Fixed-point convert to floating-point | |
2362 | #[inline] | |
2363 | #[target_feature(enable = "neon")] | |
2364 | #[cfg_attr(test, assert_instr(scvtf))] | |
2365 | pub unsafe fn vcvts_f32_s32(a: i32) -> f32 { | |
2366 | a as f32 | |
2367 | } | |
2368 | ||
2369 | /// Fixed-point convert to floating-point | |
2370 | #[inline] | |
2371 | #[target_feature(enable = "neon")] | |
2372 | #[cfg_attr(test, assert_instr(scvtf))] | |
2373 | pub unsafe fn vcvtd_f64_s64(a: i64) -> f64 { | |
2374 | a as f64 | |
2375 | } | |
2376 | ||
2377 | /// Fixed-point convert to floating-point | |
2378 | #[inline] | |
2379 | #[target_feature(enable = "neon")] | |
2380 | #[cfg_attr(test, assert_instr(ucvtf))] | |
2381 | pub unsafe fn vcvts_f32_u32(a: u32) -> f32 { | |
2382 | a as f32 | |
2383 | } | |
2384 | ||
2385 | /// Fixed-point convert to floating-point | |
2386 | #[inline] | |
2387 | #[target_feature(enable = "neon")] | |
2388 | #[cfg_attr(test, assert_instr(ucvtf))] | |
2389 | pub unsafe fn vcvtd_f64_u64(a: u64) -> f64 { | |
2390 | a as f64 | |
2391 | } | |
2392 | ||
2393 | /// Fixed-point convert to floating-point | |
2394 | #[inline] | |
2395 | #[target_feature(enable = "neon")] | |
2396 | #[cfg_attr(test, assert_instr(fcvtzs))] | |
2397 | pub unsafe fn vcvts_s32_f32(a: f32) -> i32 { | |
2398 | a as i32 | |
2399 | } | |
2400 | ||
2401 | /// Fixed-point convert to floating-point | |
2402 | #[inline] | |
2403 | #[target_feature(enable = "neon")] | |
2404 | #[cfg_attr(test, assert_instr(fcvtzs))] | |
2405 | pub unsafe fn vcvtd_s64_f64(a: f64) -> i64 { | |
2406 | a as i64 | |
2407 | } | |
2408 | ||
2409 | /// Fixed-point convert to floating-point | |
2410 | #[inline] | |
2411 | #[target_feature(enable = "neon")] | |
2412 | #[cfg_attr(test, assert_instr(fcvtzu))] | |
2413 | pub unsafe fn vcvts_u32_f32(a: f32) -> u32 { | |
2414 | a as u32 | |
2415 | } | |
2416 | ||
2417 | /// Fixed-point convert to floating-point | |
2418 | #[inline] | |
2419 | #[target_feature(enable = "neon")] | |
2420 | #[cfg_attr(test, assert_instr(fcvtzu))] | |
2421 | pub unsafe fn vcvtd_u64_f64(a: f64) -> u64 { | |
2422 | a as u64 | |
2423 | } | |
2424 | ||
2425 | /// Floating-point convert to signed fixed-point, rounding toward zero | |
2426 | #[inline] | |
2427 | #[target_feature(enable = "neon")] | |
2428 | #[cfg_attr(test, assert_instr(fcvtzs))] | |
2429 | pub unsafe fn vcvt_s64_f64(a: float64x1_t) -> int64x1_t { | |
94222f64 XL |
2430 | #[allow(improper_ctypes)] |
2431 | extern "C" { | |
2432 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fptosi.sat.v1i64.v1f64")] | |
2433 | fn vcvt_s64_f64_(a: float64x1_t) -> int64x1_t; | |
2434 | } | |
2435 | vcvt_s64_f64_(a) | |
17df50a5 XL |
2436 | } |
2437 | ||
2438 | /// Floating-point convert to signed fixed-point, rounding toward zero | |
2439 | #[inline] | |
2440 | #[target_feature(enable = "neon")] | |
2441 | #[cfg_attr(test, assert_instr(fcvtzs))] | |
2442 | pub unsafe fn vcvtq_s64_f64(a: float64x2_t) -> int64x2_t { | |
94222f64 XL |
2443 | #[allow(improper_ctypes)] |
2444 | extern "C" { | |
2445 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fptosi.sat.v2i64.v2f64")] | |
2446 | fn vcvtq_s64_f64_(a: float64x2_t) -> int64x2_t; | |
2447 | } | |
2448 | vcvtq_s64_f64_(a) | |
17df50a5 XL |
2449 | } |
2450 | ||
2451 | /// Floating-point convert to unsigned fixed-point, rounding toward zero | |
2452 | #[inline] | |
2453 | #[target_feature(enable = "neon")] | |
2454 | #[cfg_attr(test, assert_instr(fcvtzu))] | |
2455 | pub unsafe fn vcvt_u64_f64(a: float64x1_t) -> uint64x1_t { | |
94222f64 XL |
2456 | #[allow(improper_ctypes)] |
2457 | extern "C" { | |
2458 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fptoui.sat.v1i64.v1f64")] | |
2459 | fn vcvt_u64_f64_(a: float64x1_t) -> uint64x1_t; | |
2460 | } | |
2461 | vcvt_u64_f64_(a) | |
17df50a5 XL |
2462 | } |
2463 | ||
2464 | /// Floating-point convert to unsigned fixed-point, rounding toward zero | |
2465 | #[inline] | |
2466 | #[target_feature(enable = "neon")] | |
2467 | #[cfg_attr(test, assert_instr(fcvtzu))] | |
2468 | pub unsafe fn vcvtq_u64_f64(a: float64x2_t) -> uint64x2_t { | |
94222f64 XL |
2469 | #[allow(improper_ctypes)] |
2470 | extern "C" { | |
2471 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fptoui.sat.v2i64.v2f64")] | |
2472 | fn vcvtq_u64_f64_(a: float64x2_t) -> uint64x2_t; | |
2473 | } | |
2474 | vcvtq_u64_f64_(a) | |
17df50a5 XL |
2475 | } |
2476 | ||
2477 | /// Floating-point convert to signed integer, rounding to nearest with ties to away | |
2478 | #[inline] | |
2479 | #[target_feature(enable = "neon")] | |
2480 | #[cfg_attr(test, assert_instr(fcvtas))] | |
2481 | pub unsafe fn vcvta_s32_f32(a: float32x2_t) -> int32x2_t { | |
2482 | #[allow(improper_ctypes)] | |
2483 | extern "C" { | |
2484 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtas.v2i32.v2f32")] | |
2485 | fn vcvta_s32_f32_(a: float32x2_t) -> int32x2_t; | |
2486 | } | |
2487 | vcvta_s32_f32_(a) | |
2488 | } | |
2489 | ||
2490 | /// Floating-point convert to signed integer, rounding to nearest with ties to away | |
2491 | #[inline] | |
2492 | #[target_feature(enable = "neon")] | |
2493 | #[cfg_attr(test, assert_instr(fcvtas))] | |
2494 | pub unsafe fn vcvtaq_s32_f32(a: float32x4_t) -> int32x4_t { | |
2495 | #[allow(improper_ctypes)] | |
2496 | extern "C" { | |
2497 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtas.v4i32.v4f32")] | |
2498 | fn vcvtaq_s32_f32_(a: float32x4_t) -> int32x4_t; | |
2499 | } | |
2500 | vcvtaq_s32_f32_(a) | |
2501 | } | |
2502 | ||
2503 | /// Floating-point convert to signed integer, rounding to nearest with ties to away | |
2504 | #[inline] | |
2505 | #[target_feature(enable = "neon")] | |
2506 | #[cfg_attr(test, assert_instr(fcvtas))] | |
2507 | pub unsafe fn vcvta_s64_f64(a: float64x1_t) -> int64x1_t { | |
2508 | #[allow(improper_ctypes)] | |
2509 | extern "C" { | |
2510 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtas.v1i64.v1f64")] | |
2511 | fn vcvta_s64_f64_(a: float64x1_t) -> int64x1_t; | |
2512 | } | |
2513 | vcvta_s64_f64_(a) | |
2514 | } | |
2515 | ||
2516 | /// Floating-point convert to signed integer, rounding to nearest with ties to away | |
2517 | #[inline] | |
2518 | #[target_feature(enable = "neon")] | |
2519 | #[cfg_attr(test, assert_instr(fcvtas))] | |
2520 | pub unsafe fn vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t { | |
2521 | #[allow(improper_ctypes)] | |
2522 | extern "C" { | |
2523 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtas.v2i64.v2f64")] | |
2524 | fn vcvtaq_s64_f64_(a: float64x2_t) -> int64x2_t; | |
2525 | } | |
2526 | vcvtaq_s64_f64_(a) | |
2527 | } | |
2528 | ||
2529 | /// Floating-point convert to integer, rounding to nearest with ties to away | |
2530 | #[inline] | |
2531 | #[target_feature(enable = "neon")] | |
2532 | #[cfg_attr(test, assert_instr(fcvtas))] | |
2533 | pub unsafe fn vcvtas_s32_f32(a: f32) -> i32 { | |
2534 | #[allow(improper_ctypes)] | |
2535 | extern "C" { | |
2536 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtas.i32.f32")] | |
2537 | fn vcvtas_s32_f32_(a: f32) -> i32; | |
2538 | } | |
2539 | vcvtas_s32_f32_(a) | |
2540 | } | |
2541 | ||
2542 | /// Floating-point convert to integer, rounding to nearest with ties to away | |
2543 | #[inline] | |
2544 | #[target_feature(enable = "neon")] | |
2545 | #[cfg_attr(test, assert_instr(fcvtas))] | |
2546 | pub unsafe fn vcvtad_s64_f64(a: f64) -> i64 { | |
2547 | #[allow(improper_ctypes)] | |
2548 | extern "C" { | |
2549 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtas.i64.f64")] | |
2550 | fn vcvtad_s64_f64_(a: f64) -> i64; | |
2551 | } | |
2552 | vcvtad_s64_f64_(a) | |
2553 | } | |
2554 | ||
2555 | /// Floating-point convert to integer, rounding to nearest with ties to away | |
2556 | #[inline] | |
2557 | #[target_feature(enable = "neon")] | |
2558 | #[cfg_attr(test, assert_instr(fcvtau))] | |
2559 | pub unsafe fn vcvtas_u32_f32(a: f32) -> u32 { | |
2560 | #[allow(improper_ctypes)] | |
2561 | extern "C" { | |
2562 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtau.i32.f32")] | |
2563 | fn vcvtas_u32_f32_(a: f32) -> u32; | |
2564 | } | |
2565 | vcvtas_u32_f32_(a) | |
2566 | } | |
2567 | ||
2568 | /// Floating-point convert to integer, rounding to nearest with ties to away | |
2569 | #[inline] | |
2570 | #[target_feature(enable = "neon")] | |
2571 | #[cfg_attr(test, assert_instr(fcvtau))] | |
2572 | pub unsafe fn vcvtad_u64_f64(a: f64) -> u64 { | |
2573 | #[allow(improper_ctypes)] | |
2574 | extern "C" { | |
2575 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtau.i64.f64")] | |
2576 | fn vcvtad_u64_f64_(a: f64) -> u64; | |
2577 | } | |
2578 | vcvtad_u64_f64_(a) | |
2579 | } | |
2580 | ||
2581 | /// Floating-point convert to signed integer, rounding to nearest with ties to even | |
2582 | #[inline] | |
2583 | #[target_feature(enable = "neon")] | |
2584 | #[cfg_attr(test, assert_instr(fcvtns))] | |
2585 | pub unsafe fn vcvtn_s32_f32(a: float32x2_t) -> int32x2_t { | |
2586 | #[allow(improper_ctypes)] | |
2587 | extern "C" { | |
2588 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtns.v2i32.v2f32")] | |
2589 | fn vcvtn_s32_f32_(a: float32x2_t) -> int32x2_t; | |
2590 | } | |
2591 | vcvtn_s32_f32_(a) | |
2592 | } | |
2593 | ||
2594 | /// Floating-point convert to signed integer, rounding to nearest with ties to even | |
2595 | #[inline] | |
2596 | #[target_feature(enable = "neon")] | |
2597 | #[cfg_attr(test, assert_instr(fcvtns))] | |
2598 | pub unsafe fn vcvtnq_s32_f32(a: float32x4_t) -> int32x4_t { | |
2599 | #[allow(improper_ctypes)] | |
2600 | extern "C" { | |
2601 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtns.v4i32.v4f32")] | |
2602 | fn vcvtnq_s32_f32_(a: float32x4_t) -> int32x4_t; | |
2603 | } | |
2604 | vcvtnq_s32_f32_(a) | |
2605 | } | |
2606 | ||
2607 | /// Floating-point convert to signed integer, rounding to nearest with ties to even | |
2608 | #[inline] | |
2609 | #[target_feature(enable = "neon")] | |
2610 | #[cfg_attr(test, assert_instr(fcvtns))] | |
2611 | pub unsafe fn vcvtn_s64_f64(a: float64x1_t) -> int64x1_t { | |
2612 | #[allow(improper_ctypes)] | |
2613 | extern "C" { | |
2614 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtns.v1i64.v1f64")] | |
2615 | fn vcvtn_s64_f64_(a: float64x1_t) -> int64x1_t; | |
2616 | } | |
2617 | vcvtn_s64_f64_(a) | |
2618 | } | |
2619 | ||
2620 | /// Floating-point convert to signed integer, rounding to nearest with ties to even | |
2621 | #[inline] | |
2622 | #[target_feature(enable = "neon")] | |
2623 | #[cfg_attr(test, assert_instr(fcvtns))] | |
2624 | pub unsafe fn vcvtnq_s64_f64(a: float64x2_t) -> int64x2_t { | |
2625 | #[allow(improper_ctypes)] | |
2626 | extern "C" { | |
2627 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtns.v2i64.v2f64")] | |
2628 | fn vcvtnq_s64_f64_(a: float64x2_t) -> int64x2_t; | |
2629 | } | |
2630 | vcvtnq_s64_f64_(a) | |
2631 | } | |
2632 | ||
2633 | /// Floating-point convert to signed integer, rounding to nearest with ties to even | |
2634 | #[inline] | |
2635 | #[target_feature(enable = "neon")] | |
2636 | #[cfg_attr(test, assert_instr(fcvtns))] | |
2637 | pub unsafe fn vcvtns_s32_f32(a: f32) -> i32 { | |
2638 | #[allow(improper_ctypes)] | |
2639 | extern "C" { | |
2640 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtns.i32.f32")] | |
2641 | fn vcvtns_s32_f32_(a: f32) -> i32; | |
2642 | } | |
2643 | vcvtns_s32_f32_(a) | |
2644 | } | |
2645 | ||
2646 | /// Floating-point convert to signed integer, rounding to nearest with ties to even | |
2647 | #[inline] | |
2648 | #[target_feature(enable = "neon")] | |
2649 | #[cfg_attr(test, assert_instr(fcvtns))] | |
2650 | pub unsafe fn vcvtnd_s64_f64(a: f64) -> i64 { | |
2651 | #[allow(improper_ctypes)] | |
2652 | extern "C" { | |
2653 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtns.i64.f64")] | |
2654 | fn vcvtnd_s64_f64_(a: f64) -> i64; | |
2655 | } | |
2656 | vcvtnd_s64_f64_(a) | |
2657 | } | |
2658 | ||
2659 | /// Floating-point convert to signed integer, rounding toward minus infinity | |
2660 | #[inline] | |
2661 | #[target_feature(enable = "neon")] | |
2662 | #[cfg_attr(test, assert_instr(fcvtms))] | |
2663 | pub unsafe fn vcvtm_s32_f32(a: float32x2_t) -> int32x2_t { | |
2664 | #[allow(improper_ctypes)] | |
2665 | extern "C" { | |
2666 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtms.v2i32.v2f32")] | |
2667 | fn vcvtm_s32_f32_(a: float32x2_t) -> int32x2_t; | |
2668 | } | |
2669 | vcvtm_s32_f32_(a) | |
2670 | } | |
2671 | ||
2672 | /// Floating-point convert to signed integer, rounding toward minus infinity | |
2673 | #[inline] | |
2674 | #[target_feature(enable = "neon")] | |
2675 | #[cfg_attr(test, assert_instr(fcvtms))] | |
2676 | pub unsafe fn vcvtmq_s32_f32(a: float32x4_t) -> int32x4_t { | |
2677 | #[allow(improper_ctypes)] | |
2678 | extern "C" { | |
2679 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtms.v4i32.v4f32")] | |
2680 | fn vcvtmq_s32_f32_(a: float32x4_t) -> int32x4_t; | |
2681 | } | |
2682 | vcvtmq_s32_f32_(a) | |
2683 | } | |
2684 | ||
2685 | /// Floating-point convert to signed integer, rounding toward minus infinity | |
2686 | #[inline] | |
2687 | #[target_feature(enable = "neon")] | |
2688 | #[cfg_attr(test, assert_instr(fcvtms))] | |
2689 | pub unsafe fn vcvtm_s64_f64(a: float64x1_t) -> int64x1_t { | |
2690 | #[allow(improper_ctypes)] | |
2691 | extern "C" { | |
2692 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtms.v1i64.v1f64")] | |
2693 | fn vcvtm_s64_f64_(a: float64x1_t) -> int64x1_t; | |
2694 | } | |
2695 | vcvtm_s64_f64_(a) | |
2696 | } | |
2697 | ||
2698 | /// Floating-point convert to signed integer, rounding toward minus infinity | |
2699 | #[inline] | |
2700 | #[target_feature(enable = "neon")] | |
2701 | #[cfg_attr(test, assert_instr(fcvtms))] | |
2702 | pub unsafe fn vcvtmq_s64_f64(a: float64x2_t) -> int64x2_t { | |
2703 | #[allow(improper_ctypes)] | |
2704 | extern "C" { | |
2705 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtms.v2i64.v2f64")] | |
2706 | fn vcvtmq_s64_f64_(a: float64x2_t) -> int64x2_t; | |
2707 | } | |
2708 | vcvtmq_s64_f64_(a) | |
2709 | } | |
2710 | ||
2711 | /// Floating-point convert to signed integer, rounding toward minus infinity | |
2712 | #[inline] | |
2713 | #[target_feature(enable = "neon")] | |
2714 | #[cfg_attr(test, assert_instr(fcvtms))] | |
2715 | pub unsafe fn vcvtms_s32_f32(a: f32) -> i32 { | |
2716 | #[allow(improper_ctypes)] | |
2717 | extern "C" { | |
2718 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtms.i32.f32")] | |
2719 | fn vcvtms_s32_f32_(a: f32) -> i32; | |
2720 | } | |
2721 | vcvtms_s32_f32_(a) | |
2722 | } | |
2723 | ||
2724 | /// Floating-point convert to signed integer, rounding toward minus infinity | |
2725 | #[inline] | |
2726 | #[target_feature(enable = "neon")] | |
2727 | #[cfg_attr(test, assert_instr(fcvtms))] | |
2728 | pub unsafe fn vcvtmd_s64_f64(a: f64) -> i64 { | |
2729 | #[allow(improper_ctypes)] | |
2730 | extern "C" { | |
2731 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtms.i64.f64")] | |
2732 | fn vcvtmd_s64_f64_(a: f64) -> i64; | |
2733 | } | |
2734 | vcvtmd_s64_f64_(a) | |
2735 | } | |
2736 | ||
2737 | /// Floating-point convert to signed integer, rounding toward plus infinity | |
2738 | #[inline] | |
2739 | #[target_feature(enable = "neon")] | |
2740 | #[cfg_attr(test, assert_instr(fcvtps))] | |
2741 | pub unsafe fn vcvtp_s32_f32(a: float32x2_t) -> int32x2_t { | |
2742 | #[allow(improper_ctypes)] | |
2743 | extern "C" { | |
2744 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtps.v2i32.v2f32")] | |
2745 | fn vcvtp_s32_f32_(a: float32x2_t) -> int32x2_t; | |
2746 | } | |
2747 | vcvtp_s32_f32_(a) | |
2748 | } | |
2749 | ||
2750 | /// Floating-point convert to signed integer, rounding toward plus infinity | |
2751 | #[inline] | |
2752 | #[target_feature(enable = "neon")] | |
2753 | #[cfg_attr(test, assert_instr(fcvtps))] | |
2754 | pub unsafe fn vcvtpq_s32_f32(a: float32x4_t) -> int32x4_t { | |
2755 | #[allow(improper_ctypes)] | |
2756 | extern "C" { | |
2757 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtps.v4i32.v4f32")] | |
2758 | fn vcvtpq_s32_f32_(a: float32x4_t) -> int32x4_t; | |
2759 | } | |
2760 | vcvtpq_s32_f32_(a) | |
2761 | } | |
2762 | ||
2763 | /// Floating-point convert to signed integer, rounding toward plus infinity | |
2764 | #[inline] | |
2765 | #[target_feature(enable = "neon")] | |
2766 | #[cfg_attr(test, assert_instr(fcvtps))] | |
2767 | pub unsafe fn vcvtp_s64_f64(a: float64x1_t) -> int64x1_t { | |
2768 | #[allow(improper_ctypes)] | |
2769 | extern "C" { | |
2770 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtps.v1i64.v1f64")] | |
2771 | fn vcvtp_s64_f64_(a: float64x1_t) -> int64x1_t; | |
2772 | } | |
2773 | vcvtp_s64_f64_(a) | |
2774 | } | |
2775 | ||
2776 | /// Floating-point convert to signed integer, rounding toward plus infinity | |
2777 | #[inline] | |
2778 | #[target_feature(enable = "neon")] | |
2779 | #[cfg_attr(test, assert_instr(fcvtps))] | |
2780 | pub unsafe fn vcvtpq_s64_f64(a: float64x2_t) -> int64x2_t { | |
2781 | #[allow(improper_ctypes)] | |
2782 | extern "C" { | |
2783 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtps.v2i64.v2f64")] | |
2784 | fn vcvtpq_s64_f64_(a: float64x2_t) -> int64x2_t; | |
2785 | } | |
2786 | vcvtpq_s64_f64_(a) | |
2787 | } | |
2788 | ||
2789 | /// Floating-point convert to signed integer, rounding toward plus infinity | |
2790 | #[inline] | |
2791 | #[target_feature(enable = "neon")] | |
2792 | #[cfg_attr(test, assert_instr(fcvtps))] | |
2793 | pub unsafe fn vcvtps_s32_f32(a: f32) -> i32 { | |
2794 | #[allow(improper_ctypes)] | |
2795 | extern "C" { | |
2796 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtps.i32.f32")] | |
2797 | fn vcvtps_s32_f32_(a: f32) -> i32; | |
2798 | } | |
2799 | vcvtps_s32_f32_(a) | |
2800 | } | |
2801 | ||
2802 | /// Floating-point convert to signed integer, rounding toward plus infinity | |
2803 | #[inline] | |
2804 | #[target_feature(enable = "neon")] | |
2805 | #[cfg_attr(test, assert_instr(fcvtps))] | |
2806 | pub unsafe fn vcvtpd_s64_f64(a: f64) -> i64 { | |
2807 | #[allow(improper_ctypes)] | |
2808 | extern "C" { | |
2809 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtps.i64.f64")] | |
2810 | fn vcvtpd_s64_f64_(a: f64) -> i64; | |
2811 | } | |
2812 | vcvtpd_s64_f64_(a) | |
2813 | } | |
2814 | ||
2815 | /// Floating-point convert to unsigned integer, rounding to nearest with ties to away | |
2816 | #[inline] | |
2817 | #[target_feature(enable = "neon")] | |
2818 | #[cfg_attr(test, assert_instr(fcvtau))] | |
2819 | pub unsafe fn vcvta_u32_f32(a: float32x2_t) -> uint32x2_t { | |
2820 | #[allow(improper_ctypes)] | |
2821 | extern "C" { | |
2822 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtau.v2i32.v2f32")] | |
2823 | fn vcvta_u32_f32_(a: float32x2_t) -> uint32x2_t; | |
2824 | } | |
2825 | vcvta_u32_f32_(a) | |
2826 | } | |
2827 | ||
2828 | /// Floating-point convert to unsigned integer, rounding to nearest with ties to away | |
2829 | #[inline] | |
2830 | #[target_feature(enable = "neon")] | |
2831 | #[cfg_attr(test, assert_instr(fcvtau))] | |
2832 | pub unsafe fn vcvtaq_u32_f32(a: float32x4_t) -> uint32x4_t { | |
2833 | #[allow(improper_ctypes)] | |
2834 | extern "C" { | |
2835 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtau.v4i32.v4f32")] | |
2836 | fn vcvtaq_u32_f32_(a: float32x4_t) -> uint32x4_t; | |
2837 | } | |
2838 | vcvtaq_u32_f32_(a) | |
2839 | } | |
2840 | ||
2841 | /// Floating-point convert to unsigned integer, rounding to nearest with ties to away | |
2842 | #[inline] | |
2843 | #[target_feature(enable = "neon")] | |
2844 | #[cfg_attr(test, assert_instr(fcvtau))] | |
2845 | pub unsafe fn vcvta_u64_f64(a: float64x1_t) -> uint64x1_t { | |
2846 | #[allow(improper_ctypes)] | |
2847 | extern "C" { | |
2848 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtau.v1i64.v1f64")] | |
2849 | fn vcvta_u64_f64_(a: float64x1_t) -> uint64x1_t; | |
2850 | } | |
2851 | vcvta_u64_f64_(a) | |
2852 | } | |
2853 | ||
2854 | /// Floating-point convert to unsigned integer, rounding to nearest with ties to away | |
2855 | #[inline] | |
2856 | #[target_feature(enable = "neon")] | |
2857 | #[cfg_attr(test, assert_instr(fcvtau))] | |
2858 | pub unsafe fn vcvtaq_u64_f64(a: float64x2_t) -> uint64x2_t { | |
2859 | #[allow(improper_ctypes)] | |
2860 | extern "C" { | |
2861 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtau.v2i64.v2f64")] | |
2862 | fn vcvtaq_u64_f64_(a: float64x2_t) -> uint64x2_t; | |
2863 | } | |
2864 | vcvtaq_u64_f64_(a) | |
2865 | } | |
2866 | ||
2867 | /// Floating-point convert to unsigned integer, rounding to nearest with ties to even | |
2868 | #[inline] | |
2869 | #[target_feature(enable = "neon")] | |
2870 | #[cfg_attr(test, assert_instr(fcvtnu))] | |
2871 | pub unsafe fn vcvtn_u32_f32(a: float32x2_t) -> uint32x2_t { | |
2872 | #[allow(improper_ctypes)] | |
2873 | extern "C" { | |
2874 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtnu.v2i32.v2f32")] | |
2875 | fn vcvtn_u32_f32_(a: float32x2_t) -> uint32x2_t; | |
2876 | } | |
2877 | vcvtn_u32_f32_(a) | |
2878 | } | |
2879 | ||
2880 | /// Floating-point convert to unsigned integer, rounding to nearest with ties to even | |
2881 | #[inline] | |
2882 | #[target_feature(enable = "neon")] | |
2883 | #[cfg_attr(test, assert_instr(fcvtnu))] | |
2884 | pub unsafe fn vcvtnq_u32_f32(a: float32x4_t) -> uint32x4_t { | |
2885 | #[allow(improper_ctypes)] | |
2886 | extern "C" { | |
2887 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtnu.v4i32.v4f32")] | |
2888 | fn vcvtnq_u32_f32_(a: float32x4_t) -> uint32x4_t; | |
2889 | } | |
2890 | vcvtnq_u32_f32_(a) | |
2891 | } | |
2892 | ||
2893 | /// Floating-point convert to unsigned integer, rounding to nearest with ties to even | |
2894 | #[inline] | |
2895 | #[target_feature(enable = "neon")] | |
2896 | #[cfg_attr(test, assert_instr(fcvtnu))] | |
2897 | pub unsafe fn vcvtn_u64_f64(a: float64x1_t) -> uint64x1_t { | |
2898 | #[allow(improper_ctypes)] | |
2899 | extern "C" { | |
2900 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtnu.v1i64.v1f64")] | |
2901 | fn vcvtn_u64_f64_(a: float64x1_t) -> uint64x1_t; | |
2902 | } | |
2903 | vcvtn_u64_f64_(a) | |
2904 | } | |
2905 | ||
2906 | /// Floating-point convert to unsigned integer, rounding to nearest with ties to even | |
2907 | #[inline] | |
2908 | #[target_feature(enable = "neon")] | |
2909 | #[cfg_attr(test, assert_instr(fcvtnu))] | |
2910 | pub unsafe fn vcvtnq_u64_f64(a: float64x2_t) -> uint64x2_t { | |
2911 | #[allow(improper_ctypes)] | |
2912 | extern "C" { | |
2913 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtnu.v2i64.v2f64")] | |
2914 | fn vcvtnq_u64_f64_(a: float64x2_t) -> uint64x2_t; | |
2915 | } | |
2916 | vcvtnq_u64_f64_(a) | |
2917 | } | |
2918 | ||
2919 | /// Floating-point convert to unsigned integer, rounding to nearest with ties to even | |
2920 | #[inline] | |
2921 | #[target_feature(enable = "neon")] | |
2922 | #[cfg_attr(test, assert_instr(fcvtnu))] | |
2923 | pub unsafe fn vcvtns_u32_f32(a: f32) -> u32 { | |
2924 | #[allow(improper_ctypes)] | |
2925 | extern "C" { | |
2926 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtnu.i32.f32")] | |
2927 | fn vcvtns_u32_f32_(a: f32) -> u32; | |
2928 | } | |
2929 | vcvtns_u32_f32_(a) | |
2930 | } | |
2931 | ||
2932 | /// Floating-point convert to unsigned integer, rounding to nearest with ties to even | |
2933 | #[inline] | |
2934 | #[target_feature(enable = "neon")] | |
2935 | #[cfg_attr(test, assert_instr(fcvtnu))] | |
2936 | pub unsafe fn vcvtnd_u64_f64(a: f64) -> u64 { | |
2937 | #[allow(improper_ctypes)] | |
2938 | extern "C" { | |
2939 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtnu.i64.f64")] | |
2940 | fn vcvtnd_u64_f64_(a: f64) -> u64; | |
2941 | } | |
2942 | vcvtnd_u64_f64_(a) | |
2943 | } | |
2944 | ||
2945 | /// Floating-point convert to unsigned integer, rounding toward minus infinity | |
2946 | #[inline] | |
2947 | #[target_feature(enable = "neon")] | |
2948 | #[cfg_attr(test, assert_instr(fcvtmu))] | |
2949 | pub unsafe fn vcvtm_u32_f32(a: float32x2_t) -> uint32x2_t { | |
2950 | #[allow(improper_ctypes)] | |
2951 | extern "C" { | |
2952 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtmu.v2i32.v2f32")] | |
2953 | fn vcvtm_u32_f32_(a: float32x2_t) -> uint32x2_t; | |
2954 | } | |
2955 | vcvtm_u32_f32_(a) | |
2956 | } | |
2957 | ||
2958 | /// Floating-point convert to unsigned integer, rounding toward minus infinity | |
2959 | #[inline] | |
2960 | #[target_feature(enable = "neon")] | |
2961 | #[cfg_attr(test, assert_instr(fcvtmu))] | |
2962 | pub unsafe fn vcvtmq_u32_f32(a: float32x4_t) -> uint32x4_t { | |
2963 | #[allow(improper_ctypes)] | |
2964 | extern "C" { | |
2965 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtmu.v4i32.v4f32")] | |
2966 | fn vcvtmq_u32_f32_(a: float32x4_t) -> uint32x4_t; | |
2967 | } | |
2968 | vcvtmq_u32_f32_(a) | |
2969 | } | |
2970 | ||
2971 | /// Floating-point convert to unsigned integer, rounding toward minus infinity | |
2972 | #[inline] | |
2973 | #[target_feature(enable = "neon")] | |
2974 | #[cfg_attr(test, assert_instr(fcvtmu))] | |
2975 | pub unsafe fn vcvtm_u64_f64(a: float64x1_t) -> uint64x1_t { | |
2976 | #[allow(improper_ctypes)] | |
2977 | extern "C" { | |
2978 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtmu.v1i64.v1f64")] | |
2979 | fn vcvtm_u64_f64_(a: float64x1_t) -> uint64x1_t; | |
2980 | } | |
2981 | vcvtm_u64_f64_(a) | |
2982 | } | |
2983 | ||
2984 | /// Floating-point convert to unsigned integer, rounding toward minus infinity | |
2985 | #[inline] | |
2986 | #[target_feature(enable = "neon")] | |
2987 | #[cfg_attr(test, assert_instr(fcvtmu))] | |
2988 | pub unsafe fn vcvtmq_u64_f64(a: float64x2_t) -> uint64x2_t { | |
2989 | #[allow(improper_ctypes)] | |
2990 | extern "C" { | |
2991 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtmu.v2i64.v2f64")] | |
2992 | fn vcvtmq_u64_f64_(a: float64x2_t) -> uint64x2_t; | |
2993 | } | |
2994 | vcvtmq_u64_f64_(a) | |
2995 | } | |
2996 | ||
2997 | /// Floating-point convert to unsigned integer, rounding toward minus infinity | |
2998 | #[inline] | |
2999 | #[target_feature(enable = "neon")] | |
3000 | #[cfg_attr(test, assert_instr(fcvtmu))] | |
3001 | pub unsafe fn vcvtms_u32_f32(a: f32) -> u32 { | |
3002 | #[allow(improper_ctypes)] | |
3003 | extern "C" { | |
3004 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtmu.i32.f32")] | |
3005 | fn vcvtms_u32_f32_(a: f32) -> u32; | |
3006 | } | |
3007 | vcvtms_u32_f32_(a) | |
3008 | } | |
3009 | ||
3010 | /// Floating-point convert to unsigned integer, rounding toward minus infinity | |
3011 | #[inline] | |
3012 | #[target_feature(enable = "neon")] | |
3013 | #[cfg_attr(test, assert_instr(fcvtmu))] | |
3014 | pub unsafe fn vcvtmd_u64_f64(a: f64) -> u64 { | |
3015 | #[allow(improper_ctypes)] | |
3016 | extern "C" { | |
3017 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtmu.i64.f64")] | |
3018 | fn vcvtmd_u64_f64_(a: f64) -> u64; | |
3019 | } | |
3020 | vcvtmd_u64_f64_(a) | |
3021 | } | |
3022 | ||
3023 | /// Floating-point convert to unsigned integer, rounding toward plus infinity | |
3024 | #[inline] | |
3025 | #[target_feature(enable = "neon")] | |
3026 | #[cfg_attr(test, assert_instr(fcvtpu))] | |
3027 | pub unsafe fn vcvtp_u32_f32(a: float32x2_t) -> uint32x2_t { | |
3028 | #[allow(improper_ctypes)] | |
3029 | extern "C" { | |
3030 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtpu.v2i32.v2f32")] | |
3031 | fn vcvtp_u32_f32_(a: float32x2_t) -> uint32x2_t; | |
3032 | } | |
3033 | vcvtp_u32_f32_(a) | |
3034 | } | |
3035 | ||
3036 | /// Floating-point convert to unsigned integer, rounding toward plus infinity | |
3037 | #[inline] | |
3038 | #[target_feature(enable = "neon")] | |
3039 | #[cfg_attr(test, assert_instr(fcvtpu))] | |
3040 | pub unsafe fn vcvtpq_u32_f32(a: float32x4_t) -> uint32x4_t { | |
3041 | #[allow(improper_ctypes)] | |
3042 | extern "C" { | |
3043 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtpu.v4i32.v4f32")] | |
3044 | fn vcvtpq_u32_f32_(a: float32x4_t) -> uint32x4_t; | |
3045 | } | |
3046 | vcvtpq_u32_f32_(a) | |
3047 | } | |
3048 | ||
3049 | /// Floating-point convert to unsigned integer, rounding toward plus infinity | |
3050 | #[inline] | |
3051 | #[target_feature(enable = "neon")] | |
3052 | #[cfg_attr(test, assert_instr(fcvtpu))] | |
3053 | pub unsafe fn vcvtp_u64_f64(a: float64x1_t) -> uint64x1_t { | |
3054 | #[allow(improper_ctypes)] | |
3055 | extern "C" { | |
3056 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtpu.v1i64.v1f64")] | |
3057 | fn vcvtp_u64_f64_(a: float64x1_t) -> uint64x1_t; | |
3058 | } | |
3059 | vcvtp_u64_f64_(a) | |
3060 | } | |
3061 | ||
3062 | /// Floating-point convert to unsigned integer, rounding toward plus infinity | |
3063 | #[inline] | |
3064 | #[target_feature(enable = "neon")] | |
3065 | #[cfg_attr(test, assert_instr(fcvtpu))] | |
3066 | pub unsafe fn vcvtpq_u64_f64(a: float64x2_t) -> uint64x2_t { | |
3067 | #[allow(improper_ctypes)] | |
3068 | extern "C" { | |
3069 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtpu.v2i64.v2f64")] | |
3070 | fn vcvtpq_u64_f64_(a: float64x2_t) -> uint64x2_t; | |
3071 | } | |
3072 | vcvtpq_u64_f64_(a) | |
3073 | } | |
3074 | ||
3075 | /// Floating-point convert to unsigned integer, rounding toward plus infinity | |
3076 | #[inline] | |
3077 | #[target_feature(enable = "neon")] | |
3078 | #[cfg_attr(test, assert_instr(fcvtpu))] | |
3079 | pub unsafe fn vcvtps_u32_f32(a: f32) -> u32 { | |
3080 | #[allow(improper_ctypes)] | |
3081 | extern "C" { | |
3082 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtpu.i32.f32")] | |
3083 | fn vcvtps_u32_f32_(a: f32) -> u32; | |
3084 | } | |
3085 | vcvtps_u32_f32_(a) | |
3086 | } | |
3087 | ||
3088 | /// Floating-point convert to unsigned integer, rounding toward plus infinity | |
3089 | #[inline] | |
3090 | #[target_feature(enable = "neon")] | |
3091 | #[cfg_attr(test, assert_instr(fcvtpu))] | |
3092 | pub unsafe fn vcvtpd_u64_f64(a: f64) -> u64 { | |
3093 | #[allow(improper_ctypes)] | |
3094 | extern "C" { | |
3095 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fcvtpu.i64.f64")] | |
3096 | fn vcvtpd_u64_f64_(a: f64) -> u64; | |
3097 | } | |
3098 | vcvtpd_u64_f64_(a) | |
3099 | } | |
3100 | ||
3101 | /// Set all vector lanes to the same value | |
3102 | #[inline] | |
3103 | #[target_feature(enable = "neon")] | |
3104 | #[cfg_attr(test, assert_instr(dup, N = 1))] | |
3105 | #[rustc_legacy_const_generics(1)] | |
3106 | pub unsafe fn vdupq_laneq_p64<const N: i32>(a: poly64x2_t) -> poly64x2_t { | |
3107 | static_assert_imm1!(N); | |
3108 | simd_shuffle2!(a, a, <const N: i32> [N as u32, N as u32]) | |
3109 | } | |
3110 | ||
3111 | /// Set all vector lanes to the same value | |
3112 | #[inline] | |
3113 | #[target_feature(enable = "neon")] | |
3114 | #[cfg_attr(test, assert_instr(dup, N = 0))] | |
3115 | #[rustc_legacy_const_generics(1)] | |
3116 | pub unsafe fn vdupq_lane_p64<const N: i32>(a: poly64x1_t) -> poly64x2_t { | |
3117 | static_assert!(N : i32 where N == 0); | |
3118 | simd_shuffle2!(a, a, <const N: i32> [N as u32, N as u32]) | |
3119 | } | |
3120 | ||
3121 | /// Set all vector lanes to the same value | |
3122 | #[inline] | |
3123 | #[target_feature(enable = "neon")] | |
3124 | #[cfg_attr(test, assert_instr(dup, N = 1))] | |
3125 | #[rustc_legacy_const_generics(1)] | |
3126 | pub unsafe fn vdupq_laneq_f64<const N: i32>(a: float64x2_t) -> float64x2_t { | |
3127 | static_assert_imm1!(N); | |
3128 | simd_shuffle2!(a, a, <const N: i32> [N as u32, N as u32]) | |
3129 | } | |
3130 | ||
3131 | /// Set all vector lanes to the same value | |
3132 | #[inline] | |
3133 | #[target_feature(enable = "neon")] | |
3134 | #[cfg_attr(test, assert_instr(dup, N = 0))] | |
3135 | #[rustc_legacy_const_generics(1)] | |
3136 | pub unsafe fn vdupq_lane_f64<const N: i32>(a: float64x1_t) -> float64x2_t { | |
3137 | static_assert!(N : i32 where N == 0); | |
3138 | simd_shuffle2!(a, a, <const N: i32> [N as u32, N as u32]) | |
3139 | } | |
3140 | ||
3141 | /// Set all vector lanes to the same value | |
3142 | #[inline] | |
3143 | #[target_feature(enable = "neon")] | |
3144 | #[cfg_attr(test, assert_instr(nop, N = 0))] | |
3145 | #[rustc_legacy_const_generics(1)] | |
3146 | pub unsafe fn vdup_lane_p64<const N: i32>(a: poly64x1_t) -> poly64x1_t { | |
3147 | static_assert!(N : i32 where N == 0); | |
3148 | a | |
3149 | } | |
3150 | ||
3151 | /// Set all vector lanes to the same value | |
3152 | #[inline] | |
3153 | #[target_feature(enable = "neon")] | |
3154 | #[cfg_attr(test, assert_instr(nop, N = 0))] | |
3155 | #[rustc_legacy_const_generics(1)] | |
3156 | pub unsafe fn vdup_lane_f64<const N: i32>(a: float64x1_t) -> float64x1_t { | |
3157 | static_assert!(N : i32 where N == 0); | |
3158 | a | |
3159 | } | |
3160 | ||
3161 | /// Set all vector lanes to the same value | |
3162 | #[inline] | |
3163 | #[target_feature(enable = "neon")] | |
3164 | #[cfg_attr(test, assert_instr(nop, N = 1))] | |
3165 | #[rustc_legacy_const_generics(1)] | |
3166 | pub unsafe fn vdup_laneq_p64<const N: i32>(a: poly64x2_t) -> poly64x1_t { | |
3167 | static_assert_imm1!(N); | |
3168 | transmute::<u64, _>(simd_extract(a, N as u32)) | |
3169 | } | |
3170 | ||
3171 | /// Set all vector lanes to the same value | |
3172 | #[inline] | |
3173 | #[target_feature(enable = "neon")] | |
3174 | #[cfg_attr(test, assert_instr(nop, N = 1))] | |
3175 | #[rustc_legacy_const_generics(1)] | |
3176 | pub unsafe fn vdup_laneq_f64<const N: i32>(a: float64x2_t) -> float64x1_t { | |
3177 | static_assert_imm1!(N); | |
3178 | transmute::<f64, _>(simd_extract(a, N as u32)) | |
3179 | } | |
3180 | ||
3181 | /// Set all vector lanes to the same value | |
3182 | #[inline] | |
3183 | #[target_feature(enable = "neon")] | |
3184 | #[cfg_attr(test, assert_instr(nop, N = 4))] | |
3185 | #[rustc_legacy_const_generics(1)] | |
3186 | pub unsafe fn vdupb_lane_s8<const N: i32>(a: int8x8_t) -> i8 { | |
3187 | static_assert_imm3!(N); | |
3188 | simd_extract(a, N as u32) | |
3189 | } | |
3190 | ||
3191 | /// Set all vector lanes to the same value | |
3192 | #[inline] | |
3193 | #[target_feature(enable = "neon")] | |
3194 | #[cfg_attr(test, assert_instr(nop, N = 8))] | |
3195 | #[rustc_legacy_const_generics(1)] | |
3196 | pub unsafe fn vdupb_laneq_s8<const N: i32>(a: int8x16_t) -> i8 { | |
3197 | static_assert_imm4!(N); | |
3198 | simd_extract(a, N as u32) | |
3199 | } | |
3200 | ||
3201 | /// Set all vector lanes to the same value | |
3202 | #[inline] | |
3203 | #[target_feature(enable = "neon")] | |
3204 | #[cfg_attr(test, assert_instr(nop, N = 2))] | |
3205 | #[rustc_legacy_const_generics(1)] | |
3206 | pub unsafe fn vduph_lane_s16<const N: i32>(a: int16x4_t) -> i16 { | |
3207 | static_assert_imm2!(N); | |
3208 | simd_extract(a, N as u32) | |
3209 | } | |
3210 | ||
3211 | /// Set all vector lanes to the same value | |
3212 | #[inline] | |
3213 | #[target_feature(enable = "neon")] | |
3214 | #[cfg_attr(test, assert_instr(nop, N = 4))] | |
3215 | #[rustc_legacy_const_generics(1)] | |
3216 | pub unsafe fn vduph_laneq_s16<const N: i32>(a: int16x8_t) -> i16 { | |
3217 | static_assert_imm3!(N); | |
3218 | simd_extract(a, N as u32) | |
3219 | } | |
3220 | ||
3221 | /// Set all vector lanes to the same value | |
3222 | #[inline] | |
3223 | #[target_feature(enable = "neon")] | |
3224 | #[cfg_attr(test, assert_instr(nop, N = 1))] | |
3225 | #[rustc_legacy_const_generics(1)] | |
3226 | pub unsafe fn vdups_lane_s32<const N: i32>(a: int32x2_t) -> i32 { | |
3227 | static_assert_imm1!(N); | |
3228 | simd_extract(a, N as u32) | |
3229 | } | |
3230 | ||
3231 | /// Set all vector lanes to the same value | |
3232 | #[inline] | |
3233 | #[target_feature(enable = "neon")] | |
3234 | #[cfg_attr(test, assert_instr(nop, N = 2))] | |
3235 | #[rustc_legacy_const_generics(1)] | |
3236 | pub unsafe fn vdups_laneq_s32<const N: i32>(a: int32x4_t) -> i32 { | |
3237 | static_assert_imm2!(N); | |
3238 | simd_extract(a, N as u32) | |
3239 | } | |
3240 | ||
3241 | /// Set all vector lanes to the same value | |
3242 | #[inline] | |
3243 | #[target_feature(enable = "neon")] | |
3244 | #[cfg_attr(test, assert_instr(nop, N = 0))] | |
3245 | #[rustc_legacy_const_generics(1)] | |
3246 | pub unsafe fn vdupd_lane_s64<const N: i32>(a: int64x1_t) -> i64 { | |
3247 | static_assert!(N : i32 where N == 0); | |
3248 | simd_extract(a, N as u32) | |
3249 | } | |
3250 | ||
3251 | /// Set all vector lanes to the same value | |
3252 | #[inline] | |
3253 | #[target_feature(enable = "neon")] | |
3254 | #[cfg_attr(test, assert_instr(nop, N = 1))] | |
3255 | #[rustc_legacy_const_generics(1)] | |
3256 | pub unsafe fn vdupd_laneq_s64<const N: i32>(a: int64x2_t) -> i64 { | |
3257 | static_assert_imm1!(N); | |
3258 | simd_extract(a, N as u32) | |
3259 | } | |
3260 | ||
3261 | /// Set all vector lanes to the same value | |
3262 | #[inline] | |
3263 | #[target_feature(enable = "neon")] | |
3264 | #[cfg_attr(test, assert_instr(nop, N = 4))] | |
3265 | #[rustc_legacy_const_generics(1)] | |
3266 | pub unsafe fn vdupb_lane_u8<const N: i32>(a: uint8x8_t) -> u8 { | |
3267 | static_assert_imm3!(N); | |
3268 | simd_extract(a, N as u32) | |
3269 | } | |
3270 | ||
3271 | /// Set all vector lanes to the same value | |
3272 | #[inline] | |
3273 | #[target_feature(enable = "neon")] | |
3274 | #[cfg_attr(test, assert_instr(nop, N = 8))] | |
3275 | #[rustc_legacy_const_generics(1)] | |
3276 | pub unsafe fn vdupb_laneq_u8<const N: i32>(a: uint8x16_t) -> u8 { | |
3277 | static_assert_imm4!(N); | |
3278 | simd_extract(a, N as u32) | |
3279 | } | |
3280 | ||
3281 | /// Set all vector lanes to the same value | |
3282 | #[inline] | |
3283 | #[target_feature(enable = "neon")] | |
3284 | #[cfg_attr(test, assert_instr(nop, N = 2))] | |
3285 | #[rustc_legacy_const_generics(1)] | |
3286 | pub unsafe fn vduph_lane_u16<const N: i32>(a: uint16x4_t) -> u16 { | |
3287 | static_assert_imm2!(N); | |
3288 | simd_extract(a, N as u32) | |
3289 | } | |
3290 | ||
3291 | /// Set all vector lanes to the same value | |
3292 | #[inline] | |
3293 | #[target_feature(enable = "neon")] | |
3294 | #[cfg_attr(test, assert_instr(nop, N = 4))] | |
3295 | #[rustc_legacy_const_generics(1)] | |
3296 | pub unsafe fn vduph_laneq_u16<const N: i32>(a: uint16x8_t) -> u16 { | |
3297 | static_assert_imm3!(N); | |
3298 | simd_extract(a, N as u32) | |
3299 | } | |
3300 | ||
3301 | /// Set all vector lanes to the same value | |
3302 | #[inline] | |
3303 | #[target_feature(enable = "neon")] | |
3304 | #[cfg_attr(test, assert_instr(nop, N = 1))] | |
3305 | #[rustc_legacy_const_generics(1)] | |
3306 | pub unsafe fn vdups_lane_u32<const N: i32>(a: uint32x2_t) -> u32 { | |
3307 | static_assert_imm1!(N); | |
3308 | simd_extract(a, N as u32) | |
3309 | } | |
3310 | ||
3311 | /// Set all vector lanes to the same value | |
3312 | #[inline] | |
3313 | #[target_feature(enable = "neon")] | |
3314 | #[cfg_attr(test, assert_instr(nop, N = 2))] | |
3315 | #[rustc_legacy_const_generics(1)] | |
3316 | pub unsafe fn vdups_laneq_u32<const N: i32>(a: uint32x4_t) -> u32 { | |
3317 | static_assert_imm2!(N); | |
3318 | simd_extract(a, N as u32) | |
3319 | } | |
3320 | ||
3321 | /// Set all vector lanes to the same value | |
3322 | #[inline] | |
3323 | #[target_feature(enable = "neon")] | |
3324 | #[cfg_attr(test, assert_instr(nop, N = 0))] | |
3325 | #[rustc_legacy_const_generics(1)] | |
3326 | pub unsafe fn vdupd_lane_u64<const N: i32>(a: uint64x1_t) -> u64 { | |
3327 | static_assert!(N : i32 where N == 0); | |
3328 | simd_extract(a, N as u32) | |
3329 | } | |
3330 | ||
3331 | /// Set all vector lanes to the same value | |
3332 | #[inline] | |
3333 | #[target_feature(enable = "neon")] | |
3334 | #[cfg_attr(test, assert_instr(nop, N = 1))] | |
3335 | #[rustc_legacy_const_generics(1)] | |
3336 | pub unsafe fn vdupd_laneq_u64<const N: i32>(a: uint64x2_t) -> u64 { | |
3337 | static_assert_imm1!(N); | |
3338 | simd_extract(a, N as u32) | |
3339 | } | |
3340 | ||
3341 | /// Set all vector lanes to the same value | |
3342 | #[inline] | |
3343 | #[target_feature(enable = "neon")] | |
3344 | #[cfg_attr(test, assert_instr(nop, N = 4))] | |
3345 | #[rustc_legacy_const_generics(1)] | |
3346 | pub unsafe fn vdupb_lane_p8<const N: i32>(a: poly8x8_t) -> p8 { | |
3347 | static_assert_imm3!(N); | |
3348 | simd_extract(a, N as u32) | |
3349 | } | |
3350 | ||
3351 | /// Set all vector lanes to the same value | |
3352 | #[inline] | |
3353 | #[target_feature(enable = "neon")] | |
3354 | #[cfg_attr(test, assert_instr(nop, N = 8))] | |
3355 | #[rustc_legacy_const_generics(1)] | |
3356 | pub unsafe fn vdupb_laneq_p8<const N: i32>(a: poly8x16_t) -> p8 { | |
3357 | static_assert_imm4!(N); | |
3358 | simd_extract(a, N as u32) | |
3359 | } | |
3360 | ||
3361 | /// Set all vector lanes to the same value | |
3362 | #[inline] | |
3363 | #[target_feature(enable = "neon")] | |
3364 | #[cfg_attr(test, assert_instr(nop, N = 2))] | |
3365 | #[rustc_legacy_const_generics(1)] | |
3366 | pub unsafe fn vduph_lane_p16<const N: i32>(a: poly16x4_t) -> p16 { | |
3367 | static_assert_imm2!(N); | |
3368 | simd_extract(a, N as u32) | |
3369 | } | |
3370 | ||
3371 | /// Set all vector lanes to the same value | |
3372 | #[inline] | |
3373 | #[target_feature(enable = "neon")] | |
3374 | #[cfg_attr(test, assert_instr(nop, N = 4))] | |
3375 | #[rustc_legacy_const_generics(1)] | |
3376 | pub unsafe fn vduph_laneq_p16<const N: i32>(a: poly16x8_t) -> p16 { | |
3377 | static_assert_imm3!(N); | |
3378 | simd_extract(a, N as u32) | |
3379 | } | |
3380 | ||
3381 | /// Set all vector lanes to the same value | |
3382 | #[inline] | |
3383 | #[target_feature(enable = "neon")] | |
3384 | #[cfg_attr(test, assert_instr(nop, N = 1))] | |
3385 | #[rustc_legacy_const_generics(1)] | |
3386 | pub unsafe fn vdups_lane_f32<const N: i32>(a: float32x2_t) -> f32 { | |
3387 | static_assert_imm1!(N); | |
3388 | simd_extract(a, N as u32) | |
3389 | } | |
3390 | ||
3391 | /// Set all vector lanes to the same value | |
3392 | #[inline] | |
3393 | #[target_feature(enable = "neon")] | |
3394 | #[cfg_attr(test, assert_instr(nop, N = 2))] | |
3395 | #[rustc_legacy_const_generics(1)] | |
3396 | pub unsafe fn vdups_laneq_f32<const N: i32>(a: float32x4_t) -> f32 { | |
3397 | static_assert_imm2!(N); | |
3398 | simd_extract(a, N as u32) | |
3399 | } | |
3400 | ||
3401 | /// Set all vector lanes to the same value | |
3402 | #[inline] | |
3403 | #[target_feature(enable = "neon")] | |
3404 | #[cfg_attr(test, assert_instr(nop, N = 0))] | |
3405 | #[rustc_legacy_const_generics(1)] | |
3406 | pub unsafe fn vdupd_lane_f64<const N: i32>(a: float64x1_t) -> f64 { | |
3407 | static_assert!(N : i32 where N == 0); | |
3408 | simd_extract(a, N as u32) | |
3409 | } | |
3410 | ||
3411 | /// Set all vector lanes to the same value | |
3412 | #[inline] | |
3413 | #[target_feature(enable = "neon")] | |
3414 | #[cfg_attr(test, assert_instr(nop, N = 1))] | |
3415 | #[rustc_legacy_const_generics(1)] | |
3416 | pub unsafe fn vdupd_laneq_f64<const N: i32>(a: float64x2_t) -> f64 { | |
3417 | static_assert_imm1!(N); | |
3418 | simd_extract(a, N as u32) | |
3419 | } | |
3420 | ||
3421 | /// Extract vector from pair of vectors | |
3422 | #[inline] | |
3423 | #[target_feature(enable = "neon")] | |
3424 | #[cfg_attr(test, assert_instr(ext, N = 1))] | |
3425 | #[rustc_legacy_const_generics(2)] | |
3426 | pub unsafe fn vextq_p64<const N: i32>(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { | |
3427 | static_assert_imm1!(N); | |
3428 | match N & 0b1 { | |
3429 | 0 => simd_shuffle2!(a, b, [0, 1]), | |
3430 | 1 => simd_shuffle2!(a, b, [1, 2]), | |
3431 | _ => unreachable_unchecked(), | |
3432 | } | |
3433 | } | |
3434 | ||
3435 | /// Extract vector from pair of vectors | |
3436 | #[inline] | |
3437 | #[target_feature(enable = "neon")] | |
3438 | #[cfg_attr(test, assert_instr(ext, N = 1))] | |
3439 | #[rustc_legacy_const_generics(2)] | |
3440 | pub unsafe fn vextq_f64<const N: i32>(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
3441 | static_assert_imm1!(N); | |
3442 | match N & 0b1 { | |
3443 | 0 => simd_shuffle2!(a, b, [0, 1]), | |
3444 | 1 => simd_shuffle2!(a, b, [1, 2]), | |
3445 | _ => unreachable_unchecked(), | |
3446 | } | |
3447 | } | |
3448 | ||
3449 | /// Floating-point multiply-add to accumulator | |
3450 | #[inline] | |
3451 | #[target_feature(enable = "neon")] | |
3452 | #[cfg_attr(test, assert_instr(fmul))] | |
3453 | pub unsafe fn vmla_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { | |
3454 | simd_add(a, simd_mul(b, c)) | |
3455 | } | |
3456 | ||
3457 | /// Floating-point multiply-add to accumulator | |
3458 | #[inline] | |
3459 | #[target_feature(enable = "neon")] | |
3460 | #[cfg_attr(test, assert_instr(fmul))] | |
3461 | pub unsafe fn vmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { | |
3462 | simd_add(a, simd_mul(b, c)) | |
3463 | } | |
3464 | ||
3465 | /// Signed multiply-add long | |
3466 | #[inline] | |
3467 | #[target_feature(enable = "neon")] | |
3468 | #[cfg_attr(test, assert_instr(smlal2))] | |
3469 | pub unsafe fn vmlal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { | |
3470 | let b: int8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
3471 | let c: int8x8_t = simd_shuffle8!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); | |
3472 | vmlal_s8(a, b, c) | |
3473 | } | |
3474 | ||
3475 | /// Signed multiply-add long | |
3476 | #[inline] | |
3477 | #[target_feature(enable = "neon")] | |
3478 | #[cfg_attr(test, assert_instr(smlal2))] | |
3479 | pub unsafe fn vmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { | |
3480 | let b: int16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
3481 | let c: int16x4_t = simd_shuffle4!(c, c, [4, 5, 6, 7]); | |
3482 | vmlal_s16(a, b, c) | |
3483 | } | |
3484 | ||
3485 | /// Signed multiply-add long | |
3486 | #[inline] | |
3487 | #[target_feature(enable = "neon")] | |
3488 | #[cfg_attr(test, assert_instr(smlal2))] | |
3489 | pub unsafe fn vmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { | |
3490 | let b: int32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
3491 | let c: int32x2_t = simd_shuffle2!(c, c, [2, 3]); | |
3492 | vmlal_s32(a, b, c) | |
3493 | } | |
3494 | ||
3495 | /// Unsigned multiply-add long | |
3496 | #[inline] | |
3497 | #[target_feature(enable = "neon")] | |
3498 | #[cfg_attr(test, assert_instr(umlal2))] | |
3499 | pub unsafe fn vmlal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { | |
3500 | let b: uint8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
3501 | let c: uint8x8_t = simd_shuffle8!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); | |
3502 | vmlal_u8(a, b, c) | |
3503 | } | |
3504 | ||
3505 | /// Unsigned multiply-add long | |
3506 | #[inline] | |
3507 | #[target_feature(enable = "neon")] | |
3508 | #[cfg_attr(test, assert_instr(umlal2))] | |
3509 | pub unsafe fn vmlal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { | |
3510 | let b: uint16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
3511 | let c: uint16x4_t = simd_shuffle4!(c, c, [4, 5, 6, 7]); | |
3512 | vmlal_u16(a, b, c) | |
3513 | } | |
3514 | ||
3515 | /// Unsigned multiply-add long | |
3516 | #[inline] | |
3517 | #[target_feature(enable = "neon")] | |
3518 | #[cfg_attr(test, assert_instr(umlal2))] | |
3519 | pub unsafe fn vmlal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { | |
3520 | let b: uint32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
3521 | let c: uint32x2_t = simd_shuffle2!(c, c, [2, 3]); | |
3522 | vmlal_u32(a, b, c) | |
3523 | } | |
3524 | ||
3525 | /// Multiply-add long | |
3526 | #[inline] | |
3527 | #[target_feature(enable = "neon")] | |
3528 | #[cfg_attr(test, assert_instr(smlal2))] | |
3529 | pub unsafe fn vmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { | |
3530 | vmlal_high_s16(a, b, vdupq_n_s16(c)) | |
3531 | } | |
3532 | ||
3533 | /// Multiply-add long | |
3534 | #[inline] | |
3535 | #[target_feature(enable = "neon")] | |
3536 | #[cfg_attr(test, assert_instr(smlal2))] | |
3537 | pub unsafe fn vmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { | |
3538 | vmlal_high_s32(a, b, vdupq_n_s32(c)) | |
3539 | } | |
3540 | ||
3541 | /// Multiply-add long | |
3542 | #[inline] | |
3543 | #[target_feature(enable = "neon")] | |
3544 | #[cfg_attr(test, assert_instr(umlal2))] | |
3545 | pub unsafe fn vmlal_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t { | |
3546 | vmlal_high_u16(a, b, vdupq_n_u16(c)) | |
3547 | } | |
3548 | ||
3549 | /// Multiply-add long | |
3550 | #[inline] | |
3551 | #[target_feature(enable = "neon")] | |
3552 | #[cfg_attr(test, assert_instr(umlal2))] | |
3553 | pub unsafe fn vmlal_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t { | |
3554 | vmlal_high_u32(a, b, vdupq_n_u32(c)) | |
3555 | } | |
3556 | ||
3557 | /// Multiply-add long | |
3558 | #[inline] | |
3559 | #[target_feature(enable = "neon")] | |
3560 | #[cfg_attr(test, assert_instr(smlal2, LANE = 1))] | |
3561 | #[rustc_legacy_const_generics(3)] | |
3562 | pub unsafe fn vmlal_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { | |
3563 | static_assert_imm2!(LANE); | |
3564 | vmlal_high_s16(a, b, simd_shuffle8!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3565 | } | |
3566 | ||
3567 | /// Multiply-add long | |
3568 | #[inline] | |
3569 | #[target_feature(enable = "neon")] | |
3570 | #[cfg_attr(test, assert_instr(smlal2, LANE = 1))] | |
3571 | #[rustc_legacy_const_generics(3)] | |
3572 | pub unsafe fn vmlal_high_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { | |
3573 | static_assert_imm3!(LANE); | |
3574 | vmlal_high_s16(a, b, simd_shuffle8!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3575 | } | |
3576 | ||
3577 | /// Multiply-add long | |
3578 | #[inline] | |
3579 | #[target_feature(enable = "neon")] | |
3580 | #[cfg_attr(test, assert_instr(smlal2, LANE = 1))] | |
3581 | #[rustc_legacy_const_generics(3)] | |
3582 | pub unsafe fn vmlal_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { | |
3583 | static_assert_imm1!(LANE); | |
3584 | vmlal_high_s32(a, b, simd_shuffle4!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3585 | } | |
3586 | ||
3587 | /// Multiply-add long | |
3588 | #[inline] | |
3589 | #[target_feature(enable = "neon")] | |
3590 | #[cfg_attr(test, assert_instr(smlal2, LANE = 1))] | |
3591 | #[rustc_legacy_const_generics(3)] | |
3592 | pub unsafe fn vmlal_high_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { | |
3593 | static_assert_imm2!(LANE); | |
3594 | vmlal_high_s32(a, b, simd_shuffle4!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3595 | } | |
3596 | ||
3597 | /// Multiply-add long | |
3598 | #[inline] | |
3599 | #[target_feature(enable = "neon")] | |
3600 | #[cfg_attr(test, assert_instr(umlal2, LANE = 1))] | |
3601 | #[rustc_legacy_const_generics(3)] | |
3602 | pub unsafe fn vmlal_high_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x8_t, c: uint16x4_t) -> uint32x4_t { | |
3603 | static_assert_imm2!(LANE); | |
3604 | vmlal_high_u16(a, b, simd_shuffle8!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3605 | } | |
3606 | ||
3607 | /// Multiply-add long | |
3608 | #[inline] | |
3609 | #[target_feature(enable = "neon")] | |
3610 | #[cfg_attr(test, assert_instr(umlal2, LANE = 1))] | |
3611 | #[rustc_legacy_const_generics(3)] | |
3612 | pub unsafe fn vmlal_high_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { | |
3613 | static_assert_imm3!(LANE); | |
3614 | vmlal_high_u16(a, b, simd_shuffle8!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3615 | } | |
3616 | ||
3617 | /// Multiply-add long | |
3618 | #[inline] | |
3619 | #[target_feature(enable = "neon")] | |
3620 | #[cfg_attr(test, assert_instr(umlal2, LANE = 1))] | |
3621 | #[rustc_legacy_const_generics(3)] | |
3622 | pub unsafe fn vmlal_high_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x4_t, c: uint32x2_t) -> uint64x2_t { | |
3623 | static_assert_imm1!(LANE); | |
3624 | vmlal_high_u32(a, b, simd_shuffle4!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3625 | } | |
3626 | ||
3627 | /// Multiply-add long | |
3628 | #[inline] | |
3629 | #[target_feature(enable = "neon")] | |
3630 | #[cfg_attr(test, assert_instr(umlal2, LANE = 1))] | |
3631 | #[rustc_legacy_const_generics(3)] | |
3632 | pub unsafe fn vmlal_high_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { | |
3633 | static_assert_imm2!(LANE); | |
3634 | vmlal_high_u32(a, b, simd_shuffle4!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3635 | } | |
3636 | ||
3637 | /// Floating-point multiply-subtract from accumulator | |
3638 | #[inline] | |
3639 | #[target_feature(enable = "neon")] | |
3640 | #[cfg_attr(test, assert_instr(fmul))] | |
3641 | pub unsafe fn vmls_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { | |
3642 | simd_sub(a, simd_mul(b, c)) | |
3643 | } | |
3644 | ||
3645 | /// Floating-point multiply-subtract from accumulator | |
3646 | #[inline] | |
3647 | #[target_feature(enable = "neon")] | |
3648 | #[cfg_attr(test, assert_instr(fmul))] | |
3649 | pub unsafe fn vmlsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { | |
3650 | simd_sub(a, simd_mul(b, c)) | |
3651 | } | |
3652 | ||
3653 | /// Signed multiply-subtract long | |
3654 | #[inline] | |
3655 | #[target_feature(enable = "neon")] | |
3656 | #[cfg_attr(test, assert_instr(smlsl2))] | |
3657 | pub unsafe fn vmlsl_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { | |
3658 | let b: int8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
3659 | let c: int8x8_t = simd_shuffle8!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); | |
3660 | vmlsl_s8(a, b, c) | |
3661 | } | |
3662 | ||
3663 | /// Signed multiply-subtract long | |
3664 | #[inline] | |
3665 | #[target_feature(enable = "neon")] | |
3666 | #[cfg_attr(test, assert_instr(smlsl2))] | |
3667 | pub unsafe fn vmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { | |
3668 | let b: int16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
3669 | let c: int16x4_t = simd_shuffle4!(c, c, [4, 5, 6, 7]); | |
3670 | vmlsl_s16(a, b, c) | |
3671 | } | |
3672 | ||
3673 | /// Signed multiply-subtract long | |
3674 | #[inline] | |
3675 | #[target_feature(enable = "neon")] | |
3676 | #[cfg_attr(test, assert_instr(smlsl2))] | |
3677 | pub unsafe fn vmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { | |
3678 | let b: int32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
3679 | let c: int32x2_t = simd_shuffle2!(c, c, [2, 3]); | |
3680 | vmlsl_s32(a, b, c) | |
3681 | } | |
3682 | ||
3683 | /// Unsigned multiply-subtract long | |
3684 | #[inline] | |
3685 | #[target_feature(enable = "neon")] | |
3686 | #[cfg_attr(test, assert_instr(umlsl2))] | |
3687 | pub unsafe fn vmlsl_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { | |
3688 | let b: uint8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
3689 | let c: uint8x8_t = simd_shuffle8!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); | |
3690 | vmlsl_u8(a, b, c) | |
3691 | } | |
3692 | ||
3693 | /// Unsigned multiply-subtract long | |
3694 | #[inline] | |
3695 | #[target_feature(enable = "neon")] | |
3696 | #[cfg_attr(test, assert_instr(umlsl2))] | |
3697 | pub unsafe fn vmlsl_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { | |
3698 | let b: uint16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
3699 | let c: uint16x4_t = simd_shuffle4!(c, c, [4, 5, 6, 7]); | |
3700 | vmlsl_u16(a, b, c) | |
3701 | } | |
3702 | ||
3703 | /// Unsigned multiply-subtract long | |
3704 | #[inline] | |
3705 | #[target_feature(enable = "neon")] | |
3706 | #[cfg_attr(test, assert_instr(umlsl2))] | |
3707 | pub unsafe fn vmlsl_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { | |
3708 | let b: uint32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
3709 | let c: uint32x2_t = simd_shuffle2!(c, c, [2, 3]); | |
3710 | vmlsl_u32(a, b, c) | |
3711 | } | |
3712 | ||
3713 | /// Multiply-subtract long | |
3714 | #[inline] | |
3715 | #[target_feature(enable = "neon")] | |
3716 | #[cfg_attr(test, assert_instr(smlsl2))] | |
3717 | pub unsafe fn vmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { | |
3718 | vmlsl_high_s16(a, b, vdupq_n_s16(c)) | |
3719 | } | |
3720 | ||
3721 | /// Multiply-subtract long | |
3722 | #[inline] | |
3723 | #[target_feature(enable = "neon")] | |
3724 | #[cfg_attr(test, assert_instr(smlsl2))] | |
3725 | pub unsafe fn vmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { | |
3726 | vmlsl_high_s32(a, b, vdupq_n_s32(c)) | |
3727 | } | |
3728 | ||
3729 | /// Multiply-subtract long | |
3730 | #[inline] | |
3731 | #[target_feature(enable = "neon")] | |
3732 | #[cfg_attr(test, assert_instr(umlsl2))] | |
3733 | pub unsafe fn vmlsl_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t { | |
3734 | vmlsl_high_u16(a, b, vdupq_n_u16(c)) | |
3735 | } | |
3736 | ||
3737 | /// Multiply-subtract long | |
3738 | #[inline] | |
3739 | #[target_feature(enable = "neon")] | |
3740 | #[cfg_attr(test, assert_instr(umlsl2))] | |
3741 | pub unsafe fn vmlsl_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t { | |
3742 | vmlsl_high_u32(a, b, vdupq_n_u32(c)) | |
3743 | } | |
3744 | ||
3745 | /// Multiply-subtract long | |
3746 | #[inline] | |
3747 | #[target_feature(enable = "neon")] | |
3748 | #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] | |
3749 | #[rustc_legacy_const_generics(3)] | |
3750 | pub unsafe fn vmlsl_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { | |
3751 | static_assert_imm2!(LANE); | |
3752 | vmlsl_high_s16(a, b, simd_shuffle8!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3753 | } | |
3754 | ||
3755 | /// Multiply-subtract long | |
3756 | #[inline] | |
3757 | #[target_feature(enable = "neon")] | |
3758 | #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] | |
3759 | #[rustc_legacy_const_generics(3)] | |
3760 | pub unsafe fn vmlsl_high_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { | |
3761 | static_assert_imm3!(LANE); | |
3762 | vmlsl_high_s16(a, b, simd_shuffle8!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3763 | } | |
3764 | ||
3765 | /// Multiply-subtract long | |
3766 | #[inline] | |
3767 | #[target_feature(enable = "neon")] | |
3768 | #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] | |
3769 | #[rustc_legacy_const_generics(3)] | |
3770 | pub unsafe fn vmlsl_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { | |
3771 | static_assert_imm1!(LANE); | |
3772 | vmlsl_high_s32(a, b, simd_shuffle4!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3773 | } | |
3774 | ||
3775 | /// Multiply-subtract long | |
3776 | #[inline] | |
3777 | #[target_feature(enable = "neon")] | |
3778 | #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] | |
3779 | #[rustc_legacy_const_generics(3)] | |
3780 | pub unsafe fn vmlsl_high_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { | |
3781 | static_assert_imm2!(LANE); | |
3782 | vmlsl_high_s32(a, b, simd_shuffle4!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3783 | } | |
3784 | ||
3785 | /// Multiply-subtract long | |
3786 | #[inline] | |
3787 | #[target_feature(enable = "neon")] | |
3788 | #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] | |
3789 | #[rustc_legacy_const_generics(3)] | |
3790 | pub unsafe fn vmlsl_high_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x8_t, c: uint16x4_t) -> uint32x4_t { | |
3791 | static_assert_imm2!(LANE); | |
3792 | vmlsl_high_u16(a, b, simd_shuffle8!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3793 | } | |
3794 | ||
3795 | /// Multiply-subtract long | |
3796 | #[inline] | |
3797 | #[target_feature(enable = "neon")] | |
3798 | #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] | |
3799 | #[rustc_legacy_const_generics(3)] | |
3800 | pub unsafe fn vmlsl_high_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { | |
3801 | static_assert_imm3!(LANE); | |
3802 | vmlsl_high_u16(a, b, simd_shuffle8!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3803 | } | |
3804 | ||
3805 | /// Multiply-subtract long | |
3806 | #[inline] | |
3807 | #[target_feature(enable = "neon")] | |
3808 | #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] | |
3809 | #[rustc_legacy_const_generics(3)] | |
3810 | pub unsafe fn vmlsl_high_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x4_t, c: uint32x2_t) -> uint64x2_t { | |
3811 | static_assert_imm1!(LANE); | |
3812 | vmlsl_high_u32(a, b, simd_shuffle4!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3813 | } | |
3814 | ||
3815 | /// Multiply-subtract long | |
3816 | #[inline] | |
3817 | #[target_feature(enable = "neon")] | |
3818 | #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] | |
3819 | #[rustc_legacy_const_generics(3)] | |
3820 | pub unsafe fn vmlsl_high_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { | |
3821 | static_assert_imm2!(LANE); | |
3822 | vmlsl_high_u32(a, b, simd_shuffle4!(c, c, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
3823 | } | |
3824 | ||
3825 | /// Extract narrow | |
3826 | #[inline] | |
3827 | #[target_feature(enable = "neon")] | |
3828 | #[cfg_attr(test, assert_instr(xtn2))] | |
3829 | pub unsafe fn vmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { | |
3830 | let c: int8x8_t = simd_cast(b); | |
3831 | simd_shuffle16!(a, c, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
3832 | } | |
3833 | ||
3834 | /// Extract narrow | |
3835 | #[inline] | |
3836 | #[target_feature(enable = "neon")] | |
3837 | #[cfg_attr(test, assert_instr(xtn2))] | |
3838 | pub unsafe fn vmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { | |
3839 | let c: int16x4_t = simd_cast(b); | |
3840 | simd_shuffle8!(a, c, [0, 1, 2, 3, 4, 5, 6, 7]) | |
3841 | } | |
3842 | ||
3843 | /// Extract narrow | |
3844 | #[inline] | |
3845 | #[target_feature(enable = "neon")] | |
3846 | #[cfg_attr(test, assert_instr(xtn2))] | |
3847 | pub unsafe fn vmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { | |
3848 | let c: int32x2_t = simd_cast(b); | |
3849 | simd_shuffle4!(a, c, [0, 1, 2, 3]) | |
3850 | } | |
3851 | ||
3852 | /// Extract narrow | |
3853 | #[inline] | |
3854 | #[target_feature(enable = "neon")] | |
3855 | #[cfg_attr(test, assert_instr(xtn2))] | |
3856 | pub unsafe fn vmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { | |
3857 | let c: uint8x8_t = simd_cast(b); | |
3858 | simd_shuffle16!(a, c, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
3859 | } | |
3860 | ||
3861 | /// Extract narrow | |
3862 | #[inline] | |
3863 | #[target_feature(enable = "neon")] | |
3864 | #[cfg_attr(test, assert_instr(xtn2))] | |
3865 | pub unsafe fn vmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { | |
3866 | let c: uint16x4_t = simd_cast(b); | |
3867 | simd_shuffle8!(a, c, [0, 1, 2, 3, 4, 5, 6, 7]) | |
3868 | } | |
3869 | ||
3870 | /// Extract narrow | |
3871 | #[inline] | |
3872 | #[target_feature(enable = "neon")] | |
3873 | #[cfg_attr(test, assert_instr(xtn2))] | |
3874 | pub unsafe fn vmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { | |
3875 | let c: uint32x2_t = simd_cast(b); | |
3876 | simd_shuffle4!(a, c, [0, 1, 2, 3]) | |
3877 | } | |
3878 | ||
3879 | /// Negate | |
3880 | #[inline] | |
3881 | #[target_feature(enable = "neon")] | |
3882 | #[cfg_attr(test, assert_instr(neg))] | |
3883 | pub unsafe fn vneg_s64(a: int64x1_t) -> int64x1_t { | |
3884 | simd_neg(a) | |
3885 | } | |
3886 | ||
3887 | /// Negate | |
3888 | #[inline] | |
3889 | #[target_feature(enable = "neon")] | |
3890 | #[cfg_attr(test, assert_instr(neg))] | |
3891 | pub unsafe fn vnegq_s64(a: int64x2_t) -> int64x2_t { | |
3892 | simd_neg(a) | |
3893 | } | |
3894 | ||
3895 | /// Negate | |
3896 | #[inline] | |
3897 | #[target_feature(enable = "neon")] | |
3898 | #[cfg_attr(test, assert_instr(fneg))] | |
3899 | pub unsafe fn vneg_f64(a: float64x1_t) -> float64x1_t { | |
3900 | simd_neg(a) | |
3901 | } | |
3902 | ||
3903 | /// Negate | |
3904 | #[inline] | |
3905 | #[target_feature(enable = "neon")] | |
3906 | #[cfg_attr(test, assert_instr(fneg))] | |
3907 | pub unsafe fn vnegq_f64(a: float64x2_t) -> float64x2_t { | |
3908 | simd_neg(a) | |
3909 | } | |
3910 | ||
3911 | /// Signed saturating negate | |
3912 | #[inline] | |
3913 | #[target_feature(enable = "neon")] | |
3914 | #[cfg_attr(test, assert_instr(sqneg))] | |
3915 | pub unsafe fn vqneg_s64(a: int64x1_t) -> int64x1_t { | |
3916 | #[allow(improper_ctypes)] | |
3917 | extern "C" { | |
3918 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqneg.v1i64")] | |
3919 | fn vqneg_s64_(a: int64x1_t) -> int64x1_t; | |
3920 | } | |
3921 | vqneg_s64_(a) | |
3922 | } | |
3923 | ||
3924 | /// Signed saturating negate | |
3925 | #[inline] | |
3926 | #[target_feature(enable = "neon")] | |
3927 | #[cfg_attr(test, assert_instr(sqneg))] | |
3928 | pub unsafe fn vqnegq_s64(a: int64x2_t) -> int64x2_t { | |
3929 | #[allow(improper_ctypes)] | |
3930 | extern "C" { | |
3931 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqneg.v2i64")] | |
3932 | fn vqnegq_s64_(a: int64x2_t) -> int64x2_t; | |
3933 | } | |
3934 | vqnegq_s64_(a) | |
3935 | } | |
3936 | ||
3937 | /// Saturating subtract | |
3938 | #[inline] | |
3939 | #[target_feature(enable = "neon")] | |
3940 | #[cfg_attr(test, assert_instr(sqsub))] | |
3941 | pub unsafe fn vqsubb_s8(a: i8, b: i8) -> i8 { | |
3942 | let a: int8x8_t = vdup_n_s8(a); | |
3943 | let b: int8x8_t = vdup_n_s8(b); | |
3944 | simd_extract(vqsub_s8(a, b), 0) | |
3945 | } | |
3946 | ||
3947 | /// Saturating subtract | |
3948 | #[inline] | |
3949 | #[target_feature(enable = "neon")] | |
3950 | #[cfg_attr(test, assert_instr(sqsub))] | |
3951 | pub unsafe fn vqsubh_s16(a: i16, b: i16) -> i16 { | |
3952 | let a: int16x4_t = vdup_n_s16(a); | |
3953 | let b: int16x4_t = vdup_n_s16(b); | |
3954 | simd_extract(vqsub_s16(a, b), 0) | |
3955 | } | |
3956 | ||
3957 | /// Saturating subtract | |
3958 | #[inline] | |
3959 | #[target_feature(enable = "neon")] | |
3960 | #[cfg_attr(test, assert_instr(uqsub))] | |
3961 | pub unsafe fn vqsubb_u8(a: u8, b: u8) -> u8 { | |
3962 | let a: uint8x8_t = vdup_n_u8(a); | |
3963 | let b: uint8x8_t = vdup_n_u8(b); | |
3964 | simd_extract(vqsub_u8(a, b), 0) | |
3965 | } | |
3966 | ||
3967 | /// Saturating subtract | |
3968 | #[inline] | |
3969 | #[target_feature(enable = "neon")] | |
3970 | #[cfg_attr(test, assert_instr(uqsub))] | |
3971 | pub unsafe fn vqsubh_u16(a: u16, b: u16) -> u16 { | |
3972 | let a: uint16x4_t = vdup_n_u16(a); | |
3973 | let b: uint16x4_t = vdup_n_u16(b); | |
3974 | simd_extract(vqsub_u16(a, b), 0) | |
3975 | } | |
3976 | ||
3977 | /// Saturating subtract | |
3978 | #[inline] | |
3979 | #[target_feature(enable = "neon")] | |
3980 | #[cfg_attr(test, assert_instr(uqsub))] | |
3981 | pub unsafe fn vqsubs_u32(a: u32, b: u32) -> u32 { | |
3982 | #[allow(improper_ctypes)] | |
3983 | extern "C" { | |
3984 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqsub.i32")] | |
3985 | fn vqsubs_u32_(a: u32, b: u32) -> u32; | |
3986 | } | |
3987 | vqsubs_u32_(a, b) | |
3988 | } | |
3989 | ||
3990 | /// Saturating subtract | |
3991 | #[inline] | |
3992 | #[target_feature(enable = "neon")] | |
3993 | #[cfg_attr(test, assert_instr(uqsub))] | |
3994 | pub unsafe fn vqsubd_u64(a: u64, b: u64) -> u64 { | |
3995 | #[allow(improper_ctypes)] | |
3996 | extern "C" { | |
3997 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqsub.i64")] | |
3998 | fn vqsubd_u64_(a: u64, b: u64) -> u64; | |
3999 | } | |
4000 | vqsubd_u64_(a, b) | |
4001 | } | |
4002 | ||
4003 | /// Saturating subtract | |
4004 | #[inline] | |
4005 | #[target_feature(enable = "neon")] | |
4006 | #[cfg_attr(test, assert_instr(sqsub))] | |
4007 | pub unsafe fn vqsubs_s32(a: i32, b: i32) -> i32 { | |
4008 | #[allow(improper_ctypes)] | |
4009 | extern "C" { | |
4010 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqsub.i32")] | |
4011 | fn vqsubs_s32_(a: i32, b: i32) -> i32; | |
4012 | } | |
4013 | vqsubs_s32_(a, b) | |
4014 | } | |
4015 | ||
4016 | /// Saturating subtract | |
4017 | #[inline] | |
4018 | #[target_feature(enable = "neon")] | |
4019 | #[cfg_attr(test, assert_instr(sqsub))] | |
4020 | pub unsafe fn vqsubd_s64(a: i64, b: i64) -> i64 { | |
4021 | #[allow(improper_ctypes)] | |
4022 | extern "C" { | |
4023 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqsub.i64")] | |
4024 | fn vqsubd_s64_(a: i64, b: i64) -> i64; | |
4025 | } | |
4026 | vqsubd_s64_(a, b) | |
4027 | } | |
4028 | ||
4029 | /// Reverse bit order | |
4030 | #[inline] | |
4031 | #[target_feature(enable = "neon")] | |
4032 | #[cfg_attr(test, assert_instr(rbit))] | |
4033 | pub unsafe fn vrbit_s8(a: int8x8_t) -> int8x8_t { | |
4034 | #[allow(improper_ctypes)] | |
4035 | extern "C" { | |
4036 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.rbit.v8i8")] | |
4037 | fn vrbit_s8_(a: int8x8_t) -> int8x8_t; | |
4038 | } | |
4039 | vrbit_s8_(a) | |
4040 | } | |
4041 | ||
4042 | /// Reverse bit order | |
4043 | #[inline] | |
4044 | #[target_feature(enable = "neon")] | |
4045 | #[cfg_attr(test, assert_instr(rbit))] | |
4046 | pub unsafe fn vrbitq_s8(a: int8x16_t) -> int8x16_t { | |
4047 | #[allow(improper_ctypes)] | |
4048 | extern "C" { | |
4049 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.rbit.v16i8")] | |
4050 | fn vrbitq_s8_(a: int8x16_t) -> int8x16_t; | |
4051 | } | |
4052 | vrbitq_s8_(a) | |
4053 | } | |
4054 | ||
4055 | /// Reverse bit order | |
4056 | #[inline] | |
4057 | #[target_feature(enable = "neon")] | |
4058 | #[cfg_attr(test, assert_instr(rbit))] | |
4059 | pub unsafe fn vrbit_u8(a: uint8x8_t) -> uint8x8_t { | |
4060 | transmute(vrbit_s8(transmute(a))) | |
4061 | } | |
4062 | ||
4063 | /// Reverse bit order | |
4064 | #[inline] | |
4065 | #[target_feature(enable = "neon")] | |
4066 | #[cfg_attr(test, assert_instr(rbit))] | |
4067 | pub unsafe fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t { | |
4068 | transmute(vrbitq_s8(transmute(a))) | |
4069 | } | |
4070 | ||
4071 | /// Reverse bit order | |
4072 | #[inline] | |
4073 | #[target_feature(enable = "neon")] | |
4074 | #[cfg_attr(test, assert_instr(rbit))] | |
4075 | pub unsafe fn vrbit_p8(a: poly8x8_t) -> poly8x8_t { | |
4076 | transmute(vrbit_s8(transmute(a))) | |
4077 | } | |
4078 | ||
4079 | /// Reverse bit order | |
4080 | #[inline] | |
4081 | #[target_feature(enable = "neon")] | |
4082 | #[cfg_attr(test, assert_instr(rbit))] | |
4083 | pub unsafe fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t { | |
4084 | transmute(vrbitq_s8(transmute(a))) | |
4085 | } | |
4086 | ||
4087 | /// Floating-point round to integral exact, using current rounding mode | |
4088 | #[inline] | |
4089 | #[target_feature(enable = "neon")] | |
4090 | #[cfg_attr(test, assert_instr(frintx))] | |
4091 | pub unsafe fn vrndx_f32(a: float32x2_t) -> float32x2_t { | |
4092 | #[allow(improper_ctypes)] | |
4093 | extern "C" { | |
4094 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.rint.v2f32")] | |
4095 | fn vrndx_f32_(a: float32x2_t) -> float32x2_t; | |
4096 | } | |
4097 | vrndx_f32_(a) | |
4098 | } | |
4099 | ||
4100 | /// Floating-point round to integral exact, using current rounding mode | |
4101 | #[inline] | |
4102 | #[target_feature(enable = "neon")] | |
4103 | #[cfg_attr(test, assert_instr(frintx))] | |
4104 | pub unsafe fn vrndxq_f32(a: float32x4_t) -> float32x4_t { | |
4105 | #[allow(improper_ctypes)] | |
4106 | extern "C" { | |
4107 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.rint.v4f32")] | |
4108 | fn vrndxq_f32_(a: float32x4_t) -> float32x4_t; | |
4109 | } | |
4110 | vrndxq_f32_(a) | |
4111 | } | |
4112 | ||
4113 | /// Floating-point round to integral exact, using current rounding mode | |
4114 | #[inline] | |
4115 | #[target_feature(enable = "neon")] | |
4116 | #[cfg_attr(test, assert_instr(frintx))] | |
4117 | pub unsafe fn vrndx_f64(a: float64x1_t) -> float64x1_t { | |
4118 | #[allow(improper_ctypes)] | |
4119 | extern "C" { | |
4120 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.rint.v1f64")] | |
4121 | fn vrndx_f64_(a: float64x1_t) -> float64x1_t; | |
4122 | } | |
4123 | vrndx_f64_(a) | |
4124 | } | |
4125 | ||
4126 | /// Floating-point round to integral exact, using current rounding mode | |
4127 | #[inline] | |
4128 | #[target_feature(enable = "neon")] | |
4129 | #[cfg_attr(test, assert_instr(frintx))] | |
4130 | pub unsafe fn vrndxq_f64(a: float64x2_t) -> float64x2_t { | |
4131 | #[allow(improper_ctypes)] | |
4132 | extern "C" { | |
4133 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.rint.v2f64")] | |
4134 | fn vrndxq_f64_(a: float64x2_t) -> float64x2_t; | |
4135 | } | |
4136 | vrndxq_f64_(a) | |
4137 | } | |
4138 | ||
4139 | /// Floating-point round to integral, to nearest with ties to away | |
4140 | #[inline] | |
4141 | #[target_feature(enable = "neon")] | |
4142 | #[cfg_attr(test, assert_instr(frinta))] | |
4143 | pub unsafe fn vrnda_f32(a: float32x2_t) -> float32x2_t { | |
4144 | #[allow(improper_ctypes)] | |
4145 | extern "C" { | |
4146 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.round.v2f32")] | |
4147 | fn vrnda_f32_(a: float32x2_t) -> float32x2_t; | |
4148 | } | |
4149 | vrnda_f32_(a) | |
4150 | } | |
4151 | ||
4152 | /// Floating-point round to integral, to nearest with ties to away | |
4153 | #[inline] | |
4154 | #[target_feature(enable = "neon")] | |
4155 | #[cfg_attr(test, assert_instr(frinta))] | |
4156 | pub unsafe fn vrndaq_f32(a: float32x4_t) -> float32x4_t { | |
4157 | #[allow(improper_ctypes)] | |
4158 | extern "C" { | |
4159 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.round.v4f32")] | |
4160 | fn vrndaq_f32_(a: float32x4_t) -> float32x4_t; | |
4161 | } | |
4162 | vrndaq_f32_(a) | |
4163 | } | |
4164 | ||
4165 | /// Floating-point round to integral, to nearest with ties to away | |
4166 | #[inline] | |
4167 | #[target_feature(enable = "neon")] | |
4168 | #[cfg_attr(test, assert_instr(frinta))] | |
4169 | pub unsafe fn vrnda_f64(a: float64x1_t) -> float64x1_t { | |
4170 | #[allow(improper_ctypes)] | |
4171 | extern "C" { | |
4172 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.round.v1f64")] | |
4173 | fn vrnda_f64_(a: float64x1_t) -> float64x1_t; | |
4174 | } | |
4175 | vrnda_f64_(a) | |
4176 | } | |
4177 | ||
4178 | /// Floating-point round to integral, to nearest with ties to away | |
4179 | #[inline] | |
4180 | #[target_feature(enable = "neon")] | |
4181 | #[cfg_attr(test, assert_instr(frinta))] | |
4182 | pub unsafe fn vrndaq_f64(a: float64x2_t) -> float64x2_t { | |
4183 | #[allow(improper_ctypes)] | |
4184 | extern "C" { | |
4185 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.round.v2f64")] | |
4186 | fn vrndaq_f64_(a: float64x2_t) -> float64x2_t; | |
4187 | } | |
4188 | vrndaq_f64_(a) | |
4189 | } | |
4190 | ||
4191 | /// Floating-point round to integral, to nearest with ties to even | |
4192 | #[inline] | |
4193 | #[target_feature(enable = "neon")] | |
4194 | #[cfg_attr(test, assert_instr(frintn))] | |
4195 | pub unsafe fn vrndn_f64(a: float64x1_t) -> float64x1_t { | |
4196 | #[allow(improper_ctypes)] | |
4197 | extern "C" { | |
4198 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.frintn.v1f64")] | |
4199 | fn vrndn_f64_(a: float64x1_t) -> float64x1_t; | |
4200 | } | |
4201 | vrndn_f64_(a) | |
4202 | } | |
4203 | ||
4204 | /// Floating-point round to integral, to nearest with ties to even | |
4205 | #[inline] | |
4206 | #[target_feature(enable = "neon")] | |
4207 | #[cfg_attr(test, assert_instr(frintn))] | |
4208 | pub unsafe fn vrndnq_f64(a: float64x2_t) -> float64x2_t { | |
4209 | #[allow(improper_ctypes)] | |
4210 | extern "C" { | |
4211 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.frintn.v2f64")] | |
4212 | fn vrndnq_f64_(a: float64x2_t) -> float64x2_t; | |
4213 | } | |
4214 | vrndnq_f64_(a) | |
4215 | } | |
4216 | ||
4217 | /// Floating-point round to integral, toward minus infinity | |
4218 | #[inline] | |
4219 | #[target_feature(enable = "neon")] | |
4220 | #[cfg_attr(test, assert_instr(frintm))] | |
4221 | pub unsafe fn vrndm_f32(a: float32x2_t) -> float32x2_t { | |
4222 | #[allow(improper_ctypes)] | |
4223 | extern "C" { | |
4224 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.floor.v2f32")] | |
4225 | fn vrndm_f32_(a: float32x2_t) -> float32x2_t; | |
4226 | } | |
4227 | vrndm_f32_(a) | |
4228 | } | |
4229 | ||
4230 | /// Floating-point round to integral, toward minus infinity | |
4231 | #[inline] | |
4232 | #[target_feature(enable = "neon")] | |
4233 | #[cfg_attr(test, assert_instr(frintm))] | |
4234 | pub unsafe fn vrndmq_f32(a: float32x4_t) -> float32x4_t { | |
4235 | #[allow(improper_ctypes)] | |
4236 | extern "C" { | |
4237 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.floor.v4f32")] | |
4238 | fn vrndmq_f32_(a: float32x4_t) -> float32x4_t; | |
4239 | } | |
4240 | vrndmq_f32_(a) | |
4241 | } | |
4242 | ||
4243 | /// Floating-point round to integral, toward minus infinity | |
4244 | #[inline] | |
4245 | #[target_feature(enable = "neon")] | |
4246 | #[cfg_attr(test, assert_instr(frintm))] | |
4247 | pub unsafe fn vrndm_f64(a: float64x1_t) -> float64x1_t { | |
4248 | #[allow(improper_ctypes)] | |
4249 | extern "C" { | |
4250 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.floor.v1f64")] | |
4251 | fn vrndm_f64_(a: float64x1_t) -> float64x1_t; | |
4252 | } | |
4253 | vrndm_f64_(a) | |
4254 | } | |
4255 | ||
4256 | /// Floating-point round to integral, toward minus infinity | |
4257 | #[inline] | |
4258 | #[target_feature(enable = "neon")] | |
4259 | #[cfg_attr(test, assert_instr(frintm))] | |
4260 | pub unsafe fn vrndmq_f64(a: float64x2_t) -> float64x2_t { | |
4261 | #[allow(improper_ctypes)] | |
4262 | extern "C" { | |
4263 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.floor.v2f64")] | |
4264 | fn vrndmq_f64_(a: float64x2_t) -> float64x2_t; | |
4265 | } | |
4266 | vrndmq_f64_(a) | |
4267 | } | |
4268 | ||
4269 | /// Floating-point round to integral, toward plus infinity | |
4270 | #[inline] | |
4271 | #[target_feature(enable = "neon")] | |
4272 | #[cfg_attr(test, assert_instr(frintp))] | |
4273 | pub unsafe fn vrndp_f32(a: float32x2_t) -> float32x2_t { | |
4274 | #[allow(improper_ctypes)] | |
4275 | extern "C" { | |
4276 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.ceil.v2f32")] | |
4277 | fn vrndp_f32_(a: float32x2_t) -> float32x2_t; | |
4278 | } | |
4279 | vrndp_f32_(a) | |
4280 | } | |
4281 | ||
4282 | /// Floating-point round to integral, toward plus infinity | |
4283 | #[inline] | |
4284 | #[target_feature(enable = "neon")] | |
4285 | #[cfg_attr(test, assert_instr(frintp))] | |
4286 | pub unsafe fn vrndpq_f32(a: float32x4_t) -> float32x4_t { | |
4287 | #[allow(improper_ctypes)] | |
4288 | extern "C" { | |
4289 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.ceil.v4f32")] | |
4290 | fn vrndpq_f32_(a: float32x4_t) -> float32x4_t; | |
4291 | } | |
4292 | vrndpq_f32_(a) | |
4293 | } | |
4294 | ||
4295 | /// Floating-point round to integral, toward plus infinity | |
4296 | #[inline] | |
4297 | #[target_feature(enable = "neon")] | |
4298 | #[cfg_attr(test, assert_instr(frintp))] | |
4299 | pub unsafe fn vrndp_f64(a: float64x1_t) -> float64x1_t { | |
4300 | #[allow(improper_ctypes)] | |
4301 | extern "C" { | |
4302 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.ceil.v1f64")] | |
4303 | fn vrndp_f64_(a: float64x1_t) -> float64x1_t; | |
4304 | } | |
4305 | vrndp_f64_(a) | |
4306 | } | |
4307 | ||
4308 | /// Floating-point round to integral, toward plus infinity | |
4309 | #[inline] | |
4310 | #[target_feature(enable = "neon")] | |
4311 | #[cfg_attr(test, assert_instr(frintp))] | |
4312 | pub unsafe fn vrndpq_f64(a: float64x2_t) -> float64x2_t { | |
4313 | #[allow(improper_ctypes)] | |
4314 | extern "C" { | |
4315 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.ceil.v2f64")] | |
4316 | fn vrndpq_f64_(a: float64x2_t) -> float64x2_t; | |
4317 | } | |
4318 | vrndpq_f64_(a) | |
4319 | } | |
4320 | ||
4321 | /// Floating-point round to integral, toward zero | |
4322 | #[inline] | |
4323 | #[target_feature(enable = "neon")] | |
4324 | #[cfg_attr(test, assert_instr(frintz))] | |
4325 | pub unsafe fn vrnd_f32(a: float32x2_t) -> float32x2_t { | |
4326 | #[allow(improper_ctypes)] | |
4327 | extern "C" { | |
4328 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.trunc.v2f32")] | |
4329 | fn vrnd_f32_(a: float32x2_t) -> float32x2_t; | |
4330 | } | |
4331 | vrnd_f32_(a) | |
4332 | } | |
4333 | ||
4334 | /// Floating-point round to integral, toward zero | |
4335 | #[inline] | |
4336 | #[target_feature(enable = "neon")] | |
4337 | #[cfg_attr(test, assert_instr(frintz))] | |
4338 | pub unsafe fn vrndq_f32(a: float32x4_t) -> float32x4_t { | |
4339 | #[allow(improper_ctypes)] | |
4340 | extern "C" { | |
4341 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.trunc.v4f32")] | |
4342 | fn vrndq_f32_(a: float32x4_t) -> float32x4_t; | |
4343 | } | |
4344 | vrndq_f32_(a) | |
4345 | } | |
4346 | ||
4347 | /// Floating-point round to integral, toward zero | |
4348 | #[inline] | |
4349 | #[target_feature(enable = "neon")] | |
4350 | #[cfg_attr(test, assert_instr(frintz))] | |
4351 | pub unsafe fn vrnd_f64(a: float64x1_t) -> float64x1_t { | |
4352 | #[allow(improper_ctypes)] | |
4353 | extern "C" { | |
4354 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.trunc.v1f64")] | |
4355 | fn vrnd_f64_(a: float64x1_t) -> float64x1_t; | |
4356 | } | |
4357 | vrnd_f64_(a) | |
4358 | } | |
4359 | ||
4360 | /// Floating-point round to integral, toward zero | |
4361 | #[inline] | |
4362 | #[target_feature(enable = "neon")] | |
4363 | #[cfg_attr(test, assert_instr(frintz))] | |
4364 | pub unsafe fn vrndq_f64(a: float64x2_t) -> float64x2_t { | |
4365 | #[allow(improper_ctypes)] | |
4366 | extern "C" { | |
4367 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.trunc.v2f64")] | |
4368 | fn vrndq_f64_(a: float64x2_t) -> float64x2_t; | |
4369 | } | |
4370 | vrndq_f64_(a) | |
4371 | } | |
4372 | ||
4373 | /// Floating-point round to integral, using current rounding mode | |
4374 | #[inline] | |
4375 | #[target_feature(enable = "neon")] | |
4376 | #[cfg_attr(test, assert_instr(frinti))] | |
4377 | pub unsafe fn vrndi_f32(a: float32x2_t) -> float32x2_t { | |
4378 | #[allow(improper_ctypes)] | |
4379 | extern "C" { | |
4380 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.nearbyint.v2f32")] | |
4381 | fn vrndi_f32_(a: float32x2_t) -> float32x2_t; | |
4382 | } | |
4383 | vrndi_f32_(a) | |
4384 | } | |
4385 | ||
4386 | /// Floating-point round to integral, using current rounding mode | |
4387 | #[inline] | |
4388 | #[target_feature(enable = "neon")] | |
4389 | #[cfg_attr(test, assert_instr(frinti))] | |
4390 | pub unsafe fn vrndiq_f32(a: float32x4_t) -> float32x4_t { | |
4391 | #[allow(improper_ctypes)] | |
4392 | extern "C" { | |
4393 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.nearbyint.v4f32")] | |
4394 | fn vrndiq_f32_(a: float32x4_t) -> float32x4_t; | |
4395 | } | |
4396 | vrndiq_f32_(a) | |
4397 | } | |
4398 | ||
4399 | /// Floating-point round to integral, using current rounding mode | |
4400 | #[inline] | |
4401 | #[target_feature(enable = "neon")] | |
4402 | #[cfg_attr(test, assert_instr(frinti))] | |
4403 | pub unsafe fn vrndi_f64(a: float64x1_t) -> float64x1_t { | |
4404 | #[allow(improper_ctypes)] | |
4405 | extern "C" { | |
4406 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.nearbyint.v1f64")] | |
4407 | fn vrndi_f64_(a: float64x1_t) -> float64x1_t; | |
4408 | } | |
4409 | vrndi_f64_(a) | |
4410 | } | |
4411 | ||
4412 | /// Floating-point round to integral, using current rounding mode | |
4413 | #[inline] | |
4414 | #[target_feature(enable = "neon")] | |
4415 | #[cfg_attr(test, assert_instr(frinti))] | |
4416 | pub unsafe fn vrndiq_f64(a: float64x2_t) -> float64x2_t { | |
4417 | #[allow(improper_ctypes)] | |
4418 | extern "C" { | |
4419 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.nearbyint.v2f64")] | |
4420 | fn vrndiq_f64_(a: float64x2_t) -> float64x2_t; | |
4421 | } | |
4422 | vrndiq_f64_(a) | |
4423 | } | |
4424 | ||
4425 | /// Saturating add | |
4426 | #[inline] | |
4427 | #[target_feature(enable = "neon")] | |
4428 | #[cfg_attr(test, assert_instr(sqadd))] | |
4429 | pub unsafe fn vqaddb_s8(a: i8, b: i8) -> i8 { | |
4430 | let a: int8x8_t = vdup_n_s8(a); | |
4431 | let b: int8x8_t = vdup_n_s8(b); | |
4432 | simd_extract(vqadd_s8(a, b), 0) | |
4433 | } | |
4434 | ||
4435 | /// Saturating add | |
4436 | #[inline] | |
4437 | #[target_feature(enable = "neon")] | |
4438 | #[cfg_attr(test, assert_instr(sqadd))] | |
4439 | pub unsafe fn vqaddh_s16(a: i16, b: i16) -> i16 { | |
4440 | let a: int16x4_t = vdup_n_s16(a); | |
4441 | let b: int16x4_t = vdup_n_s16(b); | |
4442 | simd_extract(vqadd_s16(a, b), 0) | |
4443 | } | |
4444 | ||
4445 | /// Saturating add | |
4446 | #[inline] | |
4447 | #[target_feature(enable = "neon")] | |
4448 | #[cfg_attr(test, assert_instr(uqadd))] | |
4449 | pub unsafe fn vqaddb_u8(a: u8, b: u8) -> u8 { | |
4450 | let a: uint8x8_t = vdup_n_u8(a); | |
4451 | let b: uint8x8_t = vdup_n_u8(b); | |
4452 | simd_extract(vqadd_u8(a, b), 0) | |
4453 | } | |
4454 | ||
4455 | /// Saturating add | |
4456 | #[inline] | |
4457 | #[target_feature(enable = "neon")] | |
4458 | #[cfg_attr(test, assert_instr(uqadd))] | |
4459 | pub unsafe fn vqaddh_u16(a: u16, b: u16) -> u16 { | |
4460 | let a: uint16x4_t = vdup_n_u16(a); | |
4461 | let b: uint16x4_t = vdup_n_u16(b); | |
4462 | simd_extract(vqadd_u16(a, b), 0) | |
4463 | } | |
4464 | ||
4465 | /// Saturating add | |
4466 | #[inline] | |
4467 | #[target_feature(enable = "neon")] | |
4468 | #[cfg_attr(test, assert_instr(uqadd))] | |
4469 | pub unsafe fn vqadds_u32(a: u32, b: u32) -> u32 { | |
4470 | #[allow(improper_ctypes)] | |
4471 | extern "C" { | |
4472 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqadd.i32")] | |
4473 | fn vqadds_u32_(a: u32, b: u32) -> u32; | |
4474 | } | |
4475 | vqadds_u32_(a, b) | |
4476 | } | |
4477 | ||
4478 | /// Saturating add | |
4479 | #[inline] | |
4480 | #[target_feature(enable = "neon")] | |
4481 | #[cfg_attr(test, assert_instr(uqadd))] | |
4482 | pub unsafe fn vqaddd_u64(a: u64, b: u64) -> u64 { | |
4483 | #[allow(improper_ctypes)] | |
4484 | extern "C" { | |
4485 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqadd.i64")] | |
4486 | fn vqaddd_u64_(a: u64, b: u64) -> u64; | |
4487 | } | |
4488 | vqaddd_u64_(a, b) | |
4489 | } | |
4490 | ||
4491 | /// Saturating add | |
4492 | #[inline] | |
4493 | #[target_feature(enable = "neon")] | |
4494 | #[cfg_attr(test, assert_instr(sqadd))] | |
4495 | pub unsafe fn vqadds_s32(a: i32, b: i32) -> i32 { | |
4496 | #[allow(improper_ctypes)] | |
4497 | extern "C" { | |
4498 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqadd.i32")] | |
4499 | fn vqadds_s32_(a: i32, b: i32) -> i32; | |
4500 | } | |
4501 | vqadds_s32_(a, b) | |
4502 | } | |
4503 | ||
4504 | /// Saturating add | |
4505 | #[inline] | |
4506 | #[target_feature(enable = "neon")] | |
4507 | #[cfg_attr(test, assert_instr(sqadd))] | |
4508 | pub unsafe fn vqaddd_s64(a: i64, b: i64) -> i64 { | |
4509 | #[allow(improper_ctypes)] | |
4510 | extern "C" { | |
4511 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqadd.i64")] | |
4512 | fn vqaddd_s64_(a: i64, b: i64) -> i64; | |
4513 | } | |
4514 | vqaddd_s64_(a, b) | |
4515 | } | |
4516 | ||
4517 | /// Multiply | |
4518 | #[inline] | |
4519 | #[target_feature(enable = "neon")] | |
4520 | #[cfg_attr(test, assert_instr(fmul))] | |
4521 | pub unsafe fn vmul_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
4522 | simd_mul(a, b) | |
4523 | } | |
4524 | ||
4525 | /// Multiply | |
4526 | #[inline] | |
4527 | #[target_feature(enable = "neon")] | |
4528 | #[cfg_attr(test, assert_instr(fmul))] | |
4529 | pub unsafe fn vmulq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
4530 | simd_mul(a, b) | |
4531 | } | |
4532 | ||
4533 | /// Vector multiply by scalar | |
4534 | #[inline] | |
4535 | #[target_feature(enable = "neon")] | |
4536 | #[cfg_attr(test, assert_instr(fmul))] | |
4537 | pub unsafe fn vmul_n_f64(a: float64x1_t, b: f64) -> float64x1_t { | |
4538 | simd_mul(a, vdup_n_f64(b)) | |
4539 | } | |
4540 | ||
4541 | /// Vector multiply by scalar | |
4542 | #[inline] | |
4543 | #[target_feature(enable = "neon")] | |
4544 | #[cfg_attr(test, assert_instr(fmul))] | |
4545 | pub unsafe fn vmulq_n_f64(a: float64x2_t, b: f64) -> float64x2_t { | |
4546 | simd_mul(a, vdupq_n_f64(b)) | |
4547 | } | |
4548 | ||
4549 | /// Floating-point multiply | |
4550 | #[inline] | |
4551 | #[target_feature(enable = "neon")] | |
4552 | #[cfg_attr(test, assert_instr(fmul, LANE = 0))] | |
4553 | #[rustc_legacy_const_generics(2)] | |
4554 | pub unsafe fn vmul_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
4555 | static_assert!(LANE : i32 where LANE == 0); | |
4556 | simd_mul(a, transmute::<f64, _>(simd_extract(b, LANE as u32))) | |
4557 | } | |
4558 | ||
4559 | /// Floating-point multiply | |
4560 | #[inline] | |
4561 | #[target_feature(enable = "neon")] | |
4562 | #[cfg_attr(test, assert_instr(fmul, LANE = 0))] | |
4563 | #[rustc_legacy_const_generics(2)] | |
4564 | pub unsafe fn vmul_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x2_t) -> float64x1_t { | |
4565 | static_assert_imm1!(LANE); | |
4566 | simd_mul(a, transmute::<f64, _>(simd_extract(b, LANE as u32))) | |
4567 | } | |
4568 | ||
4569 | /// Floating-point multiply | |
4570 | #[inline] | |
4571 | #[target_feature(enable = "neon")] | |
4572 | #[cfg_attr(test, assert_instr(fmul, LANE = 0))] | |
4573 | #[rustc_legacy_const_generics(2)] | |
4574 | pub unsafe fn vmulq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x1_t) -> float64x2_t { | |
4575 | static_assert!(LANE : i32 where LANE == 0); | |
4576 | simd_mul(a, simd_shuffle2!(b, b, <const LANE: i32> [LANE as u32, LANE as u32])) | |
4577 | } | |
4578 | ||
4579 | /// Floating-point multiply | |
4580 | #[inline] | |
4581 | #[target_feature(enable = "neon")] | |
4582 | #[cfg_attr(test, assert_instr(fmul, LANE = 0))] | |
4583 | #[rustc_legacy_const_generics(2)] | |
4584 | pub unsafe fn vmulq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
4585 | static_assert_imm1!(LANE); | |
4586 | simd_mul(a, simd_shuffle2!(b, b, <const LANE: i32> [LANE as u32, LANE as u32])) | |
4587 | } | |
4588 | ||
4589 | /// Floating-point multiply | |
4590 | #[inline] | |
4591 | #[target_feature(enable = "neon")] | |
4592 | #[cfg_attr(test, assert_instr(fmul, LANE = 0))] | |
4593 | #[rustc_legacy_const_generics(2)] | |
4594 | pub unsafe fn vmuls_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> f32 { | |
4595 | static_assert_imm1!(LANE); | |
4596 | let b: f32 = simd_extract(b, LANE as u32); | |
4597 | a * b | |
4598 | } | |
4599 | ||
4600 | /// Floating-point multiply | |
4601 | #[inline] | |
4602 | #[target_feature(enable = "neon")] | |
4603 | #[cfg_attr(test, assert_instr(fmul, LANE = 0))] | |
4604 | #[rustc_legacy_const_generics(2)] | |
4605 | pub unsafe fn vmuls_laneq_f32<const LANE: i32>(a: f32, b: float32x4_t) -> f32 { | |
4606 | static_assert_imm2!(LANE); | |
4607 | let b: f32 = simd_extract(b, LANE as u32); | |
4608 | a * b | |
4609 | } | |
4610 | ||
4611 | /// Floating-point multiply | |
4612 | #[inline] | |
4613 | #[target_feature(enable = "neon")] | |
4614 | #[cfg_attr(test, assert_instr(fmul, LANE = 0))] | |
4615 | #[rustc_legacy_const_generics(2)] | |
4616 | pub unsafe fn vmuld_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> f64 { | |
4617 | static_assert!(LANE : i32 where LANE == 0); | |
4618 | let b: f64 = simd_extract(b, LANE as u32); | |
4619 | a * b | |
4620 | } | |
4621 | ||
4622 | /// Floating-point multiply | |
4623 | #[inline] | |
4624 | #[target_feature(enable = "neon")] | |
4625 | #[cfg_attr(test, assert_instr(fmul, LANE = 0))] | |
4626 | #[rustc_legacy_const_generics(2)] | |
4627 | pub unsafe fn vmuld_laneq_f64<const LANE: i32>(a: f64, b: float64x2_t) -> f64 { | |
4628 | static_assert_imm1!(LANE); | |
4629 | let b: f64 = simd_extract(b, LANE as u32); | |
4630 | a * b | |
4631 | } | |
4632 | ||
4633 | /// Signed multiply long | |
4634 | #[inline] | |
4635 | #[target_feature(enable = "neon")] | |
4636 | #[cfg_attr(test, assert_instr(smull2))] | |
4637 | pub unsafe fn vmull_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { | |
4638 | let a: int8x8_t = simd_shuffle8!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); | |
4639 | let b: int8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
4640 | vmull_s8(a, b) | |
4641 | } | |
4642 | ||
4643 | /// Signed multiply long | |
4644 | #[inline] | |
4645 | #[target_feature(enable = "neon")] | |
4646 | #[cfg_attr(test, assert_instr(smull2))] | |
4647 | pub unsafe fn vmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { | |
4648 | let a: int16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
4649 | let b: int16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
4650 | vmull_s16(a, b) | |
4651 | } | |
4652 | ||
4653 | /// Signed multiply long | |
4654 | #[inline] | |
4655 | #[target_feature(enable = "neon")] | |
4656 | #[cfg_attr(test, assert_instr(smull2))] | |
4657 | pub unsafe fn vmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { | |
4658 | let a: int32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
4659 | let b: int32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
4660 | vmull_s32(a, b) | |
4661 | } | |
4662 | ||
4663 | /// Unsigned multiply long | |
4664 | #[inline] | |
4665 | #[target_feature(enable = "neon")] | |
4666 | #[cfg_attr(test, assert_instr(umull2))] | |
4667 | pub unsafe fn vmull_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { | |
4668 | let a: uint8x8_t = simd_shuffle8!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); | |
4669 | let b: uint8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
4670 | vmull_u8(a, b) | |
4671 | } | |
4672 | ||
4673 | /// Unsigned multiply long | |
4674 | #[inline] | |
4675 | #[target_feature(enable = "neon")] | |
4676 | #[cfg_attr(test, assert_instr(umull2))] | |
4677 | pub unsafe fn vmull_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { | |
4678 | let a: uint16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
4679 | let b: uint16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
4680 | vmull_u16(a, b) | |
4681 | } | |
4682 | ||
4683 | /// Unsigned multiply long | |
4684 | #[inline] | |
4685 | #[target_feature(enable = "neon")] | |
4686 | #[cfg_attr(test, assert_instr(umull2))] | |
4687 | pub unsafe fn vmull_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { | |
4688 | let a: uint32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
4689 | let b: uint32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
4690 | vmull_u32(a, b) | |
4691 | } | |
4692 | ||
4693 | /// Polynomial multiply long | |
4694 | #[inline] | |
94222f64 | 4695 | #[target_feature(enable = "neon,aes")] |
17df50a5 XL |
4696 | #[cfg_attr(test, assert_instr(pmull))] |
4697 | pub unsafe fn vmull_p64(a: p64, b: p64) -> p128 { | |
4698 | #[allow(improper_ctypes)] | |
4699 | extern "C" { | |
4700 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.pmull64")] | |
4701 | fn vmull_p64_(a: p64, b: p64) -> int8x16_t; | |
4702 | } | |
4703 | transmute(vmull_p64_(a, b)) | |
4704 | } | |
4705 | ||
4706 | /// Polynomial multiply long | |
4707 | #[inline] | |
4708 | #[target_feature(enable = "neon")] | |
4709 | #[cfg_attr(test, assert_instr(pmull))] | |
4710 | pub unsafe fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t { | |
4711 | let a: poly8x8_t = simd_shuffle8!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); | |
4712 | let b: poly8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
4713 | vmull_p8(a, b) | |
4714 | } | |
4715 | ||
4716 | /// Polynomial multiply long | |
4717 | #[inline] | |
94222f64 | 4718 | #[target_feature(enable = "neon,aes")] |
17df50a5 XL |
4719 | #[cfg_attr(test, assert_instr(pmull))] |
4720 | pub unsafe fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 { | |
4721 | vmull_p64(simd_extract(a, 1), simd_extract(b, 1)) | |
4722 | } | |
4723 | ||
4724 | /// Multiply long | |
4725 | #[inline] | |
4726 | #[target_feature(enable = "neon")] | |
4727 | #[cfg_attr(test, assert_instr(smull2))] | |
4728 | pub unsafe fn vmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t { | |
4729 | vmull_high_s16(a, vdupq_n_s16(b)) | |
4730 | } | |
4731 | ||
4732 | /// Multiply long | |
4733 | #[inline] | |
4734 | #[target_feature(enable = "neon")] | |
4735 | #[cfg_attr(test, assert_instr(smull2))] | |
4736 | pub unsafe fn vmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t { | |
4737 | vmull_high_s32(a, vdupq_n_s32(b)) | |
4738 | } | |
4739 | ||
4740 | /// Multiply long | |
4741 | #[inline] | |
4742 | #[target_feature(enable = "neon")] | |
4743 | #[cfg_attr(test, assert_instr(umull2))] | |
4744 | pub unsafe fn vmull_high_n_u16(a: uint16x8_t, b: u16) -> uint32x4_t { | |
4745 | vmull_high_u16(a, vdupq_n_u16(b)) | |
4746 | } | |
4747 | ||
4748 | /// Multiply long | |
4749 | #[inline] | |
4750 | #[target_feature(enable = "neon")] | |
4751 | #[cfg_attr(test, assert_instr(umull2))] | |
4752 | pub unsafe fn vmull_high_n_u32(a: uint32x4_t, b: u32) -> uint64x2_t { | |
4753 | vmull_high_u32(a, vdupq_n_u32(b)) | |
4754 | } | |
4755 | ||
4756 | /// Multiply long | |
4757 | #[inline] | |
4758 | #[target_feature(enable = "neon")] | |
4759 | #[cfg_attr(test, assert_instr(smull2, LANE = 1))] | |
4760 | #[rustc_legacy_const_generics(2)] | |
4761 | pub unsafe fn vmull_high_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int32x4_t { | |
4762 | static_assert_imm2!(LANE); | |
4763 | vmull_high_s16(a, simd_shuffle8!(b, b, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
4764 | } | |
4765 | ||
4766 | /// Multiply long | |
4767 | #[inline] | |
4768 | #[target_feature(enable = "neon")] | |
4769 | #[cfg_attr(test, assert_instr(smull2, LANE = 1))] | |
4770 | #[rustc_legacy_const_generics(2)] | |
4771 | pub unsafe fn vmull_high_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int32x4_t { | |
4772 | static_assert_imm3!(LANE); | |
4773 | vmull_high_s16(a, simd_shuffle8!(b, b, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
4774 | } | |
4775 | ||
4776 | /// Multiply long | |
4777 | #[inline] | |
4778 | #[target_feature(enable = "neon")] | |
4779 | #[cfg_attr(test, assert_instr(smull2, LANE = 1))] | |
4780 | #[rustc_legacy_const_generics(2)] | |
4781 | pub unsafe fn vmull_high_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int64x2_t { | |
4782 | static_assert_imm1!(LANE); | |
4783 | vmull_high_s32(a, simd_shuffle4!(b, b, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
4784 | } | |
4785 | ||
4786 | /// Multiply long | |
4787 | #[inline] | |
4788 | #[target_feature(enable = "neon")] | |
4789 | #[cfg_attr(test, assert_instr(smull2, LANE = 1))] | |
4790 | #[rustc_legacy_const_generics(2)] | |
4791 | pub unsafe fn vmull_high_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int64x2_t { | |
4792 | static_assert_imm2!(LANE); | |
4793 | vmull_high_s32(a, simd_shuffle4!(b, b, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
4794 | } | |
4795 | ||
4796 | /// Multiply long | |
4797 | #[inline] | |
4798 | #[target_feature(enable = "neon")] | |
4799 | #[cfg_attr(test, assert_instr(umull2, LANE = 1))] | |
4800 | #[rustc_legacy_const_generics(2)] | |
4801 | pub unsafe fn vmull_high_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uint32x4_t { | |
4802 | static_assert_imm2!(LANE); | |
4803 | vmull_high_u16(a, simd_shuffle8!(b, b, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
4804 | } | |
4805 | ||
4806 | /// Multiply long | |
4807 | #[inline] | |
4808 | #[target_feature(enable = "neon")] | |
4809 | #[cfg_attr(test, assert_instr(umull2, LANE = 1))] | |
4810 | #[rustc_legacy_const_generics(2)] | |
4811 | pub unsafe fn vmull_high_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { | |
4812 | static_assert_imm3!(LANE); | |
4813 | vmull_high_u16(a, simd_shuffle8!(b, b, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
4814 | } | |
4815 | ||
4816 | /// Multiply long | |
4817 | #[inline] | |
4818 | #[target_feature(enable = "neon")] | |
4819 | #[cfg_attr(test, assert_instr(umull2, LANE = 1))] | |
4820 | #[rustc_legacy_const_generics(2)] | |
4821 | pub unsafe fn vmull_high_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uint64x2_t { | |
4822 | static_assert_imm1!(LANE); | |
4823 | vmull_high_u32(a, simd_shuffle4!(b, b, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
4824 | } | |
4825 | ||
4826 | /// Multiply long | |
4827 | #[inline] | |
4828 | #[target_feature(enable = "neon")] | |
4829 | #[cfg_attr(test, assert_instr(umull2, LANE = 1))] | |
4830 | #[rustc_legacy_const_generics(2)] | |
4831 | pub unsafe fn vmull_high_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { | |
4832 | static_assert_imm2!(LANE); | |
4833 | vmull_high_u32(a, simd_shuffle4!(b, b, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
4834 | } | |
4835 | ||
4836 | /// Floating-point multiply extended | |
4837 | #[inline] | |
4838 | #[target_feature(enable = "neon")] | |
4839 | #[cfg_attr(test, assert_instr(fmulx))] | |
4840 | pub unsafe fn vmulx_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
4841 | #[allow(improper_ctypes)] | |
4842 | extern "C" { | |
4843 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmulx.v2f32")] | |
4844 | fn vmulx_f32_(a: float32x2_t, b: float32x2_t) -> float32x2_t; | |
4845 | } | |
4846 | vmulx_f32_(a, b) | |
4847 | } | |
4848 | ||
4849 | /// Floating-point multiply extended | |
4850 | #[inline] | |
4851 | #[target_feature(enable = "neon")] | |
4852 | #[cfg_attr(test, assert_instr(fmulx))] | |
4853 | pub unsafe fn vmulxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
4854 | #[allow(improper_ctypes)] | |
4855 | extern "C" { | |
4856 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmulx.v4f32")] | |
4857 | fn vmulxq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t; | |
4858 | } | |
4859 | vmulxq_f32_(a, b) | |
4860 | } | |
4861 | ||
4862 | /// Floating-point multiply extended | |
4863 | #[inline] | |
4864 | #[target_feature(enable = "neon")] | |
4865 | #[cfg_attr(test, assert_instr(fmulx))] | |
4866 | pub unsafe fn vmulx_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
4867 | #[allow(improper_ctypes)] | |
4868 | extern "C" { | |
4869 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmulx.v1f64")] | |
4870 | fn vmulx_f64_(a: float64x1_t, b: float64x1_t) -> float64x1_t; | |
4871 | } | |
4872 | vmulx_f64_(a, b) | |
4873 | } | |
4874 | ||
4875 | /// Floating-point multiply extended | |
4876 | #[inline] | |
4877 | #[target_feature(enable = "neon")] | |
4878 | #[cfg_attr(test, assert_instr(fmulx))] | |
4879 | pub unsafe fn vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
4880 | #[allow(improper_ctypes)] | |
4881 | extern "C" { | |
4882 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmulx.v2f64")] | |
4883 | fn vmulxq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; | |
4884 | } | |
4885 | vmulxq_f64_(a, b) | |
4886 | } | |
4887 | ||
4888 | /// Floating-point multiply extended | |
4889 | #[inline] | |
4890 | #[target_feature(enable = "neon")] | |
4891 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
4892 | #[rustc_legacy_const_generics(2)] | |
4893 | pub unsafe fn vmulx_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
4894 | static_assert!(LANE : i32 where LANE == 0); | |
4895 | vmulx_f64(a, transmute::<f64, _>(simd_extract(b, LANE as u32))) | |
4896 | } | |
4897 | ||
4898 | /// Floating-point multiply extended | |
4899 | #[inline] | |
4900 | #[target_feature(enable = "neon")] | |
4901 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
4902 | #[rustc_legacy_const_generics(2)] | |
4903 | pub unsafe fn vmulx_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x2_t) -> float64x1_t { | |
4904 | static_assert_imm1!(LANE); | |
4905 | vmulx_f64(a, transmute::<f64, _>(simd_extract(b, LANE as u32))) | |
4906 | } | |
4907 | ||
4908 | /// Floating-point multiply extended | |
4909 | #[inline] | |
4910 | #[target_feature(enable = "neon")] | |
4911 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
4912 | #[rustc_legacy_const_generics(2)] | |
4913 | pub unsafe fn vmulx_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
4914 | static_assert_imm1!(LANE); | |
4915 | vmulx_f32(a, simd_shuffle2!(b, b, <const LANE: i32> [LANE as u32, LANE as u32])) | |
4916 | } | |
4917 | ||
4918 | /// Floating-point multiply extended | |
4919 | #[inline] | |
4920 | #[target_feature(enable = "neon")] | |
4921 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
4922 | #[rustc_legacy_const_generics(2)] | |
4923 | pub unsafe fn vmulx_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x4_t) -> float32x2_t { | |
4924 | static_assert_imm2!(LANE); | |
4925 | vmulx_f32(a, simd_shuffle2!(b, b, <const LANE: i32> [LANE as u32, LANE as u32])) | |
4926 | } | |
4927 | ||
4928 | /// Floating-point multiply extended | |
4929 | #[inline] | |
4930 | #[target_feature(enable = "neon")] | |
4931 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
4932 | #[rustc_legacy_const_generics(2)] | |
4933 | pub unsafe fn vmulxq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x2_t) -> float32x4_t { | |
4934 | static_assert_imm1!(LANE); | |
4935 | vmulxq_f32(a, simd_shuffle4!(b, b, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
4936 | } | |
4937 | ||
4938 | /// Floating-point multiply extended | |
4939 | #[inline] | |
4940 | #[target_feature(enable = "neon")] | |
4941 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
4942 | #[rustc_legacy_const_generics(2)] | |
4943 | pub unsafe fn vmulxq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
4944 | static_assert_imm2!(LANE); | |
4945 | vmulxq_f32(a, simd_shuffle4!(b, b, <const LANE: i32> [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) | |
4946 | } | |
4947 | ||
4948 | /// Floating-point multiply extended | |
4949 | #[inline] | |
4950 | #[target_feature(enable = "neon")] | |
4951 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
4952 | #[rustc_legacy_const_generics(2)] | |
4953 | pub unsafe fn vmulxq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x1_t) -> float64x2_t { | |
4954 | static_assert!(LANE : i32 where LANE == 0); | |
4955 | vmulxq_f64(a, simd_shuffle2!(b, b, <const LANE: i32> [LANE as u32, LANE as u32])) | |
4956 | } | |
4957 | ||
4958 | /// Floating-point multiply extended | |
4959 | #[inline] | |
4960 | #[target_feature(enable = "neon")] | |
4961 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
4962 | #[rustc_legacy_const_generics(2)] | |
4963 | pub unsafe fn vmulxq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
4964 | static_assert_imm1!(LANE); | |
4965 | vmulxq_f64(a, simd_shuffle2!(b, b, <const LANE: i32> [LANE as u32, LANE as u32])) | |
4966 | } | |
4967 | ||
4968 | /// Floating-point multiply extended | |
4969 | #[inline] | |
4970 | #[target_feature(enable = "neon")] | |
4971 | #[cfg_attr(test, assert_instr(fmulx))] | |
4972 | pub unsafe fn vmulxs_f32(a: f32, b: f32) -> f32 { | |
4973 | #[allow(improper_ctypes)] | |
4974 | extern "C" { | |
4975 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmulx.f32")] | |
4976 | fn vmulxs_f32_(a: f32, b: f32) -> f32; | |
4977 | } | |
4978 | vmulxs_f32_(a, b) | |
4979 | } | |
4980 | ||
4981 | /// Floating-point multiply extended | |
4982 | #[inline] | |
4983 | #[target_feature(enable = "neon")] | |
4984 | #[cfg_attr(test, assert_instr(fmulx))] | |
4985 | pub unsafe fn vmulxd_f64(a: f64, b: f64) -> f64 { | |
4986 | #[allow(improper_ctypes)] | |
4987 | extern "C" { | |
4988 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmulx.f64")] | |
4989 | fn vmulxd_f64_(a: f64, b: f64) -> f64; | |
4990 | } | |
4991 | vmulxd_f64_(a, b) | |
4992 | } | |
4993 | ||
4994 | /// Floating-point multiply extended | |
4995 | #[inline] | |
4996 | #[target_feature(enable = "neon")] | |
4997 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
4998 | #[rustc_legacy_const_generics(2)] | |
4999 | pub unsafe fn vmulxs_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> f32 { | |
5000 | static_assert_imm1!(LANE); | |
5001 | vmulxs_f32(a, simd_extract(b, LANE as u32)) | |
5002 | } | |
5003 | ||
5004 | /// Floating-point multiply extended | |
5005 | #[inline] | |
5006 | #[target_feature(enable = "neon")] | |
5007 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
5008 | #[rustc_legacy_const_generics(2)] | |
5009 | pub unsafe fn vmulxs_laneq_f32<const LANE: i32>(a: f32, b: float32x4_t) -> f32 { | |
5010 | static_assert_imm2!(LANE); | |
5011 | vmulxs_f32(a, simd_extract(b, LANE as u32)) | |
5012 | } | |
5013 | ||
5014 | /// Floating-point multiply extended | |
5015 | #[inline] | |
5016 | #[target_feature(enable = "neon")] | |
5017 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
5018 | #[rustc_legacy_const_generics(2)] | |
5019 | pub unsafe fn vmulxd_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> f64 { | |
5020 | static_assert!(LANE : i32 where LANE == 0); | |
5021 | vmulxd_f64(a, simd_extract(b, LANE as u32)) | |
5022 | } | |
5023 | ||
5024 | /// Floating-point multiply extended | |
5025 | #[inline] | |
5026 | #[target_feature(enable = "neon")] | |
5027 | #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] | |
5028 | #[rustc_legacy_const_generics(2)] | |
5029 | pub unsafe fn vmulxd_laneq_f64<const LANE: i32>(a: f64, b: float64x2_t) -> f64 { | |
5030 | static_assert_imm1!(LANE); | |
5031 | vmulxd_f64(a, simd_extract(b, LANE as u32)) | |
5032 | } | |
5033 | ||
5034 | /// Floating-point fused Multiply-Add to accumulator(vector) | |
5035 | #[inline] | |
5036 | #[target_feature(enable = "neon")] | |
5037 | #[cfg_attr(test, assert_instr(fmadd))] | |
5038 | pub unsafe fn vfma_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { | |
5039 | #[allow(improper_ctypes)] | |
5040 | extern "C" { | |
5041 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v1f64")] | |
5042 | fn vfma_f64_(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t; | |
5043 | } | |
5044 | vfma_f64_(b, c, a) | |
5045 | } | |
5046 | ||
5047 | /// Floating-point fused Multiply-Add to accumulator(vector) | |
5048 | #[inline] | |
5049 | #[target_feature(enable = "neon")] | |
5050 | #[cfg_attr(test, assert_instr(fmla))] | |
5051 | pub unsafe fn vfmaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { | |
5052 | #[allow(improper_ctypes)] | |
5053 | extern "C" { | |
5054 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v2f64")] | |
5055 | fn vfmaq_f64_(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; | |
5056 | } | |
5057 | vfmaq_f64_(b, c, a) | |
5058 | } | |
5059 | ||
5060 | /// Floating-point fused Multiply-Add to accumulator(vector) | |
5061 | #[inline] | |
5062 | #[target_feature(enable = "neon")] | |
5063 | #[cfg_attr(test, assert_instr(fmadd))] | |
5064 | pub unsafe fn vfma_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t { | |
5065 | vfma_f64(a, b, vdup_n_f64(c)) | |
5066 | } | |
5067 | ||
5068 | /// Floating-point fused Multiply-Add to accumulator(vector) | |
5069 | #[inline] | |
5070 | #[target_feature(enable = "neon")] | |
5071 | #[cfg_attr(test, assert_instr(fmla))] | |
5072 | pub unsafe fn vfmaq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t { | |
5073 | vfmaq_f64(a, b, vdupq_n_f64(c)) | |
5074 | } | |
5075 | ||
5076 | /// Floating-point fused multiply-add to accumulator | |
5077 | #[inline] | |
5078 | #[target_feature(enable = "neon")] | |
5079 | #[cfg_attr(test, assert_instr(fmla, LANE = 0))] | |
5080 | #[rustc_legacy_const_generics(3)] | |
5081 | pub unsafe fn vfma_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { | |
5082 | static_assert_imm1!(LANE); | |
5083 | vfma_f32(a, b, vdup_n_f32(simd_extract(c, LANE as u32))) | |
5084 | } | |
5085 | ||
5086 | /// Floating-point fused multiply-add to accumulator | |
5087 | #[inline] | |
5088 | #[target_feature(enable = "neon")] | |
5089 | #[cfg_attr(test, assert_instr(fmla, LANE = 0))] | |
5090 | #[rustc_legacy_const_generics(3)] | |
5091 | pub unsafe fn vfma_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t, c: float32x4_t) -> float32x2_t { | |
5092 | static_assert_imm2!(LANE); | |
5093 | vfma_f32(a, b, vdup_n_f32(simd_extract(c, LANE as u32))) | |
5094 | } | |
5095 | ||
5096 | /// Floating-point fused multiply-add to accumulator | |
5097 | #[inline] | |
5098 | #[target_feature(enable = "neon")] | |
5099 | #[cfg_attr(test, assert_instr(fmla, LANE = 0))] | |
5100 | #[rustc_legacy_const_generics(3)] | |
5101 | pub unsafe fn vfmaq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t, c: float32x2_t) -> float32x4_t { | |
5102 | static_assert_imm1!(LANE); | |
5103 | vfmaq_f32(a, b, vdupq_n_f32(simd_extract(c, LANE as u32))) | |
5104 | } | |
5105 | ||
5106 | /// Floating-point fused multiply-add to accumulator | |
5107 | #[inline] | |
5108 | #[target_feature(enable = "neon")] | |
5109 | #[cfg_attr(test, assert_instr(fmla, LANE = 0))] | |
5110 | #[rustc_legacy_const_generics(3)] | |
5111 | pub unsafe fn vfmaq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { | |
5112 | static_assert_imm2!(LANE); | |
5113 | vfmaq_f32(a, b, vdupq_n_f32(simd_extract(c, LANE as u32))) | |
5114 | } | |
5115 | ||
5116 | /// Floating-point fused multiply-add to accumulator | |
5117 | #[inline] | |
5118 | #[target_feature(enable = "neon")] | |
5119 | #[cfg_attr(test, assert_instr(fmadd, LANE = 0))] | |
5120 | #[rustc_legacy_const_generics(3)] | |
5121 | pub unsafe fn vfma_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { | |
5122 | static_assert!(LANE : i32 where LANE == 0); | |
5123 | vfma_f64(a, b, vdup_n_f64(simd_extract(c, LANE as u32))) | |
5124 | } | |
5125 | ||
5126 | /// Floating-point fused multiply-add to accumulator | |
5127 | #[inline] | |
5128 | #[target_feature(enable = "neon")] | |
5129 | #[cfg_attr(test, assert_instr(fmla, LANE = 0))] | |
5130 | #[rustc_legacy_const_generics(3)] | |
5131 | pub unsafe fn vfma_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t, c: float64x2_t) -> float64x1_t { | |
5132 | static_assert_imm1!(LANE); | |
5133 | vfma_f64(a, b, vdup_n_f64(simd_extract(c, LANE as u32))) | |
5134 | } | |
5135 | ||
5136 | /// Floating-point fused multiply-add to accumulator | |
5137 | #[inline] | |
5138 | #[target_feature(enable = "neon")] | |
5139 | #[cfg_attr(test, assert_instr(fmla, LANE = 0))] | |
5140 | #[rustc_legacy_const_generics(3)] | |
5141 | pub unsafe fn vfmaq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t, c: float64x1_t) -> float64x2_t { | |
5142 | static_assert!(LANE : i32 where LANE == 0); | |
5143 | vfmaq_f64(a, b, vdupq_n_f64(simd_extract(c, LANE as u32))) | |
5144 | } | |
5145 | ||
5146 | /// Floating-point fused multiply-add to accumulator | |
5147 | #[inline] | |
5148 | #[target_feature(enable = "neon")] | |
5149 | #[cfg_attr(test, assert_instr(fmla, LANE = 0))] | |
5150 | #[rustc_legacy_const_generics(3)] | |
5151 | pub unsafe fn vfmaq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { | |
5152 | static_assert_imm1!(LANE); | |
5153 | vfmaq_f64(a, b, vdupq_n_f64(simd_extract(c, LANE as u32))) | |
5154 | } | |
5155 | ||
5156 | /// Floating-point fused multiply-add to accumulator | |
5157 | #[inline] | |
5158 | #[target_feature(enable = "neon")] | |
5159 | #[cfg_attr(test, assert_instr(fmla, LANE = 0))] | |
5160 | #[rustc_legacy_const_generics(3)] | |
5161 | pub unsafe fn vfmas_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 { | |
5162 | #[allow(improper_ctypes)] | |
5163 | extern "C" { | |
5164 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.f32")] | |
5165 | fn vfmas_lane_f32_(a: f32, b: f32, c: f32) -> f32; | |
5166 | } | |
5167 | static_assert_imm1!(LANE); | |
5168 | let c: f32 = simd_extract(c, LANE as u32); | |
5169 | vfmas_lane_f32_(b, c, a) | |
5170 | } | |
5171 | ||
5172 | /// Floating-point fused multiply-add to accumulator | |
5173 | #[inline] | |
5174 | #[target_feature(enable = "neon")] | |
5175 | #[cfg_attr(test, assert_instr(fmla, LANE = 0))] | |
5176 | #[rustc_legacy_const_generics(3)] | |
5177 | pub unsafe fn vfmas_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 { | |
5178 | #[allow(improper_ctypes)] | |
5179 | extern "C" { | |
5180 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.f32")] | |
5181 | fn vfmas_laneq_f32_(a: f32, b: f32, c: f32) -> f32; | |
5182 | } | |
5183 | static_assert_imm2!(LANE); | |
5184 | let c: f32 = simd_extract(c, LANE as u32); | |
5185 | vfmas_laneq_f32_(b, c, a) | |
5186 | } | |
5187 | ||
5188 | /// Floating-point fused multiply-add to accumulator | |
5189 | #[inline] | |
5190 | #[target_feature(enable = "neon")] | |
5191 | #[cfg_attr(test, assert_instr(fmadd, LANE = 0))] | |
5192 | #[rustc_legacy_const_generics(3)] | |
5193 | pub unsafe fn vfmad_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) -> f64 { | |
5194 | #[allow(improper_ctypes)] | |
5195 | extern "C" { | |
5196 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.f64")] | |
5197 | fn vfmad_lane_f64_(a: f64, b: f64, c: f64) -> f64; | |
5198 | } | |
5199 | static_assert!(LANE : i32 where LANE == 0); | |
5200 | let c: f64 = simd_extract(c, LANE as u32); | |
5201 | vfmad_lane_f64_(b, c, a) | |
5202 | } | |
5203 | ||
5204 | /// Floating-point fused multiply-add to accumulator | |
5205 | #[inline] | |
5206 | #[target_feature(enable = "neon")] | |
5207 | #[cfg_attr(test, assert_instr(fmla, LANE = 0))] | |
5208 | #[rustc_legacy_const_generics(3)] | |
5209 | pub unsafe fn vfmad_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 { | |
5210 | #[allow(improper_ctypes)] | |
5211 | extern "C" { | |
5212 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.f64")] | |
5213 | fn vfmad_laneq_f64_(a: f64, b: f64, c: f64) -> f64; | |
5214 | } | |
5215 | static_assert_imm1!(LANE); | |
5216 | let c: f64 = simd_extract(c, LANE as u32); | |
5217 | vfmad_laneq_f64_(b, c, a) | |
5218 | } | |
5219 | ||
5220 | /// Floating-point fused multiply-subtract from accumulator | |
5221 | #[inline] | |
5222 | #[target_feature(enable = "neon")] | |
5223 | #[cfg_attr(test, assert_instr(fmsub))] | |
5224 | pub unsafe fn vfms_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { | |
5225 | let b: float64x1_t = simd_neg(b); | |
5226 | vfma_f64(a, b, c) | |
5227 | } | |
5228 | ||
5229 | /// Floating-point fused multiply-subtract from accumulator | |
5230 | #[inline] | |
5231 | #[target_feature(enable = "neon")] | |
5232 | #[cfg_attr(test, assert_instr(fmls))] | |
5233 | pub unsafe fn vfmsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { | |
5234 | let b: float64x2_t = simd_neg(b); | |
5235 | vfmaq_f64(a, b, c) | |
5236 | } | |
5237 | ||
5238 | /// Floating-point fused Multiply-subtract to accumulator(vector) | |
5239 | #[inline] | |
5240 | #[target_feature(enable = "neon")] | |
5241 | #[cfg_attr(test, assert_instr(fmsub))] | |
5242 | pub unsafe fn vfms_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t { | |
5243 | vfms_f64(a, b, vdup_n_f64(c)) | |
5244 | } | |
5245 | ||
5246 | /// Floating-point fused Multiply-subtract to accumulator(vector) | |
5247 | #[inline] | |
5248 | #[target_feature(enable = "neon")] | |
5249 | #[cfg_attr(test, assert_instr(fmls))] | |
5250 | pub unsafe fn vfmsq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t { | |
5251 | vfmsq_f64(a, b, vdupq_n_f64(c)) | |
5252 | } | |
5253 | ||
5254 | /// Floating-point fused multiply-subtract to accumulator | |
5255 | #[inline] | |
5256 | #[target_feature(enable = "neon")] | |
5257 | #[cfg_attr(test, assert_instr(fmls, LANE = 0))] | |
5258 | #[rustc_legacy_const_generics(3)] | |
5259 | pub unsafe fn vfms_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { | |
5260 | static_assert_imm1!(LANE); | |
5261 | vfms_f32(a, b, vdup_n_f32(simd_extract(c, LANE as u32))) | |
5262 | } | |
5263 | ||
5264 | /// Floating-point fused multiply-subtract to accumulator | |
5265 | #[inline] | |
5266 | #[target_feature(enable = "neon")] | |
5267 | #[cfg_attr(test, assert_instr(fmls, LANE = 0))] | |
5268 | #[rustc_legacy_const_generics(3)] | |
5269 | pub unsafe fn vfms_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t, c: float32x4_t) -> float32x2_t { | |
5270 | static_assert_imm2!(LANE); | |
5271 | vfms_f32(a, b, vdup_n_f32(simd_extract(c, LANE as u32))) | |
5272 | } | |
5273 | ||
5274 | /// Floating-point fused multiply-subtract to accumulator | |
5275 | #[inline] | |
5276 | #[target_feature(enable = "neon")] | |
5277 | #[cfg_attr(test, assert_instr(fmls, LANE = 0))] | |
5278 | #[rustc_legacy_const_generics(3)] | |
5279 | pub unsafe fn vfmsq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t, c: float32x2_t) -> float32x4_t { | |
5280 | static_assert_imm1!(LANE); | |
5281 | vfmsq_f32(a, b, vdupq_n_f32(simd_extract(c, LANE as u32))) | |
5282 | } | |
5283 | ||
5284 | /// Floating-point fused multiply-subtract to accumulator | |
5285 | #[inline] | |
5286 | #[target_feature(enable = "neon")] | |
5287 | #[cfg_attr(test, assert_instr(fmls, LANE = 0))] | |
5288 | #[rustc_legacy_const_generics(3)] | |
5289 | pub unsafe fn vfmsq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { | |
5290 | static_assert_imm2!(LANE); | |
5291 | vfmsq_f32(a, b, vdupq_n_f32(simd_extract(c, LANE as u32))) | |
5292 | } | |
5293 | ||
5294 | /// Floating-point fused multiply-subtract to accumulator | |
5295 | #[inline] | |
5296 | #[target_feature(enable = "neon")] | |
5297 | #[cfg_attr(test, assert_instr(fmsub, LANE = 0))] | |
5298 | #[rustc_legacy_const_generics(3)] | |
5299 | pub unsafe fn vfms_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { | |
5300 | static_assert!(LANE : i32 where LANE == 0); | |
5301 | vfms_f64(a, b, vdup_n_f64(simd_extract(c, LANE as u32))) | |
5302 | } | |
5303 | ||
5304 | /// Floating-point fused multiply-subtract to accumulator | |
5305 | #[inline] | |
5306 | #[target_feature(enable = "neon")] | |
5307 | #[cfg_attr(test, assert_instr(fmls, LANE = 0))] | |
5308 | #[rustc_legacy_const_generics(3)] | |
5309 | pub unsafe fn vfms_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t, c: float64x2_t) -> float64x1_t { | |
5310 | static_assert_imm1!(LANE); | |
5311 | vfms_f64(a, b, vdup_n_f64(simd_extract(c, LANE as u32))) | |
5312 | } | |
5313 | ||
5314 | /// Floating-point fused multiply-subtract to accumulator | |
5315 | #[inline] | |
5316 | #[target_feature(enable = "neon")] | |
5317 | #[cfg_attr(test, assert_instr(fmls, LANE = 0))] | |
5318 | #[rustc_legacy_const_generics(3)] | |
5319 | pub unsafe fn vfmsq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t, c: float64x1_t) -> float64x2_t { | |
5320 | static_assert!(LANE : i32 where LANE == 0); | |
5321 | vfmsq_f64(a, b, vdupq_n_f64(simd_extract(c, LANE as u32))) | |
5322 | } | |
5323 | ||
5324 | /// Floating-point fused multiply-subtract to accumulator | |
5325 | #[inline] | |
5326 | #[target_feature(enable = "neon")] | |
5327 | #[cfg_attr(test, assert_instr(fmls, LANE = 0))] | |
5328 | #[rustc_legacy_const_generics(3)] | |
5329 | pub unsafe fn vfmsq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { | |
5330 | static_assert_imm1!(LANE); | |
5331 | vfmsq_f64(a, b, vdupq_n_f64(simd_extract(c, LANE as u32))) | |
5332 | } | |
5333 | ||
5334 | /// Floating-point fused multiply-subtract to accumulator | |
5335 | #[inline] | |
5336 | #[target_feature(enable = "neon")] | |
5337 | #[cfg_attr(test, assert_instr(fmls, LANE = 0))] | |
5338 | #[rustc_legacy_const_generics(3)] | |
5339 | pub unsafe fn vfmss_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 { | |
5340 | vfmas_lane_f32::<LANE>(a, -b, c) | |
5341 | } | |
5342 | ||
5343 | /// Floating-point fused multiply-subtract to accumulator | |
5344 | #[inline] | |
5345 | #[target_feature(enable = "neon")] | |
5346 | #[cfg_attr(test, assert_instr(fmls, LANE = 0))] | |
5347 | #[rustc_legacy_const_generics(3)] | |
5348 | pub unsafe fn vfmss_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 { | |
5349 | vfmas_laneq_f32::<LANE>(a, -b, c) | |
5350 | } | |
5351 | ||
5352 | /// Floating-point fused multiply-subtract to accumulator | |
5353 | #[inline] | |
5354 | #[target_feature(enable = "neon")] | |
5355 | #[cfg_attr(test, assert_instr(fmsub, LANE = 0))] | |
5356 | #[rustc_legacy_const_generics(3)] | |
5357 | pub unsafe fn vfmsd_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) -> f64 { | |
5358 | vfmad_lane_f64::<LANE>(a, -b, c) | |
5359 | } | |
5360 | ||
5361 | /// Floating-point fused multiply-subtract to accumulator | |
5362 | #[inline] | |
5363 | #[target_feature(enable = "neon")] | |
5364 | #[cfg_attr(test, assert_instr(fmls, LANE = 0))] | |
5365 | #[rustc_legacy_const_generics(3)] | |
5366 | pub unsafe fn vfmsd_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 { | |
5367 | vfmad_laneq_f64::<LANE>(a, -b, c) | |
5368 | } | |
5369 | ||
5370 | /// Divide | |
5371 | #[inline] | |
5372 | #[target_feature(enable = "neon")] | |
5373 | #[cfg_attr(test, assert_instr(fdiv))] | |
5374 | pub unsafe fn vdiv_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
5375 | simd_div(a, b) | |
5376 | } | |
5377 | ||
5378 | /// Divide | |
5379 | #[inline] | |
5380 | #[target_feature(enable = "neon")] | |
5381 | #[cfg_attr(test, assert_instr(fdiv))] | |
5382 | pub unsafe fn vdivq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
5383 | simd_div(a, b) | |
5384 | } | |
5385 | ||
5386 | /// Divide | |
5387 | #[inline] | |
5388 | #[target_feature(enable = "neon")] | |
5389 | #[cfg_attr(test, assert_instr(fdiv))] | |
5390 | pub unsafe fn vdiv_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
5391 | simd_div(a, b) | |
5392 | } | |
5393 | ||
5394 | /// Divide | |
5395 | #[inline] | |
5396 | #[target_feature(enable = "neon")] | |
5397 | #[cfg_attr(test, assert_instr(fdiv))] | |
5398 | pub unsafe fn vdivq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
5399 | simd_div(a, b) | |
5400 | } | |
5401 | ||
5402 | /// Subtract | |
5403 | #[inline] | |
5404 | #[target_feature(enable = "neon")] | |
5405 | #[cfg_attr(test, assert_instr(fsub))] | |
5406 | pub unsafe fn vsub_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
5407 | simd_sub(a, b) | |
5408 | } | |
5409 | ||
5410 | /// Subtract | |
5411 | #[inline] | |
5412 | #[target_feature(enable = "neon")] | |
5413 | #[cfg_attr(test, assert_instr(fsub))] | |
5414 | pub unsafe fn vsubq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
5415 | simd_sub(a, b) | |
5416 | } | |
5417 | ||
5418 | /// Signed Add Long across Vector | |
5419 | #[inline] | |
5420 | #[target_feature(enable = "neon")] | |
5421 | #[cfg_attr(test, assert_instr(saddlv))] | |
5422 | pub unsafe fn vaddlv_s16(a: int16x4_t) -> i32 { | |
5423 | #[allow(improper_ctypes)] | |
5424 | extern "C" { | |
5425 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.saddlv.i32.v4i16")] | |
5426 | fn vaddlv_s16_(a: int16x4_t) -> i32; | |
5427 | } | |
5428 | vaddlv_s16_(a) | |
5429 | } | |
5430 | ||
5431 | /// Signed Add Long across Vector | |
5432 | #[inline] | |
5433 | #[target_feature(enable = "neon")] | |
5434 | #[cfg_attr(test, assert_instr(saddlv))] | |
5435 | pub unsafe fn vaddlvq_s16(a: int16x8_t) -> i32 { | |
5436 | #[allow(improper_ctypes)] | |
5437 | extern "C" { | |
5438 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.saddlv.i32.v8i16")] | |
5439 | fn vaddlvq_s16_(a: int16x8_t) -> i32; | |
5440 | } | |
5441 | vaddlvq_s16_(a) | |
5442 | } | |
5443 | ||
5444 | /// Signed Add Long across Vector | |
5445 | #[inline] | |
5446 | #[target_feature(enable = "neon")] | |
5447 | #[cfg_attr(test, assert_instr(saddlp))] | |
5448 | pub unsafe fn vaddlv_s32(a: int32x2_t) -> i64 { | |
5449 | #[allow(improper_ctypes)] | |
5450 | extern "C" { | |
5451 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.saddlv.i64.v2i32")] | |
5452 | fn vaddlv_s32_(a: int32x2_t) -> i64; | |
5453 | } | |
5454 | vaddlv_s32_(a) | |
5455 | } | |
5456 | ||
5457 | /// Signed Add Long across Vector | |
5458 | #[inline] | |
5459 | #[target_feature(enable = "neon")] | |
5460 | #[cfg_attr(test, assert_instr(saddlv))] | |
5461 | pub unsafe fn vaddlvq_s32(a: int32x4_t) -> i64 { | |
5462 | #[allow(improper_ctypes)] | |
5463 | extern "C" { | |
5464 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.saddlv.i64.v4i32")] | |
5465 | fn vaddlvq_s32_(a: int32x4_t) -> i64; | |
5466 | } | |
5467 | vaddlvq_s32_(a) | |
5468 | } | |
5469 | ||
5470 | /// Unsigned Add Long across Vector | |
5471 | #[inline] | |
5472 | #[target_feature(enable = "neon")] | |
5473 | #[cfg_attr(test, assert_instr(uaddlv))] | |
5474 | pub unsafe fn vaddlv_u16(a: uint16x4_t) -> u32 { | |
5475 | #[allow(improper_ctypes)] | |
5476 | extern "C" { | |
5477 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uaddlv.i32.v4i16")] | |
5478 | fn vaddlv_u16_(a: uint16x4_t) -> u32; | |
5479 | } | |
5480 | vaddlv_u16_(a) | |
5481 | } | |
5482 | ||
5483 | /// Unsigned Add Long across Vector | |
5484 | #[inline] | |
5485 | #[target_feature(enable = "neon")] | |
5486 | #[cfg_attr(test, assert_instr(uaddlv))] | |
5487 | pub unsafe fn vaddlvq_u16(a: uint16x8_t) -> u32 { | |
5488 | #[allow(improper_ctypes)] | |
5489 | extern "C" { | |
5490 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uaddlv.i32.v8i16")] | |
5491 | fn vaddlvq_u16_(a: uint16x8_t) -> u32; | |
5492 | } | |
5493 | vaddlvq_u16_(a) | |
5494 | } | |
5495 | ||
5496 | /// Unsigned Add Long across Vector | |
5497 | #[inline] | |
5498 | #[target_feature(enable = "neon")] | |
5499 | #[cfg_attr(test, assert_instr(uaddlp))] | |
5500 | pub unsafe fn vaddlv_u32(a: uint32x2_t) -> u64 { | |
5501 | #[allow(improper_ctypes)] | |
5502 | extern "C" { | |
5503 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uaddlv.i64.v2i32")] | |
5504 | fn vaddlv_u32_(a: uint32x2_t) -> u64; | |
5505 | } | |
5506 | vaddlv_u32_(a) | |
5507 | } | |
5508 | ||
5509 | /// Unsigned Add Long across Vector | |
5510 | #[inline] | |
5511 | #[target_feature(enable = "neon")] | |
5512 | #[cfg_attr(test, assert_instr(uaddlv))] | |
5513 | pub unsafe fn vaddlvq_u32(a: uint32x4_t) -> u64 { | |
5514 | #[allow(improper_ctypes)] | |
5515 | extern "C" { | |
5516 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uaddlv.i64.v4i32")] | |
5517 | fn vaddlvq_u32_(a: uint32x4_t) -> u64; | |
5518 | } | |
5519 | vaddlvq_u32_(a) | |
5520 | } | |
5521 | ||
5522 | /// Signed Subtract Wide | |
5523 | #[inline] | |
5524 | #[target_feature(enable = "neon")] | |
5525 | #[cfg_attr(test, assert_instr(ssubw))] | |
5526 | pub unsafe fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { | |
5527 | let c: int8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
5528 | simd_sub(a, simd_cast(c)) | |
5529 | } | |
5530 | ||
5531 | /// Signed Subtract Wide | |
5532 | #[inline] | |
5533 | #[target_feature(enable = "neon")] | |
5534 | #[cfg_attr(test, assert_instr(ssubw))] | |
5535 | pub unsafe fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { | |
5536 | let c: int16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
5537 | simd_sub(a, simd_cast(c)) | |
5538 | } | |
5539 | ||
5540 | /// Signed Subtract Wide | |
5541 | #[inline] | |
5542 | #[target_feature(enable = "neon")] | |
5543 | #[cfg_attr(test, assert_instr(ssubw))] | |
5544 | pub unsafe fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { | |
5545 | let c: int32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
5546 | simd_sub(a, simd_cast(c)) | |
5547 | } | |
5548 | ||
5549 | /// Unsigned Subtract Wide | |
5550 | #[inline] | |
5551 | #[target_feature(enable = "neon")] | |
5552 | #[cfg_attr(test, assert_instr(usubw))] | |
5553 | pub unsafe fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { | |
5554 | let c: uint8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
5555 | simd_sub(a, simd_cast(c)) | |
5556 | } | |
5557 | ||
5558 | /// Unsigned Subtract Wide | |
5559 | #[inline] | |
5560 | #[target_feature(enable = "neon")] | |
5561 | #[cfg_attr(test, assert_instr(usubw))] | |
5562 | pub unsafe fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { | |
5563 | let c: uint16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
5564 | simd_sub(a, simd_cast(c)) | |
5565 | } | |
5566 | ||
5567 | /// Unsigned Subtract Wide | |
5568 | #[inline] | |
5569 | #[target_feature(enable = "neon")] | |
5570 | #[cfg_attr(test, assert_instr(usubw))] | |
5571 | pub unsafe fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { | |
5572 | let c: uint32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
5573 | simd_sub(a, simd_cast(c)) | |
5574 | } | |
5575 | ||
5576 | /// Signed Subtract Long | |
5577 | #[inline] | |
5578 | #[target_feature(enable = "neon")] | |
5579 | #[cfg_attr(test, assert_instr(ssubl))] | |
5580 | pub unsafe fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { | |
5581 | let c: int8x8_t = simd_shuffle8!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); | |
5582 | let d: int16x8_t = simd_cast(c); | |
5583 | let e: int8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
5584 | let f: int16x8_t = simd_cast(e); | |
5585 | simd_sub(d, f) | |
5586 | } | |
5587 | ||
5588 | /// Signed Subtract Long | |
5589 | #[inline] | |
5590 | #[target_feature(enable = "neon")] | |
5591 | #[cfg_attr(test, assert_instr(ssubl))] | |
5592 | pub unsafe fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { | |
5593 | let c: int16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
5594 | let d: int32x4_t = simd_cast(c); | |
5595 | let e: int16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
5596 | let f: int32x4_t = simd_cast(e); | |
5597 | simd_sub(d, f) | |
5598 | } | |
5599 | ||
5600 | /// Signed Subtract Long | |
5601 | #[inline] | |
5602 | #[target_feature(enable = "neon")] | |
5603 | #[cfg_attr(test, assert_instr(ssubl))] | |
5604 | pub unsafe fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { | |
5605 | let c: int32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
5606 | let d: int64x2_t = simd_cast(c); | |
5607 | let e: int32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
5608 | let f: int64x2_t = simd_cast(e); | |
5609 | simd_sub(d, f) | |
5610 | } | |
5611 | ||
5612 | /// Unsigned Subtract Long | |
5613 | #[inline] | |
5614 | #[target_feature(enable = "neon")] | |
5615 | #[cfg_attr(test, assert_instr(usubl))] | |
5616 | pub unsafe fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { | |
5617 | let c: uint8x8_t = simd_shuffle8!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); | |
5618 | let d: uint16x8_t = simd_cast(c); | |
5619 | let e: uint8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
5620 | let f: uint16x8_t = simd_cast(e); | |
5621 | simd_sub(d, f) | |
5622 | } | |
5623 | ||
5624 | /// Unsigned Subtract Long | |
5625 | #[inline] | |
5626 | #[target_feature(enable = "neon")] | |
5627 | #[cfg_attr(test, assert_instr(usubl))] | |
5628 | pub unsafe fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { | |
5629 | let c: uint16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
5630 | let d: uint32x4_t = simd_cast(c); | |
5631 | let e: uint16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
5632 | let f: uint32x4_t = simd_cast(e); | |
5633 | simd_sub(d, f) | |
5634 | } | |
5635 | ||
5636 | /// Unsigned Subtract Long | |
5637 | #[inline] | |
5638 | #[target_feature(enable = "neon")] | |
5639 | #[cfg_attr(test, assert_instr(usubl))] | |
5640 | pub unsafe fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { | |
5641 | let c: uint32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
5642 | let d: uint64x2_t = simd_cast(c); | |
5643 | let e: uint32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
5644 | let f: uint64x2_t = simd_cast(e); | |
5645 | simd_sub(d, f) | |
5646 | } | |
5647 | ||
5648 | /// Maximum (vector) | |
5649 | #[inline] | |
5650 | #[target_feature(enable = "neon")] | |
5651 | #[cfg_attr(test, assert_instr(fmax))] | |
5652 | pub unsafe fn vmax_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
5653 | #[allow(improper_ctypes)] | |
5654 | extern "C" { | |
5655 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmax.v1f64")] | |
5656 | fn vmax_f64_(a: float64x1_t, b: float64x1_t) -> float64x1_t; | |
5657 | } | |
5658 | vmax_f64_(a, b) | |
5659 | } | |
5660 | ||
5661 | /// Maximum (vector) | |
5662 | #[inline] | |
5663 | #[target_feature(enable = "neon")] | |
5664 | #[cfg_attr(test, assert_instr(fmax))] | |
5665 | pub unsafe fn vmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
5666 | #[allow(improper_ctypes)] | |
5667 | extern "C" { | |
5668 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmax.v2f64")] | |
5669 | fn vmaxq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; | |
5670 | } | |
5671 | vmaxq_f64_(a, b) | |
5672 | } | |
5673 | ||
5674 | /// Floating-point Maximun Number (vector) | |
5675 | #[inline] | |
5676 | #[target_feature(enable = "neon")] | |
5677 | #[cfg_attr(test, assert_instr(fmaxnm))] | |
5678 | pub unsafe fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
5679 | #[allow(improper_ctypes)] | |
5680 | extern "C" { | |
5681 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmaxnm.v1f64")] | |
5682 | fn vmaxnm_f64_(a: float64x1_t, b: float64x1_t) -> float64x1_t; | |
5683 | } | |
5684 | vmaxnm_f64_(a, b) | |
5685 | } | |
5686 | ||
5687 | /// Floating-point Maximun Number (vector) | |
5688 | #[inline] | |
5689 | #[target_feature(enable = "neon")] | |
5690 | #[cfg_attr(test, assert_instr(fmaxnm))] | |
5691 | pub unsafe fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
5692 | #[allow(improper_ctypes)] | |
5693 | extern "C" { | |
5694 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmaxnm.v2f64")] | |
5695 | fn vmaxnmq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; | |
5696 | } | |
5697 | vmaxnmq_f64_(a, b) | |
5698 | } | |
5699 | ||
5700 | /// Floating-point Maximum Number Pairwise (vector). | |
5701 | #[inline] | |
5702 | #[target_feature(enable = "neon")] | |
5703 | #[cfg_attr(test, assert_instr(fmaxnmp))] | |
5704 | pub unsafe fn vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
5705 | #[allow(improper_ctypes)] | |
5706 | extern "C" { | |
5707 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmaxnmp.v2f32")] | |
5708 | fn vpmaxnm_f32_(a: float32x2_t, b: float32x2_t) -> float32x2_t; | |
5709 | } | |
5710 | vpmaxnm_f32_(a, b) | |
5711 | } | |
5712 | ||
5713 | /// Floating-point Maximum Number Pairwise (vector). | |
5714 | #[inline] | |
5715 | #[target_feature(enable = "neon")] | |
5716 | #[cfg_attr(test, assert_instr(fmaxnmp))] | |
5717 | pub unsafe fn vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
5718 | #[allow(improper_ctypes)] | |
5719 | extern "C" { | |
5720 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmaxnmp.v2f64")] | |
5721 | fn vpmaxnmq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; | |
5722 | } | |
5723 | vpmaxnmq_f64_(a, b) | |
5724 | } | |
5725 | ||
5726 | /// Floating-point Maximum Number Pairwise (vector). | |
5727 | #[inline] | |
5728 | #[target_feature(enable = "neon")] | |
5729 | #[cfg_attr(test, assert_instr(fmaxnmp))] | |
5730 | pub unsafe fn vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
5731 | #[allow(improper_ctypes)] | |
5732 | extern "C" { | |
5733 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmaxnmp.v4f32")] | |
5734 | fn vpmaxnmq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t; | |
5735 | } | |
5736 | vpmaxnmq_f32_(a, b) | |
5737 | } | |
5738 | ||
5739 | /// Minimum (vector) | |
5740 | #[inline] | |
5741 | #[target_feature(enable = "neon")] | |
5742 | #[cfg_attr(test, assert_instr(fmin))] | |
5743 | pub unsafe fn vmin_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
5744 | #[allow(improper_ctypes)] | |
5745 | extern "C" { | |
5746 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmin.v1f64")] | |
5747 | fn vmin_f64_(a: float64x1_t, b: float64x1_t) -> float64x1_t; | |
5748 | } | |
5749 | vmin_f64_(a, b) | |
5750 | } | |
5751 | ||
5752 | /// Minimum (vector) | |
5753 | #[inline] | |
5754 | #[target_feature(enable = "neon")] | |
5755 | #[cfg_attr(test, assert_instr(fmin))] | |
5756 | pub unsafe fn vminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
5757 | #[allow(improper_ctypes)] | |
5758 | extern "C" { | |
5759 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmin.v2f64")] | |
5760 | fn vminq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; | |
5761 | } | |
5762 | vminq_f64_(a, b) | |
5763 | } | |
5764 | ||
5765 | /// Floating-point Minimun Number (vector) | |
5766 | #[inline] | |
5767 | #[target_feature(enable = "neon")] | |
5768 | #[cfg_attr(test, assert_instr(fminnm))] | |
5769 | pub unsafe fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
5770 | #[allow(improper_ctypes)] | |
5771 | extern "C" { | |
5772 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fminnm.v1f64")] | |
5773 | fn vminnm_f64_(a: float64x1_t, b: float64x1_t) -> float64x1_t; | |
5774 | } | |
5775 | vminnm_f64_(a, b) | |
5776 | } | |
5777 | ||
5778 | /// Floating-point Minimun Number (vector) | |
5779 | #[inline] | |
5780 | #[target_feature(enable = "neon")] | |
5781 | #[cfg_attr(test, assert_instr(fminnm))] | |
5782 | pub unsafe fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
5783 | #[allow(improper_ctypes)] | |
5784 | extern "C" { | |
5785 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fminnm.v2f64")] | |
5786 | fn vminnmq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; | |
5787 | } | |
5788 | vminnmq_f64_(a, b) | |
5789 | } | |
5790 | ||
5791 | /// Floating-point Minimum Number Pairwise (vector). | |
5792 | #[inline] | |
5793 | #[target_feature(enable = "neon")] | |
5794 | #[cfg_attr(test, assert_instr(fminnmp))] | |
5795 | pub unsafe fn vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
5796 | #[allow(improper_ctypes)] | |
5797 | extern "C" { | |
5798 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fminnmp.v2f32")] | |
5799 | fn vpminnm_f32_(a: float32x2_t, b: float32x2_t) -> float32x2_t; | |
5800 | } | |
5801 | vpminnm_f32_(a, b) | |
5802 | } | |
5803 | ||
5804 | /// Floating-point Minimum Number Pairwise (vector). | |
5805 | #[inline] | |
5806 | #[target_feature(enable = "neon")] | |
5807 | #[cfg_attr(test, assert_instr(fminnmp))] | |
5808 | pub unsafe fn vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
5809 | #[allow(improper_ctypes)] | |
5810 | extern "C" { | |
5811 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fminnmp.v2f64")] | |
5812 | fn vpminnmq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; | |
5813 | } | |
5814 | vpminnmq_f64_(a, b) | |
5815 | } | |
5816 | ||
5817 | /// Floating-point Minimum Number Pairwise (vector). | |
5818 | #[inline] | |
5819 | #[target_feature(enable = "neon")] | |
5820 | #[cfg_attr(test, assert_instr(fminnmp))] | |
5821 | pub unsafe fn vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
5822 | #[allow(improper_ctypes)] | |
5823 | extern "C" { | |
5824 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fminnmp.v4f32")] | |
5825 | fn vpminnmq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t; | |
5826 | } | |
5827 | vpminnmq_f32_(a, b) | |
5828 | } | |
5829 | ||
5830 | /// Signed saturating doubling multiply long | |
5831 | #[inline] | |
5832 | #[target_feature(enable = "neon")] | |
5833 | #[cfg_attr(test, assert_instr(sqdmull))] | |
5834 | pub unsafe fn vqdmullh_s16(a: i16, b: i16) -> i32 { | |
5835 | let a: int16x4_t = vdup_n_s16(a); | |
5836 | let b: int16x4_t = vdup_n_s16(b); | |
5837 | simd_extract(vqdmull_s16(a, b), 0) | |
5838 | } | |
5839 | ||
5840 | /// Signed saturating doubling multiply long | |
5841 | #[inline] | |
5842 | #[target_feature(enable = "neon")] | |
5843 | #[cfg_attr(test, assert_instr(sqdmull))] | |
5844 | pub unsafe fn vqdmulls_s32(a: i32, b: i32) -> i64 { | |
5845 | #[allow(improper_ctypes)] | |
5846 | extern "C" { | |
5847 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqdmulls.scalar")] | |
5848 | fn vqdmulls_s32_(a: i32, b: i32) -> i64; | |
5849 | } | |
5850 | vqdmulls_s32_(a, b) | |
5851 | } | |
5852 | ||
5853 | /// Signed saturating doubling multiply long | |
5854 | #[inline] | |
5855 | #[target_feature(enable = "neon")] | |
5856 | #[cfg_attr(test, assert_instr(sqdmull2))] | |
5857 | pub unsafe fn vqdmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { | |
5858 | let a: int16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
5859 | let b: int16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
5860 | vqdmull_s16(a, b) | |
5861 | } | |
5862 | ||
5863 | /// Signed saturating doubling multiply long | |
5864 | #[inline] | |
5865 | #[target_feature(enable = "neon")] | |
5866 | #[cfg_attr(test, assert_instr(sqdmull2))] | |
5867 | pub unsafe fn vqdmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { | |
5868 | let a: int32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
5869 | let b: int32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
5870 | vqdmull_s32(a, b) | |
5871 | } | |
5872 | ||
5873 | /// Signed saturating doubling multiply long | |
5874 | #[inline] | |
5875 | #[target_feature(enable = "neon")] | |
5876 | #[cfg_attr(test, assert_instr(sqdmull2))] | |
5877 | pub unsafe fn vqdmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t { | |
5878 | let a: int16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
5879 | let b: int16x4_t = vdup_n_s16(b); | |
5880 | vqdmull_s16(a, b) | |
5881 | } | |
5882 | ||
5883 | /// Signed saturating doubling multiply long | |
5884 | #[inline] | |
5885 | #[target_feature(enable = "neon")] | |
5886 | #[cfg_attr(test, assert_instr(sqdmull2))] | |
5887 | pub unsafe fn vqdmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t { | |
5888 | let a: int32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
5889 | let b: int32x2_t = vdup_n_s32(b); | |
5890 | vqdmull_s32(a, b) | |
5891 | } | |
5892 | ||
5893 | /// Vector saturating doubling long multiply by scalar | |
5894 | #[inline] | |
5895 | #[target_feature(enable = "neon")] | |
5896 | #[cfg_attr(test, assert_instr(sqdmull, N = 4))] | |
5897 | #[rustc_legacy_const_generics(2)] | |
5898 | pub unsafe fn vqdmull_laneq_s16<const N: i32>(a: int16x4_t, b: int16x8_t) -> int32x4_t { | |
5899 | static_assert_imm3!(N); | |
5900 | let b: int16x4_t = simd_shuffle4!(b, b, <const N: i32> [N as u32, N as u32, N as u32, N as u32]); | |
5901 | vqdmull_s16(a, b) | |
5902 | } | |
5903 | ||
5904 | /// Vector saturating doubling long multiply by scalar | |
5905 | #[inline] | |
5906 | #[target_feature(enable = "neon")] | |
5907 | #[cfg_attr(test, assert_instr(sqdmull, N = 2))] | |
5908 | #[rustc_legacy_const_generics(2)] | |
5909 | pub unsafe fn vqdmull_laneq_s32<const N: i32>(a: int32x2_t, b: int32x4_t) -> int64x2_t { | |
5910 | static_assert_imm2!(N); | |
5911 | let b: int32x2_t = simd_shuffle2!(b, b, <const N: i32> [N as u32, N as u32]); | |
5912 | vqdmull_s32(a, b) | |
5913 | } | |
5914 | ||
5915 | /// Signed saturating doubling multiply long | |
5916 | #[inline] | |
5917 | #[target_feature(enable = "neon")] | |
5918 | #[cfg_attr(test, assert_instr(sqdmull, N = 2))] | |
5919 | #[rustc_legacy_const_generics(2)] | |
5920 | pub unsafe fn vqdmullh_lane_s16<const N: i32>(a: i16, b: int16x4_t) -> i32 { | |
5921 | static_assert_imm2!(N); | |
5922 | let b: i16 = simd_extract(b, N as u32); | |
5923 | vqdmullh_s16(a, b) | |
5924 | } | |
5925 | ||
5926 | /// Signed saturating doubling multiply long | |
5927 | #[inline] | |
5928 | #[target_feature(enable = "neon")] | |
5929 | #[cfg_attr(test, assert_instr(sqdmull, N = 4))] | |
5930 | #[rustc_legacy_const_generics(2)] | |
5931 | pub unsafe fn vqdmullh_laneq_s16<const N: i32>(a: i16, b: int16x8_t) -> i32 { | |
5932 | static_assert_imm3!(N); | |
5933 | let b: i16 = simd_extract(b, N as u32); | |
5934 | vqdmullh_s16(a, b) | |
5935 | } | |
5936 | ||
5937 | /// Signed saturating doubling multiply long | |
5938 | #[inline] | |
5939 | #[target_feature(enable = "neon")] | |
5940 | #[cfg_attr(test, assert_instr(sqdmull, N = 1))] | |
5941 | #[rustc_legacy_const_generics(2)] | |
5942 | pub unsafe fn vqdmulls_lane_s32<const N: i32>(a: i32, b: int32x2_t) -> i64 { | |
5943 | static_assert_imm1!(N); | |
5944 | let b: i32 = simd_extract(b, N as u32); | |
5945 | vqdmulls_s32(a, b) | |
5946 | } | |
5947 | ||
5948 | /// Signed saturating doubling multiply long | |
5949 | #[inline] | |
5950 | #[target_feature(enable = "neon")] | |
5951 | #[cfg_attr(test, assert_instr(sqdmull, N = 2))] | |
5952 | #[rustc_legacy_const_generics(2)] | |
5953 | pub unsafe fn vqdmulls_laneq_s32<const N: i32>(a: i32, b: int32x4_t) -> i64 { | |
5954 | static_assert_imm2!(N); | |
5955 | let b: i32 = simd_extract(b, N as u32); | |
5956 | vqdmulls_s32(a, b) | |
5957 | } | |
5958 | ||
5959 | /// Signed saturating doubling multiply long | |
5960 | #[inline] | |
5961 | #[target_feature(enable = "neon")] | |
5962 | #[cfg_attr(test, assert_instr(sqdmull2, N = 2))] | |
5963 | #[rustc_legacy_const_generics(2)] | |
5964 | pub unsafe fn vqdmull_high_lane_s16<const N: i32>(a: int16x8_t, b: int16x4_t) -> int32x4_t { | |
5965 | static_assert_imm2!(N); | |
5966 | let a: int16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
5967 | let b: int16x4_t = simd_shuffle4!(b, b, <const N: i32> [N as u32, N as u32, N as u32, N as u32]); | |
5968 | vqdmull_s16(a, b) | |
5969 | } | |
5970 | ||
5971 | /// Signed saturating doubling multiply long | |
5972 | #[inline] | |
5973 | #[target_feature(enable = "neon")] | |
5974 | #[cfg_attr(test, assert_instr(sqdmull2, N = 1))] | |
5975 | #[rustc_legacy_const_generics(2)] | |
5976 | pub unsafe fn vqdmull_high_lane_s32<const N: i32>(a: int32x4_t, b: int32x2_t) -> int64x2_t { | |
5977 | static_assert_imm1!(N); | |
5978 | let a: int32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
5979 | let b: int32x2_t = simd_shuffle2!(b, b, <const N: i32> [N as u32, N as u32]); | |
5980 | vqdmull_s32(a, b) | |
5981 | } | |
5982 | ||
5983 | /// Signed saturating doubling multiply long | |
5984 | #[inline] | |
5985 | #[target_feature(enable = "neon")] | |
5986 | #[cfg_attr(test, assert_instr(sqdmull2, N = 4))] | |
5987 | #[rustc_legacy_const_generics(2)] | |
5988 | pub unsafe fn vqdmull_high_laneq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int32x4_t { | |
5989 | static_assert_imm3!(N); | |
5990 | let a: int16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
5991 | let b: int16x4_t = simd_shuffle4!(b, b, <const N: i32> [N as u32, N as u32, N as u32, N as u32]); | |
5992 | vqdmull_s16(a, b) | |
5993 | } | |
5994 | ||
5995 | /// Signed saturating doubling multiply long | |
5996 | #[inline] | |
5997 | #[target_feature(enable = "neon")] | |
5998 | #[cfg_attr(test, assert_instr(sqdmull2, N = 2))] | |
5999 | #[rustc_legacy_const_generics(2)] | |
6000 | pub unsafe fn vqdmull_high_laneq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int64x2_t { | |
6001 | static_assert_imm2!(N); | |
6002 | let a: int32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
6003 | let b: int32x2_t = simd_shuffle2!(b, b, <const N: i32> [N as u32, N as u32]); | |
6004 | vqdmull_s32(a, b) | |
6005 | } | |
6006 | ||
6007 | /// Signed saturating doubling multiply-add long | |
6008 | #[inline] | |
6009 | #[target_feature(enable = "neon")] | |
6010 | #[cfg_attr(test, assert_instr(sqdmlal2))] | |
6011 | pub unsafe fn vqdmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { | |
6012 | vqaddq_s32(a, vqdmull_high_s16(b, c)) | |
6013 | } | |
6014 | ||
6015 | /// Signed saturating doubling multiply-add long | |
6016 | #[inline] | |
6017 | #[target_feature(enable = "neon")] | |
6018 | #[cfg_attr(test, assert_instr(sqdmlal2))] | |
6019 | pub unsafe fn vqdmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { | |
6020 | vqaddq_s64(a, vqdmull_high_s32(b, c)) | |
6021 | } | |
6022 | ||
6023 | /// Signed saturating doubling multiply-add long | |
6024 | #[inline] | |
6025 | #[target_feature(enable = "neon")] | |
6026 | #[cfg_attr(test, assert_instr(sqdmlal2))] | |
6027 | pub unsafe fn vqdmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { | |
6028 | vqaddq_s32(a, vqdmull_high_n_s16(b, c)) | |
6029 | } | |
6030 | ||
6031 | /// Signed saturating doubling multiply-add long | |
6032 | #[inline] | |
6033 | #[target_feature(enable = "neon")] | |
6034 | #[cfg_attr(test, assert_instr(sqdmlal2))] | |
6035 | pub unsafe fn vqdmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { | |
6036 | vqaddq_s64(a, vqdmull_high_n_s32(b, c)) | |
6037 | } | |
6038 | ||
6039 | /// Vector widening saturating doubling multiply accumulate with scalar | |
6040 | #[inline] | |
6041 | #[target_feature(enable = "neon")] | |
6042 | #[cfg_attr(test, assert_instr(sqdmlal, N = 2))] | |
6043 | #[rustc_legacy_const_generics(3)] | |
6044 | pub unsafe fn vqdmlal_laneq_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { | |
6045 | static_assert_imm3!(N); | |
6046 | vqaddq_s32(a, vqdmull_laneq_s16::<N>(b, c)) | |
6047 | } | |
6048 | ||
6049 | /// Vector widening saturating doubling multiply accumulate with scalar | |
6050 | #[inline] | |
6051 | #[target_feature(enable = "neon")] | |
6052 | #[cfg_attr(test, assert_instr(sqdmlal, N = 1))] | |
6053 | #[rustc_legacy_const_generics(3)] | |
6054 | pub unsafe fn vqdmlal_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { | |
6055 | static_assert_imm2!(N); | |
6056 | vqaddq_s64(a, vqdmull_laneq_s32::<N>(b, c)) | |
6057 | } | |
6058 | ||
6059 | /// Signed saturating doubling multiply-add long | |
6060 | #[inline] | |
6061 | #[target_feature(enable = "neon")] | |
6062 | #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] | |
6063 | #[rustc_legacy_const_generics(3)] | |
6064 | pub unsafe fn vqdmlal_high_lane_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { | |
6065 | static_assert_imm2!(N); | |
6066 | vqaddq_s32(a, vqdmull_high_lane_s16::<N>(b, c)) | |
6067 | } | |
6068 | ||
6069 | /// Signed saturating doubling multiply-add long | |
6070 | #[inline] | |
6071 | #[target_feature(enable = "neon")] | |
6072 | #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] | |
6073 | #[rustc_legacy_const_generics(3)] | |
6074 | pub unsafe fn vqdmlal_high_laneq_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { | |
6075 | static_assert_imm3!(N); | |
6076 | vqaddq_s32(a, vqdmull_high_laneq_s16::<N>(b, c)) | |
6077 | } | |
6078 | ||
6079 | /// Signed saturating doubling multiply-add long | |
6080 | #[inline] | |
6081 | #[target_feature(enable = "neon")] | |
6082 | #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] | |
6083 | #[rustc_legacy_const_generics(3)] | |
6084 | pub unsafe fn vqdmlal_high_lane_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { | |
6085 | static_assert_imm1!(N); | |
6086 | vqaddq_s64(a, vqdmull_high_lane_s32::<N>(b, c)) | |
6087 | } | |
6088 | ||
6089 | /// Signed saturating doubling multiply-add long | |
6090 | #[inline] | |
6091 | #[target_feature(enable = "neon")] | |
6092 | #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] | |
6093 | #[rustc_legacy_const_generics(3)] | |
6094 | pub unsafe fn vqdmlal_high_laneq_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { | |
6095 | static_assert_imm2!(N); | |
6096 | vqaddq_s64(a, vqdmull_high_laneq_s32::<N>(b, c)) | |
6097 | } | |
6098 | ||
6099 | /// Signed saturating doubling multiply-subtract long | |
6100 | #[inline] | |
6101 | #[target_feature(enable = "neon")] | |
6102 | #[cfg_attr(test, assert_instr(sqdmlsl2))] | |
6103 | pub unsafe fn vqdmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { | |
6104 | vqsubq_s32(a, vqdmull_high_s16(b, c)) | |
6105 | } | |
6106 | ||
6107 | /// Signed saturating doubling multiply-subtract long | |
6108 | #[inline] | |
6109 | #[target_feature(enable = "neon")] | |
6110 | #[cfg_attr(test, assert_instr(sqdmlsl2))] | |
6111 | pub unsafe fn vqdmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { | |
6112 | vqsubq_s64(a, vqdmull_high_s32(b, c)) | |
6113 | } | |
6114 | ||
6115 | /// Signed saturating doubling multiply-subtract long | |
6116 | #[inline] | |
6117 | #[target_feature(enable = "neon")] | |
6118 | #[cfg_attr(test, assert_instr(sqdmlsl2))] | |
6119 | pub unsafe fn vqdmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { | |
6120 | vqsubq_s32(a, vqdmull_high_n_s16(b, c)) | |
6121 | } | |
6122 | ||
6123 | /// Signed saturating doubling multiply-subtract long | |
6124 | #[inline] | |
6125 | #[target_feature(enable = "neon")] | |
6126 | #[cfg_attr(test, assert_instr(sqdmlsl2))] | |
6127 | pub unsafe fn vqdmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { | |
6128 | vqsubq_s64(a, vqdmull_high_n_s32(b, c)) | |
6129 | } | |
6130 | ||
6131 | /// Vector widening saturating doubling multiply subtract with scalar | |
6132 | #[inline] | |
6133 | #[target_feature(enable = "neon")] | |
6134 | #[cfg_attr(test, assert_instr(sqdmlsl, N = 2))] | |
6135 | #[rustc_legacy_const_generics(3)] | |
6136 | pub unsafe fn vqdmlsl_laneq_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { | |
6137 | static_assert_imm3!(N); | |
6138 | vqsubq_s32(a, vqdmull_laneq_s16::<N>(b, c)) | |
6139 | } | |
6140 | ||
6141 | /// Vector widening saturating doubling multiply subtract with scalar | |
6142 | #[inline] | |
6143 | #[target_feature(enable = "neon")] | |
6144 | #[cfg_attr(test, assert_instr(sqdmlsl, N = 1))] | |
6145 | #[rustc_legacy_const_generics(3)] | |
6146 | pub unsafe fn vqdmlsl_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { | |
6147 | static_assert_imm2!(N); | |
6148 | vqsubq_s64(a, vqdmull_laneq_s32::<N>(b, c)) | |
6149 | } | |
6150 | ||
6151 | /// Signed saturating doubling multiply-subtract long | |
6152 | #[inline] | |
6153 | #[target_feature(enable = "neon")] | |
6154 | #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] | |
6155 | #[rustc_legacy_const_generics(3)] | |
6156 | pub unsafe fn vqdmlsl_high_lane_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { | |
6157 | static_assert_imm2!(N); | |
6158 | vqsubq_s32(a, vqdmull_high_lane_s16::<N>(b, c)) | |
6159 | } | |
6160 | ||
6161 | /// Signed saturating doubling multiply-subtract long | |
6162 | #[inline] | |
6163 | #[target_feature(enable = "neon")] | |
6164 | #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] | |
6165 | #[rustc_legacy_const_generics(3)] | |
6166 | pub unsafe fn vqdmlsl_high_laneq_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { | |
6167 | static_assert_imm3!(N); | |
6168 | vqsubq_s32(a, vqdmull_high_laneq_s16::<N>(b, c)) | |
6169 | } | |
6170 | ||
6171 | /// Signed saturating doubling multiply-subtract long | |
6172 | #[inline] | |
6173 | #[target_feature(enable = "neon")] | |
6174 | #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] | |
6175 | #[rustc_legacy_const_generics(3)] | |
6176 | pub unsafe fn vqdmlsl_high_lane_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { | |
6177 | static_assert_imm1!(N); | |
6178 | vqsubq_s64(a, vqdmull_high_lane_s32::<N>(b, c)) | |
6179 | } | |
6180 | ||
6181 | /// Signed saturating doubling multiply-subtract long | |
6182 | #[inline] | |
6183 | #[target_feature(enable = "neon")] | |
6184 | #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] | |
6185 | #[rustc_legacy_const_generics(3)] | |
6186 | pub unsafe fn vqdmlsl_high_laneq_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { | |
6187 | static_assert_imm2!(N); | |
6188 | vqsubq_s64(a, vqdmull_high_laneq_s32::<N>(b, c)) | |
6189 | } | |
6190 | ||
6191 | /// Signed saturating doubling multiply returning high half | |
6192 | #[inline] | |
6193 | #[target_feature(enable = "neon")] | |
6194 | #[cfg_attr(test, assert_instr(sqdmulh))] | |
6195 | pub unsafe fn vqdmulhh_s16(a: i16, b: i16) -> i16 { | |
6196 | let a: int16x4_t = vdup_n_s16(a); | |
6197 | let b: int16x4_t = vdup_n_s16(b); | |
6198 | simd_extract(vqdmulh_s16(a, b), 0) | |
6199 | } | |
6200 | ||
6201 | /// Signed saturating doubling multiply returning high half | |
6202 | #[inline] | |
6203 | #[target_feature(enable = "neon")] | |
6204 | #[cfg_attr(test, assert_instr(sqdmulh))] | |
6205 | pub unsafe fn vqdmulhs_s32(a: i32, b: i32) -> i32 { | |
6206 | let a: int32x2_t = vdup_n_s32(a); | |
6207 | let b: int32x2_t = vdup_n_s32(b); | |
6208 | simd_extract(vqdmulh_s32(a, b), 0) | |
6209 | } | |
6210 | ||
6211 | /// Signed saturating doubling multiply returning high half | |
6212 | #[inline] | |
6213 | #[target_feature(enable = "neon")] | |
6214 | #[cfg_attr(test, assert_instr(sqdmulh, N = 2))] | |
6215 | #[rustc_legacy_const_generics(2)] | |
6216 | pub unsafe fn vqdmulhh_lane_s16<const N: i32>(a: i16, b: int16x4_t) -> i16 { | |
6217 | static_assert_imm2!(N); | |
6218 | let b: i16 = simd_extract(b, N as u32); | |
6219 | vqdmulhh_s16(a, b) | |
6220 | } | |
6221 | ||
6222 | /// Signed saturating doubling multiply returning high half | |
6223 | #[inline] | |
6224 | #[target_feature(enable = "neon")] | |
6225 | #[cfg_attr(test, assert_instr(sqdmulh, N = 2))] | |
6226 | #[rustc_legacy_const_generics(2)] | |
6227 | pub unsafe fn vqdmulhh_laneq_s16<const N: i32>(a: i16, b: int16x8_t) -> i16 { | |
6228 | static_assert_imm3!(N); | |
6229 | let b: i16 = simd_extract(b, N as u32); | |
6230 | vqdmulhh_s16(a, b) | |
6231 | } | |
6232 | ||
6233 | /// Signed saturating doubling multiply returning high half | |
6234 | #[inline] | |
6235 | #[target_feature(enable = "neon")] | |
6236 | #[cfg_attr(test, assert_instr(sqdmulh, N = 1))] | |
6237 | #[rustc_legacy_const_generics(2)] | |
6238 | pub unsafe fn vqdmulhs_lane_s32<const N: i32>(a: i32, b: int32x2_t) -> i32 { | |
6239 | static_assert_imm1!(N); | |
6240 | let b: i32 = simd_extract(b, N as u32); | |
6241 | vqdmulhs_s32(a, b) | |
6242 | } | |
6243 | ||
6244 | /// Signed saturating doubling multiply returning high half | |
6245 | #[inline] | |
6246 | #[target_feature(enable = "neon")] | |
6247 | #[cfg_attr(test, assert_instr(sqdmulh, N = 1))] | |
6248 | #[rustc_legacy_const_generics(2)] | |
6249 | pub unsafe fn vqdmulhs_laneq_s32<const N: i32>(a: i32, b: int32x4_t) -> i32 { | |
6250 | static_assert_imm2!(N); | |
6251 | let b: i32 = simd_extract(b, N as u32); | |
6252 | vqdmulhs_s32(a, b) | |
6253 | } | |
6254 | ||
6255 | /// Saturating extract narrow | |
6256 | #[inline] | |
6257 | #[target_feature(enable = "neon")] | |
6258 | #[cfg_attr(test, assert_instr(sqxtn))] | |
6259 | pub unsafe fn vqmovnh_s16(a: i16) -> i8 { | |
6260 | simd_extract(vqmovn_s16(vdupq_n_s16(a)), 0) | |
6261 | } | |
6262 | ||
6263 | /// Saturating extract narrow | |
6264 | #[inline] | |
6265 | #[target_feature(enable = "neon")] | |
6266 | #[cfg_attr(test, assert_instr(sqxtn))] | |
6267 | pub unsafe fn vqmovns_s32(a: i32) -> i16 { | |
6268 | simd_extract(vqmovn_s32(vdupq_n_s32(a)), 0) | |
6269 | } | |
6270 | ||
6271 | /// Saturating extract narrow | |
6272 | #[inline] | |
6273 | #[target_feature(enable = "neon")] | |
6274 | #[cfg_attr(test, assert_instr(uqxtn))] | |
6275 | pub unsafe fn vqmovnh_u16(a: u16) -> u8 { | |
6276 | simd_extract(vqmovn_u16(vdupq_n_u16(a)), 0) | |
6277 | } | |
6278 | ||
6279 | /// Saturating extract narrow | |
6280 | #[inline] | |
6281 | #[target_feature(enable = "neon")] | |
6282 | #[cfg_attr(test, assert_instr(uqxtn))] | |
6283 | pub unsafe fn vqmovns_u32(a: u32) -> u16 { | |
6284 | simd_extract(vqmovn_u32(vdupq_n_u32(a)), 0) | |
6285 | } | |
6286 | ||
6287 | /// Saturating extract narrow | |
6288 | #[inline] | |
6289 | #[target_feature(enable = "neon")] | |
6290 | #[cfg_attr(test, assert_instr(sqxtn))] | |
6291 | pub unsafe fn vqmovnd_s64(a: i64) -> i32 { | |
6292 | #[allow(improper_ctypes)] | |
6293 | extern "C" { | |
6294 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.scalar.sqxtn.i32.i64")] | |
6295 | fn vqmovnd_s64_(a: i64) -> i32; | |
6296 | } | |
6297 | vqmovnd_s64_(a) | |
6298 | } | |
6299 | ||
6300 | /// Saturating extract narrow | |
6301 | #[inline] | |
6302 | #[target_feature(enable = "neon")] | |
6303 | #[cfg_attr(test, assert_instr(uqxtn))] | |
6304 | pub unsafe fn vqmovnd_u64(a: u64) -> u32 { | |
6305 | #[allow(improper_ctypes)] | |
6306 | extern "C" { | |
6307 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.scalar.uqxtn.i32.i64")] | |
6308 | fn vqmovnd_u64_(a: u64) -> u32; | |
6309 | } | |
6310 | vqmovnd_u64_(a) | |
6311 | } | |
6312 | ||
6313 | /// Signed saturating extract narrow | |
6314 | #[inline] | |
6315 | #[target_feature(enable = "neon")] | |
6316 | #[cfg_attr(test, assert_instr(sqxtn2))] | |
6317 | pub unsafe fn vqmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { | |
6318 | simd_shuffle16!(a, vqmovn_s16(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
6319 | } | |
6320 | ||
6321 | /// Signed saturating extract narrow | |
6322 | #[inline] | |
6323 | #[target_feature(enable = "neon")] | |
6324 | #[cfg_attr(test, assert_instr(sqxtn2))] | |
6325 | pub unsafe fn vqmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { | |
6326 | simd_shuffle8!(a, vqmovn_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
6327 | } | |
6328 | ||
6329 | /// Signed saturating extract narrow | |
6330 | #[inline] | |
6331 | #[target_feature(enable = "neon")] | |
6332 | #[cfg_attr(test, assert_instr(sqxtn2))] | |
6333 | pub unsafe fn vqmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { | |
6334 | simd_shuffle4!(a, vqmovn_s64(b), [0, 1, 2, 3]) | |
6335 | } | |
6336 | ||
6337 | /// Signed saturating extract narrow | |
6338 | #[inline] | |
6339 | #[target_feature(enable = "neon")] | |
6340 | #[cfg_attr(test, assert_instr(uqxtn2))] | |
6341 | pub unsafe fn vqmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { | |
6342 | simd_shuffle16!(a, vqmovn_u16(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
6343 | } | |
6344 | ||
6345 | /// Signed saturating extract narrow | |
6346 | #[inline] | |
6347 | #[target_feature(enable = "neon")] | |
6348 | #[cfg_attr(test, assert_instr(uqxtn2))] | |
6349 | pub unsafe fn vqmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { | |
6350 | simd_shuffle8!(a, vqmovn_u32(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
6351 | } | |
6352 | ||
6353 | /// Signed saturating extract narrow | |
6354 | #[inline] | |
6355 | #[target_feature(enable = "neon")] | |
6356 | #[cfg_attr(test, assert_instr(uqxtn2))] | |
6357 | pub unsafe fn vqmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { | |
6358 | simd_shuffle4!(a, vqmovn_u64(b), [0, 1, 2, 3]) | |
6359 | } | |
6360 | ||
6361 | /// Signed saturating extract unsigned narrow | |
6362 | #[inline] | |
6363 | #[target_feature(enable = "neon")] | |
6364 | #[cfg_attr(test, assert_instr(sqxtun))] | |
6365 | pub unsafe fn vqmovunh_s16(a: i16) -> u8 { | |
6366 | simd_extract(vqmovun_s16(vdupq_n_s16(a)), 0) | |
6367 | } | |
6368 | ||
6369 | /// Signed saturating extract unsigned narrow | |
6370 | #[inline] | |
6371 | #[target_feature(enable = "neon")] | |
6372 | #[cfg_attr(test, assert_instr(sqxtun))] | |
6373 | pub unsafe fn vqmovuns_s32(a: i32) -> u16 { | |
6374 | simd_extract(vqmovun_s32(vdupq_n_s32(a)), 0) | |
6375 | } | |
6376 | ||
6377 | /// Signed saturating extract unsigned narrow | |
6378 | #[inline] | |
6379 | #[target_feature(enable = "neon")] | |
6380 | #[cfg_attr(test, assert_instr(sqxtun))] | |
6381 | pub unsafe fn vqmovund_s64(a: i64) -> u32 { | |
6382 | simd_extract(vqmovun_s64(vdupq_n_s64(a)), 0) | |
6383 | } | |
6384 | ||
6385 | /// Signed saturating extract unsigned narrow | |
6386 | #[inline] | |
6387 | #[target_feature(enable = "neon")] | |
6388 | #[cfg_attr(test, assert_instr(sqxtun2))] | |
6389 | pub unsafe fn vqmovun_high_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { | |
6390 | simd_shuffle16!(a, vqmovun_s16(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
6391 | } | |
6392 | ||
6393 | /// Signed saturating extract unsigned narrow | |
6394 | #[inline] | |
6395 | #[target_feature(enable = "neon")] | |
6396 | #[cfg_attr(test, assert_instr(sqxtun2))] | |
6397 | pub unsafe fn vqmovun_high_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { | |
6398 | simd_shuffle8!(a, vqmovun_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
6399 | } | |
6400 | ||
6401 | /// Signed saturating extract unsigned narrow | |
6402 | #[inline] | |
6403 | #[target_feature(enable = "neon")] | |
6404 | #[cfg_attr(test, assert_instr(sqxtun2))] | |
6405 | pub unsafe fn vqmovun_high_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { | |
6406 | simd_shuffle4!(a, vqmovun_s64(b), [0, 1, 2, 3]) | |
6407 | } | |
6408 | ||
6409 | /// Signed saturating rounding doubling multiply returning high half | |
6410 | #[inline] | |
6411 | #[target_feature(enable = "neon")] | |
6412 | #[cfg_attr(test, assert_instr(sqrdmulh))] | |
6413 | pub unsafe fn vqrdmulhh_s16(a: i16, b: i16) -> i16 { | |
6414 | simd_extract(vqrdmulh_s16(vdup_n_s16(a), vdup_n_s16(b)), 0) | |
6415 | } | |
6416 | ||
6417 | /// Signed saturating rounding doubling multiply returning high half | |
6418 | #[inline] | |
6419 | #[target_feature(enable = "neon")] | |
6420 | #[cfg_attr(test, assert_instr(sqrdmulh))] | |
6421 | pub unsafe fn vqrdmulhs_s32(a: i32, b: i32) -> i32 { | |
6422 | simd_extract(vqrdmulh_s32(vdup_n_s32(a), vdup_n_s32(b)), 0) | |
6423 | } | |
6424 | ||
6425 | /// Signed saturating rounding doubling multiply returning high half | |
6426 | #[inline] | |
6427 | #[target_feature(enable = "neon")] | |
6428 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6429 | #[rustc_legacy_const_generics(2)] | |
6430 | pub unsafe fn vqrdmulhh_lane_s16<const LANE: i32>(a: i16, b: int16x4_t) -> i16 { | |
6431 | static_assert_imm2!(LANE); | |
6432 | vqrdmulhh_s16(a, simd_extract(b, LANE as u32)) | |
6433 | } | |
6434 | ||
6435 | /// Signed saturating rounding doubling multiply returning high half | |
6436 | #[inline] | |
6437 | #[target_feature(enable = "neon")] | |
6438 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6439 | #[rustc_legacy_const_generics(2)] | |
6440 | pub unsafe fn vqrdmulhh_laneq_s16<const LANE: i32>(a: i16, b: int16x8_t) -> i16 { | |
6441 | static_assert_imm3!(LANE); | |
6442 | vqrdmulhh_s16(a, simd_extract(b, LANE as u32)) | |
6443 | } | |
6444 | ||
6445 | /// Signed saturating rounding doubling multiply returning high half | |
6446 | #[inline] | |
6447 | #[target_feature(enable = "neon")] | |
6448 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6449 | #[rustc_legacy_const_generics(2)] | |
6450 | pub unsafe fn vqrdmulhs_lane_s32<const LANE: i32>(a: i32, b: int32x2_t) -> i32 { | |
6451 | static_assert_imm1!(LANE); | |
6452 | vqrdmulhs_s32(a, simd_extract(b, LANE as u32)) | |
6453 | } | |
6454 | ||
6455 | /// Signed saturating rounding doubling multiply returning high half | |
6456 | #[inline] | |
6457 | #[target_feature(enable = "neon")] | |
6458 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6459 | #[rustc_legacy_const_generics(2)] | |
6460 | pub unsafe fn vqrdmulhs_laneq_s32<const LANE: i32>(a: i32, b: int32x4_t) -> i32 { | |
6461 | static_assert_imm2!(LANE); | |
6462 | vqrdmulhs_s32(a, simd_extract(b, LANE as u32)) | |
6463 | } | |
6464 | ||
6465 | /// Signed saturating rounding doubling multiply accumulate returning high half | |
6466 | #[inline] | |
6467 | #[target_feature(enable = "neon")] | |
6468 | #[cfg_attr(test, assert_instr(sqrdmulh))] | |
6469 | pub unsafe fn vqrdmlahh_s16(a: i16, b: i16, c: i16) -> i16 { | |
6470 | vqaddh_s16(a, vqrdmulhh_s16(b, c)) | |
6471 | } | |
6472 | ||
6473 | /// Signed saturating rounding doubling multiply accumulate returning high half | |
6474 | #[inline] | |
6475 | #[target_feature(enable = "neon")] | |
6476 | #[cfg_attr(test, assert_instr(sqrdmulh))] | |
6477 | pub unsafe fn vqrdmlahs_s32(a: i32, b: i32, c: i32) -> i32 { | |
6478 | vqadds_s32(a, vqrdmulhs_s32(b, c)) | |
6479 | } | |
6480 | ||
6481 | /// Signed saturating rounding doubling multiply accumulate returning high half | |
6482 | #[inline] | |
6483 | #[target_feature(enable = "neon")] | |
6484 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6485 | #[rustc_legacy_const_generics(3)] | |
6486 | pub unsafe fn vqrdmlahh_lane_s16<const LANE: i32>(a: i16, b: i16, c: int16x4_t) -> i16 { | |
6487 | static_assert_imm2!(LANE); | |
6488 | vqaddh_s16(a, vqrdmulhh_lane_s16::<LANE>(b, c)) | |
6489 | } | |
6490 | ||
6491 | /// Signed saturating rounding doubling multiply accumulate returning high half | |
6492 | #[inline] | |
6493 | #[target_feature(enable = "neon")] | |
6494 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6495 | #[rustc_legacy_const_generics(3)] | |
6496 | pub unsafe fn vqrdmlahh_laneq_s16<const LANE: i32>(a: i16, b: i16, c: int16x8_t) -> i16 { | |
6497 | static_assert_imm3!(LANE); | |
6498 | vqaddh_s16(a, vqrdmulhh_laneq_s16::<LANE>(b, c)) | |
6499 | } | |
6500 | ||
6501 | /// Signed saturating rounding doubling multiply accumulate returning high half | |
6502 | #[inline] | |
6503 | #[target_feature(enable = "neon")] | |
6504 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6505 | #[rustc_legacy_const_generics(3)] | |
6506 | pub unsafe fn vqrdmlahs_lane_s32<const LANE: i32>(a: i32, b: i32, c: int32x2_t) -> i32 { | |
6507 | static_assert_imm1!(LANE); | |
6508 | vqadds_s32(a, vqrdmulhs_lane_s32::<LANE>(b, c)) | |
6509 | } | |
6510 | ||
6511 | /// Signed saturating rounding doubling multiply accumulate returning high half | |
6512 | #[inline] | |
6513 | #[target_feature(enable = "neon")] | |
6514 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6515 | #[rustc_legacy_const_generics(3)] | |
6516 | pub unsafe fn vqrdmlahs_laneq_s32<const LANE: i32>(a: i32, b: i32, c: int32x4_t) -> i32 { | |
6517 | static_assert_imm2!(LANE); | |
6518 | vqadds_s32(a, vqrdmulhs_laneq_s32::<LANE>(b, c)) | |
6519 | } | |
6520 | ||
6521 | /// Signed saturating rounding doubling multiply subtract returning high half | |
6522 | #[inline] | |
6523 | #[target_feature(enable = "neon")] | |
6524 | #[cfg_attr(test, assert_instr(sqrdmulh))] | |
6525 | pub unsafe fn vqrdmlshh_s16(a: i16, b: i16, c: i16) -> i16 { | |
6526 | vqsubh_s16(a, vqrdmulhh_s16(b, c)) | |
6527 | } | |
6528 | ||
6529 | /// Signed saturating rounding doubling multiply subtract returning high half | |
6530 | #[inline] | |
6531 | #[target_feature(enable = "neon")] | |
6532 | #[cfg_attr(test, assert_instr(sqrdmulh))] | |
6533 | pub unsafe fn vqrdmlshs_s32(a: i32, b: i32, c: i32) -> i32 { | |
6534 | vqsubs_s32(a, vqrdmulhs_s32(b, c)) | |
6535 | } | |
6536 | ||
6537 | /// Signed saturating rounding doubling multiply subtract returning high half | |
6538 | #[inline] | |
6539 | #[target_feature(enable = "neon")] | |
6540 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6541 | #[rustc_legacy_const_generics(3)] | |
6542 | pub unsafe fn vqrdmlshh_lane_s16<const LANE: i32>(a: i16, b: i16, c: int16x4_t) -> i16 { | |
6543 | static_assert_imm2!(LANE); | |
6544 | vqsubh_s16(a, vqrdmulhh_lane_s16::<LANE>(b, c)) | |
6545 | } | |
6546 | ||
6547 | /// Signed saturating rounding doubling multiply subtract returning high half | |
6548 | #[inline] | |
6549 | #[target_feature(enable = "neon")] | |
6550 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6551 | #[rustc_legacy_const_generics(3)] | |
6552 | pub unsafe fn vqrdmlshh_laneq_s16<const LANE: i32>(a: i16, b: i16, c: int16x8_t) -> i16 { | |
6553 | static_assert_imm3!(LANE); | |
6554 | vqsubh_s16(a, vqrdmulhh_laneq_s16::<LANE>(b, c)) | |
6555 | } | |
6556 | ||
6557 | /// Signed saturating rounding doubling multiply subtract returning high half | |
6558 | #[inline] | |
6559 | #[target_feature(enable = "neon")] | |
6560 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6561 | #[rustc_legacy_const_generics(3)] | |
6562 | pub unsafe fn vqrdmlshs_lane_s32<const LANE: i32>(a: i32, b: i32, c: int32x2_t) -> i32 { | |
6563 | static_assert_imm1!(LANE); | |
6564 | vqsubs_s32(a, vqrdmulhs_lane_s32::<LANE>(b, c)) | |
6565 | } | |
6566 | ||
6567 | /// Signed saturating rounding doubling multiply subtract returning high half | |
6568 | #[inline] | |
6569 | #[target_feature(enable = "neon")] | |
6570 | #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] | |
6571 | #[rustc_legacy_const_generics(3)] | |
6572 | pub unsafe fn vqrdmlshs_laneq_s32<const LANE: i32>(a: i32, b: i32, c: int32x4_t) -> i32 { | |
6573 | static_assert_imm2!(LANE); | |
6574 | vqsubs_s32(a, vqrdmulhs_laneq_s32::<LANE>(b, c)) | |
6575 | } | |
6576 | ||
6577 | /// Signed saturating rounding shift left | |
6578 | #[inline] | |
6579 | #[target_feature(enable = "neon")] | |
6580 | #[cfg_attr(test, assert_instr(sqrshl))] | |
6581 | pub unsafe fn vqrshls_s32(a: i32, b: i32) -> i32 { | |
6582 | #[allow(improper_ctypes)] | |
6583 | extern "C" { | |
6584 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqrshl.i32")] | |
6585 | fn vqrshls_s32_(a: i32, b: i32) -> i32; | |
6586 | } | |
6587 | vqrshls_s32_(a, b) | |
6588 | } | |
6589 | ||
6590 | /// Signed saturating rounding shift left | |
6591 | #[inline] | |
6592 | #[target_feature(enable = "neon")] | |
6593 | #[cfg_attr(test, assert_instr(sqrshl))] | |
6594 | pub unsafe fn vqrshld_s64(a: i64, b: i64) -> i64 { | |
6595 | #[allow(improper_ctypes)] | |
6596 | extern "C" { | |
6597 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqrshl.i64")] | |
6598 | fn vqrshld_s64_(a: i64, b: i64) -> i64; | |
6599 | } | |
6600 | vqrshld_s64_(a, b) | |
6601 | } | |
6602 | ||
6603 | /// Signed saturating rounding shift left | |
6604 | #[inline] | |
6605 | #[target_feature(enable = "neon")] | |
6606 | #[cfg_attr(test, assert_instr(sqrshl))] | |
6607 | pub unsafe fn vqrshlb_s8(a: i8, b: i8) -> i8 { | |
6608 | let a: int8x8_t = vdup_n_s8(a); | |
6609 | let b: int8x8_t = vdup_n_s8(b); | |
6610 | simd_extract(vqrshl_s8(a, b), 0) | |
6611 | } | |
6612 | ||
6613 | /// Signed saturating rounding shift left | |
6614 | #[inline] | |
6615 | #[target_feature(enable = "neon")] | |
6616 | #[cfg_attr(test, assert_instr(sqrshl))] | |
6617 | pub unsafe fn vqrshlh_s16(a: i16, b: i16) -> i16 { | |
6618 | let a: int16x4_t = vdup_n_s16(a); | |
6619 | let b: int16x4_t = vdup_n_s16(b); | |
6620 | simd_extract(vqrshl_s16(a, b), 0) | |
6621 | } | |
6622 | ||
6623 | /// Unsigned signed saturating rounding shift left | |
6624 | #[inline] | |
6625 | #[target_feature(enable = "neon")] | |
6626 | #[cfg_attr(test, assert_instr(uqrshl))] | |
6627 | pub unsafe fn vqrshls_u32(a: u32, b: i32) -> u32 { | |
6628 | #[allow(improper_ctypes)] | |
6629 | extern "C" { | |
6630 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqrshl.i32")] | |
6631 | fn vqrshls_u32_(a: u32, b: i32) -> u32; | |
6632 | } | |
6633 | vqrshls_u32_(a, b) | |
6634 | } | |
6635 | ||
6636 | /// Unsigned signed saturating rounding shift left | |
6637 | #[inline] | |
6638 | #[target_feature(enable = "neon")] | |
6639 | #[cfg_attr(test, assert_instr(uqrshl))] | |
6640 | pub unsafe fn vqrshld_u64(a: u64, b: i64) -> u64 { | |
6641 | #[allow(improper_ctypes)] | |
6642 | extern "C" { | |
6643 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqrshl.i64")] | |
6644 | fn vqrshld_u64_(a: u64, b: i64) -> u64; | |
6645 | } | |
6646 | vqrshld_u64_(a, b) | |
6647 | } | |
6648 | ||
6649 | /// Unsigned signed saturating rounding shift left | |
6650 | #[inline] | |
6651 | #[target_feature(enable = "neon")] | |
6652 | #[cfg_attr(test, assert_instr(uqrshl))] | |
6653 | pub unsafe fn vqrshlb_u8(a: u8, b: i8) -> u8 { | |
6654 | let a: uint8x8_t = vdup_n_u8(a); | |
6655 | let b: int8x8_t = vdup_n_s8(b); | |
6656 | simd_extract(vqrshl_u8(a, b), 0) | |
6657 | } | |
6658 | ||
6659 | /// Unsigned signed saturating rounding shift left | |
6660 | #[inline] | |
6661 | #[target_feature(enable = "neon")] | |
6662 | #[cfg_attr(test, assert_instr(uqrshl))] | |
6663 | pub unsafe fn vqrshlh_u16(a: u16, b: i16) -> u16 { | |
6664 | let a: uint16x4_t = vdup_n_u16(a); | |
6665 | let b: int16x4_t = vdup_n_s16(b); | |
6666 | simd_extract(vqrshl_u16(a, b), 0) | |
6667 | } | |
6668 | ||
6669 | /// Signed saturating rounded shift right narrow | |
6670 | #[inline] | |
6671 | #[target_feature(enable = "neon")] | |
6672 | #[cfg_attr(test, assert_instr(sqrshrn, N = 2))] | |
6673 | #[rustc_legacy_const_generics(1)] | |
6674 | pub unsafe fn vqrshrnh_n_s16<const N: i32>(a: i16) -> i8 { | |
6675 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
6676 | let a: int16x8_t = vdupq_n_s16(a); | |
6677 | simd_extract(vqrshrn_n_s16::<N>(a), 0) | |
6678 | } | |
6679 | ||
6680 | /// Signed saturating rounded shift right narrow | |
6681 | #[inline] | |
6682 | #[target_feature(enable = "neon")] | |
6683 | #[cfg_attr(test, assert_instr(sqrshrn, N = 2))] | |
6684 | #[rustc_legacy_const_generics(1)] | |
6685 | pub unsafe fn vqrshrns_n_s32<const N: i32>(a: i32) -> i16 { | |
6686 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
6687 | let a: int32x4_t = vdupq_n_s32(a); | |
6688 | simd_extract(vqrshrn_n_s32::<N>(a), 0) | |
6689 | } | |
6690 | ||
6691 | /// Signed saturating rounded shift right narrow | |
6692 | #[inline] | |
6693 | #[target_feature(enable = "neon")] | |
6694 | #[cfg_attr(test, assert_instr(sqrshrn, N = 2))] | |
6695 | #[rustc_legacy_const_generics(1)] | |
6696 | pub unsafe fn vqrshrnd_n_s64<const N: i32>(a: i64) -> i32 { | |
6697 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
6698 | let a: int64x2_t = vdupq_n_s64(a); | |
6699 | simd_extract(vqrshrn_n_s64::<N>(a), 0) | |
6700 | } | |
6701 | ||
6702 | /// Signed saturating rounded shift right narrow | |
6703 | #[inline] | |
6704 | #[target_feature(enable = "neon")] | |
6705 | #[cfg_attr(test, assert_instr(sqrshrn2, N = 2))] | |
6706 | #[rustc_legacy_const_generics(2)] | |
6707 | pub unsafe fn vqrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t { | |
6708 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
6709 | simd_shuffle16!(a, vqrshrn_n_s16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
6710 | } | |
6711 | ||
6712 | /// Signed saturating rounded shift right narrow | |
6713 | #[inline] | |
6714 | #[target_feature(enable = "neon")] | |
6715 | #[cfg_attr(test, assert_instr(sqrshrn2, N = 2))] | |
6716 | #[rustc_legacy_const_generics(2)] | |
6717 | pub unsafe fn vqrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t { | |
6718 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
6719 | simd_shuffle8!(a, vqrshrn_n_s32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
6720 | } | |
6721 | ||
6722 | /// Signed saturating rounded shift right narrow | |
6723 | #[inline] | |
6724 | #[target_feature(enable = "neon")] | |
6725 | #[cfg_attr(test, assert_instr(sqrshrn2, N = 2))] | |
6726 | #[rustc_legacy_const_generics(2)] | |
6727 | pub unsafe fn vqrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t { | |
6728 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
6729 | simd_shuffle4!(a, vqrshrn_n_s64::<N>(b), [0, 1, 2, 3]) | |
6730 | } | |
6731 | ||
6732 | /// Unsigned saturating rounded shift right narrow | |
6733 | #[inline] | |
6734 | #[target_feature(enable = "neon")] | |
6735 | #[cfg_attr(test, assert_instr(uqrshrn, N = 2))] | |
6736 | #[rustc_legacy_const_generics(1)] | |
6737 | pub unsafe fn vqrshrnh_n_u16<const N: i32>(a: u16) -> u8 { | |
6738 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
6739 | let a: uint16x8_t = vdupq_n_u16(a); | |
6740 | simd_extract(vqrshrn_n_u16::<N>(a), 0) | |
6741 | } | |
6742 | ||
6743 | /// Unsigned saturating rounded shift right narrow | |
6744 | #[inline] | |
6745 | #[target_feature(enable = "neon")] | |
6746 | #[cfg_attr(test, assert_instr(uqrshrn, N = 2))] | |
6747 | #[rustc_legacy_const_generics(1)] | |
6748 | pub unsafe fn vqrshrns_n_u32<const N: i32>(a: u32) -> u16 { | |
6749 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
6750 | let a: uint32x4_t = vdupq_n_u32(a); | |
6751 | simd_extract(vqrshrn_n_u32::<N>(a), 0) | |
6752 | } | |
6753 | ||
6754 | /// Unsigned saturating rounded shift right narrow | |
6755 | #[inline] | |
6756 | #[target_feature(enable = "neon")] | |
6757 | #[cfg_attr(test, assert_instr(uqrshrn, N = 2))] | |
6758 | #[rustc_legacy_const_generics(1)] | |
6759 | pub unsafe fn vqrshrnd_n_u64<const N: i32>(a: u64) -> u32 { | |
6760 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
6761 | let a: uint64x2_t = vdupq_n_u64(a); | |
6762 | simd_extract(vqrshrn_n_u64::<N>(a), 0) | |
6763 | } | |
6764 | ||
6765 | /// Unsigned saturating rounded shift right narrow | |
6766 | #[inline] | |
6767 | #[target_feature(enable = "neon")] | |
6768 | #[cfg_attr(test, assert_instr(uqrshrn2, N = 2))] | |
6769 | #[rustc_legacy_const_generics(2)] | |
6770 | pub unsafe fn vqrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { | |
6771 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
6772 | simd_shuffle16!(a, vqrshrn_n_u16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
6773 | } | |
6774 | ||
6775 | /// Unsigned saturating rounded shift right narrow | |
6776 | #[inline] | |
6777 | #[target_feature(enable = "neon")] | |
6778 | #[cfg_attr(test, assert_instr(uqrshrn2, N = 2))] | |
6779 | #[rustc_legacy_const_generics(2)] | |
6780 | pub unsafe fn vqrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { | |
6781 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
6782 | simd_shuffle8!(a, vqrshrn_n_u32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
6783 | } | |
6784 | ||
6785 | /// Unsigned saturating rounded shift right narrow | |
6786 | #[inline] | |
6787 | #[target_feature(enable = "neon")] | |
6788 | #[cfg_attr(test, assert_instr(uqrshrn2, N = 2))] | |
6789 | #[rustc_legacy_const_generics(2)] | |
6790 | pub unsafe fn vqrshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { | |
6791 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
6792 | simd_shuffle4!(a, vqrshrn_n_u64::<N>(b), [0, 1, 2, 3]) | |
6793 | } | |
6794 | ||
6795 | /// Signed saturating rounded shift right unsigned narrow | |
6796 | #[inline] | |
6797 | #[target_feature(enable = "neon")] | |
6798 | #[cfg_attr(test, assert_instr(sqrshrun, N = 2))] | |
6799 | #[rustc_legacy_const_generics(1)] | |
6800 | pub unsafe fn vqrshrunh_n_s16<const N: i32>(a: i16) -> u8 { | |
6801 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
6802 | let a: int16x8_t = vdupq_n_s16(a); | |
6803 | simd_extract(vqrshrun_n_s16::<N>(a), 0) | |
6804 | } | |
6805 | ||
6806 | /// Signed saturating rounded shift right unsigned narrow | |
6807 | #[inline] | |
6808 | #[target_feature(enable = "neon")] | |
6809 | #[cfg_attr(test, assert_instr(sqrshrun, N = 2))] | |
6810 | #[rustc_legacy_const_generics(1)] | |
6811 | pub unsafe fn vqrshruns_n_s32<const N: i32>(a: i32) -> u16 { | |
6812 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
6813 | let a: int32x4_t = vdupq_n_s32(a); | |
6814 | simd_extract(vqrshrun_n_s32::<N>(a), 0) | |
6815 | } | |
6816 | ||
6817 | /// Signed saturating rounded shift right unsigned narrow | |
6818 | #[inline] | |
6819 | #[target_feature(enable = "neon")] | |
6820 | #[cfg_attr(test, assert_instr(sqrshrun, N = 2))] | |
6821 | #[rustc_legacy_const_generics(1)] | |
6822 | pub unsafe fn vqrshrund_n_s64<const N: i32>(a: i64) -> u32 { | |
6823 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
6824 | let a: int64x2_t = vdupq_n_s64(a); | |
6825 | simd_extract(vqrshrun_n_s64::<N>(a), 0) | |
6826 | } | |
6827 | ||
6828 | /// Signed saturating rounded shift right unsigned narrow | |
6829 | #[inline] | |
6830 | #[target_feature(enable = "neon")] | |
6831 | #[cfg_attr(test, assert_instr(sqrshrun2, N = 2))] | |
6832 | #[rustc_legacy_const_generics(2)] | |
6833 | pub unsafe fn vqrshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { | |
6834 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
6835 | simd_shuffle16!(a, vqrshrun_n_s16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
6836 | } | |
6837 | ||
6838 | /// Signed saturating rounded shift right unsigned narrow | |
6839 | #[inline] | |
6840 | #[target_feature(enable = "neon")] | |
6841 | #[cfg_attr(test, assert_instr(sqrshrun2, N = 2))] | |
6842 | #[rustc_legacy_const_generics(2)] | |
6843 | pub unsafe fn vqrshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { | |
6844 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
6845 | simd_shuffle8!(a, vqrshrun_n_s32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
6846 | } | |
6847 | ||
6848 | /// Signed saturating rounded shift right unsigned narrow | |
6849 | #[inline] | |
6850 | #[target_feature(enable = "neon")] | |
6851 | #[cfg_attr(test, assert_instr(sqrshrun2, N = 2))] | |
6852 | #[rustc_legacy_const_generics(2)] | |
6853 | pub unsafe fn vqrshrun_high_n_s64<const N: i32>(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { | |
6854 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
6855 | simd_shuffle4!(a, vqrshrun_n_s64::<N>(b), [0, 1, 2, 3]) | |
6856 | } | |
6857 | ||
6858 | /// Signed saturating shift left | |
6859 | #[inline] | |
6860 | #[target_feature(enable = "neon")] | |
6861 | #[cfg_attr(test, assert_instr(sqshl))] | |
6862 | pub unsafe fn vqshld_s64(a: i64, b: i64) -> i64 { | |
6863 | #[allow(improper_ctypes)] | |
6864 | extern "C" { | |
6865 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqshl.i64")] | |
6866 | fn vqshld_s64_(a: i64, b: i64) -> i64; | |
6867 | } | |
6868 | vqshld_s64_(a, b) | |
6869 | } | |
6870 | ||
6871 | /// Signed saturating shift left | |
6872 | #[inline] | |
6873 | #[target_feature(enable = "neon")] | |
6874 | #[cfg_attr(test, assert_instr(sqshl))] | |
6875 | pub unsafe fn vqshlb_s8(a: i8, b: i8) -> i8 { | |
6876 | let c: int8x8_t = vqshl_s8(vdup_n_s8(a), vdup_n_s8(b)); | |
6877 | simd_extract(c, 0) | |
6878 | } | |
6879 | ||
6880 | /// Signed saturating shift left | |
6881 | #[inline] | |
6882 | #[target_feature(enable = "neon")] | |
6883 | #[cfg_attr(test, assert_instr(sqshl))] | |
6884 | pub unsafe fn vqshlh_s16(a: i16, b: i16) -> i16 { | |
6885 | let c: int16x4_t = vqshl_s16(vdup_n_s16(a), vdup_n_s16(b)); | |
6886 | simd_extract(c, 0) | |
6887 | } | |
6888 | ||
6889 | /// Signed saturating shift left | |
6890 | #[inline] | |
6891 | #[target_feature(enable = "neon")] | |
6892 | #[cfg_attr(test, assert_instr(sqshl))] | |
6893 | pub unsafe fn vqshls_s32(a: i32, b: i32) -> i32 { | |
6894 | let c: int32x2_t = vqshl_s32(vdup_n_s32(a), vdup_n_s32(b)); | |
6895 | simd_extract(c, 0) | |
6896 | } | |
6897 | ||
6898 | /// Unsigned saturating shift left | |
6899 | #[inline] | |
6900 | #[target_feature(enable = "neon")] | |
6901 | #[cfg_attr(test, assert_instr(uqshl))] | |
6902 | pub unsafe fn vqshld_u64(a: u64, b: i64) -> u64 { | |
6903 | #[allow(improper_ctypes)] | |
6904 | extern "C" { | |
6905 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqshl.i64")] | |
6906 | fn vqshld_u64_(a: u64, b: i64) -> u64; | |
6907 | } | |
6908 | vqshld_u64_(a, b) | |
6909 | } | |
6910 | ||
6911 | /// Unsigned saturating shift left | |
6912 | #[inline] | |
6913 | #[target_feature(enable = "neon")] | |
6914 | #[cfg_attr(test, assert_instr(uqshl))] | |
6915 | pub unsafe fn vqshlb_u8(a: u8, b: i8) -> u8 { | |
6916 | let c: uint8x8_t = vqshl_u8(vdup_n_u8(a), vdup_n_s8(b)); | |
6917 | simd_extract(c, 0) | |
6918 | } | |
6919 | ||
6920 | /// Unsigned saturating shift left | |
6921 | #[inline] | |
6922 | #[target_feature(enable = "neon")] | |
6923 | #[cfg_attr(test, assert_instr(uqshl))] | |
6924 | pub unsafe fn vqshlh_u16(a: u16, b: i16) -> u16 { | |
6925 | let c: uint16x4_t = vqshl_u16(vdup_n_u16(a), vdup_n_s16(b)); | |
6926 | simd_extract(c, 0) | |
6927 | } | |
6928 | ||
6929 | /// Unsigned saturating shift left | |
6930 | #[inline] | |
6931 | #[target_feature(enable = "neon")] | |
6932 | #[cfg_attr(test, assert_instr(uqshl))] | |
6933 | pub unsafe fn vqshls_u32(a: u32, b: i32) -> u32 { | |
6934 | let c: uint32x2_t = vqshl_u32(vdup_n_u32(a), vdup_n_s32(b)); | |
6935 | simd_extract(c, 0) | |
6936 | } | |
6937 | ||
6938 | /// Signed saturating shift left | |
6939 | #[inline] | |
6940 | #[target_feature(enable = "neon")] | |
6941 | #[cfg_attr(test, assert_instr(sqshl, N = 2))] | |
6942 | #[rustc_legacy_const_generics(1)] | |
6943 | pub unsafe fn vqshlb_n_s8<const N: i32>(a: i8) -> i8 { | |
6944 | static_assert_imm3!(N); | |
6945 | simd_extract(vqshl_n_s8::<N>(vdup_n_s8(a)), 0) | |
6946 | } | |
6947 | ||
6948 | /// Signed saturating shift left | |
6949 | #[inline] | |
6950 | #[target_feature(enable = "neon")] | |
6951 | #[cfg_attr(test, assert_instr(sqshl, N = 2))] | |
6952 | #[rustc_legacy_const_generics(1)] | |
6953 | pub unsafe fn vqshlh_n_s16<const N: i32>(a: i16) -> i16 { | |
6954 | static_assert_imm4!(N); | |
6955 | simd_extract(vqshl_n_s16::<N>(vdup_n_s16(a)), 0) | |
6956 | } | |
6957 | ||
6958 | /// Signed saturating shift left | |
6959 | #[inline] | |
6960 | #[target_feature(enable = "neon")] | |
6961 | #[cfg_attr(test, assert_instr(sqshl, N = 2))] | |
6962 | #[rustc_legacy_const_generics(1)] | |
6963 | pub unsafe fn vqshls_n_s32<const N: i32>(a: i32) -> i32 { | |
6964 | static_assert_imm5!(N); | |
6965 | simd_extract(vqshl_n_s32::<N>(vdup_n_s32(a)), 0) | |
6966 | } | |
6967 | ||
6968 | /// Signed saturating shift left | |
6969 | #[inline] | |
6970 | #[target_feature(enable = "neon")] | |
6971 | #[cfg_attr(test, assert_instr(sqshl, N = 2))] | |
6972 | #[rustc_legacy_const_generics(1)] | |
6973 | pub unsafe fn vqshld_n_s64<const N: i32>(a: i64) -> i64 { | |
6974 | static_assert_imm6!(N); | |
6975 | simd_extract(vqshl_n_s64::<N>(vdup_n_s64(a)), 0) | |
6976 | } | |
6977 | ||
6978 | /// Unsigned saturating shift left | |
6979 | #[inline] | |
6980 | #[target_feature(enable = "neon")] | |
6981 | #[cfg_attr(test, assert_instr(uqshl, N = 2))] | |
6982 | #[rustc_legacy_const_generics(1)] | |
6983 | pub unsafe fn vqshlb_n_u8<const N: i32>(a: u8) -> u8 { | |
6984 | static_assert_imm3!(N); | |
6985 | simd_extract(vqshl_n_u8::<N>(vdup_n_u8(a)), 0) | |
6986 | } | |
6987 | ||
6988 | /// Unsigned saturating shift left | |
6989 | #[inline] | |
6990 | #[target_feature(enable = "neon")] | |
6991 | #[cfg_attr(test, assert_instr(uqshl, N = 2))] | |
6992 | #[rustc_legacy_const_generics(1)] | |
6993 | pub unsafe fn vqshlh_n_u16<const N: i32>(a: u16) -> u16 { | |
6994 | static_assert_imm4!(N); | |
6995 | simd_extract(vqshl_n_u16::<N>(vdup_n_u16(a)), 0) | |
6996 | } | |
6997 | ||
6998 | /// Unsigned saturating shift left | |
6999 | #[inline] | |
7000 | #[target_feature(enable = "neon")] | |
7001 | #[cfg_attr(test, assert_instr(uqshl, N = 2))] | |
7002 | #[rustc_legacy_const_generics(1)] | |
7003 | pub unsafe fn vqshls_n_u32<const N: i32>(a: u32) -> u32 { | |
7004 | static_assert_imm5!(N); | |
7005 | simd_extract(vqshl_n_u32::<N>(vdup_n_u32(a)), 0) | |
7006 | } | |
7007 | ||
7008 | /// Unsigned saturating shift left | |
7009 | #[inline] | |
7010 | #[target_feature(enable = "neon")] | |
7011 | #[cfg_attr(test, assert_instr(uqshl, N = 2))] | |
7012 | #[rustc_legacy_const_generics(1)] | |
7013 | pub unsafe fn vqshld_n_u64<const N: i32>(a: u64) -> u64 { | |
7014 | static_assert_imm6!(N); | |
7015 | simd_extract(vqshl_n_u64::<N>(vdup_n_u64(a)), 0) | |
7016 | } | |
7017 | ||
7018 | /// Signed saturating shift right narrow | |
7019 | #[inline] | |
7020 | #[target_feature(enable = "neon")] | |
7021 | #[cfg_attr(test, assert_instr(sqshrn, N = 2))] | |
7022 | #[rustc_legacy_const_generics(1)] | |
7023 | pub unsafe fn vqshrnd_n_s64<const N: i32>(a: i64) -> i32 { | |
7024 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
7025 | #[allow(improper_ctypes)] | |
7026 | extern "C" { | |
7027 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqshrn.i32")] | |
7028 | fn vqshrnd_n_s64_(a: i64, n: i32) -> i32; | |
7029 | } | |
7030 | vqshrnd_n_s64_(a, N) | |
7031 | } | |
7032 | ||
7033 | /// Signed saturating shift right narrow | |
7034 | #[inline] | |
7035 | #[target_feature(enable = "neon")] | |
7036 | #[cfg_attr(test, assert_instr(sqshrn, N = 2))] | |
7037 | #[rustc_legacy_const_generics(1)] | |
7038 | pub unsafe fn vqshrnh_n_s16<const N: i32>(a: i16) -> i8 { | |
7039 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
7040 | simd_extract(vqshrn_n_s16::<N>(vdupq_n_s16(a)), 0) | |
7041 | } | |
7042 | ||
7043 | /// Signed saturating shift right narrow | |
7044 | #[inline] | |
7045 | #[target_feature(enable = "neon")] | |
7046 | #[cfg_attr(test, assert_instr(sqshrn, N = 2))] | |
7047 | #[rustc_legacy_const_generics(1)] | |
7048 | pub unsafe fn vqshrns_n_s32<const N: i32>(a: i32) -> i16 { | |
7049 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
7050 | simd_extract(vqshrn_n_s32::<N>(vdupq_n_s32(a)), 0) | |
7051 | } | |
7052 | ||
7053 | /// Signed saturating shift right narrow | |
7054 | #[inline] | |
7055 | #[target_feature(enable = "neon")] | |
7056 | #[cfg_attr(test, assert_instr(sqshrn2, N = 2))] | |
7057 | #[rustc_legacy_const_generics(2)] | |
7058 | pub unsafe fn vqshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t { | |
7059 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
7060 | simd_shuffle16!(a, vqshrn_n_s16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
7061 | } | |
7062 | ||
7063 | /// Signed saturating shift right narrow | |
7064 | #[inline] | |
7065 | #[target_feature(enable = "neon")] | |
7066 | #[cfg_attr(test, assert_instr(sqshrn2, N = 2))] | |
7067 | #[rustc_legacy_const_generics(2)] | |
7068 | pub unsafe fn vqshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t { | |
7069 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
7070 | simd_shuffle8!(a, vqshrn_n_s32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
7071 | } | |
7072 | ||
7073 | /// Signed saturating shift right narrow | |
7074 | #[inline] | |
7075 | #[target_feature(enable = "neon")] | |
7076 | #[cfg_attr(test, assert_instr(sqshrn2, N = 2))] | |
7077 | #[rustc_legacy_const_generics(2)] | |
7078 | pub unsafe fn vqshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t { | |
7079 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
7080 | simd_shuffle4!(a, vqshrn_n_s64::<N>(b), [0, 1, 2, 3]) | |
7081 | } | |
7082 | ||
7083 | /// Unsigned saturating shift right narrow | |
7084 | #[inline] | |
7085 | #[target_feature(enable = "neon")] | |
7086 | #[cfg_attr(test, assert_instr(uqshrn, N = 2))] | |
7087 | #[rustc_legacy_const_generics(1)] | |
7088 | pub unsafe fn vqshrnd_n_u64<const N: i32>(a: u64) -> u32 { | |
7089 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
7090 | #[allow(improper_ctypes)] | |
7091 | extern "C" { | |
7092 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uqshrn.i32")] | |
7093 | fn vqshrnd_n_u64_(a: u64, n: i32) -> u32; | |
7094 | } | |
7095 | vqshrnd_n_u64_(a, N) | |
7096 | } | |
7097 | ||
7098 | /// Unsigned saturating shift right narrow | |
7099 | #[inline] | |
7100 | #[target_feature(enable = "neon")] | |
7101 | #[cfg_attr(test, assert_instr(uqshrn, N = 2))] | |
7102 | #[rustc_legacy_const_generics(1)] | |
7103 | pub unsafe fn vqshrnh_n_u16<const N: i32>(a: u16) -> u8 { | |
7104 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
7105 | simd_extract(vqshrn_n_u16::<N>(vdupq_n_u16(a)), 0) | |
7106 | } | |
7107 | ||
7108 | /// Unsigned saturating shift right narrow | |
7109 | #[inline] | |
7110 | #[target_feature(enable = "neon")] | |
7111 | #[cfg_attr(test, assert_instr(uqshrn, N = 2))] | |
7112 | #[rustc_legacy_const_generics(1)] | |
7113 | pub unsafe fn vqshrns_n_u32<const N: i32>(a: u32) -> u16 { | |
7114 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
7115 | simd_extract(vqshrn_n_u32::<N>(vdupq_n_u32(a)), 0) | |
7116 | } | |
7117 | ||
7118 | /// Unsigned saturating shift right narrow | |
7119 | #[inline] | |
7120 | #[target_feature(enable = "neon")] | |
7121 | #[cfg_attr(test, assert_instr(uqshrn2, N = 2))] | |
7122 | #[rustc_legacy_const_generics(2)] | |
7123 | pub unsafe fn vqshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { | |
7124 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
7125 | simd_shuffle16!(a, vqshrn_n_u16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
7126 | } | |
7127 | ||
7128 | /// Unsigned saturating shift right narrow | |
7129 | #[inline] | |
7130 | #[target_feature(enable = "neon")] | |
7131 | #[cfg_attr(test, assert_instr(uqshrn2, N = 2))] | |
7132 | #[rustc_legacy_const_generics(2)] | |
7133 | pub unsafe fn vqshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { | |
7134 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
7135 | simd_shuffle8!(a, vqshrn_n_u32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
7136 | } | |
7137 | ||
7138 | /// Unsigned saturating shift right narrow | |
7139 | #[inline] | |
7140 | #[target_feature(enable = "neon")] | |
7141 | #[cfg_attr(test, assert_instr(uqshrn2, N = 2))] | |
7142 | #[rustc_legacy_const_generics(2)] | |
7143 | pub unsafe fn vqshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { | |
7144 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
7145 | simd_shuffle4!(a, vqshrn_n_u64::<N>(b), [0, 1, 2, 3]) | |
7146 | } | |
7147 | ||
7148 | /// Signed saturating shift right unsigned narrow | |
7149 | #[inline] | |
7150 | #[target_feature(enable = "neon")] | |
7151 | #[cfg_attr(test, assert_instr(sqshrun, N = 2))] | |
7152 | #[rustc_legacy_const_generics(1)] | |
7153 | pub unsafe fn vqshrunh_n_s16<const N: i32>(a: i16) -> u8 { | |
7154 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
7155 | simd_extract(vqshrun_n_s16::<N>(vdupq_n_s16(a)), 0) | |
7156 | } | |
7157 | ||
7158 | /// Signed saturating shift right unsigned narrow | |
7159 | #[inline] | |
7160 | #[target_feature(enable = "neon")] | |
7161 | #[cfg_attr(test, assert_instr(sqshrun, N = 2))] | |
7162 | #[rustc_legacy_const_generics(1)] | |
7163 | pub unsafe fn vqshruns_n_s32<const N: i32>(a: i32) -> u16 { | |
7164 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
7165 | simd_extract(vqshrun_n_s32::<N>(vdupq_n_s32(a)), 0) | |
7166 | } | |
7167 | ||
7168 | /// Signed saturating shift right unsigned narrow | |
7169 | #[inline] | |
7170 | #[target_feature(enable = "neon")] | |
7171 | #[cfg_attr(test, assert_instr(sqshrun, N = 2))] | |
7172 | #[rustc_legacy_const_generics(1)] | |
7173 | pub unsafe fn vqshrund_n_s64<const N: i32>(a: i64) -> u32 { | |
7174 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
7175 | simd_extract(vqshrun_n_s64::<N>(vdupq_n_s64(a)), 0) | |
7176 | } | |
7177 | ||
7178 | /// Signed saturating shift right unsigned narrow | |
7179 | #[inline] | |
7180 | #[target_feature(enable = "neon")] | |
7181 | #[cfg_attr(test, assert_instr(sqshrun2, N = 2))] | |
7182 | #[rustc_legacy_const_generics(2)] | |
7183 | pub unsafe fn vqshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { | |
7184 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
7185 | simd_shuffle16!(a, vqshrun_n_s16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
7186 | } | |
7187 | ||
7188 | /// Signed saturating shift right unsigned narrow | |
7189 | #[inline] | |
7190 | #[target_feature(enable = "neon")] | |
7191 | #[cfg_attr(test, assert_instr(sqshrun2, N = 2))] | |
7192 | #[rustc_legacy_const_generics(2)] | |
7193 | pub unsafe fn vqshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { | |
7194 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
7195 | simd_shuffle8!(a, vqshrun_n_s32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
7196 | } | |
7197 | ||
7198 | /// Signed saturating shift right unsigned narrow | |
7199 | #[inline] | |
7200 | #[target_feature(enable = "neon")] | |
7201 | #[cfg_attr(test, assert_instr(sqshrun2, N = 2))] | |
7202 | #[rustc_legacy_const_generics(2)] | |
7203 | pub unsafe fn vqshrun_high_n_s64<const N: i32>(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { | |
7204 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
7205 | simd_shuffle4!(a, vqshrun_n_s64::<N>(b), [0, 1, 2, 3]) | |
7206 | } | |
7207 | ||
7208 | /// Calculates the square root of each lane. | |
7209 | #[inline] | |
7210 | #[target_feature(enable = "neon")] | |
7211 | #[cfg_attr(test, assert_instr(fsqrt))] | |
7212 | pub unsafe fn vsqrt_f32(a: float32x2_t) -> float32x2_t { | |
7213 | simd_fsqrt(a) | |
7214 | } | |
7215 | ||
7216 | /// Calculates the square root of each lane. | |
7217 | #[inline] | |
7218 | #[target_feature(enable = "neon")] | |
7219 | #[cfg_attr(test, assert_instr(fsqrt))] | |
7220 | pub unsafe fn vsqrtq_f32(a: float32x4_t) -> float32x4_t { | |
7221 | simd_fsqrt(a) | |
7222 | } | |
7223 | ||
7224 | /// Calculates the square root of each lane. | |
7225 | #[inline] | |
7226 | #[target_feature(enable = "neon")] | |
7227 | #[cfg_attr(test, assert_instr(fsqrt))] | |
7228 | pub unsafe fn vsqrt_f64(a: float64x1_t) -> float64x1_t { | |
7229 | simd_fsqrt(a) | |
7230 | } | |
7231 | ||
7232 | /// Calculates the square root of each lane. | |
7233 | #[inline] | |
7234 | #[target_feature(enable = "neon")] | |
7235 | #[cfg_attr(test, assert_instr(fsqrt))] | |
7236 | pub unsafe fn vsqrtq_f64(a: float64x2_t) -> float64x2_t { | |
7237 | simd_fsqrt(a) | |
7238 | } | |
7239 | ||
7240 | /// Reciprocal square-root estimate. | |
7241 | #[inline] | |
7242 | #[target_feature(enable = "neon")] | |
7243 | #[cfg_attr(test, assert_instr(frsqrte))] | |
7244 | pub unsafe fn vrsqrte_f64(a: float64x1_t) -> float64x1_t { | |
7245 | #[allow(improper_ctypes)] | |
7246 | extern "C" { | |
7247 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.frsqrte.v1f64")] | |
7248 | fn vrsqrte_f64_(a: float64x1_t) -> float64x1_t; | |
7249 | } | |
7250 | vrsqrte_f64_(a) | |
7251 | } | |
7252 | ||
7253 | /// Reciprocal square-root estimate. | |
7254 | #[inline] | |
7255 | #[target_feature(enable = "neon")] | |
7256 | #[cfg_attr(test, assert_instr(frsqrte))] | |
7257 | pub unsafe fn vrsqrteq_f64(a: float64x2_t) -> float64x2_t { | |
7258 | #[allow(improper_ctypes)] | |
7259 | extern "C" { | |
7260 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.frsqrte.v2f64")] | |
7261 | fn vrsqrteq_f64_(a: float64x2_t) -> float64x2_t; | |
7262 | } | |
7263 | vrsqrteq_f64_(a) | |
7264 | } | |
7265 | ||
7266 | /// Reciprocal estimate. | |
7267 | #[inline] | |
7268 | #[target_feature(enable = "neon")] | |
7269 | #[cfg_attr(test, assert_instr(frecpe))] | |
7270 | pub unsafe fn vrecpe_f64(a: float64x1_t) -> float64x1_t { | |
7271 | #[allow(improper_ctypes)] | |
7272 | extern "C" { | |
7273 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.frecpe.v1f64")] | |
7274 | fn vrecpe_f64_(a: float64x1_t) -> float64x1_t; | |
7275 | } | |
7276 | vrecpe_f64_(a) | |
7277 | } | |
7278 | ||
7279 | /// Reciprocal estimate. | |
7280 | #[inline] | |
7281 | #[target_feature(enable = "neon")] | |
7282 | #[cfg_attr(test, assert_instr(frecpe))] | |
7283 | pub unsafe fn vrecpeq_f64(a: float64x2_t) -> float64x2_t { | |
7284 | #[allow(improper_ctypes)] | |
7285 | extern "C" { | |
7286 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.frecpe.v2f64")] | |
7287 | fn vrecpeq_f64_(a: float64x2_t) -> float64x2_t; | |
7288 | } | |
7289 | vrecpeq_f64_(a) | |
7290 | } | |
7291 | ||
7292 | /// Vector reinterpret cast operation | |
7293 | #[inline] | |
7294 | #[target_feature(enable = "neon")] | |
7295 | #[cfg_attr(test, assert_instr(str))] | |
7296 | pub unsafe fn vreinterpret_s64_p64(a: poly64x1_t) -> int64x1_t { | |
7297 | transmute(a) | |
7298 | } | |
7299 | ||
7300 | /// Vector reinterpret cast operation | |
7301 | #[inline] | |
7302 | #[target_feature(enable = "neon")] | |
7303 | #[cfg_attr(test, assert_instr(str))] | |
7304 | pub unsafe fn vreinterpret_u64_p64(a: poly64x1_t) -> uint64x1_t { | |
7305 | transmute(a) | |
7306 | } | |
7307 | ||
7308 | /// Vector reinterpret cast operation | |
7309 | #[inline] | |
7310 | #[target_feature(enable = "neon")] | |
7311 | #[cfg_attr(test, assert_instr(str))] | |
7312 | pub unsafe fn vreinterpret_p64_s64(a: int64x1_t) -> poly64x1_t { | |
7313 | transmute(a) | |
7314 | } | |
7315 | ||
7316 | /// Vector reinterpret cast operation | |
7317 | #[inline] | |
7318 | #[target_feature(enable = "neon")] | |
7319 | #[cfg_attr(test, assert_instr(str))] | |
7320 | pub unsafe fn vreinterpret_p64_u64(a: uint64x1_t) -> poly64x1_t { | |
7321 | transmute(a) | |
7322 | } | |
7323 | ||
7324 | /// Vector reinterpret cast operation | |
7325 | #[inline] | |
7326 | #[target_feature(enable = "neon")] | |
7327 | #[cfg_attr(test, assert_instr(str))] | |
7328 | pub unsafe fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t { | |
7329 | transmute(a) | |
7330 | } | |
7331 | ||
7332 | /// Vector reinterpret cast operation | |
7333 | #[inline] | |
7334 | #[target_feature(enable = "neon")] | |
7335 | #[cfg_attr(test, assert_instr(str))] | |
7336 | pub unsafe fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t { | |
7337 | transmute(a) | |
7338 | } | |
7339 | ||
7340 | /// Vector reinterpret cast operation | |
7341 | #[inline] | |
7342 | #[target_feature(enable = "neon")] | |
7343 | #[cfg_attr(test, assert_instr(str))] | |
7344 | pub unsafe fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t { | |
7345 | transmute(a) | |
7346 | } | |
7347 | ||
7348 | /// Vector reinterpret cast operation | |
7349 | #[inline] | |
7350 | #[target_feature(enable = "neon")] | |
7351 | #[cfg_attr(test, assert_instr(str))] | |
7352 | pub unsafe fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t { | |
7353 | transmute(a) | |
7354 | } | |
7355 | ||
7356 | /// Vector reinterpret cast operation | |
7357 | #[inline] | |
7358 | #[target_feature(enable = "neon")] | |
7359 | #[cfg_attr(test, assert_instr(str))] | |
7360 | pub unsafe fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { | |
7361 | transmute(a) | |
7362 | } | |
7363 | ||
7364 | /// Vector reinterpret cast operation | |
7365 | #[inline] | |
7366 | #[target_feature(enable = "neon")] | |
7367 | #[cfg_attr(test, assert_instr(str))] | |
7368 | pub unsafe fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t { | |
7369 | transmute(a) | |
7370 | } | |
7371 | ||
7372 | /// Vector reinterpret cast operation | |
7373 | #[inline] | |
7374 | #[target_feature(enable = "neon")] | |
7375 | #[cfg_attr(test, assert_instr(str))] | |
7376 | pub unsafe fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t { | |
7377 | transmute(a) | |
7378 | } | |
7379 | ||
7380 | /// Vector reinterpret cast operation | |
7381 | #[inline] | |
7382 | #[target_feature(enable = "neon")] | |
7383 | #[cfg_attr(test, assert_instr(str))] | |
7384 | pub unsafe fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t { | |
7385 | transmute(a) | |
7386 | } | |
7387 | ||
7388 | /// Vector reinterpret cast operation | |
7389 | #[inline] | |
7390 | #[target_feature(enable = "neon")] | |
7391 | #[cfg_attr(test, assert_instr(str))] | |
7392 | pub unsafe fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { | |
7393 | transmute(a) | |
7394 | } | |
7395 | ||
7396 | /// Vector reinterpret cast operation | |
7397 | #[inline] | |
7398 | #[target_feature(enable = "neon")] | |
7399 | #[cfg_attr(test, assert_instr(str))] | |
7400 | pub unsafe fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { | |
7401 | transmute(a) | |
7402 | } | |
7403 | ||
7404 | /// Vector reinterpret cast operation | |
7405 | #[inline] | |
7406 | #[target_feature(enable = "neon")] | |
7407 | #[cfg_attr(test, assert_instr(str))] | |
7408 | pub unsafe fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { | |
7409 | transmute(a) | |
7410 | } | |
7411 | ||
7412 | /// Vector reinterpret cast operation | |
7413 | #[inline] | |
7414 | #[target_feature(enable = "neon")] | |
7415 | #[cfg_attr(test, assert_instr(str))] | |
7416 | pub unsafe fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { | |
7417 | transmute(a) | |
7418 | } | |
7419 | ||
7420 | /// Vector reinterpret cast operation | |
7421 | #[inline] | |
7422 | #[target_feature(enable = "neon")] | |
7423 | #[cfg_attr(test, assert_instr(str))] | |
7424 | pub unsafe fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { | |
7425 | transmute(a) | |
7426 | } | |
7427 | ||
7428 | /// Vector reinterpret cast operation | |
7429 | #[inline] | |
7430 | #[target_feature(enable = "neon")] | |
7431 | #[cfg_attr(test, assert_instr(str))] | |
7432 | pub unsafe fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { | |
7433 | transmute(a) | |
7434 | } | |
7435 | ||
7436 | /// Vector reinterpret cast operation | |
7437 | #[inline] | |
7438 | #[target_feature(enable = "neon")] | |
7439 | #[cfg_attr(test, assert_instr(str))] | |
7440 | pub unsafe fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { | |
7441 | transmute(a) | |
7442 | } | |
7443 | ||
7444 | /// Vector reinterpret cast operation | |
7445 | #[inline] | |
7446 | #[target_feature(enable = "neon")] | |
7447 | #[cfg_attr(test, assert_instr(str))] | |
7448 | pub unsafe fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t { | |
7449 | transmute(a) | |
7450 | } | |
7451 | ||
7452 | /// Vector reinterpret cast operation | |
7453 | #[inline] | |
7454 | #[target_feature(enable = "neon")] | |
7455 | #[cfg_attr(test, assert_instr(str))] | |
7456 | pub unsafe fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t { | |
7457 | transmute(a) | |
7458 | } | |
7459 | ||
7460 | /// Vector reinterpret cast operation | |
7461 | #[inline] | |
7462 | #[target_feature(enable = "neon")] | |
7463 | #[cfg_attr(test, assert_instr(str))] | |
7464 | pub unsafe fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t { | |
7465 | transmute(a) | |
7466 | } | |
7467 | ||
7468 | /// Vector reinterpret cast operation | |
7469 | #[inline] | |
7470 | #[target_feature(enable = "neon")] | |
7471 | #[cfg_attr(test, assert_instr(str))] | |
7472 | pub unsafe fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { | |
7473 | transmute(a) | |
7474 | } | |
7475 | ||
7476 | /// Vector reinterpret cast operation | |
7477 | #[inline] | |
7478 | #[target_feature(enable = "neon")] | |
7479 | #[cfg_attr(test, assert_instr(str))] | |
7480 | pub unsafe fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { | |
7481 | transmute(a) | |
7482 | } | |
7483 | ||
7484 | /// Vector reinterpret cast operation | |
7485 | #[inline] | |
7486 | #[target_feature(enable = "neon")] | |
7487 | #[cfg_attr(test, assert_instr(str))] | |
7488 | pub unsafe fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { | |
7489 | transmute(a) | |
7490 | } | |
7491 | ||
7492 | /// Vector reinterpret cast operation | |
7493 | #[inline] | |
7494 | #[target_feature(enable = "neon")] | |
7495 | #[cfg_attr(test, assert_instr(str))] | |
7496 | pub unsafe fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { | |
7497 | transmute(a) | |
7498 | } | |
7499 | ||
7500 | /// Vector reinterpret cast operation | |
7501 | #[inline] | |
7502 | #[target_feature(enable = "neon")] | |
7503 | #[cfg_attr(test, assert_instr(str))] | |
7504 | pub unsafe fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { | |
7505 | transmute(a) | |
7506 | } | |
7507 | ||
7508 | /// Vector reinterpret cast operation | |
7509 | #[inline] | |
7510 | #[target_feature(enable = "neon")] | |
7511 | #[cfg_attr(test, assert_instr(str))] | |
7512 | pub unsafe fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { | |
7513 | transmute(a) | |
7514 | } | |
7515 | ||
7516 | /// Vector reinterpret cast operation | |
7517 | #[inline] | |
7518 | #[target_feature(enable = "neon")] | |
7519 | #[cfg_attr(test, assert_instr(str))] | |
7520 | pub unsafe fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { | |
7521 | transmute(a) | |
7522 | } | |
7523 | ||
7524 | /// Vector reinterpret cast operation | |
7525 | #[inline] | |
7526 | #[target_feature(enable = "neon")] | |
7527 | #[cfg_attr(test, assert_instr(str))] | |
7528 | pub unsafe fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { | |
7529 | transmute(a) | |
7530 | } | |
7531 | ||
7532 | /// Vector reinterpret cast operation | |
7533 | #[inline] | |
7534 | #[target_feature(enable = "neon")] | |
7535 | #[cfg_attr(test, assert_instr(str))] | |
7536 | pub unsafe fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { | |
7537 | transmute(a) | |
7538 | } | |
7539 | ||
7540 | /// Vector reinterpret cast operation | |
7541 | #[inline] | |
7542 | #[target_feature(enable = "neon")] | |
7543 | #[cfg_attr(test, assert_instr(str))] | |
7544 | pub unsafe fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t { | |
7545 | transmute(a) | |
7546 | } | |
7547 | ||
7548 | /// Vector reinterpret cast operation | |
7549 | #[inline] | |
7550 | #[target_feature(enable = "neon")] | |
7551 | #[cfg_attr(test, assert_instr(str))] | |
7552 | pub unsafe fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t { | |
7553 | transmute(a) | |
7554 | } | |
7555 | ||
7556 | /// Vector reinterpret cast operation | |
7557 | #[inline] | |
7558 | #[target_feature(enable = "neon")] | |
7559 | #[cfg_attr(test, assert_instr(str))] | |
7560 | pub unsafe fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t { | |
7561 | transmute(a) | |
7562 | } | |
7563 | ||
7564 | /// Vector reinterpret cast operation | |
7565 | #[inline] | |
7566 | #[target_feature(enable = "neon")] | |
7567 | #[cfg_attr(test, assert_instr(str))] | |
7568 | pub unsafe fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { | |
7569 | transmute(a) | |
7570 | } | |
7571 | ||
7572 | /// Vector reinterpret cast operation | |
7573 | #[inline] | |
7574 | #[target_feature(enable = "neon")] | |
7575 | #[cfg_attr(test, assert_instr(str))] | |
7576 | pub unsafe fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { | |
7577 | transmute(a) | |
7578 | } | |
7579 | ||
7580 | /// Vector reinterpret cast operation | |
7581 | #[inline] | |
7582 | #[target_feature(enable = "neon")] | |
7583 | #[cfg_attr(test, assert_instr(str))] | |
7584 | pub unsafe fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { | |
7585 | transmute(a) | |
7586 | } | |
7587 | ||
7588 | /// Vector reinterpret cast operation | |
7589 | #[inline] | |
7590 | #[target_feature(enable = "neon")] | |
7591 | #[cfg_attr(test, assert_instr(str))] | |
7592 | pub unsafe fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { | |
7593 | transmute(a) | |
7594 | } | |
7595 | ||
7596 | /// Vector reinterpret cast operation | |
7597 | #[inline] | |
7598 | #[target_feature(enable = "neon")] | |
7599 | #[cfg_attr(test, assert_instr(str))] | |
7600 | pub unsafe fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { | |
7601 | transmute(a) | |
7602 | } | |
7603 | ||
7604 | /// Vector reinterpret cast operation | |
7605 | #[inline] | |
7606 | #[target_feature(enable = "neon")] | |
7607 | #[cfg_attr(test, assert_instr(str))] | |
7608 | pub unsafe fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { | |
7609 | transmute(a) | |
7610 | } | |
7611 | ||
7612 | /// Vector reinterpret cast operation | |
7613 | #[inline] | |
7614 | #[target_feature(enable = "neon")] | |
7615 | #[cfg_attr(test, assert_instr(str))] | |
7616 | pub unsafe fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t { | |
7617 | transmute(a) | |
7618 | } | |
7619 | ||
7620 | /// Vector reinterpret cast operation | |
7621 | #[inline] | |
7622 | #[target_feature(enable = "neon")] | |
7623 | #[cfg_attr(test, assert_instr(str))] | |
7624 | pub unsafe fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t { | |
7625 | transmute(a) | |
7626 | } | |
7627 | ||
7628 | /// Vector reinterpret cast operation | |
7629 | #[inline] | |
7630 | #[target_feature(enable = "neon")] | |
7631 | #[cfg_attr(test, assert_instr(str))] | |
7632 | pub unsafe fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t { | |
7633 | transmute(a) | |
7634 | } | |
7635 | ||
7636 | /// Vector reinterpret cast operation | |
7637 | #[inline] | |
7638 | #[target_feature(enable = "neon")] | |
7639 | #[cfg_attr(test, assert_instr(str))] | |
7640 | pub unsafe fn vreinterpret_s64_f64(a: float64x1_t) -> int64x1_t { | |
7641 | transmute(a) | |
7642 | } | |
7643 | ||
7644 | /// Vector reinterpret cast operation | |
7645 | #[inline] | |
7646 | #[target_feature(enable = "neon")] | |
7647 | #[cfg_attr(test, assert_instr(str))] | |
7648 | pub unsafe fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t { | |
7649 | transmute(a) | |
7650 | } | |
7651 | ||
7652 | /// Vector reinterpret cast operation | |
7653 | #[inline] | |
7654 | #[target_feature(enable = "neon")] | |
7655 | #[cfg_attr(test, assert_instr(str))] | |
7656 | pub unsafe fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t { | |
7657 | transmute(a) | |
7658 | } | |
7659 | ||
7660 | /// Vector reinterpret cast operation | |
7661 | #[inline] | |
7662 | #[target_feature(enable = "neon")] | |
7663 | #[cfg_attr(test, assert_instr(str))] | |
7664 | pub unsafe fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t { | |
7665 | transmute(a) | |
7666 | } | |
7667 | ||
7668 | /// Vector reinterpret cast operation | |
7669 | #[inline] | |
7670 | #[target_feature(enable = "neon")] | |
7671 | #[cfg_attr(test, assert_instr(str))] | |
7672 | pub unsafe fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t { | |
7673 | transmute(a) | |
7674 | } | |
7675 | ||
7676 | /// Vector reinterpret cast operation | |
7677 | #[inline] | |
7678 | #[target_feature(enable = "neon")] | |
7679 | #[cfg_attr(test, assert_instr(str))] | |
7680 | pub unsafe fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t { | |
7681 | transmute(a) | |
7682 | } | |
7683 | ||
7684 | /// Vector reinterpret cast operation | |
7685 | #[inline] | |
7686 | #[target_feature(enable = "neon")] | |
7687 | #[cfg_attr(test, assert_instr(str))] | |
7688 | pub unsafe fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t { | |
7689 | transmute(a) | |
7690 | } | |
7691 | ||
7692 | /// Vector reinterpret cast operation | |
7693 | #[inline] | |
7694 | #[target_feature(enable = "neon")] | |
7695 | #[cfg_attr(test, assert_instr(str))] | |
7696 | pub unsafe fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t { | |
7697 | transmute(a) | |
7698 | } | |
7699 | ||
7700 | /// Vector reinterpret cast operation | |
7701 | #[inline] | |
7702 | #[target_feature(enable = "neon")] | |
7703 | #[cfg_attr(test, assert_instr(str))] | |
7704 | pub unsafe fn vreinterpret_u64_f64(a: float64x1_t) -> uint64x1_t { | |
7705 | transmute(a) | |
7706 | } | |
7707 | ||
7708 | /// Vector reinterpret cast operation | |
7709 | #[inline] | |
7710 | #[target_feature(enable = "neon")] | |
7711 | #[cfg_attr(test, assert_instr(str))] | |
7712 | pub unsafe fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t { | |
7713 | transmute(a) | |
7714 | } | |
7715 | ||
7716 | /// Vector reinterpret cast operation | |
7717 | #[inline] | |
7718 | #[target_feature(enable = "neon")] | |
7719 | #[cfg_attr(test, assert_instr(str))] | |
7720 | pub unsafe fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t { | |
7721 | transmute(a) | |
7722 | } | |
7723 | ||
7724 | /// Vector reinterpret cast operation | |
7725 | #[inline] | |
7726 | #[target_feature(enable = "neon")] | |
7727 | #[cfg_attr(test, assert_instr(str))] | |
7728 | pub unsafe fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t { | |
7729 | transmute(a) | |
7730 | } | |
7731 | ||
7732 | /// Vector reinterpret cast operation | |
7733 | #[inline] | |
7734 | #[target_feature(enable = "neon")] | |
7735 | #[cfg_attr(test, assert_instr(str))] | |
7736 | pub unsafe fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t { | |
7737 | transmute(a) | |
7738 | } | |
7739 | ||
7740 | /// Vector reinterpret cast operation | |
7741 | #[inline] | |
7742 | #[target_feature(enable = "neon")] | |
7743 | #[cfg_attr(test, assert_instr(str))] | |
7744 | pub unsafe fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t { | |
7745 | transmute(a) | |
7746 | } | |
7747 | ||
7748 | /// Vector reinterpret cast operation | |
7749 | #[inline] | |
7750 | #[target_feature(enable = "neon")] | |
7751 | #[cfg_attr(test, assert_instr(str))] | |
7752 | pub unsafe fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t { | |
7753 | transmute(a) | |
7754 | } | |
7755 | ||
7756 | /// Vector reinterpret cast operation | |
7757 | #[inline] | |
7758 | #[target_feature(enable = "neon")] | |
7759 | #[cfg_attr(test, assert_instr(str))] | |
7760 | pub unsafe fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t { | |
7761 | transmute(a) | |
7762 | } | |
7763 | ||
7764 | /// Vector reinterpret cast operation | |
7765 | #[inline] | |
7766 | #[target_feature(enable = "neon")] | |
7767 | #[cfg_attr(test, assert_instr(str))] | |
7768 | pub unsafe fn vreinterpret_p64_f64(a: float64x1_t) -> poly64x1_t { | |
7769 | transmute(a) | |
7770 | } | |
7771 | ||
7772 | /// Vector reinterpret cast operation | |
7773 | #[inline] | |
7774 | #[target_feature(enable = "neon")] | |
7775 | #[cfg_attr(test, assert_instr(str))] | |
7776 | pub unsafe fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t { | |
7777 | transmute(a) | |
7778 | } | |
7779 | ||
7780 | /// Vector reinterpret cast operation | |
7781 | #[inline] | |
7782 | #[target_feature(enable = "neon")] | |
7783 | #[cfg_attr(test, assert_instr(str))] | |
7784 | pub unsafe fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t { | |
7785 | transmute(a) | |
7786 | } | |
7787 | ||
7788 | /// Vector reinterpret cast operation | |
7789 | #[inline] | |
7790 | #[target_feature(enable = "neon")] | |
7791 | #[cfg_attr(test, assert_instr(str))] | |
7792 | pub unsafe fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t { | |
7793 | transmute(a) | |
7794 | } | |
7795 | ||
7796 | /// Vector reinterpret cast operation | |
7797 | #[inline] | |
7798 | #[target_feature(enable = "neon")] | |
7799 | #[cfg_attr(test, assert_instr(str))] | |
7800 | pub unsafe fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t { | |
7801 | transmute(a) | |
7802 | } | |
7803 | ||
7804 | /// Vector reinterpret cast operation | |
7805 | #[inline] | |
7806 | #[target_feature(enable = "neon")] | |
7807 | #[cfg_attr(test, assert_instr(str))] | |
7808 | pub unsafe fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t { | |
7809 | transmute(a) | |
7810 | } | |
7811 | ||
7812 | /// Vector reinterpret cast operation | |
7813 | #[inline] | |
7814 | #[target_feature(enable = "neon")] | |
7815 | #[cfg_attr(test, assert_instr(str))] | |
7816 | pub unsafe fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t { | |
7817 | transmute(a) | |
7818 | } | |
7819 | ||
7820 | /// Vector reinterpret cast operation | |
7821 | #[inline] | |
7822 | #[target_feature(enable = "neon")] | |
7823 | #[cfg_attr(test, assert_instr(str))] | |
7824 | pub unsafe fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t { | |
7825 | transmute(a) | |
7826 | } | |
7827 | ||
7828 | /// Vector reinterpret cast operation | |
7829 | #[inline] | |
7830 | #[target_feature(enable = "neon")] | |
7831 | #[cfg_attr(test, assert_instr(str))] | |
7832 | pub unsafe fn vreinterpret_f64_s64(a: int64x1_t) -> float64x1_t { | |
7833 | transmute(a) | |
7834 | } | |
7835 | ||
7836 | /// Vector reinterpret cast operation | |
7837 | #[inline] | |
7838 | #[target_feature(enable = "neon")] | |
7839 | #[cfg_attr(test, assert_instr(str))] | |
7840 | pub unsafe fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t { | |
7841 | transmute(a) | |
7842 | } | |
7843 | ||
7844 | /// Vector reinterpret cast operation | |
7845 | #[inline] | |
7846 | #[target_feature(enable = "neon")] | |
7847 | #[cfg_attr(test, assert_instr(str))] | |
7848 | pub unsafe fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t { | |
7849 | transmute(a) | |
7850 | } | |
7851 | ||
7852 | /// Vector reinterpret cast operation | |
7853 | #[inline] | |
7854 | #[target_feature(enable = "neon")] | |
7855 | #[cfg_attr(test, assert_instr(str))] | |
7856 | pub unsafe fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t { | |
7857 | transmute(a) | |
7858 | } | |
7859 | ||
7860 | /// Vector reinterpret cast operation | |
7861 | #[inline] | |
7862 | #[target_feature(enable = "neon")] | |
7863 | #[cfg_attr(test, assert_instr(str))] | |
7864 | pub unsafe fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t { | |
7865 | transmute(a) | |
7866 | } | |
7867 | ||
7868 | /// Vector reinterpret cast operation | |
7869 | #[inline] | |
7870 | #[target_feature(enable = "neon")] | |
7871 | #[cfg_attr(test, assert_instr(str))] | |
7872 | pub unsafe fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t { | |
7873 | transmute(a) | |
7874 | } | |
7875 | ||
7876 | /// Vector reinterpret cast operation | |
7877 | #[inline] | |
7878 | #[target_feature(enable = "neon")] | |
7879 | #[cfg_attr(test, assert_instr(str))] | |
7880 | pub unsafe fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t { | |
7881 | transmute(a) | |
7882 | } | |
7883 | ||
7884 | /// Vector reinterpret cast operation | |
7885 | #[inline] | |
7886 | #[target_feature(enable = "neon")] | |
7887 | #[cfg_attr(test, assert_instr(str))] | |
7888 | pub unsafe fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t { | |
7889 | transmute(a) | |
7890 | } | |
7891 | ||
7892 | /// Vector reinterpret cast operation | |
7893 | #[inline] | |
7894 | #[target_feature(enable = "neon")] | |
7895 | #[cfg_attr(test, assert_instr(str))] | |
7896 | pub unsafe fn vreinterpret_f64_u64(a: uint64x1_t) -> float64x1_t { | |
7897 | transmute(a) | |
7898 | } | |
7899 | ||
7900 | /// Vector reinterpret cast operation | |
7901 | #[inline] | |
7902 | #[target_feature(enable = "neon")] | |
7903 | #[cfg_attr(test, assert_instr(str))] | |
7904 | pub unsafe fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t { | |
7905 | transmute(a) | |
7906 | } | |
7907 | ||
7908 | /// Vector reinterpret cast operation | |
7909 | #[inline] | |
7910 | #[target_feature(enable = "neon")] | |
7911 | #[cfg_attr(test, assert_instr(str))] | |
7912 | pub unsafe fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t { | |
7913 | transmute(a) | |
7914 | } | |
7915 | ||
7916 | /// Vector reinterpret cast operation | |
7917 | #[inline] | |
7918 | #[target_feature(enable = "neon")] | |
7919 | #[cfg_attr(test, assert_instr(str))] | |
7920 | pub unsafe fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t { | |
7921 | transmute(a) | |
7922 | } | |
7923 | ||
7924 | /// Vector reinterpret cast operation | |
7925 | #[inline] | |
7926 | #[target_feature(enable = "neon")] | |
7927 | #[cfg_attr(test, assert_instr(str))] | |
7928 | pub unsafe fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t { | |
7929 | transmute(a) | |
7930 | } | |
7931 | ||
7932 | /// Vector reinterpret cast operation | |
7933 | #[inline] | |
7934 | #[target_feature(enable = "neon")] | |
7935 | #[cfg_attr(test, assert_instr(str))] | |
7936 | pub unsafe fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t { | |
7937 | transmute(a) | |
7938 | } | |
7939 | ||
7940 | /// Vector reinterpret cast operation | |
7941 | #[inline] | |
7942 | #[target_feature(enable = "neon")] | |
7943 | #[cfg_attr(test, assert_instr(str))] | |
7944 | pub unsafe fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t { | |
7945 | transmute(a) | |
7946 | } | |
7947 | ||
7948 | /// Vector reinterpret cast operation | |
7949 | #[inline] | |
7950 | #[target_feature(enable = "neon")] | |
7951 | #[cfg_attr(test, assert_instr(str))] | |
7952 | pub unsafe fn vreinterpret_f64_p64(a: poly64x1_t) -> float64x1_t { | |
7953 | transmute(a) | |
7954 | } | |
7955 | ||
7956 | /// Vector reinterpret cast operation | |
7957 | #[inline] | |
7958 | #[target_feature(enable = "neon")] | |
7959 | #[cfg_attr(test, assert_instr(str))] | |
7960 | pub unsafe fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t { | |
7961 | transmute(a) | |
7962 | } | |
7963 | ||
7964 | /// Vector reinterpret cast operation | |
7965 | #[inline] | |
7966 | #[target_feature(enable = "neon")] | |
7967 | #[cfg_attr(test, assert_instr(str))] | |
7968 | pub unsafe fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t { | |
7969 | transmute(a) | |
7970 | } | |
7971 | ||
7972 | /// Vector reinterpret cast operation | |
7973 | #[inline] | |
7974 | #[target_feature(enable = "neon")] | |
7975 | #[cfg_attr(test, assert_instr(str))] | |
7976 | pub unsafe fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t { | |
7977 | transmute(a) | |
7978 | } | |
7979 | ||
7980 | /// Vector reinterpret cast operation | |
7981 | #[inline] | |
7982 | #[target_feature(enable = "neon")] | |
7983 | #[cfg_attr(test, assert_instr(str))] | |
7984 | pub unsafe fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t { | |
7985 | transmute(a) | |
7986 | } | |
7987 | ||
7988 | /// Vector reinterpret cast operation | |
7989 | #[inline] | |
7990 | #[target_feature(enable = "neon")] | |
7991 | #[cfg_attr(test, assert_instr(str))] | |
7992 | pub unsafe fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t { | |
7993 | transmute(a) | |
7994 | } | |
7995 | ||
7996 | /// Vector reinterpret cast operation | |
7997 | #[inline] | |
7998 | #[target_feature(enable = "neon")] | |
7999 | #[cfg_attr(test, assert_instr(str))] | |
8000 | pub unsafe fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t { | |
8001 | transmute(a) | |
8002 | } | |
8003 | ||
8004 | /// Vector reinterpret cast operation | |
8005 | #[inline] | |
8006 | #[target_feature(enable = "neon")] | |
8007 | #[cfg_attr(test, assert_instr(str))] | |
8008 | pub unsafe fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t { | |
8009 | transmute(a) | |
8010 | } | |
8011 | ||
8012 | /// Vector reinterpret cast operation | |
8013 | #[inline] | |
8014 | #[target_feature(enable = "neon")] | |
8015 | #[cfg_attr(test, assert_instr(str))] | |
8016 | pub unsafe fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t { | |
8017 | transmute(a) | |
8018 | } | |
8019 | ||
8020 | /// Vector reinterpret cast operation | |
8021 | #[inline] | |
8022 | #[target_feature(enable = "neon")] | |
8023 | #[cfg_attr(test, assert_instr(str))] | |
8024 | pub unsafe fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t { | |
8025 | transmute(a) | |
8026 | } | |
8027 | ||
8028 | /// Signed rounding shift left | |
8029 | #[inline] | |
8030 | #[target_feature(enable = "neon")] | |
8031 | #[cfg_attr(test, assert_instr(srshl))] | |
8032 | pub unsafe fn vrshld_s64(a: i64, b: i64) -> i64 { | |
8033 | #[allow(improper_ctypes)] | |
8034 | extern "C" { | |
8035 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.srshl.i64")] | |
8036 | fn vrshld_s64_(a: i64, b: i64) -> i64; | |
8037 | } | |
8038 | vrshld_s64_(a, b) | |
8039 | } | |
8040 | ||
8041 | /// Unsigned rounding shift left | |
8042 | #[inline] | |
8043 | #[target_feature(enable = "neon")] | |
8044 | #[cfg_attr(test, assert_instr(urshl))] | |
8045 | pub unsafe fn vrshld_u64(a: u64, b: i64) -> u64 { | |
8046 | #[allow(improper_ctypes)] | |
8047 | extern "C" { | |
8048 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.urshl.i64")] | |
8049 | fn vrshld_u64_(a: u64, b: i64) -> u64; | |
8050 | } | |
8051 | vrshld_u64_(a, b) | |
8052 | } | |
8053 | ||
8054 | /// Signed rounding shift right | |
8055 | #[inline] | |
8056 | #[target_feature(enable = "neon")] | |
8057 | #[cfg_attr(test, assert_instr(srshr, N = 2))] | |
8058 | #[rustc_legacy_const_generics(1)] | |
8059 | pub unsafe fn vrshrd_n_s64<const N: i32>(a: i64) -> i64 { | |
8060 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
8061 | vrshld_s64(a, -N as i64) | |
8062 | } | |
8063 | ||
8064 | /// Unsigned rounding shift right | |
8065 | #[inline] | |
8066 | #[target_feature(enable = "neon")] | |
8067 | #[cfg_attr(test, assert_instr(urshr, N = 2))] | |
8068 | #[rustc_legacy_const_generics(1)] | |
8069 | pub unsafe fn vrshrd_n_u64<const N: i32>(a: u64) -> u64 { | |
8070 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
8071 | vrshld_u64(a, -N as i64) | |
8072 | } | |
8073 | ||
8074 | /// Rounding shift right narrow | |
8075 | #[inline] | |
8076 | #[target_feature(enable = "neon")] | |
8077 | #[cfg_attr(test, assert_instr(rshrn2, N = 2))] | |
8078 | #[rustc_legacy_const_generics(2)] | |
8079 | pub unsafe fn vrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t { | |
8080 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
8081 | simd_shuffle16!(a, vrshrn_n_s16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
8082 | } | |
8083 | ||
8084 | /// Rounding shift right narrow | |
8085 | #[inline] | |
8086 | #[target_feature(enable = "neon")] | |
8087 | #[cfg_attr(test, assert_instr(rshrn2, N = 2))] | |
8088 | #[rustc_legacy_const_generics(2)] | |
8089 | pub unsafe fn vrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t { | |
8090 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
8091 | simd_shuffle8!(a, vrshrn_n_s32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
8092 | } | |
8093 | ||
8094 | /// Rounding shift right narrow | |
8095 | #[inline] | |
8096 | #[target_feature(enable = "neon")] | |
8097 | #[cfg_attr(test, assert_instr(rshrn2, N = 2))] | |
8098 | #[rustc_legacy_const_generics(2)] | |
8099 | pub unsafe fn vrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t { | |
8100 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
8101 | simd_shuffle4!(a, vrshrn_n_s64::<N>(b), [0, 1, 2, 3]) | |
8102 | } | |
8103 | ||
8104 | /// Rounding shift right narrow | |
8105 | #[inline] | |
8106 | #[target_feature(enable = "neon")] | |
8107 | #[cfg_attr(test, assert_instr(rshrn2, N = 2))] | |
8108 | #[rustc_legacy_const_generics(2)] | |
8109 | pub unsafe fn vrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { | |
8110 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
8111 | simd_shuffle16!(a, vrshrn_n_u16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
8112 | } | |
8113 | ||
8114 | /// Rounding shift right narrow | |
8115 | #[inline] | |
8116 | #[target_feature(enable = "neon")] | |
8117 | #[cfg_attr(test, assert_instr(rshrn2, N = 2))] | |
8118 | #[rustc_legacy_const_generics(2)] | |
8119 | pub unsafe fn vrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { | |
8120 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
8121 | simd_shuffle8!(a, vrshrn_n_u32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
8122 | } | |
8123 | ||
8124 | /// Rounding shift right narrow | |
8125 | #[inline] | |
8126 | #[target_feature(enable = "neon")] | |
8127 | #[cfg_attr(test, assert_instr(rshrn2, N = 2))] | |
8128 | #[rustc_legacy_const_generics(2)] | |
8129 | pub unsafe fn vrshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { | |
8130 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
8131 | simd_shuffle4!(a, vrshrn_n_u64::<N>(b), [0, 1, 2, 3]) | |
8132 | } | |
8133 | ||
8134 | /// Signed rounding shift right and accumulate. | |
8135 | #[inline] | |
8136 | #[target_feature(enable = "neon")] | |
8137 | #[cfg_attr(test, assert_instr(srsra, N = 2))] | |
8138 | #[rustc_legacy_const_generics(2)] | |
8139 | pub unsafe fn vrsrad_n_s64<const N: i32>(a: i64, b: i64) -> i64 { | |
8140 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
8141 | let b: i64 = vrshrd_n_s64::<N>(b); | |
8142 | a + b | |
8143 | } | |
8144 | ||
8145 | /// Ungisned rounding shift right and accumulate. | |
8146 | #[inline] | |
8147 | #[target_feature(enable = "neon")] | |
8148 | #[cfg_attr(test, assert_instr(ursra, N = 2))] | |
8149 | #[rustc_legacy_const_generics(2)] | |
8150 | pub unsafe fn vrsrad_n_u64<const N: i32>(a: u64, b: u64) -> u64 { | |
8151 | static_assert!(N : i32 where N >= 1 && N <= 64); | |
8152 | let b: u64 = vrshrd_n_u64::<N>(b); | |
8153 | a + b | |
8154 | } | |
8155 | ||
8156 | /// Insert vector element from another vector element | |
8157 | #[inline] | |
8158 | #[target_feature(enable = "neon")] | |
8159 | #[cfg_attr(test, assert_instr(nop, LANE = 0))] | |
8160 | #[rustc_legacy_const_generics(2)] | |
8161 | pub unsafe fn vset_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> float64x1_t { | |
8162 | static_assert!(LANE : i32 where LANE == 0); | |
8163 | simd_insert(b, LANE as u32, a) | |
8164 | } | |
8165 | ||
8166 | /// Insert vector element from another vector element | |
8167 | #[inline] | |
8168 | #[target_feature(enable = "neon")] | |
8169 | #[cfg_attr(test, assert_instr(nop, LANE = 0))] | |
8170 | #[rustc_legacy_const_generics(2)] | |
8171 | pub unsafe fn vsetq_lane_f64<const LANE: i32>(a: f64, b: float64x2_t) -> float64x2_t { | |
8172 | static_assert_imm1!(LANE); | |
8173 | simd_insert(b, LANE as u32, a) | |
8174 | } | |
8175 | ||
8176 | /// Signed Shift left | |
8177 | #[inline] | |
8178 | #[target_feature(enable = "neon")] | |
8179 | #[cfg_attr(test, assert_instr(sshl))] | |
8180 | pub unsafe fn vshld_s64(a: i64, b: i64) -> i64 { | |
8181 | transmute(vshl_s64(transmute(a), transmute(b))) | |
8182 | } | |
8183 | ||
8184 | /// Unsigned Shift left | |
8185 | #[inline] | |
8186 | #[target_feature(enable = "neon")] | |
8187 | #[cfg_attr(test, assert_instr(ushl))] | |
8188 | pub unsafe fn vshld_u64(a: u64, b: i64) -> u64 { | |
8189 | transmute(vshl_u64(transmute(a), transmute(b))) | |
8190 | } | |
8191 | ||
8192 | /// Signed shift left long | |
8193 | #[inline] | |
8194 | #[target_feature(enable = "neon")] | |
8195 | #[cfg_attr(test, assert_instr(sshll2, N = 2))] | |
8196 | #[rustc_legacy_const_generics(1)] | |
8197 | pub unsafe fn vshll_high_n_s8<const N: i32>(a: int8x16_t) -> int16x8_t { | |
8198 | static_assert!(N : i32 where N >= 0 && N <= 8); | |
8199 | let b: int8x8_t = simd_shuffle8!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); | |
8200 | vshll_n_s8::<N>(b) | |
8201 | } | |
8202 | ||
8203 | /// Signed shift left long | |
8204 | #[inline] | |
8205 | #[target_feature(enable = "neon")] | |
8206 | #[cfg_attr(test, assert_instr(sshll2, N = 2))] | |
8207 | #[rustc_legacy_const_generics(1)] | |
8208 | pub unsafe fn vshll_high_n_s16<const N: i32>(a: int16x8_t) -> int32x4_t { | |
8209 | static_assert!(N : i32 where N >= 0 && N <= 16); | |
8210 | let b: int16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
8211 | vshll_n_s16::<N>(b) | |
8212 | } | |
8213 | ||
8214 | /// Signed shift left long | |
8215 | #[inline] | |
8216 | #[target_feature(enable = "neon")] | |
8217 | #[cfg_attr(test, assert_instr(sshll2, N = 2))] | |
8218 | #[rustc_legacy_const_generics(1)] | |
8219 | pub unsafe fn vshll_high_n_s32<const N: i32>(a: int32x4_t) -> int64x2_t { | |
8220 | static_assert!(N : i32 where N >= 0 && N <= 32); | |
8221 | let b: int32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
8222 | vshll_n_s32::<N>(b) | |
8223 | } | |
8224 | ||
8225 | /// Signed shift left long | |
8226 | #[inline] | |
8227 | #[target_feature(enable = "neon")] | |
8228 | #[cfg_attr(test, assert_instr(ushll2, N = 2))] | |
8229 | #[rustc_legacy_const_generics(1)] | |
8230 | pub unsafe fn vshll_high_n_u8<const N: i32>(a: uint8x16_t) -> uint16x8_t { | |
8231 | static_assert!(N : i32 where N >= 0 && N <= 8); | |
8232 | let b: uint8x8_t = simd_shuffle8!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); | |
8233 | vshll_n_u8::<N>(b) | |
8234 | } | |
8235 | ||
8236 | /// Signed shift left long | |
8237 | #[inline] | |
8238 | #[target_feature(enable = "neon")] | |
8239 | #[cfg_attr(test, assert_instr(ushll2, N = 2))] | |
8240 | #[rustc_legacy_const_generics(1)] | |
8241 | pub unsafe fn vshll_high_n_u16<const N: i32>(a: uint16x8_t) -> uint32x4_t { | |
8242 | static_assert!(N : i32 where N >= 0 && N <= 16); | |
8243 | let b: uint16x4_t = simd_shuffle4!(a, a, [4, 5, 6, 7]); | |
8244 | vshll_n_u16::<N>(b) | |
8245 | } | |
8246 | ||
8247 | /// Signed shift left long | |
8248 | #[inline] | |
8249 | #[target_feature(enable = "neon")] | |
8250 | #[cfg_attr(test, assert_instr(ushll2, N = 2))] | |
8251 | #[rustc_legacy_const_generics(1)] | |
8252 | pub unsafe fn vshll_high_n_u32<const N: i32>(a: uint32x4_t) -> uint64x2_t { | |
8253 | static_assert!(N : i32 where N >= 0 && N <= 32); | |
8254 | let b: uint32x2_t = simd_shuffle2!(a, a, [2, 3]); | |
8255 | vshll_n_u32::<N>(b) | |
8256 | } | |
8257 | ||
8258 | /// Shift right narrow | |
8259 | #[inline] | |
8260 | #[target_feature(enable = "neon")] | |
8261 | #[cfg_attr(test, assert_instr(shrn2, N = 2))] | |
8262 | #[rustc_legacy_const_generics(2)] | |
8263 | pub unsafe fn vshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t { | |
8264 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
8265 | simd_shuffle16!(a, vshrn_n_s16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
8266 | } | |
8267 | ||
8268 | /// Shift right narrow | |
8269 | #[inline] | |
8270 | #[target_feature(enable = "neon")] | |
8271 | #[cfg_attr(test, assert_instr(shrn2, N = 2))] | |
8272 | #[rustc_legacy_const_generics(2)] | |
8273 | pub unsafe fn vshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t { | |
8274 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
8275 | simd_shuffle8!(a, vshrn_n_s32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
8276 | } | |
8277 | ||
8278 | /// Shift right narrow | |
8279 | #[inline] | |
8280 | #[target_feature(enable = "neon")] | |
8281 | #[cfg_attr(test, assert_instr(shrn2, N = 2))] | |
8282 | #[rustc_legacy_const_generics(2)] | |
8283 | pub unsafe fn vshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t { | |
8284 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
8285 | simd_shuffle4!(a, vshrn_n_s64::<N>(b), [0, 1, 2, 3]) | |
8286 | } | |
8287 | ||
8288 | /// Shift right narrow | |
8289 | #[inline] | |
8290 | #[target_feature(enable = "neon")] | |
8291 | #[cfg_attr(test, assert_instr(shrn2, N = 2))] | |
8292 | #[rustc_legacy_const_generics(2)] | |
8293 | pub unsafe fn vshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { | |
8294 | static_assert!(N : i32 where N >= 1 && N <= 8); | |
8295 | simd_shuffle16!(a, vshrn_n_u16::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) | |
8296 | } | |
8297 | ||
8298 | /// Shift right narrow | |
8299 | #[inline] | |
8300 | #[target_feature(enable = "neon")] | |
8301 | #[cfg_attr(test, assert_instr(shrn2, N = 2))] | |
8302 | #[rustc_legacy_const_generics(2)] | |
8303 | pub unsafe fn vshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { | |
8304 | static_assert!(N : i32 where N >= 1 && N <= 16); | |
8305 | simd_shuffle8!(a, vshrn_n_u32::<N>(b), [0, 1, 2, 3, 4, 5, 6, 7]) | |
8306 | } | |
8307 | ||
8308 | /// Shift right narrow | |
8309 | #[inline] | |
8310 | #[target_feature(enable = "neon")] | |
8311 | #[cfg_attr(test, assert_instr(shrn2, N = 2))] | |
8312 | #[rustc_legacy_const_generics(2)] | |
8313 | pub unsafe fn vshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { | |
8314 | static_assert!(N : i32 where N >= 1 && N <= 32); | |
8315 | simd_shuffle4!(a, vshrn_n_u64::<N>(b), [0, 1, 2, 3]) | |
8316 | } | |
8317 | ||
8318 | /// Transpose vectors | |
8319 | #[inline] | |
8320 | #[target_feature(enable = "neon")] | |
8321 | #[cfg_attr(test, assert_instr(trn1))] | |
8322 | pub unsafe fn vtrn1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { | |
8323 | simd_shuffle8!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) | |
8324 | } | |
8325 | ||
8326 | /// Transpose vectors | |
8327 | #[inline] | |
8328 | #[target_feature(enable = "neon")] | |
8329 | #[cfg_attr(test, assert_instr(trn1))] | |
8330 | pub unsafe fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { | |
8331 | simd_shuffle16!(a, b, [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]) | |
8332 | } | |
8333 | ||
8334 | /// Transpose vectors | |
8335 | #[inline] | |
8336 | #[target_feature(enable = "neon")] | |
8337 | #[cfg_attr(test, assert_instr(trn1))] | |
8338 | pub unsafe fn vtrn1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { | |
8339 | simd_shuffle4!(a, b, [0, 4, 2, 6]) | |
8340 | } | |
8341 | ||
8342 | /// Transpose vectors | |
8343 | #[inline] | |
8344 | #[target_feature(enable = "neon")] | |
8345 | #[cfg_attr(test, assert_instr(trn1))] | |
8346 | pub unsafe fn vtrn1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { | |
8347 | simd_shuffle8!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) | |
8348 | } | |
8349 | ||
8350 | /// Transpose vectors | |
8351 | #[inline] | |
8352 | #[target_feature(enable = "neon")] | |
8353 | #[cfg_attr(test, assert_instr(trn1))] | |
8354 | pub unsafe fn vtrn1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { | |
8355 | simd_shuffle4!(a, b, [0, 4, 2, 6]) | |
8356 | } | |
8357 | ||
8358 | /// Transpose vectors | |
8359 | #[inline] | |
8360 | #[target_feature(enable = "neon")] | |
8361 | #[cfg_attr(test, assert_instr(trn1))] | |
8362 | pub unsafe fn vtrn1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { | |
8363 | simd_shuffle8!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) | |
8364 | } | |
8365 | ||
8366 | /// Transpose vectors | |
8367 | #[inline] | |
8368 | #[target_feature(enable = "neon")] | |
8369 | #[cfg_attr(test, assert_instr(trn1))] | |
8370 | pub unsafe fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { | |
8371 | simd_shuffle16!(a, b, [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]) | |
8372 | } | |
8373 | ||
8374 | /// Transpose vectors | |
8375 | #[inline] | |
8376 | #[target_feature(enable = "neon")] | |
8377 | #[cfg_attr(test, assert_instr(trn1))] | |
8378 | pub unsafe fn vtrn1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { | |
8379 | simd_shuffle4!(a, b, [0, 4, 2, 6]) | |
8380 | } | |
8381 | ||
8382 | /// Transpose vectors | |
8383 | #[inline] | |
8384 | #[target_feature(enable = "neon")] | |
8385 | #[cfg_attr(test, assert_instr(trn1))] | |
8386 | pub unsafe fn vtrn1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { | |
8387 | simd_shuffle8!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) | |
8388 | } | |
8389 | ||
8390 | /// Transpose vectors | |
8391 | #[inline] | |
8392 | #[target_feature(enable = "neon")] | |
8393 | #[cfg_attr(test, assert_instr(trn1))] | |
8394 | pub unsafe fn vtrn1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { | |
8395 | simd_shuffle4!(a, b, [0, 4, 2, 6]) | |
8396 | } | |
8397 | ||
8398 | /// Transpose vectors | |
8399 | #[inline] | |
8400 | #[target_feature(enable = "neon")] | |
8401 | #[cfg_attr(test, assert_instr(trn1))] | |
8402 | pub unsafe fn vtrn1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { | |
8403 | simd_shuffle8!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) | |
8404 | } | |
8405 | ||
8406 | /// Transpose vectors | |
8407 | #[inline] | |
8408 | #[target_feature(enable = "neon")] | |
8409 | #[cfg_attr(test, assert_instr(trn1))] | |
8410 | pub unsafe fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { | |
8411 | simd_shuffle16!(a, b, [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]) | |
8412 | } | |
8413 | ||
8414 | /// Transpose vectors | |
8415 | #[inline] | |
8416 | #[target_feature(enable = "neon")] | |
8417 | #[cfg_attr(test, assert_instr(trn1))] | |
8418 | pub unsafe fn vtrn1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { | |
8419 | simd_shuffle4!(a, b, [0, 4, 2, 6]) | |
8420 | } | |
8421 | ||
8422 | /// Transpose vectors | |
8423 | #[inline] | |
8424 | #[target_feature(enable = "neon")] | |
8425 | #[cfg_attr(test, assert_instr(trn1))] | |
8426 | pub unsafe fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { | |
8427 | simd_shuffle8!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) | |
8428 | } | |
8429 | ||
8430 | /// Transpose vectors | |
8431 | #[inline] | |
8432 | #[target_feature(enable = "neon")] | |
8433 | #[cfg_attr(test, assert_instr(zip1))] | |
8434 | pub unsafe fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { | |
8435 | simd_shuffle2!(a, b, [0, 2]) | |
8436 | } | |
8437 | ||
8438 | /// Transpose vectors | |
8439 | #[inline] | |
8440 | #[target_feature(enable = "neon")] | |
8441 | #[cfg_attr(test, assert_instr(zip1))] | |
8442 | pub unsafe fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { | |
8443 | simd_shuffle2!(a, b, [0, 2]) | |
8444 | } | |
8445 | ||
8446 | /// Transpose vectors | |
8447 | #[inline] | |
8448 | #[target_feature(enable = "neon")] | |
8449 | #[cfg_attr(test, assert_instr(zip1))] | |
8450 | pub unsafe fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { | |
8451 | simd_shuffle2!(a, b, [0, 2]) | |
8452 | } | |
8453 | ||
8454 | /// Transpose vectors | |
8455 | #[inline] | |
8456 | #[target_feature(enable = "neon")] | |
8457 | #[cfg_attr(test, assert_instr(zip1))] | |
8458 | pub unsafe fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
8459 | simd_shuffle2!(a, b, [0, 2]) | |
8460 | } | |
8461 | ||
8462 | /// Transpose vectors | |
8463 | #[inline] | |
8464 | #[target_feature(enable = "neon")] | |
8465 | #[cfg_attr(test, assert_instr(zip1))] | |
8466 | pub unsafe fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { | |
8467 | simd_shuffle2!(a, b, [0, 2]) | |
8468 | } | |
8469 | ||
8470 | /// Transpose vectors | |
8471 | #[inline] | |
8472 | #[target_feature(enable = "neon")] | |
8473 | #[cfg_attr(test, assert_instr(trn1))] | |
8474 | pub unsafe fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
8475 | simd_shuffle4!(a, b, [0, 4, 2, 6]) | |
8476 | } | |
8477 | ||
8478 | /// Transpose vectors | |
8479 | #[inline] | |
8480 | #[target_feature(enable = "neon")] | |
8481 | #[cfg_attr(test, assert_instr(zip1))] | |
8482 | pub unsafe fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
8483 | simd_shuffle2!(a, b, [0, 2]) | |
8484 | } | |
8485 | ||
8486 | /// Transpose vectors | |
8487 | #[inline] | |
8488 | #[target_feature(enable = "neon")] | |
8489 | #[cfg_attr(test, assert_instr(zip1))] | |
8490 | pub unsafe fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
8491 | simd_shuffle2!(a, b, [0, 2]) | |
8492 | } | |
8493 | ||
8494 | /// Transpose vectors | |
8495 | #[inline] | |
8496 | #[target_feature(enable = "neon")] | |
8497 | #[cfg_attr(test, assert_instr(trn2))] | |
8498 | pub unsafe fn vtrn2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { | |
8499 | simd_shuffle8!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) | |
8500 | } | |
8501 | ||
8502 | /// Transpose vectors | |
8503 | #[inline] | |
8504 | #[target_feature(enable = "neon")] | |
8505 | #[cfg_attr(test, assert_instr(trn2))] | |
8506 | pub unsafe fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { | |
8507 | simd_shuffle16!(a, b, [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]) | |
8508 | } | |
8509 | ||
8510 | /// Transpose vectors | |
8511 | #[inline] | |
8512 | #[target_feature(enable = "neon")] | |
8513 | #[cfg_attr(test, assert_instr(trn2))] | |
8514 | pub unsafe fn vtrn2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { | |
8515 | simd_shuffle4!(a, b, [1, 5, 3, 7]) | |
8516 | } | |
8517 | ||
8518 | /// Transpose vectors | |
8519 | #[inline] | |
8520 | #[target_feature(enable = "neon")] | |
8521 | #[cfg_attr(test, assert_instr(trn2))] | |
8522 | pub unsafe fn vtrn2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { | |
8523 | simd_shuffle8!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) | |
8524 | } | |
8525 | ||
8526 | /// Transpose vectors | |
8527 | #[inline] | |
8528 | #[target_feature(enable = "neon")] | |
8529 | #[cfg_attr(test, assert_instr(trn2))] | |
8530 | pub unsafe fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { | |
8531 | simd_shuffle4!(a, b, [1, 5, 3, 7]) | |
8532 | } | |
8533 | ||
8534 | /// Transpose vectors | |
8535 | #[inline] | |
8536 | #[target_feature(enable = "neon")] | |
8537 | #[cfg_attr(test, assert_instr(trn2))] | |
8538 | pub unsafe fn vtrn2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { | |
8539 | simd_shuffle8!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) | |
8540 | } | |
8541 | ||
8542 | /// Transpose vectors | |
8543 | #[inline] | |
8544 | #[target_feature(enable = "neon")] | |
8545 | #[cfg_attr(test, assert_instr(trn2))] | |
8546 | pub unsafe fn vtrn2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { | |
8547 | simd_shuffle16!(a, b, [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]) | |
8548 | } | |
8549 | ||
8550 | /// Transpose vectors | |
8551 | #[inline] | |
8552 | #[target_feature(enable = "neon")] | |
8553 | #[cfg_attr(test, assert_instr(trn2))] | |
8554 | pub unsafe fn vtrn2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { | |
8555 | simd_shuffle4!(a, b, [1, 5, 3, 7]) | |
8556 | } | |
8557 | ||
8558 | /// Transpose vectors | |
8559 | #[inline] | |
8560 | #[target_feature(enable = "neon")] | |
8561 | #[cfg_attr(test, assert_instr(trn2))] | |
8562 | pub unsafe fn vtrn2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { | |
8563 | simd_shuffle8!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) | |
8564 | } | |
8565 | ||
8566 | /// Transpose vectors | |
8567 | #[inline] | |
8568 | #[target_feature(enable = "neon")] | |
8569 | #[cfg_attr(test, assert_instr(trn2))] | |
8570 | pub unsafe fn vtrn2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { | |
8571 | simd_shuffle4!(a, b, [1, 5, 3, 7]) | |
8572 | } | |
8573 | ||
8574 | /// Transpose vectors | |
8575 | #[inline] | |
8576 | #[target_feature(enable = "neon")] | |
8577 | #[cfg_attr(test, assert_instr(trn2))] | |
8578 | pub unsafe fn vtrn2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { | |
8579 | simd_shuffle8!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) | |
8580 | } | |
8581 | ||
8582 | /// Transpose vectors | |
8583 | #[inline] | |
8584 | #[target_feature(enable = "neon")] | |
8585 | #[cfg_attr(test, assert_instr(trn2))] | |
8586 | pub unsafe fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { | |
8587 | simd_shuffle16!(a, b, [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]) | |
8588 | } | |
8589 | ||
8590 | /// Transpose vectors | |
8591 | #[inline] | |
8592 | #[target_feature(enable = "neon")] | |
8593 | #[cfg_attr(test, assert_instr(trn2))] | |
8594 | pub unsafe fn vtrn2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { | |
8595 | simd_shuffle4!(a, b, [1, 5, 3, 7]) | |
8596 | } | |
8597 | ||
8598 | /// Transpose vectors | |
8599 | #[inline] | |
8600 | #[target_feature(enable = "neon")] | |
8601 | #[cfg_attr(test, assert_instr(trn2))] | |
8602 | pub unsafe fn vtrn2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { | |
8603 | simd_shuffle8!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) | |
8604 | } | |
8605 | ||
8606 | /// Transpose vectors | |
8607 | #[inline] | |
8608 | #[target_feature(enable = "neon")] | |
8609 | #[cfg_attr(test, assert_instr(zip2))] | |
8610 | pub unsafe fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { | |
8611 | simd_shuffle2!(a, b, [1, 3]) | |
8612 | } | |
8613 | ||
8614 | /// Transpose vectors | |
8615 | #[inline] | |
8616 | #[target_feature(enable = "neon")] | |
8617 | #[cfg_attr(test, assert_instr(zip2))] | |
8618 | pub unsafe fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { | |
8619 | simd_shuffle2!(a, b, [1, 3]) | |
8620 | } | |
8621 | ||
8622 | /// Transpose vectors | |
8623 | #[inline] | |
8624 | #[target_feature(enable = "neon")] | |
8625 | #[cfg_attr(test, assert_instr(zip2))] | |
8626 | pub unsafe fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { | |
8627 | simd_shuffle2!(a, b, [1, 3]) | |
8628 | } | |
8629 | ||
8630 | /// Transpose vectors | |
8631 | #[inline] | |
8632 | #[target_feature(enable = "neon")] | |
8633 | #[cfg_attr(test, assert_instr(zip2))] | |
8634 | pub unsafe fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
8635 | simd_shuffle2!(a, b, [1, 3]) | |
8636 | } | |
8637 | ||
8638 | /// Transpose vectors | |
8639 | #[inline] | |
8640 | #[target_feature(enable = "neon")] | |
8641 | #[cfg_attr(test, assert_instr(zip2))] | |
8642 | pub unsafe fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { | |
8643 | simd_shuffle2!(a, b, [1, 3]) | |
8644 | } | |
8645 | ||
8646 | /// Transpose vectors | |
8647 | #[inline] | |
8648 | #[target_feature(enable = "neon")] | |
8649 | #[cfg_attr(test, assert_instr(trn2))] | |
8650 | pub unsafe fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
8651 | simd_shuffle4!(a, b, [1, 5, 3, 7]) | |
8652 | } | |
8653 | ||
8654 | /// Transpose vectors | |
8655 | #[inline] | |
8656 | #[target_feature(enable = "neon")] | |
8657 | #[cfg_attr(test, assert_instr(zip2))] | |
8658 | pub unsafe fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
8659 | simd_shuffle2!(a, b, [1, 3]) | |
8660 | } | |
8661 | ||
8662 | /// Transpose vectors | |
8663 | #[inline] | |
8664 | #[target_feature(enable = "neon")] | |
8665 | #[cfg_attr(test, assert_instr(zip2))] | |
8666 | pub unsafe fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
8667 | simd_shuffle2!(a, b, [1, 3]) | |
8668 | } | |
8669 | ||
8670 | /// Zip vectors | |
8671 | #[inline] | |
8672 | #[target_feature(enable = "neon")] | |
8673 | #[cfg_attr(test, assert_instr(zip1))] | |
8674 | pub unsafe fn vzip1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { | |
8675 | simd_shuffle8!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) | |
8676 | } | |
8677 | ||
8678 | /// Zip vectors | |
8679 | #[inline] | |
8680 | #[target_feature(enable = "neon")] | |
8681 | #[cfg_attr(test, assert_instr(zip1))] | |
8682 | pub unsafe fn vzip1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { | |
8683 | simd_shuffle16!(a, b, [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]) | |
8684 | } | |
8685 | ||
8686 | /// Zip vectors | |
8687 | #[inline] | |
8688 | #[target_feature(enable = "neon")] | |
8689 | #[cfg_attr(test, assert_instr(zip1))] | |
8690 | pub unsafe fn vzip1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { | |
8691 | simd_shuffle4!(a, b, [0, 4, 1, 5]) | |
8692 | } | |
8693 | ||
8694 | /// Zip vectors | |
8695 | #[inline] | |
8696 | #[target_feature(enable = "neon")] | |
8697 | #[cfg_attr(test, assert_instr(zip1))] | |
8698 | pub unsafe fn vzip1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { | |
8699 | simd_shuffle8!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) | |
8700 | } | |
8701 | ||
8702 | /// Zip vectors | |
8703 | #[inline] | |
8704 | #[target_feature(enable = "neon")] | |
8705 | #[cfg_attr(test, assert_instr(zip1))] | |
8706 | pub unsafe fn vzip1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { | |
8707 | simd_shuffle2!(a, b, [0, 2]) | |
8708 | } | |
8709 | ||
8710 | /// Zip vectors | |
8711 | #[inline] | |
8712 | #[target_feature(enable = "neon")] | |
8713 | #[cfg_attr(test, assert_instr(zip1))] | |
8714 | pub unsafe fn vzip1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { | |
8715 | simd_shuffle4!(a, b, [0, 4, 1, 5]) | |
8716 | } | |
8717 | ||
8718 | /// Zip vectors | |
8719 | #[inline] | |
8720 | #[target_feature(enable = "neon")] | |
8721 | #[cfg_attr(test, assert_instr(zip1))] | |
8722 | pub unsafe fn vzip1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { | |
8723 | simd_shuffle2!(a, b, [0, 2]) | |
8724 | } | |
8725 | ||
8726 | /// Zip vectors | |
8727 | #[inline] | |
8728 | #[target_feature(enable = "neon")] | |
8729 | #[cfg_attr(test, assert_instr(zip1))] | |
8730 | pub unsafe fn vzip1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { | |
8731 | simd_shuffle8!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) | |
8732 | } | |
8733 | ||
8734 | /// Zip vectors | |
8735 | #[inline] | |
8736 | #[target_feature(enable = "neon")] | |
8737 | #[cfg_attr(test, assert_instr(zip1))] | |
8738 | pub unsafe fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { | |
8739 | simd_shuffle16!(a, b, [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]) | |
8740 | } | |
8741 | ||
8742 | /// Zip vectors | |
8743 | #[inline] | |
8744 | #[target_feature(enable = "neon")] | |
8745 | #[cfg_attr(test, assert_instr(zip1))] | |
8746 | pub unsafe fn vzip1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { | |
8747 | simd_shuffle4!(a, b, [0, 4, 1, 5]) | |
8748 | } | |
8749 | ||
8750 | /// Zip vectors | |
8751 | #[inline] | |
8752 | #[target_feature(enable = "neon")] | |
8753 | #[cfg_attr(test, assert_instr(zip1))] | |
8754 | pub unsafe fn vzip1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { | |
8755 | simd_shuffle8!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) | |
8756 | } | |
8757 | ||
8758 | /// Zip vectors | |
8759 | #[inline] | |
8760 | #[target_feature(enable = "neon")] | |
8761 | #[cfg_attr(test, assert_instr(zip1))] | |
8762 | pub unsafe fn vzip1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { | |
8763 | simd_shuffle2!(a, b, [0, 2]) | |
8764 | } | |
8765 | ||
8766 | /// Zip vectors | |
8767 | #[inline] | |
8768 | #[target_feature(enable = "neon")] | |
8769 | #[cfg_attr(test, assert_instr(zip1))] | |
8770 | pub unsafe fn vzip1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { | |
8771 | simd_shuffle4!(a, b, [0, 4, 1, 5]) | |
8772 | } | |
8773 | ||
8774 | /// Zip vectors | |
8775 | #[inline] | |
8776 | #[target_feature(enable = "neon")] | |
8777 | #[cfg_attr(test, assert_instr(zip1))] | |
8778 | pub unsafe fn vzip1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
8779 | simd_shuffle2!(a, b, [0, 2]) | |
8780 | } | |
8781 | ||
8782 | /// Zip vectors | |
8783 | #[inline] | |
8784 | #[target_feature(enable = "neon")] | |
8785 | #[cfg_attr(test, assert_instr(zip1))] | |
8786 | pub unsafe fn vzip1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { | |
8787 | simd_shuffle8!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) | |
8788 | } | |
8789 | ||
8790 | /// Zip vectors | |
8791 | #[inline] | |
8792 | #[target_feature(enable = "neon")] | |
8793 | #[cfg_attr(test, assert_instr(zip1))] | |
8794 | pub unsafe fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { | |
8795 | simd_shuffle16!(a, b, [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]) | |
8796 | } | |
8797 | ||
8798 | /// Zip vectors | |
8799 | #[inline] | |
8800 | #[target_feature(enable = "neon")] | |
8801 | #[cfg_attr(test, assert_instr(zip1))] | |
8802 | pub unsafe fn vzip1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { | |
8803 | simd_shuffle4!(a, b, [0, 4, 1, 5]) | |
8804 | } | |
8805 | ||
8806 | /// Zip vectors | |
8807 | #[inline] | |
8808 | #[target_feature(enable = "neon")] | |
8809 | #[cfg_attr(test, assert_instr(zip1))] | |
8810 | pub unsafe fn vzip1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { | |
8811 | simd_shuffle8!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) | |
8812 | } | |
8813 | ||
8814 | /// Zip vectors | |
8815 | #[inline] | |
8816 | #[target_feature(enable = "neon")] | |
8817 | #[cfg_attr(test, assert_instr(zip1))] | |
8818 | pub unsafe fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { | |
8819 | simd_shuffle2!(a, b, [0, 2]) | |
8820 | } | |
8821 | ||
8822 | /// Zip vectors | |
8823 | #[inline] | |
8824 | #[target_feature(enable = "neon")] | |
8825 | #[cfg_attr(test, assert_instr(zip1))] | |
8826 | pub unsafe fn vzip1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
8827 | simd_shuffle2!(a, b, [0, 2]) | |
8828 | } | |
8829 | ||
8830 | /// Zip vectors | |
8831 | #[inline] | |
8832 | #[target_feature(enable = "neon")] | |
8833 | #[cfg_attr(test, assert_instr(zip1))] | |
8834 | pub unsafe fn vzip1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
8835 | simd_shuffle4!(a, b, [0, 4, 1, 5]) | |
8836 | } | |
8837 | ||
8838 | /// Zip vectors | |
8839 | #[inline] | |
8840 | #[target_feature(enable = "neon")] | |
8841 | #[cfg_attr(test, assert_instr(zip1))] | |
8842 | pub unsafe fn vzip1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
8843 | simd_shuffle2!(a, b, [0, 2]) | |
8844 | } | |
8845 | ||
8846 | /// Zip vectors | |
8847 | #[inline] | |
8848 | #[target_feature(enable = "neon")] | |
8849 | #[cfg_attr(test, assert_instr(zip2))] | |
8850 | pub unsafe fn vzip2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { | |
8851 | simd_shuffle8!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) | |
8852 | } | |
8853 | ||
8854 | /// Zip vectors | |
8855 | #[inline] | |
8856 | #[target_feature(enable = "neon")] | |
8857 | #[cfg_attr(test, assert_instr(zip2))] | |
8858 | pub unsafe fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { | |
8859 | simd_shuffle16!(a, b, [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]) | |
8860 | } | |
8861 | ||
8862 | /// Zip vectors | |
8863 | #[inline] | |
8864 | #[target_feature(enable = "neon")] | |
8865 | #[cfg_attr(test, assert_instr(zip2))] | |
8866 | pub unsafe fn vzip2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { | |
8867 | simd_shuffle4!(a, b, [2, 6, 3, 7]) | |
8868 | } | |
8869 | ||
8870 | /// Zip vectors | |
8871 | #[inline] | |
8872 | #[target_feature(enable = "neon")] | |
8873 | #[cfg_attr(test, assert_instr(zip2))] | |
8874 | pub unsafe fn vzip2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { | |
8875 | simd_shuffle8!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) | |
8876 | } | |
8877 | ||
8878 | /// Zip vectors | |
8879 | #[inline] | |
8880 | #[target_feature(enable = "neon")] | |
8881 | #[cfg_attr(test, assert_instr(zip2))] | |
8882 | pub unsafe fn vzip2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { | |
8883 | simd_shuffle2!(a, b, [1, 3]) | |
8884 | } | |
8885 | ||
8886 | /// Zip vectors | |
8887 | #[inline] | |
8888 | #[target_feature(enable = "neon")] | |
8889 | #[cfg_attr(test, assert_instr(zip2))] | |
8890 | pub unsafe fn vzip2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { | |
8891 | simd_shuffle4!(a, b, [2, 6, 3, 7]) | |
8892 | } | |
8893 | ||
8894 | /// Zip vectors | |
8895 | #[inline] | |
8896 | #[target_feature(enable = "neon")] | |
8897 | #[cfg_attr(test, assert_instr(zip2))] | |
8898 | pub unsafe fn vzip2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { | |
8899 | simd_shuffle2!(a, b, [1, 3]) | |
8900 | } | |
8901 | ||
8902 | /// Zip vectors | |
8903 | #[inline] | |
8904 | #[target_feature(enable = "neon")] | |
8905 | #[cfg_attr(test, assert_instr(zip2))] | |
8906 | pub unsafe fn vzip2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { | |
8907 | simd_shuffle8!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) | |
8908 | } | |
8909 | ||
8910 | /// Zip vectors | |
8911 | #[inline] | |
8912 | #[target_feature(enable = "neon")] | |
8913 | #[cfg_attr(test, assert_instr(zip2))] | |
8914 | pub unsafe fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { | |
8915 | simd_shuffle16!(a, b, [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]) | |
8916 | } | |
8917 | ||
8918 | /// Zip vectors | |
8919 | #[inline] | |
8920 | #[target_feature(enable = "neon")] | |
8921 | #[cfg_attr(test, assert_instr(zip2))] | |
8922 | pub unsafe fn vzip2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { | |
8923 | simd_shuffle4!(a, b, [2, 6, 3, 7]) | |
8924 | } | |
8925 | ||
8926 | /// Zip vectors | |
8927 | #[inline] | |
8928 | #[target_feature(enable = "neon")] | |
8929 | #[cfg_attr(test, assert_instr(zip2))] | |
8930 | pub unsafe fn vzip2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { | |
8931 | simd_shuffle8!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) | |
8932 | } | |
8933 | ||
8934 | /// Zip vectors | |
8935 | #[inline] | |
8936 | #[target_feature(enable = "neon")] | |
8937 | #[cfg_attr(test, assert_instr(zip2))] | |
8938 | pub unsafe fn vzip2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { | |
8939 | simd_shuffle2!(a, b, [1, 3]) | |
8940 | } | |
8941 | ||
8942 | /// Zip vectors | |
8943 | #[inline] | |
8944 | #[target_feature(enable = "neon")] | |
8945 | #[cfg_attr(test, assert_instr(zip2))] | |
8946 | pub unsafe fn vzip2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { | |
8947 | simd_shuffle4!(a, b, [2, 6, 3, 7]) | |
8948 | } | |
8949 | ||
8950 | /// Zip vectors | |
8951 | #[inline] | |
8952 | #[target_feature(enable = "neon")] | |
8953 | #[cfg_attr(test, assert_instr(zip2))] | |
8954 | pub unsafe fn vzip2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
8955 | simd_shuffle2!(a, b, [1, 3]) | |
8956 | } | |
8957 | ||
8958 | /// Zip vectors | |
8959 | #[inline] | |
8960 | #[target_feature(enable = "neon")] | |
8961 | #[cfg_attr(test, assert_instr(zip2))] | |
8962 | pub unsafe fn vzip2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { | |
8963 | simd_shuffle8!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) | |
8964 | } | |
8965 | ||
8966 | /// Zip vectors | |
8967 | #[inline] | |
8968 | #[target_feature(enable = "neon")] | |
8969 | #[cfg_attr(test, assert_instr(zip2))] | |
8970 | pub unsafe fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { | |
8971 | simd_shuffle16!(a, b, [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]) | |
8972 | } | |
8973 | ||
8974 | /// Zip vectors | |
8975 | #[inline] | |
8976 | #[target_feature(enable = "neon")] | |
8977 | #[cfg_attr(test, assert_instr(zip2))] | |
8978 | pub unsafe fn vzip2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { | |
8979 | simd_shuffle4!(a, b, [2, 6, 3, 7]) | |
8980 | } | |
8981 | ||
8982 | /// Zip vectors | |
8983 | #[inline] | |
8984 | #[target_feature(enable = "neon")] | |
8985 | #[cfg_attr(test, assert_instr(zip2))] | |
8986 | pub unsafe fn vzip2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { | |
8987 | simd_shuffle8!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) | |
8988 | } | |
8989 | ||
8990 | /// Zip vectors | |
8991 | #[inline] | |
8992 | #[target_feature(enable = "neon")] | |
8993 | #[cfg_attr(test, assert_instr(zip2))] | |
8994 | pub unsafe fn vzip2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { | |
8995 | simd_shuffle2!(a, b, [1, 3]) | |
8996 | } | |
8997 | ||
8998 | /// Zip vectors | |
8999 | #[inline] | |
9000 | #[target_feature(enable = "neon")] | |
9001 | #[cfg_attr(test, assert_instr(zip2))] | |
9002 | pub unsafe fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
9003 | simd_shuffle2!(a, b, [1, 3]) | |
9004 | } | |
9005 | ||
9006 | /// Zip vectors | |
9007 | #[inline] | |
9008 | #[target_feature(enable = "neon")] | |
9009 | #[cfg_attr(test, assert_instr(zip2))] | |
9010 | pub unsafe fn vzip2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
9011 | simd_shuffle4!(a, b, [2, 6, 3, 7]) | |
9012 | } | |
9013 | ||
9014 | /// Zip vectors | |
9015 | #[inline] | |
9016 | #[target_feature(enable = "neon")] | |
9017 | #[cfg_attr(test, assert_instr(zip2))] | |
9018 | pub unsafe fn vzip2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
9019 | simd_shuffle2!(a, b, [1, 3]) | |
9020 | } | |
9021 | ||
9022 | /// Unzip vectors | |
9023 | #[inline] | |
9024 | #[target_feature(enable = "neon")] | |
9025 | #[cfg_attr(test, assert_instr(uzp1))] | |
9026 | pub unsafe fn vuzp1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { | |
9027 | simd_shuffle8!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) | |
9028 | } | |
9029 | ||
9030 | /// Unzip vectors | |
9031 | #[inline] | |
9032 | #[target_feature(enable = "neon")] | |
9033 | #[cfg_attr(test, assert_instr(uzp1))] | |
9034 | pub unsafe fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { | |
9035 | simd_shuffle16!(a, b, [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]) | |
9036 | } | |
9037 | ||
9038 | /// Unzip vectors | |
9039 | #[inline] | |
9040 | #[target_feature(enable = "neon")] | |
9041 | #[cfg_attr(test, assert_instr(uzp1))] | |
9042 | pub unsafe fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { | |
9043 | simd_shuffle4!(a, b, [0, 2, 4, 6]) | |
9044 | } | |
9045 | ||
9046 | /// Unzip vectors | |
9047 | #[inline] | |
9048 | #[target_feature(enable = "neon")] | |
9049 | #[cfg_attr(test, assert_instr(uzp1))] | |
9050 | pub unsafe fn vuzp1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { | |
9051 | simd_shuffle8!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) | |
9052 | } | |
9053 | ||
9054 | /// Unzip vectors | |
9055 | #[inline] | |
9056 | #[target_feature(enable = "neon")] | |
9057 | #[cfg_attr(test, assert_instr(uzp1))] | |
9058 | pub unsafe fn vuzp1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { | |
9059 | simd_shuffle4!(a, b, [0, 2, 4, 6]) | |
9060 | } | |
9061 | ||
9062 | /// Unzip vectors | |
9063 | #[inline] | |
9064 | #[target_feature(enable = "neon")] | |
9065 | #[cfg_attr(test, assert_instr(uzp1))] | |
9066 | pub unsafe fn vuzp1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { | |
9067 | simd_shuffle8!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) | |
9068 | } | |
9069 | ||
9070 | /// Unzip vectors | |
9071 | #[inline] | |
9072 | #[target_feature(enable = "neon")] | |
9073 | #[cfg_attr(test, assert_instr(uzp1))] | |
9074 | pub unsafe fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { | |
9075 | simd_shuffle16!(a, b, [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]) | |
9076 | } | |
9077 | ||
9078 | /// Unzip vectors | |
9079 | #[inline] | |
9080 | #[target_feature(enable = "neon")] | |
9081 | #[cfg_attr(test, assert_instr(uzp1))] | |
9082 | pub unsafe fn vuzp1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { | |
9083 | simd_shuffle4!(a, b, [0, 2, 4, 6]) | |
9084 | } | |
9085 | ||
9086 | /// Unzip vectors | |
9087 | #[inline] | |
9088 | #[target_feature(enable = "neon")] | |
9089 | #[cfg_attr(test, assert_instr(uzp1))] | |
9090 | pub unsafe fn vuzp1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { | |
9091 | simd_shuffle8!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) | |
9092 | } | |
9093 | ||
9094 | /// Unzip vectors | |
9095 | #[inline] | |
9096 | #[target_feature(enable = "neon")] | |
9097 | #[cfg_attr(test, assert_instr(uzp1))] | |
9098 | pub unsafe fn vuzp1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { | |
9099 | simd_shuffle4!(a, b, [0, 2, 4, 6]) | |
9100 | } | |
9101 | ||
9102 | /// Unzip vectors | |
9103 | #[inline] | |
9104 | #[target_feature(enable = "neon")] | |
9105 | #[cfg_attr(test, assert_instr(uzp1))] | |
9106 | pub unsafe fn vuzp1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { | |
9107 | simd_shuffle8!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) | |
9108 | } | |
9109 | ||
9110 | /// Unzip vectors | |
9111 | #[inline] | |
9112 | #[target_feature(enable = "neon")] | |
9113 | #[cfg_attr(test, assert_instr(uzp1))] | |
9114 | pub unsafe fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { | |
9115 | simd_shuffle16!(a, b, [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]) | |
9116 | } | |
9117 | ||
9118 | /// Unzip vectors | |
9119 | #[inline] | |
9120 | #[target_feature(enable = "neon")] | |
9121 | #[cfg_attr(test, assert_instr(uzp1))] | |
9122 | pub unsafe fn vuzp1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { | |
9123 | simd_shuffle4!(a, b, [0, 2, 4, 6]) | |
9124 | } | |
9125 | ||
9126 | /// Unzip vectors | |
9127 | #[inline] | |
9128 | #[target_feature(enable = "neon")] | |
9129 | #[cfg_attr(test, assert_instr(uzp1))] | |
9130 | pub unsafe fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { | |
9131 | simd_shuffle8!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) | |
9132 | } | |
9133 | ||
9134 | /// Unzip vectors | |
9135 | #[inline] | |
9136 | #[target_feature(enable = "neon")] | |
9137 | #[cfg_attr(test, assert_instr(zip1))] | |
9138 | pub unsafe fn vuzp1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { | |
9139 | simd_shuffle2!(a, b, [0, 2]) | |
9140 | } | |
9141 | ||
9142 | /// Unzip vectors | |
9143 | #[inline] | |
9144 | #[target_feature(enable = "neon")] | |
9145 | #[cfg_attr(test, assert_instr(zip1))] | |
9146 | pub unsafe fn vuzp1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { | |
9147 | simd_shuffle2!(a, b, [0, 2]) | |
9148 | } | |
9149 | ||
9150 | /// Unzip vectors | |
9151 | #[inline] | |
9152 | #[target_feature(enable = "neon")] | |
9153 | #[cfg_attr(test, assert_instr(zip1))] | |
9154 | pub unsafe fn vuzp1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { | |
9155 | simd_shuffle2!(a, b, [0, 2]) | |
9156 | } | |
9157 | ||
9158 | /// Unzip vectors | |
9159 | #[inline] | |
9160 | #[target_feature(enable = "neon")] | |
9161 | #[cfg_attr(test, assert_instr(zip1))] | |
9162 | pub unsafe fn vuzp1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
9163 | simd_shuffle2!(a, b, [0, 2]) | |
9164 | } | |
9165 | ||
9166 | /// Unzip vectors | |
9167 | #[inline] | |
9168 | #[target_feature(enable = "neon")] | |
9169 | #[cfg_attr(test, assert_instr(zip1))] | |
9170 | pub unsafe fn vuzp1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { | |
9171 | simd_shuffle2!(a, b, [0, 2]) | |
9172 | } | |
9173 | ||
9174 | /// Unzip vectors | |
9175 | #[inline] | |
9176 | #[target_feature(enable = "neon")] | |
9177 | #[cfg_attr(test, assert_instr(uzp1))] | |
9178 | pub unsafe fn vuzp1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
9179 | simd_shuffle4!(a, b, [0, 2, 4, 6]) | |
9180 | } | |
9181 | ||
9182 | /// Unzip vectors | |
9183 | #[inline] | |
9184 | #[target_feature(enable = "neon")] | |
9185 | #[cfg_attr(test, assert_instr(zip1))] | |
9186 | pub unsafe fn vuzp1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
9187 | simd_shuffle2!(a, b, [0, 2]) | |
9188 | } | |
9189 | ||
9190 | /// Unzip vectors | |
9191 | #[inline] | |
9192 | #[target_feature(enable = "neon")] | |
9193 | #[cfg_attr(test, assert_instr(zip1))] | |
9194 | pub unsafe fn vuzp1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
9195 | simd_shuffle2!(a, b, [0, 2]) | |
9196 | } | |
9197 | ||
9198 | /// Unzip vectors | |
9199 | #[inline] | |
9200 | #[target_feature(enable = "neon")] | |
9201 | #[cfg_attr(test, assert_instr(uzp2))] | |
9202 | pub unsafe fn vuzp2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { | |
9203 | simd_shuffle8!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) | |
9204 | } | |
9205 | ||
9206 | /// Unzip vectors | |
9207 | #[inline] | |
9208 | #[target_feature(enable = "neon")] | |
9209 | #[cfg_attr(test, assert_instr(uzp2))] | |
9210 | pub unsafe fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { | |
9211 | simd_shuffle16!(a, b, [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]) | |
9212 | } | |
9213 | ||
9214 | /// Unzip vectors | |
9215 | #[inline] | |
9216 | #[target_feature(enable = "neon")] | |
9217 | #[cfg_attr(test, assert_instr(uzp2))] | |
9218 | pub unsafe fn vuzp2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { | |
9219 | simd_shuffle4!(a, b, [1, 3, 5, 7]) | |
9220 | } | |
9221 | ||
9222 | /// Unzip vectors | |
9223 | #[inline] | |
9224 | #[target_feature(enable = "neon")] | |
9225 | #[cfg_attr(test, assert_instr(uzp2))] | |
9226 | pub unsafe fn vuzp2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { | |
9227 | simd_shuffle8!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) | |
9228 | } | |
9229 | ||
9230 | /// Unzip vectors | |
9231 | #[inline] | |
9232 | #[target_feature(enable = "neon")] | |
9233 | #[cfg_attr(test, assert_instr(uzp2))] | |
9234 | pub unsafe fn vuzp2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { | |
9235 | simd_shuffle4!(a, b, [1, 3, 5, 7]) | |
9236 | } | |
9237 | ||
9238 | /// Unzip vectors | |
9239 | #[inline] | |
9240 | #[target_feature(enable = "neon")] | |
9241 | #[cfg_attr(test, assert_instr(uzp2))] | |
9242 | pub unsafe fn vuzp2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { | |
9243 | simd_shuffle8!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) | |
9244 | } | |
9245 | ||
9246 | /// Unzip vectors | |
9247 | #[inline] | |
9248 | #[target_feature(enable = "neon")] | |
9249 | #[cfg_attr(test, assert_instr(uzp2))] | |
9250 | pub unsafe fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { | |
9251 | simd_shuffle16!(a, b, [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]) | |
9252 | } | |
9253 | ||
9254 | /// Unzip vectors | |
9255 | #[inline] | |
9256 | #[target_feature(enable = "neon")] | |
9257 | #[cfg_attr(test, assert_instr(uzp2))] | |
9258 | pub unsafe fn vuzp2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { | |
9259 | simd_shuffle4!(a, b, [1, 3, 5, 7]) | |
9260 | } | |
9261 | ||
9262 | /// Unzip vectors | |
9263 | #[inline] | |
9264 | #[target_feature(enable = "neon")] | |
9265 | #[cfg_attr(test, assert_instr(uzp2))] | |
9266 | pub unsafe fn vuzp2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { | |
9267 | simd_shuffle8!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) | |
9268 | } | |
9269 | ||
9270 | /// Unzip vectors | |
9271 | #[inline] | |
9272 | #[target_feature(enable = "neon")] | |
9273 | #[cfg_attr(test, assert_instr(uzp2))] | |
9274 | pub unsafe fn vuzp2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { | |
9275 | simd_shuffle4!(a, b, [1, 3, 5, 7]) | |
9276 | } | |
9277 | ||
9278 | /// Unzip vectors | |
9279 | #[inline] | |
9280 | #[target_feature(enable = "neon")] | |
9281 | #[cfg_attr(test, assert_instr(uzp2))] | |
9282 | pub unsafe fn vuzp2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { | |
9283 | simd_shuffle8!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) | |
9284 | } | |
9285 | ||
9286 | /// Unzip vectors | |
9287 | #[inline] | |
9288 | #[target_feature(enable = "neon")] | |
9289 | #[cfg_attr(test, assert_instr(uzp2))] | |
9290 | pub unsafe fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { | |
9291 | simd_shuffle16!(a, b, [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]) | |
9292 | } | |
9293 | ||
9294 | /// Unzip vectors | |
9295 | #[inline] | |
9296 | #[target_feature(enable = "neon")] | |
9297 | #[cfg_attr(test, assert_instr(uzp2))] | |
9298 | pub unsafe fn vuzp2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { | |
9299 | simd_shuffle4!(a, b, [1, 3, 5, 7]) | |
9300 | } | |
9301 | ||
9302 | /// Unzip vectors | |
9303 | #[inline] | |
9304 | #[target_feature(enable = "neon")] | |
9305 | #[cfg_attr(test, assert_instr(uzp2))] | |
9306 | pub unsafe fn vuzp2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { | |
9307 | simd_shuffle8!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) | |
9308 | } | |
9309 | ||
9310 | /// Unzip vectors | |
9311 | #[inline] | |
9312 | #[target_feature(enable = "neon")] | |
9313 | #[cfg_attr(test, assert_instr(zip2))] | |
9314 | pub unsafe fn vuzp2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { | |
9315 | simd_shuffle2!(a, b, [1, 3]) | |
9316 | } | |
9317 | ||
9318 | /// Unzip vectors | |
9319 | #[inline] | |
9320 | #[target_feature(enable = "neon")] | |
9321 | #[cfg_attr(test, assert_instr(zip2))] | |
9322 | pub unsafe fn vuzp2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { | |
9323 | simd_shuffle2!(a, b, [1, 3]) | |
9324 | } | |
9325 | ||
9326 | /// Unzip vectors | |
9327 | #[inline] | |
9328 | #[target_feature(enable = "neon")] | |
9329 | #[cfg_attr(test, assert_instr(zip2))] | |
9330 | pub unsafe fn vuzp2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { | |
9331 | simd_shuffle2!(a, b, [1, 3]) | |
9332 | } | |
9333 | ||
9334 | /// Unzip vectors | |
9335 | #[inline] | |
9336 | #[target_feature(enable = "neon")] | |
9337 | #[cfg_attr(test, assert_instr(zip2))] | |
9338 | pub unsafe fn vuzp2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { | |
9339 | simd_shuffle2!(a, b, [1, 3]) | |
9340 | } | |
9341 | ||
9342 | /// Unzip vectors | |
9343 | #[inline] | |
9344 | #[target_feature(enable = "neon")] | |
9345 | #[cfg_attr(test, assert_instr(zip2))] | |
9346 | pub unsafe fn vuzp2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { | |
9347 | simd_shuffle2!(a, b, [1, 3]) | |
9348 | } | |
9349 | ||
9350 | /// Unzip vectors | |
9351 | #[inline] | |
9352 | #[target_feature(enable = "neon")] | |
9353 | #[cfg_attr(test, assert_instr(uzp2))] | |
9354 | pub unsafe fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
9355 | simd_shuffle4!(a, b, [1, 3, 5, 7]) | |
9356 | } | |
9357 | ||
9358 | /// Unzip vectors | |
9359 | #[inline] | |
9360 | #[target_feature(enable = "neon")] | |
9361 | #[cfg_attr(test, assert_instr(zip2))] | |
9362 | pub unsafe fn vuzp2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { | |
9363 | simd_shuffle2!(a, b, [1, 3]) | |
9364 | } | |
9365 | ||
9366 | /// Unzip vectors | |
9367 | #[inline] | |
9368 | #[target_feature(enable = "neon")] | |
9369 | #[cfg_attr(test, assert_instr(zip2))] | |
9370 | pub unsafe fn vuzp2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
9371 | simd_shuffle2!(a, b, [1, 3]) | |
9372 | } | |
9373 | ||
9374 | /// Unsigned Absolute difference and Accumulate Long | |
9375 | #[inline] | |
9376 | #[target_feature(enable = "neon")] | |
9377 | #[cfg_attr(test, assert_instr(uabal))] | |
9378 | pub unsafe fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { | |
9379 | let d: uint8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
9380 | let e: uint8x8_t = simd_shuffle8!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); | |
9381 | let f: uint8x8_t = vabd_u8(d, e); | |
9382 | simd_add(a, simd_cast(f)) | |
9383 | } | |
9384 | ||
9385 | /// Unsigned Absolute difference and Accumulate Long | |
9386 | #[inline] | |
9387 | #[target_feature(enable = "neon")] | |
9388 | #[cfg_attr(test, assert_instr(uabal))] | |
9389 | pub unsafe fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { | |
9390 | let d: uint16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
9391 | let e: uint16x4_t = simd_shuffle4!(c, c, [4, 5, 6, 7]); | |
9392 | let f: uint16x4_t = vabd_u16(d, e); | |
9393 | simd_add(a, simd_cast(f)) | |
9394 | } | |
9395 | ||
9396 | /// Unsigned Absolute difference and Accumulate Long | |
9397 | #[inline] | |
9398 | #[target_feature(enable = "neon")] | |
9399 | #[cfg_attr(test, assert_instr(uabal))] | |
9400 | pub unsafe fn vabal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { | |
9401 | let d: uint32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
9402 | let e: uint32x2_t = simd_shuffle2!(c, c, [2, 3]); | |
9403 | let f: uint32x2_t = vabd_u32(d, e); | |
9404 | simd_add(a, simd_cast(f)) | |
9405 | } | |
9406 | ||
9407 | /// Signed Absolute difference and Accumulate Long | |
9408 | #[inline] | |
9409 | #[target_feature(enable = "neon")] | |
9410 | #[cfg_attr(test, assert_instr(sabal))] | |
9411 | pub unsafe fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { | |
9412 | let d: int8x8_t = simd_shuffle8!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); | |
9413 | let e: int8x8_t = simd_shuffle8!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); | |
9414 | let f: int8x8_t = vabd_s8(d, e); | |
9415 | let f: uint8x8_t = simd_cast(f); | |
9416 | simd_add(a, simd_cast(f)) | |
9417 | } | |
9418 | ||
9419 | /// Signed Absolute difference and Accumulate Long | |
9420 | #[inline] | |
9421 | #[target_feature(enable = "neon")] | |
9422 | #[cfg_attr(test, assert_instr(sabal))] | |
9423 | pub unsafe fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { | |
9424 | let d: int16x4_t = simd_shuffle4!(b, b, [4, 5, 6, 7]); | |
9425 | let e: int16x4_t = simd_shuffle4!(c, c, [4, 5, 6, 7]); | |
9426 | let f: int16x4_t = vabd_s16(d, e); | |
9427 | let f: uint16x4_t = simd_cast(f); | |
9428 | simd_add(a, simd_cast(f)) | |
9429 | } | |
9430 | ||
9431 | /// Signed Absolute difference and Accumulate Long | |
9432 | #[inline] | |
9433 | #[target_feature(enable = "neon")] | |
9434 | #[cfg_attr(test, assert_instr(sabal))] | |
9435 | pub unsafe fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { | |
9436 | let d: int32x2_t = simd_shuffle2!(b, b, [2, 3]); | |
9437 | let e: int32x2_t = simd_shuffle2!(c, c, [2, 3]); | |
9438 | let f: int32x2_t = vabd_s32(d, e); | |
9439 | let f: uint32x2_t = simd_cast(f); | |
9440 | simd_add(a, simd_cast(f)) | |
9441 | } | |
9442 | ||
9443 | /// Singned saturating Absolute value | |
9444 | #[inline] | |
9445 | #[target_feature(enable = "neon")] | |
9446 | #[cfg_attr(test, assert_instr(sqabs))] | |
9447 | pub unsafe fn vqabs_s64(a: int64x1_t) -> int64x1_t { | |
9448 | #[allow(improper_ctypes)] | |
9449 | extern "C" { | |
9450 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqabs.v1i64")] | |
9451 | fn vqabs_s64_(a: int64x1_t) -> int64x1_t; | |
9452 | } | |
9453 | vqabs_s64_(a) | |
9454 | } | |
9455 | ||
9456 | /// Singned saturating Absolute value | |
9457 | #[inline] | |
9458 | #[target_feature(enable = "neon")] | |
9459 | #[cfg_attr(test, assert_instr(sqabs))] | |
9460 | pub unsafe fn vqabsq_s64(a: int64x2_t) -> int64x2_t { | |
9461 | #[allow(improper_ctypes)] | |
9462 | extern "C" { | |
9463 | #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sqabs.v2i64")] | |
9464 | fn vqabsq_s64_(a: int64x2_t) -> int64x2_t; | |
9465 | } | |
9466 | vqabsq_s64_(a) | |
9467 | } | |
9468 | ||
9469 | #[cfg(test)] | |
9470 | mod test { | |
9471 | use super::*; | |
9472 | use crate::core_arch::simd::*; | |
9473 | use std::mem::transmute; | |
9474 | use stdarch_test::simd_test; | |
9475 | ||
9476 | #[simd_test(enable = "neon")] | |
9477 | unsafe fn test_vabd_f64() { | |
9478 | let a: f64 = 1.0; | |
9479 | let b: f64 = 9.0; | |
9480 | let e: f64 = 8.0; | |
9481 | let r: f64 = transmute(vabd_f64(transmute(a), transmute(b))); | |
9482 | assert_eq!(r, e); | |
9483 | } | |
9484 | ||
9485 | #[simd_test(enable = "neon")] | |
9486 | unsafe fn test_vabdq_f64() { | |
9487 | let a: f64x2 = f64x2::new(1.0, 2.0); | |
9488 | let b: f64x2 = f64x2::new(9.0, 3.0); | |
9489 | let e: f64x2 = f64x2::new(8.0, 1.0); | |
9490 | let r: f64x2 = transmute(vabdq_f64(transmute(a), transmute(b))); | |
9491 | assert_eq!(r, e); | |
9492 | } | |
9493 | ||
9494 | #[simd_test(enable = "neon")] | |
9495 | unsafe fn test_vabdl_high_u8() { | |
9496 | let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
9497 | let b: u8x16 = u8x16::new(10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10); | |
9498 | let e: u16x8 = u16x8::new(1, 0, 1, 2, 3, 4, 5, 6); | |
9499 | let r: u16x8 = transmute(vabdl_high_u8(transmute(a), transmute(b))); | |
9500 | assert_eq!(r, e); | |
9501 | } | |
9502 | ||
9503 | #[simd_test(enable = "neon")] | |
9504 | unsafe fn test_vabdl_high_u16() { | |
9505 | let a: u16x8 = u16x8::new(1, 2, 3, 4, 8, 9, 11, 12); | |
9506 | let b: u16x8 = u16x8::new(10, 10, 10, 10, 10, 10, 10, 10); | |
9507 | let e: u32x4 = u32x4::new(2, 1, 1, 2); | |
9508 | let r: u32x4 = transmute(vabdl_high_u16(transmute(a), transmute(b))); | |
9509 | assert_eq!(r, e); | |
9510 | } | |
9511 | ||
9512 | #[simd_test(enable = "neon")] | |
9513 | unsafe fn test_vabdl_high_u32() { | |
9514 | let a: u32x4 = u32x4::new(1, 2, 3, 4); | |
9515 | let b: u32x4 = u32x4::new(10, 10, 10, 10); | |
9516 | let e: u64x2 = u64x2::new(7, 6); | |
9517 | let r: u64x2 = transmute(vabdl_high_u32(transmute(a), transmute(b))); | |
9518 | assert_eq!(r, e); | |
9519 | } | |
9520 | ||
9521 | #[simd_test(enable = "neon")] | |
9522 | unsafe fn test_vabdl_high_s8() { | |
9523 | let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
9524 | let b: i8x16 = i8x16::new(10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10); | |
9525 | let e: i16x8 = i16x8::new(1, 0, 1, 2, 3, 4, 5, 6); | |
9526 | let r: i16x8 = transmute(vabdl_high_s8(transmute(a), transmute(b))); | |
9527 | assert_eq!(r, e); | |
9528 | } | |
9529 | ||
9530 | #[simd_test(enable = "neon")] | |
9531 | unsafe fn test_vabdl_high_s16() { | |
9532 | let a: i16x8 = i16x8::new(1, 2, 3, 4, 9, 10, 11, 12); | |
9533 | let b: i16x8 = i16x8::new(10, 10, 10, 10, 10, 10, 10, 10); | |
9534 | let e: i32x4 = i32x4::new(1, 0, 1, 2); | |
9535 | let r: i32x4 = transmute(vabdl_high_s16(transmute(a), transmute(b))); | |
9536 | assert_eq!(r, e); | |
9537 | } | |
9538 | ||
9539 | #[simd_test(enable = "neon")] | |
9540 | unsafe fn test_vabdl_high_s32() { | |
9541 | let a: i32x4 = i32x4::new(1, 2, 3, 4); | |
9542 | let b: i32x4 = i32x4::new(10, 10, 10, 10); | |
9543 | let e: i64x2 = i64x2::new(7, 6); | |
9544 | let r: i64x2 = transmute(vabdl_high_s32(transmute(a), transmute(b))); | |
9545 | assert_eq!(r, e); | |
9546 | } | |
9547 | ||
9548 | #[simd_test(enable = "neon")] | |
9549 | unsafe fn test_vceq_u64() { | |
9550 | let a: u64x1 = u64x1::new(0); | |
9551 | let b: u64x1 = u64x1::new(0); | |
9552 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9553 | let r: u64x1 = transmute(vceq_u64(transmute(a), transmute(b))); | |
9554 | assert_eq!(r, e); | |
9555 | ||
9556 | let a: u64x1 = u64x1::new(0); | |
9557 | let b: u64x1 = u64x1::new(0); | |
9558 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9559 | let r: u64x1 = transmute(vceq_u64(transmute(a), transmute(b))); | |
9560 | assert_eq!(r, e); | |
9561 | } | |
9562 | ||
9563 | #[simd_test(enable = "neon")] | |
9564 | unsafe fn test_vceqq_u64() { | |
9565 | let a: u64x2 = u64x2::new(0, 0x01); | |
9566 | let b: u64x2 = u64x2::new(0, 0x01); | |
9567 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9568 | let r: u64x2 = transmute(vceqq_u64(transmute(a), transmute(b))); | |
9569 | assert_eq!(r, e); | |
9570 | ||
9571 | let a: u64x2 = u64x2::new(0, 0); | |
9572 | let b: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9573 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); | |
9574 | let r: u64x2 = transmute(vceqq_u64(transmute(a), transmute(b))); | |
9575 | assert_eq!(r, e); | |
9576 | } | |
9577 | ||
9578 | #[simd_test(enable = "neon")] | |
9579 | unsafe fn test_vceq_s64() { | |
9580 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
9581 | let b: i64x1 = i64x1::new(-9223372036854775808); | |
9582 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9583 | let r: u64x1 = transmute(vceq_s64(transmute(a), transmute(b))); | |
9584 | assert_eq!(r, e); | |
9585 | ||
9586 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
9587 | let b: i64x1 = i64x1::new(-9223372036854775808); | |
9588 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9589 | let r: u64x1 = transmute(vceq_s64(transmute(a), transmute(b))); | |
9590 | assert_eq!(r, e); | |
9591 | } | |
9592 | ||
9593 | #[simd_test(enable = "neon")] | |
9594 | unsafe fn test_vceqq_s64() { | |
9595 | let a: i64x2 = i64x2::new(-9223372036854775808, 0x01); | |
9596 | let b: i64x2 = i64x2::new(-9223372036854775808, 0x01); | |
9597 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9598 | let r: u64x2 = transmute(vceqq_s64(transmute(a), transmute(b))); | |
9599 | assert_eq!(r, e); | |
9600 | ||
9601 | let a: i64x2 = i64x2::new(-9223372036854775808, -9223372036854775808); | |
9602 | let b: i64x2 = i64x2::new(-9223372036854775808, 0x7F_FF_FF_FF_FF_FF_FF_FF); | |
9603 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); | |
9604 | let r: u64x2 = transmute(vceqq_s64(transmute(a), transmute(b))); | |
9605 | assert_eq!(r, e); | |
9606 | } | |
9607 | ||
9608 | #[simd_test(enable = "neon")] | |
9609 | unsafe fn test_vceq_p64() { | |
9610 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
9611 | let b: i64x1 = i64x1::new(-9223372036854775808); | |
9612 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9613 | let r: u64x1 = transmute(vceq_p64(transmute(a), transmute(b))); | |
9614 | assert_eq!(r, e); | |
9615 | ||
9616 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
9617 | let b: i64x1 = i64x1::new(-9223372036854775808); | |
9618 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9619 | let r: u64x1 = transmute(vceq_p64(transmute(a), transmute(b))); | |
9620 | assert_eq!(r, e); | |
9621 | } | |
9622 | ||
9623 | #[simd_test(enable = "neon")] | |
9624 | unsafe fn test_vceqq_p64() { | |
9625 | let a: i64x2 = i64x2::new(-9223372036854775808, 0x01); | |
9626 | let b: i64x2 = i64x2::new(-9223372036854775808, 0x01); | |
9627 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9628 | let r: u64x2 = transmute(vceqq_p64(transmute(a), transmute(b))); | |
9629 | assert_eq!(r, e); | |
9630 | ||
9631 | let a: i64x2 = i64x2::new(-9223372036854775808, -9223372036854775808); | |
9632 | let b: i64x2 = i64x2::new(-9223372036854775808, 0x7F_FF_FF_FF_FF_FF_FF_FF); | |
9633 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); | |
9634 | let r: u64x2 = transmute(vceqq_p64(transmute(a), transmute(b))); | |
9635 | assert_eq!(r, e); | |
9636 | } | |
9637 | ||
9638 | #[simd_test(enable = "neon")] | |
9639 | unsafe fn test_vceq_f64() { | |
9640 | let a: f64 = 1.2; | |
9641 | let b: f64 = 1.2; | |
9642 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9643 | let r: u64x1 = transmute(vceq_f64(transmute(a), transmute(b))); | |
9644 | assert_eq!(r, e); | |
9645 | } | |
9646 | ||
9647 | #[simd_test(enable = "neon")] | |
9648 | unsafe fn test_vceqq_f64() { | |
9649 | let a: f64x2 = f64x2::new(1.2, 3.4); | |
9650 | let b: f64x2 = f64x2::new(1.2, 3.4); | |
9651 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9652 | let r: u64x2 = transmute(vceqq_f64(transmute(a), transmute(b))); | |
9653 | assert_eq!(r, e); | |
9654 | } | |
9655 | ||
9656 | #[simd_test(enable = "neon")] | |
9657 | unsafe fn test_vceqz_s8() { | |
9658 | let a: i8x8 = i8x8::new(-128, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); | |
9659 | let e: u8x8 = u8x8::new(0, 0xFF, 0, 0, 0, 0, 0, 0); | |
9660 | let r: u8x8 = transmute(vceqz_s8(transmute(a))); | |
9661 | assert_eq!(r, e); | |
9662 | } | |
9663 | ||
9664 | #[simd_test(enable = "neon")] | |
9665 | unsafe fn test_vceqzq_s8() { | |
9666 | let a: i8x16 = i8x16::new(-128, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x7F); | |
9667 | let e: u8x16 = u8x16::new(0, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
9668 | let r: u8x16 = transmute(vceqzq_s8(transmute(a))); | |
9669 | assert_eq!(r, e); | |
9670 | } | |
9671 | ||
9672 | #[simd_test(enable = "neon")] | |
9673 | unsafe fn test_vceqz_s16() { | |
9674 | let a: i16x4 = i16x4::new(-32768, 0x00, 0x01, 0x02); | |
9675 | let e: u16x4 = u16x4::new(0, 0xFF_FF, 0, 0); | |
9676 | let r: u16x4 = transmute(vceqz_s16(transmute(a))); | |
9677 | assert_eq!(r, e); | |
9678 | } | |
9679 | ||
9680 | #[simd_test(enable = "neon")] | |
9681 | unsafe fn test_vceqzq_s16() { | |
9682 | let a: i16x8 = i16x8::new(-32768, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); | |
9683 | let e: u16x8 = u16x8::new(0, 0xFF_FF, 0, 0, 0, 0, 0, 0); | |
9684 | let r: u16x8 = transmute(vceqzq_s16(transmute(a))); | |
9685 | assert_eq!(r, e); | |
9686 | } | |
9687 | ||
9688 | #[simd_test(enable = "neon")] | |
9689 | unsafe fn test_vceqz_s32() { | |
9690 | let a: i32x2 = i32x2::new(-2147483648, 0x00); | |
9691 | let e: u32x2 = u32x2::new(0, 0xFF_FF_FF_FF); | |
9692 | let r: u32x2 = transmute(vceqz_s32(transmute(a))); | |
9693 | assert_eq!(r, e); | |
9694 | } | |
9695 | ||
9696 | #[simd_test(enable = "neon")] | |
9697 | unsafe fn test_vceqzq_s32() { | |
9698 | let a: i32x4 = i32x4::new(-2147483648, 0x00, 0x01, 0x02); | |
9699 | let e: u32x4 = u32x4::new(0, 0xFF_FF_FF_FF, 0, 0); | |
9700 | let r: u32x4 = transmute(vceqzq_s32(transmute(a))); | |
9701 | assert_eq!(r, e); | |
9702 | } | |
9703 | ||
9704 | #[simd_test(enable = "neon")] | |
9705 | unsafe fn test_vceqz_s64() { | |
9706 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
9707 | let e: u64x1 = u64x1::new(0); | |
9708 | let r: u64x1 = transmute(vceqz_s64(transmute(a))); | |
9709 | assert_eq!(r, e); | |
9710 | } | |
9711 | ||
9712 | #[simd_test(enable = "neon")] | |
9713 | unsafe fn test_vceqzq_s64() { | |
9714 | let a: i64x2 = i64x2::new(-9223372036854775808, 0x00); | |
9715 | let e: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9716 | let r: u64x2 = transmute(vceqzq_s64(transmute(a))); | |
9717 | assert_eq!(r, e); | |
9718 | } | |
9719 | ||
9720 | #[simd_test(enable = "neon")] | |
9721 | unsafe fn test_vceqz_p8() { | |
9722 | let a: i8x8 = i8x8::new(-128, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); | |
9723 | let e: u8x8 = u8x8::new(0, 0xFF, 0, 0, 0, 0, 0, 0); | |
9724 | let r: u8x8 = transmute(vceqz_p8(transmute(a))); | |
9725 | assert_eq!(r, e); | |
9726 | } | |
9727 | ||
9728 | #[simd_test(enable = "neon")] | |
9729 | unsafe fn test_vceqzq_p8() { | |
9730 | let a: i8x16 = i8x16::new(-128, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x7F); | |
9731 | let e: u8x16 = u8x16::new(0, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
9732 | let r: u8x16 = transmute(vceqzq_p8(transmute(a))); | |
9733 | assert_eq!(r, e); | |
9734 | } | |
9735 | ||
9736 | #[simd_test(enable = "neon")] | |
9737 | unsafe fn test_vceqz_p64() { | |
9738 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
9739 | let e: u64x1 = u64x1::new(0); | |
9740 | let r: u64x1 = transmute(vceqz_p64(transmute(a))); | |
9741 | assert_eq!(r, e); | |
9742 | } | |
9743 | ||
9744 | #[simd_test(enable = "neon")] | |
9745 | unsafe fn test_vceqzq_p64() { | |
9746 | let a: i64x2 = i64x2::new(-9223372036854775808, 0x00); | |
9747 | let e: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9748 | let r: u64x2 = transmute(vceqzq_p64(transmute(a))); | |
9749 | assert_eq!(r, e); | |
9750 | } | |
9751 | ||
9752 | #[simd_test(enable = "neon")] | |
9753 | unsafe fn test_vceqz_u8() { | |
9754 | let a: u8x8 = u8x8::new(0, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); | |
9755 | let e: u8x8 = u8x8::new(0xFF, 0xFF, 0, 0, 0, 0, 0, 0); | |
9756 | let r: u8x8 = transmute(vceqz_u8(transmute(a))); | |
9757 | assert_eq!(r, e); | |
9758 | } | |
9759 | ||
9760 | #[simd_test(enable = "neon")] | |
9761 | unsafe fn test_vceqzq_u8() { | |
9762 | let a: u8x16 = u8x16::new(0, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0xFF); | |
9763 | let e: u8x16 = u8x16::new(0xFF, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
9764 | let r: u8x16 = transmute(vceqzq_u8(transmute(a))); | |
9765 | assert_eq!(r, e); | |
9766 | } | |
9767 | ||
9768 | #[simd_test(enable = "neon")] | |
9769 | unsafe fn test_vceqz_u16() { | |
9770 | let a: u16x4 = u16x4::new(0, 0x00, 0x01, 0x02); | |
9771 | let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0, 0); | |
9772 | let r: u16x4 = transmute(vceqz_u16(transmute(a))); | |
9773 | assert_eq!(r, e); | |
9774 | } | |
9775 | ||
9776 | #[simd_test(enable = "neon")] | |
9777 | unsafe fn test_vceqzq_u16() { | |
9778 | let a: u16x8 = u16x8::new(0, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); | |
9779 | let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0, 0, 0, 0, 0, 0); | |
9780 | let r: u16x8 = transmute(vceqzq_u16(transmute(a))); | |
9781 | assert_eq!(r, e); | |
9782 | } | |
9783 | ||
9784 | #[simd_test(enable = "neon")] | |
9785 | unsafe fn test_vceqz_u32() { | |
9786 | let a: u32x2 = u32x2::new(0, 0x00); | |
9787 | let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); | |
9788 | let r: u32x2 = transmute(vceqz_u32(transmute(a))); | |
9789 | assert_eq!(r, e); | |
9790 | } | |
9791 | ||
9792 | #[simd_test(enable = "neon")] | |
9793 | unsafe fn test_vceqzq_u32() { | |
9794 | let a: u32x4 = u32x4::new(0, 0x00, 0x01, 0x02); | |
9795 | let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0, 0); | |
9796 | let r: u32x4 = transmute(vceqzq_u32(transmute(a))); | |
9797 | assert_eq!(r, e); | |
9798 | } | |
9799 | ||
9800 | #[simd_test(enable = "neon")] | |
9801 | unsafe fn test_vceqz_u64() { | |
9802 | let a: u64x1 = u64x1::new(0); | |
9803 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9804 | let r: u64x1 = transmute(vceqz_u64(transmute(a))); | |
9805 | assert_eq!(r, e); | |
9806 | } | |
9807 | ||
9808 | #[simd_test(enable = "neon")] | |
9809 | unsafe fn test_vceqzq_u64() { | |
9810 | let a: u64x2 = u64x2::new(0, 0x00); | |
9811 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9812 | let r: u64x2 = transmute(vceqzq_u64(transmute(a))); | |
9813 | assert_eq!(r, e); | |
9814 | } | |
9815 | ||
9816 | #[simd_test(enable = "neon")] | |
9817 | unsafe fn test_vceqz_f32() { | |
9818 | let a: f32x2 = f32x2::new(0.0, 1.2); | |
9819 | let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0); | |
9820 | let r: u32x2 = transmute(vceqz_f32(transmute(a))); | |
9821 | assert_eq!(r, e); | |
9822 | } | |
9823 | ||
9824 | #[simd_test(enable = "neon")] | |
9825 | unsafe fn test_vceqzq_f32() { | |
9826 | let a: f32x4 = f32x4::new(0.0, 1.2, 3.4, 5.6); | |
9827 | let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0, 0, 0); | |
9828 | let r: u32x4 = transmute(vceqzq_f32(transmute(a))); | |
9829 | assert_eq!(r, e); | |
9830 | } | |
9831 | ||
9832 | #[simd_test(enable = "neon")] | |
9833 | unsafe fn test_vceqz_f64() { | |
9834 | let a: f64 = 0.0; | |
9835 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9836 | let r: u64x1 = transmute(vceqz_f64(transmute(a))); | |
9837 | assert_eq!(r, e); | |
9838 | } | |
9839 | ||
9840 | #[simd_test(enable = "neon")] | |
9841 | unsafe fn test_vceqzq_f64() { | |
9842 | let a: f64x2 = f64x2::new(0.0, 1.2); | |
9843 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); | |
9844 | let r: u64x2 = transmute(vceqzq_f64(transmute(a))); | |
9845 | assert_eq!(r, e); | |
9846 | } | |
9847 | ||
9848 | #[simd_test(enable = "neon")] | |
9849 | unsafe fn test_vtst_s64() { | |
9850 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
9851 | let b: i64x1 = i64x1::new(-9223372036854775808); | |
9852 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9853 | let r: u64x1 = transmute(vtst_s64(transmute(a), transmute(b))); | |
9854 | assert_eq!(r, e); | |
9855 | } | |
9856 | ||
9857 | #[simd_test(enable = "neon")] | |
9858 | unsafe fn test_vtstq_s64() { | |
9859 | let a: i64x2 = i64x2::new(-9223372036854775808, 0x00); | |
9860 | let b: i64x2 = i64x2::new(-9223372036854775808, 0x00); | |
9861 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); | |
9862 | let r: u64x2 = transmute(vtstq_s64(transmute(a), transmute(b))); | |
9863 | assert_eq!(r, e); | |
9864 | } | |
9865 | ||
9866 | #[simd_test(enable = "neon")] | |
9867 | unsafe fn test_vtst_p64() { | |
9868 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
9869 | let b: i64x1 = i64x1::new(-9223372036854775808); | |
9870 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9871 | let r: u64x1 = transmute(vtst_p64(transmute(a), transmute(b))); | |
9872 | assert_eq!(r, e); | |
9873 | } | |
9874 | ||
9875 | #[simd_test(enable = "neon")] | |
9876 | unsafe fn test_vtstq_p64() { | |
9877 | let a: i64x2 = i64x2::new(-9223372036854775808, 0x00); | |
9878 | let b: i64x2 = i64x2::new(-9223372036854775808, 0x00); | |
9879 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); | |
9880 | let r: u64x2 = transmute(vtstq_p64(transmute(a), transmute(b))); | |
9881 | assert_eq!(r, e); | |
9882 | } | |
9883 | ||
9884 | #[simd_test(enable = "neon")] | |
9885 | unsafe fn test_vtst_u64() { | |
9886 | let a: u64x1 = u64x1::new(0); | |
9887 | let b: u64x1 = u64x1::new(0); | |
9888 | let e: u64x1 = u64x1::new(0); | |
9889 | let r: u64x1 = transmute(vtst_u64(transmute(a), transmute(b))); | |
9890 | assert_eq!(r, e); | |
9891 | } | |
9892 | ||
9893 | #[simd_test(enable = "neon")] | |
9894 | unsafe fn test_vtstq_u64() { | |
9895 | let a: u64x2 = u64x2::new(0, 0x00); | |
9896 | let b: u64x2 = u64x2::new(0, 0x00); | |
9897 | let e: u64x2 = u64x2::new(0, 0); | |
9898 | let r: u64x2 = transmute(vtstq_u64(transmute(a), transmute(b))); | |
9899 | assert_eq!(r, e); | |
9900 | } | |
9901 | ||
9902 | #[simd_test(enable = "neon")] | |
9903 | unsafe fn test_vabs_f64() { | |
9904 | let a: f64 = -0.1; | |
9905 | let e: f64 = 0.1; | |
9906 | let r: f64 = transmute(vabs_f64(transmute(a))); | |
9907 | assert_eq!(r, e); | |
9908 | } | |
9909 | ||
9910 | #[simd_test(enable = "neon")] | |
9911 | unsafe fn test_vabsq_f64() { | |
9912 | let a: f64x2 = f64x2::new(-0.1, -2.2); | |
9913 | let e: f64x2 = f64x2::new(0.1, 2.2); | |
9914 | let r: f64x2 = transmute(vabsq_f64(transmute(a))); | |
9915 | assert_eq!(r, e); | |
9916 | } | |
9917 | ||
9918 | #[simd_test(enable = "neon")] | |
9919 | unsafe fn test_vcgt_s64() { | |
9920 | let a: i64x1 = i64x1::new(1); | |
9921 | let b: i64x1 = i64x1::new(0); | |
9922 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9923 | let r: u64x1 = transmute(vcgt_s64(transmute(a), transmute(b))); | |
9924 | assert_eq!(r, e); | |
9925 | } | |
9926 | ||
9927 | #[simd_test(enable = "neon")] | |
9928 | unsafe fn test_vcgtq_s64() { | |
9929 | let a: i64x2 = i64x2::new(1, 2); | |
9930 | let b: i64x2 = i64x2::new(0, 1); | |
9931 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9932 | let r: u64x2 = transmute(vcgtq_s64(transmute(a), transmute(b))); | |
9933 | assert_eq!(r, e); | |
9934 | } | |
9935 | ||
9936 | #[simd_test(enable = "neon")] | |
9937 | unsafe fn test_vcgt_u64() { | |
9938 | let a: u64x1 = u64x1::new(1); | |
9939 | let b: u64x1 = u64x1::new(0); | |
9940 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9941 | let r: u64x1 = transmute(vcgt_u64(transmute(a), transmute(b))); | |
9942 | assert_eq!(r, e); | |
9943 | } | |
9944 | ||
9945 | #[simd_test(enable = "neon")] | |
9946 | unsafe fn test_vcgtq_u64() { | |
9947 | let a: u64x2 = u64x2::new(1, 2); | |
9948 | let b: u64x2 = u64x2::new(0, 1); | |
9949 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9950 | let r: u64x2 = transmute(vcgtq_u64(transmute(a), transmute(b))); | |
9951 | assert_eq!(r, e); | |
9952 | } | |
9953 | ||
9954 | #[simd_test(enable = "neon")] | |
9955 | unsafe fn test_vcgt_f64() { | |
9956 | let a: f64 = 1.2; | |
9957 | let b: f64 = 0.1; | |
9958 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9959 | let r: u64x1 = transmute(vcgt_f64(transmute(a), transmute(b))); | |
9960 | assert_eq!(r, e); | |
9961 | } | |
9962 | ||
9963 | #[simd_test(enable = "neon")] | |
9964 | unsafe fn test_vcgtq_f64() { | |
9965 | let a: f64x2 = f64x2::new(1.2, 2.3); | |
9966 | let b: f64x2 = f64x2::new(0.1, 1.2); | |
9967 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9968 | let r: u64x2 = transmute(vcgtq_f64(transmute(a), transmute(b))); | |
9969 | assert_eq!(r, e); | |
9970 | } | |
9971 | ||
9972 | #[simd_test(enable = "neon")] | |
9973 | unsafe fn test_vclt_s64() { | |
9974 | let a: i64x1 = i64x1::new(0); | |
9975 | let b: i64x1 = i64x1::new(1); | |
9976 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9977 | let r: u64x1 = transmute(vclt_s64(transmute(a), transmute(b))); | |
9978 | assert_eq!(r, e); | |
9979 | } | |
9980 | ||
9981 | #[simd_test(enable = "neon")] | |
9982 | unsafe fn test_vcltq_s64() { | |
9983 | let a: i64x2 = i64x2::new(0, 1); | |
9984 | let b: i64x2 = i64x2::new(1, 2); | |
9985 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9986 | let r: u64x2 = transmute(vcltq_s64(transmute(a), transmute(b))); | |
9987 | assert_eq!(r, e); | |
9988 | } | |
9989 | ||
9990 | #[simd_test(enable = "neon")] | |
9991 | unsafe fn test_vclt_u64() { | |
9992 | let a: u64x1 = u64x1::new(0); | |
9993 | let b: u64x1 = u64x1::new(1); | |
9994 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
9995 | let r: u64x1 = transmute(vclt_u64(transmute(a), transmute(b))); | |
9996 | assert_eq!(r, e); | |
9997 | } | |
9998 | ||
9999 | #[simd_test(enable = "neon")] | |
10000 | unsafe fn test_vcltq_u64() { | |
10001 | let a: u64x2 = u64x2::new(0, 1); | |
10002 | let b: u64x2 = u64x2::new(1, 2); | |
10003 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10004 | let r: u64x2 = transmute(vcltq_u64(transmute(a), transmute(b))); | |
10005 | assert_eq!(r, e); | |
10006 | } | |
10007 | ||
10008 | #[simd_test(enable = "neon")] | |
10009 | unsafe fn test_vclt_f64() { | |
10010 | let a: f64 = 0.1; | |
10011 | let b: f64 = 1.2; | |
10012 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10013 | let r: u64x1 = transmute(vclt_f64(transmute(a), transmute(b))); | |
10014 | assert_eq!(r, e); | |
10015 | } | |
10016 | ||
10017 | #[simd_test(enable = "neon")] | |
10018 | unsafe fn test_vcltq_f64() { | |
10019 | let a: f64x2 = f64x2::new(0.1, 1.2); | |
10020 | let b: f64x2 = f64x2::new(1.2, 2.3); | |
10021 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10022 | let r: u64x2 = transmute(vcltq_f64(transmute(a), transmute(b))); | |
10023 | assert_eq!(r, e); | |
10024 | } | |
10025 | ||
10026 | #[simd_test(enable = "neon")] | |
10027 | unsafe fn test_vcle_s64() { | |
10028 | let a: i64x1 = i64x1::new(0); | |
10029 | let b: i64x1 = i64x1::new(1); | |
10030 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10031 | let r: u64x1 = transmute(vcle_s64(transmute(a), transmute(b))); | |
10032 | assert_eq!(r, e); | |
10033 | } | |
10034 | ||
10035 | #[simd_test(enable = "neon")] | |
10036 | unsafe fn test_vcleq_s64() { | |
10037 | let a: i64x2 = i64x2::new(0, 1); | |
10038 | let b: i64x2 = i64x2::new(1, 2); | |
10039 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10040 | let r: u64x2 = transmute(vcleq_s64(transmute(a), transmute(b))); | |
10041 | assert_eq!(r, e); | |
10042 | } | |
10043 | ||
10044 | #[simd_test(enable = "neon")] | |
10045 | unsafe fn test_vcle_u64() { | |
10046 | let a: u64x1 = u64x1::new(0); | |
10047 | let b: u64x1 = u64x1::new(1); | |
10048 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10049 | let r: u64x1 = transmute(vcle_u64(transmute(a), transmute(b))); | |
10050 | assert_eq!(r, e); | |
10051 | } | |
10052 | ||
10053 | #[simd_test(enable = "neon")] | |
10054 | unsafe fn test_vcleq_u64() { | |
10055 | let a: u64x2 = u64x2::new(0, 1); | |
10056 | let b: u64x2 = u64x2::new(1, 2); | |
10057 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10058 | let r: u64x2 = transmute(vcleq_u64(transmute(a), transmute(b))); | |
10059 | assert_eq!(r, e); | |
10060 | } | |
10061 | ||
10062 | #[simd_test(enable = "neon")] | |
10063 | unsafe fn test_vcle_f64() { | |
10064 | let a: f64 = 0.1; | |
10065 | let b: f64 = 1.2; | |
10066 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10067 | let r: u64x1 = transmute(vcle_f64(transmute(a), transmute(b))); | |
10068 | assert_eq!(r, e); | |
10069 | } | |
10070 | ||
10071 | #[simd_test(enable = "neon")] | |
10072 | unsafe fn test_vcleq_f64() { | |
10073 | let a: f64x2 = f64x2::new(0.1, 1.2); | |
10074 | let b: f64x2 = f64x2::new(1.2, 2.3); | |
10075 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10076 | let r: u64x2 = transmute(vcleq_f64(transmute(a), transmute(b))); | |
10077 | assert_eq!(r, e); | |
10078 | } | |
10079 | ||
10080 | #[simd_test(enable = "neon")] | |
10081 | unsafe fn test_vcge_s64() { | |
10082 | let a: i64x1 = i64x1::new(1); | |
10083 | let b: i64x1 = i64x1::new(0); | |
10084 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10085 | let r: u64x1 = transmute(vcge_s64(transmute(a), transmute(b))); | |
10086 | assert_eq!(r, e); | |
10087 | } | |
10088 | ||
10089 | #[simd_test(enable = "neon")] | |
10090 | unsafe fn test_vcgeq_s64() { | |
10091 | let a: i64x2 = i64x2::new(1, 2); | |
10092 | let b: i64x2 = i64x2::new(0, 1); | |
10093 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10094 | let r: u64x2 = transmute(vcgeq_s64(transmute(a), transmute(b))); | |
10095 | assert_eq!(r, e); | |
10096 | } | |
10097 | ||
10098 | #[simd_test(enable = "neon")] | |
10099 | unsafe fn test_vcge_u64() { | |
10100 | let a: u64x1 = u64x1::new(1); | |
10101 | let b: u64x1 = u64x1::new(0); | |
10102 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10103 | let r: u64x1 = transmute(vcge_u64(transmute(a), transmute(b))); | |
10104 | assert_eq!(r, e); | |
10105 | } | |
10106 | ||
10107 | #[simd_test(enable = "neon")] | |
10108 | unsafe fn test_vcgeq_u64() { | |
10109 | let a: u64x2 = u64x2::new(1, 2); | |
10110 | let b: u64x2 = u64x2::new(0, 1); | |
10111 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10112 | let r: u64x2 = transmute(vcgeq_u64(transmute(a), transmute(b))); | |
10113 | assert_eq!(r, e); | |
10114 | } | |
10115 | ||
10116 | #[simd_test(enable = "neon")] | |
10117 | unsafe fn test_vcge_f64() { | |
10118 | let a: f64 = 1.2; | |
10119 | let b: f64 = 0.1; | |
10120 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10121 | let r: u64x1 = transmute(vcge_f64(transmute(a), transmute(b))); | |
10122 | assert_eq!(r, e); | |
10123 | } | |
10124 | ||
10125 | #[simd_test(enable = "neon")] | |
10126 | unsafe fn test_vcgeq_f64() { | |
10127 | let a: f64x2 = f64x2::new(1.2, 2.3); | |
10128 | let b: f64x2 = f64x2::new(0.1, 1.2); | |
10129 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10130 | let r: u64x2 = transmute(vcgeq_f64(transmute(a), transmute(b))); | |
10131 | assert_eq!(r, e); | |
10132 | } | |
10133 | ||
10134 | #[simd_test(enable = "neon")] | |
10135 | unsafe fn test_vcgez_s8() { | |
10136 | let a: i8x8 = i8x8::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); | |
10137 | let e: u8x8 = u8x8::new(0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); | |
10138 | let r: u8x8 = transmute(vcgez_s8(transmute(a))); | |
10139 | assert_eq!(r, e); | |
10140 | } | |
10141 | ||
10142 | #[simd_test(enable = "neon")] | |
10143 | unsafe fn test_vcgezq_s8() { | |
10144 | let a: i8x16 = i8x16::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x7F); | |
10145 | let e: u8x16 = u8x16::new(0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); | |
10146 | let r: u8x16 = transmute(vcgezq_s8(transmute(a))); | |
10147 | assert_eq!(r, e); | |
10148 | } | |
10149 | ||
10150 | #[simd_test(enable = "neon")] | |
10151 | unsafe fn test_vcgez_s16() { | |
10152 | let a: i16x4 = i16x4::new(-32768, -1, 0x00, 0x01); | |
10153 | let e: u16x4 = u16x4::new(0, 0, 0xFF_FF, 0xFF_FF); | |
10154 | let r: u16x4 = transmute(vcgez_s16(transmute(a))); | |
10155 | assert_eq!(r, e); | |
10156 | } | |
10157 | ||
10158 | #[simd_test(enable = "neon")] | |
10159 | unsafe fn test_vcgezq_s16() { | |
10160 | let a: i16x8 = i16x8::new(-32768, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); | |
10161 | let e: u16x8 = u16x8::new(0, 0, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); | |
10162 | let r: u16x8 = transmute(vcgezq_s16(transmute(a))); | |
10163 | assert_eq!(r, e); | |
10164 | } | |
10165 | ||
10166 | #[simd_test(enable = "neon")] | |
10167 | unsafe fn test_vcgez_s32() { | |
10168 | let a: i32x2 = i32x2::new(-2147483648, -1); | |
10169 | let e: u32x2 = u32x2::new(0, 0); | |
10170 | let r: u32x2 = transmute(vcgez_s32(transmute(a))); | |
10171 | assert_eq!(r, e); | |
10172 | } | |
10173 | ||
10174 | #[simd_test(enable = "neon")] | |
10175 | unsafe fn test_vcgezq_s32() { | |
10176 | let a: i32x4 = i32x4::new(-2147483648, -1, 0x00, 0x01); | |
10177 | let e: u32x4 = u32x4::new(0, 0, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); | |
10178 | let r: u32x4 = transmute(vcgezq_s32(transmute(a))); | |
10179 | assert_eq!(r, e); | |
10180 | } | |
10181 | ||
10182 | #[simd_test(enable = "neon")] | |
10183 | unsafe fn test_vcgez_s64() { | |
10184 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
10185 | let e: u64x1 = u64x1::new(0); | |
10186 | let r: u64x1 = transmute(vcgez_s64(transmute(a))); | |
10187 | assert_eq!(r, e); | |
10188 | } | |
10189 | ||
10190 | #[simd_test(enable = "neon")] | |
10191 | unsafe fn test_vcgezq_s64() { | |
10192 | let a: i64x2 = i64x2::new(-9223372036854775808, -1); | |
10193 | let e: u64x2 = u64x2::new(0, 0); | |
10194 | let r: u64x2 = transmute(vcgezq_s64(transmute(a))); | |
10195 | assert_eq!(r, e); | |
10196 | } | |
10197 | ||
10198 | #[simd_test(enable = "neon")] | |
10199 | unsafe fn test_vcgez_f32() { | |
10200 | let a: f32x2 = f32x2::new(-1.2, 0.0); | |
10201 | let e: u32x2 = u32x2::new(0, 0xFF_FF_FF_FF); | |
10202 | let r: u32x2 = transmute(vcgez_f32(transmute(a))); | |
10203 | assert_eq!(r, e); | |
10204 | } | |
10205 | ||
10206 | #[simd_test(enable = "neon")] | |
10207 | unsafe fn test_vcgezq_f32() { | |
10208 | let a: f32x4 = f32x4::new(-1.2, 0.0, 1.2, 2.3); | |
10209 | let e: u32x4 = u32x4::new(0, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); | |
10210 | let r: u32x4 = transmute(vcgezq_f32(transmute(a))); | |
10211 | assert_eq!(r, e); | |
10212 | } | |
10213 | ||
10214 | #[simd_test(enable = "neon")] | |
10215 | unsafe fn test_vcgez_f64() { | |
10216 | let a: f64 = -1.2; | |
10217 | let e: u64x1 = u64x1::new(0); | |
10218 | let r: u64x1 = transmute(vcgez_f64(transmute(a))); | |
10219 | assert_eq!(r, e); | |
10220 | } | |
10221 | ||
10222 | #[simd_test(enable = "neon")] | |
10223 | unsafe fn test_vcgezq_f64() { | |
10224 | let a: f64x2 = f64x2::new(-1.2, 0.0); | |
10225 | let e: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10226 | let r: u64x2 = transmute(vcgezq_f64(transmute(a))); | |
10227 | assert_eq!(r, e); | |
10228 | } | |
10229 | ||
10230 | #[simd_test(enable = "neon")] | |
10231 | unsafe fn test_vcgtz_s8() { | |
10232 | let a: i8x8 = i8x8::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); | |
10233 | let e: u8x8 = u8x8::new(0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); | |
10234 | let r: u8x8 = transmute(vcgtz_s8(transmute(a))); | |
10235 | assert_eq!(r, e); | |
10236 | } | |
10237 | ||
10238 | #[simd_test(enable = "neon")] | |
10239 | unsafe fn test_vcgtzq_s8() { | |
10240 | let a: i8x16 = i8x16::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x7F); | |
10241 | let e: u8x16 = u8x16::new(0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); | |
10242 | let r: u8x16 = transmute(vcgtzq_s8(transmute(a))); | |
10243 | assert_eq!(r, e); | |
10244 | } | |
10245 | ||
10246 | #[simd_test(enable = "neon")] | |
10247 | unsafe fn test_vcgtz_s16() { | |
10248 | let a: i16x4 = i16x4::new(-32768, -1, 0x00, 0x01); | |
10249 | let e: u16x4 = u16x4::new(0, 0, 0, 0xFF_FF); | |
10250 | let r: u16x4 = transmute(vcgtz_s16(transmute(a))); | |
10251 | assert_eq!(r, e); | |
10252 | } | |
10253 | ||
10254 | #[simd_test(enable = "neon")] | |
10255 | unsafe fn test_vcgtzq_s16() { | |
10256 | let a: i16x8 = i16x8::new(-32768, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); | |
10257 | let e: u16x8 = u16x8::new(0, 0, 0, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); | |
10258 | let r: u16x8 = transmute(vcgtzq_s16(transmute(a))); | |
10259 | assert_eq!(r, e); | |
10260 | } | |
10261 | ||
10262 | #[simd_test(enable = "neon")] | |
10263 | unsafe fn test_vcgtz_s32() { | |
10264 | let a: i32x2 = i32x2::new(-2147483648, -1); | |
10265 | let e: u32x2 = u32x2::new(0, 0); | |
10266 | let r: u32x2 = transmute(vcgtz_s32(transmute(a))); | |
10267 | assert_eq!(r, e); | |
10268 | } | |
10269 | ||
10270 | #[simd_test(enable = "neon")] | |
10271 | unsafe fn test_vcgtzq_s32() { | |
10272 | let a: i32x4 = i32x4::new(-2147483648, -1, 0x00, 0x01); | |
10273 | let e: u32x4 = u32x4::new(0, 0, 0, 0xFF_FF_FF_FF); | |
10274 | let r: u32x4 = transmute(vcgtzq_s32(transmute(a))); | |
10275 | assert_eq!(r, e); | |
10276 | } | |
10277 | ||
10278 | #[simd_test(enable = "neon")] | |
10279 | unsafe fn test_vcgtz_s64() { | |
10280 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
10281 | let e: u64x1 = u64x1::new(0); | |
10282 | let r: u64x1 = transmute(vcgtz_s64(transmute(a))); | |
10283 | assert_eq!(r, e); | |
10284 | } | |
10285 | ||
10286 | #[simd_test(enable = "neon")] | |
10287 | unsafe fn test_vcgtzq_s64() { | |
10288 | let a: i64x2 = i64x2::new(-9223372036854775808, -1); | |
10289 | let e: u64x2 = u64x2::new(0, 0); | |
10290 | let r: u64x2 = transmute(vcgtzq_s64(transmute(a))); | |
10291 | assert_eq!(r, e); | |
10292 | } | |
10293 | ||
10294 | #[simd_test(enable = "neon")] | |
10295 | unsafe fn test_vcgtz_f32() { | |
10296 | let a: f32x2 = f32x2::new(-1.2, 0.0); | |
10297 | let e: u32x2 = u32x2::new(0, 0); | |
10298 | let r: u32x2 = transmute(vcgtz_f32(transmute(a))); | |
10299 | assert_eq!(r, e); | |
10300 | } | |
10301 | ||
10302 | #[simd_test(enable = "neon")] | |
10303 | unsafe fn test_vcgtzq_f32() { | |
10304 | let a: f32x4 = f32x4::new(-1.2, 0.0, 1.2, 2.3); | |
10305 | let e: u32x4 = u32x4::new(0, 0, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); | |
10306 | let r: u32x4 = transmute(vcgtzq_f32(transmute(a))); | |
10307 | assert_eq!(r, e); | |
10308 | } | |
10309 | ||
10310 | #[simd_test(enable = "neon")] | |
10311 | unsafe fn test_vcgtz_f64() { | |
10312 | let a: f64 = -1.2; | |
10313 | let e: u64x1 = u64x1::new(0); | |
10314 | let r: u64x1 = transmute(vcgtz_f64(transmute(a))); | |
10315 | assert_eq!(r, e); | |
10316 | } | |
10317 | ||
10318 | #[simd_test(enable = "neon")] | |
10319 | unsafe fn test_vcgtzq_f64() { | |
10320 | let a: f64x2 = f64x2::new(-1.2, 0.0); | |
10321 | let e: u64x2 = u64x2::new(0, 0); | |
10322 | let r: u64x2 = transmute(vcgtzq_f64(transmute(a))); | |
10323 | assert_eq!(r, e); | |
10324 | } | |
10325 | ||
10326 | #[simd_test(enable = "neon")] | |
10327 | unsafe fn test_vclez_s8() { | |
10328 | let a: i8x8 = i8x8::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); | |
10329 | let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0, 0, 0, 0, 0); | |
10330 | let r: u8x8 = transmute(vclez_s8(transmute(a))); | |
10331 | assert_eq!(r, e); | |
10332 | } | |
10333 | ||
10334 | #[simd_test(enable = "neon")] | |
10335 | unsafe fn test_vclezq_s8() { | |
10336 | let a: i8x16 = i8x16::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x7F); | |
10337 | let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
10338 | let r: u8x16 = transmute(vclezq_s8(transmute(a))); | |
10339 | assert_eq!(r, e); | |
10340 | } | |
10341 | ||
10342 | #[simd_test(enable = "neon")] | |
10343 | unsafe fn test_vclez_s16() { | |
10344 | let a: i16x4 = i16x4::new(-32768, -1, 0x00, 0x01); | |
10345 | let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0); | |
10346 | let r: u16x4 = transmute(vclez_s16(transmute(a))); | |
10347 | assert_eq!(r, e); | |
10348 | } | |
10349 | ||
10350 | #[simd_test(enable = "neon")] | |
10351 | unsafe fn test_vclezq_s16() { | |
10352 | let a: i16x8 = i16x8::new(-32768, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); | |
10353 | let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0, 0, 0, 0, 0); | |
10354 | let r: u16x8 = transmute(vclezq_s16(transmute(a))); | |
10355 | assert_eq!(r, e); | |
10356 | } | |
10357 | ||
10358 | #[simd_test(enable = "neon")] | |
10359 | unsafe fn test_vclez_s32() { | |
10360 | let a: i32x2 = i32x2::new(-2147483648, -1); | |
10361 | let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); | |
10362 | let r: u32x2 = transmute(vclez_s32(transmute(a))); | |
10363 | assert_eq!(r, e); | |
10364 | } | |
10365 | ||
10366 | #[simd_test(enable = "neon")] | |
10367 | unsafe fn test_vclezq_s32() { | |
10368 | let a: i32x4 = i32x4::new(-2147483648, -1, 0x00, 0x01); | |
10369 | let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0); | |
10370 | let r: u32x4 = transmute(vclezq_s32(transmute(a))); | |
10371 | assert_eq!(r, e); | |
10372 | } | |
10373 | ||
10374 | #[simd_test(enable = "neon")] | |
10375 | unsafe fn test_vclez_s64() { | |
10376 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
10377 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10378 | let r: u64x1 = transmute(vclez_s64(transmute(a))); | |
10379 | assert_eq!(r, e); | |
10380 | } | |
10381 | ||
10382 | #[simd_test(enable = "neon")] | |
10383 | unsafe fn test_vclezq_s64() { | |
10384 | let a: i64x2 = i64x2::new(-9223372036854775808, -1); | |
10385 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10386 | let r: u64x2 = transmute(vclezq_s64(transmute(a))); | |
10387 | assert_eq!(r, e); | |
10388 | } | |
10389 | ||
10390 | #[simd_test(enable = "neon")] | |
10391 | unsafe fn test_vclez_f32() { | |
10392 | let a: f32x2 = f32x2::new(-1.2, 0.0); | |
10393 | let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); | |
10394 | let r: u32x2 = transmute(vclez_f32(transmute(a))); | |
10395 | assert_eq!(r, e); | |
10396 | } | |
10397 | ||
10398 | #[simd_test(enable = "neon")] | |
10399 | unsafe fn test_vclezq_f32() { | |
10400 | let a: f32x4 = f32x4::new(-1.2, 0.0, 1.2, 2.3); | |
10401 | let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0, 0); | |
10402 | let r: u32x4 = transmute(vclezq_f32(transmute(a))); | |
10403 | assert_eq!(r, e); | |
10404 | } | |
10405 | ||
10406 | #[simd_test(enable = "neon")] | |
10407 | unsafe fn test_vclez_f64() { | |
10408 | let a: f64 = -1.2; | |
10409 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10410 | let r: u64x1 = transmute(vclez_f64(transmute(a))); | |
10411 | assert_eq!(r, e); | |
10412 | } | |
10413 | ||
10414 | #[simd_test(enable = "neon")] | |
10415 | unsafe fn test_vclezq_f64() { | |
10416 | let a: f64x2 = f64x2::new(-1.2, 0.0); | |
10417 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10418 | let r: u64x2 = transmute(vclezq_f64(transmute(a))); | |
10419 | assert_eq!(r, e); | |
10420 | } | |
10421 | ||
10422 | #[simd_test(enable = "neon")] | |
10423 | unsafe fn test_vcltz_s8() { | |
10424 | let a: i8x8 = i8x8::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); | |
10425 | let e: u8x8 = u8x8::new(0xFF, 0xFF, 0, 0, 0, 0, 0, 0); | |
10426 | let r: u8x8 = transmute(vcltz_s8(transmute(a))); | |
10427 | assert_eq!(r, e); | |
10428 | } | |
10429 | ||
10430 | #[simd_test(enable = "neon")] | |
10431 | unsafe fn test_vcltzq_s8() { | |
10432 | let a: i8x16 = i8x16::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x7F); | |
10433 | let e: u8x16 = u8x16::new(0xFF, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
10434 | let r: u8x16 = transmute(vcltzq_s8(transmute(a))); | |
10435 | assert_eq!(r, e); | |
10436 | } | |
10437 | ||
10438 | #[simd_test(enable = "neon")] | |
10439 | unsafe fn test_vcltz_s16() { | |
10440 | let a: i16x4 = i16x4::new(-32768, -1, 0x00, 0x01); | |
10441 | let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0, 0); | |
10442 | let r: u16x4 = transmute(vcltz_s16(transmute(a))); | |
10443 | assert_eq!(r, e); | |
10444 | } | |
10445 | ||
10446 | #[simd_test(enable = "neon")] | |
10447 | unsafe fn test_vcltzq_s16() { | |
10448 | let a: i16x8 = i16x8::new(-32768, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); | |
10449 | let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0, 0, 0, 0, 0, 0); | |
10450 | let r: u16x8 = transmute(vcltzq_s16(transmute(a))); | |
10451 | assert_eq!(r, e); | |
10452 | } | |
10453 | ||
10454 | #[simd_test(enable = "neon")] | |
10455 | unsafe fn test_vcltz_s32() { | |
10456 | let a: i32x2 = i32x2::new(-2147483648, -1); | |
10457 | let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); | |
10458 | let r: u32x2 = transmute(vcltz_s32(transmute(a))); | |
10459 | assert_eq!(r, e); | |
10460 | } | |
10461 | ||
10462 | #[simd_test(enable = "neon")] | |
10463 | unsafe fn test_vcltzq_s32() { | |
10464 | let a: i32x4 = i32x4::new(-2147483648, -1, 0x00, 0x01); | |
10465 | let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0, 0); | |
10466 | let r: u32x4 = transmute(vcltzq_s32(transmute(a))); | |
10467 | assert_eq!(r, e); | |
10468 | } | |
10469 | ||
10470 | #[simd_test(enable = "neon")] | |
10471 | unsafe fn test_vcltz_s64() { | |
10472 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
10473 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10474 | let r: u64x1 = transmute(vcltz_s64(transmute(a))); | |
10475 | assert_eq!(r, e); | |
10476 | } | |
10477 | ||
10478 | #[simd_test(enable = "neon")] | |
10479 | unsafe fn test_vcltzq_s64() { | |
10480 | let a: i64x2 = i64x2::new(-9223372036854775808, -1); | |
10481 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10482 | let r: u64x2 = transmute(vcltzq_s64(transmute(a))); | |
10483 | assert_eq!(r, e); | |
10484 | } | |
10485 | ||
10486 | #[simd_test(enable = "neon")] | |
10487 | unsafe fn test_vcltz_f32() { | |
10488 | let a: f32x2 = f32x2::new(-1.2, 0.0); | |
10489 | let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0); | |
10490 | let r: u32x2 = transmute(vcltz_f32(transmute(a))); | |
10491 | assert_eq!(r, e); | |
10492 | } | |
10493 | ||
10494 | #[simd_test(enable = "neon")] | |
10495 | unsafe fn test_vcltzq_f32() { | |
10496 | let a: f32x4 = f32x4::new(-1.2, 0.0, 1.2, 2.3); | |
10497 | let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0, 0, 0); | |
10498 | let r: u32x4 = transmute(vcltzq_f32(transmute(a))); | |
10499 | assert_eq!(r, e); | |
10500 | } | |
10501 | ||
10502 | #[simd_test(enable = "neon")] | |
10503 | unsafe fn test_vcltz_f64() { | |
10504 | let a: f64 = -1.2; | |
10505 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10506 | let r: u64x1 = transmute(vcltz_f64(transmute(a))); | |
10507 | assert_eq!(r, e); | |
10508 | } | |
10509 | ||
10510 | #[simd_test(enable = "neon")] | |
10511 | unsafe fn test_vcltzq_f64() { | |
10512 | let a: f64x2 = f64x2::new(-1.2, 0.0); | |
10513 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); | |
10514 | let r: u64x2 = transmute(vcltzq_f64(transmute(a))); | |
10515 | assert_eq!(r, e); | |
10516 | } | |
10517 | ||
10518 | #[simd_test(enable = "neon")] | |
10519 | unsafe fn test_vcagt_f64() { | |
10520 | let a: f64 = -1.2; | |
10521 | let b: f64 = -1.1; | |
10522 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10523 | let r: u64x1 = transmute(vcagt_f64(transmute(a), transmute(b))); | |
10524 | assert_eq!(r, e); | |
10525 | } | |
10526 | ||
10527 | #[simd_test(enable = "neon")] | |
10528 | unsafe fn test_vcagtq_f64() { | |
10529 | let a: f64x2 = f64x2::new(-1.2, 0.0); | |
10530 | let b: f64x2 = f64x2::new(-1.1, 0.0); | |
10531 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); | |
10532 | let r: u64x2 = transmute(vcagtq_f64(transmute(a), transmute(b))); | |
10533 | assert_eq!(r, e); | |
10534 | } | |
10535 | ||
10536 | #[simd_test(enable = "neon")] | |
10537 | unsafe fn test_vcage_f64() { | |
10538 | let a: f64 = -1.2; | |
10539 | let b: f64 = -1.1; | |
10540 | let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10541 | let r: u64x1 = transmute(vcage_f64(transmute(a), transmute(b))); | |
10542 | assert_eq!(r, e); | |
10543 | } | |
10544 | ||
10545 | #[simd_test(enable = "neon")] | |
10546 | unsafe fn test_vcageq_f64() { | |
10547 | let a: f64x2 = f64x2::new(-1.2, 0.0); | |
10548 | let b: f64x2 = f64x2::new(-1.1, 0.0); | |
10549 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10550 | let r: u64x2 = transmute(vcageq_f64(transmute(a), transmute(b))); | |
10551 | assert_eq!(r, e); | |
10552 | } | |
10553 | ||
10554 | #[simd_test(enable = "neon")] | |
10555 | unsafe fn test_vcalt_f64() { | |
10556 | let a: f64 = -1.2; | |
10557 | let b: f64 = -1.1; | |
10558 | let e: u64x1 = u64x1::new(0); | |
10559 | let r: u64x1 = transmute(vcalt_f64(transmute(a), transmute(b))); | |
10560 | assert_eq!(r, e); | |
10561 | } | |
10562 | ||
10563 | #[simd_test(enable = "neon")] | |
10564 | unsafe fn test_vcaltq_f64() { | |
10565 | let a: f64x2 = f64x2::new(-1.2, 0.0); | |
10566 | let b: f64x2 = f64x2::new(-1.1, 0.0); | |
10567 | let e: u64x2 = u64x2::new(0, 0); | |
10568 | let r: u64x2 = transmute(vcaltq_f64(transmute(a), transmute(b))); | |
10569 | assert_eq!(r, e); | |
10570 | } | |
10571 | ||
10572 | #[simd_test(enable = "neon")] | |
10573 | unsafe fn test_vcale_f64() { | |
10574 | let a: f64 = -1.2; | |
10575 | let b: f64 = -1.1; | |
10576 | let e: u64x1 = u64x1::new(0); | |
10577 | let r: u64x1 = transmute(vcale_f64(transmute(a), transmute(b))); | |
10578 | assert_eq!(r, e); | |
10579 | } | |
10580 | ||
10581 | #[simd_test(enable = "neon")] | |
10582 | unsafe fn test_vcaleq_f64() { | |
10583 | let a: f64x2 = f64x2::new(-1.2, 0.0); | |
10584 | let b: f64x2 = f64x2::new(-1.1, 0.0); | |
10585 | let e: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10586 | let r: u64x2 = transmute(vcaleq_f64(transmute(a), transmute(b))); | |
10587 | assert_eq!(r, e); | |
10588 | } | |
10589 | ||
10590 | #[simd_test(enable = "neon")] | |
10591 | unsafe fn test_vcopy_lane_s8() { | |
10592 | let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10593 | let b: i8x8 = i8x8::new(0, 0x7F, 0, 0, 0, 0, 0, 0); | |
10594 | let e: i8x8 = i8x8::new(0x7F, 2, 3, 4, 5, 6, 7, 8); | |
10595 | let r: i8x8 = transmute(vcopy_lane_s8::<0, 1>(transmute(a), transmute(b))); | |
10596 | assert_eq!(r, e); | |
10597 | } | |
10598 | ||
10599 | #[simd_test(enable = "neon")] | |
10600 | unsafe fn test_vcopyq_laneq_s8() { | |
10601 | let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10602 | let b: i8x16 = i8x16::new(0, 0x7F, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
10603 | let e: i8x16 = i8x16::new(0x7F, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10604 | let r: i8x16 = transmute(vcopyq_laneq_s8::<0, 1>(transmute(a), transmute(b))); | |
10605 | assert_eq!(r, e); | |
10606 | } | |
10607 | ||
10608 | #[simd_test(enable = "neon")] | |
10609 | unsafe fn test_vcopy_lane_s16() { | |
10610 | let a: i16x4 = i16x4::new(1, 2, 3, 4); | |
10611 | let b: i16x4 = i16x4::new(0, 0x7F_FF, 0, 0); | |
10612 | let e: i16x4 = i16x4::new(0x7F_FF, 2, 3, 4); | |
10613 | let r: i16x4 = transmute(vcopy_lane_s16::<0, 1>(transmute(a), transmute(b))); | |
10614 | assert_eq!(r, e); | |
10615 | } | |
10616 | ||
10617 | #[simd_test(enable = "neon")] | |
10618 | unsafe fn test_vcopyq_laneq_s16() { | |
10619 | let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10620 | let b: i16x8 = i16x8::new(0, 0x7F_FF, 0, 0, 0, 0, 0, 0); | |
10621 | let e: i16x8 = i16x8::new(0x7F_FF, 2, 3, 4, 5, 6, 7, 8); | |
10622 | let r: i16x8 = transmute(vcopyq_laneq_s16::<0, 1>(transmute(a), transmute(b))); | |
10623 | assert_eq!(r, e); | |
10624 | } | |
10625 | ||
10626 | #[simd_test(enable = "neon")] | |
10627 | unsafe fn test_vcopy_lane_s32() { | |
10628 | let a: i32x2 = i32x2::new(1, 2); | |
10629 | let b: i32x2 = i32x2::new(0, 0x7F_FF_FF_FF); | |
10630 | let e: i32x2 = i32x2::new(0x7F_FF_FF_FF, 2); | |
10631 | let r: i32x2 = transmute(vcopy_lane_s32::<0, 1>(transmute(a), transmute(b))); | |
10632 | assert_eq!(r, e); | |
10633 | } | |
10634 | ||
10635 | #[simd_test(enable = "neon")] | |
10636 | unsafe fn test_vcopyq_laneq_s32() { | |
10637 | let a: i32x4 = i32x4::new(1, 2, 3, 4); | |
10638 | let b: i32x4 = i32x4::new(0, 0x7F_FF_FF_FF, 0, 0); | |
10639 | let e: i32x4 = i32x4::new(0x7F_FF_FF_FF, 2, 3, 4); | |
10640 | let r: i32x4 = transmute(vcopyq_laneq_s32::<0, 1>(transmute(a), transmute(b))); | |
10641 | assert_eq!(r, e); | |
10642 | } | |
10643 | ||
10644 | #[simd_test(enable = "neon")] | |
10645 | unsafe fn test_vcopyq_laneq_s64() { | |
10646 | let a: i64x2 = i64x2::new(1, 2); | |
10647 | let b: i64x2 = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF); | |
10648 | let e: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 2); | |
10649 | let r: i64x2 = transmute(vcopyq_laneq_s64::<0, 1>(transmute(a), transmute(b))); | |
10650 | assert_eq!(r, e); | |
10651 | } | |
10652 | ||
10653 | #[simd_test(enable = "neon")] | |
10654 | unsafe fn test_vcopy_lane_u8() { | |
10655 | let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10656 | let b: u8x8 = u8x8::new(0, 0xFF, 0, 0, 0, 0, 0, 0); | |
10657 | let e: u8x8 = u8x8::new(0xFF, 2, 3, 4, 5, 6, 7, 8); | |
10658 | let r: u8x8 = transmute(vcopy_lane_u8::<0, 1>(transmute(a), transmute(b))); | |
10659 | assert_eq!(r, e); | |
10660 | } | |
10661 | ||
10662 | #[simd_test(enable = "neon")] | |
10663 | unsafe fn test_vcopyq_laneq_u8() { | |
10664 | let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10665 | let b: u8x16 = u8x16::new(0, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
10666 | let e: u8x16 = u8x16::new(0xFF, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10667 | let r: u8x16 = transmute(vcopyq_laneq_u8::<0, 1>(transmute(a), transmute(b))); | |
10668 | assert_eq!(r, e); | |
10669 | } | |
10670 | ||
10671 | #[simd_test(enable = "neon")] | |
10672 | unsafe fn test_vcopy_lane_u16() { | |
10673 | let a: u16x4 = u16x4::new(1, 2, 3, 4); | |
10674 | let b: u16x4 = u16x4::new(0, 0xFF_FF, 0, 0); | |
10675 | let e: u16x4 = u16x4::new(0xFF_FF, 2, 3, 4); | |
10676 | let r: u16x4 = transmute(vcopy_lane_u16::<0, 1>(transmute(a), transmute(b))); | |
10677 | assert_eq!(r, e); | |
10678 | } | |
10679 | ||
10680 | #[simd_test(enable = "neon")] | |
10681 | unsafe fn test_vcopyq_laneq_u16() { | |
10682 | let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10683 | let b: u16x8 = u16x8::new(0, 0xFF_FF, 0, 0, 0, 0, 0, 0); | |
10684 | let e: u16x8 = u16x8::new(0xFF_FF, 2, 3, 4, 5, 6, 7, 8); | |
10685 | let r: u16x8 = transmute(vcopyq_laneq_u16::<0, 1>(transmute(a), transmute(b))); | |
10686 | assert_eq!(r, e); | |
10687 | } | |
10688 | ||
10689 | #[simd_test(enable = "neon")] | |
10690 | unsafe fn test_vcopy_lane_u32() { | |
10691 | let a: u32x2 = u32x2::new(1, 2); | |
10692 | let b: u32x2 = u32x2::new(0, 0xFF_FF_FF_FF); | |
10693 | let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 2); | |
10694 | let r: u32x2 = transmute(vcopy_lane_u32::<0, 1>(transmute(a), transmute(b))); | |
10695 | assert_eq!(r, e); | |
10696 | } | |
10697 | ||
10698 | #[simd_test(enable = "neon")] | |
10699 | unsafe fn test_vcopyq_laneq_u32() { | |
10700 | let a: u32x4 = u32x4::new(1, 2, 3, 4); | |
10701 | let b: u32x4 = u32x4::new(0, 0xFF_FF_FF_FF, 0, 0); | |
10702 | let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 2, 3, 4); | |
10703 | let r: u32x4 = transmute(vcopyq_laneq_u32::<0, 1>(transmute(a), transmute(b))); | |
10704 | assert_eq!(r, e); | |
10705 | } | |
10706 | ||
10707 | #[simd_test(enable = "neon")] | |
10708 | unsafe fn test_vcopyq_laneq_u64() { | |
10709 | let a: u64x2 = u64x2::new(1, 2); | |
10710 | let b: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10711 | let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 2); | |
10712 | let r: u64x2 = transmute(vcopyq_laneq_u64::<0, 1>(transmute(a), transmute(b))); | |
10713 | assert_eq!(r, e); | |
10714 | } | |
10715 | ||
10716 | #[simd_test(enable = "neon")] | |
10717 | unsafe fn test_vcopy_lane_p8() { | |
10718 | let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10719 | let b: i8x8 = i8x8::new(0, 0x7F, 0, 0, 0, 0, 0, 0); | |
10720 | let e: i8x8 = i8x8::new(0x7F, 2, 3, 4, 5, 6, 7, 8); | |
10721 | let r: i8x8 = transmute(vcopy_lane_p8::<0, 1>(transmute(a), transmute(b))); | |
10722 | assert_eq!(r, e); | |
10723 | } | |
10724 | ||
10725 | #[simd_test(enable = "neon")] | |
10726 | unsafe fn test_vcopyq_laneq_p8() { | |
10727 | let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10728 | let b: i8x16 = i8x16::new(0, 0x7F, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
10729 | let e: i8x16 = i8x16::new(0x7F, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10730 | let r: i8x16 = transmute(vcopyq_laneq_p8::<0, 1>(transmute(a), transmute(b))); | |
10731 | assert_eq!(r, e); | |
10732 | } | |
10733 | ||
10734 | #[simd_test(enable = "neon")] | |
10735 | unsafe fn test_vcopy_lane_p16() { | |
10736 | let a: i16x4 = i16x4::new(1, 2, 3, 4); | |
10737 | let b: i16x4 = i16x4::new(0, 0x7F_FF, 0, 0); | |
10738 | let e: i16x4 = i16x4::new(0x7F_FF, 2, 3, 4); | |
10739 | let r: i16x4 = transmute(vcopy_lane_p16::<0, 1>(transmute(a), transmute(b))); | |
10740 | assert_eq!(r, e); | |
10741 | } | |
10742 | ||
10743 | #[simd_test(enable = "neon")] | |
10744 | unsafe fn test_vcopyq_laneq_p16() { | |
10745 | let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10746 | let b: i16x8 = i16x8::new(0, 0x7F_FF, 0, 0, 0, 0, 0, 0); | |
10747 | let e: i16x8 = i16x8::new(0x7F_FF, 2, 3, 4, 5, 6, 7, 8); | |
10748 | let r: i16x8 = transmute(vcopyq_laneq_p16::<0, 1>(transmute(a), transmute(b))); | |
10749 | assert_eq!(r, e); | |
10750 | } | |
10751 | ||
10752 | #[simd_test(enable = "neon")] | |
10753 | unsafe fn test_vcopyq_laneq_p64() { | |
10754 | let a: i64x2 = i64x2::new(1, 2); | |
10755 | let b: i64x2 = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF); | |
10756 | let e: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 2); | |
10757 | let r: i64x2 = transmute(vcopyq_laneq_p64::<0, 1>(transmute(a), transmute(b))); | |
10758 | assert_eq!(r, e); | |
10759 | } | |
10760 | ||
10761 | #[simd_test(enable = "neon")] | |
10762 | unsafe fn test_vcopy_lane_f32() { | |
10763 | let a: f32x2 = f32x2::new(1., 2.); | |
10764 | let b: f32x2 = f32x2::new(0., 0.5); | |
10765 | let e: f32x2 = f32x2::new(0.5, 2.); | |
10766 | let r: f32x2 = transmute(vcopy_lane_f32::<0, 1>(transmute(a), transmute(b))); | |
10767 | assert_eq!(r, e); | |
10768 | } | |
10769 | ||
10770 | #[simd_test(enable = "neon")] | |
10771 | unsafe fn test_vcopyq_laneq_f32() { | |
10772 | let a: f32x4 = f32x4::new(1., 2., 3., 4.); | |
10773 | let b: f32x4 = f32x4::new(0., 0.5, 0., 0.); | |
10774 | let e: f32x4 = f32x4::new(0.5, 2., 3., 4.); | |
10775 | let r: f32x4 = transmute(vcopyq_laneq_f32::<0, 1>(transmute(a), transmute(b))); | |
10776 | assert_eq!(r, e); | |
10777 | } | |
10778 | ||
10779 | #[simd_test(enable = "neon")] | |
10780 | unsafe fn test_vcopyq_laneq_f64() { | |
10781 | let a: f64x2 = f64x2::new(1., 2.); | |
10782 | let b: f64x2 = f64x2::new(0., 0.5); | |
10783 | let e: f64x2 = f64x2::new(0.5, 2.); | |
10784 | let r: f64x2 = transmute(vcopyq_laneq_f64::<0, 1>(transmute(a), transmute(b))); | |
10785 | assert_eq!(r, e); | |
10786 | } | |
10787 | ||
10788 | #[simd_test(enable = "neon")] | |
10789 | unsafe fn test_vcopy_laneq_s8() { | |
10790 | let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10791 | let b: i8x16 = i8x16::new(0, 0x7F, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
10792 | let e: i8x8 = i8x8::new(0x7F, 2, 3, 4, 5, 6, 7, 8); | |
10793 | let r: i8x8 = transmute(vcopy_laneq_s8::<0, 1>(transmute(a), transmute(b))); | |
10794 | assert_eq!(r, e); | |
10795 | } | |
10796 | ||
10797 | #[simd_test(enable = "neon")] | |
10798 | unsafe fn test_vcopy_laneq_s16() { | |
10799 | let a: i16x4 = i16x4::new(1, 2, 3, 4); | |
10800 | let b: i16x8 = i16x8::new(0, 0x7F_FF, 0, 0, 0, 0, 0, 0); | |
10801 | let e: i16x4 = i16x4::new(0x7F_FF, 2, 3, 4); | |
10802 | let r: i16x4 = transmute(vcopy_laneq_s16::<0, 1>(transmute(a), transmute(b))); | |
10803 | assert_eq!(r, e); | |
10804 | } | |
10805 | ||
10806 | #[simd_test(enable = "neon")] | |
10807 | unsafe fn test_vcopy_laneq_s32() { | |
10808 | let a: i32x2 = i32x2::new(1, 2); | |
10809 | let b: i32x4 = i32x4::new(0, 0x7F_FF_FF_FF, 0, 0); | |
10810 | let e: i32x2 = i32x2::new(0x7F_FF_FF_FF, 2); | |
10811 | let r: i32x2 = transmute(vcopy_laneq_s32::<0, 1>(transmute(a), transmute(b))); | |
10812 | assert_eq!(r, e); | |
10813 | } | |
10814 | ||
10815 | #[simd_test(enable = "neon")] | |
10816 | unsafe fn test_vcopy_laneq_u8() { | |
10817 | let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10818 | let b: u8x16 = u8x16::new(0, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
10819 | let e: u8x8 = u8x8::new(0xFF, 2, 3, 4, 5, 6, 7, 8); | |
10820 | let r: u8x8 = transmute(vcopy_laneq_u8::<0, 1>(transmute(a), transmute(b))); | |
10821 | assert_eq!(r, e); | |
10822 | } | |
10823 | ||
10824 | #[simd_test(enable = "neon")] | |
10825 | unsafe fn test_vcopy_laneq_u16() { | |
10826 | let a: u16x4 = u16x4::new(1, 2, 3, 4); | |
10827 | let b: u16x8 = u16x8::new(0, 0xFF_FF, 0, 0, 0, 0, 0, 0); | |
10828 | let e: u16x4 = u16x4::new(0xFF_FF, 2, 3, 4); | |
10829 | let r: u16x4 = transmute(vcopy_laneq_u16::<0, 1>(transmute(a), transmute(b))); | |
10830 | assert_eq!(r, e); | |
10831 | } | |
10832 | ||
10833 | #[simd_test(enable = "neon")] | |
10834 | unsafe fn test_vcopy_laneq_u32() { | |
10835 | let a: u32x2 = u32x2::new(1, 2); | |
10836 | let b: u32x4 = u32x4::new(0, 0xFF_FF_FF_FF, 0, 0); | |
10837 | let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 2); | |
10838 | let r: u32x2 = transmute(vcopy_laneq_u32::<0, 1>(transmute(a), transmute(b))); | |
10839 | assert_eq!(r, e); | |
10840 | } | |
10841 | ||
10842 | #[simd_test(enable = "neon")] | |
10843 | unsafe fn test_vcopy_laneq_p8() { | |
10844 | let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10845 | let b: i8x16 = i8x16::new(0, 0x7F, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
10846 | let e: i8x8 = i8x8::new(0x7F, 2, 3, 4, 5, 6, 7, 8); | |
10847 | let r: i8x8 = transmute(vcopy_laneq_p8::<0, 1>(transmute(a), transmute(b))); | |
10848 | assert_eq!(r, e); | |
10849 | } | |
10850 | ||
10851 | #[simd_test(enable = "neon")] | |
10852 | unsafe fn test_vcopy_laneq_p16() { | |
10853 | let a: i16x4 = i16x4::new(1, 2, 3, 4); | |
10854 | let b: i16x8 = i16x8::new(0, 0x7F_FF, 0, 0, 0, 0, 0, 0); | |
10855 | let e: i16x4 = i16x4::new(0x7F_FF, 2, 3, 4); | |
10856 | let r: i16x4 = transmute(vcopy_laneq_p16::<0, 1>(transmute(a), transmute(b))); | |
10857 | assert_eq!(r, e); | |
10858 | } | |
10859 | ||
10860 | #[simd_test(enable = "neon")] | |
10861 | unsafe fn test_vcopy_laneq_f32() { | |
10862 | let a: f32x2 = f32x2::new(1., 2.); | |
10863 | let b: f32x4 = f32x4::new(0., 0.5, 0., 0.); | |
10864 | let e: f32x2 = f32x2::new(0.5, 2.); | |
10865 | let r: f32x2 = transmute(vcopy_laneq_f32::<0, 1>(transmute(a), transmute(b))); | |
10866 | assert_eq!(r, e); | |
10867 | } | |
10868 | ||
10869 | #[simd_test(enable = "neon")] | |
10870 | unsafe fn test_vcopyq_lane_s8() { | |
10871 | let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10872 | let b: i8x8 = i8x8::new(0, 0x7F, 0, 0, 0, 0, 0, 0); | |
10873 | let e: i8x16 = i8x16::new(0x7F, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10874 | let r: i8x16 = transmute(vcopyq_lane_s8::<0, 1>(transmute(a), transmute(b))); | |
10875 | assert_eq!(r, e); | |
10876 | } | |
10877 | ||
10878 | #[simd_test(enable = "neon")] | |
10879 | unsafe fn test_vcopyq_lane_s16() { | |
10880 | let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10881 | let b: i16x4 = i16x4::new(0, 0x7F_FF, 0, 0); | |
10882 | let e: i16x8 = i16x8::new(0x7F_FF, 2, 3, 4, 5, 6, 7, 8); | |
10883 | let r: i16x8 = transmute(vcopyq_lane_s16::<0, 1>(transmute(a), transmute(b))); | |
10884 | assert_eq!(r, e); | |
10885 | } | |
10886 | ||
10887 | #[simd_test(enable = "neon")] | |
10888 | unsafe fn test_vcopyq_lane_s32() { | |
10889 | let a: i32x4 = i32x4::new(1, 2, 3, 4); | |
10890 | let b: i32x2 = i32x2::new(0, 0x7F_FF_FF_FF); | |
10891 | let e: i32x4 = i32x4::new(0x7F_FF_FF_FF, 2, 3, 4); | |
10892 | let r: i32x4 = transmute(vcopyq_lane_s32::<0, 1>(transmute(a), transmute(b))); | |
10893 | assert_eq!(r, e); | |
10894 | } | |
10895 | ||
10896 | #[simd_test(enable = "neon")] | |
10897 | unsafe fn test_vcopyq_lane_u8() { | |
10898 | let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10899 | let b: u8x8 = u8x8::new(0, 0xFF, 0, 0, 0, 0, 0, 0); | |
10900 | let e: u8x16 = u8x16::new(0xFF, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10901 | let r: u8x16 = transmute(vcopyq_lane_u8::<0, 1>(transmute(a), transmute(b))); | |
10902 | assert_eq!(r, e); | |
10903 | } | |
10904 | ||
10905 | #[simd_test(enable = "neon")] | |
10906 | unsafe fn test_vcopyq_lane_u16() { | |
10907 | let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10908 | let b: u16x4 = u16x4::new(0, 0xFF_FF, 0, 0); | |
10909 | let e: u16x8 = u16x8::new(0xFF_FF, 2, 3, 4, 5, 6, 7, 8); | |
10910 | let r: u16x8 = transmute(vcopyq_lane_u16::<0, 1>(transmute(a), transmute(b))); | |
10911 | assert_eq!(r, e); | |
10912 | } | |
10913 | ||
10914 | #[simd_test(enable = "neon")] | |
10915 | unsafe fn test_vcopyq_lane_u32() { | |
10916 | let a: u32x4 = u32x4::new(1, 2, 3, 4); | |
10917 | let b: u32x2 = u32x2::new(0, 0xFF_FF_FF_FF); | |
10918 | let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 2, 3, 4); | |
10919 | let r: u32x4 = transmute(vcopyq_lane_u32::<0, 1>(transmute(a), transmute(b))); | |
10920 | assert_eq!(r, e); | |
10921 | } | |
10922 | ||
10923 | #[simd_test(enable = "neon")] | |
10924 | unsafe fn test_vcopyq_lane_p8() { | |
10925 | let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10926 | let b: i8x8 = i8x8::new(0, 0x7F, 0, 0, 0, 0, 0, 0); | |
10927 | let e: i8x16 = i8x16::new(0x7F, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
10928 | let r: i8x16 = transmute(vcopyq_lane_p8::<0, 1>(transmute(a), transmute(b))); | |
10929 | assert_eq!(r, e); | |
10930 | } | |
10931 | ||
10932 | #[simd_test(enable = "neon")] | |
10933 | unsafe fn test_vcopyq_lane_p16() { | |
10934 | let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
10935 | let b: i16x4 = i16x4::new(0, 0x7F_FF, 0, 0); | |
10936 | let e: i16x8 = i16x8::new(0x7F_FF, 2, 3, 4, 5, 6, 7, 8); | |
10937 | let r: i16x8 = transmute(vcopyq_lane_p16::<0, 1>(transmute(a), transmute(b))); | |
10938 | assert_eq!(r, e); | |
10939 | } | |
10940 | ||
10941 | #[simd_test(enable = "neon")] | |
10942 | unsafe fn test_vcopyq_lane_s64() { | |
10943 | let a: i64x2 = i64x2::new(1, 2); | |
10944 | let b: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); | |
10945 | let e: i64x2 = i64x2::new(1, 0x7F_FF_FF_FF_FF_FF_FF_FF); | |
10946 | let r: i64x2 = transmute(vcopyq_lane_s64::<1, 0>(transmute(a), transmute(b))); | |
10947 | assert_eq!(r, e); | |
10948 | } | |
10949 | ||
10950 | #[simd_test(enable = "neon")] | |
10951 | unsafe fn test_vcopyq_lane_u64() { | |
10952 | let a: u64x2 = u64x2::new(1, 2); | |
10953 | let b: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10954 | let e: u64x2 = u64x2::new(1, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
10955 | let r: u64x2 = transmute(vcopyq_lane_u64::<1, 0>(transmute(a), transmute(b))); | |
10956 | assert_eq!(r, e); | |
10957 | } | |
10958 | ||
10959 | #[simd_test(enable = "neon")] | |
10960 | unsafe fn test_vcopyq_lane_p64() { | |
10961 | let a: i64x2 = i64x2::new(1, 2); | |
10962 | let b: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); | |
10963 | let e: i64x2 = i64x2::new(1, 0x7F_FF_FF_FF_FF_FF_FF_FF); | |
10964 | let r: i64x2 = transmute(vcopyq_lane_p64::<1, 0>(transmute(a), transmute(b))); | |
10965 | assert_eq!(r, e); | |
10966 | } | |
10967 | ||
10968 | #[simd_test(enable = "neon")] | |
10969 | unsafe fn test_vcopyq_lane_f32() { | |
10970 | let a: f32x4 = f32x4::new(1., 2., 3., 4.); | |
10971 | let b: f32x2 = f32x2::new(0.5, 0.); | |
10972 | let e: f32x4 = f32x4::new(1., 0.5, 3., 4.); | |
10973 | let r: f32x4 = transmute(vcopyq_lane_f32::<1, 0>(transmute(a), transmute(b))); | |
10974 | assert_eq!(r, e); | |
10975 | } | |
10976 | ||
10977 | #[simd_test(enable = "neon")] | |
10978 | unsafe fn test_vcopyq_lane_f64() { | |
10979 | let a: f64x2 = f64x2::new(1., 2.); | |
10980 | let b: f64 = 0.5; | |
10981 | let e: f64x2 = f64x2::new(1., 0.5); | |
10982 | let r: f64x2 = transmute(vcopyq_lane_f64::<1, 0>(transmute(a), transmute(b))); | |
10983 | assert_eq!(r, e); | |
10984 | } | |
10985 | ||
10986 | #[simd_test(enable = "neon")] | |
10987 | unsafe fn test_vcreate_f64() { | |
10988 | let a: u64 = 0; | |
10989 | let e: f64 = 0.; | |
10990 | let r: f64 = transmute(vcreate_f64(transmute(a))); | |
10991 | assert_eq!(r, e); | |
10992 | } | |
10993 | ||
10994 | #[simd_test(enable = "neon")] | |
10995 | unsafe fn test_vcvt_f64_s64() { | |
10996 | let a: i64x1 = i64x1::new(1); | |
10997 | let e: f64 = 1.; | |
10998 | let r: f64 = transmute(vcvt_f64_s64(transmute(a))); | |
10999 | assert_eq!(r, e); | |
11000 | } | |
11001 | ||
11002 | #[simd_test(enable = "neon")] | |
11003 | unsafe fn test_vcvtq_f64_s64() { | |
11004 | let a: i64x2 = i64x2::new(1, 2); | |
11005 | let e: f64x2 = f64x2::new(1., 2.); | |
11006 | let r: f64x2 = transmute(vcvtq_f64_s64(transmute(a))); | |
11007 | assert_eq!(r, e); | |
11008 | } | |
11009 | ||
11010 | #[simd_test(enable = "neon")] | |
11011 | unsafe fn test_vcvt_f64_u64() { | |
11012 | let a: u64x1 = u64x1::new(1); | |
11013 | let e: f64 = 1.; | |
11014 | let r: f64 = transmute(vcvt_f64_u64(transmute(a))); | |
11015 | assert_eq!(r, e); | |
11016 | } | |
11017 | ||
11018 | #[simd_test(enable = "neon")] | |
11019 | unsafe fn test_vcvtq_f64_u64() { | |
11020 | let a: u64x2 = u64x2::new(1, 2); | |
11021 | let e: f64x2 = f64x2::new(1., 2.); | |
11022 | let r: f64x2 = transmute(vcvtq_f64_u64(transmute(a))); | |
11023 | assert_eq!(r, e); | |
11024 | } | |
11025 | ||
11026 | #[simd_test(enable = "neon")] | |
11027 | unsafe fn test_vcvt_f64_f32() { | |
11028 | let a: f32x2 = f32x2::new(-1.2, 1.2); | |
11029 | let e: f64x2 = f64x2::new(-1.2f32 as f64, 1.2f32 as f64); | |
11030 | let r: f64x2 = transmute(vcvt_f64_f32(transmute(a))); | |
11031 | assert_eq!(r, e); | |
11032 | } | |
11033 | ||
11034 | #[simd_test(enable = "neon")] | |
11035 | unsafe fn test_vcvt_high_f64_f32() { | |
11036 | let a: f32x4 = f32x4::new(-1.2, 1.2, 2.3, 3.4); | |
11037 | let e: f64x2 = f64x2::new(2.3f32 as f64, 3.4f32 as f64); | |
11038 | let r: f64x2 = transmute(vcvt_high_f64_f32(transmute(a))); | |
11039 | assert_eq!(r, e); | |
11040 | } | |
11041 | ||
11042 | #[simd_test(enable = "neon")] | |
11043 | unsafe fn test_vcvt_f32_f64() { | |
11044 | let a: f64x2 = f64x2::new(-1.2, 1.2); | |
11045 | let e: f32x2 = f32x2::new(-1.2f64 as f32, 1.2f64 as f32); | |
11046 | let r: f32x2 = transmute(vcvt_f32_f64(transmute(a))); | |
11047 | assert_eq!(r, e); | |
11048 | } | |
11049 | ||
11050 | #[simd_test(enable = "neon")] | |
11051 | unsafe fn test_vcvt_high_f32_f64() { | |
11052 | let a: f32x2 = f32x2::new(-1.2, 1.2); | |
11053 | let b: f64x2 = f64x2::new(-2.3, 3.4); | |
11054 | let e: f32x4 = f32x4::new(-1.2, 1.2, -2.3f64 as f32, 3.4f64 as f32); | |
11055 | let r: f32x4 = transmute(vcvt_high_f32_f64(transmute(a), transmute(b))); | |
11056 | assert_eq!(r, e); | |
11057 | } | |
11058 | ||
11059 | #[simd_test(enable = "neon")] | |
11060 | unsafe fn test_vcvtx_f32_f64() { | |
11061 | let a: f64x2 = f64x2::new(-1.0, 2.0); | |
11062 | let e: f32x2 = f32x2::new(-1.0, 2.0); | |
11063 | let r: f32x2 = transmute(vcvtx_f32_f64(transmute(a))); | |
11064 | assert_eq!(r, e); | |
11065 | } | |
11066 | ||
11067 | #[simd_test(enable = "neon")] | |
11068 | unsafe fn test_vcvtx_high_f32_f64() { | |
11069 | let a: f32x2 = f32x2::new(-1.0, 2.0); | |
11070 | let b: f64x2 = f64x2::new(-3.0, 4.0); | |
11071 | let e: f32x4 = f32x4::new(-1.0, 2.0, -3.0, 4.0); | |
11072 | let r: f32x4 = transmute(vcvtx_high_f32_f64(transmute(a), transmute(b))); | |
11073 | assert_eq!(r, e); | |
11074 | } | |
11075 | ||
11076 | #[simd_test(enable = "neon")] | |
11077 | unsafe fn test_vcvt_n_f64_s64() { | |
11078 | let a: i64x1 = i64x1::new(1); | |
11079 | let e: f64 = 0.25; | |
11080 | let r: f64 = transmute(vcvt_n_f64_s64::<2>(transmute(a))); | |
11081 | assert_eq!(r, e); | |
11082 | } | |
11083 | ||
11084 | #[simd_test(enable = "neon")] | |
11085 | unsafe fn test_vcvtq_n_f64_s64() { | |
11086 | let a: i64x2 = i64x2::new(1, 2); | |
11087 | let e: f64x2 = f64x2::new(0.25, 0.5); | |
11088 | let r: f64x2 = transmute(vcvtq_n_f64_s64::<2>(transmute(a))); | |
11089 | assert_eq!(r, e); | |
11090 | } | |
11091 | ||
11092 | #[simd_test(enable = "neon")] | |
11093 | unsafe fn test_vcvts_n_f32_s32() { | |
11094 | let a: i32 = 1; | |
11095 | let e: f32 = 0.25; | |
11096 | let r: f32 = transmute(vcvts_n_f32_s32::<2>(transmute(a))); | |
11097 | assert_eq!(r, e); | |
11098 | } | |
11099 | ||
11100 | #[simd_test(enable = "neon")] | |
11101 | unsafe fn test_vcvtd_n_f64_s64() { | |
11102 | let a: i64 = 1; | |
11103 | let e: f64 = 0.25; | |
11104 | let r: f64 = transmute(vcvtd_n_f64_s64::<2>(transmute(a))); | |
11105 | assert_eq!(r, e); | |
11106 | } | |
11107 | ||
11108 | #[simd_test(enable = "neon")] | |
11109 | unsafe fn test_vcvt_n_f64_u64() { | |
11110 | let a: u64x1 = u64x1::new(1); | |
11111 | let e: f64 = 0.25; | |
11112 | let r: f64 = transmute(vcvt_n_f64_u64::<2>(transmute(a))); | |
11113 | assert_eq!(r, e); | |
11114 | } | |
11115 | ||
11116 | #[simd_test(enable = "neon")] | |
11117 | unsafe fn test_vcvtq_n_f64_u64() { | |
11118 | let a: u64x2 = u64x2::new(1, 2); | |
11119 | let e: f64x2 = f64x2::new(0.25, 0.5); | |
11120 | let r: f64x2 = transmute(vcvtq_n_f64_u64::<2>(transmute(a))); | |
11121 | assert_eq!(r, e); | |
11122 | } | |
11123 | ||
11124 | #[simd_test(enable = "neon")] | |
11125 | unsafe fn test_vcvts_n_f32_u32() { | |
11126 | let a: u32 = 1; | |
11127 | let e: f32 = 0.25; | |
11128 | let r: f32 = transmute(vcvts_n_f32_u32::<2>(transmute(a))); | |
11129 | assert_eq!(r, e); | |
11130 | } | |
11131 | ||
11132 | #[simd_test(enable = "neon")] | |
11133 | unsafe fn test_vcvtd_n_f64_u64() { | |
11134 | let a: u64 = 1; | |
11135 | let e: f64 = 0.25; | |
11136 | let r: f64 = transmute(vcvtd_n_f64_u64::<2>(transmute(a))); | |
11137 | assert_eq!(r, e); | |
11138 | } | |
11139 | ||
11140 | #[simd_test(enable = "neon")] | |
11141 | unsafe fn test_vcvt_n_s64_f64() { | |
11142 | let a: f64 = 0.25; | |
11143 | let e: i64x1 = i64x1::new(1); | |
11144 | let r: i64x1 = transmute(vcvt_n_s64_f64::<2>(transmute(a))); | |
11145 | assert_eq!(r, e); | |
11146 | } | |
11147 | ||
11148 | #[simd_test(enable = "neon")] | |
11149 | unsafe fn test_vcvtq_n_s64_f64() { | |
11150 | let a: f64x2 = f64x2::new(0.25, 0.5); | |
11151 | let e: i64x2 = i64x2::new(1, 2); | |
11152 | let r: i64x2 = transmute(vcvtq_n_s64_f64::<2>(transmute(a))); | |
11153 | assert_eq!(r, e); | |
11154 | } | |
11155 | ||
11156 | #[simd_test(enable = "neon")] | |
11157 | unsafe fn test_vcvts_n_s32_f32() { | |
11158 | let a: f32 = 0.25; | |
11159 | let e: i32 = 1; | |
11160 | let r: i32 = transmute(vcvts_n_s32_f32::<2>(transmute(a))); | |
11161 | assert_eq!(r, e); | |
11162 | } | |
11163 | ||
11164 | #[simd_test(enable = "neon")] | |
11165 | unsafe fn test_vcvtd_n_s64_f64() { | |
11166 | let a: f64 = 0.25; | |
11167 | let e: i64 = 1; | |
11168 | let r: i64 = transmute(vcvtd_n_s64_f64::<2>(transmute(a))); | |
11169 | assert_eq!(r, e); | |
11170 | } | |
11171 | ||
11172 | #[simd_test(enable = "neon")] | |
11173 | unsafe fn test_vcvt_n_u64_f64() { | |
11174 | let a: f64 = 0.25; | |
11175 | let e: u64x1 = u64x1::new(1); | |
11176 | let r: u64x1 = transmute(vcvt_n_u64_f64::<2>(transmute(a))); | |
11177 | assert_eq!(r, e); | |
11178 | } | |
11179 | ||
11180 | #[simd_test(enable = "neon")] | |
11181 | unsafe fn test_vcvtq_n_u64_f64() { | |
11182 | let a: f64x2 = f64x2::new(0.25, 0.5); | |
11183 | let e: u64x2 = u64x2::new(1, 2); | |
11184 | let r: u64x2 = transmute(vcvtq_n_u64_f64::<2>(transmute(a))); | |
11185 | assert_eq!(r, e); | |
11186 | } | |
11187 | ||
11188 | #[simd_test(enable = "neon")] | |
11189 | unsafe fn test_vcvts_n_u32_f32() { | |
11190 | let a: f32 = 0.25; | |
11191 | let e: u32 = 1; | |
11192 | let r: u32 = transmute(vcvts_n_u32_f32::<2>(transmute(a))); | |
11193 | assert_eq!(r, e); | |
11194 | } | |
11195 | ||
11196 | #[simd_test(enable = "neon")] | |
11197 | unsafe fn test_vcvtd_n_u64_f64() { | |
11198 | let a: f64 = 0.25; | |
11199 | let e: u64 = 1; | |
11200 | let r: u64 = transmute(vcvtd_n_u64_f64::<2>(transmute(a))); | |
11201 | assert_eq!(r, e); | |
11202 | } | |
11203 | ||
11204 | #[simd_test(enable = "neon")] | |
11205 | unsafe fn test_vcvts_f32_s32() { | |
11206 | let a: i32 = 1; | |
11207 | let e: f32 = 1.; | |
11208 | let r: f32 = transmute(vcvts_f32_s32(transmute(a))); | |
11209 | assert_eq!(r, e); | |
11210 | } | |
11211 | ||
11212 | #[simd_test(enable = "neon")] | |
11213 | unsafe fn test_vcvtd_f64_s64() { | |
11214 | let a: i64 = 1; | |
11215 | let e: f64 = 1.; | |
11216 | let r: f64 = transmute(vcvtd_f64_s64(transmute(a))); | |
11217 | assert_eq!(r, e); | |
11218 | } | |
11219 | ||
11220 | #[simd_test(enable = "neon")] | |
11221 | unsafe fn test_vcvts_f32_u32() { | |
11222 | let a: u32 = 1; | |
11223 | let e: f32 = 1.; | |
11224 | let r: f32 = transmute(vcvts_f32_u32(transmute(a))); | |
11225 | assert_eq!(r, e); | |
11226 | } | |
11227 | ||
11228 | #[simd_test(enable = "neon")] | |
11229 | unsafe fn test_vcvtd_f64_u64() { | |
11230 | let a: u64 = 1; | |
11231 | let e: f64 = 1.; | |
11232 | let r: f64 = transmute(vcvtd_f64_u64(transmute(a))); | |
11233 | assert_eq!(r, e); | |
11234 | } | |
11235 | ||
11236 | #[simd_test(enable = "neon")] | |
11237 | unsafe fn test_vcvts_s32_f32() { | |
11238 | let a: f32 = 1.; | |
11239 | let e: i32 = 1; | |
11240 | let r: i32 = transmute(vcvts_s32_f32(transmute(a))); | |
11241 | assert_eq!(r, e); | |
11242 | } | |
11243 | ||
11244 | #[simd_test(enable = "neon")] | |
11245 | unsafe fn test_vcvtd_s64_f64() { | |
11246 | let a: f64 = 1.; | |
11247 | let e: i64 = 1; | |
11248 | let r: i64 = transmute(vcvtd_s64_f64(transmute(a))); | |
11249 | assert_eq!(r, e); | |
11250 | } | |
11251 | ||
11252 | #[simd_test(enable = "neon")] | |
11253 | unsafe fn test_vcvts_u32_f32() { | |
11254 | let a: f32 = 1.; | |
11255 | let e: u32 = 1; | |
11256 | let r: u32 = transmute(vcvts_u32_f32(transmute(a))); | |
11257 | assert_eq!(r, e); | |
11258 | } | |
11259 | ||
11260 | #[simd_test(enable = "neon")] | |
11261 | unsafe fn test_vcvtd_u64_f64() { | |
11262 | let a: f64 = 1.; | |
11263 | let e: u64 = 1; | |
11264 | let r: u64 = transmute(vcvtd_u64_f64(transmute(a))); | |
11265 | assert_eq!(r, e); | |
11266 | } | |
11267 | ||
11268 | #[simd_test(enable = "neon")] | |
11269 | unsafe fn test_vcvt_s64_f64() { | |
11270 | let a: f64 = -1.1; | |
11271 | let e: i64x1 = i64x1::new(-1); | |
11272 | let r: i64x1 = transmute(vcvt_s64_f64(transmute(a))); | |
11273 | assert_eq!(r, e); | |
11274 | } | |
11275 | ||
11276 | #[simd_test(enable = "neon")] | |
11277 | unsafe fn test_vcvtq_s64_f64() { | |
11278 | let a: f64x2 = f64x2::new(-1.1, 2.1); | |
11279 | let e: i64x2 = i64x2::new(-1, 2); | |
11280 | let r: i64x2 = transmute(vcvtq_s64_f64(transmute(a))); | |
11281 | assert_eq!(r, e); | |
11282 | } | |
11283 | ||
11284 | #[simd_test(enable = "neon")] | |
11285 | unsafe fn test_vcvt_u64_f64() { | |
11286 | let a: f64 = 1.1; | |
11287 | let e: u64x1 = u64x1::new(1); | |
11288 | let r: u64x1 = transmute(vcvt_u64_f64(transmute(a))); | |
11289 | assert_eq!(r, e); | |
11290 | } | |
11291 | ||
11292 | #[simd_test(enable = "neon")] | |
11293 | unsafe fn test_vcvtq_u64_f64() { | |
11294 | let a: f64x2 = f64x2::new(1.1, 2.1); | |
11295 | let e: u64x2 = u64x2::new(1, 2); | |
11296 | let r: u64x2 = transmute(vcvtq_u64_f64(transmute(a))); | |
11297 | assert_eq!(r, e); | |
11298 | } | |
11299 | ||
11300 | #[simd_test(enable = "neon")] | |
11301 | unsafe fn test_vcvta_s32_f32() { | |
11302 | let a: f32x2 = f32x2::new(-1.1, 2.1); | |
11303 | let e: i32x2 = i32x2::new(-1, 2); | |
11304 | let r: i32x2 = transmute(vcvta_s32_f32(transmute(a))); | |
11305 | assert_eq!(r, e); | |
11306 | } | |
11307 | ||
11308 | #[simd_test(enable = "neon")] | |
11309 | unsafe fn test_vcvtaq_s32_f32() { | |
11310 | let a: f32x4 = f32x4::new(-1.1, 2.1, -2.9, 3.9); | |
11311 | let e: i32x4 = i32x4::new(-1, 2, -3, 4); | |
11312 | let r: i32x4 = transmute(vcvtaq_s32_f32(transmute(a))); | |
11313 | assert_eq!(r, e); | |
11314 | } | |
11315 | ||
11316 | #[simd_test(enable = "neon")] | |
11317 | unsafe fn test_vcvta_s64_f64() { | |
11318 | let a: f64 = -1.1; | |
11319 | let e: i64x1 = i64x1::new(-1); | |
11320 | let r: i64x1 = transmute(vcvta_s64_f64(transmute(a))); | |
11321 | assert_eq!(r, e); | |
11322 | } | |
11323 | ||
11324 | #[simd_test(enable = "neon")] | |
11325 | unsafe fn test_vcvtaq_s64_f64() { | |
11326 | let a: f64x2 = f64x2::new(-1.1, 2.1); | |
11327 | let e: i64x2 = i64x2::new(-1, 2); | |
11328 | let r: i64x2 = transmute(vcvtaq_s64_f64(transmute(a))); | |
11329 | assert_eq!(r, e); | |
11330 | } | |
11331 | ||
11332 | #[simd_test(enable = "neon")] | |
11333 | unsafe fn test_vcvtas_s32_f32() { | |
11334 | let a: f32 = 2.9; | |
11335 | let e: i32 = 3; | |
11336 | let r: i32 = transmute(vcvtas_s32_f32(transmute(a))); | |
11337 | assert_eq!(r, e); | |
11338 | } | |
11339 | ||
11340 | #[simd_test(enable = "neon")] | |
11341 | unsafe fn test_vcvtad_s64_f64() { | |
11342 | let a: f64 = 2.9; | |
11343 | let e: i64 = 3; | |
11344 | let r: i64 = transmute(vcvtad_s64_f64(transmute(a))); | |
11345 | assert_eq!(r, e); | |
11346 | } | |
11347 | ||
11348 | #[simd_test(enable = "neon")] | |
11349 | unsafe fn test_vcvtas_u32_f32() { | |
11350 | let a: f32 = 2.9; | |
11351 | let e: u32 = 3; | |
11352 | let r: u32 = transmute(vcvtas_u32_f32(transmute(a))); | |
11353 | assert_eq!(r, e); | |
11354 | } | |
11355 | ||
11356 | #[simd_test(enable = "neon")] | |
11357 | unsafe fn test_vcvtad_u64_f64() { | |
11358 | let a: f64 = 2.9; | |
11359 | let e: u64 = 3; | |
11360 | let r: u64 = transmute(vcvtad_u64_f64(transmute(a))); | |
11361 | assert_eq!(r, e); | |
11362 | } | |
11363 | ||
11364 | #[simd_test(enable = "neon")] | |
11365 | unsafe fn test_vcvtn_s32_f32() { | |
11366 | let a: f32x2 = f32x2::new(-1.5, 2.1); | |
11367 | let e: i32x2 = i32x2::new(-2, 2); | |
11368 | let r: i32x2 = transmute(vcvtn_s32_f32(transmute(a))); | |
11369 | assert_eq!(r, e); | |
11370 | } | |
11371 | ||
11372 | #[simd_test(enable = "neon")] | |
11373 | unsafe fn test_vcvtnq_s32_f32() { | |
11374 | let a: f32x4 = f32x4::new(-1.5, 2.1, -2.9, 3.9); | |
11375 | let e: i32x4 = i32x4::new(-2, 2, -3, 4); | |
11376 | let r: i32x4 = transmute(vcvtnq_s32_f32(transmute(a))); | |
11377 | assert_eq!(r, e); | |
11378 | } | |
11379 | ||
11380 | #[simd_test(enable = "neon")] | |
11381 | unsafe fn test_vcvtn_s64_f64() { | |
11382 | let a: f64 = -1.5; | |
11383 | let e: i64x1 = i64x1::new(-2); | |
11384 | let r: i64x1 = transmute(vcvtn_s64_f64(transmute(a))); | |
11385 | assert_eq!(r, e); | |
11386 | } | |
11387 | ||
11388 | #[simd_test(enable = "neon")] | |
11389 | unsafe fn test_vcvtnq_s64_f64() { | |
11390 | let a: f64x2 = f64x2::new(-1.5, 2.1); | |
11391 | let e: i64x2 = i64x2::new(-2, 2); | |
11392 | let r: i64x2 = transmute(vcvtnq_s64_f64(transmute(a))); | |
11393 | assert_eq!(r, e); | |
11394 | } | |
11395 | ||
11396 | #[simd_test(enable = "neon")] | |
11397 | unsafe fn test_vcvtns_s32_f32() { | |
11398 | let a: f32 = -1.5; | |
11399 | let e: i32 = -2; | |
11400 | let r: i32 = transmute(vcvtns_s32_f32(transmute(a))); | |
11401 | assert_eq!(r, e); | |
11402 | } | |
11403 | ||
11404 | #[simd_test(enable = "neon")] | |
11405 | unsafe fn test_vcvtnd_s64_f64() { | |
11406 | let a: f64 = -1.5; | |
11407 | let e: i64 = -2; | |
11408 | let r: i64 = transmute(vcvtnd_s64_f64(transmute(a))); | |
11409 | assert_eq!(r, e); | |
11410 | } | |
11411 | ||
11412 | #[simd_test(enable = "neon")] | |
11413 | unsafe fn test_vcvtm_s32_f32() { | |
11414 | let a: f32x2 = f32x2::new(-1.1, 2.1); | |
11415 | let e: i32x2 = i32x2::new(-2, 2); | |
11416 | let r: i32x2 = transmute(vcvtm_s32_f32(transmute(a))); | |
11417 | assert_eq!(r, e); | |
11418 | } | |
11419 | ||
11420 | #[simd_test(enable = "neon")] | |
11421 | unsafe fn test_vcvtmq_s32_f32() { | |
11422 | let a: f32x4 = f32x4::new(-1.1, 2.1, -2.9, 3.9); | |
11423 | let e: i32x4 = i32x4::new(-2, 2, -3, 3); | |
11424 | let r: i32x4 = transmute(vcvtmq_s32_f32(transmute(a))); | |
11425 | assert_eq!(r, e); | |
11426 | } | |
11427 | ||
11428 | #[simd_test(enable = "neon")] | |
11429 | unsafe fn test_vcvtm_s64_f64() { | |
11430 | let a: f64 = -1.1; | |
11431 | let e: i64x1 = i64x1::new(-2); | |
11432 | let r: i64x1 = transmute(vcvtm_s64_f64(transmute(a))); | |
11433 | assert_eq!(r, e); | |
11434 | } | |
11435 | ||
11436 | #[simd_test(enable = "neon")] | |
11437 | unsafe fn test_vcvtmq_s64_f64() { | |
11438 | let a: f64x2 = f64x2::new(-1.1, 2.1); | |
11439 | let e: i64x2 = i64x2::new(-2, 2); | |
11440 | let r: i64x2 = transmute(vcvtmq_s64_f64(transmute(a))); | |
11441 | assert_eq!(r, e); | |
11442 | } | |
11443 | ||
11444 | #[simd_test(enable = "neon")] | |
11445 | unsafe fn test_vcvtms_s32_f32() { | |
11446 | let a: f32 = -1.1; | |
11447 | let e: i32 = -2; | |
11448 | let r: i32 = transmute(vcvtms_s32_f32(transmute(a))); | |
11449 | assert_eq!(r, e); | |
11450 | } | |
11451 | ||
11452 | #[simd_test(enable = "neon")] | |
11453 | unsafe fn test_vcvtmd_s64_f64() { | |
11454 | let a: f64 = -1.1; | |
11455 | let e: i64 = -2; | |
11456 | let r: i64 = transmute(vcvtmd_s64_f64(transmute(a))); | |
11457 | assert_eq!(r, e); | |
11458 | } | |
11459 | ||
11460 | #[simd_test(enable = "neon")] | |
11461 | unsafe fn test_vcvtp_s32_f32() { | |
11462 | let a: f32x2 = f32x2::new(-1.1, 2.1); | |
11463 | let e: i32x2 = i32x2::new(-1, 3); | |
11464 | let r: i32x2 = transmute(vcvtp_s32_f32(transmute(a))); | |
11465 | assert_eq!(r, e); | |
11466 | } | |
11467 | ||
11468 | #[simd_test(enable = "neon")] | |
11469 | unsafe fn test_vcvtpq_s32_f32() { | |
11470 | let a: f32x4 = f32x4::new(-1.1, 2.1, -2.9, 3.9); | |
11471 | let e: i32x4 = i32x4::new(-1, 3, -2, 4); | |
11472 | let r: i32x4 = transmute(vcvtpq_s32_f32(transmute(a))); | |
11473 | assert_eq!(r, e); | |
11474 | } | |
11475 | ||
11476 | #[simd_test(enable = "neon")] | |
11477 | unsafe fn test_vcvtp_s64_f64() { | |
11478 | let a: f64 = -1.1; | |
11479 | let e: i64x1 = i64x1::new(-1); | |
11480 | let r: i64x1 = transmute(vcvtp_s64_f64(transmute(a))); | |
11481 | assert_eq!(r, e); | |
11482 | } | |
11483 | ||
11484 | #[simd_test(enable = "neon")] | |
11485 | unsafe fn test_vcvtpq_s64_f64() { | |
11486 | let a: f64x2 = f64x2::new(-1.1, 2.1); | |
11487 | let e: i64x2 = i64x2::new(-1, 3); | |
11488 | let r: i64x2 = transmute(vcvtpq_s64_f64(transmute(a))); | |
11489 | assert_eq!(r, e); | |
11490 | } | |
11491 | ||
11492 | #[simd_test(enable = "neon")] | |
11493 | unsafe fn test_vcvtps_s32_f32() { | |
11494 | let a: f32 = -1.1; | |
11495 | let e: i32 = -1; | |
11496 | let r: i32 = transmute(vcvtps_s32_f32(transmute(a))); | |
11497 | assert_eq!(r, e); | |
11498 | } | |
11499 | ||
11500 | #[simd_test(enable = "neon")] | |
11501 | unsafe fn test_vcvtpd_s64_f64() { | |
11502 | let a: f64 = -1.1; | |
11503 | let e: i64 = -1; | |
11504 | let r: i64 = transmute(vcvtpd_s64_f64(transmute(a))); | |
11505 | assert_eq!(r, e); | |
11506 | } | |
11507 | ||
11508 | #[simd_test(enable = "neon")] | |
11509 | unsafe fn test_vcvta_u32_f32() { | |
11510 | let a: f32x2 = f32x2::new(1.1, 2.1); | |
11511 | let e: u32x2 = u32x2::new(1, 2); | |
11512 | let r: u32x2 = transmute(vcvta_u32_f32(transmute(a))); | |
11513 | assert_eq!(r, e); | |
11514 | } | |
11515 | ||
11516 | #[simd_test(enable = "neon")] | |
11517 | unsafe fn test_vcvtaq_u32_f32() { | |
11518 | let a: f32x4 = f32x4::new(1.1, 2.1, 2.9, 3.9); | |
11519 | let e: u32x4 = u32x4::new(1, 2, 3, 4); | |
11520 | let r: u32x4 = transmute(vcvtaq_u32_f32(transmute(a))); | |
11521 | assert_eq!(r, e); | |
11522 | } | |
11523 | ||
11524 | #[simd_test(enable = "neon")] | |
11525 | unsafe fn test_vcvta_u64_f64() { | |
11526 | let a: f64 = 1.1; | |
11527 | let e: u64x1 = u64x1::new(1); | |
11528 | let r: u64x1 = transmute(vcvta_u64_f64(transmute(a))); | |
11529 | assert_eq!(r, e); | |
11530 | } | |
11531 | ||
11532 | #[simd_test(enable = "neon")] | |
11533 | unsafe fn test_vcvtaq_u64_f64() { | |
11534 | let a: f64x2 = f64x2::new(1.1, 2.1); | |
11535 | let e: u64x2 = u64x2::new(1, 2); | |
11536 | let r: u64x2 = transmute(vcvtaq_u64_f64(transmute(a))); | |
11537 | assert_eq!(r, e); | |
11538 | } | |
11539 | ||
11540 | #[simd_test(enable = "neon")] | |
11541 | unsafe fn test_vcvtn_u32_f32() { | |
11542 | let a: f32x2 = f32x2::new(1.5, 2.1); | |
11543 | let e: u32x2 = u32x2::new(2, 2); | |
11544 | let r: u32x2 = transmute(vcvtn_u32_f32(transmute(a))); | |
11545 | assert_eq!(r, e); | |
11546 | } | |
11547 | ||
11548 | #[simd_test(enable = "neon")] | |
11549 | unsafe fn test_vcvtnq_u32_f32() { | |
11550 | let a: f32x4 = f32x4::new(1.5, 2.1, 2.9, 3.9); | |
11551 | let e: u32x4 = u32x4::new(2, 2, 3, 4); | |
11552 | let r: u32x4 = transmute(vcvtnq_u32_f32(transmute(a))); | |
11553 | assert_eq!(r, e); | |
11554 | } | |
11555 | ||
11556 | #[simd_test(enable = "neon")] | |
11557 | unsafe fn test_vcvtn_u64_f64() { | |
11558 | let a: f64 = 1.5; | |
11559 | let e: u64x1 = u64x1::new(2); | |
11560 | let r: u64x1 = transmute(vcvtn_u64_f64(transmute(a))); | |
11561 | assert_eq!(r, e); | |
11562 | } | |
11563 | ||
11564 | #[simd_test(enable = "neon")] | |
11565 | unsafe fn test_vcvtnq_u64_f64() { | |
11566 | let a: f64x2 = f64x2::new(1.5, 2.1); | |
11567 | let e: u64x2 = u64x2::new(2, 2); | |
11568 | let r: u64x2 = transmute(vcvtnq_u64_f64(transmute(a))); | |
11569 | assert_eq!(r, e); | |
11570 | } | |
11571 | ||
11572 | #[simd_test(enable = "neon")] | |
11573 | unsafe fn test_vcvtns_u32_f32() { | |
11574 | let a: f32 = 1.5; | |
11575 | let e: u32 = 2; | |
11576 | let r: u32 = transmute(vcvtns_u32_f32(transmute(a))); | |
11577 | assert_eq!(r, e); | |
11578 | } | |
11579 | ||
11580 | #[simd_test(enable = "neon")] | |
11581 | unsafe fn test_vcvtnd_u64_f64() { | |
11582 | let a: f64 = 1.5; | |
11583 | let e: u64 = 2; | |
11584 | let r: u64 = transmute(vcvtnd_u64_f64(transmute(a))); | |
11585 | assert_eq!(r, e); | |
11586 | } | |
11587 | ||
11588 | #[simd_test(enable = "neon")] | |
11589 | unsafe fn test_vcvtm_u32_f32() { | |
11590 | let a: f32x2 = f32x2::new(1.1, 2.1); | |
11591 | let e: u32x2 = u32x2::new(1, 2); | |
11592 | let r: u32x2 = transmute(vcvtm_u32_f32(transmute(a))); | |
11593 | assert_eq!(r, e); | |
11594 | } | |
11595 | ||
11596 | #[simd_test(enable = "neon")] | |
11597 | unsafe fn test_vcvtmq_u32_f32() { | |
11598 | let a: f32x4 = f32x4::new(1.1, 2.1, 2.9, 3.9); | |
11599 | let e: u32x4 = u32x4::new(1, 2, 2, 3); | |
11600 | let r: u32x4 = transmute(vcvtmq_u32_f32(transmute(a))); | |
11601 | assert_eq!(r, e); | |
11602 | } | |
11603 | ||
11604 | #[simd_test(enable = "neon")] | |
11605 | unsafe fn test_vcvtm_u64_f64() { | |
11606 | let a: f64 = 1.1; | |
11607 | let e: u64x1 = u64x1::new(1); | |
11608 | let r: u64x1 = transmute(vcvtm_u64_f64(transmute(a))); | |
11609 | assert_eq!(r, e); | |
11610 | } | |
11611 | ||
11612 | #[simd_test(enable = "neon")] | |
11613 | unsafe fn test_vcvtmq_u64_f64() { | |
11614 | let a: f64x2 = f64x2::new(1.1, 2.1); | |
11615 | let e: u64x2 = u64x2::new(1, 2); | |
11616 | let r: u64x2 = transmute(vcvtmq_u64_f64(transmute(a))); | |
11617 | assert_eq!(r, e); | |
11618 | } | |
11619 | ||
11620 | #[simd_test(enable = "neon")] | |
11621 | unsafe fn test_vcvtms_u32_f32() { | |
11622 | let a: f32 = 1.1; | |
11623 | let e: u32 = 1; | |
11624 | let r: u32 = transmute(vcvtms_u32_f32(transmute(a))); | |
11625 | assert_eq!(r, e); | |
11626 | } | |
11627 | ||
11628 | #[simd_test(enable = "neon")] | |
11629 | unsafe fn test_vcvtmd_u64_f64() { | |
11630 | let a: f64 = 1.1; | |
11631 | let e: u64 = 1; | |
11632 | let r: u64 = transmute(vcvtmd_u64_f64(transmute(a))); | |
11633 | assert_eq!(r, e); | |
11634 | } | |
11635 | ||
11636 | #[simd_test(enable = "neon")] | |
11637 | unsafe fn test_vcvtp_u32_f32() { | |
11638 | let a: f32x2 = f32x2::new(1.1, 2.1); | |
11639 | let e: u32x2 = u32x2::new(2, 3); | |
11640 | let r: u32x2 = transmute(vcvtp_u32_f32(transmute(a))); | |
11641 | assert_eq!(r, e); | |
11642 | } | |
11643 | ||
11644 | #[simd_test(enable = "neon")] | |
11645 | unsafe fn test_vcvtpq_u32_f32() { | |
11646 | let a: f32x4 = f32x4::new(1.1, 2.1, 2.9, 3.9); | |
11647 | let e: u32x4 = u32x4::new(2, 3, 3, 4); | |
11648 | let r: u32x4 = transmute(vcvtpq_u32_f32(transmute(a))); | |
11649 | assert_eq!(r, e); | |
11650 | } | |
11651 | ||
11652 | #[simd_test(enable = "neon")] | |
11653 | unsafe fn test_vcvtp_u64_f64() { | |
11654 | let a: f64 = 1.1; | |
11655 | let e: u64x1 = u64x1::new(2); | |
11656 | let r: u64x1 = transmute(vcvtp_u64_f64(transmute(a))); | |
11657 | assert_eq!(r, e); | |
11658 | } | |
11659 | ||
11660 | #[simd_test(enable = "neon")] | |
11661 | unsafe fn test_vcvtpq_u64_f64() { | |
11662 | let a: f64x2 = f64x2::new(1.1, 2.1); | |
11663 | let e: u64x2 = u64x2::new(2, 3); | |
11664 | let r: u64x2 = transmute(vcvtpq_u64_f64(transmute(a))); | |
11665 | assert_eq!(r, e); | |
11666 | } | |
11667 | ||
11668 | #[simd_test(enable = "neon")] | |
11669 | unsafe fn test_vcvtps_u32_f32() { | |
11670 | let a: f32 = 1.1; | |
11671 | let e: u32 = 2; | |
11672 | let r: u32 = transmute(vcvtps_u32_f32(transmute(a))); | |
11673 | assert_eq!(r, e); | |
11674 | } | |
11675 | ||
11676 | #[simd_test(enable = "neon")] | |
11677 | unsafe fn test_vcvtpd_u64_f64() { | |
11678 | let a: f64 = 1.1; | |
11679 | let e: u64 = 2; | |
11680 | let r: u64 = transmute(vcvtpd_u64_f64(transmute(a))); | |
11681 | assert_eq!(r, e); | |
11682 | } | |
11683 | ||
11684 | #[simd_test(enable = "neon")] | |
11685 | unsafe fn test_vdupq_laneq_p64() { | |
11686 | let a: i64x2 = i64x2::new(1, 1); | |
11687 | let e: i64x2 = i64x2::new(1, 1); | |
11688 | let r: i64x2 = transmute(vdupq_laneq_p64::<1>(transmute(a))); | |
11689 | assert_eq!(r, e); | |
11690 | } | |
11691 | ||
11692 | #[simd_test(enable = "neon")] | |
11693 | unsafe fn test_vdupq_lane_p64() { | |
11694 | let a: i64x1 = i64x1::new(1); | |
11695 | let e: i64x2 = i64x2::new(1, 1); | |
11696 | let r: i64x2 = transmute(vdupq_lane_p64::<0>(transmute(a))); | |
11697 | assert_eq!(r, e); | |
11698 | } | |
11699 | ||
11700 | #[simd_test(enable = "neon")] | |
11701 | unsafe fn test_vdupq_laneq_f64() { | |
11702 | let a: f64x2 = f64x2::new(1., 1.); | |
11703 | let e: f64x2 = f64x2::new(1., 1.); | |
11704 | let r: f64x2 = transmute(vdupq_laneq_f64::<1>(transmute(a))); | |
11705 | assert_eq!(r, e); | |
11706 | } | |
11707 | ||
11708 | #[simd_test(enable = "neon")] | |
11709 | unsafe fn test_vdupq_lane_f64() { | |
11710 | let a: f64 = 1.; | |
11711 | let e: f64x2 = f64x2::new(1., 1.); | |
11712 | let r: f64x2 = transmute(vdupq_lane_f64::<0>(transmute(a))); | |
11713 | assert_eq!(r, e); | |
11714 | } | |
11715 | ||
11716 | #[simd_test(enable = "neon")] | |
11717 | unsafe fn test_vdup_lane_p64() { | |
11718 | let a: i64x1 = i64x1::new(0); | |
11719 | let e: i64x1 = i64x1::new(0); | |
11720 | let r: i64x1 = transmute(vdup_lane_p64::<0>(transmute(a))); | |
11721 | assert_eq!(r, e); | |
11722 | } | |
11723 | ||
11724 | #[simd_test(enable = "neon")] | |
11725 | unsafe fn test_vdup_lane_f64() { | |
11726 | let a: f64 = 0.; | |
11727 | let e: f64 = 0.; | |
11728 | let r: f64 = transmute(vdup_lane_f64::<0>(transmute(a))); | |
11729 | assert_eq!(r, e); | |
11730 | } | |
11731 | ||
11732 | #[simd_test(enable = "neon")] | |
11733 | unsafe fn test_vdup_laneq_p64() { | |
11734 | let a: i64x2 = i64x2::new(0, 1); | |
11735 | let e: i64x1 = i64x1::new(1); | |
11736 | let r: i64x1 = transmute(vdup_laneq_p64::<1>(transmute(a))); | |
11737 | assert_eq!(r, e); | |
11738 | } | |
11739 | ||
11740 | #[simd_test(enable = "neon")] | |
11741 | unsafe fn test_vdup_laneq_f64() { | |
11742 | let a: f64x2 = f64x2::new(0., 1.); | |
11743 | let e: f64 = 1.; | |
11744 | let r: f64 = transmute(vdup_laneq_f64::<1>(transmute(a))); | |
11745 | assert_eq!(r, e); | |
11746 | } | |
11747 | ||
11748 | #[simd_test(enable = "neon")] | |
11749 | unsafe fn test_vdupb_lane_s8() { | |
11750 | let a: i8x8 = i8x8::new(1, 1, 1, 4, 1, 6, 7, 8); | |
11751 | let e: i8 = 1; | |
11752 | let r: i8 = transmute(vdupb_lane_s8::<4>(transmute(a))); | |
11753 | assert_eq!(r, e); | |
11754 | } | |
11755 | ||
11756 | #[simd_test(enable = "neon")] | |
11757 | unsafe fn test_vdupb_laneq_s8() { | |
11758 | let a: i8x16 = i8x16::new(1, 1, 1, 4, 1, 6, 7, 8, 1, 10, 11, 12, 13, 14, 15, 16); | |
11759 | let e: i8 = 1; | |
11760 | let r: i8 = transmute(vdupb_laneq_s8::<8>(transmute(a))); | |
11761 | assert_eq!(r, e); | |
11762 | } | |
11763 | ||
11764 | #[simd_test(enable = "neon")] | |
11765 | unsafe fn test_vduph_lane_s16() { | |
11766 | let a: i16x4 = i16x4::new(1, 1, 1, 4); | |
11767 | let e: i16 = 1; | |
11768 | let r: i16 = transmute(vduph_lane_s16::<2>(transmute(a))); | |
11769 | assert_eq!(r, e); | |
11770 | } | |
11771 | ||
11772 | #[simd_test(enable = "neon")] | |
11773 | unsafe fn test_vduph_laneq_s16() { | |
11774 | let a: i16x8 = i16x8::new(1, 1, 1, 4, 1, 6, 7, 8); | |
11775 | let e: i16 = 1; | |
11776 | let r: i16 = transmute(vduph_laneq_s16::<4>(transmute(a))); | |
11777 | assert_eq!(r, e); | |
11778 | } | |
11779 | ||
11780 | #[simd_test(enable = "neon")] | |
11781 | unsafe fn test_vdups_lane_s32() { | |
11782 | let a: i32x2 = i32x2::new(1, 1); | |
11783 | let e: i32 = 1; | |
11784 | let r: i32 = transmute(vdups_lane_s32::<1>(transmute(a))); | |
11785 | assert_eq!(r, e); | |
11786 | } | |
11787 | ||
11788 | #[simd_test(enable = "neon")] | |
11789 | unsafe fn test_vdups_laneq_s32() { | |
11790 | let a: i32x4 = i32x4::new(1, 1, 1, 4); | |
11791 | let e: i32 = 1; | |
11792 | let r: i32 = transmute(vdups_laneq_s32::<2>(transmute(a))); | |
11793 | assert_eq!(r, e); | |
11794 | } | |
11795 | ||
11796 | #[simd_test(enable = "neon")] | |
11797 | unsafe fn test_vdupd_lane_s64() { | |
11798 | let a: i64x1 = i64x1::new(1); | |
11799 | let e: i64 = 1; | |
11800 | let r: i64 = transmute(vdupd_lane_s64::<0>(transmute(a))); | |
11801 | assert_eq!(r, e); | |
11802 | } | |
11803 | ||
11804 | #[simd_test(enable = "neon")] | |
11805 | unsafe fn test_vdupd_laneq_s64() { | |
11806 | let a: i64x2 = i64x2::new(1, 1); | |
11807 | let e: i64 = 1; | |
11808 | let r: i64 = transmute(vdupd_laneq_s64::<1>(transmute(a))); | |
11809 | assert_eq!(r, e); | |
11810 | } | |
11811 | ||
11812 | #[simd_test(enable = "neon")] | |
11813 | unsafe fn test_vdupb_lane_u8() { | |
11814 | let a: u8x8 = u8x8::new(1, 1, 1, 4, 1, 6, 7, 8); | |
11815 | let e: u8 = 1; | |
11816 | let r: u8 = transmute(vdupb_lane_u8::<4>(transmute(a))); | |
11817 | assert_eq!(r, e); | |
11818 | } | |
11819 | ||
11820 | #[simd_test(enable = "neon")] | |
11821 | unsafe fn test_vdupb_laneq_u8() { | |
11822 | let a: u8x16 = u8x16::new(1, 1, 1, 4, 1, 6, 7, 8, 1, 10, 11, 12, 13, 14, 15, 16); | |
11823 | let e: u8 = 1; | |
11824 | let r: u8 = transmute(vdupb_laneq_u8::<8>(transmute(a))); | |
11825 | assert_eq!(r, e); | |
11826 | } | |
11827 | ||
11828 | #[simd_test(enable = "neon")] | |
11829 | unsafe fn test_vduph_lane_u16() { | |
11830 | let a: u16x4 = u16x4::new(1, 1, 1, 4); | |
11831 | let e: u16 = 1; | |
11832 | let r: u16 = transmute(vduph_lane_u16::<2>(transmute(a))); | |
11833 | assert_eq!(r, e); | |
11834 | } | |
11835 | ||
11836 | #[simd_test(enable = "neon")] | |
11837 | unsafe fn test_vduph_laneq_u16() { | |
11838 | let a: u16x8 = u16x8::new(1, 1, 1, 4, 1, 6, 7, 8); | |
11839 | let e: u16 = 1; | |
11840 | let r: u16 = transmute(vduph_laneq_u16::<4>(transmute(a))); | |
11841 | assert_eq!(r, e); | |
11842 | } | |
11843 | ||
11844 | #[simd_test(enable = "neon")] | |
11845 | unsafe fn test_vdups_lane_u32() { | |
11846 | let a: u32x2 = u32x2::new(1, 1); | |
11847 | let e: u32 = 1; | |
11848 | let r: u32 = transmute(vdups_lane_u32::<1>(transmute(a))); | |
11849 | assert_eq!(r, e); | |
11850 | } | |
11851 | ||
11852 | #[simd_test(enable = "neon")] | |
11853 | unsafe fn test_vdups_laneq_u32() { | |
11854 | let a: u32x4 = u32x4::new(1, 1, 1, 4); | |
11855 | let e: u32 = 1; | |
11856 | let r: u32 = transmute(vdups_laneq_u32::<2>(transmute(a))); | |
11857 | assert_eq!(r, e); | |
11858 | } | |
11859 | ||
11860 | #[simd_test(enable = "neon")] | |
11861 | unsafe fn test_vdupd_lane_u64() { | |
11862 | let a: u64x1 = u64x1::new(1); | |
11863 | let e: u64 = 1; | |
11864 | let r: u64 = transmute(vdupd_lane_u64::<0>(transmute(a))); | |
11865 | assert_eq!(r, e); | |
11866 | } | |
11867 | ||
11868 | #[simd_test(enable = "neon")] | |
11869 | unsafe fn test_vdupd_laneq_u64() { | |
11870 | let a: u64x2 = u64x2::new(1, 1); | |
11871 | let e: u64 = 1; | |
11872 | let r: u64 = transmute(vdupd_laneq_u64::<1>(transmute(a))); | |
11873 | assert_eq!(r, e); | |
11874 | } | |
11875 | ||
11876 | #[simd_test(enable = "neon")] | |
11877 | unsafe fn test_vdupb_lane_p8() { | |
11878 | let a: i8x8 = i8x8::new(1, 1, 1, 4, 1, 6, 7, 8); | |
11879 | let e: p8 = 1; | |
11880 | let r: p8 = transmute(vdupb_lane_p8::<4>(transmute(a))); | |
11881 | assert_eq!(r, e); | |
11882 | } | |
11883 | ||
11884 | #[simd_test(enable = "neon")] | |
11885 | unsafe fn test_vdupb_laneq_p8() { | |
11886 | let a: i8x16 = i8x16::new(1, 1, 1, 4, 1, 6, 7, 8, 1, 10, 11, 12, 13, 14, 15, 16); | |
11887 | let e: p8 = 1; | |
11888 | let r: p8 = transmute(vdupb_laneq_p8::<8>(transmute(a))); | |
11889 | assert_eq!(r, e); | |
11890 | } | |
11891 | ||
11892 | #[simd_test(enable = "neon")] | |
11893 | unsafe fn test_vduph_lane_p16() { | |
11894 | let a: i16x4 = i16x4::new(1, 1, 1, 4); | |
11895 | let e: p16 = 1; | |
11896 | let r: p16 = transmute(vduph_lane_p16::<2>(transmute(a))); | |
11897 | assert_eq!(r, e); | |
11898 | } | |
11899 | ||
11900 | #[simd_test(enable = "neon")] | |
11901 | unsafe fn test_vduph_laneq_p16() { | |
11902 | let a: i16x8 = i16x8::new(1, 1, 1, 4, 1, 6, 7, 8); | |
11903 | let e: p16 = 1; | |
11904 | let r: p16 = transmute(vduph_laneq_p16::<4>(transmute(a))); | |
11905 | assert_eq!(r, e); | |
11906 | } | |
11907 | ||
11908 | #[simd_test(enable = "neon")] | |
11909 | unsafe fn test_vdups_lane_f32() { | |
11910 | let a: f32x2 = f32x2::new(1., 1.); | |
11911 | let e: f32 = 1.; | |
11912 | let r: f32 = transmute(vdups_lane_f32::<1>(transmute(a))); | |
11913 | assert_eq!(r, e); | |
11914 | } | |
11915 | ||
11916 | #[simd_test(enable = "neon")] | |
11917 | unsafe fn test_vdups_laneq_f32() { | |
11918 | let a: f32x4 = f32x4::new(1., 1., 1., 4.); | |
11919 | let e: f32 = 1.; | |
11920 | let r: f32 = transmute(vdups_laneq_f32::<2>(transmute(a))); | |
11921 | assert_eq!(r, e); | |
11922 | } | |
11923 | ||
11924 | #[simd_test(enable = "neon")] | |
11925 | unsafe fn test_vdupd_lane_f64() { | |
11926 | let a: f64 = 1.; | |
11927 | let e: f64 = 1.; | |
11928 | let r: f64 = transmute(vdupd_lane_f64::<0>(transmute(a))); | |
11929 | assert_eq!(r, e); | |
11930 | } | |
11931 | ||
11932 | #[simd_test(enable = "neon")] | |
11933 | unsafe fn test_vdupd_laneq_f64() { | |
11934 | let a: f64x2 = f64x2::new(1., 1.); | |
11935 | let e: f64 = 1.; | |
11936 | let r: f64 = transmute(vdupd_laneq_f64::<1>(transmute(a))); | |
11937 | assert_eq!(r, e); | |
11938 | } | |
11939 | ||
11940 | #[simd_test(enable = "neon")] | |
11941 | unsafe fn test_vextq_p64() { | |
11942 | let a: i64x2 = i64x2::new(0, 8); | |
11943 | let b: i64x2 = i64x2::new(9, 11); | |
11944 | let e: i64x2 = i64x2::new(8, 9); | |
11945 | let r: i64x2 = transmute(vextq_p64::<1>(transmute(a), transmute(b))); | |
11946 | assert_eq!(r, e); | |
11947 | } | |
11948 | ||
11949 | #[simd_test(enable = "neon")] | |
11950 | unsafe fn test_vextq_f64() { | |
11951 | let a: f64x2 = f64x2::new(0., 2.); | |
11952 | let b: f64x2 = f64x2::new(3., 4.); | |
11953 | let e: f64x2 = f64x2::new(2., 3.); | |
11954 | let r: f64x2 = transmute(vextq_f64::<1>(transmute(a), transmute(b))); | |
11955 | assert_eq!(r, e); | |
11956 | } | |
11957 | ||
11958 | #[simd_test(enable = "neon")] | |
11959 | unsafe fn test_vmla_f64() { | |
11960 | let a: f64 = 0.; | |
11961 | let b: f64 = 2.; | |
11962 | let c: f64 = 3.; | |
11963 | let e: f64 = 6.; | |
11964 | let r: f64 = transmute(vmla_f64(transmute(a), transmute(b), transmute(c))); | |
11965 | assert_eq!(r, e); | |
11966 | } | |
11967 | ||
11968 | #[simd_test(enable = "neon")] | |
11969 | unsafe fn test_vmlaq_f64() { | |
11970 | let a: f64x2 = f64x2::new(0., 1.); | |
11971 | let b: f64x2 = f64x2::new(2., 2.); | |
11972 | let c: f64x2 = f64x2::new(3., 3.); | |
11973 | let e: f64x2 = f64x2::new(6., 7.); | |
11974 | let r: f64x2 = transmute(vmlaq_f64(transmute(a), transmute(b), transmute(c))); | |
11975 | assert_eq!(r, e); | |
11976 | } | |
11977 | ||
11978 | #[simd_test(enable = "neon")] | |
11979 | unsafe fn test_vmlal_high_s8() { | |
11980 | let a: i16x8 = i16x8::new(8, 7, 6, 5, 4, 3, 2, 1); | |
11981 | let b: i8x16 = i8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); | |
11982 | let c: i8x16 = i8x16::new(3, 3, 0, 1, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7); | |
11983 | let e: i16x8 = i16x8::new(8, 9, 10, 11, 12, 13, 14, 15); | |
11984 | let r: i16x8 = transmute(vmlal_high_s8(transmute(a), transmute(b), transmute(c))); | |
11985 | assert_eq!(r, e); | |
11986 | } | |
11987 | ||
11988 | #[simd_test(enable = "neon")] | |
11989 | unsafe fn test_vmlal_high_s16() { | |
11990 | let a: i32x4 = i32x4::new(8, 7, 6, 5); | |
11991 | let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); | |
11992 | let c: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
11993 | let e: i32x4 = i32x4::new(8, 9, 10, 11); | |
11994 | let r: i32x4 = transmute(vmlal_high_s16(transmute(a), transmute(b), transmute(c))); | |
11995 | assert_eq!(r, e); | |
11996 | } | |
11997 | ||
11998 | #[simd_test(enable = "neon")] | |
11999 | unsafe fn test_vmlal_high_s32() { | |
12000 | let a: i64x2 = i64x2::new(8, 7); | |
12001 | let b: i32x4 = i32x4::new(2, 2, 2, 2); | |
12002 | let c: i32x4 = i32x4::new(3, 3, 0, 1); | |
12003 | let e: i64x2 = i64x2::new(8, 9); | |
12004 | let r: i64x2 = transmute(vmlal_high_s32(transmute(a), transmute(b), transmute(c))); | |
12005 | assert_eq!(r, e); | |
12006 | } | |
12007 | ||
12008 | #[simd_test(enable = "neon")] | |
12009 | unsafe fn test_vmlal_high_u8() { | |
12010 | let a: u16x8 = u16x8::new(8, 7, 6, 5, 4, 3, 2, 1); | |
12011 | let b: u8x16 = u8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); | |
12012 | let c: u8x16 = u8x16::new(3, 3, 0, 1, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7); | |
12013 | let e: u16x8 = u16x8::new(8, 9, 10, 11, 12, 13, 14, 15); | |
12014 | let r: u16x8 = transmute(vmlal_high_u8(transmute(a), transmute(b), transmute(c))); | |
12015 | assert_eq!(r, e); | |
12016 | } | |
12017 | ||
12018 | #[simd_test(enable = "neon")] | |
12019 | unsafe fn test_vmlal_high_u16() { | |
12020 | let a: u32x4 = u32x4::new(8, 7, 6, 5); | |
12021 | let b: u16x8 = u16x8::new(2, 2, 2, 2, 2, 2, 2, 2); | |
12022 | let c: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12023 | let e: u32x4 = u32x4::new(8, 9, 10, 11); | |
12024 | let r: u32x4 = transmute(vmlal_high_u16(transmute(a), transmute(b), transmute(c))); | |
12025 | assert_eq!(r, e); | |
12026 | } | |
12027 | ||
12028 | #[simd_test(enable = "neon")] | |
12029 | unsafe fn test_vmlal_high_u32() { | |
12030 | let a: u64x2 = u64x2::new(8, 7); | |
12031 | let b: u32x4 = u32x4::new(2, 2, 2, 2); | |
12032 | let c: u32x4 = u32x4::new(3, 3, 0, 1); | |
12033 | let e: u64x2 = u64x2::new(8, 9); | |
12034 | let r: u64x2 = transmute(vmlal_high_u32(transmute(a), transmute(b), transmute(c))); | |
12035 | assert_eq!(r, e); | |
12036 | } | |
12037 | ||
12038 | #[simd_test(enable = "neon")] | |
12039 | unsafe fn test_vmlal_high_n_s16() { | |
12040 | let a: i32x4 = i32x4::new(8, 7, 6, 5); | |
12041 | let b: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12042 | let c: i16 = 2; | |
12043 | let e: i32x4 = i32x4::new(8, 9, 10, 11); | |
12044 | let r: i32x4 = transmute(vmlal_high_n_s16(transmute(a), transmute(b), transmute(c))); | |
12045 | assert_eq!(r, e); | |
12046 | } | |
12047 | ||
12048 | #[simd_test(enable = "neon")] | |
12049 | unsafe fn test_vmlal_high_n_s32() { | |
12050 | let a: i64x2 = i64x2::new(8, 7); | |
12051 | let b: i32x4 = i32x4::new(3, 3, 0, 1); | |
12052 | let c: i32 = 2; | |
12053 | let e: i64x2 = i64x2::new(8, 9); | |
12054 | let r: i64x2 = transmute(vmlal_high_n_s32(transmute(a), transmute(b), transmute(c))); | |
12055 | assert_eq!(r, e); | |
12056 | } | |
12057 | ||
12058 | #[simd_test(enable = "neon")] | |
12059 | unsafe fn test_vmlal_high_n_u16() { | |
12060 | let a: u32x4 = u32x4::new(8, 7, 6, 5); | |
12061 | let b: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12062 | let c: u16 = 2; | |
12063 | let e: u32x4 = u32x4::new(8, 9, 10, 11); | |
12064 | let r: u32x4 = transmute(vmlal_high_n_u16(transmute(a), transmute(b), transmute(c))); | |
12065 | assert_eq!(r, e); | |
12066 | } | |
12067 | ||
12068 | #[simd_test(enable = "neon")] | |
12069 | unsafe fn test_vmlal_high_n_u32() { | |
12070 | let a: u64x2 = u64x2::new(8, 7); | |
12071 | let b: u32x4 = u32x4::new(3, 3, 0, 1); | |
12072 | let c: u32 = 2; | |
12073 | let e: u64x2 = u64x2::new(8, 9); | |
12074 | let r: u64x2 = transmute(vmlal_high_n_u32(transmute(a), transmute(b), transmute(c))); | |
12075 | assert_eq!(r, e); | |
12076 | } | |
12077 | ||
12078 | #[simd_test(enable = "neon")] | |
12079 | unsafe fn test_vmlal_high_lane_s16() { | |
12080 | let a: i32x4 = i32x4::new(8, 7, 6, 5); | |
12081 | let b: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12082 | let c: i16x4 = i16x4::new(0, 2, 0, 0); | |
12083 | let e: i32x4 = i32x4::new(8, 9, 10, 11); | |
12084 | let r: i32x4 = transmute(vmlal_high_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
12085 | assert_eq!(r, e); | |
12086 | } | |
12087 | ||
12088 | #[simd_test(enable = "neon")] | |
12089 | unsafe fn test_vmlal_high_laneq_s16() { | |
12090 | let a: i32x4 = i32x4::new(8, 7, 6, 5); | |
12091 | let b: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12092 | let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
12093 | let e: i32x4 = i32x4::new(8, 9, 10, 11); | |
12094 | let r: i32x4 = transmute(vmlal_high_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
12095 | assert_eq!(r, e); | |
12096 | } | |
12097 | ||
12098 | #[simd_test(enable = "neon")] | |
12099 | unsafe fn test_vmlal_high_lane_s32() { | |
12100 | let a: i64x2 = i64x2::new(8, 7); | |
12101 | let b: i32x4 = i32x4::new(3, 3, 0, 1); | |
12102 | let c: i32x2 = i32x2::new(0, 2); | |
12103 | let e: i64x2 = i64x2::new(8, 9); | |
12104 | let r: i64x2 = transmute(vmlal_high_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
12105 | assert_eq!(r, e); | |
12106 | } | |
12107 | ||
12108 | #[simd_test(enable = "neon")] | |
12109 | unsafe fn test_vmlal_high_laneq_s32() { | |
12110 | let a: i64x2 = i64x2::new(8, 7); | |
12111 | let b: i32x4 = i32x4::new(3, 3, 0, 1); | |
12112 | let c: i32x4 = i32x4::new(0, 2, 0, 0); | |
12113 | let e: i64x2 = i64x2::new(8, 9); | |
12114 | let r: i64x2 = transmute(vmlal_high_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
12115 | assert_eq!(r, e); | |
12116 | } | |
12117 | ||
12118 | #[simd_test(enable = "neon")] | |
12119 | unsafe fn test_vmlal_high_lane_u16() { | |
12120 | let a: u32x4 = u32x4::new(8, 7, 6, 5); | |
12121 | let b: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12122 | let c: u16x4 = u16x4::new(0, 2, 0, 0); | |
12123 | let e: u32x4 = u32x4::new(8, 9, 10, 11); | |
12124 | let r: u32x4 = transmute(vmlal_high_lane_u16::<1>(transmute(a), transmute(b), transmute(c))); | |
12125 | assert_eq!(r, e); | |
12126 | } | |
12127 | ||
12128 | #[simd_test(enable = "neon")] | |
12129 | unsafe fn test_vmlal_high_laneq_u16() { | |
12130 | let a: u32x4 = u32x4::new(8, 7, 6, 5); | |
12131 | let b: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12132 | let c: u16x8 = u16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
12133 | let e: u32x4 = u32x4::new(8, 9, 10, 11); | |
12134 | let r: u32x4 = transmute(vmlal_high_laneq_u16::<1>(transmute(a), transmute(b), transmute(c))); | |
12135 | assert_eq!(r, e); | |
12136 | } | |
12137 | ||
12138 | #[simd_test(enable = "neon")] | |
12139 | unsafe fn test_vmlal_high_lane_u32() { | |
12140 | let a: u64x2 = u64x2::new(8, 7); | |
12141 | let b: u32x4 = u32x4::new(3, 3, 0, 1); | |
12142 | let c: u32x2 = u32x2::new(0, 2); | |
12143 | let e: u64x2 = u64x2::new(8, 9); | |
12144 | let r: u64x2 = transmute(vmlal_high_lane_u32::<1>(transmute(a), transmute(b), transmute(c))); | |
12145 | assert_eq!(r, e); | |
12146 | } | |
12147 | ||
12148 | #[simd_test(enable = "neon")] | |
12149 | unsafe fn test_vmlal_high_laneq_u32() { | |
12150 | let a: u64x2 = u64x2::new(8, 7); | |
12151 | let b: u32x4 = u32x4::new(3, 3, 0, 1); | |
12152 | let c: u32x4 = u32x4::new(0, 2, 0, 0); | |
12153 | let e: u64x2 = u64x2::new(8, 9); | |
12154 | let r: u64x2 = transmute(vmlal_high_laneq_u32::<1>(transmute(a), transmute(b), transmute(c))); | |
12155 | assert_eq!(r, e); | |
12156 | } | |
12157 | ||
12158 | #[simd_test(enable = "neon")] | |
12159 | unsafe fn test_vmls_f64() { | |
12160 | let a: f64 = 6.; | |
12161 | let b: f64 = 2.; | |
12162 | let c: f64 = 3.; | |
12163 | let e: f64 = 0.; | |
12164 | let r: f64 = transmute(vmls_f64(transmute(a), transmute(b), transmute(c))); | |
12165 | assert_eq!(r, e); | |
12166 | } | |
12167 | ||
12168 | #[simd_test(enable = "neon")] | |
12169 | unsafe fn test_vmlsq_f64() { | |
12170 | let a: f64x2 = f64x2::new(6., 7.); | |
12171 | let b: f64x2 = f64x2::new(2., 2.); | |
12172 | let c: f64x2 = f64x2::new(3., 3.); | |
12173 | let e: f64x2 = f64x2::new(0., 1.); | |
12174 | let r: f64x2 = transmute(vmlsq_f64(transmute(a), transmute(b), transmute(c))); | |
12175 | assert_eq!(r, e); | |
12176 | } | |
12177 | ||
12178 | #[simd_test(enable = "neon")] | |
12179 | unsafe fn test_vmlsl_high_s8() { | |
12180 | let a: i16x8 = i16x8::new(14, 15, 16, 17, 18, 19, 20, 21); | |
12181 | let b: i8x16 = i8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); | |
12182 | let c: i8x16 = i8x16::new(3, 3, 0, 1, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7); | |
12183 | let e: i16x8 = i16x8::new(14, 13, 12, 11, 10, 9, 8, 7); | |
12184 | let r: i16x8 = transmute(vmlsl_high_s8(transmute(a), transmute(b), transmute(c))); | |
12185 | assert_eq!(r, e); | |
12186 | } | |
12187 | ||
12188 | #[simd_test(enable = "neon")] | |
12189 | unsafe fn test_vmlsl_high_s16() { | |
12190 | let a: i32x4 = i32x4::new(14, 15, 16, 17); | |
12191 | let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); | |
12192 | let c: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12193 | let e: i32x4 = i32x4::new(14, 13, 12, 11); | |
12194 | let r: i32x4 = transmute(vmlsl_high_s16(transmute(a), transmute(b), transmute(c))); | |
12195 | assert_eq!(r, e); | |
12196 | } | |
12197 | ||
12198 | #[simd_test(enable = "neon")] | |
12199 | unsafe fn test_vmlsl_high_s32() { | |
12200 | let a: i64x2 = i64x2::new(14, 15); | |
12201 | let b: i32x4 = i32x4::new(2, 2, 2, 2); | |
12202 | let c: i32x4 = i32x4::new(3, 3, 0, 1); | |
12203 | let e: i64x2 = i64x2::new(14, 13); | |
12204 | let r: i64x2 = transmute(vmlsl_high_s32(transmute(a), transmute(b), transmute(c))); | |
12205 | assert_eq!(r, e); | |
12206 | } | |
12207 | ||
12208 | #[simd_test(enable = "neon")] | |
12209 | unsafe fn test_vmlsl_high_u8() { | |
12210 | let a: u16x8 = u16x8::new(14, 15, 16, 17, 18, 19, 20, 21); | |
12211 | let b: u8x16 = u8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); | |
12212 | let c: u8x16 = u8x16::new(3, 3, 0, 1, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7); | |
12213 | let e: u16x8 = u16x8::new(14, 13, 12, 11, 10, 9, 8, 7); | |
12214 | let r: u16x8 = transmute(vmlsl_high_u8(transmute(a), transmute(b), transmute(c))); | |
12215 | assert_eq!(r, e); | |
12216 | } | |
12217 | ||
12218 | #[simd_test(enable = "neon")] | |
12219 | unsafe fn test_vmlsl_high_u16() { | |
12220 | let a: u32x4 = u32x4::new(14, 15, 16, 17); | |
12221 | let b: u16x8 = u16x8::new(2, 2, 2, 2, 2, 2, 2, 2); | |
12222 | let c: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12223 | let e: u32x4 = u32x4::new(14, 13, 12, 11); | |
12224 | let r: u32x4 = transmute(vmlsl_high_u16(transmute(a), transmute(b), transmute(c))); | |
12225 | assert_eq!(r, e); | |
12226 | } | |
12227 | ||
12228 | #[simd_test(enable = "neon")] | |
12229 | unsafe fn test_vmlsl_high_u32() { | |
12230 | let a: u64x2 = u64x2::new(14, 15); | |
12231 | let b: u32x4 = u32x4::new(2, 2, 2, 2); | |
12232 | let c: u32x4 = u32x4::new(3, 3, 0, 1); | |
12233 | let e: u64x2 = u64x2::new(14, 13); | |
12234 | let r: u64x2 = transmute(vmlsl_high_u32(transmute(a), transmute(b), transmute(c))); | |
12235 | assert_eq!(r, e); | |
12236 | } | |
12237 | ||
12238 | #[simd_test(enable = "neon")] | |
12239 | unsafe fn test_vmlsl_high_n_s16() { | |
12240 | let a: i32x4 = i32x4::new(14, 15, 16, 17); | |
12241 | let b: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12242 | let c: i16 = 2; | |
12243 | let e: i32x4 = i32x4::new(14, 13, 12, 11); | |
12244 | let r: i32x4 = transmute(vmlsl_high_n_s16(transmute(a), transmute(b), transmute(c))); | |
12245 | assert_eq!(r, e); | |
12246 | } | |
12247 | ||
12248 | #[simd_test(enable = "neon")] | |
12249 | unsafe fn test_vmlsl_high_n_s32() { | |
12250 | let a: i64x2 = i64x2::new(14, 15); | |
12251 | let b: i32x4 = i32x4::new(3, 3, 0, 1); | |
12252 | let c: i32 = 2; | |
12253 | let e: i64x2 = i64x2::new(14, 13); | |
12254 | let r: i64x2 = transmute(vmlsl_high_n_s32(transmute(a), transmute(b), transmute(c))); | |
12255 | assert_eq!(r, e); | |
12256 | } | |
12257 | ||
12258 | #[simd_test(enable = "neon")] | |
12259 | unsafe fn test_vmlsl_high_n_u16() { | |
12260 | let a: u32x4 = u32x4::new(14, 15, 16, 17); | |
12261 | let b: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12262 | let c: u16 = 2; | |
12263 | let e: u32x4 = u32x4::new(14, 13, 12, 11); | |
12264 | let r: u32x4 = transmute(vmlsl_high_n_u16(transmute(a), transmute(b), transmute(c))); | |
12265 | assert_eq!(r, e); | |
12266 | } | |
12267 | ||
12268 | #[simd_test(enable = "neon")] | |
12269 | unsafe fn test_vmlsl_high_n_u32() { | |
12270 | let a: u64x2 = u64x2::new(14, 15); | |
12271 | let b: u32x4 = u32x4::new(3, 3, 0, 1); | |
12272 | let c: u32 = 2; | |
12273 | let e: u64x2 = u64x2::new(14, 13); | |
12274 | let r: u64x2 = transmute(vmlsl_high_n_u32(transmute(a), transmute(b), transmute(c))); | |
12275 | assert_eq!(r, e); | |
12276 | } | |
12277 | ||
12278 | #[simd_test(enable = "neon")] | |
12279 | unsafe fn test_vmlsl_high_lane_s16() { | |
12280 | let a: i32x4 = i32x4::new(14, 15, 16, 17); | |
12281 | let b: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12282 | let c: i16x4 = i16x4::new(0, 2, 0, 0); | |
12283 | let e: i32x4 = i32x4::new(14, 13, 12, 11); | |
12284 | let r: i32x4 = transmute(vmlsl_high_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
12285 | assert_eq!(r, e); | |
12286 | } | |
12287 | ||
12288 | #[simd_test(enable = "neon")] | |
12289 | unsafe fn test_vmlsl_high_laneq_s16() { | |
12290 | let a: i32x4 = i32x4::new(14, 15, 16, 17); | |
12291 | let b: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12292 | let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
12293 | let e: i32x4 = i32x4::new(14, 13, 12, 11); | |
12294 | let r: i32x4 = transmute(vmlsl_high_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
12295 | assert_eq!(r, e); | |
12296 | } | |
12297 | ||
12298 | #[simd_test(enable = "neon")] | |
12299 | unsafe fn test_vmlsl_high_lane_s32() { | |
12300 | let a: i64x2 = i64x2::new(14, 15); | |
12301 | let b: i32x4 = i32x4::new(3, 3, 0, 1); | |
12302 | let c: i32x2 = i32x2::new(0, 2); | |
12303 | let e: i64x2 = i64x2::new(14, 13); | |
12304 | let r: i64x2 = transmute(vmlsl_high_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
12305 | assert_eq!(r, e); | |
12306 | } | |
12307 | ||
12308 | #[simd_test(enable = "neon")] | |
12309 | unsafe fn test_vmlsl_high_laneq_s32() { | |
12310 | let a: i64x2 = i64x2::new(14, 15); | |
12311 | let b: i32x4 = i32x4::new(3, 3, 0, 1); | |
12312 | let c: i32x4 = i32x4::new(0, 2, 0, 0); | |
12313 | let e: i64x2 = i64x2::new(14, 13); | |
12314 | let r: i64x2 = transmute(vmlsl_high_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
12315 | assert_eq!(r, e); | |
12316 | } | |
12317 | ||
12318 | #[simd_test(enable = "neon")] | |
12319 | unsafe fn test_vmlsl_high_lane_u16() { | |
12320 | let a: u32x4 = u32x4::new(14, 15, 16, 17); | |
12321 | let b: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12322 | let c: u16x4 = u16x4::new(0, 2, 0, 0); | |
12323 | let e: u32x4 = u32x4::new(14, 13, 12, 11); | |
12324 | let r: u32x4 = transmute(vmlsl_high_lane_u16::<1>(transmute(a), transmute(b), transmute(c))); | |
12325 | assert_eq!(r, e); | |
12326 | } | |
12327 | ||
12328 | #[simd_test(enable = "neon")] | |
12329 | unsafe fn test_vmlsl_high_laneq_u16() { | |
12330 | let a: u32x4 = u32x4::new(14, 15, 16, 17); | |
12331 | let b: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); | |
12332 | let c: u16x8 = u16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
12333 | let e: u32x4 = u32x4::new(14, 13, 12, 11); | |
12334 | let r: u32x4 = transmute(vmlsl_high_laneq_u16::<1>(transmute(a), transmute(b), transmute(c))); | |
12335 | assert_eq!(r, e); | |
12336 | } | |
12337 | ||
12338 | #[simd_test(enable = "neon")] | |
12339 | unsafe fn test_vmlsl_high_lane_u32() { | |
12340 | let a: u64x2 = u64x2::new(14, 15); | |
12341 | let b: u32x4 = u32x4::new(3, 3, 0, 1); | |
12342 | let c: u32x2 = u32x2::new(0, 2); | |
12343 | let e: u64x2 = u64x2::new(14, 13); | |
12344 | let r: u64x2 = transmute(vmlsl_high_lane_u32::<1>(transmute(a), transmute(b), transmute(c))); | |
12345 | assert_eq!(r, e); | |
12346 | } | |
12347 | ||
12348 | #[simd_test(enable = "neon")] | |
12349 | unsafe fn test_vmlsl_high_laneq_u32() { | |
12350 | let a: u64x2 = u64x2::new(14, 15); | |
12351 | let b: u32x4 = u32x4::new(3, 3, 0, 1); | |
12352 | let c: u32x4 = u32x4::new(0, 2, 0, 0); | |
12353 | let e: u64x2 = u64x2::new(14, 13); | |
12354 | let r: u64x2 = transmute(vmlsl_high_laneq_u32::<1>(transmute(a), transmute(b), transmute(c))); | |
12355 | assert_eq!(r, e); | |
12356 | } | |
12357 | ||
12358 | #[simd_test(enable = "neon")] | |
12359 | unsafe fn test_vmovn_high_s16() { | |
12360 | let a: i8x8 = i8x8::new(0, 1, 2, 3, 2, 3, 4, 5); | |
12361 | let b: i16x8 = i16x8::new(2, 3, 4, 5, 12, 13, 14, 15); | |
12362 | let e: i8x16 = i8x16::new(0, 1, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 12, 13, 14, 15); | |
12363 | let r: i8x16 = transmute(vmovn_high_s16(transmute(a), transmute(b))); | |
12364 | assert_eq!(r, e); | |
12365 | } | |
12366 | ||
12367 | #[simd_test(enable = "neon")] | |
12368 | unsafe fn test_vmovn_high_s32() { | |
12369 | let a: i16x4 = i16x4::new(0, 1, 2, 3); | |
12370 | let b: i32x4 = i32x4::new(2, 3, 4, 5); | |
12371 | let e: i16x8 = i16x8::new(0, 1, 2, 3, 2, 3, 4, 5); | |
12372 | let r: i16x8 = transmute(vmovn_high_s32(transmute(a), transmute(b))); | |
12373 | assert_eq!(r, e); | |
12374 | } | |
12375 | ||
12376 | #[simd_test(enable = "neon")] | |
12377 | unsafe fn test_vmovn_high_s64() { | |
12378 | let a: i32x2 = i32x2::new(0, 1); | |
12379 | let b: i64x2 = i64x2::new(2, 3); | |
12380 | let e: i32x4 = i32x4::new(0, 1, 2, 3); | |
12381 | let r: i32x4 = transmute(vmovn_high_s64(transmute(a), transmute(b))); | |
12382 | assert_eq!(r, e); | |
12383 | } | |
12384 | ||
12385 | #[simd_test(enable = "neon")] | |
12386 | unsafe fn test_vmovn_high_u16() { | |
12387 | let a: u8x8 = u8x8::new(0, 1, 2, 3, 2, 3, 4, 5); | |
12388 | let b: u16x8 = u16x8::new(2, 3, 4, 5, 12, 13, 14, 15); | |
12389 | let e: u8x16 = u8x16::new(0, 1, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 12, 13, 14, 15); | |
12390 | let r: u8x16 = transmute(vmovn_high_u16(transmute(a), transmute(b))); | |
12391 | assert_eq!(r, e); | |
12392 | } | |
12393 | ||
12394 | #[simd_test(enable = "neon")] | |
12395 | unsafe fn test_vmovn_high_u32() { | |
12396 | let a: u16x4 = u16x4::new(0, 1, 2, 3); | |
12397 | let b: u32x4 = u32x4::new(2, 3, 4, 5); | |
12398 | let e: u16x8 = u16x8::new(0, 1, 2, 3, 2, 3, 4, 5); | |
12399 | let r: u16x8 = transmute(vmovn_high_u32(transmute(a), transmute(b))); | |
12400 | assert_eq!(r, e); | |
12401 | } | |
12402 | ||
12403 | #[simd_test(enable = "neon")] | |
12404 | unsafe fn test_vmovn_high_u64() { | |
12405 | let a: u32x2 = u32x2::new(0, 1); | |
12406 | let b: u64x2 = u64x2::new(2, 3); | |
12407 | let e: u32x4 = u32x4::new(0, 1, 2, 3); | |
12408 | let r: u32x4 = transmute(vmovn_high_u64(transmute(a), transmute(b))); | |
12409 | assert_eq!(r, e); | |
12410 | } | |
12411 | ||
12412 | #[simd_test(enable = "neon")] | |
12413 | unsafe fn test_vneg_s64() { | |
12414 | let a: i64x1 = i64x1::new(0); | |
12415 | let e: i64x1 = i64x1::new(0); | |
12416 | let r: i64x1 = transmute(vneg_s64(transmute(a))); | |
12417 | assert_eq!(r, e); | |
12418 | } | |
12419 | ||
12420 | #[simd_test(enable = "neon")] | |
12421 | unsafe fn test_vnegq_s64() { | |
12422 | let a: i64x2 = i64x2::new(0, 1); | |
12423 | let e: i64x2 = i64x2::new(0, -1); | |
12424 | let r: i64x2 = transmute(vnegq_s64(transmute(a))); | |
12425 | assert_eq!(r, e); | |
12426 | } | |
12427 | ||
12428 | #[simd_test(enable = "neon")] | |
12429 | unsafe fn test_vneg_f64() { | |
12430 | let a: f64 = 0.; | |
12431 | let e: f64 = 0.; | |
12432 | let r: f64 = transmute(vneg_f64(transmute(a))); | |
12433 | assert_eq!(r, e); | |
12434 | } | |
12435 | ||
12436 | #[simd_test(enable = "neon")] | |
12437 | unsafe fn test_vnegq_f64() { | |
12438 | let a: f64x2 = f64x2::new(0., 1.); | |
12439 | let e: f64x2 = f64x2::new(0., -1.); | |
12440 | let r: f64x2 = transmute(vnegq_f64(transmute(a))); | |
12441 | assert_eq!(r, e); | |
12442 | } | |
12443 | ||
12444 | #[simd_test(enable = "neon")] | |
12445 | unsafe fn test_vqneg_s64() { | |
12446 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
12447 | let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); | |
12448 | let r: i64x1 = transmute(vqneg_s64(transmute(a))); | |
12449 | assert_eq!(r, e); | |
12450 | } | |
12451 | ||
12452 | #[simd_test(enable = "neon")] | |
12453 | unsafe fn test_vqnegq_s64() { | |
12454 | let a: i64x2 = i64x2::new(-9223372036854775808, 0); | |
12455 | let e: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 0); | |
12456 | let r: i64x2 = transmute(vqnegq_s64(transmute(a))); | |
12457 | assert_eq!(r, e); | |
12458 | } | |
12459 | ||
12460 | #[simd_test(enable = "neon")] | |
12461 | unsafe fn test_vqsubb_s8() { | |
12462 | let a: i8 = 42; | |
12463 | let b: i8 = 1; | |
12464 | let e: i8 = 41; | |
12465 | let r: i8 = transmute(vqsubb_s8(transmute(a), transmute(b))); | |
12466 | assert_eq!(r, e); | |
12467 | } | |
12468 | ||
12469 | #[simd_test(enable = "neon")] | |
12470 | unsafe fn test_vqsubh_s16() { | |
12471 | let a: i16 = 42; | |
12472 | let b: i16 = 1; | |
12473 | let e: i16 = 41; | |
12474 | let r: i16 = transmute(vqsubh_s16(transmute(a), transmute(b))); | |
12475 | assert_eq!(r, e); | |
12476 | } | |
12477 | ||
12478 | #[simd_test(enable = "neon")] | |
12479 | unsafe fn test_vqsubb_u8() { | |
12480 | let a: u8 = 42; | |
12481 | let b: u8 = 1; | |
12482 | let e: u8 = 41; | |
12483 | let r: u8 = transmute(vqsubb_u8(transmute(a), transmute(b))); | |
12484 | assert_eq!(r, e); | |
12485 | } | |
12486 | ||
12487 | #[simd_test(enable = "neon")] | |
12488 | unsafe fn test_vqsubh_u16() { | |
12489 | let a: u16 = 42; | |
12490 | let b: u16 = 1; | |
12491 | let e: u16 = 41; | |
12492 | let r: u16 = transmute(vqsubh_u16(transmute(a), transmute(b))); | |
12493 | assert_eq!(r, e); | |
12494 | } | |
12495 | ||
12496 | #[simd_test(enable = "neon")] | |
12497 | unsafe fn test_vqsubs_u32() { | |
12498 | let a: u32 = 42; | |
12499 | let b: u32 = 1; | |
12500 | let e: u32 = 41; | |
12501 | let r: u32 = transmute(vqsubs_u32(transmute(a), transmute(b))); | |
12502 | assert_eq!(r, e); | |
12503 | } | |
12504 | ||
12505 | #[simd_test(enable = "neon")] | |
12506 | unsafe fn test_vqsubd_u64() { | |
12507 | let a: u64 = 42; | |
12508 | let b: u64 = 1; | |
12509 | let e: u64 = 41; | |
12510 | let r: u64 = transmute(vqsubd_u64(transmute(a), transmute(b))); | |
12511 | assert_eq!(r, e); | |
12512 | } | |
12513 | ||
12514 | #[simd_test(enable = "neon")] | |
12515 | unsafe fn test_vqsubs_s32() { | |
12516 | let a: i32 = 42; | |
12517 | let b: i32 = 1; | |
12518 | let e: i32 = 41; | |
12519 | let r: i32 = transmute(vqsubs_s32(transmute(a), transmute(b))); | |
12520 | assert_eq!(r, e); | |
12521 | } | |
12522 | ||
12523 | #[simd_test(enable = "neon")] | |
12524 | unsafe fn test_vqsubd_s64() { | |
12525 | let a: i64 = 42; | |
12526 | let b: i64 = 1; | |
12527 | let e: i64 = 41; | |
12528 | let r: i64 = transmute(vqsubd_s64(transmute(a), transmute(b))); | |
12529 | assert_eq!(r, e); | |
12530 | } | |
12531 | ||
12532 | #[simd_test(enable = "neon")] | |
12533 | unsafe fn test_vrbit_s8() { | |
12534 | let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
12535 | let e: i8x8 = i8x8::new(0, 64, 32, 96, 16, 80, 48, 112); | |
12536 | let r: i8x8 = transmute(vrbit_s8(transmute(a))); | |
12537 | assert_eq!(r, e); | |
12538 | } | |
12539 | ||
12540 | #[simd_test(enable = "neon")] | |
12541 | unsafe fn test_vrbitq_s8() { | |
12542 | let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
12543 | let e: i8x16 = i8x16::new(0, 64, 32, 96, 16, 80, 48, 112, 8, 72, 40, 104, 24, 88, 56, 120); | |
12544 | let r: i8x16 = transmute(vrbitq_s8(transmute(a))); | |
12545 | assert_eq!(r, e); | |
12546 | } | |
12547 | ||
12548 | #[simd_test(enable = "neon")] | |
12549 | unsafe fn test_vrbit_u8() { | |
12550 | let a: u8x8 = u8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
12551 | let e: u8x8 = u8x8::new(0, 64, 32, 96, 16, 80, 48, 112); | |
12552 | let r: u8x8 = transmute(vrbit_u8(transmute(a))); | |
12553 | assert_eq!(r, e); | |
12554 | } | |
12555 | ||
12556 | #[simd_test(enable = "neon")] | |
12557 | unsafe fn test_vrbitq_u8() { | |
12558 | let a: u8x16 = u8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
12559 | let e: u8x16 = u8x16::new(0, 64, 32, 96, 16, 80, 48, 112, 8, 72, 40, 104, 24, 88, 56, 120); | |
12560 | let r: u8x16 = transmute(vrbitq_u8(transmute(a))); | |
12561 | assert_eq!(r, e); | |
12562 | } | |
12563 | ||
12564 | #[simd_test(enable = "neon")] | |
12565 | unsafe fn test_vrbit_p8() { | |
12566 | let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
12567 | let e: i8x8 = i8x8::new(0, 64, 32, 96, 16, 80, 48, 112); | |
12568 | let r: i8x8 = transmute(vrbit_p8(transmute(a))); | |
12569 | assert_eq!(r, e); | |
12570 | } | |
12571 | ||
12572 | #[simd_test(enable = "neon")] | |
12573 | unsafe fn test_vrbitq_p8() { | |
12574 | let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
12575 | let e: i8x16 = i8x16::new(0, 64, 32, 96, 16, 80, 48, 112, 8, 72, 40, 104, 24, 88, 56, 120); | |
12576 | let r: i8x16 = transmute(vrbitq_p8(transmute(a))); | |
12577 | assert_eq!(r, e); | |
12578 | } | |
12579 | ||
12580 | #[simd_test(enable = "neon")] | |
12581 | unsafe fn test_vrndx_f32() { | |
12582 | let a: f32x2 = f32x2::new(-1.5, 0.5); | |
12583 | let e: f32x2 = f32x2::new(-2.0, 0.0); | |
12584 | let r: f32x2 = transmute(vrndx_f32(transmute(a))); | |
12585 | assert_eq!(r, e); | |
12586 | } | |
12587 | ||
12588 | #[simd_test(enable = "neon")] | |
12589 | unsafe fn test_vrndxq_f32() { | |
12590 | let a: f32x4 = f32x4::new(-1.5, 0.5, 1.5, 2.5); | |
12591 | let e: f32x4 = f32x4::new(-2.0, 0.0, 2.0, 2.0); | |
12592 | let r: f32x4 = transmute(vrndxq_f32(transmute(a))); | |
12593 | assert_eq!(r, e); | |
12594 | } | |
12595 | ||
12596 | #[simd_test(enable = "neon")] | |
12597 | unsafe fn test_vrndx_f64() { | |
12598 | let a: f64 = -1.5; | |
12599 | let e: f64 = -2.0; | |
12600 | let r: f64 = transmute(vrndx_f64(transmute(a))); | |
12601 | assert_eq!(r, e); | |
12602 | } | |
12603 | ||
12604 | #[simd_test(enable = "neon")] | |
12605 | unsafe fn test_vrndxq_f64() { | |
12606 | let a: f64x2 = f64x2::new(-1.5, 0.5); | |
12607 | let e: f64x2 = f64x2::new(-2.0, 0.0); | |
12608 | let r: f64x2 = transmute(vrndxq_f64(transmute(a))); | |
12609 | assert_eq!(r, e); | |
12610 | } | |
12611 | ||
12612 | #[simd_test(enable = "neon")] | |
12613 | unsafe fn test_vrnda_f32() { | |
12614 | let a: f32x2 = f32x2::new(-1.5, 0.5); | |
12615 | let e: f32x2 = f32x2::new(-2.0, 1.0); | |
12616 | let r: f32x2 = transmute(vrnda_f32(transmute(a))); | |
12617 | assert_eq!(r, e); | |
12618 | } | |
12619 | ||
12620 | #[simd_test(enable = "neon")] | |
12621 | unsafe fn test_vrndaq_f32() { | |
12622 | let a: f32x4 = f32x4::new(-1.5, 0.5, 1.5, 2.5); | |
12623 | let e: f32x4 = f32x4::new(-2.0, 1.0, 2.0, 3.0); | |
12624 | let r: f32x4 = transmute(vrndaq_f32(transmute(a))); | |
12625 | assert_eq!(r, e); | |
12626 | } | |
12627 | ||
12628 | #[simd_test(enable = "neon")] | |
12629 | unsafe fn test_vrnda_f64() { | |
12630 | let a: f64 = -1.5; | |
12631 | let e: f64 = -2.0; | |
12632 | let r: f64 = transmute(vrnda_f64(transmute(a))); | |
12633 | assert_eq!(r, e); | |
12634 | } | |
12635 | ||
12636 | #[simd_test(enable = "neon")] | |
12637 | unsafe fn test_vrndaq_f64() { | |
12638 | let a: f64x2 = f64x2::new(-1.5, 0.5); | |
12639 | let e: f64x2 = f64x2::new(-2.0, 1.0); | |
12640 | let r: f64x2 = transmute(vrndaq_f64(transmute(a))); | |
12641 | assert_eq!(r, e); | |
12642 | } | |
12643 | ||
12644 | #[simd_test(enable = "neon")] | |
12645 | unsafe fn test_vrndn_f64() { | |
12646 | let a: f64 = -1.5; | |
12647 | let e: f64 = -2.0; | |
12648 | let r: f64 = transmute(vrndn_f64(transmute(a))); | |
12649 | assert_eq!(r, e); | |
12650 | } | |
12651 | ||
12652 | #[simd_test(enable = "neon")] | |
12653 | unsafe fn test_vrndnq_f64() { | |
12654 | let a: f64x2 = f64x2::new(-1.5, 0.5); | |
12655 | let e: f64x2 = f64x2::new(-2.0, 0.0); | |
12656 | let r: f64x2 = transmute(vrndnq_f64(transmute(a))); | |
12657 | assert_eq!(r, e); | |
12658 | } | |
12659 | ||
12660 | #[simd_test(enable = "neon")] | |
12661 | unsafe fn test_vrndm_f32() { | |
12662 | let a: f32x2 = f32x2::new(-1.5, 0.5); | |
12663 | let e: f32x2 = f32x2::new(-2.0, 0.0); | |
12664 | let r: f32x2 = transmute(vrndm_f32(transmute(a))); | |
12665 | assert_eq!(r, e); | |
12666 | } | |
12667 | ||
12668 | #[simd_test(enable = "neon")] | |
12669 | unsafe fn test_vrndmq_f32() { | |
12670 | let a: f32x4 = f32x4::new(-1.5, 0.5, 1.5, 2.5); | |
12671 | let e: f32x4 = f32x4::new(-2.0, 0.0, 1.0, 2.0); | |
12672 | let r: f32x4 = transmute(vrndmq_f32(transmute(a))); | |
12673 | assert_eq!(r, e); | |
12674 | } | |
12675 | ||
12676 | #[simd_test(enable = "neon")] | |
12677 | unsafe fn test_vrndm_f64() { | |
12678 | let a: f64 = -1.5; | |
12679 | let e: f64 = -2.0; | |
12680 | let r: f64 = transmute(vrndm_f64(transmute(a))); | |
12681 | assert_eq!(r, e); | |
12682 | } | |
12683 | ||
12684 | #[simd_test(enable = "neon")] | |
12685 | unsafe fn test_vrndmq_f64() { | |
12686 | let a: f64x2 = f64x2::new(-1.5, 0.5); | |
12687 | let e: f64x2 = f64x2::new(-2.0, 0.0); | |
12688 | let r: f64x2 = transmute(vrndmq_f64(transmute(a))); | |
12689 | assert_eq!(r, e); | |
12690 | } | |
12691 | ||
12692 | #[simd_test(enable = "neon")] | |
12693 | unsafe fn test_vrndp_f32() { | |
12694 | let a: f32x2 = f32x2::new(-1.5, 0.5); | |
12695 | let e: f32x2 = f32x2::new(-1.0, 1.0); | |
12696 | let r: f32x2 = transmute(vrndp_f32(transmute(a))); | |
12697 | assert_eq!(r, e); | |
12698 | } | |
12699 | ||
12700 | #[simd_test(enable = "neon")] | |
12701 | unsafe fn test_vrndpq_f32() { | |
12702 | let a: f32x4 = f32x4::new(-1.5, 0.5, 1.5, 2.5); | |
12703 | let e: f32x4 = f32x4::new(-1.0, 1.0, 2.0, 3.0); | |
12704 | let r: f32x4 = transmute(vrndpq_f32(transmute(a))); | |
12705 | assert_eq!(r, e); | |
12706 | } | |
12707 | ||
12708 | #[simd_test(enable = "neon")] | |
12709 | unsafe fn test_vrndp_f64() { | |
12710 | let a: f64 = -1.5; | |
12711 | let e: f64 = -1.0; | |
12712 | let r: f64 = transmute(vrndp_f64(transmute(a))); | |
12713 | assert_eq!(r, e); | |
12714 | } | |
12715 | ||
12716 | #[simd_test(enable = "neon")] | |
12717 | unsafe fn test_vrndpq_f64() { | |
12718 | let a: f64x2 = f64x2::new(-1.5, 0.5); | |
12719 | let e: f64x2 = f64x2::new(-1.0, 1.0); | |
12720 | let r: f64x2 = transmute(vrndpq_f64(transmute(a))); | |
12721 | assert_eq!(r, e); | |
12722 | } | |
12723 | ||
12724 | #[simd_test(enable = "neon")] | |
12725 | unsafe fn test_vrnd_f32() { | |
12726 | let a: f32x2 = f32x2::new(-1.5, 0.5); | |
12727 | let e: f32x2 = f32x2::new(-1.0, 0.0); | |
12728 | let r: f32x2 = transmute(vrnd_f32(transmute(a))); | |
12729 | assert_eq!(r, e); | |
12730 | } | |
12731 | ||
12732 | #[simd_test(enable = "neon")] | |
12733 | unsafe fn test_vrndq_f32() { | |
12734 | let a: f32x4 = f32x4::new(-1.5, 0.5, 1.5, 2.5); | |
12735 | let e: f32x4 = f32x4::new(-1.0, 0.0, 1.0, 2.0); | |
12736 | let r: f32x4 = transmute(vrndq_f32(transmute(a))); | |
12737 | assert_eq!(r, e); | |
12738 | } | |
12739 | ||
12740 | #[simd_test(enable = "neon")] | |
12741 | unsafe fn test_vrnd_f64() { | |
12742 | let a: f64 = -1.5; | |
12743 | let e: f64 = -1.0; | |
12744 | let r: f64 = transmute(vrnd_f64(transmute(a))); | |
12745 | assert_eq!(r, e); | |
12746 | } | |
12747 | ||
12748 | #[simd_test(enable = "neon")] | |
12749 | unsafe fn test_vrndq_f64() { | |
12750 | let a: f64x2 = f64x2::new(-1.5, 0.5); | |
12751 | let e: f64x2 = f64x2::new(-1.0, 0.0); | |
12752 | let r: f64x2 = transmute(vrndq_f64(transmute(a))); | |
12753 | assert_eq!(r, e); | |
12754 | } | |
12755 | ||
12756 | #[simd_test(enable = "neon")] | |
12757 | unsafe fn test_vrndi_f32() { | |
12758 | let a: f32x2 = f32x2::new(-1.5, 0.5); | |
12759 | let e: f32x2 = f32x2::new(-2.0, 0.0); | |
12760 | let r: f32x2 = transmute(vrndi_f32(transmute(a))); | |
12761 | assert_eq!(r, e); | |
12762 | } | |
12763 | ||
12764 | #[simd_test(enable = "neon")] | |
12765 | unsafe fn test_vrndiq_f32() { | |
12766 | let a: f32x4 = f32x4::new(-1.5, 0.5, 1.5, 2.5); | |
12767 | let e: f32x4 = f32x4::new(-2.0, 0.0, 2.0, 2.0); | |
12768 | let r: f32x4 = transmute(vrndiq_f32(transmute(a))); | |
12769 | assert_eq!(r, e); | |
12770 | } | |
12771 | ||
12772 | #[simd_test(enable = "neon")] | |
12773 | unsafe fn test_vrndi_f64() { | |
12774 | let a: f64 = -1.5; | |
12775 | let e: f64 = -2.0; | |
12776 | let r: f64 = transmute(vrndi_f64(transmute(a))); | |
12777 | assert_eq!(r, e); | |
12778 | } | |
12779 | ||
12780 | #[simd_test(enable = "neon")] | |
12781 | unsafe fn test_vrndiq_f64() { | |
12782 | let a: f64x2 = f64x2::new(-1.5, 0.5); | |
12783 | let e: f64x2 = f64x2::new(-2.0, 0.0); | |
12784 | let r: f64x2 = transmute(vrndiq_f64(transmute(a))); | |
12785 | assert_eq!(r, e); | |
12786 | } | |
12787 | ||
12788 | #[simd_test(enable = "neon")] | |
12789 | unsafe fn test_vqaddb_s8() { | |
12790 | let a: i8 = 42; | |
12791 | let b: i8 = 1; | |
12792 | let e: i8 = 43; | |
12793 | let r: i8 = transmute(vqaddb_s8(transmute(a), transmute(b))); | |
12794 | assert_eq!(r, e); | |
12795 | } | |
12796 | ||
12797 | #[simd_test(enable = "neon")] | |
12798 | unsafe fn test_vqaddh_s16() { | |
12799 | let a: i16 = 42; | |
12800 | let b: i16 = 1; | |
12801 | let e: i16 = 43; | |
12802 | let r: i16 = transmute(vqaddh_s16(transmute(a), transmute(b))); | |
12803 | assert_eq!(r, e); | |
12804 | } | |
12805 | ||
12806 | #[simd_test(enable = "neon")] | |
12807 | unsafe fn test_vqaddb_u8() { | |
12808 | let a: u8 = 42; | |
12809 | let b: u8 = 1; | |
12810 | let e: u8 = 43; | |
12811 | let r: u8 = transmute(vqaddb_u8(transmute(a), transmute(b))); | |
12812 | assert_eq!(r, e); | |
12813 | } | |
12814 | ||
12815 | #[simd_test(enable = "neon")] | |
12816 | unsafe fn test_vqaddh_u16() { | |
12817 | let a: u16 = 42; | |
12818 | let b: u16 = 1; | |
12819 | let e: u16 = 43; | |
12820 | let r: u16 = transmute(vqaddh_u16(transmute(a), transmute(b))); | |
12821 | assert_eq!(r, e); | |
12822 | } | |
12823 | ||
12824 | #[simd_test(enable = "neon")] | |
12825 | unsafe fn test_vqadds_u32() { | |
12826 | let a: u32 = 42; | |
12827 | let b: u32 = 1; | |
12828 | let e: u32 = 43; | |
12829 | let r: u32 = transmute(vqadds_u32(transmute(a), transmute(b))); | |
12830 | assert_eq!(r, e); | |
12831 | } | |
12832 | ||
12833 | #[simd_test(enable = "neon")] | |
12834 | unsafe fn test_vqaddd_u64() { | |
12835 | let a: u64 = 42; | |
12836 | let b: u64 = 1; | |
12837 | let e: u64 = 43; | |
12838 | let r: u64 = transmute(vqaddd_u64(transmute(a), transmute(b))); | |
12839 | assert_eq!(r, e); | |
12840 | } | |
12841 | ||
12842 | #[simd_test(enable = "neon")] | |
12843 | unsafe fn test_vqadds_s32() { | |
12844 | let a: i32 = 42; | |
12845 | let b: i32 = 1; | |
12846 | let e: i32 = 43; | |
12847 | let r: i32 = transmute(vqadds_s32(transmute(a), transmute(b))); | |
12848 | assert_eq!(r, e); | |
12849 | } | |
12850 | ||
12851 | #[simd_test(enable = "neon")] | |
12852 | unsafe fn test_vqaddd_s64() { | |
12853 | let a: i64 = 42; | |
12854 | let b: i64 = 1; | |
12855 | let e: i64 = 43; | |
12856 | let r: i64 = transmute(vqaddd_s64(transmute(a), transmute(b))); | |
12857 | assert_eq!(r, e); | |
12858 | } | |
12859 | ||
12860 | #[simd_test(enable = "neon")] | |
12861 | unsafe fn test_vmul_f64() { | |
12862 | let a: f64 = 1.0; | |
12863 | let b: f64 = 2.0; | |
12864 | let e: f64 = 2.0; | |
12865 | let r: f64 = transmute(vmul_f64(transmute(a), transmute(b))); | |
12866 | assert_eq!(r, e); | |
12867 | } | |
12868 | ||
12869 | #[simd_test(enable = "neon")] | |
12870 | unsafe fn test_vmulq_f64() { | |
12871 | let a: f64x2 = f64x2::new(1.0, 2.0); | |
12872 | let b: f64x2 = f64x2::new(2.0, 3.0); | |
12873 | let e: f64x2 = f64x2::new(2.0, 6.0); | |
12874 | let r: f64x2 = transmute(vmulq_f64(transmute(a), transmute(b))); | |
12875 | assert_eq!(r, e); | |
12876 | } | |
12877 | ||
12878 | #[simd_test(enable = "neon")] | |
12879 | unsafe fn test_vmul_n_f64() { | |
12880 | let a: f64 = 1.; | |
12881 | let b: f64 = 2.; | |
12882 | let e: f64 = 2.; | |
12883 | let r: f64 = transmute(vmul_n_f64(transmute(a), transmute(b))); | |
12884 | assert_eq!(r, e); | |
12885 | } | |
12886 | ||
12887 | #[simd_test(enable = "neon")] | |
12888 | unsafe fn test_vmulq_n_f64() { | |
12889 | let a: f64x2 = f64x2::new(1., 2.); | |
12890 | let b: f64 = 2.; | |
12891 | let e: f64x2 = f64x2::new(2., 4.); | |
12892 | let r: f64x2 = transmute(vmulq_n_f64(transmute(a), transmute(b))); | |
12893 | assert_eq!(r, e); | |
12894 | } | |
12895 | ||
12896 | #[simd_test(enable = "neon")] | |
12897 | unsafe fn test_vmul_lane_f64() { | |
12898 | let a: f64 = 1.; | |
12899 | let b: f64 = 2.; | |
12900 | let e: f64 = 2.; | |
12901 | let r: f64 = transmute(vmul_lane_f64::<0>(transmute(a), transmute(b))); | |
12902 | assert_eq!(r, e); | |
12903 | } | |
12904 | ||
12905 | #[simd_test(enable = "neon")] | |
12906 | unsafe fn test_vmul_laneq_f64() { | |
12907 | let a: f64 = 1.; | |
12908 | let b: f64x2 = f64x2::new(2., 0.); | |
12909 | let e: f64 = 2.; | |
12910 | let r: f64 = transmute(vmul_laneq_f64::<0>(transmute(a), transmute(b))); | |
12911 | assert_eq!(r, e); | |
12912 | } | |
12913 | ||
12914 | #[simd_test(enable = "neon")] | |
12915 | unsafe fn test_vmulq_lane_f64() { | |
12916 | let a: f64x2 = f64x2::new(1., 2.); | |
12917 | let b: f64 = 2.; | |
12918 | let e: f64x2 = f64x2::new(2., 4.); | |
12919 | let r: f64x2 = transmute(vmulq_lane_f64::<0>(transmute(a), transmute(b))); | |
12920 | assert_eq!(r, e); | |
12921 | } | |
12922 | ||
12923 | #[simd_test(enable = "neon")] | |
12924 | unsafe fn test_vmulq_laneq_f64() { | |
12925 | let a: f64x2 = f64x2::new(1., 2.); | |
12926 | let b: f64x2 = f64x2::new(2., 0.); | |
12927 | let e: f64x2 = f64x2::new(2., 4.); | |
12928 | let r: f64x2 = transmute(vmulq_laneq_f64::<0>(transmute(a), transmute(b))); | |
12929 | assert_eq!(r, e); | |
12930 | } | |
12931 | ||
12932 | #[simd_test(enable = "neon")] | |
12933 | unsafe fn test_vmuls_lane_f32() { | |
12934 | let a: f32 = 1.; | |
12935 | let b: f32x2 = f32x2::new(2., 0.); | |
12936 | let e: f32 = 2.; | |
12937 | let r: f32 = transmute(vmuls_lane_f32::<0>(transmute(a), transmute(b))); | |
12938 | assert_eq!(r, e); | |
12939 | } | |
12940 | ||
12941 | #[simd_test(enable = "neon")] | |
12942 | unsafe fn test_vmuls_laneq_f32() { | |
12943 | let a: f32 = 1.; | |
12944 | let b: f32x4 = f32x4::new(2., 0., 0., 0.); | |
12945 | let e: f32 = 2.; | |
12946 | let r: f32 = transmute(vmuls_laneq_f32::<0>(transmute(a), transmute(b))); | |
12947 | assert_eq!(r, e); | |
12948 | } | |
12949 | ||
12950 | #[simd_test(enable = "neon")] | |
12951 | unsafe fn test_vmuld_lane_f64() { | |
12952 | let a: f64 = 1.; | |
12953 | let b: f64 = 2.; | |
12954 | let e: f64 = 2.; | |
12955 | let r: f64 = transmute(vmuld_lane_f64::<0>(transmute(a), transmute(b))); | |
12956 | assert_eq!(r, e); | |
12957 | } | |
12958 | ||
12959 | #[simd_test(enable = "neon")] | |
12960 | unsafe fn test_vmuld_laneq_f64() { | |
12961 | let a: f64 = 1.; | |
12962 | let b: f64x2 = f64x2::new(2., 0.); | |
12963 | let e: f64 = 2.; | |
12964 | let r: f64 = transmute(vmuld_laneq_f64::<0>(transmute(a), transmute(b))); | |
12965 | assert_eq!(r, e); | |
12966 | } | |
12967 | ||
12968 | #[simd_test(enable = "neon")] | |
12969 | unsafe fn test_vmull_high_s8() { | |
12970 | let a: i8x16 = i8x16::new(1, 2, 9, 10, 9, 10, 11, 12, 9, 10, 11, 12, 13, 14, 15, 16); | |
12971 | let b: i8x16 = i8x16::new(1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2); | |
12972 | let e: i16x8 = i16x8::new(9, 20, 11, 24, 13, 28, 15, 32); | |
12973 | let r: i16x8 = transmute(vmull_high_s8(transmute(a), transmute(b))); | |
12974 | assert_eq!(r, e); | |
12975 | } | |
12976 | ||
12977 | #[simd_test(enable = "neon")] | |
12978 | unsafe fn test_vmull_high_s16() { | |
12979 | let a: i16x8 = i16x8::new(1, 2, 9, 10, 9, 10, 11, 12); | |
12980 | let b: i16x8 = i16x8::new(1, 2, 1, 2, 1, 2, 1, 2); | |
12981 | let e: i32x4 = i32x4::new(9, 20, 11, 24); | |
12982 | let r: i32x4 = transmute(vmull_high_s16(transmute(a), transmute(b))); | |
12983 | assert_eq!(r, e); | |
12984 | } | |
12985 | ||
12986 | #[simd_test(enable = "neon")] | |
12987 | unsafe fn test_vmull_high_s32() { | |
12988 | let a: i32x4 = i32x4::new(1, 2, 9, 10); | |
12989 | let b: i32x4 = i32x4::new(1, 2, 1, 2); | |
12990 | let e: i64x2 = i64x2::new(9, 20); | |
12991 | let r: i64x2 = transmute(vmull_high_s32(transmute(a), transmute(b))); | |
12992 | assert_eq!(r, e); | |
12993 | } | |
12994 | ||
12995 | #[simd_test(enable = "neon")] | |
12996 | unsafe fn test_vmull_high_u8() { | |
12997 | let a: u8x16 = u8x16::new(1, 2, 9, 10, 9, 10, 11, 12, 9, 10, 11, 12, 13, 14, 15, 16); | |
12998 | let b: u8x16 = u8x16::new(1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2); | |
12999 | let e: u16x8 = u16x8::new(9, 20, 11, 24, 13, 28, 15, 32); | |
13000 | let r: u16x8 = transmute(vmull_high_u8(transmute(a), transmute(b))); | |
13001 | assert_eq!(r, e); | |
13002 | } | |
13003 | ||
13004 | #[simd_test(enable = "neon")] | |
13005 | unsafe fn test_vmull_high_u16() { | |
13006 | let a: u16x8 = u16x8::new(1, 2, 9, 10, 9, 10, 11, 12); | |
13007 | let b: u16x8 = u16x8::new(1, 2, 1, 2, 1, 2, 1, 2); | |
13008 | let e: u32x4 = u32x4::new(9, 20, 11, 24); | |
13009 | let r: u32x4 = transmute(vmull_high_u16(transmute(a), transmute(b))); | |
13010 | assert_eq!(r, e); | |
13011 | } | |
13012 | ||
13013 | #[simd_test(enable = "neon")] | |
13014 | unsafe fn test_vmull_high_u32() { | |
13015 | let a: u32x4 = u32x4::new(1, 2, 9, 10); | |
13016 | let b: u32x4 = u32x4::new(1, 2, 1, 2); | |
13017 | let e: u64x2 = u64x2::new(9, 20); | |
13018 | let r: u64x2 = transmute(vmull_high_u32(transmute(a), transmute(b))); | |
13019 | assert_eq!(r, e); | |
13020 | } | |
13021 | ||
13022 | #[simd_test(enable = "neon")] | |
13023 | unsafe fn test_vmull_p64() { | |
13024 | let a: p64 = 15; | |
13025 | let b: p64 = 3; | |
13026 | let e: p128 = 17; | |
13027 | let r: p128 = transmute(vmull_p64(transmute(a), transmute(b))); | |
13028 | assert_eq!(r, e); | |
13029 | } | |
13030 | ||
13031 | #[simd_test(enable = "neon")] | |
13032 | unsafe fn test_vmull_high_p8() { | |
13033 | let a: i8x16 = i8x16::new(1, 2, 9, 10, 9, 10, 11, 12, 9, 10, 11, 12, 13, 14, 15, 16); | |
13034 | let b: i8x16 = i8x16::new(1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3); | |
13035 | let e: i16x8 = i16x8::new(9, 30, 11, 20, 13, 18, 15, 48); | |
13036 | let r: i16x8 = transmute(vmull_high_p8(transmute(a), transmute(b))); | |
13037 | assert_eq!(r, e); | |
13038 | } | |
13039 | ||
13040 | #[simd_test(enable = "neon")] | |
13041 | unsafe fn test_vmull_high_p64() { | |
13042 | let a: i64x2 = i64x2::new(1, 15); | |
13043 | let b: i64x2 = i64x2::new(1, 3); | |
13044 | let e: p128 = 17; | |
13045 | let r: p128 = transmute(vmull_high_p64(transmute(a), transmute(b))); | |
13046 | assert_eq!(r, e); | |
13047 | } | |
13048 | ||
13049 | #[simd_test(enable = "neon")] | |
13050 | unsafe fn test_vmull_high_n_s16() { | |
13051 | let a: i16x8 = i16x8::new(1, 2, 9, 10, 9, 10, 11, 12); | |
13052 | let b: i16 = 2; | |
13053 | let e: i32x4 = i32x4::new(18, 20, 22, 24); | |
13054 | let r: i32x4 = transmute(vmull_high_n_s16(transmute(a), transmute(b))); | |
13055 | assert_eq!(r, e); | |
13056 | } | |
13057 | ||
13058 | #[simd_test(enable = "neon")] | |
13059 | unsafe fn test_vmull_high_n_s32() { | |
13060 | let a: i32x4 = i32x4::new(1, 2, 9, 10); | |
13061 | let b: i32 = 2; | |
13062 | let e: i64x2 = i64x2::new(18, 20); | |
13063 | let r: i64x2 = transmute(vmull_high_n_s32(transmute(a), transmute(b))); | |
13064 | assert_eq!(r, e); | |
13065 | } | |
13066 | ||
13067 | #[simd_test(enable = "neon")] | |
13068 | unsafe fn test_vmull_high_n_u16() { | |
13069 | let a: u16x8 = u16x8::new(1, 2, 9, 10, 9, 10, 11, 12); | |
13070 | let b: u16 = 2; | |
13071 | let e: u32x4 = u32x4::new(18, 20, 22, 24); | |
13072 | let r: u32x4 = transmute(vmull_high_n_u16(transmute(a), transmute(b))); | |
13073 | assert_eq!(r, e); | |
13074 | } | |
13075 | ||
13076 | #[simd_test(enable = "neon")] | |
13077 | unsafe fn test_vmull_high_n_u32() { | |
13078 | let a: u32x4 = u32x4::new(1, 2, 9, 10); | |
13079 | let b: u32 = 2; | |
13080 | let e: u64x2 = u64x2::new(18, 20); | |
13081 | let r: u64x2 = transmute(vmull_high_n_u32(transmute(a), transmute(b))); | |
13082 | assert_eq!(r, e); | |
13083 | } | |
13084 | ||
13085 | #[simd_test(enable = "neon")] | |
13086 | unsafe fn test_vmull_high_lane_s16() { | |
13087 | let a: i16x8 = i16x8::new(1, 2, 9, 10, 9, 10, 11, 12); | |
13088 | let b: i16x4 = i16x4::new(0, 2, 0, 0); | |
13089 | let e: i32x4 = i32x4::new(18, 20, 22, 24); | |
13090 | let r: i32x4 = transmute(vmull_high_lane_s16::<1>(transmute(a), transmute(b))); | |
13091 | assert_eq!(r, e); | |
13092 | } | |
13093 | ||
13094 | #[simd_test(enable = "neon")] | |
13095 | unsafe fn test_vmull_high_laneq_s16() { | |
13096 | let a: i16x8 = i16x8::new(1, 2, 9, 10, 9, 10, 11, 12); | |
13097 | let b: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
13098 | let e: i32x4 = i32x4::new(18, 20, 22, 24); | |
13099 | let r: i32x4 = transmute(vmull_high_laneq_s16::<1>(transmute(a), transmute(b))); | |
13100 | assert_eq!(r, e); | |
13101 | } | |
13102 | ||
13103 | #[simd_test(enable = "neon")] | |
13104 | unsafe fn test_vmull_high_lane_s32() { | |
13105 | let a: i32x4 = i32x4::new(1, 2, 9, 10); | |
13106 | let b: i32x2 = i32x2::new(0, 2); | |
13107 | let e: i64x2 = i64x2::new(18, 20); | |
13108 | let r: i64x2 = transmute(vmull_high_lane_s32::<1>(transmute(a), transmute(b))); | |
13109 | assert_eq!(r, e); | |
13110 | } | |
13111 | ||
13112 | #[simd_test(enable = "neon")] | |
13113 | unsafe fn test_vmull_high_laneq_s32() { | |
13114 | let a: i32x4 = i32x4::new(1, 2, 9, 10); | |
13115 | let b: i32x4 = i32x4::new(0, 2, 0, 0); | |
13116 | let e: i64x2 = i64x2::new(18, 20); | |
13117 | let r: i64x2 = transmute(vmull_high_laneq_s32::<1>(transmute(a), transmute(b))); | |
13118 | assert_eq!(r, e); | |
13119 | } | |
13120 | ||
13121 | #[simd_test(enable = "neon")] | |
13122 | unsafe fn test_vmull_high_lane_u16() { | |
13123 | let a: u16x8 = u16x8::new(1, 2, 9, 10, 9, 10, 11, 12); | |
13124 | let b: u16x4 = u16x4::new(0, 2, 0, 0); | |
13125 | let e: u32x4 = u32x4::new(18, 20, 22, 24); | |
13126 | let r: u32x4 = transmute(vmull_high_lane_u16::<1>(transmute(a), transmute(b))); | |
13127 | assert_eq!(r, e); | |
13128 | } | |
13129 | ||
13130 | #[simd_test(enable = "neon")] | |
13131 | unsafe fn test_vmull_high_laneq_u16() { | |
13132 | let a: u16x8 = u16x8::new(1, 2, 9, 10, 9, 10, 11, 12); | |
13133 | let b: u16x8 = u16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
13134 | let e: u32x4 = u32x4::new(18, 20, 22, 24); | |
13135 | let r: u32x4 = transmute(vmull_high_laneq_u16::<1>(transmute(a), transmute(b))); | |
13136 | assert_eq!(r, e); | |
13137 | } | |
13138 | ||
13139 | #[simd_test(enable = "neon")] | |
13140 | unsafe fn test_vmull_high_lane_u32() { | |
13141 | let a: u32x4 = u32x4::new(1, 2, 9, 10); | |
13142 | let b: u32x2 = u32x2::new(0, 2); | |
13143 | let e: u64x2 = u64x2::new(18, 20); | |
13144 | let r: u64x2 = transmute(vmull_high_lane_u32::<1>(transmute(a), transmute(b))); | |
13145 | assert_eq!(r, e); | |
13146 | } | |
13147 | ||
13148 | #[simd_test(enable = "neon")] | |
13149 | unsafe fn test_vmull_high_laneq_u32() { | |
13150 | let a: u32x4 = u32x4::new(1, 2, 9, 10); | |
13151 | let b: u32x4 = u32x4::new(0, 2, 0, 0); | |
13152 | let e: u64x2 = u64x2::new(18, 20); | |
13153 | let r: u64x2 = transmute(vmull_high_laneq_u32::<1>(transmute(a), transmute(b))); | |
13154 | assert_eq!(r, e); | |
13155 | } | |
13156 | ||
13157 | #[simd_test(enable = "neon")] | |
13158 | unsafe fn test_vmulx_f32() { | |
13159 | let a: f32x2 = f32x2::new(1., 2.); | |
13160 | let b: f32x2 = f32x2::new(2., 2.); | |
13161 | let e: f32x2 = f32x2::new(2., 4.); | |
13162 | let r: f32x2 = transmute(vmulx_f32(transmute(a), transmute(b))); | |
13163 | assert_eq!(r, e); | |
13164 | } | |
13165 | ||
13166 | #[simd_test(enable = "neon")] | |
13167 | unsafe fn test_vmulxq_f32() { | |
13168 | let a: f32x4 = f32x4::new(1., 2., 3., 4.); | |
13169 | let b: f32x4 = f32x4::new(2., 2., 2., 2.); | |
13170 | let e: f32x4 = f32x4::new(2., 4., 6., 8.); | |
13171 | let r: f32x4 = transmute(vmulxq_f32(transmute(a), transmute(b))); | |
13172 | assert_eq!(r, e); | |
13173 | } | |
13174 | ||
13175 | #[simd_test(enable = "neon")] | |
13176 | unsafe fn test_vmulx_f64() { | |
13177 | let a: f64 = 1.; | |
13178 | let b: f64 = 2.; | |
13179 | let e: f64 = 2.; | |
13180 | let r: f64 = transmute(vmulx_f64(transmute(a), transmute(b))); | |
13181 | assert_eq!(r, e); | |
13182 | } | |
13183 | ||
13184 | #[simd_test(enable = "neon")] | |
13185 | unsafe fn test_vmulxq_f64() { | |
13186 | let a: f64x2 = f64x2::new(1., 2.); | |
13187 | let b: f64x2 = f64x2::new(2., 2.); | |
13188 | let e: f64x2 = f64x2::new(2., 4.); | |
13189 | let r: f64x2 = transmute(vmulxq_f64(transmute(a), transmute(b))); | |
13190 | assert_eq!(r, e); | |
13191 | } | |
13192 | ||
13193 | #[simd_test(enable = "neon")] | |
13194 | unsafe fn test_vmulx_lane_f64() { | |
13195 | let a: f64 = 1.; | |
13196 | let b: f64 = 2.; | |
13197 | let e: f64 = 2.; | |
13198 | let r: f64 = transmute(vmulx_lane_f64::<0>(transmute(a), transmute(b))); | |
13199 | assert_eq!(r, e); | |
13200 | } | |
13201 | ||
13202 | #[simd_test(enable = "neon")] | |
13203 | unsafe fn test_vmulx_laneq_f64() { | |
13204 | let a: f64 = 1.; | |
13205 | let b: f64x2 = f64x2::new(2., 0.); | |
13206 | let e: f64 = 2.; | |
13207 | let r: f64 = transmute(vmulx_laneq_f64::<0>(transmute(a), transmute(b))); | |
13208 | assert_eq!(r, e); | |
13209 | } | |
13210 | ||
13211 | #[simd_test(enable = "neon")] | |
13212 | unsafe fn test_vmulx_lane_f32() { | |
13213 | let a: f32x2 = f32x2::new(1., 2.); | |
13214 | let b: f32x2 = f32x2::new(2., 0.); | |
13215 | let e: f32x2 = f32x2::new(2., 4.); | |
13216 | let r: f32x2 = transmute(vmulx_lane_f32::<0>(transmute(a), transmute(b))); | |
13217 | assert_eq!(r, e); | |
13218 | } | |
13219 | ||
13220 | #[simd_test(enable = "neon")] | |
13221 | unsafe fn test_vmulx_laneq_f32() { | |
13222 | let a: f32x2 = f32x2::new(1., 2.); | |
13223 | let b: f32x4 = f32x4::new(2., 0., 0., 0.); | |
13224 | let e: f32x2 = f32x2::new(2., 4.); | |
13225 | let r: f32x2 = transmute(vmulx_laneq_f32::<0>(transmute(a), transmute(b))); | |
13226 | assert_eq!(r, e); | |
13227 | } | |
13228 | ||
13229 | #[simd_test(enable = "neon")] | |
13230 | unsafe fn test_vmulxq_lane_f32() { | |
13231 | let a: f32x4 = f32x4::new(1., 2., 3., 4.); | |
13232 | let b: f32x2 = f32x2::new(2., 0.); | |
13233 | let e: f32x4 = f32x4::new(2., 4., 6., 8.); | |
13234 | let r: f32x4 = transmute(vmulxq_lane_f32::<0>(transmute(a), transmute(b))); | |
13235 | assert_eq!(r, e); | |
13236 | } | |
13237 | ||
13238 | #[simd_test(enable = "neon")] | |
13239 | unsafe fn test_vmulxq_laneq_f32() { | |
13240 | let a: f32x4 = f32x4::new(1., 2., 3., 4.); | |
13241 | let b: f32x4 = f32x4::new(2., 0., 0., 0.); | |
13242 | let e: f32x4 = f32x4::new(2., 4., 6., 8.); | |
13243 | let r: f32x4 = transmute(vmulxq_laneq_f32::<0>(transmute(a), transmute(b))); | |
13244 | assert_eq!(r, e); | |
13245 | } | |
13246 | ||
13247 | #[simd_test(enable = "neon")] | |
13248 | unsafe fn test_vmulxq_lane_f64() { | |
13249 | let a: f64x2 = f64x2::new(1., 2.); | |
13250 | let b: f64 = 2.; | |
13251 | let e: f64x2 = f64x2::new(2., 4.); | |
13252 | let r: f64x2 = transmute(vmulxq_lane_f64::<0>(transmute(a), transmute(b))); | |
13253 | assert_eq!(r, e); | |
13254 | } | |
13255 | ||
13256 | #[simd_test(enable = "neon")] | |
13257 | unsafe fn test_vmulxq_laneq_f64() { | |
13258 | let a: f64x2 = f64x2::new(1., 2.); | |
13259 | let b: f64x2 = f64x2::new(2., 0.); | |
13260 | let e: f64x2 = f64x2::new(2., 4.); | |
13261 | let r: f64x2 = transmute(vmulxq_laneq_f64::<0>(transmute(a), transmute(b))); | |
13262 | assert_eq!(r, e); | |
13263 | } | |
13264 | ||
13265 | #[simd_test(enable = "neon")] | |
13266 | unsafe fn test_vmulxs_f32() { | |
13267 | let a: f32 = 2.; | |
13268 | let b: f32 = 3.; | |
13269 | let e: f32 = 6.; | |
13270 | let r: f32 = transmute(vmulxs_f32(transmute(a), transmute(b))); | |
13271 | assert_eq!(r, e); | |
13272 | } | |
13273 | ||
13274 | #[simd_test(enable = "neon")] | |
13275 | unsafe fn test_vmulxd_f64() { | |
13276 | let a: f64 = 2.; | |
13277 | let b: f64 = 3.; | |
13278 | let e: f64 = 6.; | |
13279 | let r: f64 = transmute(vmulxd_f64(transmute(a), transmute(b))); | |
13280 | assert_eq!(r, e); | |
13281 | } | |
13282 | ||
13283 | #[simd_test(enable = "neon")] | |
13284 | unsafe fn test_vmulxs_lane_f32() { | |
13285 | let a: f32 = 2.; | |
13286 | let b: f32x2 = f32x2::new(3., 0.); | |
13287 | let e: f32 = 6.; | |
13288 | let r: f32 = transmute(vmulxs_lane_f32::<0>(transmute(a), transmute(b))); | |
13289 | assert_eq!(r, e); | |
13290 | } | |
13291 | ||
13292 | #[simd_test(enable = "neon")] | |
13293 | unsafe fn test_vmulxs_laneq_f32() { | |
13294 | let a: f32 = 2.; | |
13295 | let b: f32x4 = f32x4::new(3., 0., 0., 0.); | |
13296 | let e: f32 = 6.; | |
13297 | let r: f32 = transmute(vmulxs_laneq_f32::<0>(transmute(a), transmute(b))); | |
13298 | assert_eq!(r, e); | |
13299 | } | |
13300 | ||
13301 | #[simd_test(enable = "neon")] | |
13302 | unsafe fn test_vmulxd_lane_f64() { | |
13303 | let a: f64 = 2.; | |
13304 | let b: f64 = 3.; | |
13305 | let e: f64 = 6.; | |
13306 | let r: f64 = transmute(vmulxd_lane_f64::<0>(transmute(a), transmute(b))); | |
13307 | assert_eq!(r, e); | |
13308 | } | |
13309 | ||
13310 | #[simd_test(enable = "neon")] | |
13311 | unsafe fn test_vmulxd_laneq_f64() { | |
13312 | let a: f64 = 2.; | |
13313 | let b: f64x2 = f64x2::new(3., 0.); | |
13314 | let e: f64 = 6.; | |
13315 | let r: f64 = transmute(vmulxd_laneq_f64::<0>(transmute(a), transmute(b))); | |
13316 | assert_eq!(r, e); | |
13317 | } | |
13318 | ||
13319 | #[simd_test(enable = "neon")] | |
13320 | unsafe fn test_vfma_f64() { | |
13321 | let a: f64 = 8.0; | |
13322 | let b: f64 = 6.0; | |
13323 | let c: f64 = 2.0; | |
13324 | let e: f64 = 20.0; | |
13325 | let r: f64 = transmute(vfma_f64(transmute(a), transmute(b), transmute(c))); | |
13326 | assert_eq!(r, e); | |
13327 | } | |
13328 | ||
13329 | #[simd_test(enable = "neon")] | |
13330 | unsafe fn test_vfmaq_f64() { | |
13331 | let a: f64x2 = f64x2::new(8.0, 18.0); | |
13332 | let b: f64x2 = f64x2::new(6.0, 4.0); | |
13333 | let c: f64x2 = f64x2::new(2.0, 3.0); | |
13334 | let e: f64x2 = f64x2::new(20.0, 30.0); | |
13335 | let r: f64x2 = transmute(vfmaq_f64(transmute(a), transmute(b), transmute(c))); | |
13336 | assert_eq!(r, e); | |
13337 | } | |
13338 | ||
13339 | #[simd_test(enable = "neon")] | |
13340 | unsafe fn test_vfma_n_f64() { | |
13341 | let a: f64 = 2.0; | |
13342 | let b: f64 = 6.0; | |
13343 | let c: f64 = 8.0; | |
13344 | let e: f64 = 50.0; | |
13345 | let r: f64 = transmute(vfma_n_f64(transmute(a), transmute(b), transmute(c))); | |
13346 | assert_eq!(r, e); | |
13347 | } | |
13348 | ||
13349 | #[simd_test(enable = "neon")] | |
13350 | unsafe fn test_vfmaq_n_f64() { | |
13351 | let a: f64x2 = f64x2::new(2.0, 3.0); | |
13352 | let b: f64x2 = f64x2::new(6.0, 4.0); | |
13353 | let c: f64 = 8.0; | |
13354 | let e: f64x2 = f64x2::new(50.0, 35.0); | |
13355 | let r: f64x2 = transmute(vfmaq_n_f64(transmute(a), transmute(b), transmute(c))); | |
13356 | assert_eq!(r, e); | |
13357 | } | |
13358 | ||
13359 | #[simd_test(enable = "neon")] | |
13360 | unsafe fn test_vfma_lane_f32() { | |
13361 | let a: f32x2 = f32x2::new(2., 3.); | |
13362 | let b: f32x2 = f32x2::new(6., 4.); | |
13363 | let c: f32x2 = f32x2::new(2., 0.); | |
13364 | let e: f32x2 = f32x2::new(14., 11.); | |
13365 | let r: f32x2 = transmute(vfma_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13366 | assert_eq!(r, e); | |
13367 | } | |
13368 | ||
13369 | #[simd_test(enable = "neon")] | |
13370 | unsafe fn test_vfma_laneq_f32() { | |
13371 | let a: f32x2 = f32x2::new(2., 3.); | |
13372 | let b: f32x2 = f32x2::new(6., 4.); | |
13373 | let c: f32x4 = f32x4::new(2., 0., 0., 0.); | |
13374 | let e: f32x2 = f32x2::new(14., 11.); | |
13375 | let r: f32x2 = transmute(vfma_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13376 | assert_eq!(r, e); | |
13377 | } | |
13378 | ||
13379 | #[simd_test(enable = "neon")] | |
13380 | unsafe fn test_vfmaq_lane_f32() { | |
13381 | let a: f32x4 = f32x4::new(2., 3., 4., 5.); | |
13382 | let b: f32x4 = f32x4::new(6., 4., 7., 8.); | |
13383 | let c: f32x2 = f32x2::new(2., 0.); | |
13384 | let e: f32x4 = f32x4::new(14., 11., 18., 21.); | |
13385 | let r: f32x4 = transmute(vfmaq_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13386 | assert_eq!(r, e); | |
13387 | } | |
13388 | ||
13389 | #[simd_test(enable = "neon")] | |
13390 | unsafe fn test_vfmaq_laneq_f32() { | |
13391 | let a: f32x4 = f32x4::new(2., 3., 4., 5.); | |
13392 | let b: f32x4 = f32x4::new(6., 4., 7., 8.); | |
13393 | let c: f32x4 = f32x4::new(2., 0., 0., 0.); | |
13394 | let e: f32x4 = f32x4::new(14., 11., 18., 21.); | |
13395 | let r: f32x4 = transmute(vfmaq_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13396 | assert_eq!(r, e); | |
13397 | } | |
13398 | ||
13399 | #[simd_test(enable = "neon")] | |
13400 | unsafe fn test_vfma_lane_f64() { | |
13401 | let a: f64 = 2.; | |
13402 | let b: f64 = 6.; | |
13403 | let c: f64 = 2.; | |
13404 | let e: f64 = 14.; | |
13405 | let r: f64 = transmute(vfma_lane_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13406 | assert_eq!(r, e); | |
13407 | } | |
13408 | ||
13409 | #[simd_test(enable = "neon")] | |
13410 | unsafe fn test_vfma_laneq_f64() { | |
13411 | let a: f64 = 2.; | |
13412 | let b: f64 = 6.; | |
13413 | let c: f64x2 = f64x2::new(2., 0.); | |
13414 | let e: f64 = 14.; | |
13415 | let r: f64 = transmute(vfma_laneq_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13416 | assert_eq!(r, e); | |
13417 | } | |
13418 | ||
13419 | #[simd_test(enable = "neon")] | |
13420 | unsafe fn test_vfmaq_lane_f64() { | |
13421 | let a: f64x2 = f64x2::new(2., 3.); | |
13422 | let b: f64x2 = f64x2::new(6., 4.); | |
13423 | let c: f64 = 2.; | |
13424 | let e: f64x2 = f64x2::new(14., 11.); | |
13425 | let r: f64x2 = transmute(vfmaq_lane_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13426 | assert_eq!(r, e); | |
13427 | } | |
13428 | ||
13429 | #[simd_test(enable = "neon")] | |
13430 | unsafe fn test_vfmaq_laneq_f64() { | |
13431 | let a: f64x2 = f64x2::new(2., 3.); | |
13432 | let b: f64x2 = f64x2::new(6., 4.); | |
13433 | let c: f64x2 = f64x2::new(2., 0.); | |
13434 | let e: f64x2 = f64x2::new(14., 11.); | |
13435 | let r: f64x2 = transmute(vfmaq_laneq_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13436 | assert_eq!(r, e); | |
13437 | } | |
13438 | ||
13439 | #[simd_test(enable = "neon")] | |
13440 | unsafe fn test_vfmas_lane_f32() { | |
13441 | let a: f32 = 2.; | |
13442 | let b: f32 = 6.; | |
13443 | let c: f32x2 = f32x2::new(3., 0.); | |
13444 | let e: f32 = 20.; | |
13445 | let r: f32 = transmute(vfmas_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13446 | assert_eq!(r, e); | |
13447 | } | |
13448 | ||
13449 | #[simd_test(enable = "neon")] | |
13450 | unsafe fn test_vfmas_laneq_f32() { | |
13451 | let a: f32 = 2.; | |
13452 | let b: f32 = 6.; | |
13453 | let c: f32x4 = f32x4::new(3., 0., 0., 0.); | |
13454 | let e: f32 = 20.; | |
13455 | let r: f32 = transmute(vfmas_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13456 | assert_eq!(r, e); | |
13457 | } | |
13458 | ||
13459 | #[simd_test(enable = "neon")] | |
13460 | unsafe fn test_vfmad_lane_f64() { | |
13461 | let a: f64 = 2.; | |
13462 | let b: f64 = 6.; | |
13463 | let c: f64 = 3.; | |
13464 | let e: f64 = 20.; | |
13465 | let r: f64 = transmute(vfmad_lane_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13466 | assert_eq!(r, e); | |
13467 | } | |
13468 | ||
13469 | #[simd_test(enable = "neon")] | |
13470 | unsafe fn test_vfmad_laneq_f64() { | |
13471 | let a: f64 = 2.; | |
13472 | let b: f64 = 6.; | |
13473 | let c: f64x2 = f64x2::new(3., 0.); | |
13474 | let e: f64 = 20.; | |
13475 | let r: f64 = transmute(vfmad_laneq_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13476 | assert_eq!(r, e); | |
13477 | } | |
13478 | ||
13479 | #[simd_test(enable = "neon")] | |
13480 | unsafe fn test_vfms_f64() { | |
13481 | let a: f64 = 20.0; | |
13482 | let b: f64 = 6.0; | |
13483 | let c: f64 = 2.0; | |
13484 | let e: f64 = 8.0; | |
13485 | let r: f64 = transmute(vfms_f64(transmute(a), transmute(b), transmute(c))); | |
13486 | assert_eq!(r, e); | |
13487 | } | |
13488 | ||
13489 | #[simd_test(enable = "neon")] | |
13490 | unsafe fn test_vfmsq_f64() { | |
13491 | let a: f64x2 = f64x2::new(20.0, 30.0); | |
13492 | let b: f64x2 = f64x2::new(6.0, 4.0); | |
13493 | let c: f64x2 = f64x2::new(2.0, 3.0); | |
13494 | let e: f64x2 = f64x2::new(8.0, 18.0); | |
13495 | let r: f64x2 = transmute(vfmsq_f64(transmute(a), transmute(b), transmute(c))); | |
13496 | assert_eq!(r, e); | |
13497 | } | |
13498 | ||
13499 | #[simd_test(enable = "neon")] | |
13500 | unsafe fn test_vfms_n_f64() { | |
13501 | let a: f64 = 50.0; | |
13502 | let b: f64 = 6.0; | |
13503 | let c: f64 = 8.0; | |
13504 | let e: f64 = 2.0; | |
13505 | let r: f64 = transmute(vfms_n_f64(transmute(a), transmute(b), transmute(c))); | |
13506 | assert_eq!(r, e); | |
13507 | } | |
13508 | ||
13509 | #[simd_test(enable = "neon")] | |
13510 | unsafe fn test_vfmsq_n_f64() { | |
13511 | let a: f64x2 = f64x2::new(50.0, 35.0); | |
13512 | let b: f64x2 = f64x2::new(6.0, 4.0); | |
13513 | let c: f64 = 8.0; | |
13514 | let e: f64x2 = f64x2::new(2.0, 3.0); | |
13515 | let r: f64x2 = transmute(vfmsq_n_f64(transmute(a), transmute(b), transmute(c))); | |
13516 | assert_eq!(r, e); | |
13517 | } | |
13518 | ||
13519 | #[simd_test(enable = "neon")] | |
13520 | unsafe fn test_vfms_lane_f32() { | |
13521 | let a: f32x2 = f32x2::new(14., 11.); | |
13522 | let b: f32x2 = f32x2::new(6., 4.); | |
13523 | let c: f32x2 = f32x2::new(2., 0.); | |
13524 | let e: f32x2 = f32x2::new(2., 3.); | |
13525 | let r: f32x2 = transmute(vfms_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13526 | assert_eq!(r, e); | |
13527 | } | |
13528 | ||
13529 | #[simd_test(enable = "neon")] | |
13530 | unsafe fn test_vfms_laneq_f32() { | |
13531 | let a: f32x2 = f32x2::new(14., 11.); | |
13532 | let b: f32x2 = f32x2::new(6., 4.); | |
13533 | let c: f32x4 = f32x4::new(2., 0., 0., 0.); | |
13534 | let e: f32x2 = f32x2::new(2., 3.); | |
13535 | let r: f32x2 = transmute(vfms_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13536 | assert_eq!(r, e); | |
13537 | } | |
13538 | ||
13539 | #[simd_test(enable = "neon")] | |
13540 | unsafe fn test_vfmsq_lane_f32() { | |
13541 | let a: f32x4 = f32x4::new(14., 11., 18., 21.); | |
13542 | let b: f32x4 = f32x4::new(6., 4., 7., 8.); | |
13543 | let c: f32x2 = f32x2::new(2., 0.); | |
13544 | let e: f32x4 = f32x4::new(2., 3., 4., 5.); | |
13545 | let r: f32x4 = transmute(vfmsq_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13546 | assert_eq!(r, e); | |
13547 | } | |
13548 | ||
13549 | #[simd_test(enable = "neon")] | |
13550 | unsafe fn test_vfmsq_laneq_f32() { | |
13551 | let a: f32x4 = f32x4::new(14., 11., 18., 21.); | |
13552 | let b: f32x4 = f32x4::new(6., 4., 7., 8.); | |
13553 | let c: f32x4 = f32x4::new(2., 0., 0., 0.); | |
13554 | let e: f32x4 = f32x4::new(2., 3., 4., 5.); | |
13555 | let r: f32x4 = transmute(vfmsq_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13556 | assert_eq!(r, e); | |
13557 | } | |
13558 | ||
13559 | #[simd_test(enable = "neon")] | |
13560 | unsafe fn test_vfms_lane_f64() { | |
13561 | let a: f64 = 14.; | |
13562 | let b: f64 = 6.; | |
13563 | let c: f64 = 2.; | |
13564 | let e: f64 = 2.; | |
13565 | let r: f64 = transmute(vfms_lane_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13566 | assert_eq!(r, e); | |
13567 | } | |
13568 | ||
13569 | #[simd_test(enable = "neon")] | |
13570 | unsafe fn test_vfms_laneq_f64() { | |
13571 | let a: f64 = 14.; | |
13572 | let b: f64 = 6.; | |
13573 | let c: f64x2 = f64x2::new(2., 0.); | |
13574 | let e: f64 = 2.; | |
13575 | let r: f64 = transmute(vfms_laneq_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13576 | assert_eq!(r, e); | |
13577 | } | |
13578 | ||
13579 | #[simd_test(enable = "neon")] | |
13580 | unsafe fn test_vfmsq_lane_f64() { | |
13581 | let a: f64x2 = f64x2::new(14., 11.); | |
13582 | let b: f64x2 = f64x2::new(6., 4.); | |
13583 | let c: f64 = 2.; | |
13584 | let e: f64x2 = f64x2::new(2., 3.); | |
13585 | let r: f64x2 = transmute(vfmsq_lane_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13586 | assert_eq!(r, e); | |
13587 | } | |
13588 | ||
13589 | #[simd_test(enable = "neon")] | |
13590 | unsafe fn test_vfmsq_laneq_f64() { | |
13591 | let a: f64x2 = f64x2::new(14., 11.); | |
13592 | let b: f64x2 = f64x2::new(6., 4.); | |
13593 | let c: f64x2 = f64x2::new(2., 0.); | |
13594 | let e: f64x2 = f64x2::new(2., 3.); | |
13595 | let r: f64x2 = transmute(vfmsq_laneq_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13596 | assert_eq!(r, e); | |
13597 | } | |
13598 | ||
13599 | #[simd_test(enable = "neon")] | |
13600 | unsafe fn test_vfmss_lane_f32() { | |
13601 | let a: f32 = 14.; | |
13602 | let b: f32 = 6.; | |
13603 | let c: f32x2 = f32x2::new(2., 0.); | |
13604 | let e: f32 = 2.; | |
13605 | let r: f32 = transmute(vfmss_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13606 | assert_eq!(r, e); | |
13607 | } | |
13608 | ||
13609 | #[simd_test(enable = "neon")] | |
13610 | unsafe fn test_vfmss_laneq_f32() { | |
13611 | let a: f32 = 14.; | |
13612 | let b: f32 = 6.; | |
13613 | let c: f32x4 = f32x4::new(2., 0., 0., 0.); | |
13614 | let e: f32 = 2.; | |
13615 | let r: f32 = transmute(vfmss_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); | |
13616 | assert_eq!(r, e); | |
13617 | } | |
13618 | ||
13619 | #[simd_test(enable = "neon")] | |
13620 | unsafe fn test_vfmsd_lane_f64() { | |
13621 | let a: f64 = 14.; | |
13622 | let b: f64 = 6.; | |
13623 | let c: f64 = 2.; | |
13624 | let e: f64 = 2.; | |
13625 | let r: f64 = transmute(vfmsd_lane_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13626 | assert_eq!(r, e); | |
13627 | } | |
13628 | ||
13629 | #[simd_test(enable = "neon")] | |
13630 | unsafe fn test_vfmsd_laneq_f64() { | |
13631 | let a: f64 = 14.; | |
13632 | let b: f64 = 6.; | |
13633 | let c: f64x2 = f64x2::new(2., 0.); | |
13634 | let e: f64 = 2.; | |
13635 | let r: f64 = transmute(vfmsd_laneq_f64::<0>(transmute(a), transmute(b), transmute(c))); | |
13636 | assert_eq!(r, e); | |
13637 | } | |
13638 | ||
13639 | #[simd_test(enable = "neon")] | |
13640 | unsafe fn test_vdiv_f32() { | |
13641 | let a: f32x2 = f32x2::new(2.0, 6.0); | |
13642 | let b: f32x2 = f32x2::new(1.0, 2.0); | |
13643 | let e: f32x2 = f32x2::new(2.0, 3.0); | |
13644 | let r: f32x2 = transmute(vdiv_f32(transmute(a), transmute(b))); | |
13645 | assert_eq!(r, e); | |
13646 | } | |
13647 | ||
13648 | #[simd_test(enable = "neon")] | |
13649 | unsafe fn test_vdivq_f32() { | |
13650 | let a: f32x4 = f32x4::new(2.0, 6.0, 4.0, 10.0); | |
13651 | let b: f32x4 = f32x4::new(1.0, 2.0, 1.0, 2.0); | |
13652 | let e: f32x4 = f32x4::new(2.0, 3.0, 4.0, 5.0); | |
13653 | let r: f32x4 = transmute(vdivq_f32(transmute(a), transmute(b))); | |
13654 | assert_eq!(r, e); | |
13655 | } | |
13656 | ||
13657 | #[simd_test(enable = "neon")] | |
13658 | unsafe fn test_vdiv_f64() { | |
13659 | let a: f64 = 2.0; | |
13660 | let b: f64 = 1.0; | |
13661 | let e: f64 = 2.0; | |
13662 | let r: f64 = transmute(vdiv_f64(transmute(a), transmute(b))); | |
13663 | assert_eq!(r, e); | |
13664 | } | |
13665 | ||
13666 | #[simd_test(enable = "neon")] | |
13667 | unsafe fn test_vdivq_f64() { | |
13668 | let a: f64x2 = f64x2::new(2.0, 6.0); | |
13669 | let b: f64x2 = f64x2::new(1.0, 2.0); | |
13670 | let e: f64x2 = f64x2::new(2.0, 3.0); | |
13671 | let r: f64x2 = transmute(vdivq_f64(transmute(a), transmute(b))); | |
13672 | assert_eq!(r, e); | |
13673 | } | |
13674 | ||
13675 | #[simd_test(enable = "neon")] | |
13676 | unsafe fn test_vsub_f64() { | |
13677 | let a: f64 = 1.0; | |
13678 | let b: f64 = 1.0; | |
13679 | let e: f64 = 0.0; | |
13680 | let r: f64 = transmute(vsub_f64(transmute(a), transmute(b))); | |
13681 | assert_eq!(r, e); | |
13682 | } | |
13683 | ||
13684 | #[simd_test(enable = "neon")] | |
13685 | unsafe fn test_vsubq_f64() { | |
13686 | let a: f64x2 = f64x2::new(1.0, 4.0); | |
13687 | let b: f64x2 = f64x2::new(1.0, 2.0); | |
13688 | let e: f64x2 = f64x2::new(0.0, 2.0); | |
13689 | let r: f64x2 = transmute(vsubq_f64(transmute(a), transmute(b))); | |
13690 | assert_eq!(r, e); | |
13691 | } | |
13692 | ||
13693 | #[simd_test(enable = "neon")] | |
13694 | unsafe fn test_vaddlv_s16() { | |
13695 | let a: i16x4 = i16x4::new(1, 2, 3, 4); | |
13696 | let e: i32 = 10; | |
13697 | let r: i32 = transmute(vaddlv_s16(transmute(a))); | |
13698 | assert_eq!(r, e); | |
13699 | } | |
13700 | ||
13701 | #[simd_test(enable = "neon")] | |
13702 | unsafe fn test_vaddlvq_s16() { | |
13703 | let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
13704 | let e: i32 = 36; | |
13705 | let r: i32 = transmute(vaddlvq_s16(transmute(a))); | |
13706 | assert_eq!(r, e); | |
13707 | } | |
13708 | ||
13709 | #[simd_test(enable = "neon")] | |
13710 | unsafe fn test_vaddlv_s32() { | |
13711 | let a: i32x2 = i32x2::new(1, 2); | |
13712 | let e: i64 = 3; | |
13713 | let r: i64 = transmute(vaddlv_s32(transmute(a))); | |
13714 | assert_eq!(r, e); | |
13715 | } | |
13716 | ||
13717 | #[simd_test(enable = "neon")] | |
13718 | unsafe fn test_vaddlvq_s32() { | |
13719 | let a: i32x4 = i32x4::new(1, 2, 3, 4); | |
13720 | let e: i64 = 10; | |
13721 | let r: i64 = transmute(vaddlvq_s32(transmute(a))); | |
13722 | assert_eq!(r, e); | |
13723 | } | |
13724 | ||
13725 | #[simd_test(enable = "neon")] | |
13726 | unsafe fn test_vaddlv_u16() { | |
13727 | let a: u16x4 = u16x4::new(1, 2, 3, 4); | |
13728 | let e: u32 = 10; | |
13729 | let r: u32 = transmute(vaddlv_u16(transmute(a))); | |
13730 | assert_eq!(r, e); | |
13731 | } | |
13732 | ||
13733 | #[simd_test(enable = "neon")] | |
13734 | unsafe fn test_vaddlvq_u16() { | |
13735 | let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
13736 | let e: u32 = 36; | |
13737 | let r: u32 = transmute(vaddlvq_u16(transmute(a))); | |
13738 | assert_eq!(r, e); | |
13739 | } | |
13740 | ||
13741 | #[simd_test(enable = "neon")] | |
13742 | unsafe fn test_vaddlv_u32() { | |
13743 | let a: u32x2 = u32x2::new(1, 2); | |
13744 | let e: u64 = 3; | |
13745 | let r: u64 = transmute(vaddlv_u32(transmute(a))); | |
13746 | assert_eq!(r, e); | |
13747 | } | |
13748 | ||
13749 | #[simd_test(enable = "neon")] | |
13750 | unsafe fn test_vaddlvq_u32() { | |
13751 | let a: u32x4 = u32x4::new(1, 2, 3, 4); | |
13752 | let e: u64 = 10; | |
13753 | let r: u64 = transmute(vaddlvq_u32(transmute(a))); | |
13754 | assert_eq!(r, e); | |
13755 | } | |
13756 | ||
13757 | #[simd_test(enable = "neon")] | |
13758 | unsafe fn test_vsubw_high_s8() { | |
13759 | let a: i16x8 = i16x8::new(8, 9, 10, 12, 13, 14, 15, 16); | |
13760 | let b: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16); | |
13761 | let e: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
13762 | let r: i16x8 = transmute(vsubw_high_s8(transmute(a), transmute(b))); | |
13763 | assert_eq!(r, e); | |
13764 | } | |
13765 | ||
13766 | #[simd_test(enable = "neon")] | |
13767 | unsafe fn test_vsubw_high_s16() { | |
13768 | let a: i32x4 = i32x4::new(8, 9, 10, 11); | |
13769 | let b: i16x8 = i16x8::new(0, 1, 2, 3, 8, 9, 10, 11); | |
13770 | let e: i32x4 = i32x4::new(0, 0, 0, 0); | |
13771 | let r: i32x4 = transmute(vsubw_high_s16(transmute(a), transmute(b))); | |
13772 | assert_eq!(r, e); | |
13773 | } | |
13774 | ||
13775 | #[simd_test(enable = "neon")] | |
13776 | unsafe fn test_vsubw_high_s32() { | |
13777 | let a: i64x2 = i64x2::new(8, 9); | |
13778 | let b: i32x4 = i32x4::new(6, 7, 8, 9); | |
13779 | let e: i64x2 = i64x2::new(0, 0); | |
13780 | let r: i64x2 = transmute(vsubw_high_s32(transmute(a), transmute(b))); | |
13781 | assert_eq!(r, e); | |
13782 | } | |
13783 | ||
13784 | #[simd_test(enable = "neon")] | |
13785 | unsafe fn test_vsubw_high_u8() { | |
13786 | let a: u16x8 = u16x8::new(8, 9, 10, 11, 12, 13, 14, 15); | |
13787 | let b: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); | |
13788 | let e: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
13789 | let r: u16x8 = transmute(vsubw_high_u8(transmute(a), transmute(b))); | |
13790 | assert_eq!(r, e); | |
13791 | } | |
13792 | ||
13793 | #[simd_test(enable = "neon")] | |
13794 | unsafe fn test_vsubw_high_u16() { | |
13795 | let a: u32x4 = u32x4::new(8, 9, 10, 11); | |
13796 | let b: u16x8 = u16x8::new(0, 1, 2, 3, 8, 9, 10, 11); | |
13797 | let e: u32x4 = u32x4::new(0, 0, 0, 0); | |
13798 | let r: u32x4 = transmute(vsubw_high_u16(transmute(a), transmute(b))); | |
13799 | assert_eq!(r, e); | |
13800 | } | |
13801 | ||
13802 | #[simd_test(enable = "neon")] | |
13803 | unsafe fn test_vsubw_high_u32() { | |
13804 | let a: u64x2 = u64x2::new(8, 9); | |
13805 | let b: u32x4 = u32x4::new(6, 7, 8, 9); | |
13806 | let e: u64x2 = u64x2::new(0, 0); | |
13807 | let r: u64x2 = transmute(vsubw_high_u32(transmute(a), transmute(b))); | |
13808 | assert_eq!(r, e); | |
13809 | } | |
13810 | ||
13811 | #[simd_test(enable = "neon")] | |
13812 | unsafe fn test_vsubl_high_s8() { | |
13813 | let a: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); | |
13814 | let b: i8x16 = i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2); | |
13815 | let e: i16x8 = i16x8::new(6, 7, 8, 9, 10, 11, 12, 13); | |
13816 | let r: i16x8 = transmute(vsubl_high_s8(transmute(a), transmute(b))); | |
13817 | assert_eq!(r, e); | |
13818 | } | |
13819 | ||
13820 | #[simd_test(enable = "neon")] | |
13821 | unsafe fn test_vsubl_high_s16() { | |
13822 | let a: i16x8 = i16x8::new(8, 9, 10, 11, 12, 13, 14, 15); | |
13823 | let b: i16x8 = i16x8::new(6, 6, 6, 6, 8, 8, 8, 8); | |
13824 | let e: i32x4 = i32x4::new(4, 5, 6, 7); | |
13825 | let r: i32x4 = transmute(vsubl_high_s16(transmute(a), transmute(b))); | |
13826 | assert_eq!(r, e); | |
13827 | } | |
13828 | ||
13829 | #[simd_test(enable = "neon")] | |
13830 | unsafe fn test_vsubl_high_s32() { | |
13831 | let a: i32x4 = i32x4::new(12, 13, 14, 15); | |
13832 | let b: i32x4 = i32x4::new(6, 6, 8, 8); | |
13833 | let e: i64x2 = i64x2::new(6, 7); | |
13834 | let r: i64x2 = transmute(vsubl_high_s32(transmute(a), transmute(b))); | |
13835 | assert_eq!(r, e); | |
13836 | } | |
13837 | ||
13838 | #[simd_test(enable = "neon")] | |
13839 | unsafe fn test_vsubl_high_u8() { | |
13840 | let a: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); | |
13841 | let b: u8x16 = u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2); | |
13842 | let e: u16x8 = u16x8::new(6, 7, 8, 9, 10, 11, 12, 13); | |
13843 | let r: u16x8 = transmute(vsubl_high_u8(transmute(a), transmute(b))); | |
13844 | assert_eq!(r, e); | |
13845 | } | |
13846 | ||
13847 | #[simd_test(enable = "neon")] | |
13848 | unsafe fn test_vsubl_high_u16() { | |
13849 | let a: u16x8 = u16x8::new(8, 9, 10, 11, 12, 13, 14, 15); | |
13850 | let b: u16x8 = u16x8::new(6, 6, 6, 6, 8, 8, 8, 8); | |
13851 | let e: u32x4 = u32x4::new(4, 5, 6, 7); | |
13852 | let r: u32x4 = transmute(vsubl_high_u16(transmute(a), transmute(b))); | |
13853 | assert_eq!(r, e); | |
13854 | } | |
13855 | ||
13856 | #[simd_test(enable = "neon")] | |
13857 | unsafe fn test_vsubl_high_u32() { | |
13858 | let a: u32x4 = u32x4::new(12, 13, 14, 15); | |
13859 | let b: u32x4 = u32x4::new(6, 6, 8, 8); | |
13860 | let e: u64x2 = u64x2::new(6, 7); | |
13861 | let r: u64x2 = transmute(vsubl_high_u32(transmute(a), transmute(b))); | |
13862 | assert_eq!(r, e); | |
13863 | } | |
13864 | ||
13865 | #[simd_test(enable = "neon")] | |
13866 | unsafe fn test_vmax_f64() { | |
13867 | let a: f64 = 1.0; | |
13868 | let b: f64 = 0.0; | |
13869 | let e: f64 = 1.0; | |
13870 | let r: f64 = transmute(vmax_f64(transmute(a), transmute(b))); | |
13871 | assert_eq!(r, e); | |
13872 | } | |
13873 | ||
13874 | #[simd_test(enable = "neon")] | |
13875 | unsafe fn test_vmaxq_f64() { | |
13876 | let a: f64x2 = f64x2::new(1.0, -2.0); | |
13877 | let b: f64x2 = f64x2::new(0.0, 3.0); | |
13878 | let e: f64x2 = f64x2::new(1.0, 3.0); | |
13879 | let r: f64x2 = transmute(vmaxq_f64(transmute(a), transmute(b))); | |
13880 | assert_eq!(r, e); | |
13881 | } | |
13882 | ||
13883 | #[simd_test(enable = "neon")] | |
13884 | unsafe fn test_vmaxnm_f64() { | |
13885 | let a: f64 = 1.0; | |
13886 | let b: f64 = 8.0; | |
13887 | let e: f64 = 8.0; | |
13888 | let r: f64 = transmute(vmaxnm_f64(transmute(a), transmute(b))); | |
13889 | assert_eq!(r, e); | |
13890 | } | |
13891 | ||
13892 | #[simd_test(enable = "neon")] | |
13893 | unsafe fn test_vmaxnmq_f64() { | |
13894 | let a: f64x2 = f64x2::new(1.0, 2.0); | |
13895 | let b: f64x2 = f64x2::new(8.0, 16.0); | |
13896 | let e: f64x2 = f64x2::new(8.0, 16.0); | |
13897 | let r: f64x2 = transmute(vmaxnmq_f64(transmute(a), transmute(b))); | |
13898 | assert_eq!(r, e); | |
13899 | } | |
13900 | ||
13901 | #[simd_test(enable = "neon")] | |
13902 | unsafe fn test_vpmaxnm_f32() { | |
13903 | let a: f32x2 = f32x2::new(1.0, 2.0); | |
13904 | let b: f32x2 = f32x2::new(6.0, -3.0); | |
13905 | let e: f32x2 = f32x2::new(2.0, 6.0); | |
13906 | let r: f32x2 = transmute(vpmaxnm_f32(transmute(a), transmute(b))); | |
13907 | assert_eq!(r, e); | |
13908 | } | |
13909 | ||
13910 | #[simd_test(enable = "neon")] | |
13911 | unsafe fn test_vpmaxnmq_f64() { | |
13912 | let a: f64x2 = f64x2::new(1.0, 2.0); | |
13913 | let b: f64x2 = f64x2::new(6.0, -3.0); | |
13914 | let e: f64x2 = f64x2::new(2.0, 6.0); | |
13915 | let r: f64x2 = transmute(vpmaxnmq_f64(transmute(a), transmute(b))); | |
13916 | assert_eq!(r, e); | |
13917 | } | |
13918 | ||
13919 | #[simd_test(enable = "neon")] | |
13920 | unsafe fn test_vpmaxnmq_f32() { | |
13921 | let a: f32x4 = f32x4::new(1.0, 2.0, 3.0, -4.0); | |
13922 | let b: f32x4 = f32x4::new(8.0, 16.0, -1.0, 6.0); | |
13923 | let e: f32x4 = f32x4::new(2.0, 3.0, 16.0, 6.0); | |
13924 | let r: f32x4 = transmute(vpmaxnmq_f32(transmute(a), transmute(b))); | |
13925 | assert_eq!(r, e); | |
13926 | } | |
13927 | ||
13928 | #[simd_test(enable = "neon")] | |
13929 | unsafe fn test_vmin_f64() { | |
13930 | let a: f64 = 1.0; | |
13931 | let b: f64 = 0.0; | |
13932 | let e: f64 = 0.0; | |
13933 | let r: f64 = transmute(vmin_f64(transmute(a), transmute(b))); | |
13934 | assert_eq!(r, e); | |
13935 | } | |
13936 | ||
13937 | #[simd_test(enable = "neon")] | |
13938 | unsafe fn test_vminq_f64() { | |
13939 | let a: f64x2 = f64x2::new(1.0, -2.0); | |
13940 | let b: f64x2 = f64x2::new(0.0, 3.0); | |
13941 | let e: f64x2 = f64x2::new(0.0, -2.0); | |
13942 | let r: f64x2 = transmute(vminq_f64(transmute(a), transmute(b))); | |
13943 | assert_eq!(r, e); | |
13944 | } | |
13945 | ||
13946 | #[simd_test(enable = "neon")] | |
13947 | unsafe fn test_vminnm_f64() { | |
13948 | let a: f64 = 1.0; | |
13949 | let b: f64 = 8.0; | |
13950 | let e: f64 = 1.0; | |
13951 | let r: f64 = transmute(vminnm_f64(transmute(a), transmute(b))); | |
13952 | assert_eq!(r, e); | |
13953 | } | |
13954 | ||
13955 | #[simd_test(enable = "neon")] | |
13956 | unsafe fn test_vminnmq_f64() { | |
13957 | let a: f64x2 = f64x2::new(1.0, 2.0); | |
13958 | let b: f64x2 = f64x2::new(8.0, 16.0); | |
13959 | let e: f64x2 = f64x2::new(1.0, 2.0); | |
13960 | let r: f64x2 = transmute(vminnmq_f64(transmute(a), transmute(b))); | |
13961 | assert_eq!(r, e); | |
13962 | } | |
13963 | ||
13964 | #[simd_test(enable = "neon")] | |
13965 | unsafe fn test_vpminnm_f32() { | |
13966 | let a: f32x2 = f32x2::new(1.0, 2.0); | |
13967 | let b: f32x2 = f32x2::new(6.0, -3.0); | |
13968 | let e: f32x2 = f32x2::new(1.0, -3.0); | |
13969 | let r: f32x2 = transmute(vpminnm_f32(transmute(a), transmute(b))); | |
13970 | assert_eq!(r, e); | |
13971 | } | |
13972 | ||
13973 | #[simd_test(enable = "neon")] | |
13974 | unsafe fn test_vpminnmq_f64() { | |
13975 | let a: f64x2 = f64x2::new(1.0, 2.0); | |
13976 | let b: f64x2 = f64x2::new(6.0, -3.0); | |
13977 | let e: f64x2 = f64x2::new(1.0, -3.0); | |
13978 | let r: f64x2 = transmute(vpminnmq_f64(transmute(a), transmute(b))); | |
13979 | assert_eq!(r, e); | |
13980 | } | |
13981 | ||
13982 | #[simd_test(enable = "neon")] | |
13983 | unsafe fn test_vpminnmq_f32() { | |
13984 | let a: f32x4 = f32x4::new(1.0, 2.0, 3.0, -4.0); | |
13985 | let b: f32x4 = f32x4::new(8.0, 16.0, -1.0, 6.0); | |
13986 | let e: f32x4 = f32x4::new(1.0, -4.0, 8.0, -1.0); | |
13987 | let r: f32x4 = transmute(vpminnmq_f32(transmute(a), transmute(b))); | |
13988 | assert_eq!(r, e); | |
13989 | } | |
13990 | ||
13991 | #[simd_test(enable = "neon")] | |
13992 | unsafe fn test_vqdmullh_s16() { | |
13993 | let a: i16 = 2; | |
13994 | let b: i16 = 3; | |
13995 | let e: i32 = 12; | |
13996 | let r: i32 = transmute(vqdmullh_s16(transmute(a), transmute(b))); | |
13997 | assert_eq!(r, e); | |
13998 | } | |
13999 | ||
14000 | #[simd_test(enable = "neon")] | |
14001 | unsafe fn test_vqdmulls_s32() { | |
14002 | let a: i32 = 2; | |
14003 | let b: i32 = 3; | |
14004 | let e: i64 = 12; | |
14005 | let r: i64 = transmute(vqdmulls_s32(transmute(a), transmute(b))); | |
14006 | assert_eq!(r, e); | |
14007 | } | |
14008 | ||
14009 | #[simd_test(enable = "neon")] | |
14010 | unsafe fn test_vqdmull_high_s16() { | |
14011 | let a: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); | |
14012 | let b: i16x8 = i16x8::new(1, 2, 5, 6, 5, 6, 7, 8); | |
14013 | let e: i32x4 = i32x4::new(40, 60, 84, 112); | |
14014 | let r: i32x4 = transmute(vqdmull_high_s16(transmute(a), transmute(b))); | |
14015 | assert_eq!(r, e); | |
14016 | } | |
14017 | ||
14018 | #[simd_test(enable = "neon")] | |
14019 | unsafe fn test_vqdmull_high_s32() { | |
14020 | let a: i32x4 = i32x4::new(0, 1, 4, 5); | |
14021 | let b: i32x4 = i32x4::new(1, 2, 5, 6); | |
14022 | let e: i64x2 = i64x2::new(40, 60); | |
14023 | let r: i64x2 = transmute(vqdmull_high_s32(transmute(a), transmute(b))); | |
14024 | assert_eq!(r, e); | |
14025 | } | |
14026 | ||
14027 | #[simd_test(enable = "neon")] | |
14028 | unsafe fn test_vqdmull_high_n_s16() { | |
14029 | let a: i16x8 = i16x8::new(0, 2, 8, 10, 8, 10, 12, 14); | |
14030 | let b: i16 = 2; | |
14031 | let e: i32x4 = i32x4::new(32, 40, 48, 56); | |
14032 | let r: i32x4 = transmute(vqdmull_high_n_s16(transmute(a), transmute(b))); | |
14033 | assert_eq!(r, e); | |
14034 | } | |
14035 | ||
14036 | #[simd_test(enable = "neon")] | |
14037 | unsafe fn test_vqdmull_high_n_s32() { | |
14038 | let a: i32x4 = i32x4::new(0, 2, 8, 10); | |
14039 | let b: i32 = 2; | |
14040 | let e: i64x2 = i64x2::new(32, 40); | |
14041 | let r: i64x2 = transmute(vqdmull_high_n_s32(transmute(a), transmute(b))); | |
14042 | assert_eq!(r, e); | |
14043 | } | |
14044 | ||
14045 | #[simd_test(enable = "neon")] | |
14046 | unsafe fn test_vqdmull_laneq_s16() { | |
14047 | let a: i16x4 = i16x4::new(1, 2, 3, 4); | |
14048 | let b: i16x8 = i16x8::new(0, 2, 2, 0, 2, 0, 0, 0); | |
14049 | let e: i32x4 = i32x4::new(4, 8, 12, 16); | |
14050 | let r: i32x4 = transmute(vqdmull_laneq_s16::<4>(transmute(a), transmute(b))); | |
14051 | assert_eq!(r, e); | |
14052 | } | |
14053 | ||
14054 | #[simd_test(enable = "neon")] | |
14055 | unsafe fn test_vqdmull_laneq_s32() { | |
14056 | let a: i32x2 = i32x2::new(1, 2); | |
14057 | let b: i32x4 = i32x4::new(0, 2, 2, 0); | |
14058 | let e: i64x2 = i64x2::new(4, 8); | |
14059 | let r: i64x2 = transmute(vqdmull_laneq_s32::<2>(transmute(a), transmute(b))); | |
14060 | assert_eq!(r, e); | |
14061 | } | |
14062 | ||
14063 | #[simd_test(enable = "neon")] | |
14064 | unsafe fn test_vqdmullh_lane_s16() { | |
14065 | let a: i16 = 2; | |
14066 | let b: i16x4 = i16x4::new(0, 2, 2, 0); | |
14067 | let e: i32 = 8; | |
14068 | let r: i32 = transmute(vqdmullh_lane_s16::<2>(transmute(a), transmute(b))); | |
14069 | assert_eq!(r, e); | |
14070 | } | |
14071 | ||
14072 | #[simd_test(enable = "neon")] | |
14073 | unsafe fn test_vqdmullh_laneq_s16() { | |
14074 | let a: i16 = 2; | |
14075 | let b: i16x8 = i16x8::new(0, 2, 2, 0, 2, 0, 0, 0); | |
14076 | let e: i32 = 8; | |
14077 | let r: i32 = transmute(vqdmullh_laneq_s16::<4>(transmute(a), transmute(b))); | |
14078 | assert_eq!(r, e); | |
14079 | } | |
14080 | ||
14081 | #[simd_test(enable = "neon")] | |
14082 | unsafe fn test_vqdmulls_lane_s32() { | |
14083 | let a: i32 = 2; | |
14084 | let b: i32x2 = i32x2::new(0, 2); | |
14085 | let e: i64 = 8; | |
14086 | let r: i64 = transmute(vqdmulls_lane_s32::<1>(transmute(a), transmute(b))); | |
14087 | assert_eq!(r, e); | |
14088 | } | |
14089 | ||
14090 | #[simd_test(enable = "neon")] | |
14091 | unsafe fn test_vqdmulls_laneq_s32() { | |
14092 | let a: i32 = 2; | |
14093 | let b: i32x4 = i32x4::new(0, 2, 2, 0); | |
14094 | let e: i64 = 8; | |
14095 | let r: i64 = transmute(vqdmulls_laneq_s32::<2>(transmute(a), transmute(b))); | |
14096 | assert_eq!(r, e); | |
14097 | } | |
14098 | ||
14099 | #[simd_test(enable = "neon")] | |
14100 | unsafe fn test_vqdmull_high_lane_s16() { | |
14101 | let a: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); | |
14102 | let b: i16x4 = i16x4::new(0, 2, 2, 0); | |
14103 | let e: i32x4 = i32x4::new(16, 20, 24, 28); | |
14104 | let r: i32x4 = transmute(vqdmull_high_lane_s16::<2>(transmute(a), transmute(b))); | |
14105 | assert_eq!(r, e); | |
14106 | } | |
14107 | ||
14108 | #[simd_test(enable = "neon")] | |
14109 | unsafe fn test_vqdmull_high_lane_s32() { | |
14110 | let a: i32x4 = i32x4::new(0, 1, 4, 5); | |
14111 | let b: i32x2 = i32x2::new(0, 2); | |
14112 | let e: i64x2 = i64x2::new(16, 20); | |
14113 | let r: i64x2 = transmute(vqdmull_high_lane_s32::<1>(transmute(a), transmute(b))); | |
14114 | assert_eq!(r, e); | |
14115 | } | |
14116 | ||
14117 | #[simd_test(enable = "neon")] | |
14118 | unsafe fn test_vqdmull_high_laneq_s16() { | |
14119 | let a: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); | |
14120 | let b: i16x8 = i16x8::new(0, 2, 2, 0, 2, 0, 0, 0); | |
14121 | let e: i32x4 = i32x4::new(16, 20, 24, 28); | |
14122 | let r: i32x4 = transmute(vqdmull_high_laneq_s16::<4>(transmute(a), transmute(b))); | |
14123 | assert_eq!(r, e); | |
14124 | } | |
14125 | ||
14126 | #[simd_test(enable = "neon")] | |
14127 | unsafe fn test_vqdmull_high_laneq_s32() { | |
14128 | let a: i32x4 = i32x4::new(0, 1, 4, 5); | |
14129 | let b: i32x4 = i32x4::new(0, 2, 2, 0); | |
14130 | let e: i64x2 = i64x2::new(16, 20); | |
14131 | let r: i64x2 = transmute(vqdmull_high_laneq_s32::<2>(transmute(a), transmute(b))); | |
14132 | assert_eq!(r, e); | |
14133 | } | |
14134 | ||
14135 | #[simd_test(enable = "neon")] | |
14136 | unsafe fn test_vqdmlal_high_s16() { | |
14137 | let a: i32x4 = i32x4::new(1, 2, 3, 4); | |
14138 | let b: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); | |
14139 | let c: i16x8 = i16x8::new(1, 2, 5, 6, 5, 6, 7, 8); | |
14140 | let e: i32x4 = i32x4::new(41, 62, 87, 116); | |
14141 | let r: i32x4 = transmute(vqdmlal_high_s16(transmute(a), transmute(b), transmute(c))); | |
14142 | assert_eq!(r, e); | |
14143 | } | |
14144 | ||
14145 | #[simd_test(enable = "neon")] | |
14146 | unsafe fn test_vqdmlal_high_s32() { | |
14147 | let a: i64x2 = i64x2::new(1, 2); | |
14148 | let b: i32x4 = i32x4::new(0, 1, 4, 5); | |
14149 | let c: i32x4 = i32x4::new(1, 2, 5, 6); | |
14150 | let e: i64x2 = i64x2::new(41, 62); | |
14151 | let r: i64x2 = transmute(vqdmlal_high_s32(transmute(a), transmute(b), transmute(c))); | |
14152 | assert_eq!(r, e); | |
14153 | } | |
14154 | ||
14155 | #[simd_test(enable = "neon")] | |
14156 | unsafe fn test_vqdmlal_high_n_s16() { | |
14157 | let a: i32x4 = i32x4::new(1, 2, 3, 4); | |
14158 | let b: i16x8 = i16x8::new(0, 2, 8, 10, 8, 10, 12, 14); | |
14159 | let c: i16 = 2; | |
14160 | let e: i32x4 = i32x4::new(33, 42, 51, 60); | |
14161 | let r: i32x4 = transmute(vqdmlal_high_n_s16(transmute(a), transmute(b), transmute(c))); | |
14162 | assert_eq!(r, e); | |
14163 | } | |
14164 | ||
14165 | #[simd_test(enable = "neon")] | |
14166 | unsafe fn test_vqdmlal_high_n_s32() { | |
14167 | let a: i64x2 = i64x2::new(1, 2); | |
14168 | let b: i32x4 = i32x4::new(0, 2, 8, 10); | |
14169 | let c: i32 = 2; | |
14170 | let e: i64x2 = i64x2::new(33, 42); | |
14171 | let r: i64x2 = transmute(vqdmlal_high_n_s32(transmute(a), transmute(b), transmute(c))); | |
14172 | assert_eq!(r, e); | |
14173 | } | |
14174 | ||
14175 | #[simd_test(enable = "neon")] | |
14176 | unsafe fn test_vqdmlal_laneq_s16() { | |
14177 | let a: i32x4 = i32x4::new(1, 2, 3, 4); | |
14178 | let b: i16x4 = i16x4::new(1, 2, 3, 4); | |
14179 | let c: i16x8 = i16x8::new(0, 2, 2, 0, 2, 0, 0, 0); | |
14180 | let e: i32x4 = i32x4::new(5, 10, 15, 20); | |
14181 | let r: i32x4 = transmute(vqdmlal_laneq_s16::<2>(transmute(a), transmute(b), transmute(c))); | |
14182 | assert_eq!(r, e); | |
14183 | } | |
14184 | ||
14185 | #[simd_test(enable = "neon")] | |
14186 | unsafe fn test_vqdmlal_laneq_s32() { | |
14187 | let a: i64x2 = i64x2::new(1, 2); | |
14188 | let b: i32x2 = i32x2::new(1, 2); | |
14189 | let c: i32x4 = i32x4::new(0, 2, 2, 0); | |
14190 | let e: i64x2 = i64x2::new(5, 10); | |
14191 | let r: i64x2 = transmute(vqdmlal_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
14192 | assert_eq!(r, e); | |
14193 | } | |
14194 | ||
14195 | #[simd_test(enable = "neon")] | |
14196 | unsafe fn test_vqdmlal_high_lane_s16() { | |
14197 | let a: i32x4 = i32x4::new(1, 2, 3, 4); | |
14198 | let b: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); | |
14199 | let c: i16x4 = i16x4::new(0, 2, 0, 0); | |
14200 | let e: i32x4 = i32x4::new(17, 22, 27, 32); | |
14201 | let r: i32x4 = transmute(vqdmlal_high_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
14202 | assert_eq!(r, e); | |
14203 | } | |
14204 | ||
14205 | #[simd_test(enable = "neon")] | |
14206 | unsafe fn test_vqdmlal_high_laneq_s16() { | |
14207 | let a: i32x4 = i32x4::new(1, 2, 3, 4); | |
14208 | let b: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); | |
14209 | let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
14210 | let e: i32x4 = i32x4::new(17, 22, 27, 32); | |
14211 | let r: i32x4 = transmute(vqdmlal_high_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
14212 | assert_eq!(r, e); | |
14213 | } | |
14214 | ||
14215 | #[simd_test(enable = "neon")] | |
14216 | unsafe fn test_vqdmlal_high_lane_s32() { | |
14217 | let a: i64x2 = i64x2::new(1, 2); | |
14218 | let b: i32x4 = i32x4::new(0, 1, 4, 5); | |
14219 | let c: i32x2 = i32x2::new(0, 2); | |
14220 | let e: i64x2 = i64x2::new(17, 22); | |
14221 | let r: i64x2 = transmute(vqdmlal_high_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
14222 | assert_eq!(r, e); | |
14223 | } | |
14224 | ||
14225 | #[simd_test(enable = "neon")] | |
14226 | unsafe fn test_vqdmlal_high_laneq_s32() { | |
14227 | let a: i64x2 = i64x2::new(1, 2); | |
14228 | let b: i32x4 = i32x4::new(0, 1, 4, 5); | |
14229 | let c: i32x4 = i32x4::new(0, 2, 0, 0); | |
14230 | let e: i64x2 = i64x2::new(17, 22); | |
14231 | let r: i64x2 = transmute(vqdmlal_high_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
14232 | assert_eq!(r, e); | |
14233 | } | |
14234 | ||
14235 | #[simd_test(enable = "neon")] | |
14236 | unsafe fn test_vqdmlsl_high_s16() { | |
14237 | let a: i32x4 = i32x4::new(39, 58, 81, 108); | |
14238 | let b: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); | |
14239 | let c: i16x8 = i16x8::new(1, 2, 5, 6, 5, 6, 7, 8); | |
14240 | let e: i32x4 = i32x4::new(-1, -2, -3, -4); | |
14241 | let r: i32x4 = transmute(vqdmlsl_high_s16(transmute(a), transmute(b), transmute(c))); | |
14242 | assert_eq!(r, e); | |
14243 | } | |
14244 | ||
14245 | #[simd_test(enable = "neon")] | |
14246 | unsafe fn test_vqdmlsl_high_s32() { | |
14247 | let a: i64x2 = i64x2::new(39, 58); | |
14248 | let b: i32x4 = i32x4::new(0, 1, 4, 5); | |
14249 | let c: i32x4 = i32x4::new(1, 2, 5, 6); | |
14250 | let e: i64x2 = i64x2::new(-1, -2); | |
14251 | let r: i64x2 = transmute(vqdmlsl_high_s32(transmute(a), transmute(b), transmute(c))); | |
14252 | assert_eq!(r, e); | |
14253 | } | |
14254 | ||
14255 | #[simd_test(enable = "neon")] | |
14256 | unsafe fn test_vqdmlsl_high_n_s16() { | |
14257 | let a: i32x4 = i32x4::new(31, 38, 45, 52); | |
14258 | let b: i16x8 = i16x8::new(0, 2, 8, 10, 8, 10, 12, 14); | |
14259 | let c: i16 = 2; | |
14260 | let e: i32x4 = i32x4::new(-1, -2, -3, -4); | |
14261 | let r: i32x4 = transmute(vqdmlsl_high_n_s16(transmute(a), transmute(b), transmute(c))); | |
14262 | assert_eq!(r, e); | |
14263 | } | |
14264 | ||
14265 | #[simd_test(enable = "neon")] | |
14266 | unsafe fn test_vqdmlsl_high_n_s32() { | |
14267 | let a: i64x2 = i64x2::new(31, 38); | |
14268 | let b: i32x4 = i32x4::new(0, 2, 8, 10); | |
14269 | let c: i32 = 2; | |
14270 | let e: i64x2 = i64x2::new(-1, -2); | |
14271 | let r: i64x2 = transmute(vqdmlsl_high_n_s32(transmute(a), transmute(b), transmute(c))); | |
14272 | assert_eq!(r, e); | |
14273 | } | |
14274 | ||
14275 | #[simd_test(enable = "neon")] | |
14276 | unsafe fn test_vqdmlsl_laneq_s16() { | |
14277 | let a: i32x4 = i32x4::new(3, 6, 9, 12); | |
14278 | let b: i16x4 = i16x4::new(1, 2, 3, 4); | |
14279 | let c: i16x8 = i16x8::new(0, 2, 2, 0, 2, 0, 0, 0); | |
14280 | let e: i32x4 = i32x4::new(-1, -2, -3, -4); | |
14281 | let r: i32x4 = transmute(vqdmlsl_laneq_s16::<2>(transmute(a), transmute(b), transmute(c))); | |
14282 | assert_eq!(r, e); | |
14283 | } | |
14284 | ||
14285 | #[simd_test(enable = "neon")] | |
14286 | unsafe fn test_vqdmlsl_laneq_s32() { | |
14287 | let a: i64x2 = i64x2::new(3, 6); | |
14288 | let b: i32x2 = i32x2::new(1, 2); | |
14289 | let c: i32x4 = i32x4::new(0, 2, 2, 0); | |
14290 | let e: i64x2 = i64x2::new(-1, -2); | |
14291 | let r: i64x2 = transmute(vqdmlsl_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
14292 | assert_eq!(r, e); | |
14293 | } | |
14294 | ||
14295 | #[simd_test(enable = "neon")] | |
14296 | unsafe fn test_vqdmlsl_high_lane_s16() { | |
14297 | let a: i32x4 = i32x4::new(15, 18, 21, 24); | |
14298 | let b: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); | |
14299 | let c: i16x4 = i16x4::new(0, 2, 0, 0); | |
14300 | let e: i32x4 = i32x4::new(-1, -2, -3, -4); | |
14301 | let r: i32x4 = transmute(vqdmlsl_high_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
14302 | assert_eq!(r, e); | |
14303 | } | |
14304 | ||
14305 | #[simd_test(enable = "neon")] | |
14306 | unsafe fn test_vqdmlsl_high_laneq_s16() { | |
14307 | let a: i32x4 = i32x4::new(15, 18, 21, 24); | |
14308 | let b: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); | |
14309 | let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
14310 | let e: i32x4 = i32x4::new(-1, -2, -3, -4); | |
14311 | let r: i32x4 = transmute(vqdmlsl_high_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
14312 | assert_eq!(r, e); | |
14313 | } | |
14314 | ||
14315 | #[simd_test(enable = "neon")] | |
14316 | unsafe fn test_vqdmlsl_high_lane_s32() { | |
14317 | let a: i64x2 = i64x2::new(15, 18); | |
14318 | let b: i32x4 = i32x4::new(0, 1, 4, 5); | |
14319 | let c: i32x2 = i32x2::new(0, 2); | |
14320 | let e: i64x2 = i64x2::new(-1, -2); | |
14321 | let r: i64x2 = transmute(vqdmlsl_high_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
14322 | assert_eq!(r, e); | |
14323 | } | |
14324 | ||
14325 | #[simd_test(enable = "neon")] | |
14326 | unsafe fn test_vqdmlsl_high_laneq_s32() { | |
14327 | let a: i64x2 = i64x2::new(15, 18); | |
14328 | let b: i32x4 = i32x4::new(0, 1, 4, 5); | |
14329 | let c: i32x4 = i32x4::new(0, 2, 0, 0); | |
14330 | let e: i64x2 = i64x2::new(-1, -2); | |
14331 | let r: i64x2 = transmute(vqdmlsl_high_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
14332 | assert_eq!(r, e); | |
14333 | } | |
14334 | ||
14335 | #[simd_test(enable = "neon")] | |
14336 | unsafe fn test_vqdmulhh_s16() { | |
14337 | let a: i16 = 1; | |
14338 | let b: i16 = 2; | |
14339 | let e: i16 = 0; | |
14340 | let r: i16 = transmute(vqdmulhh_s16(transmute(a), transmute(b))); | |
14341 | assert_eq!(r, e); | |
14342 | } | |
14343 | ||
14344 | #[simd_test(enable = "neon")] | |
14345 | unsafe fn test_vqdmulhs_s32() { | |
14346 | let a: i32 = 1; | |
14347 | let b: i32 = 2; | |
14348 | let e: i32 = 0; | |
14349 | let r: i32 = transmute(vqdmulhs_s32(transmute(a), transmute(b))); | |
14350 | assert_eq!(r, e); | |
14351 | } | |
14352 | ||
14353 | #[simd_test(enable = "neon")] | |
14354 | unsafe fn test_vqdmulhh_lane_s16() { | |
14355 | let a: i16 = 2; | |
14356 | let b: i16x4 = i16x4::new(0, 0, 0x7F_FF, 0); | |
14357 | let e: i16 = 1; | |
14358 | let r: i16 = transmute(vqdmulhh_lane_s16::<2>(transmute(a), transmute(b))); | |
14359 | assert_eq!(r, e); | |
14360 | } | |
14361 | ||
14362 | #[simd_test(enable = "neon")] | |
14363 | unsafe fn test_vqdmulhh_laneq_s16() { | |
14364 | let a: i16 = 2; | |
14365 | let b: i16x8 = i16x8::new(0, 0, 0x7F_FF, 0, 0, 0, 0, 0); | |
14366 | let e: i16 = 1; | |
14367 | let r: i16 = transmute(vqdmulhh_laneq_s16::<2>(transmute(a), transmute(b))); | |
14368 | assert_eq!(r, e); | |
14369 | } | |
14370 | ||
14371 | #[simd_test(enable = "neon")] | |
14372 | unsafe fn test_vqdmulhs_lane_s32() { | |
14373 | let a: i32 = 2; | |
14374 | let b: i32x2 = i32x2::new(0, 0x7F_FF_FF_FF); | |
14375 | let e: i32 = 1; | |
14376 | let r: i32 = transmute(vqdmulhs_lane_s32::<1>(transmute(a), transmute(b))); | |
14377 | assert_eq!(r, e); | |
14378 | } | |
14379 | ||
14380 | #[simd_test(enable = "neon")] | |
14381 | unsafe fn test_vqdmulhs_laneq_s32() { | |
14382 | let a: i32 = 2; | |
14383 | let b: i32x4 = i32x4::new(0, 0x7F_FF_FF_FF, 0, 0); | |
14384 | let e: i32 = 1; | |
14385 | let r: i32 = transmute(vqdmulhs_laneq_s32::<1>(transmute(a), transmute(b))); | |
14386 | assert_eq!(r, e); | |
14387 | } | |
14388 | ||
14389 | #[simd_test(enable = "neon")] | |
14390 | unsafe fn test_vqmovnh_s16() { | |
14391 | let a: i16 = 1; | |
14392 | let e: i8 = 1; | |
14393 | let r: i8 = transmute(vqmovnh_s16(transmute(a))); | |
14394 | assert_eq!(r, e); | |
14395 | } | |
14396 | ||
14397 | #[simd_test(enable = "neon")] | |
14398 | unsafe fn test_vqmovns_s32() { | |
14399 | let a: i32 = 1; | |
14400 | let e: i16 = 1; | |
14401 | let r: i16 = transmute(vqmovns_s32(transmute(a))); | |
14402 | assert_eq!(r, e); | |
14403 | } | |
14404 | ||
14405 | #[simd_test(enable = "neon")] | |
14406 | unsafe fn test_vqmovnh_u16() { | |
14407 | let a: u16 = 1; | |
14408 | let e: u8 = 1; | |
14409 | let r: u8 = transmute(vqmovnh_u16(transmute(a))); | |
14410 | assert_eq!(r, e); | |
14411 | } | |
14412 | ||
14413 | #[simd_test(enable = "neon")] | |
14414 | unsafe fn test_vqmovns_u32() { | |
14415 | let a: u32 = 1; | |
14416 | let e: u16 = 1; | |
14417 | let r: u16 = transmute(vqmovns_u32(transmute(a))); | |
14418 | assert_eq!(r, e); | |
14419 | } | |
14420 | ||
14421 | #[simd_test(enable = "neon")] | |
14422 | unsafe fn test_vqmovnd_s64() { | |
14423 | let a: i64 = 1; | |
14424 | let e: i32 = 1; | |
14425 | let r: i32 = transmute(vqmovnd_s64(transmute(a))); | |
14426 | assert_eq!(r, e); | |
14427 | } | |
14428 | ||
14429 | #[simd_test(enable = "neon")] | |
14430 | unsafe fn test_vqmovnd_u64() { | |
14431 | let a: u64 = 1; | |
14432 | let e: u32 = 1; | |
14433 | let r: u32 = transmute(vqmovnd_u64(transmute(a))); | |
14434 | assert_eq!(r, e); | |
14435 | } | |
14436 | ||
14437 | #[simd_test(enable = "neon")] | |
14438 | unsafe fn test_vqmovn_high_s16() { | |
14439 | let a: i8x8 = i8x8::new(0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F); | |
14440 | let b: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); | |
14441 | let e: i8x16 = i8x16::new(0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F); | |
14442 | let r: i8x16 = transmute(vqmovn_high_s16(transmute(a), transmute(b))); | |
14443 | assert_eq!(r, e); | |
14444 | } | |
14445 | ||
14446 | #[simd_test(enable = "neon")] | |
14447 | unsafe fn test_vqmovn_high_s32() { | |
14448 | let a: i16x4 = i16x4::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); | |
14449 | let b: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF); | |
14450 | let e: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); | |
14451 | let r: i16x8 = transmute(vqmovn_high_s32(transmute(a), transmute(b))); | |
14452 | assert_eq!(r, e); | |
14453 | } | |
14454 | ||
14455 | #[simd_test(enable = "neon")] | |
14456 | unsafe fn test_vqmovn_high_s64() { | |
14457 | let a: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF); | |
14458 | let b: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 0x7F_FF_FF_FF_FF_FF_FF_FF); | |
14459 | let e: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF); | |
14460 | let r: i32x4 = transmute(vqmovn_high_s64(transmute(a), transmute(b))); | |
14461 | assert_eq!(r, e); | |
14462 | } | |
14463 | ||
14464 | #[simd_test(enable = "neon")] | |
14465 | unsafe fn test_vqmovn_high_u16() { | |
14466 | let a: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); | |
14467 | let b: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); | |
14468 | let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); | |
14469 | let r: u8x16 = transmute(vqmovn_high_u16(transmute(a), transmute(b))); | |
14470 | assert_eq!(r, e); | |
14471 | } | |
14472 | ||
14473 | #[simd_test(enable = "neon")] | |
14474 | unsafe fn test_vqmovn_high_u32() { | |
14475 | let a: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); | |
14476 | let b: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); | |
14477 | let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); | |
14478 | let r: u16x8 = transmute(vqmovn_high_u32(transmute(a), transmute(b))); | |
14479 | assert_eq!(r, e); | |
14480 | } | |
14481 | ||
14482 | #[simd_test(enable = "neon")] | |
14483 | unsafe fn test_vqmovn_high_u64() { | |
14484 | let a: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); | |
14485 | let b: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); | |
14486 | let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); | |
14487 | let r: u32x4 = transmute(vqmovn_high_u64(transmute(a), transmute(b))); | |
14488 | assert_eq!(r, e); | |
14489 | } | |
14490 | ||
14491 | #[simd_test(enable = "neon")] | |
14492 | unsafe fn test_vqmovunh_s16() { | |
14493 | let a: i16 = 1; | |
14494 | let e: u8 = 1; | |
14495 | let r: u8 = transmute(vqmovunh_s16(transmute(a))); | |
14496 | assert_eq!(r, e); | |
14497 | } | |
14498 | ||
14499 | #[simd_test(enable = "neon")] | |
14500 | unsafe fn test_vqmovuns_s32() { | |
14501 | let a: i32 = 1; | |
14502 | let e: u16 = 1; | |
14503 | let r: u16 = transmute(vqmovuns_s32(transmute(a))); | |
14504 | assert_eq!(r, e); | |
14505 | } | |
14506 | ||
14507 | #[simd_test(enable = "neon")] | |
14508 | unsafe fn test_vqmovund_s64() { | |
14509 | let a: i64 = 1; | |
14510 | let e: u32 = 1; | |
14511 | let r: u32 = transmute(vqmovund_s64(transmute(a))); | |
14512 | assert_eq!(r, e); | |
14513 | } | |
14514 | ||
14515 | #[simd_test(enable = "neon")] | |
14516 | unsafe fn test_vqmovun_high_s16() { | |
14517 | let a: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
14518 | let b: i16x8 = i16x8::new(-1, -1, -1, -1, -1, -1, -1, -1); | |
14519 | let e: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
14520 | let r: u8x16 = transmute(vqmovun_high_s16(transmute(a), transmute(b))); | |
14521 | assert_eq!(r, e); | |
14522 | } | |
14523 | ||
14524 | #[simd_test(enable = "neon")] | |
14525 | unsafe fn test_vqmovun_high_s32() { | |
14526 | let a: u16x4 = u16x4::new(0, 0, 0, 0); | |
14527 | let b: i32x4 = i32x4::new(-1, -1, -1, -1); | |
14528 | let e: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
14529 | let r: u16x8 = transmute(vqmovun_high_s32(transmute(a), transmute(b))); | |
14530 | assert_eq!(r, e); | |
14531 | } | |
14532 | ||
14533 | #[simd_test(enable = "neon")] | |
14534 | unsafe fn test_vqmovun_high_s64() { | |
14535 | let a: u32x2 = u32x2::new(0, 0); | |
14536 | let b: i64x2 = i64x2::new(-1, -1); | |
14537 | let e: u32x4 = u32x4::new(0, 0, 0, 0); | |
14538 | let r: u32x4 = transmute(vqmovun_high_s64(transmute(a), transmute(b))); | |
14539 | assert_eq!(r, e); | |
14540 | } | |
14541 | ||
14542 | #[simd_test(enable = "neon")] | |
14543 | unsafe fn test_vqrdmulhh_s16() { | |
14544 | let a: i16 = 1; | |
14545 | let b: i16 = 2; | |
14546 | let e: i16 = 0; | |
14547 | let r: i16 = transmute(vqrdmulhh_s16(transmute(a), transmute(b))); | |
14548 | assert_eq!(r, e); | |
14549 | } | |
14550 | ||
14551 | #[simd_test(enable = "neon")] | |
14552 | unsafe fn test_vqrdmulhs_s32() { | |
14553 | let a: i32 = 1; | |
14554 | let b: i32 = 2; | |
14555 | let e: i32 = 0; | |
14556 | let r: i32 = transmute(vqrdmulhs_s32(transmute(a), transmute(b))); | |
14557 | assert_eq!(r, e); | |
14558 | } | |
14559 | ||
14560 | #[simd_test(enable = "neon")] | |
14561 | unsafe fn test_vqrdmulhh_lane_s16() { | |
14562 | let a: i16 = 1; | |
14563 | let b: i16x4 = i16x4::new(0, 2, 0, 0); | |
14564 | let e: i16 = 0; | |
14565 | let r: i16 = transmute(vqrdmulhh_lane_s16::<1>(transmute(a), transmute(b))); | |
14566 | assert_eq!(r, e); | |
14567 | } | |
14568 | ||
14569 | #[simd_test(enable = "neon")] | |
14570 | unsafe fn test_vqrdmulhh_laneq_s16() { | |
14571 | let a: i16 = 1; | |
14572 | let b: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
14573 | let e: i16 = 0; | |
14574 | let r: i16 = transmute(vqrdmulhh_laneq_s16::<1>(transmute(a), transmute(b))); | |
14575 | assert_eq!(r, e); | |
14576 | } | |
14577 | ||
14578 | #[simd_test(enable = "neon")] | |
14579 | unsafe fn test_vqrdmulhs_lane_s32() { | |
14580 | let a: i32 = 1; | |
14581 | let b: i32x2 = i32x2::new(0, 2); | |
14582 | let e: i32 = 0; | |
14583 | let r: i32 = transmute(vqrdmulhs_lane_s32::<1>(transmute(a), transmute(b))); | |
14584 | assert_eq!(r, e); | |
14585 | } | |
14586 | ||
14587 | #[simd_test(enable = "neon")] | |
14588 | unsafe fn test_vqrdmulhs_laneq_s32() { | |
14589 | let a: i32 = 1; | |
14590 | let b: i32x4 = i32x4::new(0, 2, 0, 0); | |
14591 | let e: i32 = 0; | |
14592 | let r: i32 = transmute(vqrdmulhs_laneq_s32::<1>(transmute(a), transmute(b))); | |
14593 | assert_eq!(r, e); | |
14594 | } | |
14595 | ||
14596 | #[simd_test(enable = "neon")] | |
14597 | unsafe fn test_vqrdmlahh_s16() { | |
14598 | let a: i16 = 1; | |
14599 | let b: i16 = 1; | |
14600 | let c: i16 = 2; | |
14601 | let e: i16 = 1; | |
14602 | let r: i16 = transmute(vqrdmlahh_s16(transmute(a), transmute(b), transmute(c))); | |
14603 | assert_eq!(r, e); | |
14604 | } | |
14605 | ||
14606 | #[simd_test(enable = "neon")] | |
14607 | unsafe fn test_vqrdmlahs_s32() { | |
14608 | let a: i32 = 1; | |
14609 | let b: i32 = 1; | |
14610 | let c: i32 = 2; | |
14611 | let e: i32 = 1; | |
14612 | let r: i32 = transmute(vqrdmlahs_s32(transmute(a), transmute(b), transmute(c))); | |
14613 | assert_eq!(r, e); | |
14614 | } | |
14615 | ||
14616 | #[simd_test(enable = "neon")] | |
14617 | unsafe fn test_vqrdmlahh_lane_s16() { | |
14618 | let a: i16 = 1; | |
14619 | let b: i16 = 1; | |
14620 | let c: i16x4 = i16x4::new(0, 2, 0, 0); | |
14621 | let e: i16 = 1; | |
14622 | let r: i16 = transmute(vqrdmlahh_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
14623 | assert_eq!(r, e); | |
14624 | } | |
14625 | ||
14626 | #[simd_test(enable = "neon")] | |
14627 | unsafe fn test_vqrdmlahh_laneq_s16() { | |
14628 | let a: i16 = 1; | |
14629 | let b: i16 = 1; | |
14630 | let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
14631 | let e: i16 = 1; | |
14632 | let r: i16 = transmute(vqrdmlahh_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
14633 | assert_eq!(r, e); | |
14634 | } | |
14635 | ||
14636 | #[simd_test(enable = "neon")] | |
14637 | unsafe fn test_vqrdmlahs_lane_s32() { | |
14638 | let a: i32 = 1; | |
14639 | let b: i32 = 1; | |
14640 | let c: i32x2 = i32x2::new(0, 2); | |
14641 | let e: i32 = 1; | |
14642 | let r: i32 = transmute(vqrdmlahs_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
14643 | assert_eq!(r, e); | |
14644 | } | |
14645 | ||
14646 | #[simd_test(enable = "neon")] | |
14647 | unsafe fn test_vqrdmlahs_laneq_s32() { | |
14648 | let a: i32 = 1; | |
14649 | let b: i32 = 1; | |
14650 | let c: i32x4 = i32x4::new(0, 2, 0, 0); | |
14651 | let e: i32 = 1; | |
14652 | let r: i32 = transmute(vqrdmlahs_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
14653 | assert_eq!(r, e); | |
14654 | } | |
14655 | ||
14656 | #[simd_test(enable = "neon")] | |
14657 | unsafe fn test_vqrdmlshh_s16() { | |
14658 | let a: i16 = 1; | |
14659 | let b: i16 = 1; | |
14660 | let c: i16 = 2; | |
14661 | let e: i16 = 1; | |
14662 | let r: i16 = transmute(vqrdmlshh_s16(transmute(a), transmute(b), transmute(c))); | |
14663 | assert_eq!(r, e); | |
14664 | } | |
14665 | ||
14666 | #[simd_test(enable = "neon")] | |
14667 | unsafe fn test_vqrdmlshs_s32() { | |
14668 | let a: i32 = 1; | |
14669 | let b: i32 = 1; | |
14670 | let c: i32 = 2; | |
14671 | let e: i32 = 1; | |
14672 | let r: i32 = transmute(vqrdmlshs_s32(transmute(a), transmute(b), transmute(c))); | |
14673 | assert_eq!(r, e); | |
14674 | } | |
14675 | ||
14676 | #[simd_test(enable = "neon")] | |
14677 | unsafe fn test_vqrdmlshh_lane_s16() { | |
14678 | let a: i16 = 1; | |
14679 | let b: i16 = 1; | |
14680 | let c: i16x4 = i16x4::new(0, 2, 0, 0); | |
14681 | let e: i16 = 1; | |
14682 | let r: i16 = transmute(vqrdmlshh_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
14683 | assert_eq!(r, e); | |
14684 | } | |
14685 | ||
14686 | #[simd_test(enable = "neon")] | |
14687 | unsafe fn test_vqrdmlshh_laneq_s16() { | |
14688 | let a: i16 = 1; | |
14689 | let b: i16 = 1; | |
14690 | let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); | |
14691 | let e: i16 = 1; | |
14692 | let r: i16 = transmute(vqrdmlshh_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); | |
14693 | assert_eq!(r, e); | |
14694 | } | |
14695 | ||
14696 | #[simd_test(enable = "neon")] | |
14697 | unsafe fn test_vqrdmlshs_lane_s32() { | |
14698 | let a: i32 = 1; | |
14699 | let b: i32 = 1; | |
14700 | let c: i32x2 = i32x2::new(0, 2); | |
14701 | let e: i32 = 1; | |
14702 | let r: i32 = transmute(vqrdmlshs_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
14703 | assert_eq!(r, e); | |
14704 | } | |
14705 | ||
14706 | #[simd_test(enable = "neon")] | |
14707 | unsafe fn test_vqrdmlshs_laneq_s32() { | |
14708 | let a: i32 = 1; | |
14709 | let b: i32 = 1; | |
14710 | let c: i32x4 = i32x4::new(0, 2, 0, 0); | |
14711 | let e: i32 = 1; | |
14712 | let r: i32 = transmute(vqrdmlshs_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); | |
14713 | assert_eq!(r, e); | |
14714 | } | |
14715 | ||
14716 | #[simd_test(enable = "neon")] | |
14717 | unsafe fn test_vqrshls_s32() { | |
14718 | let a: i32 = 2; | |
14719 | let b: i32 = 2; | |
14720 | let e: i32 = 8; | |
14721 | let r: i32 = transmute(vqrshls_s32(transmute(a), transmute(b))); | |
14722 | assert_eq!(r, e); | |
14723 | } | |
14724 | ||
14725 | #[simd_test(enable = "neon")] | |
14726 | unsafe fn test_vqrshld_s64() { | |
14727 | let a: i64 = 2; | |
14728 | let b: i64 = 2; | |
14729 | let e: i64 = 8; | |
14730 | let r: i64 = transmute(vqrshld_s64(transmute(a), transmute(b))); | |
14731 | assert_eq!(r, e); | |
14732 | } | |
14733 | ||
14734 | #[simd_test(enable = "neon")] | |
14735 | unsafe fn test_vqrshlb_s8() { | |
14736 | let a: i8 = 1; | |
14737 | let b: i8 = 2; | |
14738 | let e: i8 = 4; | |
14739 | let r: i8 = transmute(vqrshlb_s8(transmute(a), transmute(b))); | |
14740 | assert_eq!(r, e); | |
14741 | } | |
14742 | ||
14743 | #[simd_test(enable = "neon")] | |
14744 | unsafe fn test_vqrshlh_s16() { | |
14745 | let a: i16 = 1; | |
14746 | let b: i16 = 2; | |
14747 | let e: i16 = 4; | |
14748 | let r: i16 = transmute(vqrshlh_s16(transmute(a), transmute(b))); | |
14749 | assert_eq!(r, e); | |
14750 | } | |
14751 | ||
14752 | #[simd_test(enable = "neon")] | |
14753 | unsafe fn test_vqrshls_u32() { | |
14754 | let a: u32 = 2; | |
14755 | let b: i32 = 2; | |
14756 | let e: u32 = 8; | |
14757 | let r: u32 = transmute(vqrshls_u32(transmute(a), transmute(b))); | |
14758 | assert_eq!(r, e); | |
14759 | } | |
14760 | ||
14761 | #[simd_test(enable = "neon")] | |
14762 | unsafe fn test_vqrshld_u64() { | |
14763 | let a: u64 = 2; | |
14764 | let b: i64 = 2; | |
14765 | let e: u64 = 8; | |
14766 | let r: u64 = transmute(vqrshld_u64(transmute(a), transmute(b))); | |
14767 | assert_eq!(r, e); | |
14768 | } | |
14769 | ||
14770 | #[simd_test(enable = "neon")] | |
14771 | unsafe fn test_vqrshlb_u8() { | |
14772 | let a: u8 = 1; | |
14773 | let b: i8 = 2; | |
14774 | let e: u8 = 4; | |
14775 | let r: u8 = transmute(vqrshlb_u8(transmute(a), transmute(b))); | |
14776 | assert_eq!(r, e); | |
14777 | } | |
14778 | ||
14779 | #[simd_test(enable = "neon")] | |
14780 | unsafe fn test_vqrshlh_u16() { | |
14781 | let a: u16 = 1; | |
14782 | let b: i16 = 2; | |
14783 | let e: u16 = 4; | |
14784 | let r: u16 = transmute(vqrshlh_u16(transmute(a), transmute(b))); | |
14785 | assert_eq!(r, e); | |
14786 | } | |
14787 | ||
14788 | #[simd_test(enable = "neon")] | |
14789 | unsafe fn test_vqrshrnh_n_s16() { | |
14790 | let a: i16 = 4; | |
14791 | let e: i8 = 1; | |
14792 | let r: i8 = transmute(vqrshrnh_n_s16::<2>(transmute(a))); | |
14793 | assert_eq!(r, e); | |
14794 | } | |
14795 | ||
14796 | #[simd_test(enable = "neon")] | |
14797 | unsafe fn test_vqrshrns_n_s32() { | |
14798 | let a: i32 = 4; | |
14799 | let e: i16 = 1; | |
14800 | let r: i16 = transmute(vqrshrns_n_s32::<2>(transmute(a))); | |
14801 | assert_eq!(r, e); | |
14802 | } | |
14803 | ||
14804 | #[simd_test(enable = "neon")] | |
14805 | unsafe fn test_vqrshrnd_n_s64() { | |
14806 | let a: i64 = 4; | |
14807 | let e: i32 = 1; | |
14808 | let r: i32 = transmute(vqrshrnd_n_s64::<2>(transmute(a))); | |
14809 | assert_eq!(r, e); | |
14810 | } | |
14811 | ||
14812 | #[simd_test(enable = "neon")] | |
14813 | unsafe fn test_vqrshrn_high_n_s16() { | |
14814 | let a: i8x8 = i8x8::new(0, 1, 2, 3, 2, 3, 6, 7); | |
14815 | let b: i16x8 = i16x8::new(8, 12, 24, 28, 48, 52, 56, 60); | |
14816 | let e: i8x16 = i8x16::new(0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 12, 13, 14, 15); | |
14817 | let r: i8x16 = transmute(vqrshrn_high_n_s16::<2>(transmute(a), transmute(b))); | |
14818 | assert_eq!(r, e); | |
14819 | } | |
14820 | ||
14821 | #[simd_test(enable = "neon")] | |
14822 | unsafe fn test_vqrshrn_high_n_s32() { | |
14823 | let a: i16x4 = i16x4::new(0, 1, 2, 3); | |
14824 | let b: i32x4 = i32x4::new(8, 12, 24, 28); | |
14825 | let e: i16x8 = i16x8::new(0, 1, 2, 3, 2, 3, 6, 7); | |
14826 | let r: i16x8 = transmute(vqrshrn_high_n_s32::<2>(transmute(a), transmute(b))); | |
14827 | assert_eq!(r, e); | |
14828 | } | |
14829 | ||
14830 | #[simd_test(enable = "neon")] | |
14831 | unsafe fn test_vqrshrn_high_n_s64() { | |
14832 | let a: i32x2 = i32x2::new(0, 1); | |
14833 | let b: i64x2 = i64x2::new(8, 12); | |
14834 | let e: i32x4 = i32x4::new(0, 1, 2, 3); | |
14835 | let r: i32x4 = transmute(vqrshrn_high_n_s64::<2>(transmute(a), transmute(b))); | |
14836 | assert_eq!(r, e); | |
14837 | } | |
14838 | ||
14839 | #[simd_test(enable = "neon")] | |
14840 | unsafe fn test_vqrshrnh_n_u16() { | |
14841 | let a: u16 = 4; | |
14842 | let e: u8 = 1; | |
14843 | let r: u8 = transmute(vqrshrnh_n_u16::<2>(transmute(a))); | |
14844 | assert_eq!(r, e); | |
14845 | } | |
14846 | ||
14847 | #[simd_test(enable = "neon")] | |
14848 | unsafe fn test_vqrshrns_n_u32() { | |
14849 | let a: u32 = 4; | |
14850 | let e: u16 = 1; | |
14851 | let r: u16 = transmute(vqrshrns_n_u32::<2>(transmute(a))); | |
14852 | assert_eq!(r, e); | |
14853 | } | |
14854 | ||
14855 | #[simd_test(enable = "neon")] | |
14856 | unsafe fn test_vqrshrnd_n_u64() { | |
14857 | let a: u64 = 4; | |
14858 | let e: u32 = 1; | |
14859 | let r: u32 = transmute(vqrshrnd_n_u64::<2>(transmute(a))); | |
14860 | assert_eq!(r, e); | |
14861 | } | |
14862 | ||
14863 | #[simd_test(enable = "neon")] | |
14864 | unsafe fn test_vqrshrn_high_n_u16() { | |
14865 | let a: u8x8 = u8x8::new(0, 1, 2, 3, 2, 3, 6, 7); | |
14866 | let b: u16x8 = u16x8::new(8, 12, 24, 28, 48, 52, 56, 60); | |
14867 | let e: u8x16 = u8x16::new(0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 12, 13, 14, 15); | |
14868 | let r: u8x16 = transmute(vqrshrn_high_n_u16::<2>(transmute(a), transmute(b))); | |
14869 | assert_eq!(r, e); | |
14870 | } | |
14871 | ||
14872 | #[simd_test(enable = "neon")] | |
14873 | unsafe fn test_vqrshrn_high_n_u32() { | |
14874 | let a: u16x4 = u16x4::new(0, 1, 2, 3); | |
14875 | let b: u32x4 = u32x4::new(8, 12, 24, 28); | |
14876 | let e: u16x8 = u16x8::new(0, 1, 2, 3, 2, 3, 6, 7); | |
14877 | let r: u16x8 = transmute(vqrshrn_high_n_u32::<2>(transmute(a), transmute(b))); | |
14878 | assert_eq!(r, e); | |
14879 | } | |
14880 | ||
14881 | #[simd_test(enable = "neon")] | |
14882 | unsafe fn test_vqrshrn_high_n_u64() { | |
14883 | let a: u32x2 = u32x2::new(0, 1); | |
14884 | let b: u64x2 = u64x2::new(8, 12); | |
14885 | let e: u32x4 = u32x4::new(0, 1, 2, 3); | |
14886 | let r: u32x4 = transmute(vqrshrn_high_n_u64::<2>(transmute(a), transmute(b))); | |
14887 | assert_eq!(r, e); | |
14888 | } | |
14889 | ||
14890 | #[simd_test(enable = "neon")] | |
14891 | unsafe fn test_vqrshrunh_n_s16() { | |
14892 | let a: i16 = 4; | |
14893 | let e: u8 = 1; | |
14894 | let r: u8 = transmute(vqrshrunh_n_s16::<2>(transmute(a))); | |
14895 | assert_eq!(r, e); | |
14896 | } | |
14897 | ||
14898 | #[simd_test(enable = "neon")] | |
14899 | unsafe fn test_vqrshruns_n_s32() { | |
14900 | let a: i32 = 4; | |
14901 | let e: u16 = 1; | |
14902 | let r: u16 = transmute(vqrshruns_n_s32::<2>(transmute(a))); | |
14903 | assert_eq!(r, e); | |
14904 | } | |
14905 | ||
14906 | #[simd_test(enable = "neon")] | |
14907 | unsafe fn test_vqrshrund_n_s64() { | |
14908 | let a: i64 = 4; | |
14909 | let e: u32 = 1; | |
14910 | let r: u32 = transmute(vqrshrund_n_s64::<2>(transmute(a))); | |
14911 | assert_eq!(r, e); | |
14912 | } | |
14913 | ||
14914 | #[simd_test(enable = "neon")] | |
14915 | unsafe fn test_vqrshrun_high_n_s16() { | |
14916 | let a: u8x8 = u8x8::new(0, 1, 2, 3, 2, 3, 6, 7); | |
14917 | let b: i16x8 = i16x8::new(8, 12, 24, 28, 48, 52, 56, 60); | |
14918 | let e: u8x16 = u8x16::new(0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 12, 13, 14, 15); | |
14919 | let r: u8x16 = transmute(vqrshrun_high_n_s16::<2>(transmute(a), transmute(b))); | |
14920 | assert_eq!(r, e); | |
14921 | } | |
14922 | ||
14923 | #[simd_test(enable = "neon")] | |
14924 | unsafe fn test_vqrshrun_high_n_s32() { | |
14925 | let a: u16x4 = u16x4::new(0, 1, 2, 3); | |
14926 | let b: i32x4 = i32x4::new(8, 12, 24, 28); | |
14927 | let e: u16x8 = u16x8::new(0, 1, 2, 3, 2, 3, 6, 7); | |
14928 | let r: u16x8 = transmute(vqrshrun_high_n_s32::<2>(transmute(a), transmute(b))); | |
14929 | assert_eq!(r, e); | |
14930 | } | |
14931 | ||
14932 | #[simd_test(enable = "neon")] | |
14933 | unsafe fn test_vqrshrun_high_n_s64() { | |
14934 | let a: u32x2 = u32x2::new(0, 1); | |
14935 | let b: i64x2 = i64x2::new(8, 12); | |
14936 | let e: u32x4 = u32x4::new(0, 1, 2, 3); | |
14937 | let r: u32x4 = transmute(vqrshrun_high_n_s64::<2>(transmute(a), transmute(b))); | |
14938 | assert_eq!(r, e); | |
14939 | } | |
14940 | ||
14941 | #[simd_test(enable = "neon")] | |
14942 | unsafe fn test_vqshld_s64() { | |
14943 | let a: i64 = 0; | |
14944 | let b: i64 = 2; | |
14945 | let e: i64 = 0; | |
14946 | let r: i64 = transmute(vqshld_s64(transmute(a), transmute(b))); | |
14947 | assert_eq!(r, e); | |
14948 | } | |
14949 | ||
14950 | #[simd_test(enable = "neon")] | |
14951 | unsafe fn test_vqshlb_s8() { | |
14952 | let a: i8 = 1; | |
14953 | let b: i8 = 2; | |
14954 | let e: i8 = 4; | |
14955 | let r: i8 = transmute(vqshlb_s8(transmute(a), transmute(b))); | |
14956 | assert_eq!(r, e); | |
14957 | } | |
14958 | ||
14959 | #[simd_test(enable = "neon")] | |
14960 | unsafe fn test_vqshlh_s16() { | |
14961 | let a: i16 = 1; | |
14962 | let b: i16 = 2; | |
14963 | let e: i16 = 4; | |
14964 | let r: i16 = transmute(vqshlh_s16(transmute(a), transmute(b))); | |
14965 | assert_eq!(r, e); | |
14966 | } | |
14967 | ||
14968 | #[simd_test(enable = "neon")] | |
14969 | unsafe fn test_vqshls_s32() { | |
14970 | let a: i32 = 1; | |
14971 | let b: i32 = 2; | |
14972 | let e: i32 = 4; | |
14973 | let r: i32 = transmute(vqshls_s32(transmute(a), transmute(b))); | |
14974 | assert_eq!(r, e); | |
14975 | } | |
14976 | ||
14977 | #[simd_test(enable = "neon")] | |
14978 | unsafe fn test_vqshld_u64() { | |
14979 | let a: u64 = 0; | |
14980 | let b: i64 = 2; | |
14981 | let e: u64 = 0; | |
14982 | let r: u64 = transmute(vqshld_u64(transmute(a), transmute(b))); | |
14983 | assert_eq!(r, e); | |
14984 | } | |
14985 | ||
14986 | #[simd_test(enable = "neon")] | |
14987 | unsafe fn test_vqshlb_u8() { | |
14988 | let a: u8 = 1; | |
14989 | let b: i8 = 2; | |
14990 | let e: u8 = 4; | |
14991 | let r: u8 = transmute(vqshlb_u8(transmute(a), transmute(b))); | |
14992 | assert_eq!(r, e); | |
14993 | } | |
14994 | ||
14995 | #[simd_test(enable = "neon")] | |
14996 | unsafe fn test_vqshlh_u16() { | |
14997 | let a: u16 = 1; | |
14998 | let b: i16 = 2; | |
14999 | let e: u16 = 4; | |
15000 | let r: u16 = transmute(vqshlh_u16(transmute(a), transmute(b))); | |
15001 | assert_eq!(r, e); | |
15002 | } | |
15003 | ||
15004 | #[simd_test(enable = "neon")] | |
15005 | unsafe fn test_vqshls_u32() { | |
15006 | let a: u32 = 1; | |
15007 | let b: i32 = 2; | |
15008 | let e: u32 = 4; | |
15009 | let r: u32 = transmute(vqshls_u32(transmute(a), transmute(b))); | |
15010 | assert_eq!(r, e); | |
15011 | } | |
15012 | ||
15013 | #[simd_test(enable = "neon")] | |
15014 | unsafe fn test_vqshlb_n_s8() { | |
15015 | let a: i8 = 1; | |
15016 | let e: i8 = 4; | |
15017 | let r: i8 = transmute(vqshlb_n_s8::<2>(transmute(a))); | |
15018 | assert_eq!(r, e); | |
15019 | } | |
15020 | ||
15021 | #[simd_test(enable = "neon")] | |
15022 | unsafe fn test_vqshlh_n_s16() { | |
15023 | let a: i16 = 1; | |
15024 | let e: i16 = 4; | |
15025 | let r: i16 = transmute(vqshlh_n_s16::<2>(transmute(a))); | |
15026 | assert_eq!(r, e); | |
15027 | } | |
15028 | ||
15029 | #[simd_test(enable = "neon")] | |
15030 | unsafe fn test_vqshls_n_s32() { | |
15031 | let a: i32 = 1; | |
15032 | let e: i32 = 4; | |
15033 | let r: i32 = transmute(vqshls_n_s32::<2>(transmute(a))); | |
15034 | assert_eq!(r, e); | |
15035 | } | |
15036 | ||
15037 | #[simd_test(enable = "neon")] | |
15038 | unsafe fn test_vqshld_n_s64() { | |
15039 | let a: i64 = 1; | |
15040 | let e: i64 = 4; | |
15041 | let r: i64 = transmute(vqshld_n_s64::<2>(transmute(a))); | |
15042 | assert_eq!(r, e); | |
15043 | } | |
15044 | ||
15045 | #[simd_test(enable = "neon")] | |
15046 | unsafe fn test_vqshlb_n_u8() { | |
15047 | let a: u8 = 1; | |
15048 | let e: u8 = 4; | |
15049 | let r: u8 = transmute(vqshlb_n_u8::<2>(transmute(a))); | |
15050 | assert_eq!(r, e); | |
15051 | } | |
15052 | ||
15053 | #[simd_test(enable = "neon")] | |
15054 | unsafe fn test_vqshlh_n_u16() { | |
15055 | let a: u16 = 1; | |
15056 | let e: u16 = 4; | |
15057 | let r: u16 = transmute(vqshlh_n_u16::<2>(transmute(a))); | |
15058 | assert_eq!(r, e); | |
15059 | } | |
15060 | ||
15061 | #[simd_test(enable = "neon")] | |
15062 | unsafe fn test_vqshls_n_u32() { | |
15063 | let a: u32 = 1; | |
15064 | let e: u32 = 4; | |
15065 | let r: u32 = transmute(vqshls_n_u32::<2>(transmute(a))); | |
15066 | assert_eq!(r, e); | |
15067 | } | |
15068 | ||
15069 | #[simd_test(enable = "neon")] | |
15070 | unsafe fn test_vqshld_n_u64() { | |
15071 | let a: u64 = 1; | |
15072 | let e: u64 = 4; | |
15073 | let r: u64 = transmute(vqshld_n_u64::<2>(transmute(a))); | |
15074 | assert_eq!(r, e); | |
15075 | } | |
15076 | ||
15077 | #[simd_test(enable = "neon")] | |
15078 | unsafe fn test_vqshrnd_n_s64() { | |
15079 | let a: i64 = 0; | |
15080 | let e: i32 = 0; | |
15081 | let r: i32 = transmute(vqshrnd_n_s64::<2>(transmute(a))); | |
15082 | assert_eq!(r, e); | |
15083 | } | |
15084 | ||
15085 | #[simd_test(enable = "neon")] | |
15086 | unsafe fn test_vqshrnh_n_s16() { | |
15087 | let a: i16 = 4; | |
15088 | let e: i8 = 1; | |
15089 | let r: i8 = transmute(vqshrnh_n_s16::<2>(transmute(a))); | |
15090 | assert_eq!(r, e); | |
15091 | } | |
15092 | ||
15093 | #[simd_test(enable = "neon")] | |
15094 | unsafe fn test_vqshrns_n_s32() { | |
15095 | let a: i32 = 4; | |
15096 | let e: i16 = 1; | |
15097 | let r: i16 = transmute(vqshrns_n_s32::<2>(transmute(a))); | |
15098 | assert_eq!(r, e); | |
15099 | } | |
15100 | ||
15101 | #[simd_test(enable = "neon")] | |
15102 | unsafe fn test_vqshrn_high_n_s16() { | |
15103 | let a: i8x8 = i8x8::new(0, 1, 8, 9, 8, 9, 10, 11); | |
15104 | let b: i16x8 = i16x8::new(32, 36, 40, 44, 48, 52, 56, 60); | |
15105 | let e: i8x16 = i8x16::new(0, 1, 8, 9, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15); | |
15106 | let r: i8x16 = transmute(vqshrn_high_n_s16::<2>(transmute(a), transmute(b))); | |
15107 | assert_eq!(r, e); | |
15108 | } | |
15109 | ||
15110 | #[simd_test(enable = "neon")] | |
15111 | unsafe fn test_vqshrn_high_n_s32() { | |
15112 | let a: i16x4 = i16x4::new(0, 1, 8, 9); | |
15113 | let b: i32x4 = i32x4::new(32, 36, 40, 44); | |
15114 | let e: i16x8 = i16x8::new(0, 1, 8, 9, 8, 9, 10, 11); | |
15115 | let r: i16x8 = transmute(vqshrn_high_n_s32::<2>(transmute(a), transmute(b))); | |
15116 | assert_eq!(r, e); | |
15117 | } | |
15118 | ||
15119 | #[simd_test(enable = "neon")] | |
15120 | unsafe fn test_vqshrn_high_n_s64() { | |
15121 | let a: i32x2 = i32x2::new(0, 1); | |
15122 | let b: i64x2 = i64x2::new(32, 36); | |
15123 | let e: i32x4 = i32x4::new(0, 1, 8, 9); | |
15124 | let r: i32x4 = transmute(vqshrn_high_n_s64::<2>(transmute(a), transmute(b))); | |
15125 | assert_eq!(r, e); | |
15126 | } | |
15127 | ||
15128 | #[simd_test(enable = "neon")] | |
15129 | unsafe fn test_vqshrnd_n_u64() { | |
15130 | let a: u64 = 0; | |
15131 | let e: u32 = 0; | |
15132 | let r: u32 = transmute(vqshrnd_n_u64::<2>(transmute(a))); | |
15133 | assert_eq!(r, e); | |
15134 | } | |
15135 | ||
15136 | #[simd_test(enable = "neon")] | |
15137 | unsafe fn test_vqshrnh_n_u16() { | |
15138 | let a: u16 = 4; | |
15139 | let e: u8 = 1; | |
15140 | let r: u8 = transmute(vqshrnh_n_u16::<2>(transmute(a))); | |
15141 | assert_eq!(r, e); | |
15142 | } | |
15143 | ||
15144 | #[simd_test(enable = "neon")] | |
15145 | unsafe fn test_vqshrns_n_u32() { | |
15146 | let a: u32 = 4; | |
15147 | let e: u16 = 1; | |
15148 | let r: u16 = transmute(vqshrns_n_u32::<2>(transmute(a))); | |
15149 | assert_eq!(r, e); | |
15150 | } | |
15151 | ||
15152 | #[simd_test(enable = "neon")] | |
15153 | unsafe fn test_vqshrn_high_n_u16() { | |
15154 | let a: u8x8 = u8x8::new(0, 1, 8, 9, 8, 9, 10, 11); | |
15155 | let b: u16x8 = u16x8::new(32, 36, 40, 44, 48, 52, 56, 60); | |
15156 | let e: u8x16 = u8x16::new(0, 1, 8, 9, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15); | |
15157 | let r: u8x16 = transmute(vqshrn_high_n_u16::<2>(transmute(a), transmute(b))); | |
15158 | assert_eq!(r, e); | |
15159 | } | |
15160 | ||
15161 | #[simd_test(enable = "neon")] | |
15162 | unsafe fn test_vqshrn_high_n_u32() { | |
15163 | let a: u16x4 = u16x4::new(0, 1, 8, 9); | |
15164 | let b: u32x4 = u32x4::new(32, 36, 40, 44); | |
15165 | let e: u16x8 = u16x8::new(0, 1, 8, 9, 8, 9, 10, 11); | |
15166 | let r: u16x8 = transmute(vqshrn_high_n_u32::<2>(transmute(a), transmute(b))); | |
15167 | assert_eq!(r, e); | |
15168 | } | |
15169 | ||
15170 | #[simd_test(enable = "neon")] | |
15171 | unsafe fn test_vqshrn_high_n_u64() { | |
15172 | let a: u32x2 = u32x2::new(0, 1); | |
15173 | let b: u64x2 = u64x2::new(32, 36); | |
15174 | let e: u32x4 = u32x4::new(0, 1, 8, 9); | |
15175 | let r: u32x4 = transmute(vqshrn_high_n_u64::<2>(transmute(a), transmute(b))); | |
15176 | assert_eq!(r, e); | |
15177 | } | |
15178 | ||
15179 | #[simd_test(enable = "neon")] | |
15180 | unsafe fn test_vqshrunh_n_s16() { | |
15181 | let a: i16 = 4; | |
15182 | let e: u8 = 1; | |
15183 | let r: u8 = transmute(vqshrunh_n_s16::<2>(transmute(a))); | |
15184 | assert_eq!(r, e); | |
15185 | } | |
15186 | ||
15187 | #[simd_test(enable = "neon")] | |
15188 | unsafe fn test_vqshruns_n_s32() { | |
15189 | let a: i32 = 4; | |
15190 | let e: u16 = 1; | |
15191 | let r: u16 = transmute(vqshruns_n_s32::<2>(transmute(a))); | |
15192 | assert_eq!(r, e); | |
15193 | } | |
15194 | ||
15195 | #[simd_test(enable = "neon")] | |
15196 | unsafe fn test_vqshrund_n_s64() { | |
15197 | let a: i64 = 4; | |
15198 | let e: u32 = 1; | |
15199 | let r: u32 = transmute(vqshrund_n_s64::<2>(transmute(a))); | |
15200 | assert_eq!(r, e); | |
15201 | } | |
15202 | ||
15203 | #[simd_test(enable = "neon")] | |
15204 | unsafe fn test_vqshrun_high_n_s16() { | |
15205 | let a: u8x8 = u8x8::new(0, 1, 8, 9, 8, 9, 10, 11); | |
15206 | let b: i16x8 = i16x8::new(32, 36, 40, 44, 48, 52, 56, 60); | |
15207 | let e: u8x16 = u8x16::new(0, 1, 8, 9, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15); | |
15208 | let r: u8x16 = transmute(vqshrun_high_n_s16::<2>(transmute(a), transmute(b))); | |
15209 | assert_eq!(r, e); | |
15210 | } | |
15211 | ||
15212 | #[simd_test(enable = "neon")] | |
15213 | unsafe fn test_vqshrun_high_n_s32() { | |
15214 | let a: u16x4 = u16x4::new(0, 1, 8, 9); | |
15215 | let b: i32x4 = i32x4::new(32, 36, 40, 44); | |
15216 | let e: u16x8 = u16x8::new(0, 1, 8, 9, 8, 9, 10, 11); | |
15217 | let r: u16x8 = transmute(vqshrun_high_n_s32::<2>(transmute(a), transmute(b))); | |
15218 | assert_eq!(r, e); | |
15219 | } | |
15220 | ||
15221 | #[simd_test(enable = "neon")] | |
15222 | unsafe fn test_vqshrun_high_n_s64() { | |
15223 | let a: u32x2 = u32x2::new(0, 1); | |
15224 | let b: i64x2 = i64x2::new(32, 36); | |
15225 | let e: u32x4 = u32x4::new(0, 1, 8, 9); | |
15226 | let r: u32x4 = transmute(vqshrun_high_n_s64::<2>(transmute(a), transmute(b))); | |
15227 | assert_eq!(r, e); | |
15228 | } | |
15229 | ||
15230 | #[simd_test(enable = "neon")] | |
15231 | unsafe fn test_vsqrt_f32() { | |
15232 | let a: f32x2 = f32x2::new(4.0, 9.0); | |
15233 | let e: f32x2 = f32x2::new(2.0, 3.0); | |
15234 | let r: f32x2 = transmute(vsqrt_f32(transmute(a))); | |
15235 | assert_eq!(r, e); | |
15236 | } | |
15237 | ||
15238 | #[simd_test(enable = "neon")] | |
15239 | unsafe fn test_vsqrtq_f32() { | |
15240 | let a: f32x4 = f32x4::new(4.0, 9.0, 16.0, 25.0); | |
15241 | let e: f32x4 = f32x4::new(2.0, 3.0, 4.0, 5.0); | |
15242 | let r: f32x4 = transmute(vsqrtq_f32(transmute(a))); | |
15243 | assert_eq!(r, e); | |
15244 | } | |
15245 | ||
15246 | #[simd_test(enable = "neon")] | |
15247 | unsafe fn test_vsqrt_f64() { | |
15248 | let a: f64 = 4.0; | |
15249 | let e: f64 = 2.0; | |
15250 | let r: f64 = transmute(vsqrt_f64(transmute(a))); | |
15251 | assert_eq!(r, e); | |
15252 | } | |
15253 | ||
15254 | #[simd_test(enable = "neon")] | |
15255 | unsafe fn test_vsqrtq_f64() { | |
15256 | let a: f64x2 = f64x2::new(4.0, 9.0); | |
15257 | let e: f64x2 = f64x2::new(2.0, 3.0); | |
15258 | let r: f64x2 = transmute(vsqrtq_f64(transmute(a))); | |
15259 | assert_eq!(r, e); | |
15260 | } | |
15261 | ||
15262 | #[simd_test(enable = "neon")] | |
15263 | unsafe fn test_vrsqrte_f64() { | |
15264 | let a: f64 = 1.0; | |
15265 | let e: f64 = 0.998046875; | |
15266 | let r: f64 = transmute(vrsqrte_f64(transmute(a))); | |
15267 | assert_eq!(r, e); | |
15268 | } | |
15269 | ||
15270 | #[simd_test(enable = "neon")] | |
15271 | unsafe fn test_vrsqrteq_f64() { | |
15272 | let a: f64x2 = f64x2::new(1.0, 2.0); | |
15273 | let e: f64x2 = f64x2::new(0.998046875, 0.705078125); | |
15274 | let r: f64x2 = transmute(vrsqrteq_f64(transmute(a))); | |
15275 | assert_eq!(r, e); | |
15276 | } | |
15277 | ||
15278 | #[simd_test(enable = "neon")] | |
15279 | unsafe fn test_vrecpe_f64() { | |
15280 | let a: f64 = 4.0; | |
15281 | let e: f64 = 0.24951171875; | |
15282 | let r: f64 = transmute(vrecpe_f64(transmute(a))); | |
15283 | assert_eq!(r, e); | |
15284 | } | |
15285 | ||
15286 | #[simd_test(enable = "neon")] | |
15287 | unsafe fn test_vrecpeq_f64() { | |
15288 | let a: f64x2 = f64x2::new(4.0, 3.0); | |
15289 | let e: f64x2 = f64x2::new(0.24951171875, 0.3330078125); | |
15290 | let r: f64x2 = transmute(vrecpeq_f64(transmute(a))); | |
15291 | assert_eq!(r, e); | |
15292 | } | |
15293 | ||
15294 | #[simd_test(enable = "neon")] | |
15295 | unsafe fn test_vreinterpret_s64_p64() { | |
15296 | let a: i64x1 = i64x1::new(0); | |
15297 | let e: i64x1 = i64x1::new(0); | |
15298 | let r: i64x1 = transmute(vreinterpret_s64_p64(transmute(a))); | |
15299 | assert_eq!(r, e); | |
15300 | } | |
15301 | ||
15302 | #[simd_test(enable = "neon")] | |
15303 | unsafe fn test_vreinterpret_u64_p64() { | |
15304 | let a: i64x1 = i64x1::new(0); | |
15305 | let e: u64x1 = u64x1::new(0); | |
15306 | let r: u64x1 = transmute(vreinterpret_u64_p64(transmute(a))); | |
15307 | assert_eq!(r, e); | |
15308 | } | |
15309 | ||
15310 | #[simd_test(enable = "neon")] | |
15311 | unsafe fn test_vreinterpret_p64_s64() { | |
15312 | let a: i64x1 = i64x1::new(0); | |
15313 | let e: i64x1 = i64x1::new(0); | |
15314 | let r: i64x1 = transmute(vreinterpret_p64_s64(transmute(a))); | |
15315 | assert_eq!(r, e); | |
15316 | } | |
15317 | ||
15318 | #[simd_test(enable = "neon")] | |
15319 | unsafe fn test_vreinterpret_p64_u64() { | |
15320 | let a: u64x1 = u64x1::new(0); | |
15321 | let e: i64x1 = i64x1::new(0); | |
15322 | let r: i64x1 = transmute(vreinterpret_p64_u64(transmute(a))); | |
15323 | assert_eq!(r, e); | |
15324 | } | |
15325 | ||
15326 | #[simd_test(enable = "neon")] | |
15327 | unsafe fn test_vreinterpretq_s64_p64() { | |
15328 | let a: i64x2 = i64x2::new(0, 1); | |
15329 | let e: i64x2 = i64x2::new(0, 1); | |
15330 | let r: i64x2 = transmute(vreinterpretq_s64_p64(transmute(a))); | |
15331 | assert_eq!(r, e); | |
15332 | } | |
15333 | ||
15334 | #[simd_test(enable = "neon")] | |
15335 | unsafe fn test_vreinterpretq_u64_p64() { | |
15336 | let a: i64x2 = i64x2::new(0, 1); | |
15337 | let e: u64x2 = u64x2::new(0, 1); | |
15338 | let r: u64x2 = transmute(vreinterpretq_u64_p64(transmute(a))); | |
15339 | assert_eq!(r, e); | |
15340 | } | |
15341 | ||
15342 | #[simd_test(enable = "neon")] | |
15343 | unsafe fn test_vreinterpretq_p64_s64() { | |
15344 | let a: i64x2 = i64x2::new(0, 1); | |
15345 | let e: i64x2 = i64x2::new(0, 1); | |
15346 | let r: i64x2 = transmute(vreinterpretq_p64_s64(transmute(a))); | |
15347 | assert_eq!(r, e); | |
15348 | } | |
15349 | ||
15350 | #[simd_test(enable = "neon")] | |
15351 | unsafe fn test_vreinterpretq_p64_u64() { | |
15352 | let a: u64x2 = u64x2::new(0, 1); | |
15353 | let e: i64x2 = i64x2::new(0, 1); | |
15354 | let r: i64x2 = transmute(vreinterpretq_p64_u64(transmute(a))); | |
15355 | assert_eq!(r, e); | |
15356 | } | |
15357 | ||
15358 | #[simd_test(enable = "neon")] | |
15359 | unsafe fn test_vreinterpret_s32_p64() { | |
15360 | let a: i64x1 = i64x1::new(0); | |
15361 | let e: i32x2 = i32x2::new(0, 0); | |
15362 | let r: i32x2 = transmute(vreinterpret_s32_p64(transmute(a))); | |
15363 | assert_eq!(r, e); | |
15364 | } | |
15365 | ||
15366 | #[simd_test(enable = "neon")] | |
15367 | unsafe fn test_vreinterpret_u32_p64() { | |
15368 | let a: i64x1 = i64x1::new(0); | |
15369 | let e: u32x2 = u32x2::new(0, 0); | |
15370 | let r: u32x2 = transmute(vreinterpret_u32_p64(transmute(a))); | |
15371 | assert_eq!(r, e); | |
15372 | } | |
15373 | ||
15374 | #[simd_test(enable = "neon")] | |
15375 | unsafe fn test_vreinterpretq_s32_p64() { | |
15376 | let a: i64x2 = i64x2::new(0, 1); | |
15377 | let e: i32x4 = i32x4::new(0, 0, 1, 0); | |
15378 | let r: i32x4 = transmute(vreinterpretq_s32_p64(transmute(a))); | |
15379 | assert_eq!(r, e); | |
15380 | } | |
15381 | ||
15382 | #[simd_test(enable = "neon")] | |
15383 | unsafe fn test_vreinterpretq_u32_p64() { | |
15384 | let a: i64x2 = i64x2::new(0, 1); | |
15385 | let e: u32x4 = u32x4::new(0, 0, 1, 0); | |
15386 | let r: u32x4 = transmute(vreinterpretq_u32_p64(transmute(a))); | |
15387 | assert_eq!(r, e); | |
15388 | } | |
15389 | ||
15390 | #[simd_test(enable = "neon")] | |
15391 | unsafe fn test_vreinterpret_p64_s32() { | |
15392 | let a: i32x2 = i32x2::new(0, 0); | |
15393 | let e: i64x1 = i64x1::new(0); | |
15394 | let r: i64x1 = transmute(vreinterpret_p64_s32(transmute(a))); | |
15395 | assert_eq!(r, e); | |
15396 | } | |
15397 | ||
15398 | #[simd_test(enable = "neon")] | |
15399 | unsafe fn test_vreinterpret_p64_u32() { | |
15400 | let a: u32x2 = u32x2::new(0, 0); | |
15401 | let e: i64x1 = i64x1::new(0); | |
15402 | let r: i64x1 = transmute(vreinterpret_p64_u32(transmute(a))); | |
15403 | assert_eq!(r, e); | |
15404 | } | |
15405 | ||
15406 | #[simd_test(enable = "neon")] | |
15407 | unsafe fn test_vreinterpretq_p64_s32() { | |
15408 | let a: i32x4 = i32x4::new(0, 0, 1, 0); | |
15409 | let e: i64x2 = i64x2::new(0, 1); | |
15410 | let r: i64x2 = transmute(vreinterpretq_p64_s32(transmute(a))); | |
15411 | assert_eq!(r, e); | |
15412 | } | |
15413 | ||
15414 | #[simd_test(enable = "neon")] | |
15415 | unsafe fn test_vreinterpretq_p64_u32() { | |
15416 | let a: u32x4 = u32x4::new(0, 0, 1, 0); | |
15417 | let e: i64x2 = i64x2::new(0, 1); | |
15418 | let r: i64x2 = transmute(vreinterpretq_p64_u32(transmute(a))); | |
15419 | assert_eq!(r, e); | |
15420 | } | |
15421 | ||
15422 | #[simd_test(enable = "neon")] | |
15423 | unsafe fn test_vreinterpret_s16_p64() { | |
15424 | let a: i64x1 = i64x1::new(0); | |
15425 | let e: i16x4 = i16x4::new(0, 0, 0, 0); | |
15426 | let r: i16x4 = transmute(vreinterpret_s16_p64(transmute(a))); | |
15427 | assert_eq!(r, e); | |
15428 | } | |
15429 | ||
15430 | #[simd_test(enable = "neon")] | |
15431 | unsafe fn test_vreinterpret_u16_p64() { | |
15432 | let a: i64x1 = i64x1::new(0); | |
15433 | let e: u16x4 = u16x4::new(0, 0, 0, 0); | |
15434 | let r: u16x4 = transmute(vreinterpret_u16_p64(transmute(a))); | |
15435 | assert_eq!(r, e); | |
15436 | } | |
15437 | ||
15438 | #[simd_test(enable = "neon")] | |
15439 | unsafe fn test_vreinterpret_p16_p64() { | |
15440 | let a: i64x1 = i64x1::new(0); | |
15441 | let e: i16x4 = i16x4::new(0, 0, 0, 0); | |
15442 | let r: i16x4 = transmute(vreinterpret_p16_p64(transmute(a))); | |
15443 | assert_eq!(r, e); | |
15444 | } | |
15445 | ||
15446 | #[simd_test(enable = "neon")] | |
15447 | unsafe fn test_vreinterpretq_s16_p64() { | |
15448 | let a: i64x2 = i64x2::new(0, 1); | |
15449 | let e: i16x8 = i16x8::new(0, 0, 0, 0, 1, 0, 0, 0); | |
15450 | let r: i16x8 = transmute(vreinterpretq_s16_p64(transmute(a))); | |
15451 | assert_eq!(r, e); | |
15452 | } | |
15453 | ||
15454 | #[simd_test(enable = "neon")] | |
15455 | unsafe fn test_vreinterpretq_u16_p64() { | |
15456 | let a: i64x2 = i64x2::new(0, 1); | |
15457 | let e: u16x8 = u16x8::new(0, 0, 0, 0, 1, 0, 0, 0); | |
15458 | let r: u16x8 = transmute(vreinterpretq_u16_p64(transmute(a))); | |
15459 | assert_eq!(r, e); | |
15460 | } | |
15461 | ||
15462 | #[simd_test(enable = "neon")] | |
15463 | unsafe fn test_vreinterpretq_p16_p64() { | |
15464 | let a: i64x2 = i64x2::new(0, 1); | |
15465 | let e: i16x8 = i16x8::new(0, 0, 0, 0, 1, 0, 0, 0); | |
15466 | let r: i16x8 = transmute(vreinterpretq_p16_p64(transmute(a))); | |
15467 | assert_eq!(r, e); | |
15468 | } | |
15469 | ||
15470 | #[simd_test(enable = "neon")] | |
15471 | unsafe fn test_vreinterpret_p64_p16() { | |
15472 | let a: i16x4 = i16x4::new(0, 0, 0, 0); | |
15473 | let e: i64x1 = i64x1::new(0); | |
15474 | let r: i64x1 = transmute(vreinterpret_p64_p16(transmute(a))); | |
15475 | assert_eq!(r, e); | |
15476 | } | |
15477 | ||
15478 | #[simd_test(enable = "neon")] | |
15479 | unsafe fn test_vreinterpret_p64_s16() { | |
15480 | let a: i16x4 = i16x4::new(0, 0, 0, 0); | |
15481 | let e: i64x1 = i64x1::new(0); | |
15482 | let r: i64x1 = transmute(vreinterpret_p64_s16(transmute(a))); | |
15483 | assert_eq!(r, e); | |
15484 | } | |
15485 | ||
15486 | #[simd_test(enable = "neon")] | |
15487 | unsafe fn test_vreinterpret_p64_u16() { | |
15488 | let a: u16x4 = u16x4::new(0, 0, 0, 0); | |
15489 | let e: i64x1 = i64x1::new(0); | |
15490 | let r: i64x1 = transmute(vreinterpret_p64_u16(transmute(a))); | |
15491 | assert_eq!(r, e); | |
15492 | } | |
15493 | ||
15494 | #[simd_test(enable = "neon")] | |
15495 | unsafe fn test_vreinterpretq_p64_p16() { | |
15496 | let a: i16x8 = i16x8::new(0, 0, 0, 0, 1, 0, 0, 0); | |
15497 | let e: i64x2 = i64x2::new(0, 1); | |
15498 | let r: i64x2 = transmute(vreinterpretq_p64_p16(transmute(a))); | |
15499 | assert_eq!(r, e); | |
15500 | } | |
15501 | ||
15502 | #[simd_test(enable = "neon")] | |
15503 | unsafe fn test_vreinterpretq_p64_s16() { | |
15504 | let a: i16x8 = i16x8::new(0, 0, 0, 0, 1, 0, 0, 0); | |
15505 | let e: i64x2 = i64x2::new(0, 1); | |
15506 | let r: i64x2 = transmute(vreinterpretq_p64_s16(transmute(a))); | |
15507 | assert_eq!(r, e); | |
15508 | } | |
15509 | ||
15510 | #[simd_test(enable = "neon")] | |
15511 | unsafe fn test_vreinterpretq_p64_u16() { | |
15512 | let a: u16x8 = u16x8::new(0, 0, 0, 0, 1, 0, 0, 0); | |
15513 | let e: i64x2 = i64x2::new(0, 1); | |
15514 | let r: i64x2 = transmute(vreinterpretq_p64_u16(transmute(a))); | |
15515 | assert_eq!(r, e); | |
15516 | } | |
15517 | ||
15518 | #[simd_test(enable = "neon")] | |
15519 | unsafe fn test_vreinterpret_s8_p64() { | |
15520 | let a: i64x1 = i64x1::new(0); | |
15521 | let e: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15522 | let r: i8x8 = transmute(vreinterpret_s8_p64(transmute(a))); | |
15523 | assert_eq!(r, e); | |
15524 | } | |
15525 | ||
15526 | #[simd_test(enable = "neon")] | |
15527 | unsafe fn test_vreinterpret_u8_p64() { | |
15528 | let a: i64x1 = i64x1::new(0); | |
15529 | let e: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15530 | let r: u8x8 = transmute(vreinterpret_u8_p64(transmute(a))); | |
15531 | assert_eq!(r, e); | |
15532 | } | |
15533 | ||
15534 | #[simd_test(enable = "neon")] | |
15535 | unsafe fn test_vreinterpret_p8_p64() { | |
15536 | let a: i64x1 = i64x1::new(0); | |
15537 | let e: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15538 | let r: i8x8 = transmute(vreinterpret_p8_p64(transmute(a))); | |
15539 | assert_eq!(r, e); | |
15540 | } | |
15541 | ||
15542 | #[simd_test(enable = "neon")] | |
15543 | unsafe fn test_vreinterpretq_s8_p64() { | |
15544 | let a: i64x2 = i64x2::new(0, 1); | |
15545 | let e: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); | |
15546 | let r: i8x16 = transmute(vreinterpretq_s8_p64(transmute(a))); | |
15547 | assert_eq!(r, e); | |
15548 | } | |
15549 | ||
15550 | #[simd_test(enable = "neon")] | |
15551 | unsafe fn test_vreinterpretq_u8_p64() { | |
15552 | let a: i64x2 = i64x2::new(0, 1); | |
15553 | let e: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); | |
15554 | let r: u8x16 = transmute(vreinterpretq_u8_p64(transmute(a))); | |
15555 | assert_eq!(r, e); | |
15556 | } | |
15557 | ||
15558 | #[simd_test(enable = "neon")] | |
15559 | unsafe fn test_vreinterpretq_p8_p64() { | |
15560 | let a: i64x2 = i64x2::new(0, 1); | |
15561 | let e: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); | |
15562 | let r: i8x16 = transmute(vreinterpretq_p8_p64(transmute(a))); | |
15563 | assert_eq!(r, e); | |
15564 | } | |
15565 | ||
15566 | #[simd_test(enable = "neon")] | |
15567 | unsafe fn test_vreinterpret_p64_p8() { | |
15568 | let a: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15569 | let e: i64x1 = i64x1::new(0); | |
15570 | let r: i64x1 = transmute(vreinterpret_p64_p8(transmute(a))); | |
15571 | assert_eq!(r, e); | |
15572 | } | |
15573 | ||
15574 | #[simd_test(enable = "neon")] | |
15575 | unsafe fn test_vreinterpret_p64_s8() { | |
15576 | let a: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15577 | let e: i64x1 = i64x1::new(0); | |
15578 | let r: i64x1 = transmute(vreinterpret_p64_s8(transmute(a))); | |
15579 | assert_eq!(r, e); | |
15580 | } | |
15581 | ||
15582 | #[simd_test(enable = "neon")] | |
15583 | unsafe fn test_vreinterpret_p64_u8() { | |
15584 | let a: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15585 | let e: i64x1 = i64x1::new(0); | |
15586 | let r: i64x1 = transmute(vreinterpret_p64_u8(transmute(a))); | |
15587 | assert_eq!(r, e); | |
15588 | } | |
15589 | ||
15590 | #[simd_test(enable = "neon")] | |
15591 | unsafe fn test_vreinterpretq_p64_p8() { | |
15592 | let a: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); | |
15593 | let e: i64x2 = i64x2::new(0, 1); | |
15594 | let r: i64x2 = transmute(vreinterpretq_p64_p8(transmute(a))); | |
15595 | assert_eq!(r, e); | |
15596 | } | |
15597 | ||
15598 | #[simd_test(enable = "neon")] | |
15599 | unsafe fn test_vreinterpretq_p64_s8() { | |
15600 | let a: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); | |
15601 | let e: i64x2 = i64x2::new(0, 1); | |
15602 | let r: i64x2 = transmute(vreinterpretq_p64_s8(transmute(a))); | |
15603 | assert_eq!(r, e); | |
15604 | } | |
15605 | ||
15606 | #[simd_test(enable = "neon")] | |
15607 | unsafe fn test_vreinterpretq_p64_u8() { | |
15608 | let a: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); | |
15609 | let e: i64x2 = i64x2::new(0, 1); | |
15610 | let r: i64x2 = transmute(vreinterpretq_p64_u8(transmute(a))); | |
15611 | assert_eq!(r, e); | |
15612 | } | |
15613 | ||
15614 | #[simd_test(enable = "neon")] | |
15615 | unsafe fn test_vreinterpret_s8_f64() { | |
15616 | let a: f64 = 0.; | |
15617 | let e: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15618 | let r: i8x8 = transmute(vreinterpret_s8_f64(transmute(a))); | |
15619 | assert_eq!(r, e); | |
15620 | } | |
15621 | ||
15622 | #[simd_test(enable = "neon")] | |
15623 | unsafe fn test_vreinterpret_s16_f64() { | |
15624 | let a: f64 = 0.; | |
15625 | let e: i16x4 = i16x4::new(0, 0, 0, 0); | |
15626 | let r: i16x4 = transmute(vreinterpret_s16_f64(transmute(a))); | |
15627 | assert_eq!(r, e); | |
15628 | } | |
15629 | ||
15630 | #[simd_test(enable = "neon")] | |
15631 | unsafe fn test_vreinterpret_s32_f64() { | |
15632 | let a: f64 = 0.; | |
15633 | let e: i32x2 = i32x2::new(0, 0); | |
15634 | let r: i32x2 = transmute(vreinterpret_s32_f64(transmute(a))); | |
15635 | assert_eq!(r, e); | |
15636 | } | |
15637 | ||
15638 | #[simd_test(enable = "neon")] | |
15639 | unsafe fn test_vreinterpret_s64_f64() { | |
15640 | let a: f64 = 0.; | |
15641 | let e: i64x1 = i64x1::new(0); | |
15642 | let r: i64x1 = transmute(vreinterpret_s64_f64(transmute(a))); | |
15643 | assert_eq!(r, e); | |
15644 | } | |
15645 | ||
15646 | #[simd_test(enable = "neon")] | |
15647 | unsafe fn test_vreinterpretq_s8_f64() { | |
15648 | let a: f64x2 = f64x2::new(0., 0.); | |
15649 | let e: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
15650 | let r: i8x16 = transmute(vreinterpretq_s8_f64(transmute(a))); | |
15651 | assert_eq!(r, e); | |
15652 | } | |
15653 | ||
15654 | #[simd_test(enable = "neon")] | |
15655 | unsafe fn test_vreinterpretq_s16_f64() { | |
15656 | let a: f64x2 = f64x2::new(0., 0.); | |
15657 | let e: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15658 | let r: i16x8 = transmute(vreinterpretq_s16_f64(transmute(a))); | |
15659 | assert_eq!(r, e); | |
15660 | } | |
15661 | ||
15662 | #[simd_test(enable = "neon")] | |
15663 | unsafe fn test_vreinterpretq_s32_f64() { | |
15664 | let a: f64x2 = f64x2::new(0., 0.); | |
15665 | let e: i32x4 = i32x4::new(0, 0, 0, 0); | |
15666 | let r: i32x4 = transmute(vreinterpretq_s32_f64(transmute(a))); | |
15667 | assert_eq!(r, e); | |
15668 | } | |
15669 | ||
15670 | #[simd_test(enable = "neon")] | |
15671 | unsafe fn test_vreinterpretq_s64_f64() { | |
15672 | let a: f64x2 = f64x2::new(0., 0.); | |
15673 | let e: i64x2 = i64x2::new(0, 0); | |
15674 | let r: i64x2 = transmute(vreinterpretq_s64_f64(transmute(a))); | |
15675 | assert_eq!(r, e); | |
15676 | } | |
15677 | ||
15678 | #[simd_test(enable = "neon")] | |
15679 | unsafe fn test_vreinterpret_u8_f64() { | |
15680 | let a: f64 = 0.; | |
15681 | let e: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15682 | let r: u8x8 = transmute(vreinterpret_u8_f64(transmute(a))); | |
15683 | assert_eq!(r, e); | |
15684 | } | |
15685 | ||
15686 | #[simd_test(enable = "neon")] | |
15687 | unsafe fn test_vreinterpret_u16_f64() { | |
15688 | let a: f64 = 0.; | |
15689 | let e: u16x4 = u16x4::new(0, 0, 0, 0); | |
15690 | let r: u16x4 = transmute(vreinterpret_u16_f64(transmute(a))); | |
15691 | assert_eq!(r, e); | |
15692 | } | |
15693 | ||
15694 | #[simd_test(enable = "neon")] | |
15695 | unsafe fn test_vreinterpret_u32_f64() { | |
15696 | let a: f64 = 0.; | |
15697 | let e: u32x2 = u32x2::new(0, 0); | |
15698 | let r: u32x2 = transmute(vreinterpret_u32_f64(transmute(a))); | |
15699 | assert_eq!(r, e); | |
15700 | } | |
15701 | ||
15702 | #[simd_test(enable = "neon")] | |
15703 | unsafe fn test_vreinterpret_u64_f64() { | |
15704 | let a: f64 = 0.; | |
15705 | let e: u64x1 = u64x1::new(0); | |
15706 | let r: u64x1 = transmute(vreinterpret_u64_f64(transmute(a))); | |
15707 | assert_eq!(r, e); | |
15708 | } | |
15709 | ||
15710 | #[simd_test(enable = "neon")] | |
15711 | unsafe fn test_vreinterpretq_u8_f64() { | |
15712 | let a: f64x2 = f64x2::new(0., 0.); | |
15713 | let e: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
15714 | let r: u8x16 = transmute(vreinterpretq_u8_f64(transmute(a))); | |
15715 | assert_eq!(r, e); | |
15716 | } | |
15717 | ||
15718 | #[simd_test(enable = "neon")] | |
15719 | unsafe fn test_vreinterpretq_u16_f64() { | |
15720 | let a: f64x2 = f64x2::new(0., 0.); | |
15721 | let e: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15722 | let r: u16x8 = transmute(vreinterpretq_u16_f64(transmute(a))); | |
15723 | assert_eq!(r, e); | |
15724 | } | |
15725 | ||
15726 | #[simd_test(enable = "neon")] | |
15727 | unsafe fn test_vreinterpretq_u32_f64() { | |
15728 | let a: f64x2 = f64x2::new(0., 0.); | |
15729 | let e: u32x4 = u32x4::new(0, 0, 0, 0); | |
15730 | let r: u32x4 = transmute(vreinterpretq_u32_f64(transmute(a))); | |
15731 | assert_eq!(r, e); | |
15732 | } | |
15733 | ||
15734 | #[simd_test(enable = "neon")] | |
15735 | unsafe fn test_vreinterpretq_u64_f64() { | |
15736 | let a: f64x2 = f64x2::new(0., 0.); | |
15737 | let e: u64x2 = u64x2::new(0, 0); | |
15738 | let r: u64x2 = transmute(vreinterpretq_u64_f64(transmute(a))); | |
15739 | assert_eq!(r, e); | |
15740 | } | |
15741 | ||
15742 | #[simd_test(enable = "neon")] | |
15743 | unsafe fn test_vreinterpret_p8_f64() { | |
15744 | let a: f64 = 0.; | |
15745 | let e: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15746 | let r: i8x8 = transmute(vreinterpret_p8_f64(transmute(a))); | |
15747 | assert_eq!(r, e); | |
15748 | } | |
15749 | ||
15750 | #[simd_test(enable = "neon")] | |
15751 | unsafe fn test_vreinterpret_p16_f64() { | |
15752 | let a: f64 = 0.; | |
15753 | let e: i16x4 = i16x4::new(0, 0, 0, 0); | |
15754 | let r: i16x4 = transmute(vreinterpret_p16_f64(transmute(a))); | |
15755 | assert_eq!(r, e); | |
15756 | } | |
15757 | ||
15758 | #[simd_test(enable = "neon")] | |
15759 | unsafe fn test_vreinterpret_p64_f32() { | |
15760 | let a: f32x2 = f32x2::new(0., 0.); | |
15761 | let e: i64x1 = i64x1::new(0); | |
15762 | let r: i64x1 = transmute(vreinterpret_p64_f32(transmute(a))); | |
15763 | assert_eq!(r, e); | |
15764 | } | |
15765 | ||
15766 | #[simd_test(enable = "neon")] | |
15767 | unsafe fn test_vreinterpret_p64_f64() { | |
15768 | let a: f64 = 0.; | |
15769 | let e: i64x1 = i64x1::new(0); | |
15770 | let r: i64x1 = transmute(vreinterpret_p64_f64(transmute(a))); | |
15771 | assert_eq!(r, e); | |
15772 | } | |
15773 | ||
15774 | #[simd_test(enable = "neon")] | |
15775 | unsafe fn test_vreinterpretq_p8_f64() { | |
15776 | let a: f64x2 = f64x2::new(0., 0.); | |
15777 | let e: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
15778 | let r: i8x16 = transmute(vreinterpretq_p8_f64(transmute(a))); | |
15779 | assert_eq!(r, e); | |
15780 | } | |
15781 | ||
15782 | #[simd_test(enable = "neon")] | |
15783 | unsafe fn test_vreinterpretq_p16_f64() { | |
15784 | let a: f64x2 = f64x2::new(0., 0.); | |
15785 | let e: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15786 | let r: i16x8 = transmute(vreinterpretq_p16_f64(transmute(a))); | |
15787 | assert_eq!(r, e); | |
15788 | } | |
15789 | ||
15790 | #[simd_test(enable = "neon")] | |
15791 | unsafe fn test_vreinterpretq_p64_f32() { | |
15792 | let a: f32x4 = f32x4::new(0., 0., 0., 0.); | |
15793 | let e: i64x2 = i64x2::new(0, 0); | |
15794 | let r: i64x2 = transmute(vreinterpretq_p64_f32(transmute(a))); | |
15795 | assert_eq!(r, e); | |
15796 | } | |
15797 | ||
15798 | #[simd_test(enable = "neon")] | |
15799 | unsafe fn test_vreinterpretq_p64_f64() { | |
15800 | let a: f64x2 = f64x2::new(0., 0.); | |
15801 | let e: i64x2 = i64x2::new(0, 0); | |
15802 | let r: i64x2 = transmute(vreinterpretq_p64_f64(transmute(a))); | |
15803 | assert_eq!(r, e); | |
15804 | } | |
15805 | ||
15806 | #[simd_test(enable = "neon")] | |
15807 | unsafe fn test_vreinterpret_f64_s8() { | |
15808 | let a: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15809 | let e: f64 = 0.; | |
15810 | let r: f64 = transmute(vreinterpret_f64_s8(transmute(a))); | |
15811 | assert_eq!(r, e); | |
15812 | } | |
15813 | ||
15814 | #[simd_test(enable = "neon")] | |
15815 | unsafe fn test_vreinterpret_f64_s16() { | |
15816 | let a: i16x4 = i16x4::new(0, 0, 0, 0); | |
15817 | let e: f64 = 0.; | |
15818 | let r: f64 = transmute(vreinterpret_f64_s16(transmute(a))); | |
15819 | assert_eq!(r, e); | |
15820 | } | |
15821 | ||
15822 | #[simd_test(enable = "neon")] | |
15823 | unsafe fn test_vreinterpret_f64_s32() { | |
15824 | let a: i32x2 = i32x2::new(0, 0); | |
15825 | let e: f64 = 0.; | |
15826 | let r: f64 = transmute(vreinterpret_f64_s32(transmute(a))); | |
15827 | assert_eq!(r, e); | |
15828 | } | |
15829 | ||
15830 | #[simd_test(enable = "neon")] | |
15831 | unsafe fn test_vreinterpret_f64_s64() { | |
15832 | let a: i64x1 = i64x1::new(0); | |
15833 | let e: f64 = 0.; | |
15834 | let r: f64 = transmute(vreinterpret_f64_s64(transmute(a))); | |
15835 | assert_eq!(r, e); | |
15836 | } | |
15837 | ||
15838 | #[simd_test(enable = "neon")] | |
15839 | unsafe fn test_vreinterpretq_f64_s8() { | |
15840 | let a: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
15841 | let e: f64x2 = f64x2::new(0., 0.); | |
15842 | let r: f64x2 = transmute(vreinterpretq_f64_s8(transmute(a))); | |
15843 | assert_eq!(r, e); | |
15844 | } | |
15845 | ||
15846 | #[simd_test(enable = "neon")] | |
15847 | unsafe fn test_vreinterpretq_f64_s16() { | |
15848 | let a: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15849 | let e: f64x2 = f64x2::new(0., 0.); | |
15850 | let r: f64x2 = transmute(vreinterpretq_f64_s16(transmute(a))); | |
15851 | assert_eq!(r, e); | |
15852 | } | |
15853 | ||
15854 | #[simd_test(enable = "neon")] | |
15855 | unsafe fn test_vreinterpretq_f64_s32() { | |
15856 | let a: i32x4 = i32x4::new(0, 0, 0, 0); | |
15857 | let e: f64x2 = f64x2::new(0., 0.); | |
15858 | let r: f64x2 = transmute(vreinterpretq_f64_s32(transmute(a))); | |
15859 | assert_eq!(r, e); | |
15860 | } | |
15861 | ||
15862 | #[simd_test(enable = "neon")] | |
15863 | unsafe fn test_vreinterpretq_f64_s64() { | |
15864 | let a: i64x2 = i64x2::new(0, 0); | |
15865 | let e: f64x2 = f64x2::new(0., 0.); | |
15866 | let r: f64x2 = transmute(vreinterpretq_f64_s64(transmute(a))); | |
15867 | assert_eq!(r, e); | |
15868 | } | |
15869 | ||
15870 | #[simd_test(enable = "neon")] | |
15871 | unsafe fn test_vreinterpret_f64_p8() { | |
15872 | let a: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15873 | let e: f64 = 0.; | |
15874 | let r: f64 = transmute(vreinterpret_f64_p8(transmute(a))); | |
15875 | assert_eq!(r, e); | |
15876 | } | |
15877 | ||
15878 | #[simd_test(enable = "neon")] | |
15879 | unsafe fn test_vreinterpret_f64_u16() { | |
15880 | let a: u16x4 = u16x4::new(0, 0, 0, 0); | |
15881 | let e: f64 = 0.; | |
15882 | let r: f64 = transmute(vreinterpret_f64_u16(transmute(a))); | |
15883 | assert_eq!(r, e); | |
15884 | } | |
15885 | ||
15886 | #[simd_test(enable = "neon")] | |
15887 | unsafe fn test_vreinterpret_f64_u32() { | |
15888 | let a: u32x2 = u32x2::new(0, 0); | |
15889 | let e: f64 = 0.; | |
15890 | let r: f64 = transmute(vreinterpret_f64_u32(transmute(a))); | |
15891 | assert_eq!(r, e); | |
15892 | } | |
15893 | ||
15894 | #[simd_test(enable = "neon")] | |
15895 | unsafe fn test_vreinterpret_f64_u64() { | |
15896 | let a: u64x1 = u64x1::new(0); | |
15897 | let e: f64 = 0.; | |
15898 | let r: f64 = transmute(vreinterpret_f64_u64(transmute(a))); | |
15899 | assert_eq!(r, e); | |
15900 | } | |
15901 | ||
15902 | #[simd_test(enable = "neon")] | |
15903 | unsafe fn test_vreinterpretq_f64_p8() { | |
15904 | let a: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
15905 | let e: f64x2 = f64x2::new(0., 0.); | |
15906 | let r: f64x2 = transmute(vreinterpretq_f64_p8(transmute(a))); | |
15907 | assert_eq!(r, e); | |
15908 | } | |
15909 | ||
15910 | #[simd_test(enable = "neon")] | |
15911 | unsafe fn test_vreinterpretq_f64_u16() { | |
15912 | let a: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15913 | let e: f64x2 = f64x2::new(0., 0.); | |
15914 | let r: f64x2 = transmute(vreinterpretq_f64_u16(transmute(a))); | |
15915 | assert_eq!(r, e); | |
15916 | } | |
15917 | ||
15918 | #[simd_test(enable = "neon")] | |
15919 | unsafe fn test_vreinterpretq_f64_u32() { | |
15920 | let a: u32x4 = u32x4::new(0, 0, 0, 0); | |
15921 | let e: f64x2 = f64x2::new(0., 0.); | |
15922 | let r: f64x2 = transmute(vreinterpretq_f64_u32(transmute(a))); | |
15923 | assert_eq!(r, e); | |
15924 | } | |
15925 | ||
15926 | #[simd_test(enable = "neon")] | |
15927 | unsafe fn test_vreinterpretq_f64_u64() { | |
15928 | let a: u64x2 = u64x2::new(0, 0); | |
15929 | let e: f64x2 = f64x2::new(0., 0.); | |
15930 | let r: f64x2 = transmute(vreinterpretq_f64_u64(transmute(a))); | |
15931 | assert_eq!(r, e); | |
15932 | } | |
15933 | ||
15934 | #[simd_test(enable = "neon")] | |
15935 | unsafe fn test_vreinterpret_f64_u8() { | |
15936 | let a: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15937 | let e: f64 = 0.; | |
15938 | let r: f64 = transmute(vreinterpret_f64_u8(transmute(a))); | |
15939 | assert_eq!(r, e); | |
15940 | } | |
15941 | ||
15942 | #[simd_test(enable = "neon")] | |
15943 | unsafe fn test_vreinterpret_f64_p16() { | |
15944 | let a: i16x4 = i16x4::new(0, 0, 0, 0); | |
15945 | let e: f64 = 0.; | |
15946 | let r: f64 = transmute(vreinterpret_f64_p16(transmute(a))); | |
15947 | assert_eq!(r, e); | |
15948 | } | |
15949 | ||
15950 | #[simd_test(enable = "neon")] | |
15951 | unsafe fn test_vreinterpret_f64_p64() { | |
15952 | let a: i64x1 = i64x1::new(0); | |
15953 | let e: f64 = 0.; | |
15954 | let r: f64 = transmute(vreinterpret_f64_p64(transmute(a))); | |
15955 | assert_eq!(r, e); | |
15956 | } | |
15957 | ||
15958 | #[simd_test(enable = "neon")] | |
15959 | unsafe fn test_vreinterpret_f32_p64() { | |
15960 | let a: i64x1 = i64x1::new(0); | |
15961 | let e: f32x2 = f32x2::new(0., 0.); | |
15962 | let r: f32x2 = transmute(vreinterpret_f32_p64(transmute(a))); | |
15963 | assert_eq!(r, e); | |
15964 | } | |
15965 | ||
15966 | #[simd_test(enable = "neon")] | |
15967 | unsafe fn test_vreinterpretq_f64_u8() { | |
15968 | let a: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
15969 | let e: f64x2 = f64x2::new(0., 0.); | |
15970 | let r: f64x2 = transmute(vreinterpretq_f64_u8(transmute(a))); | |
15971 | assert_eq!(r, e); | |
15972 | } | |
15973 | ||
15974 | #[simd_test(enable = "neon")] | |
15975 | unsafe fn test_vreinterpretq_f64_p16() { | |
15976 | let a: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); | |
15977 | let e: f64x2 = f64x2::new(0., 0.); | |
15978 | let r: f64x2 = transmute(vreinterpretq_f64_p16(transmute(a))); | |
15979 | assert_eq!(r, e); | |
15980 | } | |
15981 | ||
15982 | #[simd_test(enable = "neon")] | |
15983 | unsafe fn test_vreinterpretq_f64_p64() { | |
15984 | let a: i64x2 = i64x2::new(0, 0); | |
15985 | let e: f64x2 = f64x2::new(0., 0.); | |
15986 | let r: f64x2 = transmute(vreinterpretq_f64_p64(transmute(a))); | |
15987 | assert_eq!(r, e); | |
15988 | } | |
15989 | ||
15990 | #[simd_test(enable = "neon")] | |
15991 | unsafe fn test_vreinterpretq_f32_p64() { | |
15992 | let a: i64x2 = i64x2::new(0, 0); | |
15993 | let e: f32x4 = f32x4::new(0., 0., 0., 0.); | |
15994 | let r: f32x4 = transmute(vreinterpretq_f32_p64(transmute(a))); | |
15995 | assert_eq!(r, e); | |
15996 | } | |
15997 | ||
15998 | #[simd_test(enable = "neon")] | |
15999 | unsafe fn test_vreinterpret_f64_f32() { | |
16000 | let a: f32x2 = f32x2::new(0., 0.); | |
16001 | let e: f64 = 0.; | |
16002 | let r: f64 = transmute(vreinterpret_f64_f32(transmute(a))); | |
16003 | assert_eq!(r, e); | |
16004 | } | |
16005 | ||
16006 | #[simd_test(enable = "neon")] | |
16007 | unsafe fn test_vreinterpret_f32_f64() { | |
16008 | let a: f64 = 0.; | |
16009 | let e: f32x2 = f32x2::new(0., 0.); | |
16010 | let r: f32x2 = transmute(vreinterpret_f32_f64(transmute(a))); | |
16011 | assert_eq!(r, e); | |
16012 | } | |
16013 | ||
16014 | #[simd_test(enable = "neon")] | |
16015 | unsafe fn test_vreinterpretq_f64_f32() { | |
16016 | let a: f32x4 = f32x4::new(0., 0., 0., 0.); | |
16017 | let e: f64x2 = f64x2::new(0., 0.); | |
16018 | let r: f64x2 = transmute(vreinterpretq_f64_f32(transmute(a))); | |
16019 | assert_eq!(r, e); | |
16020 | } | |
16021 | ||
16022 | #[simd_test(enable = "neon")] | |
16023 | unsafe fn test_vreinterpretq_f32_f64() { | |
16024 | let a: f64x2 = f64x2::new(0., 0.); | |
16025 | let e: f32x4 = f32x4::new(0., 0., 0., 0.); | |
16026 | let r: f32x4 = transmute(vreinterpretq_f32_f64(transmute(a))); | |
16027 | assert_eq!(r, e); | |
16028 | } | |
16029 | ||
16030 | #[simd_test(enable = "neon")] | |
16031 | unsafe fn test_vrshld_s64() { | |
16032 | let a: i64 = 1; | |
16033 | let b: i64 = 2; | |
16034 | let e: i64 = 4; | |
16035 | let r: i64 = transmute(vrshld_s64(transmute(a), transmute(b))); | |
16036 | assert_eq!(r, e); | |
16037 | } | |
16038 | ||
16039 | #[simd_test(enable = "neon")] | |
16040 | unsafe fn test_vrshld_u64() { | |
16041 | let a: u64 = 1; | |
16042 | let b: i64 = 2; | |
16043 | let e: u64 = 4; | |
16044 | let r: u64 = transmute(vrshld_u64(transmute(a), transmute(b))); | |
16045 | assert_eq!(r, e); | |
16046 | } | |
16047 | ||
16048 | #[simd_test(enable = "neon")] | |
16049 | unsafe fn test_vrshrd_n_s64() { | |
16050 | let a: i64 = 4; | |
16051 | let e: i64 = 1; | |
16052 | let r: i64 = transmute(vrshrd_n_s64::<2>(transmute(a))); | |
16053 | assert_eq!(r, e); | |
16054 | } | |
16055 | ||
16056 | #[simd_test(enable = "neon")] | |
16057 | unsafe fn test_vrshrd_n_u64() { | |
16058 | let a: u64 = 4; | |
16059 | let e: u64 = 1; | |
16060 | let r: u64 = transmute(vrshrd_n_u64::<2>(transmute(a))); | |
16061 | assert_eq!(r, e); | |
16062 | } | |
16063 | ||
16064 | #[simd_test(enable = "neon")] | |
16065 | unsafe fn test_vrshrn_high_n_s16() { | |
16066 | let a: i8x8 = i8x8::new(0, 1, 8, 9, 8, 9, 10, 11); | |
16067 | let b: i16x8 = i16x8::new(32, 36, 40, 44, 48, 52, 56, 60); | |
16068 | let e: i8x16 = i8x16::new(0, 1, 8, 9, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15); | |
16069 | let r: i8x16 = transmute(vrshrn_high_n_s16::<2>(transmute(a), transmute(b))); | |
16070 | assert_eq!(r, e); | |
16071 | } | |
16072 | ||
16073 | #[simd_test(enable = "neon")] | |
16074 | unsafe fn test_vrshrn_high_n_s32() { | |
16075 | let a: i16x4 = i16x4::new(0, 1, 8, 9); | |
16076 | let b: i32x4 = i32x4::new(32, 36, 40, 44); | |
16077 | let e: i16x8 = i16x8::new(0, 1, 8, 9, 8, 9, 10, 11); | |
16078 | let r: i16x8 = transmute(vrshrn_high_n_s32::<2>(transmute(a), transmute(b))); | |
16079 | assert_eq!(r, e); | |
16080 | } | |
16081 | ||
16082 | #[simd_test(enable = "neon")] | |
16083 | unsafe fn test_vrshrn_high_n_s64() { | |
16084 | let a: i32x2 = i32x2::new(0, 1); | |
16085 | let b: i64x2 = i64x2::new(32, 36); | |
16086 | let e: i32x4 = i32x4::new(0, 1, 8, 9); | |
16087 | let r: i32x4 = transmute(vrshrn_high_n_s64::<2>(transmute(a), transmute(b))); | |
16088 | assert_eq!(r, e); | |
16089 | } | |
16090 | ||
16091 | #[simd_test(enable = "neon")] | |
16092 | unsafe fn test_vrshrn_high_n_u16() { | |
16093 | let a: u8x8 = u8x8::new(0, 1, 8, 9, 8, 9, 10, 11); | |
16094 | let b: u16x8 = u16x8::new(32, 36, 40, 44, 48, 52, 56, 60); | |
16095 | let e: u8x16 = u8x16::new(0, 1, 8, 9, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15); | |
16096 | let r: u8x16 = transmute(vrshrn_high_n_u16::<2>(transmute(a), transmute(b))); | |
16097 | assert_eq!(r, e); | |
16098 | } | |
16099 | ||
16100 | #[simd_test(enable = "neon")] | |
16101 | unsafe fn test_vrshrn_high_n_u32() { | |
16102 | let a: u16x4 = u16x4::new(0, 1, 8, 9); | |
16103 | let b: u32x4 = u32x4::new(32, 36, 40, 44); | |
16104 | let e: u16x8 = u16x8::new(0, 1, 8, 9, 8, 9, 10, 11); | |
16105 | let r: u16x8 = transmute(vrshrn_high_n_u32::<2>(transmute(a), transmute(b))); | |
16106 | assert_eq!(r, e); | |
16107 | } | |
16108 | ||
16109 | #[simd_test(enable = "neon")] | |
16110 | unsafe fn test_vrshrn_high_n_u64() { | |
16111 | let a: u32x2 = u32x2::new(0, 1); | |
16112 | let b: u64x2 = u64x2::new(32, 36); | |
16113 | let e: u32x4 = u32x4::new(0, 1, 8, 9); | |
16114 | let r: u32x4 = transmute(vrshrn_high_n_u64::<2>(transmute(a), transmute(b))); | |
16115 | assert_eq!(r, e); | |
16116 | } | |
16117 | ||
16118 | #[simd_test(enable = "neon")] | |
16119 | unsafe fn test_vrsrad_n_s64() { | |
16120 | let a: i64 = 1; | |
16121 | let b: i64 = 4; | |
16122 | let e: i64 = 2; | |
16123 | let r: i64 = transmute(vrsrad_n_s64::<2>(transmute(a), transmute(b))); | |
16124 | assert_eq!(r, e); | |
16125 | } | |
16126 | ||
16127 | #[simd_test(enable = "neon")] | |
16128 | unsafe fn test_vrsrad_n_u64() { | |
16129 | let a: u64 = 1; | |
16130 | let b: u64 = 4; | |
16131 | let e: u64 = 2; | |
16132 | let r: u64 = transmute(vrsrad_n_u64::<2>(transmute(a), transmute(b))); | |
16133 | assert_eq!(r, e); | |
16134 | } | |
16135 | ||
16136 | #[simd_test(enable = "neon")] | |
16137 | unsafe fn test_vset_lane_f64() { | |
16138 | let a: f64 = 1.; | |
16139 | let b: f64 = 0.; | |
16140 | let e: f64 = 1.; | |
16141 | let r: f64 = transmute(vset_lane_f64::<0>(transmute(a), transmute(b))); | |
16142 | assert_eq!(r, e); | |
16143 | } | |
16144 | ||
16145 | #[simd_test(enable = "neon")] | |
16146 | unsafe fn test_vsetq_lane_f64() { | |
16147 | let a: f64 = 1.; | |
16148 | let b: f64x2 = f64x2::new(0., 2.); | |
16149 | let e: f64x2 = f64x2::new(1., 2.); | |
16150 | let r: f64x2 = transmute(vsetq_lane_f64::<0>(transmute(a), transmute(b))); | |
16151 | assert_eq!(r, e); | |
16152 | } | |
16153 | ||
16154 | #[simd_test(enable = "neon")] | |
16155 | unsafe fn test_vshld_s64() { | |
16156 | let a: i64 = 1; | |
16157 | let b: i64 = 2; | |
16158 | let e: i64 = 4; | |
16159 | let r: i64 = transmute(vshld_s64(transmute(a), transmute(b))); | |
16160 | assert_eq!(r, e); | |
16161 | } | |
16162 | ||
16163 | #[simd_test(enable = "neon")] | |
16164 | unsafe fn test_vshld_u64() { | |
16165 | let a: u64 = 1; | |
16166 | let b: i64 = 2; | |
16167 | let e: u64 = 4; | |
16168 | let r: u64 = transmute(vshld_u64(transmute(a), transmute(b))); | |
16169 | assert_eq!(r, e); | |
16170 | } | |
16171 | ||
16172 | #[simd_test(enable = "neon")] | |
16173 | unsafe fn test_vshll_high_n_s8() { | |
16174 | let a: i8x16 = i8x16::new(0, 0, 1, 2, 1, 2, 3, 4, 1, 2, 3, 4, 5, 6, 7, 8); | |
16175 | let e: i16x8 = i16x8::new(4, 8, 12, 16, 20, 24, 28, 32); | |
16176 | let r: i16x8 = transmute(vshll_high_n_s8::<2>(transmute(a))); | |
16177 | assert_eq!(r, e); | |
16178 | } | |
16179 | ||
16180 | #[simd_test(enable = "neon")] | |
16181 | unsafe fn test_vshll_high_n_s16() { | |
16182 | let a: i16x8 = i16x8::new(0, 0, 1, 2, 1, 2, 3, 4); | |
16183 | let e: i32x4 = i32x4::new(4, 8, 12, 16); | |
16184 | let r: i32x4 = transmute(vshll_high_n_s16::<2>(transmute(a))); | |
16185 | assert_eq!(r, e); | |
16186 | } | |
16187 | ||
16188 | #[simd_test(enable = "neon")] | |
16189 | unsafe fn test_vshll_high_n_s32() { | |
16190 | let a: i32x4 = i32x4::new(0, 0, 1, 2); | |
16191 | let e: i64x2 = i64x2::new(4, 8); | |
16192 | let r: i64x2 = transmute(vshll_high_n_s32::<2>(transmute(a))); | |
16193 | assert_eq!(r, e); | |
16194 | } | |
16195 | ||
16196 | #[simd_test(enable = "neon")] | |
16197 | unsafe fn test_vshll_high_n_u8() { | |
16198 | let a: u8x16 = u8x16::new(0, 0, 1, 2, 1, 2, 3, 4, 1, 2, 3, 4, 5, 6, 7, 8); | |
16199 | let e: u16x8 = u16x8::new(4, 8, 12, 16, 20, 24, 28, 32); | |
16200 | let r: u16x8 = transmute(vshll_high_n_u8::<2>(transmute(a))); | |
16201 | assert_eq!(r, e); | |
16202 | } | |
16203 | ||
16204 | #[simd_test(enable = "neon")] | |
16205 | unsafe fn test_vshll_high_n_u16() { | |
16206 | let a: u16x8 = u16x8::new(0, 0, 1, 2, 1, 2, 3, 4); | |
16207 | let e: u32x4 = u32x4::new(4, 8, 12, 16); | |
16208 | let r: u32x4 = transmute(vshll_high_n_u16::<2>(transmute(a))); | |
16209 | assert_eq!(r, e); | |
16210 | } | |
16211 | ||
16212 | #[simd_test(enable = "neon")] | |
16213 | unsafe fn test_vshll_high_n_u32() { | |
16214 | let a: u32x4 = u32x4::new(0, 0, 1, 2); | |
16215 | let e: u64x2 = u64x2::new(4, 8); | |
16216 | let r: u64x2 = transmute(vshll_high_n_u32::<2>(transmute(a))); | |
16217 | assert_eq!(r, e); | |
16218 | } | |
16219 | ||
16220 | #[simd_test(enable = "neon")] | |
16221 | unsafe fn test_vshrn_high_n_s16() { | |
16222 | let a: i8x8 = i8x8::new(1, 2, 5, 6, 5, 6, 7, 8); | |
16223 | let b: i16x8 = i16x8::new(20, 24, 28, 32, 52, 56, 60, 64); | |
16224 | let e: i8x16 = i8x16::new(1, 2, 5, 6, 5, 6, 7, 8, 5, 6, 7, 8, 13, 14, 15, 16); | |
16225 | let r: i8x16 = transmute(vshrn_high_n_s16::<2>(transmute(a), transmute(b))); | |
16226 | assert_eq!(r, e); | |
16227 | } | |
16228 | ||
16229 | #[simd_test(enable = "neon")] | |
16230 | unsafe fn test_vshrn_high_n_s32() { | |
16231 | let a: i16x4 = i16x4::new(1, 2, 5, 6); | |
16232 | let b: i32x4 = i32x4::new(20, 24, 28, 32); | |
16233 | let e: i16x8 = i16x8::new(1, 2, 5, 6, 5, 6, 7, 8); | |
16234 | let r: i16x8 = transmute(vshrn_high_n_s32::<2>(transmute(a), transmute(b))); | |
16235 | assert_eq!(r, e); | |
16236 | } | |
16237 | ||
16238 | #[simd_test(enable = "neon")] | |
16239 | unsafe fn test_vshrn_high_n_s64() { | |
16240 | let a: i32x2 = i32x2::new(1, 2); | |
16241 | let b: i64x2 = i64x2::new(20, 24); | |
16242 | let e: i32x4 = i32x4::new(1, 2, 5, 6); | |
16243 | let r: i32x4 = transmute(vshrn_high_n_s64::<2>(transmute(a), transmute(b))); | |
16244 | assert_eq!(r, e); | |
16245 | } | |
16246 | ||
16247 | #[simd_test(enable = "neon")] | |
16248 | unsafe fn test_vshrn_high_n_u16() { | |
16249 | let a: u8x8 = u8x8::new(1, 2, 5, 6, 5, 6, 7, 8); | |
16250 | let b: u16x8 = u16x8::new(20, 24, 28, 32, 52, 56, 60, 64); | |
16251 | let e: u8x16 = u8x16::new(1, 2, 5, 6, 5, 6, 7, 8, 5, 6, 7, 8, 13, 14, 15, 16); | |
16252 | let r: u8x16 = transmute(vshrn_high_n_u16::<2>(transmute(a), transmute(b))); | |
16253 | assert_eq!(r, e); | |
16254 | } | |
16255 | ||
16256 | #[simd_test(enable = "neon")] | |
16257 | unsafe fn test_vshrn_high_n_u32() { | |
16258 | let a: u16x4 = u16x4::new(1, 2, 5, 6); | |
16259 | let b: u32x4 = u32x4::new(20, 24, 28, 32); | |
16260 | let e: u16x8 = u16x8::new(1, 2, 5, 6, 5, 6, 7, 8); | |
16261 | let r: u16x8 = transmute(vshrn_high_n_u32::<2>(transmute(a), transmute(b))); | |
16262 | assert_eq!(r, e); | |
16263 | } | |
16264 | ||
16265 | #[simd_test(enable = "neon")] | |
16266 | unsafe fn test_vshrn_high_n_u64() { | |
16267 | let a: u32x2 = u32x2::new(1, 2); | |
16268 | let b: u64x2 = u64x2::new(20, 24); | |
16269 | let e: u32x4 = u32x4::new(1, 2, 5, 6); | |
16270 | let r: u32x4 = transmute(vshrn_high_n_u64::<2>(transmute(a), transmute(b))); | |
16271 | assert_eq!(r, e); | |
16272 | } | |
16273 | ||
16274 | #[simd_test(enable = "neon")] | |
16275 | unsafe fn test_vtrn1_s8() { | |
16276 | let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16277 | let b: i8x8 = i8x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16278 | let e: i8x8 = i8x8::new(0, 1, 4, 5, 8, 9, 12, 13); | |
16279 | let r: i8x8 = transmute(vtrn1_s8(transmute(a), transmute(b))); | |
16280 | assert_eq!(r, e); | |
16281 | } | |
16282 | ||
16283 | #[simd_test(enable = "neon")] | |
16284 | unsafe fn test_vtrn1q_s8() { | |
16285 | let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
16286 | let b: i8x16 = i8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); | |
16287 | let e: i8x16 = i8x16::new(0, 1, 4, 5, 8, 9, 12, 13, 16, 17, 20, 21, 24, 25, 28, 29); | |
16288 | let r: i8x16 = transmute(vtrn1q_s8(transmute(a), transmute(b))); | |
16289 | assert_eq!(r, e); | |
16290 | } | |
16291 | ||
16292 | #[simd_test(enable = "neon")] | |
16293 | unsafe fn test_vtrn1_s16() { | |
16294 | let a: i16x4 = i16x4::new(0, 2, 4, 6); | |
16295 | let b: i16x4 = i16x4::new(1, 3, 5, 7); | |
16296 | let e: i16x4 = i16x4::new(0, 1, 4, 5); | |
16297 | let r: i16x4 = transmute(vtrn1_s16(transmute(a), transmute(b))); | |
16298 | assert_eq!(r, e); | |
16299 | } | |
16300 | ||
16301 | #[simd_test(enable = "neon")] | |
16302 | unsafe fn test_vtrn1q_s16() { | |
16303 | let a: i16x8 = i16x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16304 | let b: i16x8 = i16x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16305 | let e: i16x8 = i16x8::new(0, 1, 4, 5, 8, 9, 12, 13); | |
16306 | let r: i16x8 = transmute(vtrn1q_s16(transmute(a), transmute(b))); | |
16307 | assert_eq!(r, e); | |
16308 | } | |
16309 | ||
16310 | #[simd_test(enable = "neon")] | |
16311 | unsafe fn test_vtrn1q_s32() { | |
16312 | let a: i32x4 = i32x4::new(0, 2, 4, 6); | |
16313 | let b: i32x4 = i32x4::new(1, 3, 5, 7); | |
16314 | let e: i32x4 = i32x4::new(0, 1, 4, 5); | |
16315 | let r: i32x4 = transmute(vtrn1q_s32(transmute(a), transmute(b))); | |
16316 | assert_eq!(r, e); | |
16317 | } | |
16318 | ||
16319 | #[simd_test(enable = "neon")] | |
16320 | unsafe fn test_vtrn1_u8() { | |
16321 | let a: u8x8 = u8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16322 | let b: u8x8 = u8x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16323 | let e: u8x8 = u8x8::new(0, 1, 4, 5, 8, 9, 12, 13); | |
16324 | let r: u8x8 = transmute(vtrn1_u8(transmute(a), transmute(b))); | |
16325 | assert_eq!(r, e); | |
16326 | } | |
16327 | ||
16328 | #[simd_test(enable = "neon")] | |
16329 | unsafe fn test_vtrn1q_u8() { | |
16330 | let a: u8x16 = u8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
16331 | let b: u8x16 = u8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); | |
16332 | let e: u8x16 = u8x16::new(0, 1, 4, 5, 8, 9, 12, 13, 16, 17, 20, 21, 24, 25, 28, 29); | |
16333 | let r: u8x16 = transmute(vtrn1q_u8(transmute(a), transmute(b))); | |
16334 | assert_eq!(r, e); | |
16335 | } | |
16336 | ||
16337 | #[simd_test(enable = "neon")] | |
16338 | unsafe fn test_vtrn1_u16() { | |
16339 | let a: u16x4 = u16x4::new(0, 2, 4, 6); | |
16340 | let b: u16x4 = u16x4::new(1, 3, 5, 7); | |
16341 | let e: u16x4 = u16x4::new(0, 1, 4, 5); | |
16342 | let r: u16x4 = transmute(vtrn1_u16(transmute(a), transmute(b))); | |
16343 | assert_eq!(r, e); | |
16344 | } | |
16345 | ||
16346 | #[simd_test(enable = "neon")] | |
16347 | unsafe fn test_vtrn1q_u16() { | |
16348 | let a: u16x8 = u16x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16349 | let b: u16x8 = u16x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16350 | let e: u16x8 = u16x8::new(0, 1, 4, 5, 8, 9, 12, 13); | |
16351 | let r: u16x8 = transmute(vtrn1q_u16(transmute(a), transmute(b))); | |
16352 | assert_eq!(r, e); | |
16353 | } | |
16354 | ||
16355 | #[simd_test(enable = "neon")] | |
16356 | unsafe fn test_vtrn1q_u32() { | |
16357 | let a: u32x4 = u32x4::new(0, 2, 4, 6); | |
16358 | let b: u32x4 = u32x4::new(1, 3, 5, 7); | |
16359 | let e: u32x4 = u32x4::new(0, 1, 4, 5); | |
16360 | let r: u32x4 = transmute(vtrn1q_u32(transmute(a), transmute(b))); | |
16361 | assert_eq!(r, e); | |
16362 | } | |
16363 | ||
16364 | #[simd_test(enable = "neon")] | |
16365 | unsafe fn test_vtrn1_p8() { | |
16366 | let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16367 | let b: i8x8 = i8x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16368 | let e: i8x8 = i8x8::new(0, 1, 4, 5, 8, 9, 12, 13); | |
16369 | let r: i8x8 = transmute(vtrn1_p8(transmute(a), transmute(b))); | |
16370 | assert_eq!(r, e); | |
16371 | } | |
16372 | ||
16373 | #[simd_test(enable = "neon")] | |
16374 | unsafe fn test_vtrn1q_p8() { | |
16375 | let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
16376 | let b: i8x16 = i8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); | |
16377 | let e: i8x16 = i8x16::new(0, 1, 4, 5, 8, 9, 12, 13, 16, 17, 20, 21, 24, 25, 28, 29); | |
16378 | let r: i8x16 = transmute(vtrn1q_p8(transmute(a), transmute(b))); | |
16379 | assert_eq!(r, e); | |
16380 | } | |
16381 | ||
16382 | #[simd_test(enable = "neon")] | |
16383 | unsafe fn test_vtrn1_p16() { | |
16384 | let a: i16x4 = i16x4::new(0, 2, 4, 6); | |
16385 | let b: i16x4 = i16x4::new(1, 3, 5, 7); | |
16386 | let e: i16x4 = i16x4::new(0, 1, 4, 5); | |
16387 | let r: i16x4 = transmute(vtrn1_p16(transmute(a), transmute(b))); | |
16388 | assert_eq!(r, e); | |
16389 | } | |
16390 | ||
16391 | #[simd_test(enable = "neon")] | |
16392 | unsafe fn test_vtrn1q_p16() { | |
16393 | let a: i16x8 = i16x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16394 | let b: i16x8 = i16x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16395 | let e: i16x8 = i16x8::new(0, 1, 4, 5, 8, 9, 12, 13); | |
16396 | let r: i16x8 = transmute(vtrn1q_p16(transmute(a), transmute(b))); | |
16397 | assert_eq!(r, e); | |
16398 | } | |
16399 | ||
16400 | #[simd_test(enable = "neon")] | |
16401 | unsafe fn test_vtrn1_s32() { | |
16402 | let a: i32x2 = i32x2::new(0, 2); | |
16403 | let b: i32x2 = i32x2::new(1, 3); | |
16404 | let e: i32x2 = i32x2::new(0, 1); | |
16405 | let r: i32x2 = transmute(vtrn1_s32(transmute(a), transmute(b))); | |
16406 | assert_eq!(r, e); | |
16407 | } | |
16408 | ||
16409 | #[simd_test(enable = "neon")] | |
16410 | unsafe fn test_vtrn1q_s64() { | |
16411 | let a: i64x2 = i64x2::new(0, 2); | |
16412 | let b: i64x2 = i64x2::new(1, 3); | |
16413 | let e: i64x2 = i64x2::new(0, 1); | |
16414 | let r: i64x2 = transmute(vtrn1q_s64(transmute(a), transmute(b))); | |
16415 | assert_eq!(r, e); | |
16416 | } | |
16417 | ||
16418 | #[simd_test(enable = "neon")] | |
16419 | unsafe fn test_vtrn1_u32() { | |
16420 | let a: u32x2 = u32x2::new(0, 2); | |
16421 | let b: u32x2 = u32x2::new(1, 3); | |
16422 | let e: u32x2 = u32x2::new(0, 1); | |
16423 | let r: u32x2 = transmute(vtrn1_u32(transmute(a), transmute(b))); | |
16424 | assert_eq!(r, e); | |
16425 | } | |
16426 | ||
16427 | #[simd_test(enable = "neon")] | |
16428 | unsafe fn test_vtrn1q_u64() { | |
16429 | let a: u64x2 = u64x2::new(0, 2); | |
16430 | let b: u64x2 = u64x2::new(1, 3); | |
16431 | let e: u64x2 = u64x2::new(0, 1); | |
16432 | let r: u64x2 = transmute(vtrn1q_u64(transmute(a), transmute(b))); | |
16433 | assert_eq!(r, e); | |
16434 | } | |
16435 | ||
16436 | #[simd_test(enable = "neon")] | |
16437 | unsafe fn test_vtrn1q_p64() { | |
16438 | let a: i64x2 = i64x2::new(0, 2); | |
16439 | let b: i64x2 = i64x2::new(1, 3); | |
16440 | let e: i64x2 = i64x2::new(0, 1); | |
16441 | let r: i64x2 = transmute(vtrn1q_p64(transmute(a), transmute(b))); | |
16442 | assert_eq!(r, e); | |
16443 | } | |
16444 | ||
16445 | #[simd_test(enable = "neon")] | |
16446 | unsafe fn test_vtrn1q_f32() { | |
16447 | let a: f32x4 = f32x4::new(0., 2., 4., 6.); | |
16448 | let b: f32x4 = f32x4::new(1., 3., 5., 7.); | |
16449 | let e: f32x4 = f32x4::new(0., 1., 4., 5.); | |
16450 | let r: f32x4 = transmute(vtrn1q_f32(transmute(a), transmute(b))); | |
16451 | assert_eq!(r, e); | |
16452 | } | |
16453 | ||
16454 | #[simd_test(enable = "neon")] | |
16455 | unsafe fn test_vtrn1_f32() { | |
16456 | let a: f32x2 = f32x2::new(0., 2.); | |
16457 | let b: f32x2 = f32x2::new(1., 3.); | |
16458 | let e: f32x2 = f32x2::new(0., 1.); | |
16459 | let r: f32x2 = transmute(vtrn1_f32(transmute(a), transmute(b))); | |
16460 | assert_eq!(r, e); | |
16461 | } | |
16462 | ||
16463 | #[simd_test(enable = "neon")] | |
16464 | unsafe fn test_vtrn1q_f64() { | |
16465 | let a: f64x2 = f64x2::new(0., 2.); | |
16466 | let b: f64x2 = f64x2::new(1., 3.); | |
16467 | let e: f64x2 = f64x2::new(0., 1.); | |
16468 | let r: f64x2 = transmute(vtrn1q_f64(transmute(a), transmute(b))); | |
16469 | assert_eq!(r, e); | |
16470 | } | |
16471 | ||
16472 | #[simd_test(enable = "neon")] | |
16473 | unsafe fn test_vtrn2_s8() { | |
16474 | let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16475 | let b: i8x8 = i8x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16476 | let e: i8x8 = i8x8::new(2, 3, 6, 7, 10, 11, 14, 15); | |
16477 | let r: i8x8 = transmute(vtrn2_s8(transmute(a), transmute(b))); | |
16478 | assert_eq!(r, e); | |
16479 | } | |
16480 | ||
16481 | #[simd_test(enable = "neon")] | |
16482 | unsafe fn test_vtrn2q_s8() { | |
16483 | let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
16484 | let b: i8x16 = i8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); | |
16485 | let e: i8x16 = i8x16::new(2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31); | |
16486 | let r: i8x16 = transmute(vtrn2q_s8(transmute(a), transmute(b))); | |
16487 | assert_eq!(r, e); | |
16488 | } | |
16489 | ||
16490 | #[simd_test(enable = "neon")] | |
16491 | unsafe fn test_vtrn2_s16() { | |
16492 | let a: i16x4 = i16x4::new(0, 2, 4, 6); | |
16493 | let b: i16x4 = i16x4::new(1, 3, 5, 7); | |
16494 | let e: i16x4 = i16x4::new(2, 3, 6, 7); | |
16495 | let r: i16x4 = transmute(vtrn2_s16(transmute(a), transmute(b))); | |
16496 | assert_eq!(r, e); | |
16497 | } | |
16498 | ||
16499 | #[simd_test(enable = "neon")] | |
16500 | unsafe fn test_vtrn2q_s16() { | |
16501 | let a: i16x8 = i16x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16502 | let b: i16x8 = i16x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16503 | let e: i16x8 = i16x8::new(2, 3, 6, 7, 10, 11, 14, 15); | |
16504 | let r: i16x8 = transmute(vtrn2q_s16(transmute(a), transmute(b))); | |
16505 | assert_eq!(r, e); | |
16506 | } | |
16507 | ||
16508 | #[simd_test(enable = "neon")] | |
16509 | unsafe fn test_vtrn2q_s32() { | |
16510 | let a: i32x4 = i32x4::new(0, 2, 4, 6); | |
16511 | let b: i32x4 = i32x4::new(1, 3, 5, 7); | |
16512 | let e: i32x4 = i32x4::new(2, 3, 6, 7); | |
16513 | let r: i32x4 = transmute(vtrn2q_s32(transmute(a), transmute(b))); | |
16514 | assert_eq!(r, e); | |
16515 | } | |
16516 | ||
16517 | #[simd_test(enable = "neon")] | |
16518 | unsafe fn test_vtrn2_u8() { | |
16519 | let a: u8x8 = u8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16520 | let b: u8x8 = u8x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16521 | let e: u8x8 = u8x8::new(2, 3, 6, 7, 10, 11, 14, 15); | |
16522 | let r: u8x8 = transmute(vtrn2_u8(transmute(a), transmute(b))); | |
16523 | assert_eq!(r, e); | |
16524 | } | |
16525 | ||
16526 | #[simd_test(enable = "neon")] | |
16527 | unsafe fn test_vtrn2q_u8() { | |
16528 | let a: u8x16 = u8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
16529 | let b: u8x16 = u8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); | |
16530 | let e: u8x16 = u8x16::new(2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31); | |
16531 | let r: u8x16 = transmute(vtrn2q_u8(transmute(a), transmute(b))); | |
16532 | assert_eq!(r, e); | |
16533 | } | |
16534 | ||
16535 | #[simd_test(enable = "neon")] | |
16536 | unsafe fn test_vtrn2_u16() { | |
16537 | let a: u16x4 = u16x4::new(0, 2, 4, 6); | |
16538 | let b: u16x4 = u16x4::new(1, 3, 5, 7); | |
16539 | let e: u16x4 = u16x4::new(2, 3, 6, 7); | |
16540 | let r: u16x4 = transmute(vtrn2_u16(transmute(a), transmute(b))); | |
16541 | assert_eq!(r, e); | |
16542 | } | |
16543 | ||
16544 | #[simd_test(enable = "neon")] | |
16545 | unsafe fn test_vtrn2q_u16() { | |
16546 | let a: u16x8 = u16x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16547 | let b: u16x8 = u16x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16548 | let e: u16x8 = u16x8::new(2, 3, 6, 7, 10, 11, 14, 15); | |
16549 | let r: u16x8 = transmute(vtrn2q_u16(transmute(a), transmute(b))); | |
16550 | assert_eq!(r, e); | |
16551 | } | |
16552 | ||
16553 | #[simd_test(enable = "neon")] | |
16554 | unsafe fn test_vtrn2q_u32() { | |
16555 | let a: u32x4 = u32x4::new(0, 2, 4, 6); | |
16556 | let b: u32x4 = u32x4::new(1, 3, 5, 7); | |
16557 | let e: u32x4 = u32x4::new(2, 3, 6, 7); | |
16558 | let r: u32x4 = transmute(vtrn2q_u32(transmute(a), transmute(b))); | |
16559 | assert_eq!(r, e); | |
16560 | } | |
16561 | ||
16562 | #[simd_test(enable = "neon")] | |
16563 | unsafe fn test_vtrn2_p8() { | |
16564 | let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16565 | let b: i8x8 = i8x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16566 | let e: i8x8 = i8x8::new(2, 3, 6, 7, 10, 11, 14, 15); | |
16567 | let r: i8x8 = transmute(vtrn2_p8(transmute(a), transmute(b))); | |
16568 | assert_eq!(r, e); | |
16569 | } | |
16570 | ||
16571 | #[simd_test(enable = "neon")] | |
16572 | unsafe fn test_vtrn2q_p8() { | |
16573 | let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
16574 | let b: i8x16 = i8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); | |
16575 | let e: i8x16 = i8x16::new(2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31); | |
16576 | let r: i8x16 = transmute(vtrn2q_p8(transmute(a), transmute(b))); | |
16577 | assert_eq!(r, e); | |
16578 | } | |
16579 | ||
16580 | #[simd_test(enable = "neon")] | |
16581 | unsafe fn test_vtrn2_p16() { | |
16582 | let a: i16x4 = i16x4::new(0, 2, 4, 6); | |
16583 | let b: i16x4 = i16x4::new(1, 3, 5, 7); | |
16584 | let e: i16x4 = i16x4::new(2, 3, 6, 7); | |
16585 | let r: i16x4 = transmute(vtrn2_p16(transmute(a), transmute(b))); | |
16586 | assert_eq!(r, e); | |
16587 | } | |
16588 | ||
16589 | #[simd_test(enable = "neon")] | |
16590 | unsafe fn test_vtrn2q_p16() { | |
16591 | let a: i16x8 = i16x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16592 | let b: i16x8 = i16x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16593 | let e: i16x8 = i16x8::new(2, 3, 6, 7, 10, 11, 14, 15); | |
16594 | let r: i16x8 = transmute(vtrn2q_p16(transmute(a), transmute(b))); | |
16595 | assert_eq!(r, e); | |
16596 | } | |
16597 | ||
16598 | #[simd_test(enable = "neon")] | |
16599 | unsafe fn test_vtrn2_s32() { | |
16600 | let a: i32x2 = i32x2::new(0, 2); | |
16601 | let b: i32x2 = i32x2::new(1, 3); | |
16602 | let e: i32x2 = i32x2::new(2, 3); | |
16603 | let r: i32x2 = transmute(vtrn2_s32(transmute(a), transmute(b))); | |
16604 | assert_eq!(r, e); | |
16605 | } | |
16606 | ||
16607 | #[simd_test(enable = "neon")] | |
16608 | unsafe fn test_vtrn2q_s64() { | |
16609 | let a: i64x2 = i64x2::new(0, 2); | |
16610 | let b: i64x2 = i64x2::new(1, 3); | |
16611 | let e: i64x2 = i64x2::new(2, 3); | |
16612 | let r: i64x2 = transmute(vtrn2q_s64(transmute(a), transmute(b))); | |
16613 | assert_eq!(r, e); | |
16614 | } | |
16615 | ||
16616 | #[simd_test(enable = "neon")] | |
16617 | unsafe fn test_vtrn2_u32() { | |
16618 | let a: u32x2 = u32x2::new(0, 2); | |
16619 | let b: u32x2 = u32x2::new(1, 3); | |
16620 | let e: u32x2 = u32x2::new(2, 3); | |
16621 | let r: u32x2 = transmute(vtrn2_u32(transmute(a), transmute(b))); | |
16622 | assert_eq!(r, e); | |
16623 | } | |
16624 | ||
16625 | #[simd_test(enable = "neon")] | |
16626 | unsafe fn test_vtrn2q_u64() { | |
16627 | let a: u64x2 = u64x2::new(0, 2); | |
16628 | let b: u64x2 = u64x2::new(1, 3); | |
16629 | let e: u64x2 = u64x2::new(2, 3); | |
16630 | let r: u64x2 = transmute(vtrn2q_u64(transmute(a), transmute(b))); | |
16631 | assert_eq!(r, e); | |
16632 | } | |
16633 | ||
16634 | #[simd_test(enable = "neon")] | |
16635 | unsafe fn test_vtrn2q_p64() { | |
16636 | let a: i64x2 = i64x2::new(0, 2); | |
16637 | let b: i64x2 = i64x2::new(1, 3); | |
16638 | let e: i64x2 = i64x2::new(2, 3); | |
16639 | let r: i64x2 = transmute(vtrn2q_p64(transmute(a), transmute(b))); | |
16640 | assert_eq!(r, e); | |
16641 | } | |
16642 | ||
16643 | #[simd_test(enable = "neon")] | |
16644 | unsafe fn test_vtrn2q_f32() { | |
16645 | let a: f32x4 = f32x4::new(0., 2., 4., 6.); | |
16646 | let b: f32x4 = f32x4::new(1., 3., 5., 7.); | |
16647 | let e: f32x4 = f32x4::new(2., 3., 6., 7.); | |
16648 | let r: f32x4 = transmute(vtrn2q_f32(transmute(a), transmute(b))); | |
16649 | assert_eq!(r, e); | |
16650 | } | |
16651 | ||
16652 | #[simd_test(enable = "neon")] | |
16653 | unsafe fn test_vtrn2_f32() { | |
16654 | let a: f32x2 = f32x2::new(0., 2.); | |
16655 | let b: f32x2 = f32x2::new(1., 3.); | |
16656 | let e: f32x2 = f32x2::new(2., 3.); | |
16657 | let r: f32x2 = transmute(vtrn2_f32(transmute(a), transmute(b))); | |
16658 | assert_eq!(r, e); | |
16659 | } | |
16660 | ||
16661 | #[simd_test(enable = "neon")] | |
16662 | unsafe fn test_vtrn2q_f64() { | |
16663 | let a: f64x2 = f64x2::new(0., 2.); | |
16664 | let b: f64x2 = f64x2::new(1., 3.); | |
16665 | let e: f64x2 = f64x2::new(2., 3.); | |
16666 | let r: f64x2 = transmute(vtrn2q_f64(transmute(a), transmute(b))); | |
16667 | assert_eq!(r, e); | |
16668 | } | |
16669 | ||
16670 | #[simd_test(enable = "neon")] | |
16671 | unsafe fn test_vzip1_s8() { | |
16672 | let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16673 | let b: i8x8 = i8x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16674 | let e: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); | |
16675 | let r: i8x8 = transmute(vzip1_s8(transmute(a), transmute(b))); | |
16676 | assert_eq!(r, e); | |
16677 | } | |
16678 | ||
16679 | #[simd_test(enable = "neon")] | |
16680 | unsafe fn test_vzip1q_s8() { | |
16681 | let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
16682 | let b: i8x16 = i8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); | |
16683 | let e: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); | |
16684 | let r: i8x16 = transmute(vzip1q_s8(transmute(a), transmute(b))); | |
16685 | assert_eq!(r, e); | |
16686 | } | |
16687 | ||
16688 | #[simd_test(enable = "neon")] | |
16689 | unsafe fn test_vzip1_s16() { | |
16690 | let a: i16x4 = i16x4::new(0, 2, 4, 6); | |
16691 | let b: i16x4 = i16x4::new(1, 3, 5, 7); | |
16692 | let e: i16x4 = i16x4::new(0, 1, 2, 3); | |
16693 | let r: i16x4 = transmute(vzip1_s16(transmute(a), transmute(b))); | |
16694 | assert_eq!(r, e); | |
16695 | } | |
16696 | ||
16697 | #[simd_test(enable = "neon")] | |
16698 | unsafe fn test_vzip1q_s16() { | |
16699 | let a: i16x8 = i16x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16700 | let b: i16x8 = i16x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16701 | let e: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); | |
16702 | let r: i16x8 = transmute(vzip1q_s16(transmute(a), transmute(b))); | |
16703 | assert_eq!(r, e); | |
16704 | } | |
16705 | ||
16706 | #[simd_test(enable = "neon")] | |
16707 | unsafe fn test_vzip1_s32() { | |
16708 | let a: i32x2 = i32x2::new(0, 2); | |
16709 | let b: i32x2 = i32x2::new(1, 3); | |
16710 | let e: i32x2 = i32x2::new(0, 1); | |
16711 | let r: i32x2 = transmute(vzip1_s32(transmute(a), transmute(b))); | |
16712 | assert_eq!(r, e); | |
16713 | } | |
16714 | ||
16715 | #[simd_test(enable = "neon")] | |
16716 | unsafe fn test_vzip1q_s32() { | |
16717 | let a: i32x4 = i32x4::new(0, 2, 4, 6); | |
16718 | let b: i32x4 = i32x4::new(1, 3, 5, 7); | |
16719 | let e: i32x4 = i32x4::new(0, 1, 2, 3); | |
16720 | let r: i32x4 = transmute(vzip1q_s32(transmute(a), transmute(b))); | |
16721 | assert_eq!(r, e); | |
16722 | } | |
16723 | ||
16724 | #[simd_test(enable = "neon")] | |
16725 | unsafe fn test_vzip1q_s64() { | |
16726 | let a: i64x2 = i64x2::new(0, 2); | |
16727 | let b: i64x2 = i64x2::new(1, 3); | |
16728 | let e: i64x2 = i64x2::new(0, 1); | |
16729 | let r: i64x2 = transmute(vzip1q_s64(transmute(a), transmute(b))); | |
16730 | assert_eq!(r, e); | |
16731 | } | |
16732 | ||
16733 | #[simd_test(enable = "neon")] | |
16734 | unsafe fn test_vzip1_u8() { | |
16735 | let a: u8x8 = u8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16736 | let b: u8x8 = u8x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16737 | let e: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); | |
16738 | let r: u8x8 = transmute(vzip1_u8(transmute(a), transmute(b))); | |
16739 | assert_eq!(r, e); | |
16740 | } | |
16741 | ||
16742 | #[simd_test(enable = "neon")] | |
16743 | unsafe fn test_vzip1q_u8() { | |
16744 | let a: u8x16 = u8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
16745 | let b: u8x16 = u8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); | |
16746 | let e: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); | |
16747 | let r: u8x16 = transmute(vzip1q_u8(transmute(a), transmute(b))); | |
16748 | assert_eq!(r, e); | |
16749 | } | |
16750 | ||
16751 | #[simd_test(enable = "neon")] | |
16752 | unsafe fn test_vzip1_u16() { | |
16753 | let a: u16x4 = u16x4::new(0, 2, 4, 6); | |
16754 | let b: u16x4 = u16x4::new(1, 3, 5, 7); | |
16755 | let e: u16x4 = u16x4::new(0, 1, 2, 3); | |
16756 | let r: u16x4 = transmute(vzip1_u16(transmute(a), transmute(b))); | |
16757 | assert_eq!(r, e); | |
16758 | } | |
16759 | ||
16760 | #[simd_test(enable = "neon")] | |
16761 | unsafe fn test_vzip1q_u16() { | |
16762 | let a: u16x8 = u16x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16763 | let b: u16x8 = u16x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16764 | let e: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); | |
16765 | let r: u16x8 = transmute(vzip1q_u16(transmute(a), transmute(b))); | |
16766 | assert_eq!(r, e); | |
16767 | } | |
16768 | ||
16769 | #[simd_test(enable = "neon")] | |
16770 | unsafe fn test_vzip1_u32() { | |
16771 | let a: u32x2 = u32x2::new(0, 2); | |
16772 | let b: u32x2 = u32x2::new(1, 3); | |
16773 | let e: u32x2 = u32x2::new(0, 1); | |
16774 | let r: u32x2 = transmute(vzip1_u32(transmute(a), transmute(b))); | |
16775 | assert_eq!(r, e); | |
16776 | } | |
16777 | ||
16778 | #[simd_test(enable = "neon")] | |
16779 | unsafe fn test_vzip1q_u32() { | |
16780 | let a: u32x4 = u32x4::new(0, 2, 4, 6); | |
16781 | let b: u32x4 = u32x4::new(1, 3, 5, 7); | |
16782 | let e: u32x4 = u32x4::new(0, 1, 2, 3); | |
16783 | let r: u32x4 = transmute(vzip1q_u32(transmute(a), transmute(b))); | |
16784 | assert_eq!(r, e); | |
16785 | } | |
16786 | ||
16787 | #[simd_test(enable = "neon")] | |
16788 | unsafe fn test_vzip1q_u64() { | |
16789 | let a: u64x2 = u64x2::new(0, 2); | |
16790 | let b: u64x2 = u64x2::new(1, 3); | |
16791 | let e: u64x2 = u64x2::new(0, 1); | |
16792 | let r: u64x2 = transmute(vzip1q_u64(transmute(a), transmute(b))); | |
16793 | assert_eq!(r, e); | |
16794 | } | |
16795 | ||
16796 | #[simd_test(enable = "neon")] | |
16797 | unsafe fn test_vzip1_p8() { | |
16798 | let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16799 | let b: i8x8 = i8x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16800 | let e: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); | |
16801 | let r: i8x8 = transmute(vzip1_p8(transmute(a), transmute(b))); | |
16802 | assert_eq!(r, e); | |
16803 | } | |
16804 | ||
16805 | #[simd_test(enable = "neon")] | |
16806 | unsafe fn test_vzip1q_p8() { | |
16807 | let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); | |
16808 | let b: i8x16 = i8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); | |
16809 | let e: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); | |
16810 | let r: i8x16 = transmute(vzip1q_p8(transmute(a), transmute(b))); | |
16811 | assert_eq!(r, e); | |
16812 | } | |
16813 | ||
16814 | #[simd_test(enable = "neon")] | |
16815 | unsafe fn test_vzip1_p16() { | |
16816 | let a: i16x4 = i16x4::new(0, 2, 4, 6); | |
16817 | let b: i16x4 = i16x4::new(1, 3, 5, 7); | |
16818 | let e: i16x4 = i16x4::new(0, 1, 2, 3); | |
16819 | let r: i16x4 = transmute(vzip1_p16(transmute(a), transmute(b))); | |
16820 | assert_eq!(r, e); | |
16821 | } | |
16822 | ||
16823 | #[simd_test(enable = "neon")] | |
16824 | unsafe fn test_vzip1q_p16() { | |
16825 | let a: i16x8 = i16x8::new(0, 2, 4, 6, 8, 10, 12, 14); | |
16826 | let b: i16x8 = i16x8::new(1, 3, 5, 7, 9, 11, 13, 15); | |
16827 | let e: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); | |
16828 | let r: i16x8 = transmute(vzip1q_p16(transmute(a), transmute(b))); | |
16829 | assert_eq!(r, e); | |
16830 | } | |
16831 | ||
16832 | #[simd_test(enable = "neon")] | |
16833 | unsafe fn test_vzip1q_p64() { | |
16834 | let a: i64x2 = i64x2::new(0, 2); | |
16835 | let b: i64x2 = i64x2::new(1, 3); | |
16836 | let e: i64x2 = i64x2::new(0, 1); | |
16837 | let r: i64x2 = transmute(vzip1q_p64(transmute(a), transmute(b))); | |
16838 | assert_eq!(r, e); | |
16839 | } | |
16840 | ||
16841 | #[simd_test(enable = "neon")] | |
16842 | unsafe fn test_vzip1_f32() { | |
16843 | let a: f32x2 = f32x2::new(0., 2.); | |
16844 | let b: f32x2 = f32x2::new(1., 3.); | |
16845 | let e: f32x2 = f32x2::new(0., 1.); | |
16846 | let r: f32x2 = transmute(vzip1_f32(transmute(a), transmute(b))); | |
16847 | assert_eq!(r, e); | |
16848 | } | |
16849 | ||
16850 | #[simd_test(enable = "neon")] | |
16851 | unsafe fn test_vzip1q_f32() { | |
16852 | let a: f32x4 = f32x4::new(0., 2., 4., 6.); | |
16853 | let b: f32x4 = f32x4::new(1., 3., 5., 7.); | |
16854 | let e: f32x4 = f32x4::new(0., 1., 2., 3.); | |
16855 | let r: f32x4 = transmute(vzip1q_f32(transmute(a), transmute(b))); | |
16856 | assert_eq!(r, e); | |
16857 | } | |
16858 | ||
16859 | #[simd_test(enable = "neon")] | |
16860 | unsafe fn test_vzip1q_f64() { | |
16861 | let a: f64x2 = f64x2::new(0., 2.); | |
16862 | let b: f64x2 = f64x2::new(1., 3.); | |
16863 | let e: f64x2 = f64x2::new(0., 1.); | |
16864 | let r: f64x2 = transmute(vzip1q_f64(transmute(a), transmute(b))); | |
16865 | assert_eq!(r, e); | |
16866 | } | |
16867 | ||
16868 | #[simd_test(enable = "neon")] | |
16869 | unsafe fn test_vzip2_s8() { | |
16870 | let a: i8x8 = i8x8::new(0, 16, 16, 18, 16, 18, 20, 22); | |
16871 | let b: i8x8 = i8x8::new(1, 17, 17, 19, 17, 19, 21, 23); | |
16872 | let e: i8x8 = i8x8::new(16, 17, 18, 19, 20, 21, 22, 23); | |
16873 | let r: i8x8 = transmute(vzip2_s8(transmute(a), transmute(b))); | |
16874 | assert_eq!(r, e); | |
16875 | } | |
16876 | ||
16877 | #[simd_test(enable = "neon")] | |
16878 | unsafe fn test_vzip2q_s8() { | |
16879 | let a: i8x16 = i8x16::new(0, 16, 16, 18, 16, 18, 20, 22, 16, 18, 20, 22, 24, 26, 28, 30); | |
16880 | let b: i8x16 = i8x16::new(1, 17, 17, 19, 17, 19, 21, 23, 17, 19, 21, 23, 25, 27, 29, 31); | |
16881 | let e: i8x16 = i8x16::new(16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31); | |
16882 | let r: i8x16 = transmute(vzip2q_s8(transmute(a), transmute(b))); | |
16883 | assert_eq!(r, e); | |
16884 | } | |
16885 | ||
16886 | #[simd_test(enable = "neon")] | |
16887 | unsafe fn test_vzip2_s16() { | |
16888 | let a: i16x4 = i16x4::new(0, 16, 16, 18); | |
16889 | let b: i16x4 = i16x4::new(1, 17, 17, 19); | |
16890 | let e: i16x4 = i16x4::new(16, 17, 18, 19); | |
16891 | let r: i16x4 = transmute(vzip2_s16(transmute(a), transmute(b))); | |
16892 | assert_eq!(r, e); | |
16893 | } | |
16894 | ||
16895 | #[simd_test(enable = "neon")] | |
16896 | unsafe fn test_vzip2q_s16() { | |
16897 | let a: i16x8 = i16x8::new(0, 16, 16, 18, 16, 18, 20, 22); | |
16898 | let b: i16x8 = i16x8::new(1, 17, 17, 19, 17, 19, 21, 23); | |
16899 | let e: i16x8 = i16x8::new(16, 17, 18, 19, 20, 21, 22, 23); | |
16900 | let r: i16x8 = transmute(vzip2q_s16(transmute(a), transmute(b))); | |
16901 | assert_eq!(r, e); | |
16902 | } | |
16903 | ||
16904 | #[simd_test(enable = "neon")] | |
16905 | unsafe fn test_vzip2_s32() { | |
16906 | let a: i32x2 = i32x2::new(0, 16); | |
16907 | let b: i32x2 = i32x2::new(1, 17); | |
16908 | let e: i32x2 = i32x2::new(16, 17); | |
16909 | let r: i32x2 = transmute(vzip2_s32(transmute(a), transmute(b))); | |
16910 | assert_eq!(r, e); | |
16911 | } | |
16912 | ||
16913 | #[simd_test(enable = "neon")] | |
16914 | unsafe fn test_vzip2q_s32() { | |
16915 | let a: i32x4 = i32x4::new(0, 16, 16, 18); | |
16916 | let b: i32x4 = i32x4::new(1, 17, 17, 19); | |
16917 | let e: i32x4 = i32x4::new(16, 17, 18, 19); | |
16918 | let r: i32x4 = transmute(vzip2q_s32(transmute(a), transmute(b))); | |
16919 | assert_eq!(r, e); | |
16920 | } | |
16921 | ||
16922 | #[simd_test(enable = "neon")] | |
16923 | unsafe fn test_vzip2q_s64() { | |
16924 | let a: i64x2 = i64x2::new(0, 16); | |
16925 | let b: i64x2 = i64x2::new(1, 17); | |
16926 | let e: i64x2 = i64x2::new(16, 17); | |
16927 | let r: i64x2 = transmute(vzip2q_s64(transmute(a), transmute(b))); | |
16928 | assert_eq!(r, e); | |
16929 | } | |
16930 | ||
16931 | #[simd_test(enable = "neon")] | |
16932 | unsafe fn test_vzip2_u8() { | |
16933 | let a: u8x8 = u8x8::new(0, 16, 16, 18, 16, 18, 20, 22); | |
16934 | let b: u8x8 = u8x8::new(1, 17, 17, 19, 17, 19, 21, 23); | |
16935 | let e: u8x8 = u8x8::new(16, 17, 18, 19, 20, 21, 22, 23); | |
16936 | let r: u8x8 = transmute(vzip2_u8(transmute(a), transmute(b))); | |
16937 | assert_eq!(r, e); | |
16938 | } | |
16939 | ||
16940 | #[simd_test(enable = "neon")] | |
16941 | unsafe fn test_vzip2q_u8() { | |
16942 | let a: u8x16 = u8x16::new(0, 16, 16, 18, 16, 18, 20, 22, 16, 18, 20, 22, 24, 26, 28, 30); | |
16943 | let b: u8x16 = u8x16::new(1, 17, 17, 19, 17, 19, 21, 23, 17, 19, 21, 23, 25, 27, 29, 31); | |
16944 | let e: u8x16 = u8x16::new(16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31); | |
16945 | let r: u8x16 = transmute(vzip2q_u8(transmute(a), transmute(b))); | |
16946 | assert_eq!(r, e); | |
16947 | } | |
16948 | ||
16949 | #[simd_test(enable = "neon")] | |
16950 | unsafe fn test_vzip2_u16() { | |
16951 | let a: u16x4 = u16x4::new(0, 16, 16, 18); | |
16952 | let b: u16x4 = u16x4::new(1, 17, 17, 19); | |
16953 | let e: u16x4 = u16x4::new(16, 17, 18, 19); | |
16954 | let r: u16x4 = transmute(vzip2_u16(transmute(a), transmute(b))); | |
16955 | assert_eq!(r, e); | |
16956 | } | |
16957 | ||
16958 | #[simd_test(enable = "neon")] | |
16959 | unsafe fn test_vzip2q_u16() { | |
16960 | let a: u16x8 = u16x8::new(0, 16, 16, 18, 16, 18, 20, 22); | |
16961 | let b: u16x8 = u16x8::new(1, 17, 17, 19, 17, 19, 21, 23); | |
16962 | let e: u16x8 = u16x8::new(16, 17, 18, 19, 20, 21, 22, 23); | |
16963 | let r: u16x8 = transmute(vzip2q_u16(transmute(a), transmute(b))); | |
16964 | assert_eq!(r, e); | |
16965 | } | |
16966 | ||
16967 | #[simd_test(enable = "neon")] | |
16968 | unsafe fn test_vzip2_u32() { | |
16969 | let a: u32x2 = u32x2::new(0, 16); | |
16970 | let b: u32x2 = u32x2::new(1, 17); | |
16971 | let e: u32x2 = u32x2::new(16, 17); | |
16972 | let r: u32x2 = transmute(vzip2_u32(transmute(a), transmute(b))); | |
16973 | assert_eq!(r, e); | |
16974 | } | |
16975 | ||
16976 | #[simd_test(enable = "neon")] | |
16977 | unsafe fn test_vzip2q_u32() { | |
16978 | let a: u32x4 = u32x4::new(0, 16, 16, 18); | |
16979 | let b: u32x4 = u32x4::new(1, 17, 17, 19); | |
16980 | let e: u32x4 = u32x4::new(16, 17, 18, 19); | |
16981 | let r: u32x4 = transmute(vzip2q_u32(transmute(a), transmute(b))); | |
16982 | assert_eq!(r, e); | |
16983 | } | |
16984 | ||
16985 | #[simd_test(enable = "neon")] | |
16986 | unsafe fn test_vzip2q_u64() { | |
16987 | let a: u64x2 = u64x2::new(0, 16); | |
16988 | let b: u64x2 = u64x2::new(1, 17); | |
16989 | let e: u64x2 = u64x2::new(16, 17); | |
16990 | let r: u64x2 = transmute(vzip2q_u64(transmute(a), transmute(b))); | |
16991 | assert_eq!(r, e); | |
16992 | } | |
16993 | ||
16994 | #[simd_test(enable = "neon")] | |
16995 | unsafe fn test_vzip2_p8() { | |
16996 | let a: i8x8 = i8x8::new(0, 16, 16, 18, 16, 18, 20, 22); | |
16997 | let b: i8x8 = i8x8::new(1, 17, 17, 19, 17, 19, 21, 23); | |
16998 | let e: i8x8 = i8x8::new(16, 17, 18, 19, 20, 21, 22, 23); | |
16999 | let r: i8x8 = transmute(vzip2_p8(transmute(a), transmute(b))); | |
17000 | assert_eq!(r, e); | |
17001 | } | |
17002 | ||
17003 | #[simd_test(enable = "neon")] | |
17004 | unsafe fn test_vzip2q_p8() { | |
17005 | let a: i8x16 = i8x16::new(0, 16, 16, 18, 16, 18, 20, 22, 16, 18, 20, 22, 24, 26, 28, 30); | |
17006 | let b: i8x16 = i8x16::new(1, 17, 17, 19, 17, 19, 21, 23, 17, 19, 21, 23, 25, 27, 29, 31); | |
17007 | let e: i8x16 = i8x16::new(16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31); | |
17008 | let r: i8x16 = transmute(vzip2q_p8(transmute(a), transmute(b))); | |
17009 | assert_eq!(r, e); | |
17010 | } | |
17011 | ||
17012 | #[simd_test(enable = "neon")] | |
17013 | unsafe fn test_vzip2_p16() { | |
17014 | let a: i16x4 = i16x4::new(0, 16, 16, 18); | |
17015 | let b: i16x4 = i16x4::new(1, 17, 17, 19); | |
17016 | let e: i16x4 = i16x4::new(16, 17, 18, 19); | |
17017 | let r: i16x4 = transmute(vzip2_p16(transmute(a), transmute(b))); | |
17018 | assert_eq!(r, e); | |
17019 | } | |
17020 | ||
17021 | #[simd_test(enable = "neon")] | |
17022 | unsafe fn test_vzip2q_p16() { | |
17023 | let a: i16x8 = i16x8::new(0, 16, 16, 18, 16, 18, 20, 22); | |
17024 | let b: i16x8 = i16x8::new(1, 17, 17, 19, 17, 19, 21, 23); | |
17025 | let e: i16x8 = i16x8::new(16, 17, 18, 19, 20, 21, 22, 23); | |
17026 | let r: i16x8 = transmute(vzip2q_p16(transmute(a), transmute(b))); | |
17027 | assert_eq!(r, e); | |
17028 | } | |
17029 | ||
17030 | #[simd_test(enable = "neon")] | |
17031 | unsafe fn test_vzip2q_p64() { | |
17032 | let a: i64x2 = i64x2::new(0, 16); | |
17033 | let b: i64x2 = i64x2::new(1, 17); | |
17034 | let e: i64x2 = i64x2::new(16, 17); | |
17035 | let r: i64x2 = transmute(vzip2q_p64(transmute(a), transmute(b))); | |
17036 | assert_eq!(r, e); | |
17037 | } | |
ba9703b0 XL |
17038 | |
17039 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17040 | unsafe fn test_vzip2_f32() { |
17041 | let a: f32x2 = f32x2::new(0., 8.); | |
17042 | let b: f32x2 = f32x2::new(1., 9.); | |
17043 | let e: f32x2 = f32x2::new(8., 9.); | |
17044 | let r: f32x2 = transmute(vzip2_f32(transmute(a), transmute(b))); | |
ba9703b0 | 17045 | assert_eq!(r, e); |
17df50a5 | 17046 | } |
ba9703b0 | 17047 | |
17df50a5 XL |
17048 | #[simd_test(enable = "neon")] |
17049 | unsafe fn test_vzip2q_f32() { | |
17050 | let a: f32x4 = f32x4::new(0., 8., 8., 10.); | |
17051 | let b: f32x4 = f32x4::new(1., 9., 9., 11.); | |
17052 | let e: f32x4 = f32x4::new(8., 9., 10., 11.); | |
17053 | let r: f32x4 = transmute(vzip2q_f32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17054 | assert_eq!(r, e); |
17055 | } | |
17056 | ||
17057 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17058 | unsafe fn test_vzip2q_f64() { |
17059 | let a: f64x2 = f64x2::new(0., 8.); | |
17060 | let b: f64x2 = f64x2::new(1., 9.); | |
17061 | let e: f64x2 = f64x2::new(8., 9.); | |
17062 | let r: f64x2 = transmute(vzip2q_f64(transmute(a), transmute(b))); | |
ba9703b0 | 17063 | assert_eq!(r, e); |
17df50a5 | 17064 | } |
ba9703b0 | 17065 | |
17df50a5 XL |
17066 | #[simd_test(enable = "neon")] |
17067 | unsafe fn test_vuzp1_s8() { | |
17068 | let a: i8x8 = i8x8::new(1, 0, 2, 0, 2, 0, 3, 0); | |
17069 | let b: i8x8 = i8x8::new(2, 0, 3, 0, 7, 0, 8, 0); | |
17070 | let e: i8x8 = i8x8::new(1, 2, 2, 3, 2, 3, 7, 8); | |
17071 | let r: i8x8 = transmute(vuzp1_s8(transmute(a), transmute(b))); | |
ba9703b0 XL |
17072 | assert_eq!(r, e); |
17073 | } | |
17074 | ||
17075 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17076 | unsafe fn test_vuzp1q_s8() { |
17077 | let a: i8x16 = i8x16::new(1, 0, 2, 0, 2, 0, 3, 0, 2, 0, 3, 0, 7, 0, 8, 0); | |
17078 | let b: i8x16 = i8x16::new(2, 0, 3, 0, 7, 0, 8, 0, 13, 0, 14, 0, 15, 0, 16, 0); | |
17079 | let e: i8x16 = i8x16::new(1, 2, 2, 3, 2, 3, 7, 8, 2, 3, 7, 8, 13, 14, 15, 16); | |
17080 | let r: i8x16 = transmute(vuzp1q_s8(transmute(a), transmute(b))); | |
ba9703b0 | 17081 | assert_eq!(r, e); |
17df50a5 | 17082 | } |
ba9703b0 | 17083 | |
17df50a5 XL |
17084 | #[simd_test(enable = "neon")] |
17085 | unsafe fn test_vuzp1_s16() { | |
17086 | let a: i16x4 = i16x4::new(1, 0, 2, 0); | |
17087 | let b: i16x4 = i16x4::new(2, 0, 3, 0); | |
17088 | let e: i16x4 = i16x4::new(1, 2, 2, 3); | |
17089 | let r: i16x4 = transmute(vuzp1_s16(transmute(a), transmute(b))); | |
ba9703b0 XL |
17090 | assert_eq!(r, e); |
17091 | } | |
17092 | ||
17093 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17094 | unsafe fn test_vuzp1q_s16() { |
17095 | let a: i16x8 = i16x8::new(1, 0, 2, 0, 2, 0, 3, 0); | |
17096 | let b: i16x8 = i16x8::new(2, 0, 3, 0, 7, 0, 8, 0); | |
17097 | let e: i16x8 = i16x8::new(1, 2, 2, 3, 2, 3, 7, 8); | |
17098 | let r: i16x8 = transmute(vuzp1q_s16(transmute(a), transmute(b))); | |
ba9703b0 | 17099 | assert_eq!(r, e); |
17df50a5 | 17100 | } |
ba9703b0 | 17101 | |
17df50a5 XL |
17102 | #[simd_test(enable = "neon")] |
17103 | unsafe fn test_vuzp1q_s32() { | |
17104 | let a: i32x4 = i32x4::new(1, 0, 2, 0); | |
17105 | let b: i32x4 = i32x4::new(2, 0, 3, 0); | |
17106 | let e: i32x4 = i32x4::new(1, 2, 2, 3); | |
17107 | let r: i32x4 = transmute(vuzp1q_s32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17108 | assert_eq!(r, e); |
17109 | } | |
17110 | ||
17111 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17112 | unsafe fn test_vuzp1_u8() { |
17113 | let a: u8x8 = u8x8::new(1, 0, 2, 0, 2, 0, 3, 0); | |
17114 | let b: u8x8 = u8x8::new(2, 0, 3, 0, 7, 0, 8, 0); | |
17115 | let e: u8x8 = u8x8::new(1, 2, 2, 3, 2, 3, 7, 8); | |
17116 | let r: u8x8 = transmute(vuzp1_u8(transmute(a), transmute(b))); | |
ba9703b0 | 17117 | assert_eq!(r, e); |
17df50a5 | 17118 | } |
ba9703b0 | 17119 | |
17df50a5 XL |
17120 | #[simd_test(enable = "neon")] |
17121 | unsafe fn test_vuzp1q_u8() { | |
17122 | let a: u8x16 = u8x16::new(1, 0, 2, 0, 2, 0, 3, 0, 2, 0, 3, 0, 7, 0, 8, 0); | |
17123 | let b: u8x16 = u8x16::new(2, 0, 3, 0, 7, 0, 8, 0, 13, 0, 14, 0, 15, 0, 16, 0); | |
17124 | let e: u8x16 = u8x16::new(1, 2, 2, 3, 2, 3, 7, 8, 2, 3, 7, 8, 13, 14, 15, 16); | |
17125 | let r: u8x16 = transmute(vuzp1q_u8(transmute(a), transmute(b))); | |
ba9703b0 XL |
17126 | assert_eq!(r, e); |
17127 | } | |
17128 | ||
17129 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17130 | unsafe fn test_vuzp1_u16() { |
17131 | let a: u16x4 = u16x4::new(1, 0, 2, 0); | |
17132 | let b: u16x4 = u16x4::new(2, 0, 3, 0); | |
17133 | let e: u16x4 = u16x4::new(1, 2, 2, 3); | |
17134 | let r: u16x4 = transmute(vuzp1_u16(transmute(a), transmute(b))); | |
ba9703b0 | 17135 | assert_eq!(r, e); |
17df50a5 | 17136 | } |
ba9703b0 | 17137 | |
17df50a5 XL |
17138 | #[simd_test(enable = "neon")] |
17139 | unsafe fn test_vuzp1q_u16() { | |
17140 | let a: u16x8 = u16x8::new(1, 0, 2, 0, 2, 0, 3, 0); | |
17141 | let b: u16x8 = u16x8::new(2, 0, 3, 0, 7, 0, 8, 0); | |
17142 | let e: u16x8 = u16x8::new(1, 2, 2, 3, 2, 3, 7, 8); | |
17143 | let r: u16x8 = transmute(vuzp1q_u16(transmute(a), transmute(b))); | |
ba9703b0 XL |
17144 | assert_eq!(r, e); |
17145 | } | |
17146 | ||
17147 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17148 | unsafe fn test_vuzp1q_u32() { |
17149 | let a: u32x4 = u32x4::new(1, 0, 2, 0); | |
17150 | let b: u32x4 = u32x4::new(2, 0, 3, 0); | |
17151 | let e: u32x4 = u32x4::new(1, 2, 2, 3); | |
17152 | let r: u32x4 = transmute(vuzp1q_u32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17153 | assert_eq!(r, e); |
17154 | } | |
17155 | ||
17156 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17157 | unsafe fn test_vuzp1_p8() { |
17158 | let a: i8x8 = i8x8::new(1, 0, 2, 0, 2, 0, 3, 0); | |
17159 | let b: i8x8 = i8x8::new(2, 0, 3, 0, 7, 0, 8, 0); | |
17160 | let e: i8x8 = i8x8::new(1, 2, 2, 3, 2, 3, 7, 8); | |
17161 | let r: i8x8 = transmute(vuzp1_p8(transmute(a), transmute(b))); | |
ba9703b0 XL |
17162 | assert_eq!(r, e); |
17163 | } | |
17164 | ||
17165 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17166 | unsafe fn test_vuzp1q_p8() { |
17167 | let a: i8x16 = i8x16::new(1, 0, 2, 0, 2, 0, 3, 0, 2, 0, 3, 0, 7, 0, 8, 0); | |
17168 | let b: i8x16 = i8x16::new(2, 0, 3, 0, 7, 0, 8, 0, 13, 0, 14, 0, 15, 0, 16, 0); | |
17169 | let e: i8x16 = i8x16::new(1, 2, 2, 3, 2, 3, 7, 8, 2, 3, 7, 8, 13, 14, 15, 16); | |
17170 | let r: i8x16 = transmute(vuzp1q_p8(transmute(a), transmute(b))); | |
ba9703b0 XL |
17171 | assert_eq!(r, e); |
17172 | } | |
17173 | ||
17174 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17175 | unsafe fn test_vuzp1_p16() { |
17176 | let a: i16x4 = i16x4::new(1, 0, 2, 0); | |
17177 | let b: i16x4 = i16x4::new(2, 0, 3, 0); | |
17178 | let e: i16x4 = i16x4::new(1, 2, 2, 3); | |
17179 | let r: i16x4 = transmute(vuzp1_p16(transmute(a), transmute(b))); | |
ba9703b0 XL |
17180 | assert_eq!(r, e); |
17181 | } | |
17182 | ||
17183 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17184 | unsafe fn test_vuzp1q_p16() { |
17185 | let a: i16x8 = i16x8::new(1, 0, 2, 0, 2, 0, 3, 0); | |
17186 | let b: i16x8 = i16x8::new(2, 0, 3, 0, 7, 0, 8, 0); | |
17187 | let e: i16x8 = i16x8::new(1, 2, 2, 3, 2, 3, 7, 8); | |
17188 | let r: i16x8 = transmute(vuzp1q_p16(transmute(a), transmute(b))); | |
ba9703b0 XL |
17189 | assert_eq!(r, e); |
17190 | } | |
17191 | ||
17192 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17193 | unsafe fn test_vuzp1_s32() { |
17194 | let a: i32x2 = i32x2::new(1, 0); | |
17195 | let b: i32x2 = i32x2::new(2, 0); | |
17196 | let e: i32x2 = i32x2::new(1, 2); | |
17197 | let r: i32x2 = transmute(vuzp1_s32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17198 | assert_eq!(r, e); |
17199 | } | |
17200 | ||
17201 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17202 | unsafe fn test_vuzp1q_s64() { |
17203 | let a: i64x2 = i64x2::new(1, 0); | |
17204 | let b: i64x2 = i64x2::new(2, 0); | |
17205 | let e: i64x2 = i64x2::new(1, 2); | |
17206 | let r: i64x2 = transmute(vuzp1q_s64(transmute(a), transmute(b))); | |
ba9703b0 XL |
17207 | assert_eq!(r, e); |
17208 | } | |
17209 | ||
17210 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17211 | unsafe fn test_vuzp1_u32() { |
17212 | let a: u32x2 = u32x2::new(1, 0); | |
17213 | let b: u32x2 = u32x2::new(2, 0); | |
17214 | let e: u32x2 = u32x2::new(1, 2); | |
17215 | let r: u32x2 = transmute(vuzp1_u32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17216 | assert_eq!(r, e); |
17217 | } | |
17218 | ||
17219 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17220 | unsafe fn test_vuzp1q_u64() { |
17221 | let a: u64x2 = u64x2::new(1, 0); | |
17222 | let b: u64x2 = u64x2::new(2, 0); | |
17223 | let e: u64x2 = u64x2::new(1, 2); | |
17224 | let r: u64x2 = transmute(vuzp1q_u64(transmute(a), transmute(b))); | |
ba9703b0 XL |
17225 | assert_eq!(r, e); |
17226 | } | |
17227 | ||
17228 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17229 | unsafe fn test_vuzp1q_p64() { |
17230 | let a: i64x2 = i64x2::new(1, 0); | |
17231 | let b: i64x2 = i64x2::new(2, 0); | |
17232 | let e: i64x2 = i64x2::new(1, 2); | |
17233 | let r: i64x2 = transmute(vuzp1q_p64(transmute(a), transmute(b))); | |
ba9703b0 XL |
17234 | assert_eq!(r, e); |
17235 | } | |
17236 | ||
17237 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17238 | unsafe fn test_vuzp1q_f32() { |
17239 | let a: f32x4 = f32x4::new(0., 8., 1., 9.); | |
17240 | let b: f32x4 = f32x4::new(1., 10., 3., 11.); | |
17241 | let e: f32x4 = f32x4::new(0., 1., 1., 3.); | |
17242 | let r: f32x4 = transmute(vuzp1q_f32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17243 | assert_eq!(r, e); |
17244 | } | |
17245 | ||
17246 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17247 | unsafe fn test_vuzp1_f32() { |
17248 | let a: f32x2 = f32x2::new(0., 8.); | |
17249 | let b: f32x2 = f32x2::new(1., 10.); | |
17250 | let e: f32x2 = f32x2::new(0., 1.); | |
17251 | let r: f32x2 = transmute(vuzp1_f32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17252 | assert_eq!(r, e); |
17253 | } | |
17254 | ||
17255 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17256 | unsafe fn test_vuzp1q_f64() { |
17257 | let a: f64x2 = f64x2::new(0., 8.); | |
17258 | let b: f64x2 = f64x2::new(1., 10.); | |
17259 | let e: f64x2 = f64x2::new(0., 1.); | |
17260 | let r: f64x2 = transmute(vuzp1q_f64(transmute(a), transmute(b))); | |
ba9703b0 XL |
17261 | assert_eq!(r, e); |
17262 | } | |
17263 | ||
17264 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17265 | unsafe fn test_vuzp2_s8() { |
17266 | let a: i8x8 = i8x8::new(0, 17, 0, 18, 0, 18, 0, 19); | |
17267 | let b: i8x8 = i8x8::new(0, 18, 0, 19, 0, 23, 0, 24); | |
17268 | let e: i8x8 = i8x8::new(17, 18, 18, 19, 18, 19, 23, 24); | |
17269 | let r: i8x8 = transmute(vuzp2_s8(transmute(a), transmute(b))); | |
ba9703b0 XL |
17270 | assert_eq!(r, e); |
17271 | } | |
17272 | ||
17273 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17274 | unsafe fn test_vuzp2q_s8() { |
17275 | let a: i8x16 = i8x16::new(0, 17, 0, 18, 0, 18, 0, 19, 0, 18, 0, 19, 0, 23, 0, 24); | |
17276 | let b: i8x16 = i8x16::new(0, 18, 0, 19, 0, 23, 0, 24, 0, 29, 0, 30, 0, 31, 0, 32); | |
17277 | let e: i8x16 = i8x16::new(17, 18, 18, 19, 18, 19, 23, 24, 18, 19, 23, 24, 29, 30, 31, 32); | |
17278 | let r: i8x16 = transmute(vuzp2q_s8(transmute(a), transmute(b))); | |
ba9703b0 XL |
17279 | assert_eq!(r, e); |
17280 | } | |
17281 | ||
17282 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17283 | unsafe fn test_vuzp2_s16() { |
17284 | let a: i16x4 = i16x4::new(0, 17, 0, 18); | |
17285 | let b: i16x4 = i16x4::new(0, 18, 0, 19); | |
17286 | let e: i16x4 = i16x4::new(17, 18, 18, 19); | |
17287 | let r: i16x4 = transmute(vuzp2_s16(transmute(a), transmute(b))); | |
ba9703b0 XL |
17288 | assert_eq!(r, e); |
17289 | } | |
17290 | ||
17291 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17292 | unsafe fn test_vuzp2q_s16() { |
17293 | let a: i16x8 = i16x8::new(0, 17, 0, 18, 0, 18, 0, 19); | |
17294 | let b: i16x8 = i16x8::new(0, 18, 0, 19, 0, 23, 0, 24); | |
17295 | let e: i16x8 = i16x8::new(17, 18, 18, 19, 18, 19, 23, 24); | |
17296 | let r: i16x8 = transmute(vuzp2q_s16(transmute(a), transmute(b))); | |
ba9703b0 XL |
17297 | assert_eq!(r, e); |
17298 | } | |
17299 | ||
17300 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17301 | unsafe fn test_vuzp2q_s32() { |
17302 | let a: i32x4 = i32x4::new(0, 17, 0, 18); | |
17303 | let b: i32x4 = i32x4::new(0, 18, 0, 19); | |
17304 | let e: i32x4 = i32x4::new(17, 18, 18, 19); | |
17305 | let r: i32x4 = transmute(vuzp2q_s32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17306 | assert_eq!(r, e); |
17307 | } | |
17308 | ||
17309 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17310 | unsafe fn test_vuzp2_u8() { |
17311 | let a: u8x8 = u8x8::new(0, 17, 0, 18, 0, 18, 0, 19); | |
17312 | let b: u8x8 = u8x8::new(0, 18, 0, 19, 0, 23, 0, 24); | |
17313 | let e: u8x8 = u8x8::new(17, 18, 18, 19, 18, 19, 23, 24); | |
17314 | let r: u8x8 = transmute(vuzp2_u8(transmute(a), transmute(b))); | |
ba9703b0 XL |
17315 | assert_eq!(r, e); |
17316 | } | |
17317 | ||
17318 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17319 | unsafe fn test_vuzp2q_u8() { |
17320 | let a: u8x16 = u8x16::new(0, 17, 0, 18, 0, 18, 0, 19, 0, 18, 0, 19, 0, 23, 0, 24); | |
17321 | let b: u8x16 = u8x16::new(0, 18, 0, 19, 0, 23, 0, 24, 0, 29, 0, 30, 0, 31, 0, 32); | |
17322 | let e: u8x16 = u8x16::new(17, 18, 18, 19, 18, 19, 23, 24, 18, 19, 23, 24, 29, 30, 31, 32); | |
17323 | let r: u8x16 = transmute(vuzp2q_u8(transmute(a), transmute(b))); | |
ba9703b0 XL |
17324 | assert_eq!(r, e); |
17325 | } | |
17326 | ||
17327 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17328 | unsafe fn test_vuzp2_u16() { |
17329 | let a: u16x4 = u16x4::new(0, 17, 0, 18); | |
17330 | let b: u16x4 = u16x4::new(0, 18, 0, 19); | |
17331 | let e: u16x4 = u16x4::new(17, 18, 18, 19); | |
17332 | let r: u16x4 = transmute(vuzp2_u16(transmute(a), transmute(b))); | |
ba9703b0 XL |
17333 | assert_eq!(r, e); |
17334 | } | |
17335 | ||
17336 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17337 | unsafe fn test_vuzp2q_u16() { |
17338 | let a: u16x8 = u16x8::new(0, 17, 0, 18, 0, 18, 0, 19); | |
17339 | let b: u16x8 = u16x8::new(0, 18, 0, 19, 0, 23, 0, 24); | |
17340 | let e: u16x8 = u16x8::new(17, 18, 18, 19, 18, 19, 23, 24); | |
17341 | let r: u16x8 = transmute(vuzp2q_u16(transmute(a), transmute(b))); | |
ba9703b0 XL |
17342 | assert_eq!(r, e); |
17343 | } | |
17344 | ||
17345 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17346 | unsafe fn test_vuzp2q_u32() { |
17347 | let a: u32x4 = u32x4::new(0, 17, 0, 18); | |
17348 | let b: u32x4 = u32x4::new(0, 18, 0, 19); | |
17349 | let e: u32x4 = u32x4::new(17, 18, 18, 19); | |
17350 | let r: u32x4 = transmute(vuzp2q_u32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17351 | assert_eq!(r, e); |
17352 | } | |
17353 | ||
17354 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17355 | unsafe fn test_vuzp2_p8() { |
17356 | let a: i8x8 = i8x8::new(0, 17, 0, 18, 0, 18, 0, 19); | |
17357 | let b: i8x8 = i8x8::new(0, 18, 0, 19, 0, 23, 0, 24); | |
17358 | let e: i8x8 = i8x8::new(17, 18, 18, 19, 18, 19, 23, 24); | |
17359 | let r: i8x8 = transmute(vuzp2_p8(transmute(a), transmute(b))); | |
ba9703b0 XL |
17360 | assert_eq!(r, e); |
17361 | } | |
17362 | ||
17363 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17364 | unsafe fn test_vuzp2q_p8() { |
17365 | let a: i8x16 = i8x16::new(0, 17, 0, 18, 0, 18, 0, 19, 0, 18, 0, 19, 0, 23, 0, 24); | |
17366 | let b: i8x16 = i8x16::new(0, 18, 0, 19, 0, 23, 0, 24, 0, 29, 0, 30, 0, 31, 0, 32); | |
17367 | let e: i8x16 = i8x16::new(17, 18, 18, 19, 18, 19, 23, 24, 18, 19, 23, 24, 29, 30, 31, 32); | |
17368 | let r: i8x16 = transmute(vuzp2q_p8(transmute(a), transmute(b))); | |
ba9703b0 XL |
17369 | assert_eq!(r, e); |
17370 | } | |
17371 | ||
17372 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17373 | unsafe fn test_vuzp2_p16() { |
17374 | let a: i16x4 = i16x4::new(0, 17, 0, 18); | |
17375 | let b: i16x4 = i16x4::new(0, 18, 0, 19); | |
17376 | let e: i16x4 = i16x4::new(17, 18, 18, 19); | |
17377 | let r: i16x4 = transmute(vuzp2_p16(transmute(a), transmute(b))); | |
ba9703b0 XL |
17378 | assert_eq!(r, e); |
17379 | } | |
17380 | ||
17381 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17382 | unsafe fn test_vuzp2q_p16() { |
17383 | let a: i16x8 = i16x8::new(0, 17, 0, 18, 0, 18, 0, 19); | |
17384 | let b: i16x8 = i16x8::new(0, 18, 0, 19, 0, 23, 0, 24); | |
17385 | let e: i16x8 = i16x8::new(17, 18, 18, 19, 18, 19, 23, 24); | |
17386 | let r: i16x8 = transmute(vuzp2q_p16(transmute(a), transmute(b))); | |
ba9703b0 XL |
17387 | assert_eq!(r, e); |
17388 | } | |
17389 | ||
17390 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17391 | unsafe fn test_vuzp2_s32() { |
17392 | let a: i32x2 = i32x2::new(0, 17); | |
17393 | let b: i32x2 = i32x2::new(0, 18); | |
17394 | let e: i32x2 = i32x2::new(17, 18); | |
17395 | let r: i32x2 = transmute(vuzp2_s32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17396 | assert_eq!(r, e); |
17397 | } | |
17398 | ||
17399 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17400 | unsafe fn test_vuzp2q_s64() { |
17401 | let a: i64x2 = i64x2::new(0, 17); | |
17402 | let b: i64x2 = i64x2::new(0, 18); | |
17403 | let e: i64x2 = i64x2::new(17, 18); | |
17404 | let r: i64x2 = transmute(vuzp2q_s64(transmute(a), transmute(b))); | |
ba9703b0 XL |
17405 | assert_eq!(r, e); |
17406 | } | |
17407 | ||
17408 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17409 | unsafe fn test_vuzp2_u32() { |
17410 | let a: u32x2 = u32x2::new(0, 17); | |
17411 | let b: u32x2 = u32x2::new(0, 18); | |
17412 | let e: u32x2 = u32x2::new(17, 18); | |
17413 | let r: u32x2 = transmute(vuzp2_u32(transmute(a), transmute(b))); | |
ba9703b0 XL |
17414 | assert_eq!(r, e); |
17415 | } | |
fc512014 XL |
17416 | |
17417 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17418 | unsafe fn test_vuzp2q_u64() { |
17419 | let a: u64x2 = u64x2::new(0, 17); | |
17420 | let b: u64x2 = u64x2::new(0, 18); | |
17421 | let e: u64x2 = u64x2::new(17, 18); | |
17422 | let r: u64x2 = transmute(vuzp2q_u64(transmute(a), transmute(b))); | |
fc512014 XL |
17423 | assert_eq!(r, e); |
17424 | } | |
17425 | ||
17426 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17427 | unsafe fn test_vuzp2q_p64() { |
17428 | let a: i64x2 = i64x2::new(0, 17); | |
17429 | let b: i64x2 = i64x2::new(0, 18); | |
17430 | let e: i64x2 = i64x2::new(17, 18); | |
17431 | let r: i64x2 = transmute(vuzp2q_p64(transmute(a), transmute(b))); | |
fc512014 XL |
17432 | assert_eq!(r, e); |
17433 | } | |
17434 | ||
17435 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17436 | unsafe fn test_vuzp2q_f32() { |
17437 | let a: f32x4 = f32x4::new(0., 8., 1., 9.); | |
17438 | let b: f32x4 = f32x4::new(2., 9., 3., 11.); | |
17439 | let e: f32x4 = f32x4::new(8., 9., 9., 11.); | |
17440 | let r: f32x4 = transmute(vuzp2q_f32(transmute(a), transmute(b))); | |
fc512014 XL |
17441 | assert_eq!(r, e); |
17442 | } | |
17443 | ||
17444 | #[simd_test(enable = "neon")] | |
17df50a5 XL |
17445 | unsafe fn test_vuzp2_f32() { |
17446 | let a: f32x2 = f32x2::new(0., 8.); | |
17447 | let b: f32x2 = f32x2::new(2., 9.); | |
17448 | let e: f32x2 = f32x2::new(8., 9.); | |
17449 | let r: f32x2 = transmute(vuzp2_f32(transmute(a), transmute(b))); | |
17450 | assert_eq!(r, e); | |
17451 | } | |
17452 | ||
17453 | #[simd_test(enable = "neon")] | |
17454 | unsafe fn test_vuzp2q_f64() { | |
17455 | let a: f64x2 = f64x2::new(0., 8.); | |
17456 | let b: f64x2 = f64x2::new(2., 9.); | |
17457 | let e: f64x2 = f64x2::new(8., 9.); | |
17458 | let r: f64x2 = transmute(vuzp2q_f64(transmute(a), transmute(b))); | |
17459 | assert_eq!(r, e); | |
17460 | } | |
17461 | ||
17462 | #[simd_test(enable = "neon")] | |
17463 | unsafe fn test_vabal_high_u8() { | |
17464 | let a: u16x8 = u16x8::new(9, 10, 11, 12, 13, 14, 15, 16); | |
17465 | let b: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
17466 | let c: u8x16 = u8x16::new(10, 10, 10, 10, 10, 10, 10, 10, 20, 0, 2, 4, 6, 8, 10, 12); | |
17467 | let e: u16x8 = u16x8::new(20, 20, 20, 20, 20, 20, 20, 20); | |
17468 | let r: u16x8 = transmute(vabal_high_u8(transmute(a), transmute(b), transmute(c))); | |
17469 | assert_eq!(r, e); | |
17470 | } | |
17471 | ||
17472 | #[simd_test(enable = "neon")] | |
17473 | unsafe fn test_vabal_high_u16() { | |
17474 | let a: u32x4 = u32x4::new(9, 10, 11, 12); | |
17475 | let b: u16x8 = u16x8::new(1, 2, 3, 4, 9, 10, 11, 12); | |
17476 | let c: u16x8 = u16x8::new(10, 10, 10, 10, 20, 0, 2, 4); | |
17477 | let e: u32x4 = u32x4::new(20, 20, 20, 20); | |
17478 | let r: u32x4 = transmute(vabal_high_u16(transmute(a), transmute(b), transmute(c))); | |
17479 | assert_eq!(r, e); | |
17480 | } | |
17481 | ||
17482 | #[simd_test(enable = "neon")] | |
17483 | unsafe fn test_vabal_high_u32() { | |
17484 | let a: u64x2 = u64x2::new(15, 16); | |
17485 | let b: u32x4 = u32x4::new(1, 2, 15, 16); | |
17486 | let c: u32x4 = u32x4::new(10, 10, 10, 12); | |
17487 | let e: u64x2 = u64x2::new(20, 20); | |
17488 | let r: u64x2 = transmute(vabal_high_u32(transmute(a), transmute(b), transmute(c))); | |
17489 | assert_eq!(r, e); | |
17490 | } | |
17491 | ||
17492 | #[simd_test(enable = "neon")] | |
17493 | unsafe fn test_vabal_high_s8() { | |
17494 | let a: i16x8 = i16x8::new(9, 10, 11, 12, 13, 14, 15, 16); | |
17495 | let b: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); | |
17496 | let c: i8x16 = i8x16::new(10, 10, 10, 10, 10, 10, 10, 10, 20, 0, 2, 4, 6, 8, 10, 12); | |
17497 | let e: i16x8 = i16x8::new(20, 20, 20, 20, 20, 20, 20, 20); | |
17498 | let r: i16x8 = transmute(vabal_high_s8(transmute(a), transmute(b), transmute(c))); | |
17499 | assert_eq!(r, e); | |
17500 | } | |
17501 | ||
17502 | #[simd_test(enable = "neon")] | |
17503 | unsafe fn test_vabal_high_s16() { | |
17504 | let a: i32x4 = i32x4::new(9, 10, 11, 12); | |
17505 | let b: i16x8 = i16x8::new(1, 2, 3, 4, 9, 10, 11, 12); | |
17506 | let c: i16x8 = i16x8::new(10, 10, 10, 10, 20, 0, 2, 4); | |
17507 | let e: i32x4 = i32x4::new(20, 20, 20, 20); | |
17508 | let r: i32x4 = transmute(vabal_high_s16(transmute(a), transmute(b), transmute(c))); | |
17509 | assert_eq!(r, e); | |
17510 | } | |
17511 | ||
17512 | #[simd_test(enable = "neon")] | |
17513 | unsafe fn test_vabal_high_s32() { | |
17514 | let a: i64x2 = i64x2::new(15, 16); | |
17515 | let b: i32x4 = i32x4::new(1, 2, 15, 16); | |
17516 | let c: i32x4 = i32x4::new(10, 10, 10, 12); | |
17517 | let e: i64x2 = i64x2::new(20, 20); | |
17518 | let r: i64x2 = transmute(vabal_high_s32(transmute(a), transmute(b), transmute(c))); | |
17519 | assert_eq!(r, e); | |
17520 | } | |
17521 | ||
17522 | #[simd_test(enable = "neon")] | |
17523 | unsafe fn test_vqabs_s64() { | |
17524 | let a: i64x1 = i64x1::new(-9223372036854775808); | |
17525 | let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); | |
17526 | let r: i64x1 = transmute(vqabs_s64(transmute(a))); | |
17527 | assert_eq!(r, e); | |
17528 | } | |
17529 | ||
17530 | #[simd_test(enable = "neon")] | |
17531 | unsafe fn test_vqabsq_s64() { | |
17532 | let a: i64x2 = i64x2::new(-9223372036854775808, -7); | |
17533 | let e: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 7); | |
17534 | let r: i64x2 = transmute(vqabsq_s64(transmute(a))); | |
fc512014 XL |
17535 | assert_eq!(r, e); |
17536 | } | |
ba9703b0 | 17537 | } |