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0531ce1d XL |
1 | //! `x86` and `x86_64` intrinsics. |
2 | ||
532ac7d7 | 3 | use crate::{intrinsics, marker::Sized, mem::transmute}; |
0531ce1d XL |
4 | |
5 | #[macro_use] | |
6 | mod macros; | |
7 | ||
0531ce1d | 8 | types! { |
0531ce1d XL |
9 | /// 128-bit wide integer vector type, x86-specific |
10 | /// | |
11 | /// This type is the same as the `__m128i` type defined by Intel, | |
12 | /// representing a 128-bit SIMD register. Usage of this type typically | |
13 | /// corresponds to the `sse` and up target features for x86/x86_64. | |
14 | /// | |
15 | /// Internally this type may be viewed as: | |
16 | /// | |
17 | /// * `i8x16` - sixteen `i8` variables packed together | |
18 | /// * `i16x8` - eight `i16` variables packed together | |
19 | /// * `i32x4` - four `i32` variables packed together | |
20 | /// * `i64x2` - two `i64` variables packed together | |
21 | /// | |
22 | /// (as well as unsigned versions). Each intrinsic may interpret the | |
23 | /// internal bits differently, check the documentation of the intrinsic | |
24 | /// to see how it's being used. | |
25 | /// | |
26 | /// Note that this means that an instance of `__m128i` typically just means | |
27 | /// a "bag of bits" which is left up to interpretation at the point of use. | |
28 | /// | |
29 | /// Most intrinsics using `__m128i` are prefixed with `_mm_` and the | |
30 | /// integer types tend to correspond to suffixes like "epi8" or "epi32". | |
31 | /// | |
32 | /// # Examples | |
33 | /// | |
34 | /// ``` | |
0531ce1d XL |
35 | /// #[cfg(target_arch = "x86")] |
36 | /// use std::arch::x86::*; | |
37 | /// #[cfg(target_arch = "x86_64")] | |
38 | /// use std::arch::x86_64::*; | |
39 | /// | |
40 | /// # fn main() { | |
41 | /// # #[target_feature(enable = "sse2")] | |
42 | /// # unsafe fn foo() { | |
43 | /// let all_bytes_zero = _mm_setzero_si128(); | |
44 | /// let all_bytes_one = _mm_set1_epi8(1); | |
45 | /// let four_i32 = _mm_set_epi32(1, 2, 3, 4); | |
46 | /// # } | |
47 | /// # if is_x86_feature_detected!("sse2") { unsafe { foo() } } | |
48 | /// # } | |
49 | /// ``` | |
83c7162d | 50 | #[stable(feature = "simd_x86", since = "1.27.0")] |
0531ce1d XL |
51 | pub struct __m128i(i64, i64); |
52 | ||
53 | /// 128-bit wide set of four `f32` types, x86-specific | |
54 | /// | |
55 | /// This type is the same as the `__m128` type defined by Intel, | |
56 | /// representing a 128-bit SIMD register which internally is consisted of | |
57 | /// four packed `f32` instances. Usage of this type typically corresponds | |
58 | /// to the `sse` and up target features for x86/x86_64. | |
59 | /// | |
60 | /// Note that unlike `__m128i`, the integer version of the 128-bit | |
61 | /// registers, this `__m128` type has *one* interpretation. Each instance | |
62 | /// of `__m128` always corresponds to `f32x4`, or four `f32` types packed | |
63 | /// together. | |
64 | /// | |
65 | /// Most intrinsics using `__m128` are prefixed with `_mm_` and are | |
66 | /// suffixed with "ps" (or otherwise contain "ps"). Not to be confused with | |
67 | /// "pd" which is used for `__m128d`. | |
68 | /// | |
69 | /// # Examples | |
70 | /// | |
71 | /// ``` | |
0531ce1d XL |
72 | /// #[cfg(target_arch = "x86")] |
73 | /// use std::arch::x86::*; | |
74 | /// #[cfg(target_arch = "x86_64")] | |
75 | /// use std::arch::x86_64::*; | |
76 | /// | |
77 | /// # fn main() { | |
78 | /// # #[target_feature(enable = "sse")] | |
79 | /// # unsafe fn foo() { | |
80 | /// let four_zeros = _mm_setzero_ps(); | |
81 | /// let four_ones = _mm_set1_ps(1.0); | |
82 | /// let four_floats = _mm_set_ps(1.0, 2.0, 3.0, 4.0); | |
83 | /// # } | |
84 | /// # if is_x86_feature_detected!("sse") { unsafe { foo() } } | |
85 | /// # } | |
86 | /// ``` | |
83c7162d | 87 | #[stable(feature = "simd_x86", since = "1.27.0")] |
0531ce1d XL |
88 | pub struct __m128(f32, f32, f32, f32); |
89 | ||
90 | /// 128-bit wide set of two `f64` types, x86-specific | |
91 | /// | |
92 | /// This type is the same as the `__m128d` type defined by Intel, | |
93 | /// representing a 128-bit SIMD register which internally is consisted of | |
94 | /// two packed `f64` instances. Usage of this type typically corresponds | |
95 | /// to the `sse` and up target features for x86/x86_64. | |
96 | /// | |
97 | /// Note that unlike `__m128i`, the integer version of the 128-bit | |
98 | /// registers, this `__m128d` type has *one* interpretation. Each instance | |
99 | /// of `__m128d` always corresponds to `f64x2`, or two `f64` types packed | |
100 | /// together. | |
101 | /// | |
102 | /// Most intrinsics using `__m128d` are prefixed with `_mm_` and are | |
103 | /// suffixed with "pd" (or otherwise contain "pd"). Not to be confused with | |
104 | /// "ps" which is used for `__m128`. | |
105 | /// | |
106 | /// # Examples | |
107 | /// | |
108 | /// ``` | |
0531ce1d XL |
109 | /// #[cfg(target_arch = "x86")] |
110 | /// use std::arch::x86::*; | |
111 | /// #[cfg(target_arch = "x86_64")] | |
112 | /// use std::arch::x86_64::*; | |
113 | /// | |
114 | /// # fn main() { | |
115 | /// # #[target_feature(enable = "sse")] | |
116 | /// # unsafe fn foo() { | |
117 | /// let two_zeros = _mm_setzero_pd(); | |
118 | /// let two_ones = _mm_set1_pd(1.0); | |
119 | /// let two_floats = _mm_set_pd(1.0, 2.0); | |
120 | /// # } | |
121 | /// # if is_x86_feature_detected!("sse") { unsafe { foo() } } | |
122 | /// # } | |
123 | /// ``` | |
83c7162d | 124 | #[stable(feature = "simd_x86", since = "1.27.0")] |
0531ce1d XL |
125 | pub struct __m128d(f64, f64); |
126 | ||
127 | /// 256-bit wide integer vector type, x86-specific | |
128 | /// | |
129 | /// This type is the same as the `__m256i` type defined by Intel, | |
130 | /// representing a 256-bit SIMD register. Usage of this type typically | |
131 | /// corresponds to the `avx` and up target features for x86/x86_64. | |
132 | /// | |
133 | /// Internally this type may be viewed as: | |
134 | /// | |
135 | /// * `i8x32` - thirty two `i8` variables packed together | |
136 | /// * `i16x16` - sixteen `i16` variables packed together | |
137 | /// * `i32x8` - eight `i32` variables packed together | |
138 | /// * `i64x4` - four `i64` variables packed together | |
139 | /// | |
140 | /// (as well as unsigned versions). Each intrinsic may interpret the | |
141 | /// internal bits differently, check the documentation of the intrinsic | |
142 | /// to see how it's being used. | |
143 | /// | |
144 | /// Note that this means that an instance of `__m256i` typically just means | |
145 | /// a "bag of bits" which is left up to interpretation at the point of use. | |
146 | /// | |
147 | /// # Examples | |
148 | /// | |
149 | /// ``` | |
0531ce1d XL |
150 | /// #[cfg(target_arch = "x86")] |
151 | /// use std::arch::x86::*; | |
152 | /// #[cfg(target_arch = "x86_64")] | |
153 | /// use std::arch::x86_64::*; | |
154 | /// | |
155 | /// # fn main() { | |
156 | /// # #[target_feature(enable = "avx")] | |
157 | /// # unsafe fn foo() { | |
158 | /// let all_bytes_zero = _mm256_setzero_si256(); | |
159 | /// let all_bytes_one = _mm256_set1_epi8(1); | |
160 | /// let eight_i32 = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8); | |
161 | /// # } | |
162 | /// # if is_x86_feature_detected!("avx") { unsafe { foo() } } | |
163 | /// # } | |
164 | /// ``` | |
83c7162d | 165 | #[stable(feature = "simd_x86", since = "1.27.0")] |
0531ce1d XL |
166 | pub struct __m256i(i64, i64, i64, i64); |
167 | ||
168 | /// 256-bit wide set of eight `f32` types, x86-specific | |
169 | /// | |
170 | /// This type is the same as the `__m256` type defined by Intel, | |
171 | /// representing a 256-bit SIMD register which internally is consisted of | |
172 | /// eight packed `f32` instances. Usage of this type typically corresponds | |
173 | /// to the `avx` and up target features for x86/x86_64. | |
174 | /// | |
175 | /// Note that unlike `__m256i`, the integer version of the 256-bit | |
176 | /// registers, this `__m256` type has *one* interpretation. Each instance | |
177 | /// of `__m256` always corresponds to `f32x8`, or eight `f32` types packed | |
178 | /// together. | |
179 | /// | |
180 | /// Most intrinsics using `__m256` are prefixed with `_mm256_` and are | |
181 | /// suffixed with "ps" (or otherwise contain "ps"). Not to be confused with | |
182 | /// "pd" which is used for `__m256d`. | |
183 | /// | |
184 | /// # Examples | |
185 | /// | |
186 | /// ``` | |
0531ce1d XL |
187 | /// #[cfg(target_arch = "x86")] |
188 | /// use std::arch::x86::*; | |
189 | /// #[cfg(target_arch = "x86_64")] | |
190 | /// use std::arch::x86_64::*; | |
191 | /// | |
192 | /// # fn main() { | |
8faf50e0 | 193 | /// # #[target_feature(enable = "avx")] |
0531ce1d XL |
194 | /// # unsafe fn foo() { |
195 | /// let eight_zeros = _mm256_setzero_ps(); | |
196 | /// let eight_ones = _mm256_set1_ps(1.0); | |
197 | /// let eight_floats = _mm256_set_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0); | |
198 | /// # } | |
8faf50e0 | 199 | /// # if is_x86_feature_detected!("avx") { unsafe { foo() } } |
0531ce1d XL |
200 | /// # } |
201 | /// ``` | |
83c7162d | 202 | #[stable(feature = "simd_x86", since = "1.27.0")] |
0531ce1d XL |
203 | pub struct __m256(f32, f32, f32, f32, f32, f32, f32, f32); |
204 | ||
205 | /// 256-bit wide set of four `f64` types, x86-specific | |
206 | /// | |
207 | /// This type is the same as the `__m256d` type defined by Intel, | |
208 | /// representing a 256-bit SIMD register which internally is consisted of | |
209 | /// four packed `f64` instances. Usage of this type typically corresponds | |
210 | /// to the `avx` and up target features for x86/x86_64. | |
211 | /// | |
212 | /// Note that unlike `__m256i`, the integer version of the 256-bit | |
213 | /// registers, this `__m256d` type has *one* interpretation. Each instance | |
214 | /// of `__m256d` always corresponds to `f64x4`, or four `f64` types packed | |
215 | /// together. | |
216 | /// | |
217 | /// Most intrinsics using `__m256d` are prefixed with `_mm256_` and are | |
218 | /// suffixed with "pd" (or otherwise contain "pd"). Not to be confused with | |
219 | /// "ps" which is used for `__m256`. | |
220 | /// | |
221 | /// # Examples | |
222 | /// | |
223 | /// ``` | |
0531ce1d XL |
224 | /// #[cfg(target_arch = "x86")] |
225 | /// use std::arch::x86::*; | |
226 | /// #[cfg(target_arch = "x86_64")] | |
227 | /// use std::arch::x86_64::*; | |
228 | /// | |
229 | /// # fn main() { | |
230 | /// # #[target_feature(enable = "avx")] | |
231 | /// # unsafe fn foo() { | |
232 | /// let four_zeros = _mm256_setzero_pd(); | |
233 | /// let four_ones = _mm256_set1_pd(1.0); | |
234 | /// let four_floats = _mm256_set_pd(1.0, 2.0, 3.0, 4.0); | |
235 | /// # } | |
236 | /// # if is_x86_feature_detected!("avx") { unsafe { foo() } } | |
237 | /// # } | |
238 | /// ``` | |
83c7162d | 239 | #[stable(feature = "simd_x86", since = "1.27.0")] |
0531ce1d | 240 | pub struct __m256d(f64, f64, f64, f64); |
0731742a XL |
241 | |
242 | /// 512-bit wide integer vector type, x86-specific | |
243 | /// | |
244 | /// This type is the same as the `__m512i` type defined by Intel, | |
245 | /// representing a 512-bit SIMD register. Usage of this type typically | |
246 | /// corresponds to the `avx512*` and up target features for x86/x86_64. | |
247 | /// | |
248 | /// Internally this type may be viewed as: | |
249 | /// | |
250 | /// * `i8x64` - sixty-four `i8` variables packed together | |
251 | /// * `i16x32` - thirty-two `i16` variables packed together | |
252 | /// * `i32x16` - sixteen `i32` variables packed together | |
253 | /// * `i64x8` - eight `i64` variables packed together | |
254 | /// | |
255 | /// (as well as unsigned versions). Each intrinsic may interpret the | |
256 | /// internal bits differently, check the documentation of the intrinsic | |
257 | /// to see how it's being used. | |
258 | /// | |
259 | /// Note that this means that an instance of `__m512i` typically just means | |
260 | /// a "bag of bits" which is left up to interpretation at the point of use. | |
261 | pub struct __m512i(i64, i64, i64, i64, i64, i64, i64, i64); | |
262 | ||
263 | /// 512-bit wide set of sixteen `f32` types, x86-specific | |
264 | /// | |
265 | /// This type is the same as the `__m512` type defined by Intel, | |
266 | /// representing a 512-bit SIMD register which internally is consisted of | |
267 | /// eight packed `f32` instances. Usage of this type typically corresponds | |
268 | /// to the `avx512*` and up target features for x86/x86_64. | |
269 | /// | |
270 | /// Note that unlike `__m512i`, the integer version of the 512-bit | |
271 | /// registers, this `__m512` type has *one* interpretation. Each instance | |
272 | /// of `__m512` always corresponds to `f32x16`, or sixteen `f32` types | |
273 | /// packed together. | |
274 | /// | |
275 | /// Most intrinsics using `__m512` are prefixed with `_mm512_` and are | |
276 | /// suffixed with "ps" (or otherwise contain "ps"). Not to be confused with | |
277 | /// "pd" which is used for `__m512d`. | |
278 | pub struct __m512( | |
279 | f32, f32, f32, f32, f32, f32, f32, f32, | |
280 | f32, f32, f32, f32, f32, f32, f32, f32, | |
281 | ); | |
282 | ||
283 | /// 512-bit wide set of eight `f64` types, x86-specific | |
284 | /// | |
285 | /// This type is the same as the `__m512d` type defined by Intel, | |
286 | /// representing a 512-bit SIMD register which internally is consisted of | |
287 | /// eight packed `f64` instances. Usage of this type typically corresponds | |
288 | /// to the `avx` and up target features for x86/x86_64. | |
289 | /// | |
290 | /// Note that unlike `__m512i`, the integer version of the 512-bit | |
291 | /// registers, this `__m512d` type has *one* interpretation. Each instance | |
292 | /// of `__m512d` always corresponds to `f64x4`, or eight `f64` types packed | |
293 | /// together. | |
294 | /// | |
295 | /// Most intrinsics using `__m512d` are prefixed with `_mm512_` and are | |
296 | /// suffixed with "pd" (or otherwise contain "pd"). Not to be confused with | |
297 | /// "ps" which is used for `__m512`. | |
298 | pub struct __m512d(f64, f64, f64, f64, f64, f64, f64, f64); | |
0531ce1d XL |
299 | } |
300 | ||
0731742a XL |
301 | /// The `__mmask16` type used in AVX-512 intrinsics, a 16-bit integer |
302 | #[allow(non_camel_case_types)] | |
f9f354fc XL |
303 | pub type __mmask16 = u16; |
304 | ||
305 | /// The `__mmask8` type used in AVX-512 intrinsics, a 8-bit integer | |
306 | #[allow(non_camel_case_types)] | |
307 | pub type __mmask8 = u8; | |
0731742a | 308 | |
3dfed10e XL |
309 | /// The `_MM_CMPINT_ENUM` type used to specify comparison operations in AVX-512 intrinsics. |
310 | #[allow(non_camel_case_types)] | |
311 | pub type _MM_CMPINT_ENUM = i32; | |
312 | ||
1b1a35ee | 313 | /// The `MM_MANTISSA_NORM_ENUM` type used to specify mantissa normalized operations in AVX-512 intrinsics. |
0531ce1d | 314 | #[allow(non_camel_case_types)] |
1b1a35ee | 315 | pub type _MM_MANTISSA_NORM_ENUM = i32; |
74b04a01 | 316 | |
1b1a35ee XL |
317 | /// The `MM_MANTISSA_SIGN_ENUM` type used to specify mantissa signed operations in AVX-512 intrinsics. |
318 | #[allow(non_camel_case_types)] | |
319 | pub type _MM_MANTISSA_SIGN_ENUM = i32; | |
74b04a01 | 320 | |
1b1a35ee XL |
321 | /// The `MM_PERM_ENUM` type used to specify shuffle operations in AVX-512 intrinsics. |
322 | #[allow(non_camel_case_types)] | |
323 | pub type _MM_PERM_ENUM = i32; | |
74b04a01 | 324 | |
1b1a35ee XL |
325 | #[cfg(test)] |
326 | mod test; | |
327 | #[cfg(test)] | |
328 | pub use self::test::*; | |
74b04a01 XL |
329 | |
330 | #[allow(non_camel_case_types)] | |
1b1a35ee | 331 | #[unstable(feature = "stdsimd_internal", issue = "none")] |
0531ce1d XL |
332 | pub(crate) trait m128iExt: Sized { |
333 | fn as_m128i(self) -> __m128i; | |
334 | ||
335 | #[inline] | |
532ac7d7 XL |
336 | fn as_u8x16(self) -> crate::core_arch::simd::u8x16 { |
337 | unsafe { transmute(self.as_m128i()) } | |
0531ce1d XL |
338 | } |
339 | ||
340 | #[inline] | |
532ac7d7 XL |
341 | fn as_u16x8(self) -> crate::core_arch::simd::u16x8 { |
342 | unsafe { transmute(self.as_m128i()) } | |
0531ce1d XL |
343 | } |
344 | ||
345 | #[inline] | |
532ac7d7 XL |
346 | fn as_u32x4(self) -> crate::core_arch::simd::u32x4 { |
347 | unsafe { transmute(self.as_m128i()) } | |
0531ce1d XL |
348 | } |
349 | ||
350 | #[inline] | |
532ac7d7 XL |
351 | fn as_u64x2(self) -> crate::core_arch::simd::u64x2 { |
352 | unsafe { transmute(self.as_m128i()) } | |
0531ce1d XL |
353 | } |
354 | ||
355 | #[inline] | |
532ac7d7 XL |
356 | fn as_i8x16(self) -> crate::core_arch::simd::i8x16 { |
357 | unsafe { transmute(self.as_m128i()) } | |
0531ce1d XL |
358 | } |
359 | ||
360 | #[inline] | |
532ac7d7 XL |
361 | fn as_i16x8(self) -> crate::core_arch::simd::i16x8 { |
362 | unsafe { transmute(self.as_m128i()) } | |
0531ce1d XL |
363 | } |
364 | ||
365 | #[inline] | |
532ac7d7 XL |
366 | fn as_i32x4(self) -> crate::core_arch::simd::i32x4 { |
367 | unsafe { transmute(self.as_m128i()) } | |
0531ce1d XL |
368 | } |
369 | ||
370 | #[inline] | |
532ac7d7 XL |
371 | fn as_i64x2(self) -> crate::core_arch::simd::i64x2 { |
372 | unsafe { transmute(self.as_m128i()) } | |
0531ce1d XL |
373 | } |
374 | } | |
375 | ||
376 | impl m128iExt for __m128i { | |
377 | #[inline] | |
378 | fn as_m128i(self) -> Self { | |
379 | self | |
380 | } | |
381 | } | |
382 | ||
0531ce1d | 383 | #[allow(non_camel_case_types)] |
1b1a35ee | 384 | #[unstable(feature = "stdsimd_internal", issue = "none")] |
0531ce1d XL |
385 | pub(crate) trait m256iExt: Sized { |
386 | fn as_m256i(self) -> __m256i; | |
387 | ||
388 | #[inline] | |
532ac7d7 XL |
389 | fn as_u8x32(self) -> crate::core_arch::simd::u8x32 { |
390 | unsafe { transmute(self.as_m256i()) } | |
0531ce1d XL |
391 | } |
392 | ||
393 | #[inline] | |
532ac7d7 XL |
394 | fn as_u16x16(self) -> crate::core_arch::simd::u16x16 { |
395 | unsafe { transmute(self.as_m256i()) } | |
0531ce1d XL |
396 | } |
397 | ||
398 | #[inline] | |
532ac7d7 XL |
399 | fn as_u32x8(self) -> crate::core_arch::simd::u32x8 { |
400 | unsafe { transmute(self.as_m256i()) } | |
0531ce1d XL |
401 | } |
402 | ||
403 | #[inline] | |
532ac7d7 XL |
404 | fn as_u64x4(self) -> crate::core_arch::simd::u64x4 { |
405 | unsafe { transmute(self.as_m256i()) } | |
0531ce1d XL |
406 | } |
407 | ||
408 | #[inline] | |
532ac7d7 XL |
409 | fn as_i8x32(self) -> crate::core_arch::simd::i8x32 { |
410 | unsafe { transmute(self.as_m256i()) } | |
0531ce1d XL |
411 | } |
412 | ||
413 | #[inline] | |
532ac7d7 XL |
414 | fn as_i16x16(self) -> crate::core_arch::simd::i16x16 { |
415 | unsafe { transmute(self.as_m256i()) } | |
0531ce1d XL |
416 | } |
417 | ||
418 | #[inline] | |
532ac7d7 XL |
419 | fn as_i32x8(self) -> crate::core_arch::simd::i32x8 { |
420 | unsafe { transmute(self.as_m256i()) } | |
0531ce1d XL |
421 | } |
422 | ||
423 | #[inline] | |
532ac7d7 XL |
424 | fn as_i64x4(self) -> crate::core_arch::simd::i64x4 { |
425 | unsafe { transmute(self.as_m256i()) } | |
0531ce1d XL |
426 | } |
427 | } | |
428 | ||
429 | impl m256iExt for __m256i { | |
430 | #[inline] | |
431 | fn as_m256i(self) -> Self { | |
432 | self | |
433 | } | |
434 | } | |
435 | ||
29967ef6 XL |
436 | #[allow(non_camel_case_types)] |
437 | #[unstable(feature = "stdimd_internal", issue = "none")] | |
438 | pub(crate) trait m128Ext: Sized { | |
439 | fn as_m128(self) -> __m128; | |
440 | ||
441 | #[inline] | |
442 | fn as_f32x4(self) -> crate::core_arch::simd::f32x4 { | |
443 | unsafe { transmute(self.as_m128()) } | |
444 | } | |
445 | } | |
446 | ||
447 | impl m128Ext for __m128 { | |
448 | #[inline] | |
449 | fn as_m128(self) -> Self { | |
450 | self | |
451 | } | |
452 | } | |
453 | ||
3dfed10e | 454 | #[allow(non_camel_case_types)] |
1b1a35ee | 455 | #[unstable(feature = "stdsimd_internal", issue = "none")] |
3dfed10e XL |
456 | pub(crate) trait m256Ext: Sized { |
457 | fn as_m256(self) -> __m256; | |
458 | ||
459 | #[inline] | |
460 | fn as_f32x8(self) -> crate::core_arch::simd::f32x8 { | |
461 | unsafe { transmute(self.as_m256()) } | |
462 | } | |
463 | } | |
464 | ||
465 | impl m256Ext for __m256 { | |
466 | #[inline] | |
467 | fn as_m256(self) -> Self { | |
468 | self | |
469 | } | |
470 | } | |
471 | ||
0731742a | 472 | #[allow(non_camel_case_types)] |
1b1a35ee | 473 | #[unstable(feature = "stdsimd_internal", issue = "none")] |
0731742a XL |
474 | pub(crate) trait m512iExt: Sized { |
475 | fn as_m512i(self) -> __m512i; | |
476 | ||
3dfed10e XL |
477 | #[inline] |
478 | fn as_u32x16(self) -> crate::core_arch::simd::u32x16 { | |
479 | unsafe { transmute(self.as_m512i()) } | |
480 | } | |
481 | ||
0731742a | 482 | #[inline] |
532ac7d7 XL |
483 | fn as_i32x16(self) -> crate::core_arch::simd::i32x16 { |
484 | unsafe { transmute(self.as_m512i()) } | |
0731742a | 485 | } |
f9f354fc XL |
486 | |
487 | #[inline] | |
488 | fn as_u64x8(self) -> crate::core_arch::simd::u64x8 { | |
489 | unsafe { transmute(self.as_m512i()) } | |
490 | } | |
491 | ||
492 | #[inline] | |
493 | fn as_i64x8(self) -> crate::core_arch::simd::i64x8 { | |
494 | unsafe { transmute(self.as_m512i()) } | |
495 | } | |
0731742a XL |
496 | } |
497 | ||
498 | impl m512iExt for __m512i { | |
499 | #[inline] | |
500 | fn as_m512i(self) -> Self { | |
501 | self | |
502 | } | |
503 | } | |
504 | ||
3dfed10e | 505 | #[allow(non_camel_case_types)] |
1b1a35ee | 506 | #[unstable(feature = "stdsimd_internal", issue = "none")] |
3dfed10e XL |
507 | pub(crate) trait m512Ext: Sized { |
508 | fn as_m512(self) -> __m512; | |
509 | ||
510 | #[inline] | |
511 | fn as_f32x16(self) -> crate::core_arch::simd::f32x16 { | |
512 | unsafe { transmute(self.as_m512()) } | |
513 | } | |
514 | } | |
515 | ||
516 | impl m512Ext for __m512 { | |
517 | #[inline] | |
518 | fn as_m512(self) -> Self { | |
519 | self | |
520 | } | |
521 | } | |
522 | ||
523 | #[allow(non_camel_case_types)] | |
1b1a35ee | 524 | #[unstable(feature = "stdsimd_internal", issue = "none")] |
3dfed10e XL |
525 | pub(crate) trait m512dExt: Sized { |
526 | fn as_m512d(self) -> __m512d; | |
527 | ||
528 | #[inline] | |
529 | fn as_f64x8(self) -> crate::core_arch::simd::f64x8 { | |
530 | unsafe { transmute(self.as_m512d()) } | |
531 | } | |
532 | } | |
533 | ||
534 | impl m512dExt for __m512d { | |
535 | #[inline] | |
536 | fn as_m512d(self) -> Self { | |
537 | self | |
538 | } | |
539 | } | |
540 | ||
0531ce1d XL |
541 | mod eflags; |
542 | pub use self::eflags::*; | |
543 | ||
0531ce1d | 544 | mod fxsr; |
0531ce1d XL |
545 | pub use self::fxsr::*; |
546 | ||
547 | mod bswap; | |
548 | pub use self::bswap::*; | |
549 | ||
550 | mod rdtsc; | |
551 | pub use self::rdtsc::*; | |
552 | ||
553 | mod cpuid; | |
554 | pub use self::cpuid::*; | |
555 | mod xsave; | |
556 | pub use self::xsave::*; | |
557 | ||
558 | mod sse; | |
559 | pub use self::sse::*; | |
560 | mod sse2; | |
561 | pub use self::sse2::*; | |
562 | mod sse3; | |
563 | pub use self::sse3::*; | |
564 | mod ssse3; | |
565 | pub use self::ssse3::*; | |
566 | mod sse41; | |
567 | pub use self::sse41::*; | |
568 | mod sse42; | |
569 | pub use self::sse42::*; | |
570 | mod avx; | |
571 | pub use self::avx::*; | |
572 | mod avx2; | |
573 | pub use self::avx2::*; | |
83c7162d XL |
574 | mod fma; |
575 | pub use self::fma::*; | |
0531ce1d XL |
576 | |
577 | mod abm; | |
578 | pub use self::abm::*; | |
83c7162d XL |
579 | mod bmi1; |
580 | pub use self::bmi1::*; | |
0531ce1d XL |
581 | |
582 | mod bmi2; | |
583 | pub use self::bmi2::*; | |
584 | ||
416331ca | 585 | #[cfg(not(stdarch_intel_sde))] |
0531ce1d | 586 | mod sse4a; |
416331ca | 587 | #[cfg(not(stdarch_intel_sde))] |
0531ce1d XL |
588 | pub use self::sse4a::*; |
589 | ||
416331ca | 590 | #[cfg(not(stdarch_intel_sde))] |
0531ce1d | 591 | mod tbm; |
416331ca | 592 | #[cfg(not(stdarch_intel_sde))] |
0531ce1d XL |
593 | pub use self::tbm::*; |
594 | ||
0531ce1d XL |
595 | mod pclmulqdq; |
596 | pub use self::pclmulqdq::*; | |
597 | ||
598 | mod aes; | |
599 | pub use self::aes::*; | |
600 | ||
601 | mod rdrand; | |
602 | pub use self::rdrand::*; | |
83c7162d XL |
603 | |
604 | mod sha; | |
605 | pub use self::sha::*; | |
0731742a XL |
606 | |
607 | mod adx; | |
608 | pub use self::adx::*; | |
609 | ||
610 | #[cfg(test)] | |
416331ca | 611 | use stdarch_test::assert_instr; |
0731742a XL |
612 | |
613 | /// Generates the trap instruction `UD2` | |
614 | #[cfg_attr(test, assert_instr(ud2))] | |
615 | #[inline] | |
616 | pub unsafe fn ud2() -> ! { | |
532ac7d7 | 617 | intrinsics::abort() |
0731742a XL |
618 | } |
619 | ||
620 | mod avx512f; | |
621 | pub use self::avx512f::*; | |
9fa01778 XL |
622 | |
623 | mod avx512ifma; | |
624 | pub use self::avx512ifma::*; | |
532ac7d7 XL |
625 | |
626 | mod bt; | |
627 | pub use self::bt::*; | |
416331ca XL |
628 | |
629 | mod rtm; | |
630 | pub use self::rtm::*; | |
631 | ||
632 | mod f16c; | |
633 | pub use self::f16c::*; |