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1 | //! Advanced Vector Extensions (AVX) |
2 | //! | |
3 | //! The references are: | |
4 | //! | |
5 | //! - [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2: | |
6 | //! Instruction Set Reference, A-Z][intel64_ref]. - [AMD64 Architecture | |
7 | //! Programmer's Manual, Volume 3: General-Purpose and System | |
8 | //! Instructions][amd64_ref]. | |
9 | //! | |
10 | //! [Wikipedia][wiki] provides a quick overview of the instructions available. | |
11 | //! | |
12 | //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf | |
13 | //! [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf | |
14 | //! [wiki]: https://en.wikipedia.org/wiki/Advanced_Vector_Extensions | |
15 | ||
532ac7d7 XL |
16 | use crate::{ |
17 | core_arch::{simd_llvm::*, x86::*}, | |
18 | mem::transmute, | |
19 | }; | |
0531ce1d | 20 | |
532ac7d7 | 21 | /// Copies `a` to result, and insert the 64-bit integer `i` into result |
0531ce1d | 22 | /// at the location specified by `index`. |
83c7162d | 23 | /// |
353b0b11 | 24 | /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_insert_epi64) |
0531ce1d | 25 | #[inline] |
17df50a5 | 26 | #[rustc_legacy_const_generics(2)] |
0531ce1d XL |
27 | #[target_feature(enable = "avx")] |
28 | // This intrinsic has no corresponding instruction. | |
83c7162d | 29 | #[stable(feature = "simd_x86", since = "1.27.0")] |
17df50a5 | 30 | pub unsafe fn _mm256_insert_epi64<const INDEX: i32>(a: __m256i, i: i64) -> __m256i { |
353b0b11 | 31 | static_assert_uimm_bits!(INDEX, 2); |
17df50a5 | 32 | transmute(simd_insert(a.as_i64x4(), INDEX as u32, i)) |
0531ce1d XL |
33 | } |
34 | ||
35 | #[cfg(test)] | |
36 | mod tests { | |
416331ca | 37 | use stdarch_test::simd_test; |
0531ce1d | 38 | |
532ac7d7 | 39 | use crate::core_arch::x86::*; |
0531ce1d | 40 | |
83c7162d | 41 | #[simd_test(enable = "avx")] |
0531ce1d XL |
42 | unsafe fn test_mm256_insert_epi64() { |
43 | let a = _mm256_setr_epi64x(1, 2, 3, 4); | |
17df50a5 | 44 | let r = _mm256_insert_epi64::<3>(a, 0); |
0531ce1d XL |
45 | let e = _mm256_setr_epi64x(1, 2, 3, 0); |
46 | assert_eq_m256i(r, e); | |
47 | } | |
48 | } |