[rustc.git] / library / stdarch / crates / std_detect / src / detect / arch / riscv.rs

//! Run-time feature detection on RISC-V.

features! {
    @TARGET: riscv;
    @CFG: any(target_arch = "riscv32", target_arch = "riscv64");
    @MACRO_NAME: is_riscv_feature_detected;
    @MACRO_ATTRS:
    /// A macro to test at *runtime* whether instruction sets are available on
    /// RISC-V platforms.
    ///
    /// RISC-V standard defined the base sets and the extension sets.
    /// The base sets are RV32I, RV64I, RV32E or RV128I. Any RISC-V platform
    /// must support one base set and/or multiple extension sets.
    ///
    /// Any RISC-V standard instruction sets can be in state of either ratified,
    /// frozen or draft. The version and status of current standard instruction
    /// sets can be checked out from preface section of the [ISA manual].
    ///
    /// Platform may define and support their own custom instruction sets with
    /// ISA prefix X. These sets are highly platform specific and should be
    /// detected with their own platform support crates.
    ///
    /// # Unprivileged Specification
    ///
    /// The supported ratified RISC-V instruction sets are as follows:
    ///
    /// * RV32I: `"rv32i"`
    /// * Zifencei: `"zifencei"`
    /// * Zihintpause: `"zihintpause"`
    /// * RV64I: `"rv64i"`
    /// * M: `"m"`
    /// * A: `"a"`
    /// * Zicsr: `"zicsr"`
    /// * Zicntr: `"zicntr"`
    /// * Zihpm: `"zihpm"`
    /// * F: `"f"`
    /// * D: `"d"`
    /// * Q: `"q"`
    /// * C: `"c"`
    ///
    /// There's also bases and extensions marked as standard instruction set,
    /// but they are in frozen or draft state. These instruction sets are also
    /// reserved by this macro and can be detected in the future platforms.
    ///
    /// Frozen RISC-V instruction sets:
    ///
    /// * Zfinx: `"zfinx"`
    /// * Zdinx: `"zdinx"`
    /// * Zhinx: `"zhinx"`
    /// * Zhinxmin: `"zhinxmin"`
    /// * Ztso: `"ztso"`
    ///
    /// Draft RISC-V instruction sets:
    ///
    /// * RV32E: `"rv32e"`
    /// * RV128I: `"rv128i"`
    /// * Zfh: `"zfh"`
    /// * Zfhmin: `"zfhmin"`
    /// * B: `"b"`
    /// * J: `"j"`
    /// * P: `"p"`
    /// * V: `"v"`
    /// * Zam: `"zam"`
    ///
    /// Defined by Privileged Specification:
    ///
    /// * Supervisor: `"s"`
    /// * Svnapot: `"svnapot"`
    /// * Svpbmt: `"svpbmt"`
    /// * Svinval: `"svinval"`
    /// * Hypervisor: `"h"`
    ///
    /// # RISC-V Bit-Manipulation ISA-extensions
    ///
    /// This document defined the following extensions:
    ///
    /// * Zba: `"zba"`
    /// * Zbb: `"zbb"`
    /// * Zbc: `"zbc"`
    /// * Zbs: `"zbs"`
    ///
    /// # RISC-V Cryptography Extensions
    ///
    /// These extensions are defined in Volume I, Scalar & Entropy Source
    /// Instructions:
    ///
    /// * Zbkb: `"zbkb"`
    /// * Zbkc: `"zbkc"`
    /// * Zbkx: `"zbkx"`
    /// * Zknd: `"zknd"`
    /// * Zkne: `"zkne"`
    /// * Zknh: `"zknh"`
    /// * Zksed: `"zksed"`
    /// * Zksh: `"zksh"`
    /// * Zkr: `"zkr"`
    /// * Zkn: `"zkn"`
    /// * Zks: `"zks"`
    /// * Zk: `"zk"`
    /// * Zkt: `"zkt"`
    ///
    /// [ISA manual]: https://github.com/riscv/riscv-isa-manual/
    #[unstable(feature = "stdsimd", issue = "27731")]
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv32i: "rv32i";
    /// RV32I Base Integer Instruction Set
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zifencei: "zifencei";
    /// "Zifencei" Instruction-Fetch Fence
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zihintpause: "zihintpause";
    /// "Zihintpause" Pause Hint
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv64i: "rv64i";
    /// RV64I Base Integer Instruction Set
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] m: "m";
    /// "M" Standard Extension for Integer Multiplication and Division
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] a: "a";
    /// "A" Standard Extension for Atomic Instructions
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zicsr: "zicsr";
    /// "Zicsr", Control and Status Register (CSR) Instructions
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zicntr: "zicntr";
    /// "Zicntr", Standard Extension for Base Counters and Timers
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zihpm: "zihpm";
    /// "Zihpm", Standard Extension for Hardware Performance Counters
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] f: "f";
    /// "F" Standard Extension for Single-Precision Floating-Point
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] d: "d";
    /// "D" Standard Extension for Double-Precision Floating-Point
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] q: "q";
    /// "Q" Standard Extension for Quad-Precision Floating-Point
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] c: "c";
    /// "C" Standard Extension for Compressed Instructions

    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zfinx: "zfinx";
    /// "Zfinx" Standard Extension for Single-Precision Floating-Point in Integer Registers
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zdinx: "zdinx";
    /// "Zdinx" Standard Extension for Double-Precision Floating-Point in Integer Registers
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zhinx: "zhinx";
    /// "Zhinx" Standard Extension for Half-Precision Floating-Point in Integer Registers
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zhinxmin: "zhinxmin";
    /// "Zhinxmin" Standard Extension for Minimal Half-Precision Floating-Point in Integer Registers
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] ztso: "ztso";
    /// "Ztso" Standard Extension for Total Store Ordering

    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv32e: "rv32e";
    /// RV32E Base Integer Instruction Set
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv128i: "rv128i";
    /// RV128I Base Integer Instruction Set
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zfh: "zfh";
    /// "Zfh" Standard Extension for 16-Bit Half-Precision Floating-Point
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zfhmin: "zfhmin";
    /// "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point Support
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] b: "b";
    /// "B" Standard Extension for Bit Manipulation
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] j: "j";
    /// "J" Standard Extension for Dynamically Translated Languages
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] p: "p";
    /// "P" Standard Extension for Packed-SIMD Instructions
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] v: "v";
    /// "V" Standard Extension for Vector Operations
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zam: "zam";
    /// "Zam" Standard Extension for Misaligned Atomics

    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] s: "s";
    /// Supervisor-Level ISA
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] svnapot: "svnapot";
    /// "Svnapot" Standard Extension for NAPOT Translation Contiguity
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] svpbmt: "svpbmt";
    /// "Svpbmt" Standard Extension for Page-Based Memory Types
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] svinval: "svinval";
    /// "Svinval" Standard Extension for Fine-Grained Address-Translation Cache Invalidation
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] h: "h";
    /// Hypervisor Extension

    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zba: "zba";
    /// "Zba" Standard Extension for Address Generation Instructions
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbb: "zbb";
    /// "Zbb" Standard Extension for Basic Bit-Manipulation
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbc: "zbc";
    /// "Zbc" Standard Extension for Carry-less Multiplication
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbs: "zbs";
    /// "Zbs" Standard Extension for Single-Bit instructions

    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbkb: "zbkb";
    /// "Zbkb" Standard Extension for Bitmanip instructions for Cryptography
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbkc: "zbkc";
    /// "Zbkc" Standard Extension for Carry-less multiply instructions
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbkx: "zbkx";
    /// "Zbkx" Standard Extension for Crossbar permutation instructions
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zknd: "zknd";
    /// "Zknd" Standard Extension for NIST Suite: AES Decryption
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkne: "zkne";
    /// "Zkne" Standard Extension for NIST Suite: AES Encryption
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zknh: "zknh";
    /// "Zknh" Standard Extension for NIST Suite: Hash Function Instructions
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zksed: "zksed";
    /// "Zksed" Standard Extension for ShangMi Suite: SM4 Block Cipher Instructions
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zksh: "zksh";
    /// "Zksh" Standard Extension for ShangMi Suite: SM3 Hash Function Instructions
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkr: "zkr";
    /// "Zkr" Standard Extension for Entropy Source Extension
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkn: "zkn";
    /// "Zkn" Standard Extension for NIST Algorithm Suite
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zks: "zks";
    /// "Zks" Standard Extension for ShangMi Algorithm Suite
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zk: "zk";
    /// "Zk" Standard Extension for Standard scalar cryptography extension
    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkt: "zkt";
    /// "Zkt" Standard Extension for Data Independent Execution Latency
}
Commit	Line	Data
a2a8927a XL	1	//! Run-time feature detection on RISC-V.
	2
	3	features! {
	4	@TARGET: riscv;
5099ac24	5	@CFG: any(target_arch = "riscv32", target_arch = "riscv64");
a2a8927a XL	6	@MACRO_NAME: is_riscv_feature_detected;
	7	@MACRO_ATTRS:
	8	/// A macro to test at runtime whether instruction sets are available on
	9	/// RISC-V platforms.
	10	///
	11	/// RISC-V standard defined the base sets and the extension sets.
	12	/// The base sets are RV32I, RV64I, RV32E or RV128I. Any RISC-V platform
	13	/// must support one base set and/or multiple extension sets.
	14	///
	15	/// Any RISC-V standard instruction sets can be in state of either ratified,
	16	/// frozen or draft. The version and status of current standard instruction
	17	/// sets can be checked out from preface section of the [ISA manual].
	18	///
	19	/// Platform may define and support their own custom instruction sets with
	20	/// ISA prefix X. These sets are highly platform specific and should be
	21	/// detected with their own platform support crates.
	22	///
	23	/// # Unprivileged Specification
	24	///
	25	/// The supported ratified RISC-V instruction sets are as follows:
	26	///
	27	/// * RV32I: `"rv32i"`
	28	/// * Zifencei: `"zifencei"`
	29	/// * Zihintpause: `"zihintpause"`
	30	/// * RV64I: `"rv64i"`
	31	/// * M: `"m"`
	32	/// * A: `"a"`
	33	/// * Zicsr: `"zicsr"`
	34	/// * Zicntr: `"zicntr"`
	35	/// * Zihpm: `"zihpm"`
	36	/// * F: `"f"`
	37	/// * D: `"d"`
	38	/// * Q: `"q"`
	39	/// * C: `"c"`
	40	///
	41	/// There's also bases and extensions marked as standard instruction set,
	42	/// but they are in frozen or draft state. These instruction sets are also
	43	/// reserved by this macro and can be detected in the future platforms.
	44	///
	45	/// Frozen RISC-V instruction sets:
	46	///
	47	/// * Zfinx: `"zfinx"`
	48	/// * Zdinx: `"zdinx"`
	49	/// * Zhinx: `"zhinx"`
	50	/// * Zhinxmin: `"zhinxmin"`
	51	/// * Ztso: `"ztso"`
	52	///
	53	/// Draft RISC-V instruction sets:
	54	///
	55	/// * RV32E: `"rv32e"`
	56	/// * RV128I: `"rv128i"`
	57	/// * Zfh: `"zfh"`
	58	/// * Zfhmin: `"zfhmin"`
	59	/// * B: `"b"`
	60	/// * J: `"j"`
	61	/// * P: `"p"`
	62	/// * V: `"v"`
	63	/// * Zam: `"zam"`
	64	///
	65	/// Defined by Privileged Specification:
	66	///
	67	/// * Supervisor: `"s"`
	68	/// * Svnapot: `"svnapot"`
	69	/// * Svpbmt: `"svpbmt"`
70	/// * Svinval: `"svinval"`
71	/// * Hypervisor: `"h"`
72	///
73	/// # RISC-V Bit-Manipulation ISA-extensions
74	///
75	/// This document defined the following extensions:
76	///
77	/// * Zba: `"zba"`
78	/// * Zbb: `"zbb"`
79	/// * Zbc: `"zbc"`
80	/// * Zbs: `"zbs"`
81	///
82	/// # RISC-V Cryptography Extensions
83	///
84	/// These extensions are defined in Volume I, Scalar & Entropy Source
85	/// Instructions:
86	///
87	/// * Zbkb: `"zbkb"`
88	/// * Zbkc: `"zbkc"`
89	/// * Zbkx: `"zbkx"`
90	/// * Zknd: `"zknd"`
91	/// * Zkne: `"zkne"`
92	/// * Zknh: `"zknh"`
93	/// * Zksed: `"zksed"`
94	/// * Zksh: `"zksh"`
95	/// * Zkr: `"zkr"`
96	/// * Zkn: `"zkn"`
97	/// * Zks: `"zks"`
98	/// * Zk: `"zk"`
99	/// * Zkt: `"zkt"`
100	///
101	/// [ISA manual]: https://github.com/riscv/riscv-isa-manual/
102	#[unstable(feature = "stdsimd", issue = "27731")]
103	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv32i: "rv32i";
104	/// RV32I Base Integer Instruction Set
105	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zifencei: "zifencei";
106	/// "Zifencei" Instruction-Fetch Fence
107	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zihintpause: "zihintpause";
108	/// "Zihintpause" Pause Hint
109	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv64i: "rv64i";
110	/// RV64I Base Integer Instruction Set
111	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] m: "m";
112	/// "M" Standard Extension for Integer Multiplication and Division
113	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] a: "a";
114	/// "A" Standard Extension for Atomic Instructions
115	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zicsr: "zicsr";
116	/// "Zicsr", Control and Status Register (CSR) Instructions
117	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zicntr: "zicntr";
118	/// "Zicntr", Standard Extension for Base Counters and Timers
119	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zihpm: "zihpm";
120	/// "Zihpm", Standard Extension for Hardware Performance Counters
121	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] f: "f";
122	/// "F" Standard Extension for Single-Precision Floating-Point
123	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] d: "d";
124	/// "D" Standard Extension for Double-Precision Floating-Point
125	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] q: "q";
126	/// "Q" Standard Extension for Quad-Precision Floating-Point
127	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] c: "c";
128	/// "C" Standard Extension for Compressed Instructions
129
130	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zfinx: "zfinx";
131	/// "Zfinx" Standard Extension for Single-Precision Floating-Point in Integer Registers
132	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zdinx: "zdinx";
133	/// "Zdinx" Standard Extension for Double-Precision Floating-Point in Integer Registers
134	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zhinx: "zhinx";
135	/// "Zhinx" Standard Extension for Half-Precision Floating-Point in Integer Registers
136	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zhinxmin: "zhinxmin";
137	/// "Zhinxmin" Standard Extension for Minimal Half-Precision Floating-Point in Integer Registers
138	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] ztso: "ztso";
139	/// "Ztso" Standard Extension for Total Store Ordering
140
141	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv32e: "rv32e";
142	/// RV32E Base Integer Instruction Set
143	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv128i: "rv128i";
144	/// RV128I Base Integer Instruction Set
145	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zfh: "zfh";
146	/// "Zfh" Standard Extension for 16-Bit Half-Precision Floating-Point
147	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zfhmin: "zfhmin";
148	/// "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point Support
149	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] b: "b";
150	/// "B" Standard Extension for Bit Manipulation
151	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] j: "j";
152	/// "J" Standard Extension for Dynamically Translated Languages
153	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] p: "p";
154	/// "P" Standard Extension for Packed-SIMD Instructions
155	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] v: "v";
156	/// "V" Standard Extension for Vector Operations
157	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zam: "zam";
158	/// "Zam" Standard Extension for Misaligned Atomics
159
160	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] s: "s";
161	/// Supervisor-Level ISA
162	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] svnapot: "svnapot";
163	/// "Svnapot" Standard Extension for NAPOT Translation Contiguity
164	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] svpbmt: "svpbmt";
165	/// "Svpbmt" Standard Extension for Page-Based Memory Types
166	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] svinval: "svinval";
167	/// "Svinval" Standard Extension for Fine-Grained Address-Translation Cache Invalidation
168	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] h: "h";
169	/// Hypervisor Extension
170
171	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zba: "zba";
172	/// "Zba" Standard Extension for Address Generation Instructions
173	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbb: "zbb";
174	/// "Zbb" Standard Extension for Basic Bit-Manipulation
175	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbc: "zbc";
176	/// "Zbc" Standard Extension for Carry-less Multiplication
177	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbs: "zbs";
178	/// "Zbs" Standard Extension for Single-Bit instructions
179
180	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbkb: "zbkb";
181	/// "Zbkb" Standard Extension for Bitmanip instructions for Cryptography
182	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbkc: "zbkc";
183	/// "Zbkc" Standard Extension for Carry-less multiply instructions
184	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbkx: "zbkx";
185	/// "Zbkx" Standard Extension for Crossbar permutation instructions
186	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zknd: "zknd";
187	/// "Zknd" Standard Extension for NIST Suite: AES Decryption
188	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkne: "zkne";
189	/// "Zkne" Standard Extension for NIST Suite: AES Encryption
190	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zknh: "zknh";
191	/// "Zknh" Standard Extension for NIST Suite: Hash Function Instructions
192	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zksed: "zksed";
193	/// "Zksed" Standard Extension for ShangMi Suite: SM4 Block Cipher Instructions
194	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zksh: "zksh";
195	/// "Zksh" Standard Extension for ShangMi Suite: SM3 Hash Function Instructions
196	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkr: "zkr";
197	/// "Zkr" Standard Extension for Entropy Source Extension
198	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkn: "zkn";
199	/// "Zkn" Standard Extension for NIST Algorithm Suite
200	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zks: "zks";
201	/// "Zks" Standard Extension for ShangMi Algorithm Suite
202	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zk: "zk";
203	/// "Zk" Standard Extension for Standard scalar cryptography extension
204	@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkt: "zkt";
205	/// "Zkt" Standard Extension for Data Independent Execution Latency
206	}