]>
Commit | Line | Data |
---|---|---|
2c0262af FB |
1 | |
2 | /* this struct defines the way the registers are stored on the | |
3 | stack during a system call. */ | |
4 | ||
5 | struct target_pt_regs { | |
992f48a0 | 6 | abi_long uregs[18]; |
2c0262af FB |
7 | }; |
8 | ||
9 | #define ARM_cpsr uregs[16] | |
10 | #define ARM_pc uregs[15] | |
11 | #define ARM_lr uregs[14] | |
12 | #define ARM_sp uregs[13] | |
13 | #define ARM_ip uregs[12] | |
14 | #define ARM_fp uregs[11] | |
15 | #define ARM_r10 uregs[10] | |
16 | #define ARM_r9 uregs[9] | |
17 | #define ARM_r8 uregs[8] | |
18 | #define ARM_r7 uregs[7] | |
19 | #define ARM_r6 uregs[6] | |
20 | #define ARM_r5 uregs[5] | |
21 | #define ARM_r4 uregs[4] | |
22 | #define ARM_r3 uregs[3] | |
23 | #define ARM_r2 uregs[2] | |
24 | #define ARM_r1 uregs[1] | |
25 | #define ARM_r0 uregs[0] | |
26 | #define ARM_ORIG_r0 uregs[17] | |
27 | ||
28 | #define ARM_SYSCALL_BASE 0x900000 | |
192c7bd9 | 29 | #define ARM_THUMB_SYSCALL 0 |
6f1f31c0 | 30 | |
fbb4a2e3 | 31 | #define ARM_NR_BASE 0xf0000 |
d5355087 | 32 | #define ARM_NR_breakpoint (ARM_NR_BASE + 1) |
fbb4a2e3 PB |
33 | #define ARM_NR_cacheflush (ARM_NR_BASE + 2) |
34 | #define ARM_NR_set_tls (ARM_NR_BASE + 5) | |
cf720db3 | 35 | |
a4f81979 FB |
36 | #define ARM_NR_semihosting 0x123456 |
37 | #define ARM_NR_thumb_semihosting 0xAB | |
38 | ||
cf720db3 | 39 | #if defined(TARGET_WORDS_BIGENDIAN) |
99c475ab | 40 | #define UNAME_MACHINE "armv5teb" |
cf720db3 | 41 | #else |
99c475ab | 42 | #define UNAME_MACHINE "armv5tel" |
cf720db3 | 43 | #endif |
cbc14e6f | 44 | #define UNAME_MINIMUM_RELEASE "2.6.32" |
4ce6243d PM |
45 | |
46 | #define TARGET_CLONE_BACKWARDS | |
0903c8be TM |
47 | |
48 | #define TARGET_MINSIGSTKSZ 2048 | |
6f6a4032 TM |
49 | #define TARGET_MLOCKALL_MCL_CURRENT 1 |
50 | #define TARGET_MLOCKALL_MCL_FUTURE 2 |