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virtio-net: correctly drop truncated packets
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31e31b8a 1/*
93ac68bc 2 * qemu user main
5fafdf24 3 *
68d0f70e 4 * Copyright (c) 2003-2008 Fabrice Bellard
31e31b8a
FB		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
8167ee88 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31e31b8a
FB		 18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <stdarg.h>
04369ff2 22#include <string.h>
31e31b8a 23#include <errno.h>
0ecfa993 24#include <unistd.h>
e441570f 25#include <sys/mman.h>
edf8e2af 26#include <sys/syscall.h>
703e0e89 27#include <sys/resource.h>
31e31b8a 28
3ef693a0 29#include "qemu.h"
ca10f867 30#include "qemu-common.h"
2b41f10e 31#include "cpu.h"
9002ec79 32#include "tcg.h"
1de7afc9
PB		 33#include "qemu/timer.h"
34#include "qemu/envlist.h"
d8fd2954 35#include "elf.h"
04a6dfeb 36
d088d664
AJ		 37char *exec_path;
38
1b530a6d 39int singlestep;
8cb76755
SW		 40static const char *filename;
41static const char *argv0;
42static int gdbstub_port;
43static envlist_t *envlist;
51fb256a 44static const char *cpu_model;
379f6698
PB		 45unsigned long mmap_min_addr;
46unsigned long guest_base;
47int have_guest_base;
288e65b9
AG		 48#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
49/*
50 * When running 32-on-64 we should make sure we can fit all of the possible
51 * guest address space into a contiguous chunk of virtual host memory.
52 *
53 * This way we will never overlap with our own libraries or binaries or stack
54 * or anything else that QEMU maps.
55 */
314992b1
AG		 56# ifdef TARGET_MIPS
57/* MIPS only supports 31 bits of virtual address space for user space */
58unsigned long reserved_va = 0x77000000;
59# else
288e65b9 60unsigned long reserved_va = 0xf7000000;
314992b1 61# endif
288e65b9 62#else
68a1c816 63unsigned long reserved_va;
379f6698 64#endif
1b530a6d 65
fc9c5412
JS		 66static void usage(void);
67
7ee2822c 68static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
e586822a 69const char *qemu_uname_release;
586314f2 70
9de5e440
FB		 71/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
72 we allocate a bigger stack. Need a better solution, for example
73 by remapping the process stack directly at the right place */
703e0e89 74unsigned long guest_stack_size = 8 * 1024 * 1024UL;
31e31b8a
FB		 75
76void gemu_log(const char *fmt, ...)
77{
78 va_list ap;
79
80 va_start(ap, fmt);
81 vfprintf(stderr, fmt, ap);
82 va_end(ap);
83}
84
8fcd3692 85#if defined(TARGET_I386)
05390248 86int cpu_get_pic_interrupt(CPUX86State *env)
92ccca6a
FB		 87{
88 return -1;
89}
8fcd3692 90#endif
92ccca6a 91
d5975363
PB		 92/***********************************************************/
93/* Helper routines for implementing atomic operations. */
94
95/* To implement exclusive operations we force all cpus to syncronise.
96 We don't require a full sync, only that no cpus are executing guest code.
97 The alternative is to map target atomic ops onto host equivalents,
98 which requires quite a lot of per host/target work. */
c2764719 99static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
d5975363
PB		 100static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
101static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
102static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
103static int pending_cpus;
104
105/* Make sure everything is in a consistent state for calling fork(). */
106void fork_start(void)
107{
677ef623 108 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 109 pthread_mutex_lock(&exclusive_lock);
d032d1b4 110 mmap_fork_start();
d5975363
PB		 111}
112
113void fork_end(int child)
114{
d032d1b4 115 mmap_fork_end(child);
d5975363 116 if (child) {
bdc44640 117 CPUState *cpu, *next_cpu;
d5975363
PB		 118 /* Child processes created by fork() only have a single thread.
119 Discard information about the parent threads. */
bdc44640
AF		 120 CPU_FOREACH_SAFE(cpu, next_cpu) {
121 if (cpu != thread_cpu) {
122 QTAILQ_REMOVE(&cpus, thread_cpu, node);
123 }
124 }
d5975363
PB		 125 pending_cpus = 0;
126 pthread_mutex_init(&exclusive_lock, NULL);
c2764719 127 pthread_mutex_init(&cpu_list_mutex, NULL);
d5975363
PB		 128 pthread_cond_init(&exclusive_cond, NULL);
129 pthread_cond_init(&exclusive_resume, NULL);
677ef623 130 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
f7ec7f7b 131 gdbserver_fork(thread_cpu);
d5975363
PB		 132 } else {
133 pthread_mutex_unlock(&exclusive_lock);
677ef623 134 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 135 }
d5975363
PB		 136}
137
138/* Wait for pending exclusive operations to complete. The exclusive lock
139 must be held. */
140static inline void exclusive_idle(void)
141{
142 while (pending_cpus) {
143 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
144 }
145}
146
147/* Start an exclusive operation.
148 Must only be called from outside cpu_arm_exec. */
149static inline void start_exclusive(void)
150{
0315c31c
AF		 151 CPUState *other_cpu;
152
d5975363
PB		 153 pthread_mutex_lock(&exclusive_lock);
154 exclusive_idle();
155
156 pending_cpus = 1;
157 /* Make all other cpus stop executing. */
bdc44640 158 CPU_FOREACH(other_cpu) {
0315c31c 159 if (other_cpu->running) {
d5975363 160 pending_cpus++;
60a3e17a 161 cpu_exit(other_cpu);
d5975363
PB		 162 }
163 }
164 if (pending_cpus > 1) {
165 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
166 }
167}
168
169/* Finish an exclusive operation. */
f7e61b22 170static inline void __attribute__((unused)) end_exclusive(void)
d5975363
PB		 171{
172 pending_cpus = 0;
173 pthread_cond_broadcast(&exclusive_resume);
174 pthread_mutex_unlock(&exclusive_lock);
175}
176
177/* Wait for exclusive ops to finish, and begin cpu execution. */
0315c31c 178static inline void cpu_exec_start(CPUState *cpu)
d5975363
PB		 179{
180 pthread_mutex_lock(&exclusive_lock);
181 exclusive_idle();
0315c31c 182 cpu->running = true;
d5975363
PB		 183 pthread_mutex_unlock(&exclusive_lock);
184}
185
186/* Mark cpu as not executing, and release pending exclusive ops. */
0315c31c 187static inline void cpu_exec_end(CPUState *cpu)
d5975363
PB		 188{
189 pthread_mutex_lock(&exclusive_lock);
0315c31c 190 cpu->running = false;
d5975363
PB		 191 if (pending_cpus > 1) {
192 pending_cpus--;
193 if (pending_cpus == 1) {
194 pthread_cond_signal(&exclusive_cond);
195 }
196 }
197 exclusive_idle();
198 pthread_mutex_unlock(&exclusive_lock);
199}
c2764719
PB		 200
201void cpu_list_lock(void)
202{
203 pthread_mutex_lock(&cpu_list_mutex);
204}
205
206void cpu_list_unlock(void)
207{
208 pthread_mutex_unlock(&cpu_list_mutex);
209}
d5975363
PB		 210
211
a541f297
FB		 212#ifdef TARGET_I386
213/***********************************************************/
214/* CPUX86 core interface */
215
28ab0e2e
FB		 216uint64_t cpu_get_tsc(CPUX86State *env)
217{
218 return cpu_get_real_ticks();
219}
220
5fafdf24 221static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
f4beb510 222 int flags)
6dbad63e 223{
f4beb510 224 unsigned int e1, e2;
53a5960a 225 uint32_t *p;
6dbad63e
FB		 226 e1 = (addr << 16) | (limit & 0xffff);
227 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
f4beb510 228 e2 |= flags;
53a5960a 229 p = ptr;
d538e8f5 230 p[0] = tswap32(e1);
231 p[1] = tswap32(e2);
f4beb510
FB		 232}
233
e441570f 234static uint64_t *idt_table;
eb38c52c 235#ifdef TARGET_X86_64
d2fd1af7
FB		 236static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
237 uint64_t addr, unsigned int sel)
f4beb510 238{
4dbc422b 239 uint32_t *p, e1, e2;
f4beb510
FB		 240 e1 = (addr & 0xffff) | (sel << 16);
241 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
53a5960a 242 p = ptr;
4dbc422b
FB		 243 p[0] = tswap32(e1);
244 p[1] = tswap32(e2);
245 p[2] = tswap32(addr >> 32);
246 p[3] = 0;
6dbad63e 247}
d2fd1af7
FB		 248/* only dpl matters as we do only user space emulation */
249static void set_idt(int n, unsigned int dpl)
250{
251 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
252}
253#else
d2fd1af7
FB		 254static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
255 uint32_t addr, unsigned int sel)
256{
4dbc422b 257 uint32_t *p, e1, e2;
d2fd1af7
FB		 258 e1 = (addr & 0xffff) | (sel << 16);
259 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
260 p = ptr;
4dbc422b
FB		 261 p[0] = tswap32(e1);
262 p[1] = tswap32(e2);
d2fd1af7
FB		 263}
264
f4beb510
FB		 265/* only dpl matters as we do only user space emulation */
266static void set_idt(int n, unsigned int dpl)
267{
268 set_gate(idt_table + n, 0, dpl, 0, 0);
269}
d2fd1af7 270#endif
31e31b8a 271
89e957e7 272void cpu_loop(CPUX86State *env)
1b6b029e 273{
db6b81d4 274 CPUState *cs = CPU(x86_env_get_cpu(env));
bc8a22cc 275 int trapnr;
992f48a0 276 abi_ulong pc;
c227f099 277 target_siginfo_t info;
851e67a1 278
1b6b029e 279 for(;;) {
b040bc9c 280 cpu_exec_start(cs);
ea3e9847 281 trapnr = cpu_x86_exec(cs);
b040bc9c 282 cpu_exec_end(cs);
bc8a22cc 283 switch(trapnr) {
f4beb510 284 case 0x80:
d2fd1af7 285 /* linux syscall from int $0x80 */
5fafdf24
TS		 286 env->regs[R_EAX] = do_syscall(env,
287 env->regs[R_EAX],
f4beb510
FB		 288 env->regs[R_EBX],
289 env->regs[R_ECX],
290 env->regs[R_EDX],
291 env->regs[R_ESI],
292 env->regs[R_EDI],
5945cfcb
PM		 293 env->regs[R_EBP],
294 0, 0);
f4beb510 295 break;
d2fd1af7
FB		 296#ifndef TARGET_ABI32
297 case EXCP_SYSCALL:
5ba18547 298 /* linux syscall from syscall instruction */
d2fd1af7
FB		 299 env->regs[R_EAX] = do_syscall(env,
300 env->regs[R_EAX],
301 env->regs[R_EDI],
302 env->regs[R_ESI],
303 env->regs[R_EDX],
304 env->regs[10],
305 env->regs[8],
5945cfcb
PM		 306 env->regs[9],
307 0, 0);
d2fd1af7
FB		 308 break;
309#endif
f4beb510
FB		 310 case EXCP0B_NOSEG:
311 case EXCP0C_STACK:
a86b3c64 312 info.si_signo = TARGET_SIGBUS;
f4beb510
FB		 313 info.si_errno = 0;
314 info.si_code = TARGET_SI_KERNEL;
315 info._sifields._sigfault._addr = 0;
624f7979 316 queue_signal(env, info.si_signo, &info);
f4beb510 317 break;
1b6b029e 318 case EXCP0D_GPF:
d2fd1af7 319 /* XXX: potential problem if ABI32 */
84409ddb 320#ifndef TARGET_X86_64
851e67a1 321 if (env->eflags & VM_MASK) {
89e957e7 322 handle_vm86_fault(env);
84409ddb
JM		 323 } else
324#endif
325 {
a86b3c64 326 info.si_signo = TARGET_SIGSEGV;
f4beb510
FB		 327 info.si_errno = 0;
328 info.si_code = TARGET_SI_KERNEL;
329 info._sifields._sigfault._addr = 0;
624f7979 330 queue_signal(env, info.si_signo, &info);
1b6b029e
FB		 331 }
332 break;
b689bc57 333 case EXCP0E_PAGE:
a86b3c64 334 info.si_signo = TARGET_SIGSEGV;
b689bc57
FB		 335 info.si_errno = 0;
336 if (!(env->error_code & 1))
337 info.si_code = TARGET_SEGV_MAPERR;
338 else
339 info.si_code = TARGET_SEGV_ACCERR;
970a87a6 340 info._sifields._sigfault._addr = env->cr[2];
624f7979 341 queue_signal(env, info.si_signo, &info);
b689bc57 342 break;
9de5e440 343 case EXCP00_DIVZ:
84409ddb 344#ifndef TARGET_X86_64
bc8a22cc 345 if (env->eflags & VM_MASK) {
447db213 346 handle_vm86_trap(env, trapnr);
84409ddb
JM		 347 } else
348#endif
349 {
bc8a22cc 350 /* division by zero */
a86b3c64 351 info.si_signo = TARGET_SIGFPE;
bc8a22cc
FB		 352 info.si_errno = 0;
353 info.si_code = TARGET_FPE_INTDIV;
354 info._sifields._sigfault._addr = env->eip;
624f7979 355 queue_signal(env, info.si_signo, &info);
bc8a22cc 356 }
9de5e440 357 break;
01df040b 358 case EXCP01_DB:
447db213 359 case EXCP03_INT3:
84409ddb 360#ifndef TARGET_X86_64
447db213
FB		 361 if (env->eflags & VM_MASK) {
362 handle_vm86_trap(env, trapnr);
84409ddb
JM		 363 } else
364#endif
365 {
a86b3c64 366 info.si_signo = TARGET_SIGTRAP;
447db213 367 info.si_errno = 0;
01df040b 368 if (trapnr == EXCP01_DB) {
447db213
FB		 369 info.si_code = TARGET_TRAP_BRKPT;
370 info._sifields._sigfault._addr = env->eip;
371 } else {
372 info.si_code = TARGET_SI_KERNEL;
373 info._sifields._sigfault._addr = 0;
374 }
624f7979 375 queue_signal(env, info.si_signo, &info);
447db213
FB		 376 }
377 break;
9de5e440
FB		 378 case EXCP04_INTO:
379 case EXCP05_BOUND:
84409ddb 380#ifndef TARGET_X86_64
bc8a22cc 381 if (env->eflags & VM_MASK) {
447db213 382 handle_vm86_trap(env, trapnr);
84409ddb
JM		 383 } else
384#endif
385 {
a86b3c64 386 info.si_signo = TARGET_SIGSEGV;
bc8a22cc 387 info.si_errno = 0;
b689bc57 388 info.si_code = TARGET_SI_KERNEL;
bc8a22cc 389 info._sifields._sigfault._addr = 0;
624f7979 390 queue_signal(env, info.si_signo, &info);
bc8a22cc 391 }
9de5e440
FB		 392 break;
393 case EXCP06_ILLOP:
a86b3c64 394 info.si_signo = TARGET_SIGILL;
9de5e440
FB		 395 info.si_errno = 0;
396 info.si_code = TARGET_ILL_ILLOPN;
397 info._sifields._sigfault._addr = env->eip;
624f7979 398 queue_signal(env, info.si_signo, &info);
9de5e440
FB		 399 break;
400 case EXCP_INTERRUPT:
401 /* just indicate that signals should be handled asap */
402 break;
1fddef4b
FB		 403 case EXCP_DEBUG:
404 {
405 int sig;
406
db6b81d4 407 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 408 if (sig)
409 {
410 info.si_signo = sig;
411 info.si_errno = 0;
412 info.si_code = TARGET_TRAP_BRKPT;
624f7979 413 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 414 }
415 }
416 break;
1b6b029e 417 default:
970a87a6 418 pc = env->segs[R_CS].base + env->eip;
5fafdf24 419 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
bc8a22cc 420 (long)pc, trapnr);
1b6b029e
FB		 421 abort();
422 }
66fb9763 423 process_pending_signals(env);
1b6b029e
FB		 424 }
425}
b346ff46
FB		 426#endif
427
428#ifdef TARGET_ARM
429
d8fd2954
PB		 430#define get_user_code_u32(x, gaddr, doswap) \
431 ({ abi_long __r = get_user_u32((x), (gaddr)); \
432 if (!__r && (doswap)) { \
433 (x) = bswap32(x); \
434 } \
435 __r; \
436 })
437
438#define get_user_code_u16(x, gaddr, doswap) \
439 ({ abi_long __r = get_user_u16((x), (gaddr)); \
440 if (!__r && (doswap)) { \
441 (x) = bswap16(x); \
442 } \
443 __r; \
444 })
445
1861c454
PM		 446#ifdef TARGET_ABI32
447/* Commpage handling -- there is no commpage for AArch64 */
448
97cc7560
DDAG		 449/*
450 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
451 * Input:
452 * r0 = pointer to oldval
453 * r1 = pointer to newval
454 * r2 = pointer to target value
455 *
456 * Output:
457 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
458 * C set if *ptr was changed, clear if no exchange happened
459 *
460 * Note segv's in kernel helpers are a bit tricky, we can set the
461 * data address sensibly but the PC address is just the entry point.
462 */
463static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
464{
465 uint64_t oldval, newval, val;
466 uint32_t addr, cpsr;
467 target_siginfo_t info;
468
469 /* Based on the 32 bit code in do_kernel_trap */
470
471 /* XXX: This only works between threads, not between processes.
472 It's probably possible to implement this with native host
473 operations. However things like ldrex/strex are much harder so
474 there's not much point trying. */
475 start_exclusive();
476 cpsr = cpsr_read(env);
477 addr = env->regs[2];
478
479 if (get_user_u64(oldval, env->regs[0])) {
abf1172f 480 env->exception.vaddress = env->regs[0];
97cc7560
DDAG		 481 goto segv;
482 };
483
484 if (get_user_u64(newval, env->regs[1])) {
abf1172f 485 env->exception.vaddress = env->regs[1];
97cc7560
DDAG		 486 goto segv;
487 };
488
489 if (get_user_u64(val, addr)) {
abf1172f 490 env->exception.vaddress = addr;
97cc7560
DDAG		 491 goto segv;
492 }
493
494 if (val == oldval) {
495 val = newval;
496
497 if (put_user_u64(val, addr)) {
abf1172f 498 env->exception.vaddress = addr;
97cc7560
DDAG		 499 goto segv;
500 };
501
502 env->regs[0] = 0;
503 cpsr |= CPSR_C;
504 } else {
505 env->regs[0] = -1;
506 cpsr &= ~CPSR_C;
507 }
508 cpsr_write(env, cpsr, CPSR_C);
509 end_exclusive();
510 return;
511
512segv:
513 end_exclusive();
514 /* We get the PC of the entry address - which is as good as anything,
515 on a real kernel what you get depends on which mode it uses. */
a86b3c64 516 info.si_signo = TARGET_SIGSEGV;
97cc7560
DDAG		 517 info.si_errno = 0;
518 /* XXX: check env->error_code */
519 info.si_code = TARGET_SEGV_MAPERR;
abf1172f 520 info._sifields._sigfault._addr = env->exception.vaddress;
97cc7560 521 queue_signal(env, info.si_signo, &info);
97cc7560
DDAG		 522}
523
fbb4a2e3
PB		 524/* Handle a jump to the kernel code page. */
525static int
526do_kernel_trap(CPUARMState *env)
527{
528 uint32_t addr;
529 uint32_t cpsr;
530 uint32_t val;
531
532 switch (env->regs[15]) {
533 case 0xffff0fa0: /* __kernel_memory_barrier */
534 /* ??? No-op. Will need to do better for SMP. */
535 break;
536 case 0xffff0fc0: /* __kernel_cmpxchg */
d5975363
PB		 537 /* XXX: This only works between threads, not between processes.
538 It's probably possible to implement this with native host
539 operations. However things like ldrex/strex are much harder so
540 there's not much point trying. */
541 start_exclusive();
fbb4a2e3
PB		 542 cpsr = cpsr_read(env);
543 addr = env->regs[2];
544 /* FIXME: This should SEGV if the access fails. */
545 if (get_user_u32(val, addr))
546 val = ~env->regs[0];
547 if (val == env->regs[0]) {
548 val = env->regs[1];
549 /* FIXME: Check for segfaults. */
550 put_user_u32(val, addr);
551 env->regs[0] = 0;
552 cpsr |= CPSR_C;
553 } else {
554 env->regs[0] = -1;
555 cpsr &= ~CPSR_C;
556 }
557 cpsr_write(env, cpsr, CPSR_C);
d5975363 558 end_exclusive();
fbb4a2e3
PB		 559 break;
560 case 0xffff0fe0: /* __kernel_get_tls */
b8d43285 561 env->regs[0] = cpu_get_tls(env);
fbb4a2e3 562 break;
97cc7560
DDAG		 563 case 0xffff0f60: /* __kernel_cmpxchg64 */
564 arm_kernel_cmpxchg64_helper(env);
565 break;
566
fbb4a2e3
PB		 567 default:
568 return 1;
569 }
570 /* Jump back to the caller. */
571 addr = env->regs[14];
572 if (addr & 1) {
573 env->thumb = 1;
574 addr &= ~1;
575 }
576 env->regs[15] = addr;
577
578 return 0;
579}
580
fa2ef212 581/* Store exclusive handling for AArch32 */
426f5abc
PB		 582static int do_strex(CPUARMState *env)
583{
03d05e2d 584 uint64_t val;
426f5abc
PB		 585 int size;
586 int rc = 1;
587 int segv = 0;
588 uint32_t addr;
589 start_exclusive();
03d05e2d 590 if (env->exclusive_addr != env->exclusive_test) {
426f5abc
PB		 591 goto fail;
592 }
03d05e2d
PM		 593 /* We know we're always AArch32 so the address is in uint32_t range
594 * unless it was the -1 exclusive-monitor-lost value (which won't
595 * match exclusive_test above).
596 */
597 assert(extract64(env->exclusive_addr, 32, 32) == 0);
598 addr = env->exclusive_addr;
426f5abc
PB		 599 size = env->exclusive_info & 0xf;
600 switch (size) {
601 case 0:
602 segv = get_user_u8(val, addr);
603 break;
604 case 1:
605 segv = get_user_u16(val, addr);
606 break;
607 case 2:
608 case 3:
609 segv = get_user_u32(val, addr);
610 break;
f7001a3b
AJ		 611 default:
612 abort();
426f5abc
PB		 613 }
614 if (segv) {
abf1172f 615 env->exception.vaddress = addr;
426f5abc
PB		 616 goto done;
617 }
426f5abc 618 if (size == 3) {
03d05e2d
PM		 619 uint32_t valhi;
620 segv = get_user_u32(valhi, addr + 4);
426f5abc 621 if (segv) {
abf1172f 622 env->exception.vaddress = addr + 4;
426f5abc
PB		 623 goto done;
624 }
03d05e2d 625 val = deposit64(val, 32, 32, valhi);
426f5abc 626 }
03d05e2d
PM		 627 if (val != env->exclusive_val) {
628 goto fail;
629 }
630
426f5abc
PB		 631 val = env->regs[(env->exclusive_info >> 8) & 0xf];
632 switch (size) {
633 case 0:
634 segv = put_user_u8(val, addr);
635 break;
636 case 1:
637 segv = put_user_u16(val, addr);
638 break;
639 case 2:
640 case 3:
641 segv = put_user_u32(val, addr);
642 break;
643 }
644 if (segv) {
abf1172f 645 env->exception.vaddress = addr;
426f5abc
PB		 646 goto done;
647 }
648 if (size == 3) {
649 val = env->regs[(env->exclusive_info >> 12) & 0xf];
2c9adbda 650 segv = put_user_u32(val, addr + 4);
426f5abc 651 if (segv) {
abf1172f 652 env->exception.vaddress = addr + 4;
426f5abc
PB		 653 goto done;
654 }
655 }
656 rc = 0;
657fail:
725b8a69 658 env->regs[15] += 4;
426f5abc
PB		 659 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
660done:
661 end_exclusive();
662 return segv;
663}
664
b346ff46
FB		 665void cpu_loop(CPUARMState *env)
666{
0315c31c 667 CPUState *cs = CPU(arm_env_get_cpu(env));
b346ff46
FB		 668 int trapnr;
669 unsigned int n, insn;
c227f099 670 target_siginfo_t info;
b5ff1b31 671 uint32_t addr;
3b46e624 672
b346ff46 673 for(;;) {
0315c31c 674 cpu_exec_start(cs);
ea3e9847 675 trapnr = cpu_arm_exec(cs);
0315c31c 676 cpu_exec_end(cs);
b346ff46
FB		 677 switch(trapnr) {
678 case EXCP_UDEF:
c6981055 679 {
0429a971 680 TaskState *ts = cs->opaque;
c6981055 681 uint32_t opcode;
6d9a42be 682 int rc;
c6981055
FB		 683
684 /* we handle the FPU emulation here, as Linux */
685 /* we get the opcode */
2f619698 686 /* FIXME - what to do if get_user() fails? */
d8fd2954 687 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
3b46e624 688
6d9a42be
AJ		 689 rc = EmulateAll(opcode, &ts->fpa, env);
690 if (rc == 0) { /* illegal instruction */
a86b3c64 691 info.si_signo = TARGET_SIGILL;
c6981055
FB		 692 info.si_errno = 0;
693 info.si_code = TARGET_ILL_ILLOPN;
694 info._sifields._sigfault._addr = env->regs[15];
624f7979 695 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 696 } else if (rc < 0) { /* FP exception */
697 int arm_fpe=0;
698
699 /* translate softfloat flags to FPSR flags */
700 if (-rc & float_flag_invalid)
701 arm_fpe |= BIT_IOC;
702 if (-rc & float_flag_divbyzero)
703 arm_fpe |= BIT_DZC;
704 if (-rc & float_flag_overflow)
705 arm_fpe |= BIT_OFC;
706 if (-rc & float_flag_underflow)
707 arm_fpe |= BIT_UFC;
708 if (-rc & float_flag_inexact)
709 arm_fpe |= BIT_IXC;
710
711 FPSR fpsr = ts->fpa.fpsr;
712 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
713
714 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
a86b3c64 715 info.si_signo = TARGET_SIGFPE;
6d9a42be
AJ		 716 info.si_errno = 0;
717
718 /* ordered by priority, least first */
719 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
720 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
721 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
722 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
723 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
724
725 info._sifields._sigfault._addr = env->regs[15];
624f7979 726 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 727 } else {
728 env->regs[15] += 4;
729 }
730
731 /* accumulate unenabled exceptions */
732 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
733 fpsr |= BIT_IXC;
734 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
735 fpsr |= BIT_UFC;
736 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
737 fpsr |= BIT_OFC;
738 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
739 fpsr |= BIT_DZC;
740 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
741 fpsr |= BIT_IOC;
742 ts->fpa.fpsr=fpsr;
743 } else { /* everything OK */
c6981055
FB		 744 /* increment PC */
745 env->regs[15] += 4;
746 }
747 }
b346ff46
FB		 748 break;
749 case EXCP_SWI:
06c949e6 750 case EXCP_BKPT:
b346ff46 751 {
ce4defa0 752 env->eabi = 1;
b346ff46 753 /* system call */
06c949e6
PB		 754 if (trapnr == EXCP_BKPT) {
755 if (env->thumb) {
2f619698 756 /* FIXME - what to do if get_user() fails? */
d8fd2954 757 get_user_code_u16(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 758 n = insn & 0xff;
759 env->regs[15] += 2;
760 } else {
2f619698 761 /* FIXME - what to do if get_user() fails? */
d8fd2954 762 get_user_code_u32(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 763 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
764 env->regs[15] += 4;
765 }
192c7bd9 766 } else {
06c949e6 767 if (env->thumb) {
2f619698 768 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 769 get_user_code_u16(insn, env->regs[15] - 2,
770 env->bswap_code);
06c949e6
PB		 771 n = insn & 0xff;
772 } else {
2f619698 773 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 774 get_user_code_u32(insn, env->regs[15] - 4,
775 env->bswap_code);
06c949e6
PB		 776 n = insn & 0xffffff;
777 }
192c7bd9
FB		 778 }
779
6f1f31c0 780 if (n == ARM_NR_cacheflush) {
dcfd14b3 781 /* nop */
a4f81979
FB		 782 } else if (n == ARM_NR_semihosting
783 || n == ARM_NR_thumb_semihosting) {
784 env->regs[0] = do_arm_semihosting (env);
3a1363ac 785 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
b346ff46 786 /* linux syscall */
ce4defa0 787 if (env->thumb || n == 0) {
192c7bd9
FB		 788 n = env->regs[7];
789 } else {
790 n -= ARM_SYSCALL_BASE;
ce4defa0 791 env->eabi = 0;
192c7bd9 792 }
fbb4a2e3
PB		 793 if ( n > ARM_NR_BASE) {
794 switch (n) {
795 case ARM_NR_cacheflush:
dcfd14b3 796 /* nop */
fbb4a2e3
PB		 797 break;
798 case ARM_NR_set_tls:
799 cpu_set_tls(env, env->regs[0]);
800 env->regs[0] = 0;
801 break;
d5355087
HL		 802 case ARM_NR_breakpoint:
803 env->regs[15] -= env->thumb ? 2 : 4;
804 goto excp_debug;
fbb4a2e3
PB		 805 default:
806 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
807 n);
808 env->regs[0] = -TARGET_ENOSYS;
809 break;
810 }
811 } else {
812 env->regs[0] = do_syscall(env,
813 n,
814 env->regs[0],
815 env->regs[1],
816 env->regs[2],
817 env->regs[3],
818 env->regs[4],
5945cfcb
PM		 819 env->regs[5],
820 0, 0);
fbb4a2e3 821 }
b346ff46
FB		 822 } else {
823 goto error;
824 }
825 }
826 break;
43fff238
FB		 827 case EXCP_INTERRUPT:
828 /* just indicate that signals should be handled asap */
829 break;
abf1172f
PM		 830 case EXCP_STREX:
831 if (!do_strex(env)) {
832 break;
833 }
834 /* fall through for segv */
68016c62
FB		 835 case EXCP_PREFETCH_ABORT:
836 case EXCP_DATA_ABORT:
abf1172f 837 addr = env->exception.vaddress;
68016c62 838 {
a86b3c64 839 info.si_signo = TARGET_SIGSEGV;
68016c62
FB		 840 info.si_errno = 0;
841 /* XXX: check env->error_code */
842 info.si_code = TARGET_SEGV_MAPERR;
b5ff1b31 843 info._sifields._sigfault._addr = addr;
624f7979 844 queue_signal(env, info.si_signo, &info);
68016c62
FB		 845 }
846 break;
1fddef4b 847 case EXCP_DEBUG:
d5355087 848 excp_debug:
1fddef4b
FB		 849 {
850 int sig;
851
db6b81d4 852 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 853 if (sig)
854 {
855 info.si_signo = sig;
856 info.si_errno = 0;
857 info.si_code = TARGET_TRAP_BRKPT;
624f7979 858 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 859 }
860 }
861 break;
fbb4a2e3
PB		 862 case EXCP_KERNEL_TRAP:
863 if (do_kernel_trap(env))
864 goto error;
865 break;
b346ff46
FB		 866 default:
867 error:
5fafdf24 868 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
b346ff46 869 trapnr);
878096ee 870 cpu_dump_state(cs, stderr, fprintf, 0);
b346ff46
FB		 871 abort();
872 }
873 process_pending_signals(env);
874 }
875}
876
1861c454
PM		 877#else
878
fa2ef212
MM		 879/*
880 * Handle AArch64 store-release exclusive
881 *
882 * rs = gets the status result of store exclusive
883 * rt = is the register that is stored
884 * rt2 = is the second register store (in STP)
885 *
886 */
887static int do_strex_a64(CPUARMState *env)
888{
889 uint64_t val;
890 int size;
891 bool is_pair;
892 int rc = 1;
893 int segv = 0;
894 uint64_t addr;
895 int rs, rt, rt2;
896
897 start_exclusive();
898 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
899 size = extract32(env->exclusive_info, 0, 2);
900 is_pair = extract32(env->exclusive_info, 2, 1);
901 rs = extract32(env->exclusive_info, 4, 5);
902 rt = extract32(env->exclusive_info, 9, 5);
903 rt2 = extract32(env->exclusive_info, 14, 5);
904
905 addr = env->exclusive_addr;
906
907 if (addr != env->exclusive_test) {
908 goto finish;
909 }
910
911 switch (size) {
912 case 0:
913 segv = get_user_u8(val, addr);
914 break;
915 case 1:
916 segv = get_user_u16(val, addr);
917 break;
918 case 2:
919 segv = get_user_u32(val, addr);
920 break;
921 case 3:
922 segv = get_user_u64(val, addr);
923 break;
924 default:
925 abort();
926 }
927 if (segv) {
abf1172f 928 env->exception.vaddress = addr;
fa2ef212
MM		 929 goto error;
930 }
931 if (val != env->exclusive_val) {
932 goto finish;
933 }
934 if (is_pair) {
935 if (size == 2) {
936 segv = get_user_u32(val, addr + 4);
937 } else {
938 segv = get_user_u64(val, addr + 8);
939 }
940 if (segv) {
abf1172f 941 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 942 goto error;
943 }
944 if (val != env->exclusive_high) {
945 goto finish;
946 }
947 }
2ea5a2ca
JG		 948 /* handle the zero register */
949 val = rt == 31 ? 0 : env->xregs[rt];
fa2ef212
MM		 950 switch (size) {
951 case 0:
952 segv = put_user_u8(val, addr);
953 break;
954 case 1:
955 segv = put_user_u16(val, addr);
956 break;
957 case 2:
958 segv = put_user_u32(val, addr);
959 break;
960 case 3:
961 segv = put_user_u64(val, addr);
962 break;
963 }
964 if (segv) {
965 goto error;
966 }
967 if (is_pair) {
2ea5a2ca
JG		 968 /* handle the zero register */
969 val = rt2 == 31 ? 0 : env->xregs[rt2];
fa2ef212
MM		 970 if (size == 2) {
971 segv = put_user_u32(val, addr + 4);
972 } else {
973 segv = put_user_u64(val, addr + 8);
974 }
975 if (segv) {
abf1172f 976 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 977 goto error;
978 }
979 }
980 rc = 0;
981finish:
982 env->pc += 4;
983 /* rs == 31 encodes a write to the ZR, thus throwing away
984 * the status return. This is rather silly but valid.
985 */
986 if (rs < 31) {
987 env->xregs[rs] = rc;
988 }
989error:
990 /* instruction faulted, PC does not advance */
991 /* either way a strex releases any exclusive lock we have */
992 env->exclusive_addr = -1;
993 end_exclusive();
994 return segv;
995}
996
1861c454
PM		 997/* AArch64 main loop */
998void cpu_loop(CPUARMState *env)
999{
1000 CPUState *cs = CPU(arm_env_get_cpu(env));
1001 int trapnr, sig;
1002 target_siginfo_t info;
1861c454
PM		 1003
1004 for (;;) {
1005 cpu_exec_start(cs);
ea3e9847 1006 trapnr = cpu_arm_exec(cs);
1861c454
PM		 1007 cpu_exec_end(cs);
1008
1009 switch (trapnr) {
1010 case EXCP_SWI:
1011 env->xregs[0] = do_syscall(env,
1012 env->xregs[8],
1013 env->xregs[0],
1014 env->xregs[1],
1015 env->xregs[2],
1016 env->xregs[3],
1017 env->xregs[4],
1018 env->xregs[5],
1019 0, 0);
1020 break;
1021 case EXCP_INTERRUPT:
1022 /* just indicate that signals should be handled asap */
1023 break;
1024 case EXCP_UDEF:
a86b3c64 1025 info.si_signo = TARGET_SIGILL;
1861c454
PM		 1026 info.si_errno = 0;
1027 info.si_code = TARGET_ILL_ILLOPN;
1028 info._sifields._sigfault._addr = env->pc;
1029 queue_signal(env, info.si_signo, &info);
1030 break;
abf1172f
PM		 1031 case EXCP_STREX:
1032 if (!do_strex_a64(env)) {
1033 break;
1034 }
1035 /* fall through for segv */
1861c454 1036 case EXCP_PREFETCH_ABORT:
1861c454 1037 case EXCP_DATA_ABORT:
a86b3c64 1038 info.si_signo = TARGET_SIGSEGV;
1861c454
PM		 1039 info.si_errno = 0;
1040 /* XXX: check env->error_code */
1041 info.si_code = TARGET_SEGV_MAPERR;
686581ad 1042 info._sifields._sigfault._addr = env->exception.vaddress;
1861c454
PM		 1043 queue_signal(env, info.si_signo, &info);
1044 break;
1045 case EXCP_DEBUG:
1046 case EXCP_BKPT:
1047 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1048 if (sig) {
1049 info.si_signo = sig;
1050 info.si_errno = 0;
1051 info.si_code = TARGET_TRAP_BRKPT;
1052 queue_signal(env, info.si_signo, &info);
1053 }
1054 break;
8012c84f
PM		 1055 case EXCP_SEMIHOST:
1056 env->xregs[0] = do_arm_semihosting(env);
1057 break;
1861c454
PM		 1058 default:
1059 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
1060 trapnr);
1061 cpu_dump_state(cs, stderr, fprintf, 0);
1062 abort();
1063 }
1064 process_pending_signals(env);
fa2ef212
MM		 1065 /* Exception return on AArch64 always clears the exclusive monitor,
1066 * so any return to running guest code implies this.
1067 * A strex (successful or otherwise) also clears the monitor, so
1068 * we don't need to specialcase EXCP_STREX.
1069 */
1070 env->exclusive_addr = -1;
1861c454
PM		 1071 }
1072}
1073#endif /* ndef TARGET_ABI32 */
1074
b346ff46 1075#endif
1b6b029e 1076
d2fbca94
GX		 1077#ifdef TARGET_UNICORE32
1078
05390248 1079void cpu_loop(CPUUniCore32State *env)
d2fbca94 1080{
0315c31c 1081 CPUState *cs = CPU(uc32_env_get_cpu(env));
d2fbca94
GX		 1082 int trapnr;
1083 unsigned int n, insn;
1084 target_siginfo_t info;
1085
1086 for (;;) {
0315c31c 1087 cpu_exec_start(cs);
ea3e9847 1088 trapnr = uc32_cpu_exec(cs);
0315c31c 1089 cpu_exec_end(cs);
d2fbca94
GX		 1090 switch (trapnr) {
1091 case UC32_EXCP_PRIV:
1092 {
1093 /* system call */
1094 get_user_u32(insn, env->regs[31] - 4);
1095 n = insn & 0xffffff;
1096
1097 if (n >= UC32_SYSCALL_BASE) {
1098 /* linux syscall */
1099 n -= UC32_SYSCALL_BASE;
1100 if (n == UC32_SYSCALL_NR_set_tls) {
1101 cpu_set_tls(env, env->regs[0]);
1102 env->regs[0] = 0;
1103 } else {
1104 env->regs[0] = do_syscall(env,
1105 n,
1106 env->regs[0],
1107 env->regs[1],
1108 env->regs[2],
1109 env->regs[3],
1110 env->regs[4],
5945cfcb
PM		 1111 env->regs[5],
1112 0, 0);
d2fbca94
GX		 1113 }
1114 } else {
1115 goto error;
1116 }
1117 }
1118 break;
d48813dd
GX		 1119 case UC32_EXCP_DTRAP:
1120 case UC32_EXCP_ITRAP:
a86b3c64 1121 info.si_signo = TARGET_SIGSEGV;
d2fbca94
GX		 1122 info.si_errno = 0;
1123 /* XXX: check env->error_code */
1124 info.si_code = TARGET_SEGV_MAPERR;
1125 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1126 queue_signal(env, info.si_signo, &info);
1127 break;
1128 case EXCP_INTERRUPT:
1129 /* just indicate that signals should be handled asap */
1130 break;
1131 case EXCP_DEBUG:
1132 {
1133 int sig;
1134
db6b81d4 1135 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d2fbca94
GX		 1136 if (sig) {
1137 info.si_signo = sig;
1138 info.si_errno = 0;
1139 info.si_code = TARGET_TRAP_BRKPT;
1140 queue_signal(env, info.si_signo, &info);
1141 }
1142 }
1143 break;
1144 default:
1145 goto error;
1146 }
1147 process_pending_signals(env);
1148 }
1149
1150error:
1151 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
878096ee 1152 cpu_dump_state(cs, stderr, fprintf, 0);
d2fbca94
GX		 1153 abort();
1154}
1155#endif
1156
93ac68bc 1157#ifdef TARGET_SPARC
ed23fbd9 1158#define SPARC64_STACK_BIAS 2047
93ac68bc 1159
060366c5
FB		 1160//#define DEBUG_WIN
1161
2623cbaf
FB		 1162/* WARNING: dealing with register windows _is_ complicated. More info
1163 can be found at http://www.sics.se/~psm/sparcstack.html */
060366c5
FB		 1164static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1165{
1a14026e 1166 index = (index + cwp * 16) % (16 * env->nwindows);
060366c5
FB		 1167 /* wrap handling : if cwp is on the last window, then we use the
1168 registers 'after' the end */
1a14026e
BS		 1169 if (index < 8 && env->cwp == env->nwindows - 1)
1170 index += 16 * env->nwindows;
060366c5
FB		 1171 return index;
1172}
1173
2623cbaf
FB		 1174/* save the register window 'cwp1' */
1175static inline void save_window_offset(CPUSPARCState *env, int cwp1)
060366c5 1176{
2623cbaf 1177 unsigned int i;
992f48a0 1178 abi_ulong sp_ptr;
3b46e624 1179
53a5960a 1180 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1181#ifdef TARGET_SPARC64
1182 if (sp_ptr & 3)
1183 sp_ptr += SPARC64_STACK_BIAS;
1184#endif
060366c5 1185#if defined(DEBUG_WIN)
2daf0284
BS		 1186 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1187 sp_ptr, cwp1);
060366c5 1188#endif
2623cbaf 1189 for(i = 0; i < 16; i++) {
2f619698
FB		 1190 /* FIXME - what to do if put_user() fails? */
1191 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1192 sp_ptr += sizeof(abi_ulong);
2623cbaf 1193 }
060366c5
FB		 1194}
1195
1196static void save_window(CPUSPARCState *env)
1197{
5ef54116 1198#ifndef TARGET_SPARC64
2623cbaf 1199 unsigned int new_wim;
1a14026e
BS		 1200 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1201 ((1LL << env->nwindows) - 1);
1202 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
2623cbaf 1203 env->wim = new_wim;
5ef54116 1204#else
1a14026e 1205 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
5ef54116
FB		 1206 env->cansave++;
1207 env->canrestore--;
1208#endif
060366c5
FB		 1209}
1210
1211static void restore_window(CPUSPARCState *env)
1212{
eda52953
BS		 1213#ifndef TARGET_SPARC64
1214 unsigned int new_wim;
1215#endif
1216 unsigned int i, cwp1;
992f48a0 1217 abi_ulong sp_ptr;
3b46e624 1218
eda52953 1219#ifndef TARGET_SPARC64
1a14026e
BS		 1220 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1221 ((1LL << env->nwindows) - 1);
eda52953 1222#endif
3b46e624 1223
060366c5 1224 /* restore the invalid window */
1a14026e 1225 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
53a5960a 1226 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1227#ifdef TARGET_SPARC64
1228 if (sp_ptr & 3)
1229 sp_ptr += SPARC64_STACK_BIAS;
1230#endif
060366c5 1231#if defined(DEBUG_WIN)
2daf0284
BS		 1232 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1233 sp_ptr, cwp1);
060366c5 1234#endif
2623cbaf 1235 for(i = 0; i < 16; i++) {
2f619698
FB		 1236 /* FIXME - what to do if get_user() fails? */
1237 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1238 sp_ptr += sizeof(abi_ulong);
2623cbaf 1239 }
5ef54116
FB		 1240#ifdef TARGET_SPARC64
1241 env->canrestore++;
1a14026e
BS		 1242 if (env->cleanwin < env->nwindows - 1)
1243 env->cleanwin++;
5ef54116 1244 env->cansave--;
eda52953
BS		 1245#else
1246 env->wim = new_wim;
5ef54116 1247#endif
060366c5
FB		 1248}
1249
1250static void flush_windows(CPUSPARCState *env)
1251{
1252 int offset, cwp1;
2623cbaf
FB		 1253
1254 offset = 1;
060366c5
FB		 1255 for(;;) {
1256 /* if restore would invoke restore_window(), then we can stop */
1a14026e 1257 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
eda52953 1258#ifndef TARGET_SPARC64
060366c5
FB		 1259 if (env->wim & (1 << cwp1))
1260 break;
eda52953
BS		 1261#else
1262 if (env->canrestore == 0)
1263 break;
1264 env->cansave++;
1265 env->canrestore--;
1266#endif
2623cbaf 1267 save_window_offset(env, cwp1);
060366c5
FB		 1268 offset++;
1269 }
1a14026e 1270 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
eda52953
BS		 1271#ifndef TARGET_SPARC64
1272 /* set wim so that restore will reload the registers */
2623cbaf 1273 env->wim = 1 << cwp1;
eda52953 1274#endif
2623cbaf
FB		 1275#if defined(DEBUG_WIN)
1276 printf("flush_windows: nb=%d\n", offset - 1);
80a9d035 1277#endif
2623cbaf 1278}
060366c5 1279
93ac68bc
FB		 1280void cpu_loop (CPUSPARCState *env)
1281{
878096ee 1282 CPUState *cs = CPU(sparc_env_get_cpu(env));
2cc20260
RH		 1283 int trapnr;
1284 abi_long ret;
c227f099 1285 target_siginfo_t info;
3b46e624 1286
060366c5 1287 while (1) {
b040bc9c 1288 cpu_exec_start(cs);
ea3e9847 1289 trapnr = cpu_sparc_exec(cs);
b040bc9c 1290 cpu_exec_end(cs);
3b46e624 1291
20132b96
RH		 1292 /* Compute PSR before exposing state. */
1293 if (env->cc_op != CC_OP_FLAGS) {
1294 cpu_get_psr(env);
1295 }
1296
060366c5 1297 switch (trapnr) {
5ef54116 1298#ifndef TARGET_SPARC64
5fafdf24 1299 case 0x88:
060366c5 1300 case 0x90:
5ef54116 1301#else
cb33da57 1302 case 0x110:
5ef54116
FB		 1303 case 0x16d:
1304#endif
060366c5 1305 ret = do_syscall (env, env->gregs[1],
5fafdf24
TS		 1306 env->regwptr[0], env->regwptr[1],
1307 env->regwptr[2], env->regwptr[3],
5945cfcb
PM		 1308 env->regwptr[4], env->regwptr[5],
1309 0, 0);
2cc20260 1310 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
992f48a0 1311#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1312 env->xcc |= PSR_CARRY;
1313#else
060366c5 1314 env->psr |= PSR_CARRY;
27908725 1315#endif
060366c5
FB		 1316 ret = -ret;
1317 } else {
992f48a0 1318#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1319 env->xcc &= ~PSR_CARRY;
1320#else
060366c5 1321 env->psr &= ~PSR_CARRY;
27908725 1322#endif
060366c5
FB		 1323 }
1324 env->regwptr[0] = ret;
1325 /* next instruction */
1326 env->pc = env->npc;
1327 env->npc = env->npc + 4;
1328 break;
1329 case 0x83: /* flush windows */
992f48a0
BS		 1330#ifdef TARGET_ABI32
1331 case 0x103:
1332#endif
2623cbaf 1333 flush_windows(env);
060366c5
FB		 1334 /* next instruction */
1335 env->pc = env->npc;
1336 env->npc = env->npc + 4;
1337 break;
3475187d 1338#ifndef TARGET_SPARC64
060366c5
FB		 1339 case TT_WIN_OVF: /* window overflow */
1340 save_window(env);
1341 break;
1342 case TT_WIN_UNF: /* window underflow */
1343 restore_window(env);
1344 break;
61ff6f58
FB		 1345 case TT_TFAULT:
1346 case TT_DFAULT:
1347 {
59f7182f 1348 info.si_signo = TARGET_SIGSEGV;
61ff6f58
FB		 1349 info.si_errno = 0;
1350 /* XXX: check env->error_code */
1351 info.si_code = TARGET_SEGV_MAPERR;
1352 info._sifields._sigfault._addr = env->mmuregs[4];
624f7979 1353 queue_signal(env, info.si_signo, &info);
61ff6f58
FB		 1354 }
1355 break;
3475187d 1356#else
5ef54116
FB		 1357 case TT_SPILL: /* window overflow */
1358 save_window(env);
1359 break;
1360 case TT_FILL: /* window underflow */
1361 restore_window(env);
1362 break;
7f84a729
BS		 1363 case TT_TFAULT:
1364 case TT_DFAULT:
1365 {
59f7182f 1366 info.si_signo = TARGET_SIGSEGV;
7f84a729
BS		 1367 info.si_errno = 0;
1368 /* XXX: check env->error_code */
1369 info.si_code = TARGET_SEGV_MAPERR;
1370 if (trapnr == TT_DFAULT)
1371 info._sifields._sigfault._addr = env->dmmuregs[4];
1372 else
8194f35a 1373 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
624f7979 1374 queue_signal(env, info.si_signo, &info);
7f84a729
BS		 1375 }
1376 break;
27524dc3 1377#ifndef TARGET_ABI32
5bfb56b2
BS		 1378 case 0x16e:
1379 flush_windows(env);
1380 sparc64_get_context(env);
1381 break;
1382 case 0x16f:
1383 flush_windows(env);
1384 sparc64_set_context(env);
1385 break;
27524dc3 1386#endif
3475187d 1387#endif
48dc41eb
FB		 1388 case EXCP_INTERRUPT:
1389 /* just indicate that signals should be handled asap */
1390 break;
75f22e4e
RH		 1391 case TT_ILL_INSN:
1392 {
1393 info.si_signo = TARGET_SIGILL;
1394 info.si_errno = 0;
1395 info.si_code = TARGET_ILL_ILLOPC;
1396 info._sifields._sigfault._addr = env->pc;
1397 queue_signal(env, info.si_signo, &info);
1398 }
1399 break;
1fddef4b
FB		 1400 case EXCP_DEBUG:
1401 {
1402 int sig;
1403
db6b81d4 1404 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 1405 if (sig)
1406 {
1407 info.si_signo = sig;
1408 info.si_errno = 0;
1409 info.si_code = TARGET_TRAP_BRKPT;
624f7979 1410 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 1411 }
1412 }
1413 break;
060366c5
FB		 1414 default:
1415 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 1416 cpu_dump_state(cs, stderr, fprintf, 0);
060366c5
FB		 1417 exit (1);
1418 }
1419 process_pending_signals (env);
1420 }
93ac68bc
FB		 1421}
1422
1423#endif
1424
67867308 1425#ifdef TARGET_PPC
05390248 1426static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
9fddaa0c 1427{
7d6b1dae 1428 return cpu_get_real_ticks();
9fddaa0c 1429}
3b46e624 1430
05390248 1431uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
9fddaa0c 1432{
e3ea6529 1433 return cpu_ppc_get_tb(env);
9fddaa0c 1434}
3b46e624 1435
05390248 1436uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
9fddaa0c
FB		 1437{
1438 return cpu_ppc_get_tb(env) >> 32;
1439}
3b46e624 1440
05390248 1441uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
9fddaa0c 1442{
b711de95 1443 return cpu_ppc_get_tb(env);
9fddaa0c 1444}
5fafdf24 1445
05390248 1446uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
9fddaa0c 1447{
a062e36c 1448 return cpu_ppc_get_tb(env) >> 32;
9fddaa0c 1449}
76a66253 1450
05390248 1451uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
76a66253
JM		 1452__attribute__ (( alias ("cpu_ppc_load_tbu") ));
1453
05390248 1454uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
9fddaa0c 1455{
76a66253 1456 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
9fddaa0c 1457}
76a66253 1458
a750fc0b 1459/* XXX: to be fixed */
73b01960 1460int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
a750fc0b
JM		 1461{
1462 return -1;
1463}
1464
73b01960 1465int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
a750fc0b
JM		 1466{
1467 return -1;
1468}
1469
001faf32
BS		 1470#define EXCP_DUMP(env, fmt, ...) \
1471do { \
a0762859 1472 CPUState *cs = ENV_GET_CPU(env); \
001faf32 1473 fprintf(stderr, fmt , ## __VA_ARGS__); \
a0762859 1474 cpu_dump_state(cs, stderr, fprintf, 0); \
001faf32 1475 qemu_log(fmt, ## __VA_ARGS__); \
eeacee4d 1476 if (qemu_log_enabled()) { \
a0762859 1477 log_cpu_state(cs, 0); \
eeacee4d 1478 } \
e1833e1f
JM		 1479} while (0)
1480
56f066bb
NF		 1481static int do_store_exclusive(CPUPPCState *env)
1482{
1483 target_ulong addr;
1484 target_ulong page_addr;
e22c357b 1485 target_ulong val, val2 __attribute__((unused)) = 0;
56f066bb
NF		 1486 int flags;
1487 int segv = 0;
1488
1489 addr = env->reserve_ea;
1490 page_addr = addr & TARGET_PAGE_MASK;
1491 start_exclusive();
1492 mmap_lock();
1493 flags = page_get_flags(page_addr);
1494 if ((flags & PAGE_READ) == 0) {
1495 segv = 1;
1496 } else {
1497 int reg = env->reserve_info & 0x1f;
4b1daa72 1498 int size = env->reserve_info >> 5;
56f066bb
NF		 1499 int stored = 0;
1500
1501 if (addr == env->reserve_addr) {
1502 switch (size) {
1503 case 1: segv = get_user_u8(val, addr); break;
1504 case 2: segv = get_user_u16(val, addr); break;
1505 case 4: segv = get_user_u32(val, addr); break;
1506#if defined(TARGET_PPC64)
1507 case 8: segv = get_user_u64(val, addr); break;
27b95bfe
TM		 1508 case 16: {
1509 segv = get_user_u64(val, addr);
1510 if (!segv) {
1511 segv = get_user_u64(val2, addr + 8);
1512 }
1513 break;
1514 }
56f066bb
NF		 1515#endif
1516 default: abort();
1517 }
1518 if (!segv && val == env->reserve_val) {
1519 val = env->gpr[reg];
1520 switch (size) {
1521 case 1: segv = put_user_u8(val, addr); break;
1522 case 2: segv = put_user_u16(val, addr); break;
1523 case 4: segv = put_user_u32(val, addr); break;
1524#if defined(TARGET_PPC64)
1525 case 8: segv = put_user_u64(val, addr); break;
27b95bfe
TM		 1526 case 16: {
1527 if (val2 == env->reserve_val2) {
e22c357b
DK		 1528 if (msr_le) {
1529 val2 = val;
1530 val = env->gpr[reg+1];
1531 } else {
1532 val2 = env->gpr[reg+1];
1533 }
27b95bfe
TM		 1534 segv = put_user_u64(val, addr);
1535 if (!segv) {
1536 segv = put_user_u64(val2, addr + 8);
1537 }
1538 }
1539 break;
1540 }
56f066bb
NF		 1541#endif
1542 default: abort();
1543 }
1544 if (!segv) {
1545 stored = 1;
1546 }
1547 }
1548 }
1549 env->crf[0] = (stored << 1) | xer_so;
1550 env->reserve_addr = (target_ulong)-1;
1551 }
1552 if (!segv) {
1553 env->nip += 4;
1554 }
1555 mmap_unlock();
1556 end_exclusive();
1557 return segv;
1558}
1559
67867308
FB		 1560void cpu_loop(CPUPPCState *env)
1561{
0315c31c 1562 CPUState *cs = CPU(ppc_env_get_cpu(env));
c227f099 1563 target_siginfo_t info;
61190b14 1564 int trapnr;
9e0e2f96 1565 target_ulong ret;
3b46e624 1566
67867308 1567 for(;;) {
0315c31c 1568 cpu_exec_start(cs);
ea3e9847 1569 trapnr = cpu_ppc_exec(cs);
0315c31c 1570 cpu_exec_end(cs);
67867308 1571 switch(trapnr) {
e1833e1f
JM		 1572 case POWERPC_EXCP_NONE:
1573 /* Just go on */
67867308 1574 break;
e1833e1f 1575 case POWERPC_EXCP_CRITICAL: /* Critical input */
a47dddd7 1576 cpu_abort(cs, "Critical interrupt while in user mode. "
e1833e1f 1577 "Aborting\n");
61190b14 1578 break;
e1833e1f 1579 case POWERPC_EXCP_MCHECK: /* Machine check exception */
a47dddd7 1580 cpu_abort(cs, "Machine check exception while in user mode. "
e1833e1f
JM		 1581 "Aborting\n");
1582 break;
1583 case POWERPC_EXCP_DSI: /* Data storage exception */
90e189ec 1584 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
e1833e1f
JM		 1585 env->spr[SPR_DAR]);
1586 /* XXX: check this. Seems bugged */
2be0071f
FB		 1587 switch (env->error_code & 0xFF000000) {
1588 case 0x40000000:
61190b14
FB		 1589 info.si_signo = TARGET_SIGSEGV;
1590 info.si_errno = 0;
1591 info.si_code = TARGET_SEGV_MAPERR;
1592 break;
2be0071f 1593 case 0x04000000:
61190b14
FB		 1594 info.si_signo = TARGET_SIGILL;
1595 info.si_errno = 0;
1596 info.si_code = TARGET_ILL_ILLADR;
1597 break;
2be0071f 1598 case 0x08000000:
61190b14
FB		 1599 info.si_signo = TARGET_SIGSEGV;
1600 info.si_errno = 0;
1601 info.si_code = TARGET_SEGV_ACCERR;
1602 break;
61190b14
FB		 1603 default:
1604 /* Let's send a regular segfault... */
e1833e1f
JM		 1605 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1606 env->error_code);
61190b14
FB		 1607 info.si_signo = TARGET_SIGSEGV;
1608 info.si_errno = 0;
1609 info.si_code = TARGET_SEGV_MAPERR;
1610 break;
1611 }
67867308 1612 info._sifields._sigfault._addr = env->nip;
624f7979 1613 queue_signal(env, info.si_signo, &info);
67867308 1614 break;
e1833e1f 1615 case POWERPC_EXCP_ISI: /* Instruction storage exception */
90e189ec
BS		 1616 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1617 "\n", env->spr[SPR_SRR0]);
e1833e1f 1618 /* XXX: check this */
2be0071f
FB		 1619 switch (env->error_code & 0xFF000000) {
1620 case 0x40000000:
61190b14 1621 info.si_signo = TARGET_SIGSEGV;
67867308 1622 info.si_errno = 0;
61190b14
FB		 1623 info.si_code = TARGET_SEGV_MAPERR;
1624 break;
2be0071f
FB		 1625 case 0x10000000:
1626 case 0x08000000:
61190b14
FB		 1627 info.si_signo = TARGET_SIGSEGV;
1628 info.si_errno = 0;
1629 info.si_code = TARGET_SEGV_ACCERR;
1630 break;
1631 default:
1632 /* Let's send a regular segfault... */
e1833e1f
JM		 1633 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1634 env->error_code);
61190b14
FB		 1635 info.si_signo = TARGET_SIGSEGV;
1636 info.si_errno = 0;
1637 info.si_code = TARGET_SEGV_MAPERR;
1638 break;
1639 }
1640 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1641 queue_signal(env, info.si_signo, &info);
67867308 1642 break;
e1833e1f 1643 case POWERPC_EXCP_EXTERNAL: /* External input */
a47dddd7 1644 cpu_abort(cs, "External interrupt while in user mode. "
e1833e1f
JM		 1645 "Aborting\n");
1646 break;
1647 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1648 EXCP_DUMP(env, "Unaligned memory access\n");
1649 /* XXX: check this */
61190b14 1650 info.si_signo = TARGET_SIGBUS;
67867308 1651 info.si_errno = 0;
61190b14 1652 info.si_code = TARGET_BUS_ADRALN;
6bb9a0a9 1653 info._sifields._sigfault._addr = env->nip;
624f7979 1654 queue_signal(env, info.si_signo, &info);
67867308 1655 break;
e1833e1f
JM		 1656 case POWERPC_EXCP_PROGRAM: /* Program exception */
1657 /* XXX: check this */
61190b14 1658 switch (env->error_code & ~0xF) {
e1833e1f
JM		 1659 case POWERPC_EXCP_FP:
1660 EXCP_DUMP(env, "Floating point program exception\n");
61190b14
FB		 1661 info.si_signo = TARGET_SIGFPE;
1662 info.si_errno = 0;
1663 switch (env->error_code & 0xF) {
e1833e1f 1664 case POWERPC_EXCP_FP_OX:
61190b14
FB		 1665 info.si_code = TARGET_FPE_FLTOVF;
1666 break;
e1833e1f 1667 case POWERPC_EXCP_FP_UX:
61190b14
FB		 1668 info.si_code = TARGET_FPE_FLTUND;
1669 break;
e1833e1f
JM		 1670 case POWERPC_EXCP_FP_ZX:
1671 case POWERPC_EXCP_FP_VXZDZ:
61190b14
FB		 1672 info.si_code = TARGET_FPE_FLTDIV;
1673 break;
e1833e1f 1674 case POWERPC_EXCP_FP_XX:
61190b14
FB		 1675 info.si_code = TARGET_FPE_FLTRES;
1676 break;
e1833e1f 1677 case POWERPC_EXCP_FP_VXSOFT:
61190b14
FB		 1678 info.si_code = TARGET_FPE_FLTINV;
1679 break;
7c58044c 1680 case POWERPC_EXCP_FP_VXSNAN:
e1833e1f
JM		 1681 case POWERPC_EXCP_FP_VXISI:
1682 case POWERPC_EXCP_FP_VXIDI:
1683 case POWERPC_EXCP_FP_VXIMZ:
1684 case POWERPC_EXCP_FP_VXVC:
1685 case POWERPC_EXCP_FP_VXSQRT:
1686 case POWERPC_EXCP_FP_VXCVI:
61190b14
FB		 1687 info.si_code = TARGET_FPE_FLTSUB;
1688 break;
1689 default:
e1833e1f
JM		 1690 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1691 env->error_code);
1692 break;
61190b14 1693 }
e1833e1f
JM		 1694 break;
1695 case POWERPC_EXCP_INVAL:
1696 EXCP_DUMP(env, "Invalid instruction\n");
61190b14
FB		 1697 info.si_signo = TARGET_SIGILL;
1698 info.si_errno = 0;
1699 switch (env->error_code & 0xF) {
e1833e1f 1700 case POWERPC_EXCP_INVAL_INVAL:
61190b14
FB		 1701 info.si_code = TARGET_ILL_ILLOPC;
1702 break;
e1833e1f 1703 case POWERPC_EXCP_INVAL_LSWX:
a750fc0b 1704 info.si_code = TARGET_ILL_ILLOPN;
61190b14 1705 break;
e1833e1f 1706 case POWERPC_EXCP_INVAL_SPR:
61190b14
FB		 1707 info.si_code = TARGET_ILL_PRVREG;
1708 break;
e1833e1f 1709 case POWERPC_EXCP_INVAL_FP:
61190b14
FB		 1710 info.si_code = TARGET_ILL_COPROC;
1711 break;
1712 default:
e1833e1f
JM		 1713 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1714 env->error_code & 0xF);
61190b14
FB		 1715 info.si_code = TARGET_ILL_ILLADR;
1716 break;
1717 }
1718 break;
e1833e1f
JM		 1719 case POWERPC_EXCP_PRIV:
1720 EXCP_DUMP(env, "Privilege violation\n");
61190b14
FB		 1721 info.si_signo = TARGET_SIGILL;
1722 info.si_errno = 0;
1723 switch (env->error_code & 0xF) {
e1833e1f 1724 case POWERPC_EXCP_PRIV_OPC:
61190b14
FB		 1725 info.si_code = TARGET_ILL_PRVOPC;
1726 break;
e1833e1f 1727 case POWERPC_EXCP_PRIV_REG:
61190b14 1728 info.si_code = TARGET_ILL_PRVREG;
e1833e1f 1729 break;
61190b14 1730 default:
e1833e1f
JM		 1731 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1732 env->error_code & 0xF);
61190b14
FB		 1733 info.si_code = TARGET_ILL_PRVOPC;
1734 break;
1735 }
1736 break;
e1833e1f 1737 case POWERPC_EXCP_TRAP:
a47dddd7 1738 cpu_abort(cs, "Tried to call a TRAP\n");
e1833e1f 1739 break;
61190b14
FB		 1740 default:
1741 /* Should not happen ! */
a47dddd7 1742 cpu_abort(cs, "Unknown program exception (%02x)\n",
e1833e1f
JM		 1743 env->error_code);
1744 break;
61190b14
FB		 1745 }
1746 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1747 queue_signal(env, info.si_signo, &info);
67867308 1748 break;
e1833e1f
JM		 1749 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1750 EXCP_DUMP(env, "No floating point allowed\n");
61190b14 1751 info.si_signo = TARGET_SIGILL;
67867308 1752 info.si_errno = 0;
61190b14
FB		 1753 info.si_code = TARGET_ILL_COPROC;
1754 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1755 queue_signal(env, info.si_signo, &info);
67867308 1756 break;
e1833e1f 1757 case POWERPC_EXCP_SYSCALL: /* System call exception */
a47dddd7 1758 cpu_abort(cs, "Syscall exception while in user mode. "
e1833e1f 1759 "Aborting\n");
61190b14 1760 break;
e1833e1f
JM		 1761 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1762 EXCP_DUMP(env, "No APU instruction allowed\n");
1763 info.si_signo = TARGET_SIGILL;
1764 info.si_errno = 0;
1765 info.si_code = TARGET_ILL_COPROC;
1766 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1767 queue_signal(env, info.si_signo, &info);
61190b14 1768 break;
e1833e1f 1769 case POWERPC_EXCP_DECR: /* Decrementer exception */
a47dddd7 1770 cpu_abort(cs, "Decrementer interrupt while in user mode. "
e1833e1f 1771 "Aborting\n");
61190b14 1772 break;
e1833e1f 1773 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
a47dddd7 1774 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
e1833e1f
JM		 1775 "Aborting\n");
1776 break;
1777 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
a47dddd7 1778 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
e1833e1f
JM		 1779 "Aborting\n");
1780 break;
1781 case POWERPC_EXCP_DTLB: /* Data TLB error */
a47dddd7 1782 cpu_abort(cs, "Data TLB exception while in user mode. "
e1833e1f
JM		 1783 "Aborting\n");
1784 break;
1785 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
a47dddd7 1786 cpu_abort(cs, "Instruction TLB exception while in user mode. "
e1833e1f
JM		 1787 "Aborting\n");
1788 break;
e1833e1f
JM		 1789 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1790 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1791 info.si_signo = TARGET_SIGILL;
1792 info.si_errno = 0;
1793 info.si_code = TARGET_ILL_COPROC;
1794 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1795 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1796 break;
1797 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
a47dddd7 1798 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
e1833e1f
JM		 1799 break;
1800 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
a47dddd7 1801 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
e1833e1f
JM		 1802 break;
1803 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
a47dddd7 1804 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1805 break;
1806 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
a47dddd7 1807 cpu_abort(cs, "Doorbell interrupt while in user mode. "
e1833e1f
JM		 1808 "Aborting\n");
1809 break;
1810 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
a47dddd7 1811 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
e1833e1f
JM		 1812 "Aborting\n");
1813 break;
1814 case POWERPC_EXCP_RESET: /* System reset exception */
a47dddd7 1815 cpu_abort(cs, "Reset interrupt while in user mode. "
e1833e1f
JM		 1816 "Aborting\n");
1817 break;
e1833e1f 1818 case POWERPC_EXCP_DSEG: /* Data segment exception */
a47dddd7 1819 cpu_abort(cs, "Data segment exception while in user mode. "
e1833e1f
JM		 1820 "Aborting\n");
1821 break;
1822 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
a47dddd7 1823 cpu_abort(cs, "Instruction segment exception "
e1833e1f
JM		 1824 "while in user mode. Aborting\n");
1825 break;
e85e7c6e 1826 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1827 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
a47dddd7 1828 cpu_abort(cs, "Hypervisor decrementer interrupt "
e1833e1f
JM		 1829 "while in user mode. Aborting\n");
1830 break;
e1833e1f
JM		 1831 case POWERPC_EXCP_TRACE: /* Trace exception */
1832 /* Nothing to do:
1833 * we use this exception to emulate step-by-step execution mode.
1834 */
1835 break;
e85e7c6e 1836 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1837 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
a47dddd7 1838 cpu_abort(cs, "Hypervisor data storage exception "
e1833e1f
JM		 1839 "while in user mode. Aborting\n");
1840 break;
1841 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
a47dddd7 1842 cpu_abort(cs, "Hypervisor instruction storage exception "
e1833e1f
JM		 1843 "while in user mode. Aborting\n");
1844 break;
1845 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
a47dddd7 1846 cpu_abort(cs, "Hypervisor data segment exception "
e1833e1f
JM		 1847 "while in user mode. Aborting\n");
1848 break;
1849 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
a47dddd7 1850 cpu_abort(cs, "Hypervisor instruction segment exception "
e1833e1f
JM		 1851 "while in user mode. Aborting\n");
1852 break;
e1833e1f
JM		 1853 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1854 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1855 info.si_signo = TARGET_SIGILL;
1856 info.si_errno = 0;
1857 info.si_code = TARGET_ILL_COPROC;
1858 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1859 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1860 break;
1861 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
a47dddd7 1862 cpu_abort(cs, "Programmable interval timer interrupt "
e1833e1f
JM		 1863 "while in user mode. Aborting\n");
1864 break;
1865 case POWERPC_EXCP_IO: /* IO error exception */
a47dddd7 1866 cpu_abort(cs, "IO error exception while in user mode. "
e1833e1f
JM		 1867 "Aborting\n");
1868 break;
1869 case POWERPC_EXCP_RUNM: /* Run mode exception */
a47dddd7 1870 cpu_abort(cs, "Run mode exception while in user mode. "
e1833e1f
JM		 1871 "Aborting\n");
1872 break;
1873 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
a47dddd7 1874 cpu_abort(cs, "Emulation trap exception not handled\n");
e1833e1f
JM		 1875 break;
1876 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
a47dddd7 1877 cpu_abort(cs, "Instruction fetch TLB exception "
e1833e1f
JM		 1878 "while in user-mode. Aborting");
1879 break;
1880 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
a47dddd7 1881 cpu_abort(cs, "Data load TLB exception while in user-mode. "
e1833e1f
JM		 1882 "Aborting");
1883 break;
1884 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
a47dddd7 1885 cpu_abort(cs, "Data store TLB exception while in user-mode. "
e1833e1f
JM		 1886 "Aborting");
1887 break;
1888 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
a47dddd7 1889 cpu_abort(cs, "Floating-point assist exception not handled\n");
e1833e1f
JM		 1890 break;
1891 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
a47dddd7 1892 cpu_abort(cs, "Instruction address breakpoint exception "
e1833e1f
JM		 1893 "not handled\n");
1894 break;
1895 case POWERPC_EXCP_SMI: /* System management interrupt */
a47dddd7 1896 cpu_abort(cs, "System management interrupt while in user mode. "
e1833e1f
JM		 1897 "Aborting\n");
1898 break;
1899 case POWERPC_EXCP_THERM: /* Thermal interrupt */
a47dddd7 1900 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
e1833e1f
JM		 1901 "Aborting\n");
1902 break;
1903 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
a47dddd7 1904 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1905 break;
1906 case POWERPC_EXCP_VPUA: /* Vector assist exception */
a47dddd7 1907 cpu_abort(cs, "Vector assist exception not handled\n");
e1833e1f
JM		 1908 break;
1909 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
a47dddd7 1910 cpu_abort(cs, "Soft patch exception not handled\n");
e1833e1f
JM		 1911 break;
1912 case POWERPC_EXCP_MAINT: /* Maintenance exception */
a47dddd7 1913 cpu_abort(cs, "Maintenance exception while in user mode. "
e1833e1f
JM		 1914 "Aborting\n");
1915 break;
1916 case POWERPC_EXCP_STOP: /* stop translation */
1917 /* We did invalidate the instruction cache. Go on */
1918 break;
1919 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1920 /* We just stopped because of a branch. Go on */
1921 break;
1922 case POWERPC_EXCP_SYSCALL_USER:
1923 /* system call in user-mode emulation */
1924 /* WARNING:
1925 * PPC ABI uses overflow flag in cr0 to signal an error
1926 * in syscalls.
1927 */
e1833e1f
JM		 1928 env->crf[0] &= ~0x1;
1929 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1930 env->gpr[5], env->gpr[6], env->gpr[7],
5945cfcb 1931 env->gpr[8], 0, 0);
9e0e2f96 1932 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
bcd4933a
NF		 1933 /* Returning from a successful sigreturn syscall.
1934 Avoid corrupting register state. */
1935 break;
1936 }
9e0e2f96 1937 if (ret > (target_ulong)(-515)) {
e1833e1f
JM		 1938 env->crf[0] |= 0x1;
1939 ret = -ret;
61190b14 1940 }
e1833e1f 1941 env->gpr[3] = ret;
e1833e1f 1942 break;
56f066bb
NF		 1943 case POWERPC_EXCP_STCX:
1944 if (do_store_exclusive(env)) {
1945 info.si_signo = TARGET_SIGSEGV;
1946 info.si_errno = 0;
1947 info.si_code = TARGET_SEGV_MAPERR;
1948 info._sifields._sigfault._addr = env->nip;
1949 queue_signal(env, info.si_signo, &info);
1950 }
1951 break;
71f75756
AJ		 1952 case EXCP_DEBUG:
1953 {
1954 int sig;
1955
db6b81d4 1956 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
71f75756
AJ		 1957 if (sig) {
1958 info.si_signo = sig;
1959 info.si_errno = 0;
1960 info.si_code = TARGET_TRAP_BRKPT;
1961 queue_signal(env, info.si_signo, &info);
1962 }
1963 }
1964 break;
56ba31ff
JM		 1965 case EXCP_INTERRUPT:
1966 /* just indicate that signals should be handled asap */
1967 break;
e1833e1f 1968 default:
a47dddd7 1969 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
e1833e1f 1970 break;
67867308
FB		 1971 }
1972 process_pending_signals(env);
1973 }
1974}
1975#endif
1976
048f6b4d
FB		 1977#ifdef TARGET_MIPS
1978
ff4f7382
RH		 1979# ifdef TARGET_ABI_MIPSO32
1980# define MIPS_SYS(name, args) args,
048f6b4d 1981static const uint8_t mips_syscall_args[] = {
29fb0f25 1982 MIPS_SYS(sys_syscall , 8) /* 4000 */
048f6b4d
FB		 1983 MIPS_SYS(sys_exit , 1)
1984 MIPS_SYS(sys_fork , 0)
1985 MIPS_SYS(sys_read , 3)
1986 MIPS_SYS(sys_write , 3)
1987 MIPS_SYS(sys_open , 3) /* 4005 */
1988 MIPS_SYS(sys_close , 1)
1989 MIPS_SYS(sys_waitpid , 3)
1990 MIPS_SYS(sys_creat , 2)
1991 MIPS_SYS(sys_link , 2)
1992 MIPS_SYS(sys_unlink , 1) /* 4010 */
1993 MIPS_SYS(sys_execve , 0)
1994 MIPS_SYS(sys_chdir , 1)
1995 MIPS_SYS(sys_time , 1)
1996 MIPS_SYS(sys_mknod , 3)
1997 MIPS_SYS(sys_chmod , 2) /* 4015 */
1998 MIPS_SYS(sys_lchown , 3)
1999 MIPS_SYS(sys_ni_syscall , 0)
2000 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2001 MIPS_SYS(sys_lseek , 3)
2002 MIPS_SYS(sys_getpid , 0) /* 4020 */
2003 MIPS_SYS(sys_mount , 5)
868e34d7 2004 MIPS_SYS(sys_umount , 1)
048f6b4d
FB		 2005 MIPS_SYS(sys_setuid , 1)
2006 MIPS_SYS(sys_getuid , 0)
2007 MIPS_SYS(sys_stime , 1) /* 4025 */
2008 MIPS_SYS(sys_ptrace , 4)
2009 MIPS_SYS(sys_alarm , 1)
2010 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2011 MIPS_SYS(sys_pause , 0)
2012 MIPS_SYS(sys_utime , 2) /* 4030 */
2013 MIPS_SYS(sys_ni_syscall , 0)
2014 MIPS_SYS(sys_ni_syscall , 0)
2015 MIPS_SYS(sys_access , 2)
2016 MIPS_SYS(sys_nice , 1)
2017 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2018 MIPS_SYS(sys_sync , 0)
2019 MIPS_SYS(sys_kill , 2)
2020 MIPS_SYS(sys_rename , 2)
2021 MIPS_SYS(sys_mkdir , 2)
2022 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2023 MIPS_SYS(sys_dup , 1)
2024 MIPS_SYS(sys_pipe , 0)
2025 MIPS_SYS(sys_times , 1)
2026 MIPS_SYS(sys_ni_syscall , 0)
2027 MIPS_SYS(sys_brk , 1) /* 4045 */
2028 MIPS_SYS(sys_setgid , 1)
2029 MIPS_SYS(sys_getgid , 0)
2030 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2031 MIPS_SYS(sys_geteuid , 0)
2032 MIPS_SYS(sys_getegid , 0) /* 4050 */
2033 MIPS_SYS(sys_acct , 0)
868e34d7 2034 MIPS_SYS(sys_umount2 , 2)
048f6b4d
FB		 2035 MIPS_SYS(sys_ni_syscall , 0)
2036 MIPS_SYS(sys_ioctl , 3)
2037 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2038 MIPS_SYS(sys_ni_syscall , 2)
2039 MIPS_SYS(sys_setpgid , 2)
2040 MIPS_SYS(sys_ni_syscall , 0)
2041 MIPS_SYS(sys_olduname , 1)
2042 MIPS_SYS(sys_umask , 1) /* 4060 */
2043 MIPS_SYS(sys_chroot , 1)
2044 MIPS_SYS(sys_ustat , 2)
2045 MIPS_SYS(sys_dup2 , 2)
2046 MIPS_SYS(sys_getppid , 0)
2047 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2048 MIPS_SYS(sys_setsid , 0)
2049 MIPS_SYS(sys_sigaction , 3)
2050 MIPS_SYS(sys_sgetmask , 0)
2051 MIPS_SYS(sys_ssetmask , 1)
2052 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2053 MIPS_SYS(sys_setregid , 2)
2054 MIPS_SYS(sys_sigsuspend , 0)
2055 MIPS_SYS(sys_sigpending , 1)
2056 MIPS_SYS(sys_sethostname , 2)
2057 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2058 MIPS_SYS(sys_getrlimit , 2)
2059 MIPS_SYS(sys_getrusage , 2)
2060 MIPS_SYS(sys_gettimeofday, 2)
2061 MIPS_SYS(sys_settimeofday, 2)
2062 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2063 MIPS_SYS(sys_setgroups , 2)
2064 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2065 MIPS_SYS(sys_symlink , 2)
2066 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2067 MIPS_SYS(sys_readlink , 3) /* 4085 */
2068 MIPS_SYS(sys_uselib , 1)
2069 MIPS_SYS(sys_swapon , 2)
2070 MIPS_SYS(sys_reboot , 3)
2071 MIPS_SYS(old_readdir , 3)
2072 MIPS_SYS(old_mmap , 6) /* 4090 */
2073 MIPS_SYS(sys_munmap , 2)
2074 MIPS_SYS(sys_truncate , 2)
2075 MIPS_SYS(sys_ftruncate , 2)
2076 MIPS_SYS(sys_fchmod , 2)
2077 MIPS_SYS(sys_fchown , 3) /* 4095 */
2078 MIPS_SYS(sys_getpriority , 2)
2079 MIPS_SYS(sys_setpriority , 3)
2080 MIPS_SYS(sys_ni_syscall , 0)
2081 MIPS_SYS(sys_statfs , 2)
2082 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2083 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2084 MIPS_SYS(sys_socketcall , 2)
2085 MIPS_SYS(sys_syslog , 3)
2086 MIPS_SYS(sys_setitimer , 3)
2087 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2088 MIPS_SYS(sys_newstat , 2)
2089 MIPS_SYS(sys_newlstat , 2)
2090 MIPS_SYS(sys_newfstat , 2)
2091 MIPS_SYS(sys_uname , 1)
2092 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2093 MIPS_SYS(sys_vhangup , 0)
2094 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2095 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2096 MIPS_SYS(sys_wait4 , 4)
2097 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2098 MIPS_SYS(sys_sysinfo , 1)
2099 MIPS_SYS(sys_ipc , 6)
2100 MIPS_SYS(sys_fsync , 1)
2101 MIPS_SYS(sys_sigreturn , 0)
18113962 2102 MIPS_SYS(sys_clone , 6) /* 4120 */
048f6b4d
FB		 2103 MIPS_SYS(sys_setdomainname, 2)
2104 MIPS_SYS(sys_newuname , 1)
2105 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2106 MIPS_SYS(sys_adjtimex , 1)
2107 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2108 MIPS_SYS(sys_sigprocmask , 3)
2109 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2110 MIPS_SYS(sys_init_module , 5)
2111 MIPS_SYS(sys_delete_module, 1)
2112 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2113 MIPS_SYS(sys_quotactl , 0)
2114 MIPS_SYS(sys_getpgid , 1)
2115 MIPS_SYS(sys_fchdir , 1)
2116 MIPS_SYS(sys_bdflush , 2)
2117 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2118 MIPS_SYS(sys_personality , 1)
2119 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2120 MIPS_SYS(sys_setfsuid , 1)
2121 MIPS_SYS(sys_setfsgid , 1)
2122 MIPS_SYS(sys_llseek , 5) /* 4140 */
2123 MIPS_SYS(sys_getdents , 3)
2124 MIPS_SYS(sys_select , 5)
2125 MIPS_SYS(sys_flock , 2)
2126 MIPS_SYS(sys_msync , 3)
2127 MIPS_SYS(sys_readv , 3) /* 4145 */
2128 MIPS_SYS(sys_writev , 3)
2129 MIPS_SYS(sys_cacheflush , 3)
2130 MIPS_SYS(sys_cachectl , 3)
2131 MIPS_SYS(sys_sysmips , 4)
2132 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2133 MIPS_SYS(sys_getsid , 1)
2134 MIPS_SYS(sys_fdatasync , 0)
2135 MIPS_SYS(sys_sysctl , 1)
2136 MIPS_SYS(sys_mlock , 2)
2137 MIPS_SYS(sys_munlock , 2) /* 4155 */
2138 MIPS_SYS(sys_mlockall , 1)
2139 MIPS_SYS(sys_munlockall , 0)
2140 MIPS_SYS(sys_sched_setparam, 2)
2141 MIPS_SYS(sys_sched_getparam, 2)
2142 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2143 MIPS_SYS(sys_sched_getscheduler, 1)
2144 MIPS_SYS(sys_sched_yield , 0)
2145 MIPS_SYS(sys_sched_get_priority_max, 1)
2146 MIPS_SYS(sys_sched_get_priority_min, 1)
2147 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2148 MIPS_SYS(sys_nanosleep, 2)
b0932e06 2149 MIPS_SYS(sys_mremap , 5)
048f6b4d
FB		 2150 MIPS_SYS(sys_accept , 3)
2151 MIPS_SYS(sys_bind , 3)
2152 MIPS_SYS(sys_connect , 3) /* 4170 */
2153 MIPS_SYS(sys_getpeername , 3)
2154 MIPS_SYS(sys_getsockname , 3)
2155 MIPS_SYS(sys_getsockopt , 5)
2156 MIPS_SYS(sys_listen , 2)
2157 MIPS_SYS(sys_recv , 4) /* 4175 */
2158 MIPS_SYS(sys_recvfrom , 6)
2159 MIPS_SYS(sys_recvmsg , 3)
2160 MIPS_SYS(sys_send , 4)
2161 MIPS_SYS(sys_sendmsg , 3)
2162 MIPS_SYS(sys_sendto , 6) /* 4180 */
2163 MIPS_SYS(sys_setsockopt , 5)
2164 MIPS_SYS(sys_shutdown , 2)
2165 MIPS_SYS(sys_socket , 3)
2166 MIPS_SYS(sys_socketpair , 4)
2167 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2168 MIPS_SYS(sys_getresuid , 3)
2169 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2170 MIPS_SYS(sys_poll , 3)
2171 MIPS_SYS(sys_nfsservctl , 3)
2172 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2173 MIPS_SYS(sys_getresgid , 3)
2174 MIPS_SYS(sys_prctl , 5)
2175 MIPS_SYS(sys_rt_sigreturn, 0)
2176 MIPS_SYS(sys_rt_sigaction, 4)
2177 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2178 MIPS_SYS(sys_rt_sigpending, 2)
2179 MIPS_SYS(sys_rt_sigtimedwait, 4)
2180 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2181 MIPS_SYS(sys_rt_sigsuspend, 0)
2182 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2183 MIPS_SYS(sys_pwrite64 , 6)
2184 MIPS_SYS(sys_chown , 3)
2185 MIPS_SYS(sys_getcwd , 2)
2186 MIPS_SYS(sys_capget , 2)
2187 MIPS_SYS(sys_capset , 2) /* 4205 */
053ebb27 2188 MIPS_SYS(sys_sigaltstack , 2)
048f6b4d
FB		 2189 MIPS_SYS(sys_sendfile , 4)
2190 MIPS_SYS(sys_ni_syscall , 0)
2191 MIPS_SYS(sys_ni_syscall , 0)
2192 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2193 MIPS_SYS(sys_truncate64 , 4)
2194 MIPS_SYS(sys_ftruncate64 , 4)
2195 MIPS_SYS(sys_stat64 , 2)
2196 MIPS_SYS(sys_lstat64 , 2)
2197 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2198 MIPS_SYS(sys_pivot_root , 2)
2199 MIPS_SYS(sys_mincore , 3)
2200 MIPS_SYS(sys_madvise , 3)
2201 MIPS_SYS(sys_getdents64 , 3)
2202 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2203 MIPS_SYS(sys_ni_syscall , 0)
2204 MIPS_SYS(sys_gettid , 0)
2205 MIPS_SYS(sys_readahead , 5)
2206 MIPS_SYS(sys_setxattr , 5)
2207 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2208 MIPS_SYS(sys_fsetxattr , 5)
2209 MIPS_SYS(sys_getxattr , 4)
2210 MIPS_SYS(sys_lgetxattr , 4)
2211 MIPS_SYS(sys_fgetxattr , 4)
2212 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2213 MIPS_SYS(sys_llistxattr , 3)
2214 MIPS_SYS(sys_flistxattr , 3)
2215 MIPS_SYS(sys_removexattr , 2)
2216 MIPS_SYS(sys_lremovexattr, 2)
2217 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2218 MIPS_SYS(sys_tkill , 2)
2219 MIPS_SYS(sys_sendfile64 , 5)
43be1343 2220 MIPS_SYS(sys_futex , 6)
048f6b4d
FB		 2221 MIPS_SYS(sys_sched_setaffinity, 3)
2222 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2223 MIPS_SYS(sys_io_setup , 2)
2224 MIPS_SYS(sys_io_destroy , 1)
2225 MIPS_SYS(sys_io_getevents, 5)
2226 MIPS_SYS(sys_io_submit , 3)
2227 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2228 MIPS_SYS(sys_exit_group , 1)
2229 MIPS_SYS(sys_lookup_dcookie, 3)
2230 MIPS_SYS(sys_epoll_create, 1)
2231 MIPS_SYS(sys_epoll_ctl , 4)
2232 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2233 MIPS_SYS(sys_remap_file_pages, 5)
2234 MIPS_SYS(sys_set_tid_address, 1)
2235 MIPS_SYS(sys_restart_syscall, 0)
2236 MIPS_SYS(sys_fadvise64_64, 7)
2237 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2238 MIPS_SYS(sys_fstatfs64 , 2)
2239 MIPS_SYS(sys_timer_create, 3)
2240 MIPS_SYS(sys_timer_settime, 4)
2241 MIPS_SYS(sys_timer_gettime, 2)
2242 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2243 MIPS_SYS(sys_timer_delete, 1)
2244 MIPS_SYS(sys_clock_settime, 2)
2245 MIPS_SYS(sys_clock_gettime, 2)
2246 MIPS_SYS(sys_clock_getres, 2)
2247 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2248 MIPS_SYS(sys_tgkill , 3)
2249 MIPS_SYS(sys_utimes , 2)
2250 MIPS_SYS(sys_mbind , 4)
2251 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2252 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2253 MIPS_SYS(sys_mq_open , 4)
2254 MIPS_SYS(sys_mq_unlink , 1)
2255 MIPS_SYS(sys_mq_timedsend, 5)
2256 MIPS_SYS(sys_mq_timedreceive, 5)
2257 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2258 MIPS_SYS(sys_mq_getsetattr, 3)
2259 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2260 MIPS_SYS(sys_waitid , 4)
2261 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2262 MIPS_SYS(sys_add_key , 5)
388bb21a 2263 MIPS_SYS(sys_request_key, 4)
048f6b4d 2264 MIPS_SYS(sys_keyctl , 5)
6f5b89a0 2265 MIPS_SYS(sys_set_thread_area, 1)
388bb21a
TS		 2266 MIPS_SYS(sys_inotify_init, 0)
2267 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2268 MIPS_SYS(sys_inotify_rm_watch, 2)
2269 MIPS_SYS(sys_migrate_pages, 4)
2270 MIPS_SYS(sys_openat, 4)
2271 MIPS_SYS(sys_mkdirat, 3)
2272 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2273 MIPS_SYS(sys_fchownat, 5)
2274 MIPS_SYS(sys_futimesat, 3)
2275 MIPS_SYS(sys_fstatat64, 4)
2276 MIPS_SYS(sys_unlinkat, 3)
2277 MIPS_SYS(sys_renameat, 4) /* 4295 */
2278 MIPS_SYS(sys_linkat, 5)
2279 MIPS_SYS(sys_symlinkat, 3)
2280 MIPS_SYS(sys_readlinkat, 4)
2281 MIPS_SYS(sys_fchmodat, 3)
2282 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2283 MIPS_SYS(sys_pselect6, 6)
2284 MIPS_SYS(sys_ppoll, 5)
2285 MIPS_SYS(sys_unshare, 1)
b0932e06 2286 MIPS_SYS(sys_splice, 6)
388bb21a
TS		 2287 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2288 MIPS_SYS(sys_tee, 4)
2289 MIPS_SYS(sys_vmsplice, 4)
2290 MIPS_SYS(sys_move_pages, 6)
2291 MIPS_SYS(sys_set_robust_list, 2)
2292 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2293 MIPS_SYS(sys_kexec_load, 4)
2294 MIPS_SYS(sys_getcpu, 3)
2295 MIPS_SYS(sys_epoll_pwait, 6)
2296 MIPS_SYS(sys_ioprio_set, 3)
2297 MIPS_SYS(sys_ioprio_get, 2)
d979e8eb
PM		 2298 MIPS_SYS(sys_utimensat, 4)
2299 MIPS_SYS(sys_signalfd, 3)
2300 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2301 MIPS_SYS(sys_eventfd, 1)
2302 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2303 MIPS_SYS(sys_timerfd_create, 2)
2304 MIPS_SYS(sys_timerfd_gettime, 2)
2305 MIPS_SYS(sys_timerfd_settime, 4)
2306 MIPS_SYS(sys_signalfd4, 4)
2307 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2308 MIPS_SYS(sys_epoll_create1, 1)
2309 MIPS_SYS(sys_dup3, 3)
2310 MIPS_SYS(sys_pipe2, 2)
2311 MIPS_SYS(sys_inotify_init1, 1)
2312 MIPS_SYS(sys_preadv, 6) /* 4330 */
2313 MIPS_SYS(sys_pwritev, 6)
2314 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2315 MIPS_SYS(sys_perf_event_open, 5)
2316 MIPS_SYS(sys_accept4, 4)
2317 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2318 MIPS_SYS(sys_fanotify_init, 2)
2319 MIPS_SYS(sys_fanotify_mark, 6)
2320 MIPS_SYS(sys_prlimit64, 4)
2321 MIPS_SYS(sys_name_to_handle_at, 5)
2322 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2323 MIPS_SYS(sys_clock_adjtime, 2)
2324 MIPS_SYS(sys_syncfs, 1)
048f6b4d 2325};
ff4f7382
RH		 2326# undef MIPS_SYS
2327# endif /* O32 */
048f6b4d 2328
590bc601
PB		 2329static int do_store_exclusive(CPUMIPSState *env)
2330{
2331 target_ulong addr;
2332 target_ulong page_addr;
2333 target_ulong val;
2334 int flags;
2335 int segv = 0;
2336 int reg;
2337 int d;
2338
5499b6ff 2339 addr = env->lladdr;
590bc601
PB		 2340 page_addr = addr & TARGET_PAGE_MASK;
2341 start_exclusive();
2342 mmap_lock();
2343 flags = page_get_flags(page_addr);
2344 if ((flags & PAGE_READ) == 0) {
2345 segv = 1;
2346 } else {
2347 reg = env->llreg & 0x1f;
2348 d = (env->llreg & 0x20) != 0;
2349 if (d) {
2350 segv = get_user_s64(val, addr);
2351 } else {
2352 segv = get_user_s32(val, addr);
2353 }
2354 if (!segv) {
2355 if (val != env->llval) {
2356 env->active_tc.gpr[reg] = 0;
2357 } else {
2358 if (d) {
2359 segv = put_user_u64(env->llnewval, addr);
2360 } else {
2361 segv = put_user_u32(env->llnewval, addr);
2362 }
2363 if (!segv) {
2364 env->active_tc.gpr[reg] = 1;
2365 }
2366 }
2367 }
2368 }
5499b6ff 2369 env->lladdr = -1;
590bc601
PB		 2370 if (!segv) {
2371 env->active_tc.PC += 4;
2372 }
2373 mmap_unlock();
2374 end_exclusive();
2375 return segv;
2376}
2377
54b2f42c
MI		 2378/* Break codes */
2379enum {
2380 BRK_OVERFLOW = 6,
2381 BRK_DIVZERO = 7
2382};
2383
2384static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2385 unsigned int code)
2386{
2387 int ret = -1;
2388
2389 switch (code) {
2390 case BRK_OVERFLOW:
2391 case BRK_DIVZERO:
2392 info->si_signo = TARGET_SIGFPE;
2393 info->si_errno = 0;
2394 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2395 queue_signal(env, info->si_signo, &*info);
2396 ret = 0;
2397 break;
2398 default:
b51910ba
PJ		 2399 info->si_signo = TARGET_SIGTRAP;
2400 info->si_errno = 0;
2401 queue_signal(env, info->si_signo, &*info);
2402 ret = 0;
54b2f42c
MI		 2403 break;
2404 }
2405
2406 return ret;
2407}
2408
048f6b4d
FB		 2409void cpu_loop(CPUMIPSState *env)
2410{
0315c31c 2411 CPUState *cs = CPU(mips_env_get_cpu(env));
c227f099 2412 target_siginfo_t info;
ff4f7382
RH		 2413 int trapnr;
2414 abi_long ret;
2415# ifdef TARGET_ABI_MIPSO32
048f6b4d 2416 unsigned int syscall_num;
ff4f7382 2417# endif
048f6b4d
FB		 2418
2419 for(;;) {
0315c31c 2420 cpu_exec_start(cs);
ea3e9847 2421 trapnr = cpu_mips_exec(cs);
0315c31c 2422 cpu_exec_end(cs);
048f6b4d
FB		 2423 switch(trapnr) {
2424 case EXCP_SYSCALL:
b5dc7732 2425 env->active_tc.PC += 4;
ff4f7382
RH		 2426# ifdef TARGET_ABI_MIPSO32
2427 syscall_num = env->active_tc.gpr[2] - 4000;
388bb21a 2428 if (syscall_num >= sizeof(mips_syscall_args)) {
7c2f6157 2429 ret = -TARGET_ENOSYS;
388bb21a
TS		 2430 } else {
2431 int nb_args;
992f48a0
BS		 2432 abi_ulong sp_reg;
2433 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
388bb21a
TS		 2434
2435 nb_args = mips_syscall_args[syscall_num];
b5dc7732 2436 sp_reg = env->active_tc.gpr[29];
388bb21a
TS		 2437 switch (nb_args) {
2438 /* these arguments are taken from the stack */
94c19610
ACH		 2439 case 8:
2440 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2441 goto done_syscall;
2442 }
2443 case 7:
2444 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2445 goto done_syscall;
2446 }
2447 case 6:
2448 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2449 goto done_syscall;
2450 }
2451 case 5:
2452 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2453 goto done_syscall;
2454 }
388bb21a
TS		 2455 default:
2456 break;
048f6b4d 2457 }
b5dc7732
TS		 2458 ret = do_syscall(env, env->active_tc.gpr[2],
2459 env->active_tc.gpr[4],
2460 env->active_tc.gpr[5],
2461 env->active_tc.gpr[6],
2462 env->active_tc.gpr[7],
5945cfcb 2463 arg5, arg6, arg7, arg8);
388bb21a 2464 }
94c19610 2465done_syscall:
ff4f7382
RH		 2466# else
2467 ret = do_syscall(env, env->active_tc.gpr[2],
2468 env->active_tc.gpr[4], env->active_tc.gpr[5],
2469 env->active_tc.gpr[6], env->active_tc.gpr[7],
2470 env->active_tc.gpr[8], env->active_tc.gpr[9],
2471 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2472# endif /* O32 */
0b1bcb00
PB		 2473 if (ret == -TARGET_QEMU_ESIGRETURN) {
2474 /* Returning from a successful sigreturn syscall.
2475 Avoid clobbering register state. */
2476 break;
2477 }
ff4f7382 2478 if ((abi_ulong)ret >= (abi_ulong)-1133) {
b5dc7732 2479 env->active_tc.gpr[7] = 1; /* error flag */
388bb21a
TS		 2480 ret = -ret;
2481 } else {
b5dc7732 2482 env->active_tc.gpr[7] = 0; /* error flag */
048f6b4d 2483 }
b5dc7732 2484 env->active_tc.gpr[2] = ret;
048f6b4d 2485 break;
ca7c2b1b
TS		 2486 case EXCP_TLBL:
2487 case EXCP_TLBS:
e6e5bd2d
WT		 2488 case EXCP_AdEL:
2489 case EXCP_AdES:
e4474235
PB		 2490 info.si_signo = TARGET_SIGSEGV;
2491 info.si_errno = 0;
2492 /* XXX: check env->error_code */
2493 info.si_code = TARGET_SEGV_MAPERR;
2494 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2495 queue_signal(env, info.si_signo, &info);
2496 break;
6900e84b 2497 case EXCP_CpU:
048f6b4d 2498 case EXCP_RI:
bc1ad2de
FB		 2499 info.si_signo = TARGET_SIGILL;
2500 info.si_errno = 0;
2501 info.si_code = 0;
624f7979 2502 queue_signal(env, info.si_signo, &info);
048f6b4d 2503 break;
106ec879
FB		 2504 case EXCP_INTERRUPT:
2505 /* just indicate that signals should be handled asap */
2506 break;
d08b2a28
PB		 2507 case EXCP_DEBUG:
2508 {
2509 int sig;
2510
db6b81d4 2511 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d08b2a28
PB		 2512 if (sig)
2513 {
2514 info.si_signo = sig;
2515 info.si_errno = 0;
2516 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2517 queue_signal(env, info.si_signo, &info);
d08b2a28
PB		 2518 }
2519 }
2520 break;
590bc601
PB		 2521 case EXCP_SC:
2522 if (do_store_exclusive(env)) {
2523 info.si_signo = TARGET_SIGSEGV;
2524 info.si_errno = 0;
2525 info.si_code = TARGET_SEGV_MAPERR;
2526 info._sifields._sigfault._addr = env->active_tc.PC;
2527 queue_signal(env, info.si_signo, &info);
2528 }
2529 break;
853c3240
JL		 2530 case EXCP_DSPDIS:
2531 info.si_signo = TARGET_SIGILL;
2532 info.si_errno = 0;
2533 info.si_code = TARGET_ILL_ILLOPC;
2534 queue_signal(env, info.si_signo, &info);
2535 break;
54b2f42c
MI		 2536 /* The code below was inspired by the MIPS Linux kernel trap
2537 * handling code in arch/mips/kernel/traps.c.
2538 */
2539 case EXCP_BREAK:
2540 {
2541 abi_ulong trap_instr;
2542 unsigned int code;
2543
a0333817
KCY		 2544 if (env->hflags & MIPS_HFLAG_M16) {
2545 if (env->insn_flags & ASE_MICROMIPS) {
2546 /* microMIPS mode */
1308c464
KCY		 2547 ret = get_user_u16(trap_instr, env->active_tc.PC);
2548 if (ret != 0) {
2549 goto error;
2550 }
a0333817 2551
1308c464
KCY		 2552 if ((trap_instr >> 10) == 0x11) {
2553 /* 16-bit instruction */
2554 code = trap_instr & 0xf;
2555 } else {
2556 /* 32-bit instruction */
2557 abi_ulong instr_lo;
2558
2559 ret = get_user_u16(instr_lo,
2560 env->active_tc.PC + 2);
2561 if (ret != 0) {
2562 goto error;
2563 }
2564 trap_instr = (trap_instr << 16) | instr_lo;
2565 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2566 /* Unfortunately, microMIPS also suffers from
2567 the old assembler bug... */
2568 if (code >= (1 << 10)) {
2569 code >>= 10;
2570 }
2571 }
a0333817
KCY		 2572 } else {
2573 /* MIPS16e mode */
2574 ret = get_user_u16(trap_instr, env->active_tc.PC);
2575 if (ret != 0) {
2576 goto error;
2577 }
2578 code = (trap_instr >> 6) & 0x3f;
a0333817
KCY		 2579 }
2580 } else {
f01a361b 2581 ret = get_user_u32(trap_instr, env->active_tc.PC);
1308c464
KCY		 2582 if (ret != 0) {
2583 goto error;
2584 }
54b2f42c 2585
1308c464
KCY		 2586 /* As described in the original Linux kernel code, the
2587 * below checks on 'code' are to work around an old
2588 * assembly bug.
2589 */
2590 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2591 if (code >= (1 << 10)) {
2592 code >>= 10;
2593 }
54b2f42c
MI		 2594 }
2595
2596 if (do_break(env, &info, code) != 0) {
2597 goto error;
2598 }
2599 }
2600 break;
2601 case EXCP_TRAP:
2602 {
2603 abi_ulong trap_instr;
2604 unsigned int code = 0;
2605
a0333817
KCY		 2606 if (env->hflags & MIPS_HFLAG_M16) {
2607 /* microMIPS mode */
2608 abi_ulong instr[2];
2609
2610 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2611 get_user_u16(instr[1], env->active_tc.PC + 2);
2612
2613 trap_instr = (instr[0] << 16) | instr[1];
2614 } else {
f01a361b 2615 ret = get_user_u32(trap_instr, env->active_tc.PC);
a0333817
KCY		 2616 }
2617
54b2f42c
MI		 2618 if (ret != 0) {
2619 goto error;
2620 }
2621
2622 /* The immediate versions don't provide a code. */
2623 if (!(trap_instr & 0xFC000000)) {
a0333817
KCY		 2624 if (env->hflags & MIPS_HFLAG_M16) {
2625 /* microMIPS mode */
2626 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2627 } else {
2628 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2629 }
54b2f42c
MI		 2630 }
2631
2632 if (do_break(env, &info, code) != 0) {
2633 goto error;
2634 }
2635 }
2636 break;
048f6b4d 2637 default:
54b2f42c 2638error:
5fafdf24 2639 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
048f6b4d 2640 trapnr);
878096ee 2641 cpu_dump_state(cs, stderr, fprintf, 0);
048f6b4d
FB		 2642 abort();
2643 }
2644 process_pending_signals(env);
2645 }
2646}
2647#endif
2648
d962783e
JL		 2649#ifdef TARGET_OPENRISC
2650
2651void cpu_loop(CPUOpenRISCState *env)
2652{
878096ee 2653 CPUState *cs = CPU(openrisc_env_get_cpu(env));
d962783e
JL		 2654 int trapnr, gdbsig;
2655
2656 for (;;) {
b040bc9c 2657 cpu_exec_start(cs);
ea3e9847 2658 trapnr = cpu_openrisc_exec(cs);
b040bc9c 2659 cpu_exec_end(cs);
d962783e
JL		 2660 gdbsig = 0;
2661
2662 switch (trapnr) {
2663 case EXCP_RESET:
2664 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2665 exit(1);
2666 break;
2667 case EXCP_BUSERR:
2668 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
a86b3c64 2669 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2670 break;
2671 case EXCP_DPF:
2672 case EXCP_IPF:
878096ee 2673 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2674 gdbsig = TARGET_SIGSEGV;
2675 break;
2676 case EXCP_TICK:
2677 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2678 break;
2679 case EXCP_ALIGN:
2680 qemu_log("\nAlignment pc is %#x\n", env->pc);
a86b3c64 2681 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2682 break;
2683 case EXCP_ILLEGAL:
2684 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
a86b3c64 2685 gdbsig = TARGET_SIGILL;
d962783e
JL		 2686 break;
2687 case EXCP_INT:
2688 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2689 break;
2690 case EXCP_DTLBMISS:
2691 case EXCP_ITLBMISS:
2692 qemu_log("\nTLB miss\n");
2693 break;
2694 case EXCP_RANGE:
2695 qemu_log("\nRange\n");
a86b3c64 2696 gdbsig = TARGET_SIGSEGV;
d962783e
JL		 2697 break;
2698 case EXCP_SYSCALL:
2699 env->pc += 4; /* 0xc00; */
2700 env->gpr[11] = do_syscall(env,
2701 env->gpr[11], /* return value */
2702 env->gpr[3], /* r3 - r7 are params */
2703 env->gpr[4],
2704 env->gpr[5],
2705 env->gpr[6],
2706 env->gpr[7],
2707 env->gpr[8], 0, 0);
2708 break;
2709 case EXCP_FPE:
2710 qemu_log("\nFloating point error\n");
2711 break;
2712 case EXCP_TRAP:
2713 qemu_log("\nTrap\n");
a86b3c64 2714 gdbsig = TARGET_SIGTRAP;
d962783e
JL		 2715 break;
2716 case EXCP_NR:
2717 qemu_log("\nNR\n");
2718 break;
2719 default:
2720 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2721 trapnr);
878096ee 2722 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2723 gdbsig = TARGET_SIGILL;
2724 break;
2725 }
2726 if (gdbsig) {
db6b81d4 2727 gdb_handlesig(cs, gdbsig);
d962783e
JL		 2728 if (gdbsig != TARGET_SIGTRAP) {
2729 exit(1);
2730 }
2731 }
2732
2733 process_pending_signals(env);
2734 }
2735}
2736
2737#endif /* TARGET_OPENRISC */
2738
fdf9b3e8 2739#ifdef TARGET_SH4
05390248 2740void cpu_loop(CPUSH4State *env)
fdf9b3e8 2741{
878096ee 2742 CPUState *cs = CPU(sh_env_get_cpu(env));
fdf9b3e8 2743 int trapnr, ret;
c227f099 2744 target_siginfo_t info;
3b46e624 2745
fdf9b3e8 2746 while (1) {
b040bc9c 2747 cpu_exec_start(cs);
ea3e9847 2748 trapnr = cpu_sh4_exec(cs);
b040bc9c 2749 cpu_exec_end(cs);
3b46e624 2750
fdf9b3e8
FB		 2751 switch (trapnr) {
2752 case 0x160:
0b6d3ae0 2753 env->pc += 2;
5fafdf24
TS		 2754 ret = do_syscall(env,
2755 env->gregs[3],
2756 env->gregs[4],
2757 env->gregs[5],
2758 env->gregs[6],
2759 env->gregs[7],
2760 env->gregs[0],
5945cfcb
PM		 2761 env->gregs[1],
2762 0, 0);
9c2a9ea1 2763 env->gregs[0] = ret;
fdf9b3e8 2764 break;
c3b5bc8a
TS		 2765 case EXCP_INTERRUPT:
2766 /* just indicate that signals should be handled asap */
2767 break;
355fb23d
PB		 2768 case EXCP_DEBUG:
2769 {
2770 int sig;
2771
db6b81d4 2772 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
355fb23d
PB		 2773 if (sig)
2774 {
2775 info.si_signo = sig;
2776 info.si_errno = 0;
2777 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2778 queue_signal(env, info.si_signo, &info);
355fb23d
PB		 2779 }
2780 }
2781 break;
c3b5bc8a
TS		 2782 case 0xa0:
2783 case 0xc0:
a86b3c64 2784 info.si_signo = TARGET_SIGSEGV;
c3b5bc8a
TS		 2785 info.si_errno = 0;
2786 info.si_code = TARGET_SEGV_MAPERR;
2787 info._sifields._sigfault._addr = env->tea;
624f7979 2788 queue_signal(env, info.si_signo, &info);
c3b5bc8a
TS		 2789 break;
2790
fdf9b3e8
FB		 2791 default:
2792 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2793 cpu_dump_state(cs, stderr, fprintf, 0);
fdf9b3e8
FB		 2794 exit (1);
2795 }
2796 process_pending_signals (env);
2797 }
2798}
2799#endif
2800
48733d19 2801#ifdef TARGET_CRIS
05390248 2802void cpu_loop(CPUCRISState *env)
48733d19 2803{
878096ee 2804 CPUState *cs = CPU(cris_env_get_cpu(env));
48733d19 2805 int trapnr, ret;
c227f099 2806 target_siginfo_t info;
48733d19
TS		 2807
2808 while (1) {
b040bc9c 2809 cpu_exec_start(cs);
ea3e9847 2810 trapnr = cpu_cris_exec(cs);
b040bc9c 2811 cpu_exec_end(cs);
48733d19
TS		 2812 switch (trapnr) {
2813 case 0xaa:
2814 {
a86b3c64 2815 info.si_signo = TARGET_SIGSEGV;
48733d19
TS		 2816 info.si_errno = 0;
2817 /* XXX: check env->error_code */
2818 info.si_code = TARGET_SEGV_MAPERR;
e00c1e71 2819 info._sifields._sigfault._addr = env->pregs[PR_EDA];
624f7979 2820 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2821 }
2822 break;
b6d3abda
EI		 2823 case EXCP_INTERRUPT:
2824 /* just indicate that signals should be handled asap */
2825 break;
48733d19
TS		 2826 case EXCP_BREAK:
2827 ret = do_syscall(env,
2828 env->regs[9],
2829 env->regs[10],
2830 env->regs[11],
2831 env->regs[12],
2832 env->regs[13],
2833 env->pregs[7],
5945cfcb
PM		 2834 env->pregs[11],
2835 0, 0);
48733d19 2836 env->regs[10] = ret;
48733d19
TS		 2837 break;
2838 case EXCP_DEBUG:
2839 {
2840 int sig;
2841
db6b81d4 2842 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
48733d19
TS		 2843 if (sig)
2844 {
2845 info.si_signo = sig;
2846 info.si_errno = 0;
2847 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2848 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2849 }
2850 }
2851 break;
2852 default:
2853 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2854 cpu_dump_state(cs, stderr, fprintf, 0);
48733d19
TS		 2855 exit (1);
2856 }
2857 process_pending_signals (env);
2858 }
2859}
2860#endif
2861
b779e29e 2862#ifdef TARGET_MICROBLAZE
05390248 2863void cpu_loop(CPUMBState *env)
b779e29e 2864{
878096ee 2865 CPUState *cs = CPU(mb_env_get_cpu(env));
b779e29e 2866 int trapnr, ret;
c227f099 2867 target_siginfo_t info;
b779e29e
EI		 2868
2869 while (1) {
b040bc9c 2870 cpu_exec_start(cs);
ea3e9847 2871 trapnr = cpu_mb_exec(cs);
b040bc9c 2872 cpu_exec_end(cs);
b779e29e
EI		 2873 switch (trapnr) {
2874 case 0xaa:
2875 {
a86b3c64 2876 info.si_signo = TARGET_SIGSEGV;
b779e29e
EI		 2877 info.si_errno = 0;
2878 /* XXX: check env->error_code */
2879 info.si_code = TARGET_SEGV_MAPERR;
2880 info._sifields._sigfault._addr = 0;
2881 queue_signal(env, info.si_signo, &info);
2882 }
2883 break;
2884 case EXCP_INTERRUPT:
2885 /* just indicate that signals should be handled asap */
2886 break;
2887 case EXCP_BREAK:
2888 /* Return address is 4 bytes after the call. */
2889 env->regs[14] += 4;
d7dce494 2890 env->sregs[SR_PC] = env->regs[14];
b779e29e
EI		 2891 ret = do_syscall(env,
2892 env->regs[12],
2893 env->regs[5],
2894 env->regs[6],
2895 env->regs[7],
2896 env->regs[8],
2897 env->regs[9],
5945cfcb
PM		 2898 env->regs[10],
2899 0, 0);
b779e29e 2900 env->regs[3] = ret;
b779e29e 2901 break;
b76da7e3
EI		 2902 case EXCP_HW_EXCP:
2903 env->regs[17] = env->sregs[SR_PC] + 4;
2904 if (env->iflags & D_FLAG) {
2905 env->sregs[SR_ESR] |= 1 << 12;
2906 env->sregs[SR_PC] -= 4;
b4916d7b 2907 /* FIXME: if branch was immed, replay the imm as well. */
b76da7e3
EI		 2908 }
2909
2910 env->iflags &= ~(IMM_FLAG | D_FLAG);
2911
2912 switch (env->sregs[SR_ESR] & 31) {
22a78d64 2913 case ESR_EC_DIVZERO:
a86b3c64 2914 info.si_signo = TARGET_SIGFPE;
22a78d64
EI		 2915 info.si_errno = 0;
2916 info.si_code = TARGET_FPE_FLTDIV;
2917 info._sifields._sigfault._addr = 0;
2918 queue_signal(env, info.si_signo, &info);
2919 break;
b76da7e3 2920 case ESR_EC_FPU:
a86b3c64 2921 info.si_signo = TARGET_SIGFPE;
b76da7e3
EI		 2922 info.si_errno = 0;
2923 if (env->sregs[SR_FSR] & FSR_IO) {
2924 info.si_code = TARGET_FPE_FLTINV;
2925 }
2926 if (env->sregs[SR_FSR] & FSR_DZ) {
2927 info.si_code = TARGET_FPE_FLTDIV;
2928 }
2929 info._sifields._sigfault._addr = 0;
2930 queue_signal(env, info.si_signo, &info);
2931 break;
2932 default:
2933 printf ("Unhandled hw-exception: 0x%x\n",
2e42d52d 2934 env->sregs[SR_ESR] & ESR_EC_MASK);
878096ee 2935 cpu_dump_state(cs, stderr, fprintf, 0);
b76da7e3
EI		 2936 exit (1);
2937 break;
2938 }
2939 break;
b779e29e
EI		 2940 case EXCP_DEBUG:
2941 {
2942 int sig;
2943
db6b81d4 2944 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
b779e29e
EI		 2945 if (sig)
2946 {
2947 info.si_signo = sig;
2948 info.si_errno = 0;
2949 info.si_code = TARGET_TRAP_BRKPT;
2950 queue_signal(env, info.si_signo, &info);
2951 }
2952 }
2953 break;
2954 default:
2955 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2956 cpu_dump_state(cs, stderr, fprintf, 0);
b779e29e
EI		 2957 exit (1);
2958 }
2959 process_pending_signals (env);
2960 }
2961}
2962#endif
2963
e6e5906b
PB		 2964#ifdef TARGET_M68K
2965
2966void cpu_loop(CPUM68KState *env)
2967{
878096ee 2968 CPUState *cs = CPU(m68k_env_get_cpu(env));
e6e5906b
PB		 2969 int trapnr;
2970 unsigned int n;
c227f099 2971 target_siginfo_t info;
0429a971 2972 TaskState *ts = cs->opaque;
3b46e624 2973
e6e5906b 2974 for(;;) {
b040bc9c 2975 cpu_exec_start(cs);
ea3e9847 2976 trapnr = cpu_m68k_exec(cs);
b040bc9c 2977 cpu_exec_end(cs);
e6e5906b
PB		 2978 switch(trapnr) {
2979 case EXCP_ILLEGAL:
2980 {
2981 if (ts->sim_syscalls) {
2982 uint16_t nr;
d8d5119c 2983 get_user_u16(nr, env->pc + 2);
e6e5906b
PB		 2984 env->pc += 4;
2985 do_m68k_simcall(env, nr);
2986 } else {
2987 goto do_sigill;
2988 }
2989 }
2990 break;
a87295e8 2991 case EXCP_HALT_INSN:
e6e5906b 2992 /* Semihosing syscall. */
a87295e8 2993 env->pc += 4;
e6e5906b
PB		 2994 do_m68k_semihosting(env, env->dregs[0]);
2995 break;
2996 case EXCP_LINEA:
2997 case EXCP_LINEF:
2998 case EXCP_UNSUPPORTED:
2999 do_sigill:
a86b3c64 3000 info.si_signo = TARGET_SIGILL;
e6e5906b
PB		 3001 info.si_errno = 0;
3002 info.si_code = TARGET_ILL_ILLOPN;
3003 info._sifields._sigfault._addr = env->pc;
624f7979 3004 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3005 break;
3006 case EXCP_TRAP0:
3007 {
3008 ts->sim_syscalls = 0;
3009 n = env->dregs[0];
3010 env->pc += 2;
5fafdf24
TS		 3011 env->dregs[0] = do_syscall(env,
3012 n,
e6e5906b
PB		 3013 env->dregs[1],
3014 env->dregs[2],
3015 env->dregs[3],
3016 env->dregs[4],
3017 env->dregs[5],
5945cfcb
PM		 3018 env->aregs[0],
3019 0, 0);
e6e5906b
PB		 3020 }
3021 break;
3022 case EXCP_INTERRUPT:
3023 /* just indicate that signals should be handled asap */
3024 break;
3025 case EXCP_ACCESS:
3026 {
a86b3c64 3027 info.si_signo = TARGET_SIGSEGV;
e6e5906b
PB		 3028 info.si_errno = 0;
3029 /* XXX: check env->error_code */
3030 info.si_code = TARGET_SEGV_MAPERR;
3031 info._sifields._sigfault._addr = env->mmu.ar;
624f7979 3032 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3033 }
3034 break;
3035 case EXCP_DEBUG:
3036 {
3037 int sig;
3038
db6b81d4 3039 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
e6e5906b
PB		 3040 if (sig)
3041 {
3042 info.si_signo = sig;
3043 info.si_errno = 0;
3044 info.si_code = TARGET_TRAP_BRKPT;
624f7979 3045 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3046 }
3047 }
3048 break;
3049 default:
5fafdf24 3050 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
e6e5906b 3051 trapnr);
878096ee 3052 cpu_dump_state(cs, stderr, fprintf, 0);
e6e5906b
PB		 3053 abort();
3054 }
3055 process_pending_signals(env);
3056 }
3057}
3058#endif /* TARGET_M68K */
3059
7a3148a9 3060#ifdef TARGET_ALPHA
6910b8f6
RH		 3061static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3062{
3063 target_ulong addr, val, tmp;
3064 target_siginfo_t info;
3065 int ret = 0;
3066
3067 addr = env->lock_addr;
3068 tmp = env->lock_st_addr;
3069 env->lock_addr = -1;
3070 env->lock_st_addr = 0;
3071
3072 start_exclusive();
3073 mmap_lock();
3074
3075 if (addr == tmp) {
3076 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3077 goto do_sigsegv;
3078 }
3079
3080 if (val == env->lock_value) {
3081 tmp = env->ir[reg];
3082 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3083 goto do_sigsegv;
3084 }
3085 ret = 1;
3086 }
3087 }
3088 env->ir[reg] = ret;
3089 env->pc += 4;
3090
3091 mmap_unlock();
3092 end_exclusive();
3093 return;
3094
3095 do_sigsegv:
3096 mmap_unlock();
3097 end_exclusive();
3098
3099 info.si_signo = TARGET_SIGSEGV;
3100 info.si_errno = 0;
3101 info.si_code = TARGET_SEGV_MAPERR;
3102 info._sifields._sigfault._addr = addr;
3103 queue_signal(env, TARGET_SIGSEGV, &info);
3104}
3105
05390248 3106void cpu_loop(CPUAlphaState *env)
7a3148a9 3107{
878096ee 3108 CPUState *cs = CPU(alpha_env_get_cpu(env));
e96efcfc 3109 int trapnr;
c227f099 3110 target_siginfo_t info;
6049f4f8 3111 abi_long sysret;
3b46e624 3112
7a3148a9 3113 while (1) {
b040bc9c 3114 cpu_exec_start(cs);
ea3e9847 3115 trapnr = cpu_alpha_exec(cs);
b040bc9c 3116 cpu_exec_end(cs);
3b46e624 3117
ac316ca4
RH		 3118 /* All of the traps imply a transition through PALcode, which
3119 implies an REI instruction has been executed. Which means
3120 that the intr_flag should be cleared. */
3121 env->intr_flag = 0;
3122
7a3148a9
JM		 3123 switch (trapnr) {
3124 case EXCP_RESET:
3125 fprintf(stderr, "Reset requested. Exit\n");
3126 exit(1);
3127 break;
3128 case EXCP_MCHK:
3129 fprintf(stderr, "Machine check exception. Exit\n");
3130 exit(1);
3131 break;
07b6c13b
RH		 3132 case EXCP_SMP_INTERRUPT:
3133 case EXCP_CLK_INTERRUPT:
3134 case EXCP_DEV_INTERRUPT:
5fafdf24 3135 fprintf(stderr, "External interrupt. Exit\n");
7a3148a9
JM		 3136 exit(1);
3137 break;
07b6c13b 3138 case EXCP_MMFAULT:
6910b8f6 3139 env->lock_addr = -1;
6049f4f8
RH		 3140 info.si_signo = TARGET_SIGSEGV;
3141 info.si_errno = 0;
129d8aa5 3142 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
0be1d07c 3143 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
129d8aa5 3144 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3145 queue_signal(env, info.si_signo, &info);
7a3148a9 3146 break;
7a3148a9 3147 case EXCP_UNALIGN:
6910b8f6 3148 env->lock_addr = -1;
6049f4f8
RH		 3149 info.si_signo = TARGET_SIGBUS;
3150 info.si_errno = 0;
3151 info.si_code = TARGET_BUS_ADRALN;
129d8aa5 3152 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3153 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3154 break;
3155 case EXCP_OPCDEC:
6049f4f8 3156 do_sigill:
6910b8f6 3157 env->lock_addr = -1;
6049f4f8
RH		 3158 info.si_signo = TARGET_SIGILL;
3159 info.si_errno = 0;
3160 info.si_code = TARGET_ILL_ILLOPC;
3161 info._sifields._sigfault._addr = env->pc;
3162 queue_signal(env, info.si_signo, &info);
7a3148a9 3163 break;
07b6c13b
RH		 3164 case EXCP_ARITH:
3165 env->lock_addr = -1;
3166 info.si_signo = TARGET_SIGFPE;
3167 info.si_errno = 0;
3168 info.si_code = TARGET_FPE_FLTINV;
3169 info._sifields._sigfault._addr = env->pc;
3170 queue_signal(env, info.si_signo, &info);
3171 break;
7a3148a9 3172 case EXCP_FEN:
6049f4f8 3173 /* No-op. Linux simply re-enables the FPU. */
7a3148a9 3174 break;
07b6c13b 3175 case EXCP_CALL_PAL:
6910b8f6 3176 env->lock_addr = -1;
07b6c13b 3177 switch (env->error_code) {
6049f4f8
RH		 3178 case 0x80:
3179 /* BPT */
3180 info.si_signo = TARGET_SIGTRAP;
3181 info.si_errno = 0;
3182 info.si_code = TARGET_TRAP_BRKPT;
3183 info._sifields._sigfault._addr = env->pc;
3184 queue_signal(env, info.si_signo, &info);
3185 break;
3186 case 0x81:
3187 /* BUGCHK */
3188 info.si_signo = TARGET_SIGTRAP;
3189 info.si_errno = 0;
3190 info.si_code = 0;
3191 info._sifields._sigfault._addr = env->pc;
3192 queue_signal(env, info.si_signo, &info);
3193 break;
3194 case 0x83:
3195 /* CALLSYS */
3196 trapnr = env->ir[IR_V0];
3197 sysret = do_syscall(env, trapnr,
3198 env->ir[IR_A0], env->ir[IR_A1],
3199 env->ir[IR_A2], env->ir[IR_A3],
5945cfcb
PM		 3200 env->ir[IR_A4], env->ir[IR_A5],
3201 0, 0);
a5b3b13b
RH		 3202 if (trapnr == TARGET_NR_sigreturn
3203 || trapnr == TARGET_NR_rt_sigreturn) {
3204 break;
3205 }
3206 /* Syscall writes 0 to V0 to bypass error check, similar
0e141977
RH		 3207 to how this is handled internal to Linux kernel.
3208 (Ab)use trapnr temporarily as boolean indicating error. */
3209 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3210 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3211 env->ir[IR_A3] = trapnr;
6049f4f8
RH		 3212 break;
3213 case 0x86:
3214 /* IMB */
3215 /* ??? We can probably elide the code using page_unprotect
3216 that is checking for self-modifying code. Instead we
3217 could simply call tb_flush here. Until we work out the
3218 changes required to turn off the extra write protection,
3219 this can be a no-op. */
3220 break;
3221 case 0x9E:
3222 /* RDUNIQUE */
3223 /* Handled in the translator for usermode. */
3224 abort();
3225 case 0x9F:
3226 /* WRUNIQUE */
3227 /* Handled in the translator for usermode. */
3228 abort();
3229 case 0xAA:
3230 /* GENTRAP */
3231 info.si_signo = TARGET_SIGFPE;
3232 switch (env->ir[IR_A0]) {
3233 case TARGET_GEN_INTOVF:
3234 info.si_code = TARGET_FPE_INTOVF;
3235 break;
3236 case TARGET_GEN_INTDIV:
3237 info.si_code = TARGET_FPE_INTDIV;
3238 break;
3239 case TARGET_GEN_FLTOVF:
3240 info.si_code = TARGET_FPE_FLTOVF;
3241 break;
3242 case TARGET_GEN_FLTUND:
3243 info.si_code = TARGET_FPE_FLTUND;
3244 break;
3245 case TARGET_GEN_FLTINV:
3246 info.si_code = TARGET_FPE_FLTINV;
3247 break;
3248 case TARGET_GEN_FLTINE:
3249 info.si_code = TARGET_FPE_FLTRES;
3250 break;
3251 case TARGET_GEN_ROPRAND:
3252 info.si_code = 0;
3253 break;
3254 default:
3255 info.si_signo = TARGET_SIGTRAP;
3256 info.si_code = 0;
3257 break;
3258 }
3259 info.si_errno = 0;
3260 info._sifields._sigfault._addr = env->pc;
3261 queue_signal(env, info.si_signo, &info);
3262 break;
3263 default:
3264 goto do_sigill;
3265 }
7a3148a9 3266 break;
7a3148a9 3267 case EXCP_DEBUG:
db6b81d4 3268 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
6049f4f8 3269 if (info.si_signo) {
6910b8f6 3270 env->lock_addr = -1;
6049f4f8
RH		 3271 info.si_errno = 0;
3272 info.si_code = TARGET_TRAP_BRKPT;
3273 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3274 }
3275 break;
6910b8f6
RH		 3276 case EXCP_STL_C:
3277 case EXCP_STQ_C:
3278 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3279 break;
d0f20495
RH		 3280 case EXCP_INTERRUPT:
3281 /* Just indicate that signals should be handled asap. */
3282 break;
7a3148a9
JM		 3283 default:
3284 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3285 cpu_dump_state(cs, stderr, fprintf, 0);
7a3148a9
JM		 3286 exit (1);
3287 }
3288 process_pending_signals (env);
3289 }
3290}
3291#endif /* TARGET_ALPHA */
3292
a4c075f1
UH		 3293#ifdef TARGET_S390X
3294void cpu_loop(CPUS390XState *env)
3295{
878096ee 3296 CPUState *cs = CPU(s390_env_get_cpu(env));
d5a103cd 3297 int trapnr, n, sig;
a4c075f1 3298 target_siginfo_t info;
d5a103cd 3299 target_ulong addr;
a4c075f1
UH		 3300
3301 while (1) {
b040bc9c 3302 cpu_exec_start(cs);
ea3e9847 3303 trapnr = cpu_s390x_exec(cs);
b040bc9c 3304 cpu_exec_end(cs);
a4c075f1
UH		 3305 switch (trapnr) {
3306 case EXCP_INTERRUPT:
d5a103cd 3307 /* Just indicate that signals should be handled asap. */
a4c075f1 3308 break;
a4c075f1 3309
d5a103cd
RH		 3310 case EXCP_SVC:
3311 n = env->int_svc_code;
3312 if (!n) {
3313 /* syscalls > 255 */
3314 n = env->regs[1];
a4c075f1 3315 }
d5a103cd
RH		 3316 env->psw.addr += env->int_svc_ilen;
3317 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3318 env->regs[4], env->regs[5],
3319 env->regs[6], env->regs[7], 0, 0);
a4c075f1 3320 break;
d5a103cd
RH		 3321
3322 case EXCP_DEBUG:
db6b81d4 3323 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d5a103cd
RH		 3324 if (sig) {
3325 n = TARGET_TRAP_BRKPT;
3326 goto do_signal_pc;
a4c075f1
UH		 3327 }
3328 break;
d5a103cd
RH		 3329 case EXCP_PGM:
3330 n = env->int_pgm_code;
3331 switch (n) {
3332 case PGM_OPERATION:
3333 case PGM_PRIVILEGED:
a86b3c64 3334 sig = TARGET_SIGILL;
d5a103cd
RH		 3335 n = TARGET_ILL_ILLOPC;
3336 goto do_signal_pc;
3337 case PGM_PROTECTION:
3338 case PGM_ADDRESSING:
a86b3c64 3339 sig = TARGET_SIGSEGV;
a4c075f1 3340 /* XXX: check env->error_code */
d5a103cd
RH		 3341 n = TARGET_SEGV_MAPERR;
3342 addr = env->__excp_addr;
3343 goto do_signal;
3344 case PGM_EXECUTE:
3345 case PGM_SPECIFICATION:
3346 case PGM_SPECIAL_OP:
3347 case PGM_OPERAND:
3348 do_sigill_opn:
a86b3c64 3349 sig = TARGET_SIGILL;
d5a103cd
RH		 3350 n = TARGET_ILL_ILLOPN;
3351 goto do_signal_pc;
3352
3353 case PGM_FIXPT_OVERFLOW:
a86b3c64 3354 sig = TARGET_SIGFPE;
d5a103cd
RH		 3355 n = TARGET_FPE_INTOVF;
3356 goto do_signal_pc;
3357 case PGM_FIXPT_DIVIDE:
a86b3c64 3358 sig = TARGET_SIGFPE;
d5a103cd
RH		 3359 n = TARGET_FPE_INTDIV;
3360 goto do_signal_pc;
3361
3362 case PGM_DATA:
3363 n = (env->fpc >> 8) & 0xff;
3364 if (n == 0xff) {
3365 /* compare-and-trap */
3366 goto do_sigill_opn;
3367 } else {
3368 /* An IEEE exception, simulated or otherwise. */
3369 if (n & 0x80) {
3370 n = TARGET_FPE_FLTINV;
3371 } else if (n & 0x40) {
3372 n = TARGET_FPE_FLTDIV;
3373 } else if (n & 0x20) {
3374 n = TARGET_FPE_FLTOVF;
3375 } else if (n & 0x10) {
3376 n = TARGET_FPE_FLTUND;
3377 } else if (n & 0x08) {
3378 n = TARGET_FPE_FLTRES;
3379 } else {
3380 /* ??? Quantum exception; BFP, DFP error. */
3381 goto do_sigill_opn;
3382 }
a86b3c64 3383 sig = TARGET_SIGFPE;
d5a103cd
RH		 3384 goto do_signal_pc;
3385 }
3386
3387 default:
3388 fprintf(stderr, "Unhandled program exception: %#x\n", n);
878096ee 3389 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3390 exit(1);
a4c075f1
UH		 3391 }
3392 break;
d5a103cd
RH		 3393
3394 do_signal_pc:
3395 addr = env->psw.addr;
3396 do_signal:
3397 info.si_signo = sig;
3398 info.si_errno = 0;
3399 info.si_code = n;
3400 info._sifields._sigfault._addr = addr;
3401 queue_signal(env, info.si_signo, &info);
a4c075f1 3402 break;
d5a103cd 3403
a4c075f1 3404 default:
d5a103cd 3405 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
878096ee 3406 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3407 exit(1);
a4c075f1
UH		 3408 }
3409 process_pending_signals (env);
3410 }
3411}
3412
3413#endif /* TARGET_S390X */
3414
b16189b2
CG		 3415#ifdef TARGET_TILEGX
3416
3417static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
3418{
3419 target_siginfo_t info;
3420
3421 info.si_signo = TARGET_SIGSEGV;
3422 info.si_errno = 0;
3423 info.si_code = TARGET_SEGV_MAPERR;
3424 info._sifields._sigfault._addr = addr;
3425 queue_signal(env, info.si_signo, &info);
3426}
3427
3428static void gen_sigill_reg(CPUTLGState *env)
3429{
3430 target_siginfo_t info;
3431
3432 info.si_signo = TARGET_SIGILL;
3433 info.si_errno = 0;
3434 info.si_code = TARGET_ILL_PRVREG;
3435 info._sifields._sigfault._addr = env->pc;
3436 queue_signal(env, info.si_signo, &info);
3437}
3438
0583b233
RH		 3439static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
3440{
3441 if (unlikely(reg >= TILEGX_R_COUNT)) {
3442 switch (reg) {
3443 case TILEGX_R_SN:
3444 case TILEGX_R_ZERO:
3445 return;
3446 case TILEGX_R_IDN0:
3447 case TILEGX_R_IDN1:
3448 case TILEGX_R_UDN0:
3449 case TILEGX_R_UDN1:
3450 case TILEGX_R_UDN2:
3451 case TILEGX_R_UDN3:
3452 gen_sigill_reg(env);
3453 return;
3454 default:
3455 g_assert_not_reached();
3456 }
3457 }
3458 env->regs[reg] = val;
3459}
3460
3461/*
3462 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
3463 * memory at the address held in the first source register. If the values are
3464 * not equal, then no memory operation is performed. If the values are equal,
3465 * the 8-byte quantity from the second source register is written into memory
3466 * at the address held in the first source register. In either case, the result
3467 * of the instruction is the value read from memory. The compare and write to
3468 * memory are atomic and thus can be used for synchronization purposes. This
3469 * instruction only operates for addresses aligned to a 8-byte boundary.
3470 * Unaligned memory access causes an Unaligned Data Reference interrupt.
3471 *
3472 * Functional Description (64-bit)
3473 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
3474 * rf[Dest] = memVal;
3475 * if (memVal == SPR[CmpValueSPR])
3476 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
3477 *
3478 * Functional Description (32-bit)
3479 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
3480 * rf[Dest] = memVal;
3481 * if (memVal == signExtend32 (SPR[CmpValueSPR]))
3482 * memoryWriteWord (rf[SrcA], rf[SrcB]);
3483 *
3484 *
3485 * This function also processes exch and exch4 which need not process SPR.
3486 */
3487static void do_exch(CPUTLGState *env, bool quad, bool cmp)
3488{
3489 target_ulong addr;
3490 target_long val, sprval;
3491
3492 start_exclusive();
3493
3494 addr = env->atomic_srca;
3495 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3496 goto sigsegv_maperr;
3497 }
3498
3499 if (cmp) {
3500 if (quad) {
3501 sprval = env->spregs[TILEGX_SPR_CMPEXCH];
3502 } else {
3503 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
3504 }
3505 }
3506
3507 if (!cmp || val == sprval) {
3508 target_long valb = env->atomic_srcb;
3509 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3510 goto sigsegv_maperr;
3511 }
3512 }
3513
3514 set_regval(env, env->atomic_dstr, val);
3515 end_exclusive();
3516 return;
3517
3518 sigsegv_maperr:
3519 end_exclusive();
3520 gen_sigsegv_maperr(env, addr);
3521}
3522
3523static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
3524{
3525 int8_t write = 1;
3526 target_ulong addr;
3527 target_long val, valb;
3528
3529 start_exclusive();
3530
3531 addr = env->atomic_srca;
3532 valb = env->atomic_srcb;
3533 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3534 goto sigsegv_maperr;
3535 }
3536
3537 switch (trapnr) {
3538 case TILEGX_EXCP_OPCODE_FETCHADD:
3539 case TILEGX_EXCP_OPCODE_FETCHADD4:
3540 valb += val;
3541 break;
3542 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3543 valb += val;
3544 if (valb < 0) {
3545 write = 0;
3546 }
3547 break;
3548 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3549 valb += val;
3550 if ((int32_t)valb < 0) {
3551 write = 0;
3552 }
3553 break;
3554 case TILEGX_EXCP_OPCODE_FETCHAND:
3555 case TILEGX_EXCP_OPCODE_FETCHAND4:
3556 valb &= val;
3557 break;
3558 case TILEGX_EXCP_OPCODE_FETCHOR:
3559 case TILEGX_EXCP_OPCODE_FETCHOR4:
3560 valb |= val;
3561 break;
3562 default:
3563 g_assert_not_reached();
3564 }
3565
3566 if (write) {
3567 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3568 goto sigsegv_maperr;
3569 }
3570 }
3571
3572 set_regval(env, env->atomic_dstr, val);
3573 end_exclusive();
3574 return;
3575
3576 sigsegv_maperr:
3577 end_exclusive();
3578 gen_sigsegv_maperr(env, addr);
3579}
3580
b16189b2
CG		 3581void cpu_loop(CPUTLGState *env)
3582{
3583 CPUState *cs = CPU(tilegx_env_get_cpu(env));
3584 int trapnr;
3585
3586 while (1) {
3587 cpu_exec_start(cs);
3588 trapnr = cpu_tilegx_exec(cs);
3589 cpu_exec_end(cs);
3590 switch (trapnr) {
3591 case TILEGX_EXCP_SYSCALL:
3592 env->regs[TILEGX_R_RE] = do_syscall(env, env->regs[TILEGX_R_NR],
3593 env->regs[0], env->regs[1],
3594 env->regs[2], env->regs[3],
3595 env->regs[4], env->regs[5],
3596 env->regs[6], env->regs[7]);
3597 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(env->regs[TILEGX_R_RE])
3598 ? - env->regs[TILEGX_R_RE]
3599 : 0;
3600 break;
0583b233
RH		 3601 case TILEGX_EXCP_OPCODE_EXCH:
3602 do_exch(env, true, false);
3603 break;
3604 case TILEGX_EXCP_OPCODE_EXCH4:
3605 do_exch(env, false, false);
3606 break;
3607 case TILEGX_EXCP_OPCODE_CMPEXCH:
3608 do_exch(env, true, true);
3609 break;
3610 case TILEGX_EXCP_OPCODE_CMPEXCH4:
3611 do_exch(env, false, true);
3612 break;
3613 case TILEGX_EXCP_OPCODE_FETCHADD:
3614 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3615 case TILEGX_EXCP_OPCODE_FETCHAND:
3616 case TILEGX_EXCP_OPCODE_FETCHOR:
3617 do_fetch(env, trapnr, true);
3618 break;
3619 case TILEGX_EXCP_OPCODE_FETCHADD4:
3620 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3621 case TILEGX_EXCP_OPCODE_FETCHAND4:
3622 case TILEGX_EXCP_OPCODE_FETCHOR4:
3623 do_fetch(env, trapnr, false);
3624 break;
b16189b2
CG		 3625 case TILEGX_EXCP_REG_IDN_ACCESS:
3626 case TILEGX_EXCP_REG_UDN_ACCESS:
3627 gen_sigill_reg(env);
3628 break;
9b9dc7ac
RH		 3629 case TILEGX_EXCP_SEGV:
3630 gen_sigsegv_maperr(env, env->excaddr);
3631 break;
b16189b2
CG		 3632 default:
3633 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
3634 g_assert_not_reached();
3635 }
3636 process_pending_signals(env);
3637 }
3638}
3639
3640#endif
3641
a2247f8e 3642THREAD CPUState *thread_cpu;
59faf6d6 3643
edf8e2af
MW		 3644void task_settid(TaskState *ts)
3645{
3646 if (ts->ts_tid == 0) {
edf8e2af 3647 ts->ts_tid = (pid_t)syscall(SYS_gettid);
edf8e2af
MW		 3648 }
3649}
3650
3651void stop_all_tasks(void)
3652{
3653 /*
3654 * We trust that when using NPTL, start_exclusive()
3655 * handles thread stopping correctly.
3656 */
3657 start_exclusive();
3658}
3659
c3a92833 3660/* Assumes contents are already zeroed. */
624f7979
PB		 3661void init_task_state(TaskState *ts)
3662{
3663 int i;
3664
624f7979
PB		 3665 ts->used = 1;
3666 ts->first_free = ts->sigqueue_table;
3667 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3668 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3669 }
3670 ts->sigqueue_table[i].next = NULL;
3671}
fc9c5412 3672
30ba0ee5
AF		 3673CPUArchState *cpu_copy(CPUArchState *env)
3674{
ff4700b0 3675 CPUState *cpu = ENV_GET_CPU(env);
2994fd96 3676 CPUState *new_cpu = cpu_init(cpu_model);
61c7480f 3677 CPUArchState *new_env = new_cpu->env_ptr;
30ba0ee5
AF		 3678 CPUBreakpoint *bp;
3679 CPUWatchpoint *wp;
30ba0ee5
AF		 3680
3681 /* Reset non arch specific state */
75a34036 3682 cpu_reset(new_cpu);
30ba0ee5
AF		 3683
3684 memcpy(new_env, env, sizeof(CPUArchState));
3685
3686 /* Clone all break/watchpoints.
3687 Note: Once we support ptrace with hw-debug register access, make sure
3688 BP_CPU break/watchpoints are handled correctly on clone. */
1d085f6c
TB		 3689 QTAILQ_INIT(&new_cpu->breakpoints);
3690 QTAILQ_INIT(&new_cpu->watchpoints);
f0c3c505 3691 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
b3310ab3 3692 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
30ba0ee5 3693 }
ff4700b0 3694 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
05068c0d 3695 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
30ba0ee5 3696 }
30ba0ee5
AF		 3697
3698 return new_env;
3699}
3700
fc9c5412
JS		 3701static void handle_arg_help(const char *arg)
3702{
3703 usage();
3704}
3705
3706static void handle_arg_log(const char *arg)
3707{
3708 int mask;
fc9c5412 3709
4fde1eba 3710 mask = qemu_str_to_log_mask(arg);
fc9c5412 3711 if (!mask) {
59a6fa6e 3712 qemu_print_log_usage(stdout);
fc9c5412
JS		 3713 exit(1);
3714 }
24537a01 3715 qemu_set_log(mask);
fc9c5412
JS		 3716}
3717
50171d42
CWR		 3718static void handle_arg_log_filename(const char *arg)
3719{
9a7e5424 3720 qemu_set_log_filename(arg);
50171d42
CWR		 3721}
3722
fc9c5412
JS		 3723static void handle_arg_set_env(const char *arg)
3724{
3725 char *r, *p, *token;
3726 r = p = strdup(arg);
3727 while ((token = strsep(&p, ",")) != NULL) {
3728 if (envlist_setenv(envlist, token) != 0) {
3729 usage();
3730 }
3731 }
3732 free(r);
3733}
3734
3735static void handle_arg_unset_env(const char *arg)
3736{
3737 char *r, *p, *token;
3738 r = p = strdup(arg);
3739 while ((token = strsep(&p, ",")) != NULL) {
3740 if (envlist_unsetenv(envlist, token) != 0) {
3741 usage();
3742 }
3743 }
3744 free(r);
3745}
3746
3747static void handle_arg_argv0(const char *arg)
3748{
3749 argv0 = strdup(arg);
3750}
3751
3752static void handle_arg_stack_size(const char *arg)
3753{
3754 char *p;
3755 guest_stack_size = strtoul(arg, &p, 0);
3756 if (guest_stack_size == 0) {
3757 usage();
3758 }
3759
3760 if (*p == 'M') {
3761 guest_stack_size *= 1024 * 1024;
3762 } else if (*p == 'k' || *p == 'K') {
3763 guest_stack_size *= 1024;
3764 }
3765}
3766
3767static void handle_arg_ld_prefix(const char *arg)
3768{
3769 interp_prefix = strdup(arg);
3770}
3771
3772static void handle_arg_pagesize(const char *arg)
3773{
3774 qemu_host_page_size = atoi(arg);
3775 if (qemu_host_page_size == 0 ||
3776 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3777 fprintf(stderr, "page size must be a power of two\n");
3778 exit(1);
3779 }
3780}
3781
c5e4a5a9
MR		 3782static void handle_arg_randseed(const char *arg)
3783{
3784 unsigned long long seed;
3785
3786 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3787 fprintf(stderr, "Invalid seed number: %s\n", arg);
3788 exit(1);
3789 }
3790 srand(seed);
3791}
3792
fc9c5412
JS		 3793static void handle_arg_gdb(const char *arg)
3794{
3795 gdbstub_port = atoi(arg);
3796}
3797
3798static void handle_arg_uname(const char *arg)
3799{
3800 qemu_uname_release = strdup(arg);
3801}
3802
3803static void handle_arg_cpu(const char *arg)
3804{
3805 cpu_model = strdup(arg);
c8057f95 3806 if (cpu_model == NULL || is_help_option(cpu_model)) {
fc9c5412 3807 /* XXX: implement xxx_cpu_list for targets that still miss it */
e916cbf8
PM		 3808#if defined(cpu_list)
3809 cpu_list(stdout, &fprintf);
fc9c5412
JS		 3810#endif
3811 exit(1);
3812 }
3813}
3814
fc9c5412
JS		 3815static void handle_arg_guest_base(const char *arg)
3816{
3817 guest_base = strtol(arg, NULL, 0);
3818 have_guest_base = 1;
3819}
3820
3821static void handle_arg_reserved_va(const char *arg)
3822{
3823 char *p;
3824 int shift = 0;
3825 reserved_va = strtoul(arg, &p, 0);
3826 switch (*p) {
3827 case 'k':
3828 case 'K':
3829 shift = 10;
3830 break;
3831 case 'M':
3832 shift = 20;
3833 break;
3834 case 'G':
3835 shift = 30;
3836 break;
3837 }
3838 if (shift) {
3839 unsigned long unshifted = reserved_va;
3840 p++;
3841 reserved_va <<= shift;
3842 if (((reserved_va >> shift) != unshifted)
3843#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3844 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3845#endif
3846 ) {
3847 fprintf(stderr, "Reserved virtual address too big\n");
3848 exit(1);
3849 }
3850 }
3851 if (*p) {
3852 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3853 exit(1);
3854 }
3855}
fc9c5412
JS		 3856
3857static void handle_arg_singlestep(const char *arg)
3858{
3859 singlestep = 1;
3860}
3861
3862static void handle_arg_strace(const char *arg)
3863{
3864 do_strace = 1;
3865}
3866
3867static void handle_arg_version(const char *arg)
3868{
2e59915d 3869 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
fc9c5412 3870 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
1386d4c0 3871 exit(0);
fc9c5412
JS		 3872}
3873
3874struct qemu_argument {
3875 const char *argv;
3876 const char *env;
3877 bool has_arg;
3878 void (*handle_opt)(const char *arg);
3879 const char *example;
3880 const char *help;
3881};
3882
42644cee 3883static const struct qemu_argument arg_table[] = {
fc9c5412
JS		 3884 {"h", "", false, handle_arg_help,
3885 "", "print this help"},
3886 {"g", "QEMU_GDB", true, handle_arg_gdb,
3887 "port", "wait gdb connection to 'port'"},
3888 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3889 "path", "set the elf interpreter prefix to 'path'"},
3890 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3891 "size", "set the stack size to 'size' bytes"},
3892 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
c8057f95 3893 "model", "select CPU (-cpu help for list)"},
fc9c5412
JS		 3894 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3895 "var=value", "sets targets environment variable (see below)"},
3896 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3897 "var", "unsets targets environment variable (see below)"},
3898 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3899 "argv0", "forces target process argv[0] to be 'argv0'"},
3900 {"r", "QEMU_UNAME", true, handle_arg_uname,
3901 "uname", "set qemu uname release string to 'uname'"},
fc9c5412
JS		 3902 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3903 "address", "set guest_base address to 'address'"},
3904 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3905 "size", "reserve 'size' bytes for guest virtual address space"},
fc9c5412 3906 {"d", "QEMU_LOG", true, handle_arg_log,
989b697d
PM		 3907 "item[,...]", "enable logging of specified items "
3908 "(use '-d help' for a list of items)"},
50171d42 3909 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
989b697d 3910 "logfile", "write logs to 'logfile' (default stderr)"},
fc9c5412
JS		 3911 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3912 "pagesize", "set the host page size to 'pagesize'"},
3913 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3914 "", "run in singlestep mode"},
3915 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3916 "", "log system calls"},
c5e4a5a9
MR		 3917 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
3918 "", "Seed for pseudo-random number generator"},
fc9c5412 3919 {"version", "QEMU_VERSION", false, handle_arg_version,
1386d4c0 3920 "", "display version information and exit"},
fc9c5412
JS		 3921 {NULL, NULL, false, NULL, NULL, NULL}
3922};
3923
3924static void usage(void)
3925{
42644cee 3926 const struct qemu_argument *arginfo;
fc9c5412
JS		 3927 int maxarglen;
3928 int maxenvlen;
3929
2e59915d
PB		 3930 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3931 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
fc9c5412
JS		 3932 "\n"
3933 "Options and associated environment variables:\n"
3934 "\n");
3935
63ec54d7
PM		 3936 /* Calculate column widths. We must always have at least enough space
3937 * for the column header.
3938 */
3939 maxarglen = strlen("Argument");
3940 maxenvlen = strlen("Env-variable");
fc9c5412
JS		 3941
3942 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
63ec54d7
PM		 3943 int arglen = strlen(arginfo->argv);
3944 if (arginfo->has_arg) {
3945 arglen += strlen(arginfo->example) + 1;
3946 }
fc9c5412
JS		 3947 if (strlen(arginfo->env) > maxenvlen) {
3948 maxenvlen = strlen(arginfo->env);
3949 }
63ec54d7
PM		 3950 if (arglen > maxarglen) {
3951 maxarglen = arglen;
fc9c5412
JS		 3952 }
3953 }
3954
63ec54d7
PM		 3955 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3956 maxenvlen, "Env-variable");
fc9c5412
JS		 3957
3958 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3959 if (arginfo->has_arg) {
3960 printf("-%s %-*s %-*s %s\n", arginfo->argv,
63ec54d7
PM		 3961 (int)(maxarglen - strlen(arginfo->argv) - 1),
3962 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
fc9c5412 3963 } else {
63ec54d7 3964 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
fc9c5412
JS		 3965 maxenvlen, arginfo->env,
3966 arginfo->help);
3967 }
3968 }
3969
3970 printf("\n"
3971 "Defaults:\n"
3972 "QEMU_LD_PREFIX = %s\n"
989b697d 3973 "QEMU_STACK_SIZE = %ld byte\n",
fc9c5412 3974 interp_prefix,
989b697d 3975 guest_stack_size);
fc9c5412
JS		 3976
3977 printf("\n"
3978 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3979 "QEMU_UNSET_ENV environment variables to set and unset\n"
3980 "environment variables for the target process.\n"
3981 "It is possible to provide several variables by separating them\n"
3982 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3983 "provide the -E and -U options multiple times.\n"
3984 "The following lines are equivalent:\n"
3985 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3986 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3987 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3988 "Note that if you provide several changes to a single variable\n"
3989 "the last change will stay in effect.\n");
3990
3991 exit(1);
3992}
3993
3994static int parse_args(int argc, char **argv)
3995{
3996 const char *r;
3997 int optind;
42644cee 3998 const struct qemu_argument *arginfo;
fc9c5412
JS		 3999
4000 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4001 if (arginfo->env == NULL) {
4002 continue;
4003 }
4004
4005 r = getenv(arginfo->env);
4006 if (r != NULL) {
4007 arginfo->handle_opt(r);
4008 }
4009 }
4010
4011 optind = 1;
4012 for (;;) {
4013 if (optind >= argc) {
4014 break;
4015 }
4016 r = argv[optind];
4017 if (r[0] != '-') {
4018 break;
4019 }
4020 optind++;
4021 r++;
4022 if (!strcmp(r, "-")) {
4023 break;
4024 }
4025
4026 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4027 if (!strcmp(r, arginfo->argv)) {
fc9c5412 4028 if (arginfo->has_arg) {
1386d4c0
PM		 4029 if (optind >= argc) {
4030 usage();
4031 }
4032 arginfo->handle_opt(argv[optind]);
fc9c5412 4033 optind++;
1386d4c0
PM		 4034 } else {
4035 arginfo->handle_opt(NULL);
fc9c5412 4036 }
fc9c5412
JS		 4037 break;
4038 }
4039 }
4040
4041 /* no option matched the current argv */
4042 if (arginfo->handle_opt == NULL) {
4043 usage();
4044 }
4045 }
4046
4047 if (optind >= argc) {
4048 usage();
4049 }
4050
4051 filename = argv[optind];
4052 exec_path = argv[optind];
4053
4054 return optind;
4055}
4056
902b3d5c 4057int main(int argc, char **argv, char **envp)
31e31b8a 4058{
01ffc75b 4059 struct target_pt_regs regs1, *regs = &regs1;
31e31b8a 4060 struct image_info info1, *info = &info1;
edf8e2af 4061 struct linux_binprm bprm;
48e15fc2 4062 TaskState *ts;
9349b4f9 4063 CPUArchState *env;
db6b81d4 4064 CPUState *cpu;
586314f2 4065 int optind;
04a6dfeb 4066 char **target_environ, **wrk;
7d8cec95
AJ		 4067 char **target_argv;
4068 int target_argc;
7d8cec95 4069 int i;
fd4d81dd 4070 int ret;
03cfd8fa 4071 int execfd;
b12b6a18 4072
ce008c1f
AF		 4073 module_call_init(MODULE_INIT_QOM);
4074
04a6dfeb
AJ		 4075 if ((envlist = envlist_create()) == NULL) {
4076 (void) fprintf(stderr, "Unable to allocate envlist\n");
4077 exit(1);
4078 }
4079
4080 /* add current environment into the list */
4081 for (wrk = environ; *wrk != NULL; wrk++) {
4082 (void) envlist_setenv(envlist, *wrk);
4083 }
4084
703e0e89
RH		 4085 /* Read the stack limit from the kernel. If it's "unlimited",
4086 then we can do little else besides use the default. */
4087 {
4088 struct rlimit lim;
4089 if (getrlimit(RLIMIT_STACK, &lim) == 0
81bbe906
TY		 4090 && lim.rlim_cur != RLIM_INFINITY
4091 && lim.rlim_cur == (target_long)lim.rlim_cur) {
703e0e89
RH		 4092 guest_stack_size = lim.rlim_cur;
4093 }
4094 }
4095
b1f9be31 4096 cpu_model = NULL;
b5ec5ce0 4097#if defined(cpudef_setup)
4098 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
4099#endif
4100
c5e4a5a9
MR		 4101 srand(time(NULL));
4102
fc9c5412 4103 optind = parse_args(argc, argv);
586314f2 4104
31e31b8a 4105 /* Zero out regs */
01ffc75b 4106 memset(regs, 0, sizeof(struct target_pt_regs));
31e31b8a
FB		 4107
4108 /* Zero out image_info */
4109 memset(info, 0, sizeof(struct image_info));
4110
edf8e2af
MW		 4111 memset(&bprm, 0, sizeof (bprm));
4112
74cd30b8
FB		 4113 /* Scan interp_prefix dir for replacement files. */
4114 init_paths(interp_prefix);
4115
4a24a758
PM		 4116 init_qemu_uname_release();
4117
46027c07 4118 if (cpu_model == NULL) {
aaed909a 4119#if defined(TARGET_I386)
46027c07
FB		 4120#ifdef TARGET_X86_64
4121 cpu_model = "qemu64";
4122#else
4123 cpu_model = "qemu32";
4124#endif
aaed909a 4125#elif defined(TARGET_ARM)
088ab16c 4126 cpu_model = "any";
d2fbca94
GX		 4127#elif defined(TARGET_UNICORE32)
4128 cpu_model = "any";
aaed909a
FB		 4129#elif defined(TARGET_M68K)
4130 cpu_model = "any";
4131#elif defined(TARGET_SPARC)
4132#ifdef TARGET_SPARC64
4133 cpu_model = "TI UltraSparc II";
4134#else
4135 cpu_model = "Fujitsu MB86904";
46027c07 4136#endif
aaed909a
FB		 4137#elif defined(TARGET_MIPS)
4138#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
74797f40 4139 cpu_model = "5KEf";
aaed909a
FB		 4140#else
4141 cpu_model = "24Kf";
4142#endif
d962783e
JL		 4143#elif defined TARGET_OPENRISC
4144 cpu_model = "or1200";
aaed909a 4145#elif defined(TARGET_PPC)
a74029f6
RH		 4146# ifdef TARGET_PPC64
4147 cpu_model = "POWER7";
4148# else
aaed909a 4149 cpu_model = "750";
a74029f6 4150# endif
91c45a38
RH		 4151#elif defined TARGET_SH4
4152 cpu_model = TYPE_SH7785_CPU;
aaed909a
FB		 4153#else
4154 cpu_model = "any";
4155#endif
4156 }
d5ab9713 4157 tcg_exec_init(0);
83fb7adf
FB		 4158 /* NOTE: we need to init the CPU at this stage to get
4159 qemu_host_page_size */
2994fd96
EH		 4160 cpu = cpu_init(cpu_model);
4161 if (!cpu) {
aaed909a
FB		 4162 fprintf(stderr, "Unable to find CPU definition\n");
4163 exit(1);
4164 }
2994fd96 4165 env = cpu->env_ptr;
0ac46af3 4166 cpu_reset(cpu);
b55a37c9 4167
db6b81d4 4168 thread_cpu = cpu;
3b46e624 4169
b6741956
FB		 4170 if (getenv("QEMU_STRACE")) {
4171 do_strace = 1;
b92c47c1
TS		 4172 }
4173
c5e4a5a9
MR		 4174 if (getenv("QEMU_RAND_SEED")) {
4175 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4176 }
4177
04a6dfeb
AJ		 4178 target_environ = envlist_to_environ(envlist, NULL);
4179 envlist_free(envlist);
b12b6a18 4180
379f6698
PB		 4181 /*
4182 * Now that page sizes are configured in cpu_init() we can do
4183 * proper page alignment for guest_base.
4184 */
4185 guest_base = HOST_PAGE_ALIGN(guest_base);
68a1c816 4186
806d1021
MI		 4187 if (reserved_va || have_guest_base) {
4188 guest_base = init_guest_space(guest_base, reserved_va, 0,
4189 have_guest_base);
4190 if (guest_base == (unsigned long)-1) {
097b8cb8
PM		 4191 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
4192 "space for use as guest address space (check your virtual "
4193 "memory ulimit setting or reserve less using -R option)\n",
4194 reserved_va);
68a1c816
PB		 4195 exit(1);
4196 }
97cc7560 4197
806d1021
MI		 4198 if (reserved_va) {
4199 mmap_next_start = reserved_va;
97cc7560
DDAG		 4200 }
4201 }
379f6698
PB		 4202
4203 /*
4204 * Read in mmap_min_addr kernel parameter. This value is used
4205 * When loading the ELF image to determine whether guest_base
14f24e14 4206 * is needed. It is also used in mmap_find_vma.
379f6698 4207 */
14f24e14 4208 {
379f6698
PB		 4209 FILE *fp;
4210
4211 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
4212 unsigned long tmp;
4213 if (fscanf(fp, "%lu", &tmp) == 1) {
4214 mmap_min_addr = tmp;
4215 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
4216 }
4217 fclose(fp);
4218 }
4219 }
379f6698 4220
7d8cec95
AJ		 4221 /*
4222 * Prepare copy of argv vector for target.
4223 */
4224 target_argc = argc - optind;
4225 target_argv = calloc(target_argc + 1, sizeof (char *));
4226 if (target_argv == NULL) {
4227 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4228 exit(1);
4229 }
4230
4231 /*
4232 * If argv0 is specified (using '-0' switch) we replace
4233 * argv[0] pointer with the given one.
4234 */
4235 i = 0;
4236 if (argv0 != NULL) {
4237 target_argv[i++] = strdup(argv0);
4238 }
4239 for (; i < target_argc; i++) {
4240 target_argv[i] = strdup(argv[optind + i]);
4241 }
4242 target_argv[target_argc] = NULL;
4243
7267c094 4244 ts = g_malloc0 (sizeof(TaskState));
edf8e2af
MW		 4245 init_task_state(ts);
4246 /* build Task State */
4247 ts->info = info;
4248 ts->bprm = &bprm;
0429a971 4249 cpu->opaque = ts;
edf8e2af
MW		 4250 task_settid(ts);
4251
0b959cf5
RH		 4252 execfd = qemu_getauxval(AT_EXECFD);
4253 if (execfd == 0) {
03cfd8fa 4254 execfd = open(filename, O_RDONLY);
0b959cf5
RH		 4255 if (execfd < 0) {
4256 printf("Error while loading %s: %s\n", filename, strerror(errno));
4257 _exit(1);
4258 }
03cfd8fa
LV		 4259 }
4260
4261 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
fd4d81dd
AP		 4262 info, &bprm);
4263 if (ret != 0) {
885c1d10 4264 printf("Error while loading %s: %s\n", filename, strerror(-ret));
b12b6a18
TS		 4265 _exit(1);
4266 }
4267
4268 for (wrk = target_environ; *wrk; wrk++) {
4269 free(*wrk);
31e31b8a 4270 }
3b46e624 4271
b12b6a18
TS		 4272 free(target_environ);
4273
2e77eac6 4274 if (qemu_log_enabled()) {
379f6698 4275 qemu_log("guest_base 0x%lx\n", guest_base);
2e77eac6
BS		 4276 log_page_dump();
4277
4278 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4279 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4280 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4281 info->start_code);
4282 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4283 info->start_data);
4284 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4285 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4286 info->start_stack);
4287 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4288 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4289 }
31e31b8a 4290
53a5960a 4291 target_set_brk(info->brk);
31e31b8a 4292 syscall_init();
66fb9763 4293 signal_init();
31e31b8a 4294
9002ec79
RH		 4295 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4296 generating the prologue until now so that the prologue can take
4297 the real value of GUEST_BASE into account. */
4298 tcg_prologue_init(&tcg_ctx);
9002ec79 4299
b346ff46 4300#if defined(TARGET_I386)
3802ce26 4301 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
b98dbc90 4302 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
0514ef2f 4303 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
1bde465e
FB		 4304 env->cr[4] |= CR4_OSFXSR_MASK;
4305 env->hflags |= HF_OSFXSR_MASK;
4306 }
d2fd1af7 4307#ifndef TARGET_ABI32
4dbc422b 4308 /* enable 64 bit mode if possible */
0514ef2f 4309 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4dbc422b
FB		 4310 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4311 exit(1);
4312 }
d2fd1af7 4313 env->cr[4] |= CR4_PAE_MASK;
4dbc422b 4314 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
d2fd1af7
FB		 4315 env->hflags |= HF_LMA_MASK;
4316#endif
1bde465e 4317
415e561f
FB		 4318 /* flags setup : we activate the IRQs by default as in user mode */
4319 env->eflags |= IF_MASK;
3b46e624 4320
6dbad63e 4321 /* linux register setup */
d2fd1af7 4322#ifndef TARGET_ABI32
84409ddb
JM		 4323 env->regs[R_EAX] = regs->rax;
4324 env->regs[R_EBX] = regs->rbx;
4325 env->regs[R_ECX] = regs->rcx;
4326 env->regs[R_EDX] = regs->rdx;
4327 env->regs[R_ESI] = regs->rsi;
4328 env->regs[R_EDI] = regs->rdi;
4329 env->regs[R_EBP] = regs->rbp;
4330 env->regs[R_ESP] = regs->rsp;
4331 env->eip = regs->rip;
4332#else
0ecfa993
FB		 4333 env->regs[R_EAX] = regs->eax;
4334 env->regs[R_EBX] = regs->ebx;
4335 env->regs[R_ECX] = regs->ecx;
4336 env->regs[R_EDX] = regs->edx;
4337 env->regs[R_ESI] = regs->esi;
4338 env->regs[R_EDI] = regs->edi;
4339 env->regs[R_EBP] = regs->ebp;
4340 env->regs[R_ESP] = regs->esp;
dab2ed99 4341 env->eip = regs->eip;
84409ddb 4342#endif
31e31b8a 4343
f4beb510 4344 /* linux interrupt setup */
e441570f
AZ		 4345#ifndef TARGET_ABI32
4346 env->idt.limit = 511;
4347#else
4348 env->idt.limit = 255;
4349#endif
4350 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4351 PROT_READ|PROT_WRITE,
4352 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4353 idt_table = g2h(env->idt.base);
f4beb510
FB		 4354 set_idt(0, 0);
4355 set_idt(1, 0);
4356 set_idt(2, 0);
4357 set_idt(3, 3);
4358 set_idt(4, 3);
ec95da6c 4359 set_idt(5, 0);
f4beb510
FB		 4360 set_idt(6, 0);
4361 set_idt(7, 0);
4362 set_idt(8, 0);
4363 set_idt(9, 0);
4364 set_idt(10, 0);
4365 set_idt(11, 0);
4366 set_idt(12, 0);
4367 set_idt(13, 0);
4368 set_idt(14, 0);
4369 set_idt(15, 0);
4370 set_idt(16, 0);
4371 set_idt(17, 0);
4372 set_idt(18, 0);
4373 set_idt(19, 0);
4374 set_idt(0x80, 3);
4375
6dbad63e 4376 /* linux segment setup */
8d18e893
FB		 4377 {
4378 uint64_t *gdt_table;
e441570f
AZ		 4379 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4380 PROT_READ|PROT_WRITE,
4381 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
8d18e893 4382 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
e441570f 4383 gdt_table = g2h(env->gdt.base);
d2fd1af7 4384#ifdef TARGET_ABI32
8d18e893
FB		 4385 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4386 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4387 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
d2fd1af7
FB		 4388#else
4389 /* 64 bit code segment */
4390 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4391 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4392 DESC_L_MASK |
4393 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4394#endif
8d18e893
FB		 4395 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4396 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4397 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4398 }
6dbad63e 4399 cpu_x86_load_seg(env, R_CS, __USER_CS);
d2fd1af7
FB		 4400 cpu_x86_load_seg(env, R_SS, __USER_DS);
4401#ifdef TARGET_ABI32
6dbad63e
FB		 4402 cpu_x86_load_seg(env, R_DS, __USER_DS);
4403 cpu_x86_load_seg(env, R_ES, __USER_DS);
6dbad63e
FB		 4404 cpu_x86_load_seg(env, R_FS, __USER_DS);
4405 cpu_x86_load_seg(env, R_GS, __USER_DS);
d6eb40f6
TS		 4406 /* This hack makes Wine work... */
4407 env->segs[R_FS].selector = 0;
d2fd1af7
FB		 4408#else
4409 cpu_x86_load_seg(env, R_DS, 0);
4410 cpu_x86_load_seg(env, R_ES, 0);
4411 cpu_x86_load_seg(env, R_FS, 0);
4412 cpu_x86_load_seg(env, R_GS, 0);
4413#endif
99033cae
AG		 4414#elif defined(TARGET_AARCH64)
4415 {
4416 int i;
4417
4418 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4419 fprintf(stderr,
4420 "The selected ARM CPU does not support 64 bit mode\n");
4421 exit(1);
4422 }
4423
4424 for (i = 0; i < 31; i++) {
4425 env->xregs[i] = regs->regs[i];
4426 }
4427 env->pc = regs->pc;
4428 env->xregs[31] = regs->sp;
4429 }
b346ff46
FB		 4430#elif defined(TARGET_ARM)
4431 {
4432 int i;
b5ff1b31 4433 cpsr_write(env, regs->uregs[16], 0xffffffff);
b346ff46
FB		 4434 for(i = 0; i < 16; i++) {
4435 env->regs[i] = regs->uregs[i];
4436 }
d8fd2954
PB		 4437 /* Enable BE8. */
4438 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4439 && (info->elf_flags & EF_ARM_BE8)) {
4440 env->bswap_code = 1;
4441 }
b346ff46 4442 }
d2fbca94
GX		 4443#elif defined(TARGET_UNICORE32)
4444 {
4445 int i;
4446 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4447 for (i = 0; i < 32; i++) {
4448 env->regs[i] = regs->uregs[i];
4449 }
4450 }
93ac68bc 4451#elif defined(TARGET_SPARC)
060366c5
FB		 4452 {
4453 int i;
4454 env->pc = regs->pc;
4455 env->npc = regs->npc;
4456 env->y = regs->y;
4457 for(i = 0; i < 8; i++)
4458 env->gregs[i] = regs->u_regs[i];
4459 for(i = 0; i < 8; i++)
4460 env->regwptr[i] = regs->u_regs[i + 8];
4461 }
67867308
FB		 4462#elif defined(TARGET_PPC)
4463 {
4464 int i;
3fc6c082 4465
0411a972
JM		 4466#if defined(TARGET_PPC64)
4467#if defined(TARGET_ABI32)
4468 env->msr &= ~((target_ulong)1 << MSR_SF);
e85e7c6e 4469#else
0411a972
JM		 4470 env->msr |= (target_ulong)1 << MSR_SF;
4471#endif
84409ddb 4472#endif
67867308
FB		 4473 env->nip = regs->nip;
4474 for(i = 0; i < 32; i++) {
4475 env->gpr[i] = regs->gpr[i];
4476 }
4477 }
e6e5906b
PB		 4478#elif defined(TARGET_M68K)
4479 {
e6e5906b
PB		 4480 env->pc = regs->pc;
4481 env->dregs[0] = regs->d0;
4482 env->dregs[1] = regs->d1;
4483 env->dregs[2] = regs->d2;
4484 env->dregs[3] = regs->d3;
4485 env->dregs[4] = regs->d4;
4486 env->dregs[5] = regs->d5;
4487 env->dregs[6] = regs->d6;
4488 env->dregs[7] = regs->d7;
4489 env->aregs[0] = regs->a0;
4490 env->aregs[1] = regs->a1;
4491 env->aregs[2] = regs->a2;
4492 env->aregs[3] = regs->a3;
4493 env->aregs[4] = regs->a4;
4494 env->aregs[5] = regs->a5;
4495 env->aregs[6] = regs->a6;
4496 env->aregs[7] = regs->usp;
4497 env->sr = regs->sr;
4498 ts->sim_syscalls = 1;
4499 }
b779e29e
EI		 4500#elif defined(TARGET_MICROBLAZE)
4501 {
4502 env->regs[0] = regs->r0;
4503 env->regs[1] = regs->r1;
4504 env->regs[2] = regs->r2;
4505 env->regs[3] = regs->r3;
4506 env->regs[4] = regs->r4;
4507 env->regs[5] = regs->r5;
4508 env->regs[6] = regs->r6;
4509 env->regs[7] = regs->r7;
4510 env->regs[8] = regs->r8;
4511 env->regs[9] = regs->r9;
4512 env->regs[10] = regs->r10;
4513 env->regs[11] = regs->r11;
4514 env->regs[12] = regs->r12;
4515 env->regs[13] = regs->r13;
4516 env->regs[14] = regs->r14;
4517 env->regs[15] = regs->r15;
4518 env->regs[16] = regs->r16;
4519 env->regs[17] = regs->r17;
4520 env->regs[18] = regs->r18;
4521 env->regs[19] = regs->r19;
4522 env->regs[20] = regs->r20;
4523 env->regs[21] = regs->r21;
4524 env->regs[22] = regs->r22;
4525 env->regs[23] = regs->r23;
4526 env->regs[24] = regs->r24;
4527 env->regs[25] = regs->r25;
4528 env->regs[26] = regs->r26;
4529 env->regs[27] = regs->r27;
4530 env->regs[28] = regs->r28;
4531 env->regs[29] = regs->r29;
4532 env->regs[30] = regs->r30;
4533 env->regs[31] = regs->r31;
4534 env->sregs[SR_PC] = regs->pc;
4535 }
048f6b4d
FB		 4536#elif defined(TARGET_MIPS)
4537 {
4538 int i;
4539
4540 for(i = 0; i < 32; i++) {
b5dc7732 4541 env->active_tc.gpr[i] = regs->regs[i];
048f6b4d 4542 }
0fddbbf2
NF		 4543 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4544 if (regs->cp0_epc & 1) {
4545 env->hflags |= MIPS_HFLAG_M16;
4546 }
048f6b4d 4547 }
d962783e
JL		 4548#elif defined(TARGET_OPENRISC)
4549 {
4550 int i;
4551
4552 for (i = 0; i < 32; i++) {
4553 env->gpr[i] = regs->gpr[i];
4554 }
4555
4556 env->sr = regs->sr;
4557 env->pc = regs->pc;
4558 }
fdf9b3e8
FB		 4559#elif defined(TARGET_SH4)
4560 {
4561 int i;
4562
4563 for(i = 0; i < 16; i++) {
4564 env->gregs[i] = regs->regs[i];
4565 }
4566 env->pc = regs->pc;
4567 }
7a3148a9
JM		 4568#elif defined(TARGET_ALPHA)
4569 {
4570 int i;
4571
4572 for(i = 0; i < 28; i++) {
992f48a0 4573 env->ir[i] = ((abi_ulong *)regs)[i];
7a3148a9 4574 }
dad081ee 4575 env->ir[IR_SP] = regs->usp;
7a3148a9 4576 env->pc = regs->pc;
7a3148a9 4577 }
48733d19
TS		 4578#elif defined(TARGET_CRIS)
4579 {
4580 env->regs[0] = regs->r0;
4581 env->regs[1] = regs->r1;
4582 env->regs[2] = regs->r2;
4583 env->regs[3] = regs->r3;
4584 env->regs[4] = regs->r4;
4585 env->regs[5] = regs->r5;
4586 env->regs[6] = regs->r6;
4587 env->regs[7] = regs->r7;
4588 env->regs[8] = regs->r8;
4589 env->regs[9] = regs->r9;
4590 env->regs[10] = regs->r10;
4591 env->regs[11] = regs->r11;
4592 env->regs[12] = regs->r12;
4593 env->regs[13] = regs->r13;
4594 env->regs[14] = info->start_stack;
4595 env->regs[15] = regs->acr;
4596 env->pc = regs->erp;
4597 }
a4c075f1
UH		 4598#elif defined(TARGET_S390X)
4599 {
4600 int i;
4601 for (i = 0; i < 16; i++) {
4602 env->regs[i] = regs->gprs[i];
4603 }
4604 env->psw.mask = regs->psw.mask;
4605 env->psw.addr = regs->psw.addr;
4606 }
b16189b2
CG		 4607#elif defined(TARGET_TILEGX)
4608 {
4609 int i;
4610 for (i = 0; i < TILEGX_R_COUNT; i++) {
4611 env->regs[i] = regs->regs[i];
4612 }
4613 for (i = 0; i < TILEGX_SPR_COUNT; i++) {
4614 env->spregs[i] = 0;
4615 }
4616 env->pc = regs->pc;
4617 }
b346ff46
FB		 4618#else
4619#error unsupported target CPU
4620#endif
31e31b8a 4621
d2fbca94 4622#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
a87295e8
PB		 4623 ts->stack_base = info->start_stack;
4624 ts->heap_base = info->brk;
4625 /* This will be filled in on the first SYS_HEAPINFO call. */
4626 ts->heap_limit = 0;
4627#endif
4628
74c33bed 4629 if (gdbstub_port) {
ff7a981a
PM		 4630 if (gdbserver_start(gdbstub_port) < 0) {
4631 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4632 gdbstub_port);
4633 exit(1);
4634 }
db6b81d4 4635 gdb_handlesig(cpu, 0);
1fddef4b 4636 }
1b6b029e
FB		 4637 cpu_loop(env);
4638 /* never exits */
31e31b8a
FB		 4639 return 0;
4640}
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