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apic_common: improve readability of apic_reset_common
[mirror_qemu.git] / linux-user / main.c
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31e31b8a 1/*
93ac68bc 2 * qemu user main
5fafdf24 3 *
68d0f70e 4 * Copyright (c) 2003-2008 Fabrice Bellard
31e31b8a
FB		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
8167ee88 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31e31b8a
FB		 18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <stdarg.h>
04369ff2 22#include <string.h>
31e31b8a 23#include <errno.h>
0ecfa993 24#include <unistd.h>
e441570f 25#include <sys/mman.h>
edf8e2af 26#include <sys/syscall.h>
703e0e89 27#include <sys/resource.h>
31e31b8a 28
3ef693a0 29#include "qemu.h"
ca10f867 30#include "qemu-common.h"
2b41f10e 31#include "cpu.h"
9002ec79 32#include "tcg.h"
1de7afc9
PB		 33#include "qemu/timer.h"
34#include "qemu/envlist.h"
d8fd2954 35#include "elf.h"
04a6dfeb 36
d088d664
AJ		 37char *exec_path;
38
1b530a6d 39int singlestep;
fc9c5412
JS		 40const char *filename;
41const char *argv0;
42int gdbstub_port;
43envlist_t *envlist;
51fb256a 44static const char *cpu_model;
379f6698 45unsigned long mmap_min_addr;
14f24e14 46#if defined(CONFIG_USE_GUEST_BASE)
379f6698
PB		 47unsigned long guest_base;
48int have_guest_base;
288e65b9
AG		 49#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
50/*
51 * When running 32-on-64 we should make sure we can fit all of the possible
52 * guest address space into a contiguous chunk of virtual host memory.
53 *
54 * This way we will never overlap with our own libraries or binaries or stack
55 * or anything else that QEMU maps.
56 */
314992b1
AG		 57# ifdef TARGET_MIPS
58/* MIPS only supports 31 bits of virtual address space for user space */
59unsigned long reserved_va = 0x77000000;
60# else
288e65b9 61unsigned long reserved_va = 0xf7000000;
314992b1 62# endif
288e65b9 63#else
68a1c816 64unsigned long reserved_va;
379f6698 65#endif
288e65b9 66#endif
1b530a6d 67
fc9c5412
JS		 68static void usage(void);
69
7ee2822c 70static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
e586822a 71const char *qemu_uname_release;
586314f2 72
9de5e440
FB		 73/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
74 we allocate a bigger stack. Need a better solution, for example
75 by remapping the process stack directly at the right place */
703e0e89 76unsigned long guest_stack_size = 8 * 1024 * 1024UL;
31e31b8a
FB		 77
78void gemu_log(const char *fmt, ...)
79{
80 va_list ap;
81
82 va_start(ap, fmt);
83 vfprintf(stderr, fmt, ap);
84 va_end(ap);
85}
86
8fcd3692 87#if defined(TARGET_I386)
05390248 88int cpu_get_pic_interrupt(CPUX86State *env)
92ccca6a
FB		 89{
90 return -1;
91}
8fcd3692 92#endif
92ccca6a 93
d5975363
PB		 94/***********************************************************/
95/* Helper routines for implementing atomic operations. */
96
97/* To implement exclusive operations we force all cpus to syncronise.
98 We don't require a full sync, only that no cpus are executing guest code.
99 The alternative is to map target atomic ops onto host equivalents,
100 which requires quite a lot of per host/target work. */
c2764719 101static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
d5975363
PB		 102static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
103static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
104static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
105static int pending_cpus;
106
107/* Make sure everything is in a consistent state for calling fork(). */
108void fork_start(void)
109{
5e5f07e0 110 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 111 pthread_mutex_lock(&exclusive_lock);
d032d1b4 112 mmap_fork_start();
d5975363
PB		 113}
114
115void fork_end(int child)
116{
d032d1b4 117 mmap_fork_end(child);
d5975363 118 if (child) {
bdc44640 119 CPUState *cpu, *next_cpu;
d5975363
PB		 120 /* Child processes created by fork() only have a single thread.
121 Discard information about the parent threads. */
bdc44640
AF		 122 CPU_FOREACH_SAFE(cpu, next_cpu) {
123 if (cpu != thread_cpu) {
124 QTAILQ_REMOVE(&cpus, thread_cpu, node);
125 }
126 }
d5975363
PB		 127 pending_cpus = 0;
128 pthread_mutex_init(&exclusive_lock, NULL);
c2764719 129 pthread_mutex_init(&cpu_list_mutex, NULL);
d5975363
PB		 130 pthread_cond_init(&exclusive_cond, NULL);
131 pthread_cond_init(&exclusive_resume, NULL);
5e5f07e0 132 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
a2247f8e 133 gdbserver_fork((CPUArchState *)thread_cpu->env_ptr);
d5975363
PB		 134 } else {
135 pthread_mutex_unlock(&exclusive_lock);
5e5f07e0 136 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 137 }
d5975363
PB		 138}
139
140/* Wait for pending exclusive operations to complete. The exclusive lock
141 must be held. */
142static inline void exclusive_idle(void)
143{
144 while (pending_cpus) {
145 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
146 }
147}
148
149/* Start an exclusive operation.
150 Must only be called from outside cpu_arm_exec. */
151static inline void start_exclusive(void)
152{
0315c31c
AF		 153 CPUState *other_cpu;
154
d5975363
PB		 155 pthread_mutex_lock(&exclusive_lock);
156 exclusive_idle();
157
158 pending_cpus = 1;
159 /* Make all other cpus stop executing. */
bdc44640 160 CPU_FOREACH(other_cpu) {
0315c31c 161 if (other_cpu->running) {
d5975363 162 pending_cpus++;
60a3e17a 163 cpu_exit(other_cpu);
d5975363
PB		 164 }
165 }
166 if (pending_cpus > 1) {
167 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
168 }
169}
170
171/* Finish an exclusive operation. */
f7e61b22 172static inline void __attribute__((unused)) end_exclusive(void)
d5975363
PB		 173{
174 pending_cpus = 0;
175 pthread_cond_broadcast(&exclusive_resume);
176 pthread_mutex_unlock(&exclusive_lock);
177}
178
179/* Wait for exclusive ops to finish, and begin cpu execution. */
0315c31c 180static inline void cpu_exec_start(CPUState *cpu)
d5975363
PB		 181{
182 pthread_mutex_lock(&exclusive_lock);
183 exclusive_idle();
0315c31c 184 cpu->running = true;
d5975363
PB		 185 pthread_mutex_unlock(&exclusive_lock);
186}
187
188/* Mark cpu as not executing, and release pending exclusive ops. */
0315c31c 189static inline void cpu_exec_end(CPUState *cpu)
d5975363
PB		 190{
191 pthread_mutex_lock(&exclusive_lock);
0315c31c 192 cpu->running = false;
d5975363
PB		 193 if (pending_cpus > 1) {
194 pending_cpus--;
195 if (pending_cpus == 1) {
196 pthread_cond_signal(&exclusive_cond);
197 }
198 }
199 exclusive_idle();
200 pthread_mutex_unlock(&exclusive_lock);
201}
c2764719
PB		 202
203void cpu_list_lock(void)
204{
205 pthread_mutex_lock(&cpu_list_mutex);
206}
207
208void cpu_list_unlock(void)
209{
210 pthread_mutex_unlock(&cpu_list_mutex);
211}
d5975363
PB		 212
213
a541f297
FB		 214#ifdef TARGET_I386
215/***********************************************************/
216/* CPUX86 core interface */
217
05390248 218void cpu_smm_update(CPUX86State *env)
02a1602e
FB		 219{
220}
221
28ab0e2e
FB		 222uint64_t cpu_get_tsc(CPUX86State *env)
223{
224 return cpu_get_real_ticks();
225}
226
5fafdf24 227static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
f4beb510 228 int flags)
6dbad63e 229{
f4beb510 230 unsigned int e1, e2;
53a5960a 231 uint32_t *p;
6dbad63e
FB		 232 e1 = (addr << 16) | (limit & 0xffff);
233 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
f4beb510 234 e2 |= flags;
53a5960a 235 p = ptr;
d538e8f5 236 p[0] = tswap32(e1);
237 p[1] = tswap32(e2);
f4beb510
FB		 238}
239
e441570f 240static uint64_t *idt_table;
eb38c52c 241#ifdef TARGET_X86_64
d2fd1af7
FB		 242static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
243 uint64_t addr, unsigned int sel)
f4beb510 244{
4dbc422b 245 uint32_t *p, e1, e2;
f4beb510
FB		 246 e1 = (addr & 0xffff) | (sel << 16);
247 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
53a5960a 248 p = ptr;
4dbc422b
FB		 249 p[0] = tswap32(e1);
250 p[1] = tswap32(e2);
251 p[2] = tswap32(addr >> 32);
252 p[3] = 0;
6dbad63e 253}
d2fd1af7
FB		 254/* only dpl matters as we do only user space emulation */
255static void set_idt(int n, unsigned int dpl)
256{
257 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
258}
259#else
d2fd1af7
FB		 260static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
261 uint32_t addr, unsigned int sel)
262{
4dbc422b 263 uint32_t *p, e1, e2;
d2fd1af7
FB		 264 e1 = (addr & 0xffff) | (sel << 16);
265 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
266 p = ptr;
4dbc422b
FB		 267 p[0] = tswap32(e1);
268 p[1] = tswap32(e2);
d2fd1af7
FB		 269}
270
f4beb510
FB		 271/* only dpl matters as we do only user space emulation */
272static void set_idt(int n, unsigned int dpl)
273{
274 set_gate(idt_table + n, 0, dpl, 0, 0);
275}
d2fd1af7 276#endif
31e31b8a 277
89e957e7 278void cpu_loop(CPUX86State *env)
1b6b029e 279{
db6b81d4 280 CPUState *cs = CPU(x86_env_get_cpu(env));
bc8a22cc 281 int trapnr;
992f48a0 282 abi_ulong pc;
c227f099 283 target_siginfo_t info;
851e67a1 284
1b6b029e 285 for(;;) {
b040bc9c 286 cpu_exec_start(cs);
bc8a22cc 287 trapnr = cpu_x86_exec(env);
b040bc9c 288 cpu_exec_end(cs);
bc8a22cc 289 switch(trapnr) {
f4beb510 290 case 0x80:
d2fd1af7 291 /* linux syscall from int $0x80 */
5fafdf24
TS		 292 env->regs[R_EAX] = do_syscall(env,
293 env->regs[R_EAX],
f4beb510
FB		 294 env->regs[R_EBX],
295 env->regs[R_ECX],
296 env->regs[R_EDX],
297 env->regs[R_ESI],
298 env->regs[R_EDI],
5945cfcb
PM		 299 env->regs[R_EBP],
300 0, 0);
f4beb510 301 break;
d2fd1af7
FB		 302#ifndef TARGET_ABI32
303 case EXCP_SYSCALL:
5ba18547 304 /* linux syscall from syscall instruction */
d2fd1af7
FB		 305 env->regs[R_EAX] = do_syscall(env,
306 env->regs[R_EAX],
307 env->regs[R_EDI],
308 env->regs[R_ESI],
309 env->regs[R_EDX],
310 env->regs[10],
311 env->regs[8],
5945cfcb
PM		 312 env->regs[9],
313 0, 0);
d2fd1af7
FB		 314 break;
315#endif
f4beb510
FB		 316 case EXCP0B_NOSEG:
317 case EXCP0C_STACK:
a86b3c64 318 info.si_signo = TARGET_SIGBUS;
f4beb510
FB		 319 info.si_errno = 0;
320 info.si_code = TARGET_SI_KERNEL;
321 info._sifields._sigfault._addr = 0;
624f7979 322 queue_signal(env, info.si_signo, &info);
f4beb510 323 break;
1b6b029e 324 case EXCP0D_GPF:
d2fd1af7 325 /* XXX: potential problem if ABI32 */
84409ddb 326#ifndef TARGET_X86_64
851e67a1 327 if (env->eflags & VM_MASK) {
89e957e7 328 handle_vm86_fault(env);
84409ddb
JM		 329 } else
330#endif
331 {
a86b3c64 332 info.si_signo = TARGET_SIGSEGV;
f4beb510
FB		 333 info.si_errno = 0;
334 info.si_code = TARGET_SI_KERNEL;
335 info._sifields._sigfault._addr = 0;
624f7979 336 queue_signal(env, info.si_signo, &info);
1b6b029e
FB		 337 }
338 break;
b689bc57 339 case EXCP0E_PAGE:
a86b3c64 340 info.si_signo = TARGET_SIGSEGV;
b689bc57
FB		 341 info.si_errno = 0;
342 if (!(env->error_code & 1))
343 info.si_code = TARGET_SEGV_MAPERR;
344 else
345 info.si_code = TARGET_SEGV_ACCERR;
970a87a6 346 info._sifields._sigfault._addr = env->cr[2];
624f7979 347 queue_signal(env, info.si_signo, &info);
b689bc57 348 break;
9de5e440 349 case EXCP00_DIVZ:
84409ddb 350#ifndef TARGET_X86_64
bc8a22cc 351 if (env->eflags & VM_MASK) {
447db213 352 handle_vm86_trap(env, trapnr);
84409ddb
JM		 353 } else
354#endif
355 {
bc8a22cc 356 /* division by zero */
a86b3c64 357 info.si_signo = TARGET_SIGFPE;
bc8a22cc
FB		 358 info.si_errno = 0;
359 info.si_code = TARGET_FPE_INTDIV;
360 info._sifields._sigfault._addr = env->eip;
624f7979 361 queue_signal(env, info.si_signo, &info);
bc8a22cc 362 }
9de5e440 363 break;
01df040b 364 case EXCP01_DB:
447db213 365 case EXCP03_INT3:
84409ddb 366#ifndef TARGET_X86_64
447db213
FB		 367 if (env->eflags & VM_MASK) {
368 handle_vm86_trap(env, trapnr);
84409ddb
JM		 369 } else
370#endif
371 {
a86b3c64 372 info.si_signo = TARGET_SIGTRAP;
447db213 373 info.si_errno = 0;
01df040b 374 if (trapnr == EXCP01_DB) {
447db213
FB		 375 info.si_code = TARGET_TRAP_BRKPT;
376 info._sifields._sigfault._addr = env->eip;
377 } else {
378 info.si_code = TARGET_SI_KERNEL;
379 info._sifields._sigfault._addr = 0;
380 }
624f7979 381 queue_signal(env, info.si_signo, &info);
447db213
FB		 382 }
383 break;
9de5e440
FB		 384 case EXCP04_INTO:
385 case EXCP05_BOUND:
84409ddb 386#ifndef TARGET_X86_64
bc8a22cc 387 if (env->eflags & VM_MASK) {
447db213 388 handle_vm86_trap(env, trapnr);
84409ddb
JM		 389 } else
390#endif
391 {
a86b3c64 392 info.si_signo = TARGET_SIGSEGV;
bc8a22cc 393 info.si_errno = 0;
b689bc57 394 info.si_code = TARGET_SI_KERNEL;
bc8a22cc 395 info._sifields._sigfault._addr = 0;
624f7979 396 queue_signal(env, info.si_signo, &info);
bc8a22cc 397 }
9de5e440
FB		 398 break;
399 case EXCP06_ILLOP:
a86b3c64 400 info.si_signo = TARGET_SIGILL;
9de5e440
FB		 401 info.si_errno = 0;
402 info.si_code = TARGET_ILL_ILLOPN;
403 info._sifields._sigfault._addr = env->eip;
624f7979 404 queue_signal(env, info.si_signo, &info);
9de5e440
FB		 405 break;
406 case EXCP_INTERRUPT:
407 /* just indicate that signals should be handled asap */
408 break;
1fddef4b
FB		 409 case EXCP_DEBUG:
410 {
411 int sig;
412
db6b81d4 413 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 414 if (sig)
415 {
416 info.si_signo = sig;
417 info.si_errno = 0;
418 info.si_code = TARGET_TRAP_BRKPT;
624f7979 419 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 420 }
421 }
422 break;
1b6b029e 423 default:
970a87a6 424 pc = env->segs[R_CS].base + env->eip;
5fafdf24 425 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
bc8a22cc 426 (long)pc, trapnr);
1b6b029e
FB		 427 abort();
428 }
66fb9763 429 process_pending_signals(env);
1b6b029e
FB		 430 }
431}
b346ff46
FB		 432#endif
433
434#ifdef TARGET_ARM
435
d8fd2954
PB		 436#define get_user_code_u32(x, gaddr, doswap) \
437 ({ abi_long __r = get_user_u32((x), (gaddr)); \
438 if (!__r && (doswap)) { \
439 (x) = bswap32(x); \
440 } \
441 __r; \
442 })
443
444#define get_user_code_u16(x, gaddr, doswap) \
445 ({ abi_long __r = get_user_u16((x), (gaddr)); \
446 if (!__r && (doswap)) { \
447 (x) = bswap16(x); \
448 } \
449 __r; \
450 })
451
1861c454
PM		 452#ifdef TARGET_ABI32
453/* Commpage handling -- there is no commpage for AArch64 */
454
97cc7560
DDAG		 455/*
456 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
457 * Input:
458 * r0 = pointer to oldval
459 * r1 = pointer to newval
460 * r2 = pointer to target value
461 *
462 * Output:
463 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
464 * C set if *ptr was changed, clear if no exchange happened
465 *
466 * Note segv's in kernel helpers are a bit tricky, we can set the
467 * data address sensibly but the PC address is just the entry point.
468 */
469static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
470{
471 uint64_t oldval, newval, val;
472 uint32_t addr, cpsr;
473 target_siginfo_t info;
474
475 /* Based on the 32 bit code in do_kernel_trap */
476
477 /* XXX: This only works between threads, not between processes.
478 It's probably possible to implement this with native host
479 operations. However things like ldrex/strex are much harder so
480 there's not much point trying. */
481 start_exclusive();
482 cpsr = cpsr_read(env);
483 addr = env->regs[2];
484
485 if (get_user_u64(oldval, env->regs[0])) {
abf1172f 486 env->exception.vaddress = env->regs[0];
97cc7560
DDAG		 487 goto segv;
488 };
489
490 if (get_user_u64(newval, env->regs[1])) {
abf1172f 491 env->exception.vaddress = env->regs[1];
97cc7560
DDAG		 492 goto segv;
493 };
494
495 if (get_user_u64(val, addr)) {
abf1172f 496 env->exception.vaddress = addr;
97cc7560
DDAG		 497 goto segv;
498 }
499
500 if (val == oldval) {
501 val = newval;
502
503 if (put_user_u64(val, addr)) {
abf1172f 504 env->exception.vaddress = addr;
97cc7560
DDAG		 505 goto segv;
506 };
507
508 env->regs[0] = 0;
509 cpsr |= CPSR_C;
510 } else {
511 env->regs[0] = -1;
512 cpsr &= ~CPSR_C;
513 }
514 cpsr_write(env, cpsr, CPSR_C);
515 end_exclusive();
516 return;
517
518segv:
519 end_exclusive();
520 /* We get the PC of the entry address - which is as good as anything,
521 on a real kernel what you get depends on which mode it uses. */
a86b3c64 522 info.si_signo = TARGET_SIGSEGV;
97cc7560
DDAG		 523 info.si_errno = 0;
524 /* XXX: check env->error_code */
525 info.si_code = TARGET_SEGV_MAPERR;
abf1172f 526 info._sifields._sigfault._addr = env->exception.vaddress;
97cc7560 527 queue_signal(env, info.si_signo, &info);
97cc7560
DDAG		 528}
529
fbb4a2e3
PB		 530/* Handle a jump to the kernel code page. */
531static int
532do_kernel_trap(CPUARMState *env)
533{
534 uint32_t addr;
535 uint32_t cpsr;
536 uint32_t val;
537
538 switch (env->regs[15]) {
539 case 0xffff0fa0: /* __kernel_memory_barrier */
540 /* ??? No-op. Will need to do better for SMP. */
541 break;
542 case 0xffff0fc0: /* __kernel_cmpxchg */
d5975363
PB		 543 /* XXX: This only works between threads, not between processes.
544 It's probably possible to implement this with native host
545 operations. However things like ldrex/strex are much harder so
546 there's not much point trying. */
547 start_exclusive();
fbb4a2e3
PB		 548 cpsr = cpsr_read(env);
549 addr = env->regs[2];
550 /* FIXME: This should SEGV if the access fails. */
551 if (get_user_u32(val, addr))
552 val = ~env->regs[0];
553 if (val == env->regs[0]) {
554 val = env->regs[1];
555 /* FIXME: Check for segfaults. */
556 put_user_u32(val, addr);
557 env->regs[0] = 0;
558 cpsr |= CPSR_C;
559 } else {
560 env->regs[0] = -1;
561 cpsr &= ~CPSR_C;
562 }
563 cpsr_write(env, cpsr, CPSR_C);
d5975363 564 end_exclusive();
fbb4a2e3
PB		 565 break;
566 case 0xffff0fe0: /* __kernel_get_tls */
b8d43285 567 env->regs[0] = cpu_get_tls(env);
fbb4a2e3 568 break;
97cc7560
DDAG		 569 case 0xffff0f60: /* __kernel_cmpxchg64 */
570 arm_kernel_cmpxchg64_helper(env);
571 break;
572
fbb4a2e3
PB		 573 default:
574 return 1;
575 }
576 /* Jump back to the caller. */
577 addr = env->regs[14];
578 if (addr & 1) {
579 env->thumb = 1;
580 addr &= ~1;
581 }
582 env->regs[15] = addr;
583
584 return 0;
585}
586
fa2ef212 587/* Store exclusive handling for AArch32 */
426f5abc
PB		 588static int do_strex(CPUARMState *env)
589{
03d05e2d 590 uint64_t val;
426f5abc
PB		 591 int size;
592 int rc = 1;
593 int segv = 0;
594 uint32_t addr;
595 start_exclusive();
03d05e2d 596 if (env->exclusive_addr != env->exclusive_test) {
426f5abc
PB		 597 goto fail;
598 }
03d05e2d
PM		 599 /* We know we're always AArch32 so the address is in uint32_t range
600 * unless it was the -1 exclusive-monitor-lost value (which won't
601 * match exclusive_test above).
602 */
603 assert(extract64(env->exclusive_addr, 32, 32) == 0);
604 addr = env->exclusive_addr;
426f5abc
PB		 605 size = env->exclusive_info & 0xf;
606 switch (size) {
607 case 0:
608 segv = get_user_u8(val, addr);
609 break;
610 case 1:
611 segv = get_user_u16(val, addr);
612 break;
613 case 2:
614 case 3:
615 segv = get_user_u32(val, addr);
616 break;
f7001a3b
AJ		 617 default:
618 abort();
426f5abc
PB		 619 }
620 if (segv) {
abf1172f 621 env->exception.vaddress = addr;
426f5abc
PB		 622 goto done;
623 }
426f5abc 624 if (size == 3) {
03d05e2d
PM		 625 uint32_t valhi;
626 segv = get_user_u32(valhi, addr + 4);
426f5abc 627 if (segv) {
abf1172f 628 env->exception.vaddress = addr + 4;
426f5abc
PB		 629 goto done;
630 }
03d05e2d 631 val = deposit64(val, 32, 32, valhi);
426f5abc 632 }
03d05e2d
PM		 633 if (val != env->exclusive_val) {
634 goto fail;
635 }
636
426f5abc
PB		 637 val = env->regs[(env->exclusive_info >> 8) & 0xf];
638 switch (size) {
639 case 0:
640 segv = put_user_u8(val, addr);
641 break;
642 case 1:
643 segv = put_user_u16(val, addr);
644 break;
645 case 2:
646 case 3:
647 segv = put_user_u32(val, addr);
648 break;
649 }
650 if (segv) {
abf1172f 651 env->exception.vaddress = addr;
426f5abc
PB		 652 goto done;
653 }
654 if (size == 3) {
655 val = env->regs[(env->exclusive_info >> 12) & 0xf];
2c9adbda 656 segv = put_user_u32(val, addr + 4);
426f5abc 657 if (segv) {
abf1172f 658 env->exception.vaddress = addr + 4;
426f5abc
PB		 659 goto done;
660 }
661 }
662 rc = 0;
663fail:
725b8a69 664 env->regs[15] += 4;
426f5abc
PB		 665 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
666done:
667 end_exclusive();
668 return segv;
669}
670
b346ff46
FB		 671void cpu_loop(CPUARMState *env)
672{
0315c31c 673 CPUState *cs = CPU(arm_env_get_cpu(env));
b346ff46
FB		 674 int trapnr;
675 unsigned int n, insn;
c227f099 676 target_siginfo_t info;
b5ff1b31 677 uint32_t addr;
3b46e624 678
b346ff46 679 for(;;) {
0315c31c 680 cpu_exec_start(cs);
b346ff46 681 trapnr = cpu_arm_exec(env);
0315c31c 682 cpu_exec_end(cs);
b346ff46
FB		 683 switch(trapnr) {
684 case EXCP_UDEF:
c6981055 685 {
0429a971 686 TaskState *ts = cs->opaque;
c6981055 687 uint32_t opcode;
6d9a42be 688 int rc;
c6981055
FB		 689
690 /* we handle the FPU emulation here, as Linux */
691 /* we get the opcode */
2f619698 692 /* FIXME - what to do if get_user() fails? */
d8fd2954 693 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
3b46e624 694
6d9a42be
AJ		 695 rc = EmulateAll(opcode, &ts->fpa, env);
696 if (rc == 0) { /* illegal instruction */
a86b3c64 697 info.si_signo = TARGET_SIGILL;
c6981055
FB		 698 info.si_errno = 0;
699 info.si_code = TARGET_ILL_ILLOPN;
700 info._sifields._sigfault._addr = env->regs[15];
624f7979 701 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 702 } else if (rc < 0) { /* FP exception */
703 int arm_fpe=0;
704
705 /* translate softfloat flags to FPSR flags */
706 if (-rc & float_flag_invalid)
707 arm_fpe |= BIT_IOC;
708 if (-rc & float_flag_divbyzero)
709 arm_fpe |= BIT_DZC;
710 if (-rc & float_flag_overflow)
711 arm_fpe |= BIT_OFC;
712 if (-rc & float_flag_underflow)
713 arm_fpe |= BIT_UFC;
714 if (-rc & float_flag_inexact)
715 arm_fpe |= BIT_IXC;
716
717 FPSR fpsr = ts->fpa.fpsr;
718 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
719
720 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
a86b3c64 721 info.si_signo = TARGET_SIGFPE;
6d9a42be
AJ		 722 info.si_errno = 0;
723
724 /* ordered by priority, least first */
725 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
726 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
727 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
728 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
729 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
730
731 info._sifields._sigfault._addr = env->regs[15];
624f7979 732 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 733 } else {
734 env->regs[15] += 4;
735 }
736
737 /* accumulate unenabled exceptions */
738 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
739 fpsr |= BIT_IXC;
740 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
741 fpsr |= BIT_UFC;
742 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
743 fpsr |= BIT_OFC;
744 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
745 fpsr |= BIT_DZC;
746 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
747 fpsr |= BIT_IOC;
748 ts->fpa.fpsr=fpsr;
749 } else { /* everything OK */
c6981055
FB		 750 /* increment PC */
751 env->regs[15] += 4;
752 }
753 }
b346ff46
FB		 754 break;
755 case EXCP_SWI:
06c949e6 756 case EXCP_BKPT:
b346ff46 757 {
ce4defa0 758 env->eabi = 1;
b346ff46 759 /* system call */
06c949e6
PB		 760 if (trapnr == EXCP_BKPT) {
761 if (env->thumb) {
2f619698 762 /* FIXME - what to do if get_user() fails? */
d8fd2954 763 get_user_code_u16(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 764 n = insn & 0xff;
765 env->regs[15] += 2;
766 } else {
2f619698 767 /* FIXME - what to do if get_user() fails? */
d8fd2954 768 get_user_code_u32(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 769 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
770 env->regs[15] += 4;
771 }
192c7bd9 772 } else {
06c949e6 773 if (env->thumb) {
2f619698 774 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 775 get_user_code_u16(insn, env->regs[15] - 2,
776 env->bswap_code);
06c949e6
PB		 777 n = insn & 0xff;
778 } else {
2f619698 779 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 780 get_user_code_u32(insn, env->regs[15] - 4,
781 env->bswap_code);
06c949e6
PB		 782 n = insn & 0xffffff;
783 }
192c7bd9
FB		 784 }
785
6f1f31c0 786 if (n == ARM_NR_cacheflush) {
dcfd14b3 787 /* nop */
a4f81979
FB		 788 } else if (n == ARM_NR_semihosting
789 || n == ARM_NR_thumb_semihosting) {
790 env->regs[0] = do_arm_semihosting (env);
3a1363ac 791 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
b346ff46 792 /* linux syscall */
ce4defa0 793 if (env->thumb || n == 0) {
192c7bd9
FB		 794 n = env->regs[7];
795 } else {
796 n -= ARM_SYSCALL_BASE;
ce4defa0 797 env->eabi = 0;
192c7bd9 798 }
fbb4a2e3
PB		 799 if ( n > ARM_NR_BASE) {
800 switch (n) {
801 case ARM_NR_cacheflush:
dcfd14b3 802 /* nop */
fbb4a2e3
PB		 803 break;
804 case ARM_NR_set_tls:
805 cpu_set_tls(env, env->regs[0]);
806 env->regs[0] = 0;
807 break;
d5355087
HL		 808 case ARM_NR_breakpoint:
809 env->regs[15] -= env->thumb ? 2 : 4;
810 goto excp_debug;
fbb4a2e3
PB		 811 default:
812 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
813 n);
814 env->regs[0] = -TARGET_ENOSYS;
815 break;
816 }
817 } else {
818 env->regs[0] = do_syscall(env,
819 n,
820 env->regs[0],
821 env->regs[1],
822 env->regs[2],
823 env->regs[3],
824 env->regs[4],
5945cfcb
PM		 825 env->regs[5],
826 0, 0);
fbb4a2e3 827 }
b346ff46
FB		 828 } else {
829 goto error;
830 }
831 }
832 break;
43fff238
FB		 833 case EXCP_INTERRUPT:
834 /* just indicate that signals should be handled asap */
835 break;
abf1172f
PM		 836 case EXCP_STREX:
837 if (!do_strex(env)) {
838 break;
839 }
840 /* fall through for segv */
68016c62
FB		 841 case EXCP_PREFETCH_ABORT:
842 case EXCP_DATA_ABORT:
abf1172f 843 addr = env->exception.vaddress;
68016c62 844 {
a86b3c64 845 info.si_signo = TARGET_SIGSEGV;
68016c62
FB		 846 info.si_errno = 0;
847 /* XXX: check env->error_code */
848 info.si_code = TARGET_SEGV_MAPERR;
b5ff1b31 849 info._sifields._sigfault._addr = addr;
624f7979 850 queue_signal(env, info.si_signo, &info);
68016c62
FB		 851 }
852 break;
1fddef4b 853 case EXCP_DEBUG:
d5355087 854 excp_debug:
1fddef4b
FB		 855 {
856 int sig;
857
db6b81d4 858 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 859 if (sig)
860 {
861 info.si_signo = sig;
862 info.si_errno = 0;
863 info.si_code = TARGET_TRAP_BRKPT;
624f7979 864 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 865 }
866 }
867 break;
fbb4a2e3
PB		 868 case EXCP_KERNEL_TRAP:
869 if (do_kernel_trap(env))
870 goto error;
871 break;
b346ff46
FB		 872 default:
873 error:
5fafdf24 874 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
b346ff46 875 trapnr);
878096ee 876 cpu_dump_state(cs, stderr, fprintf, 0);
b346ff46
FB		 877 abort();
878 }
879 process_pending_signals(env);
880 }
881}
882
1861c454
PM		 883#else
884
fa2ef212
MM		 885/*
886 * Handle AArch64 store-release exclusive
887 *
888 * rs = gets the status result of store exclusive
889 * rt = is the register that is stored
890 * rt2 = is the second register store (in STP)
891 *
892 */
893static int do_strex_a64(CPUARMState *env)
894{
895 uint64_t val;
896 int size;
897 bool is_pair;
898 int rc = 1;
899 int segv = 0;
900 uint64_t addr;
901 int rs, rt, rt2;
902
903 start_exclusive();
904 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
905 size = extract32(env->exclusive_info, 0, 2);
906 is_pair = extract32(env->exclusive_info, 2, 1);
907 rs = extract32(env->exclusive_info, 4, 5);
908 rt = extract32(env->exclusive_info, 9, 5);
909 rt2 = extract32(env->exclusive_info, 14, 5);
910
911 addr = env->exclusive_addr;
912
913 if (addr != env->exclusive_test) {
914 goto finish;
915 }
916
917 switch (size) {
918 case 0:
919 segv = get_user_u8(val, addr);
920 break;
921 case 1:
922 segv = get_user_u16(val, addr);
923 break;
924 case 2:
925 segv = get_user_u32(val, addr);
926 break;
927 case 3:
928 segv = get_user_u64(val, addr);
929 break;
930 default:
931 abort();
932 }
933 if (segv) {
abf1172f 934 env->exception.vaddress = addr;
fa2ef212
MM		 935 goto error;
936 }
937 if (val != env->exclusive_val) {
938 goto finish;
939 }
940 if (is_pair) {
941 if (size == 2) {
942 segv = get_user_u32(val, addr + 4);
943 } else {
944 segv = get_user_u64(val, addr + 8);
945 }
946 if (segv) {
abf1172f 947 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 948 goto error;
949 }
950 if (val != env->exclusive_high) {
951 goto finish;
952 }
953 }
2ea5a2ca
JG		 954 /* handle the zero register */
955 val = rt == 31 ? 0 : env->xregs[rt];
fa2ef212
MM		 956 switch (size) {
957 case 0:
958 segv = put_user_u8(val, addr);
959 break;
960 case 1:
961 segv = put_user_u16(val, addr);
962 break;
963 case 2:
964 segv = put_user_u32(val, addr);
965 break;
966 case 3:
967 segv = put_user_u64(val, addr);
968 break;
969 }
970 if (segv) {
971 goto error;
972 }
973 if (is_pair) {
2ea5a2ca
JG		 974 /* handle the zero register */
975 val = rt2 == 31 ? 0 : env->xregs[rt2];
fa2ef212
MM		 976 if (size == 2) {
977 segv = put_user_u32(val, addr + 4);
978 } else {
979 segv = put_user_u64(val, addr + 8);
980 }
981 if (segv) {
abf1172f 982 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 983 goto error;
984 }
985 }
986 rc = 0;
987finish:
988 env->pc += 4;
989 /* rs == 31 encodes a write to the ZR, thus throwing away
990 * the status return. This is rather silly but valid.
991 */
992 if (rs < 31) {
993 env->xregs[rs] = rc;
994 }
995error:
996 /* instruction faulted, PC does not advance */
997 /* either way a strex releases any exclusive lock we have */
998 env->exclusive_addr = -1;
999 end_exclusive();
1000 return segv;
1001}
1002
1861c454
PM		 1003/* AArch64 main loop */
1004void cpu_loop(CPUARMState *env)
1005{
1006 CPUState *cs = CPU(arm_env_get_cpu(env));
1007 int trapnr, sig;
1008 target_siginfo_t info;
1861c454
PM		 1009
1010 for (;;) {
1011 cpu_exec_start(cs);
1012 trapnr = cpu_arm_exec(env);
1013 cpu_exec_end(cs);
1014
1015 switch (trapnr) {
1016 case EXCP_SWI:
1017 env->xregs[0] = do_syscall(env,
1018 env->xregs[8],
1019 env->xregs[0],
1020 env->xregs[1],
1021 env->xregs[2],
1022 env->xregs[3],
1023 env->xregs[4],
1024 env->xregs[5],
1025 0, 0);
1026 break;
1027 case EXCP_INTERRUPT:
1028 /* just indicate that signals should be handled asap */
1029 break;
1030 case EXCP_UDEF:
a86b3c64 1031 info.si_signo = TARGET_SIGILL;
1861c454
PM		 1032 info.si_errno = 0;
1033 info.si_code = TARGET_ILL_ILLOPN;
1034 info._sifields._sigfault._addr = env->pc;
1035 queue_signal(env, info.si_signo, &info);
1036 break;
abf1172f
PM		 1037 case EXCP_STREX:
1038 if (!do_strex_a64(env)) {
1039 break;
1040 }
1041 /* fall through for segv */
1861c454 1042 case EXCP_PREFETCH_ABORT:
1861c454 1043 case EXCP_DATA_ABORT:
a86b3c64 1044 info.si_signo = TARGET_SIGSEGV;
1861c454
PM		 1045 info.si_errno = 0;
1046 /* XXX: check env->error_code */
1047 info.si_code = TARGET_SEGV_MAPERR;
686581ad 1048 info._sifields._sigfault._addr = env->exception.vaddress;
1861c454
PM		 1049 queue_signal(env, info.si_signo, &info);
1050 break;
1051 case EXCP_DEBUG:
1052 case EXCP_BKPT:
1053 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1054 if (sig) {
1055 info.si_signo = sig;
1056 info.si_errno = 0;
1057 info.si_code = TARGET_TRAP_BRKPT;
1058 queue_signal(env, info.si_signo, &info);
1059 }
1060 break;
1861c454
PM		 1061 default:
1062 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
1063 trapnr);
1064 cpu_dump_state(cs, stderr, fprintf, 0);
1065 abort();
1066 }
1067 process_pending_signals(env);
fa2ef212
MM		 1068 /* Exception return on AArch64 always clears the exclusive monitor,
1069 * so any return to running guest code implies this.
1070 * A strex (successful or otherwise) also clears the monitor, so
1071 * we don't need to specialcase EXCP_STREX.
1072 */
1073 env->exclusive_addr = -1;
1861c454
PM		 1074 }
1075}
1076#endif /* ndef TARGET_ABI32 */
1077
b346ff46 1078#endif
1b6b029e 1079
d2fbca94
GX		 1080#ifdef TARGET_UNICORE32
1081
05390248 1082void cpu_loop(CPUUniCore32State *env)
d2fbca94 1083{
0315c31c 1084 CPUState *cs = CPU(uc32_env_get_cpu(env));
d2fbca94
GX		 1085 int trapnr;
1086 unsigned int n, insn;
1087 target_siginfo_t info;
1088
1089 for (;;) {
0315c31c 1090 cpu_exec_start(cs);
d2fbca94 1091 trapnr = uc32_cpu_exec(env);
0315c31c 1092 cpu_exec_end(cs);
d2fbca94
GX		 1093 switch (trapnr) {
1094 case UC32_EXCP_PRIV:
1095 {
1096 /* system call */
1097 get_user_u32(insn, env->regs[31] - 4);
1098 n = insn & 0xffffff;
1099
1100 if (n >= UC32_SYSCALL_BASE) {
1101 /* linux syscall */
1102 n -= UC32_SYSCALL_BASE;
1103 if (n == UC32_SYSCALL_NR_set_tls) {
1104 cpu_set_tls(env, env->regs[0]);
1105 env->regs[0] = 0;
1106 } else {
1107 env->regs[0] = do_syscall(env,
1108 n,
1109 env->regs[0],
1110 env->regs[1],
1111 env->regs[2],
1112 env->regs[3],
1113 env->regs[4],
5945cfcb
PM		 1114 env->regs[5],
1115 0, 0);
d2fbca94
GX		 1116 }
1117 } else {
1118 goto error;
1119 }
1120 }
1121 break;
d48813dd
GX		 1122 case UC32_EXCP_DTRAP:
1123 case UC32_EXCP_ITRAP:
a86b3c64 1124 info.si_signo = TARGET_SIGSEGV;
d2fbca94
GX		 1125 info.si_errno = 0;
1126 /* XXX: check env->error_code */
1127 info.si_code = TARGET_SEGV_MAPERR;
1128 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1129 queue_signal(env, info.si_signo, &info);
1130 break;
1131 case EXCP_INTERRUPT:
1132 /* just indicate that signals should be handled asap */
1133 break;
1134 case EXCP_DEBUG:
1135 {
1136 int sig;
1137
db6b81d4 1138 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d2fbca94
GX		 1139 if (sig) {
1140 info.si_signo = sig;
1141 info.si_errno = 0;
1142 info.si_code = TARGET_TRAP_BRKPT;
1143 queue_signal(env, info.si_signo, &info);
1144 }
1145 }
1146 break;
1147 default:
1148 goto error;
1149 }
1150 process_pending_signals(env);
1151 }
1152
1153error:
1154 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
878096ee 1155 cpu_dump_state(cs, stderr, fprintf, 0);
d2fbca94
GX		 1156 abort();
1157}
1158#endif
1159
93ac68bc 1160#ifdef TARGET_SPARC
ed23fbd9 1161#define SPARC64_STACK_BIAS 2047
93ac68bc 1162
060366c5
FB		 1163//#define DEBUG_WIN
1164
2623cbaf
FB		 1165/* WARNING: dealing with register windows _is_ complicated. More info
1166 can be found at http://www.sics.se/~psm/sparcstack.html */
060366c5
FB		 1167static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1168{
1a14026e 1169 index = (index + cwp * 16) % (16 * env->nwindows);
060366c5
FB		 1170 /* wrap handling : if cwp is on the last window, then we use the
1171 registers 'after' the end */
1a14026e
BS		 1172 if (index < 8 && env->cwp == env->nwindows - 1)
1173 index += 16 * env->nwindows;
060366c5
FB		 1174 return index;
1175}
1176
2623cbaf
FB		 1177/* save the register window 'cwp1' */
1178static inline void save_window_offset(CPUSPARCState *env, int cwp1)
060366c5 1179{
2623cbaf 1180 unsigned int i;
992f48a0 1181 abi_ulong sp_ptr;
3b46e624 1182
53a5960a 1183 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1184#ifdef TARGET_SPARC64
1185 if (sp_ptr & 3)
1186 sp_ptr += SPARC64_STACK_BIAS;
1187#endif
060366c5 1188#if defined(DEBUG_WIN)
2daf0284
BS		 1189 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1190 sp_ptr, cwp1);
060366c5 1191#endif
2623cbaf 1192 for(i = 0; i < 16; i++) {
2f619698
FB		 1193 /* FIXME - what to do if put_user() fails? */
1194 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1195 sp_ptr += sizeof(abi_ulong);
2623cbaf 1196 }
060366c5
FB		 1197}
1198
1199static void save_window(CPUSPARCState *env)
1200{
5ef54116 1201#ifndef TARGET_SPARC64
2623cbaf 1202 unsigned int new_wim;
1a14026e
BS		 1203 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1204 ((1LL << env->nwindows) - 1);
1205 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
2623cbaf 1206 env->wim = new_wim;
5ef54116 1207#else
1a14026e 1208 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
5ef54116
FB		 1209 env->cansave++;
1210 env->canrestore--;
1211#endif
060366c5
FB		 1212}
1213
1214static void restore_window(CPUSPARCState *env)
1215{
eda52953
BS		 1216#ifndef TARGET_SPARC64
1217 unsigned int new_wim;
1218#endif
1219 unsigned int i, cwp1;
992f48a0 1220 abi_ulong sp_ptr;
3b46e624 1221
eda52953 1222#ifndef TARGET_SPARC64
1a14026e
BS		 1223 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1224 ((1LL << env->nwindows) - 1);
eda52953 1225#endif
3b46e624 1226
060366c5 1227 /* restore the invalid window */
1a14026e 1228 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
53a5960a 1229 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1230#ifdef TARGET_SPARC64
1231 if (sp_ptr & 3)
1232 sp_ptr += SPARC64_STACK_BIAS;
1233#endif
060366c5 1234#if defined(DEBUG_WIN)
2daf0284
BS		 1235 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1236 sp_ptr, cwp1);
060366c5 1237#endif
2623cbaf 1238 for(i = 0; i < 16; i++) {
2f619698
FB		 1239 /* FIXME - what to do if get_user() fails? */
1240 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1241 sp_ptr += sizeof(abi_ulong);
2623cbaf 1242 }
5ef54116
FB		 1243#ifdef TARGET_SPARC64
1244 env->canrestore++;
1a14026e
BS		 1245 if (env->cleanwin < env->nwindows - 1)
1246 env->cleanwin++;
5ef54116 1247 env->cansave--;
eda52953
BS		 1248#else
1249 env->wim = new_wim;
5ef54116 1250#endif
060366c5
FB		 1251}
1252
1253static void flush_windows(CPUSPARCState *env)
1254{
1255 int offset, cwp1;
2623cbaf
FB		 1256
1257 offset = 1;
060366c5
FB		 1258 for(;;) {
1259 /* if restore would invoke restore_window(), then we can stop */
1a14026e 1260 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
eda52953 1261#ifndef TARGET_SPARC64
060366c5
FB		 1262 if (env->wim & (1 << cwp1))
1263 break;
eda52953
BS		 1264#else
1265 if (env->canrestore == 0)
1266 break;
1267 env->cansave++;
1268 env->canrestore--;
1269#endif
2623cbaf 1270 save_window_offset(env, cwp1);
060366c5
FB		 1271 offset++;
1272 }
1a14026e 1273 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
eda52953
BS		 1274#ifndef TARGET_SPARC64
1275 /* set wim so that restore will reload the registers */
2623cbaf 1276 env->wim = 1 << cwp1;
eda52953 1277#endif
2623cbaf
FB		 1278#if defined(DEBUG_WIN)
1279 printf("flush_windows: nb=%d\n", offset - 1);
80a9d035 1280#endif
2623cbaf 1281}
060366c5 1282
93ac68bc
FB		 1283void cpu_loop (CPUSPARCState *env)
1284{
878096ee 1285 CPUState *cs = CPU(sparc_env_get_cpu(env));
2cc20260
RH		 1286 int trapnr;
1287 abi_long ret;
c227f099 1288 target_siginfo_t info;
3b46e624 1289
060366c5 1290 while (1) {
b040bc9c 1291 cpu_exec_start(cs);
060366c5 1292 trapnr = cpu_sparc_exec (env);
b040bc9c 1293 cpu_exec_end(cs);
3b46e624 1294
20132b96
RH		 1295 /* Compute PSR before exposing state. */
1296 if (env->cc_op != CC_OP_FLAGS) {
1297 cpu_get_psr(env);
1298 }
1299
060366c5 1300 switch (trapnr) {
5ef54116 1301#ifndef TARGET_SPARC64
5fafdf24 1302 case 0x88:
060366c5 1303 case 0x90:
5ef54116 1304#else
cb33da57 1305 case 0x110:
5ef54116
FB		 1306 case 0x16d:
1307#endif
060366c5 1308 ret = do_syscall (env, env->gregs[1],
5fafdf24
TS		 1309 env->regwptr[0], env->regwptr[1],
1310 env->regwptr[2], env->regwptr[3],
5945cfcb
PM		 1311 env->regwptr[4], env->regwptr[5],
1312 0, 0);
2cc20260 1313 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
992f48a0 1314#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1315 env->xcc |= PSR_CARRY;
1316#else
060366c5 1317 env->psr |= PSR_CARRY;
27908725 1318#endif
060366c5
FB		 1319 ret = -ret;
1320 } else {
992f48a0 1321#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1322 env->xcc &= ~PSR_CARRY;
1323#else
060366c5 1324 env->psr &= ~PSR_CARRY;
27908725 1325#endif
060366c5
FB		 1326 }
1327 env->regwptr[0] = ret;
1328 /* next instruction */
1329 env->pc = env->npc;
1330 env->npc = env->npc + 4;
1331 break;
1332 case 0x83: /* flush windows */
992f48a0
BS		 1333#ifdef TARGET_ABI32
1334 case 0x103:
1335#endif
2623cbaf 1336 flush_windows(env);
060366c5
FB		 1337 /* next instruction */
1338 env->pc = env->npc;
1339 env->npc = env->npc + 4;
1340 break;
3475187d 1341#ifndef TARGET_SPARC64
060366c5
FB		 1342 case TT_WIN_OVF: /* window overflow */
1343 save_window(env);
1344 break;
1345 case TT_WIN_UNF: /* window underflow */
1346 restore_window(env);
1347 break;
61ff6f58
FB		 1348 case TT_TFAULT:
1349 case TT_DFAULT:
1350 {
59f7182f 1351 info.si_signo = TARGET_SIGSEGV;
61ff6f58
FB		 1352 info.si_errno = 0;
1353 /* XXX: check env->error_code */
1354 info.si_code = TARGET_SEGV_MAPERR;
1355 info._sifields._sigfault._addr = env->mmuregs[4];
624f7979 1356 queue_signal(env, info.si_signo, &info);
61ff6f58
FB		 1357 }
1358 break;
3475187d 1359#else
5ef54116
FB		 1360 case TT_SPILL: /* window overflow */
1361 save_window(env);
1362 break;
1363 case TT_FILL: /* window underflow */
1364 restore_window(env);
1365 break;
7f84a729
BS		 1366 case TT_TFAULT:
1367 case TT_DFAULT:
1368 {
59f7182f 1369 info.si_signo = TARGET_SIGSEGV;
7f84a729
BS		 1370 info.si_errno = 0;
1371 /* XXX: check env->error_code */
1372 info.si_code = TARGET_SEGV_MAPERR;
1373 if (trapnr == TT_DFAULT)
1374 info._sifields._sigfault._addr = env->dmmuregs[4];
1375 else
8194f35a 1376 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
624f7979 1377 queue_signal(env, info.si_signo, &info);
7f84a729
BS		 1378 }
1379 break;
27524dc3 1380#ifndef TARGET_ABI32
5bfb56b2
BS		 1381 case 0x16e:
1382 flush_windows(env);
1383 sparc64_get_context(env);
1384 break;
1385 case 0x16f:
1386 flush_windows(env);
1387 sparc64_set_context(env);
1388 break;
27524dc3 1389#endif
3475187d 1390#endif
48dc41eb
FB		 1391 case EXCP_INTERRUPT:
1392 /* just indicate that signals should be handled asap */
1393 break;
75f22e4e
RH		 1394 case TT_ILL_INSN:
1395 {
1396 info.si_signo = TARGET_SIGILL;
1397 info.si_errno = 0;
1398 info.si_code = TARGET_ILL_ILLOPC;
1399 info._sifields._sigfault._addr = env->pc;
1400 queue_signal(env, info.si_signo, &info);
1401 }
1402 break;
1fddef4b
FB		 1403 case EXCP_DEBUG:
1404 {
1405 int sig;
1406
db6b81d4 1407 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 1408 if (sig)
1409 {
1410 info.si_signo = sig;
1411 info.si_errno = 0;
1412 info.si_code = TARGET_TRAP_BRKPT;
624f7979 1413 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 1414 }
1415 }
1416 break;
060366c5
FB		 1417 default:
1418 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 1419 cpu_dump_state(cs, stderr, fprintf, 0);
060366c5
FB		 1420 exit (1);
1421 }
1422 process_pending_signals (env);
1423 }
93ac68bc
FB		 1424}
1425
1426#endif
1427
67867308 1428#ifdef TARGET_PPC
05390248 1429static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
9fddaa0c
FB		 1430{
1431 /* TO FIX */
1432 return 0;
1433}
3b46e624 1434
05390248 1435uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
9fddaa0c 1436{
e3ea6529 1437 return cpu_ppc_get_tb(env);
9fddaa0c 1438}
3b46e624 1439
05390248 1440uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
9fddaa0c
FB		 1441{
1442 return cpu_ppc_get_tb(env) >> 32;
1443}
3b46e624 1444
05390248 1445uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
9fddaa0c 1446{
b711de95 1447 return cpu_ppc_get_tb(env);
9fddaa0c 1448}
5fafdf24 1449
05390248 1450uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
9fddaa0c 1451{
a062e36c 1452 return cpu_ppc_get_tb(env) >> 32;
9fddaa0c 1453}
76a66253 1454
05390248 1455uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
76a66253
JM		 1456__attribute__ (( alias ("cpu_ppc_load_tbu") ));
1457
05390248 1458uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
9fddaa0c 1459{
76a66253 1460 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
9fddaa0c 1461}
76a66253 1462
a750fc0b 1463/* XXX: to be fixed */
73b01960 1464int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
a750fc0b
JM		 1465{
1466 return -1;
1467}
1468
73b01960 1469int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
a750fc0b
JM		 1470{
1471 return -1;
1472}
1473
001faf32
BS		 1474#define EXCP_DUMP(env, fmt, ...) \
1475do { \
a0762859 1476 CPUState *cs = ENV_GET_CPU(env); \
001faf32 1477 fprintf(stderr, fmt , ## __VA_ARGS__); \
a0762859 1478 cpu_dump_state(cs, stderr, fprintf, 0); \
001faf32 1479 qemu_log(fmt, ## __VA_ARGS__); \
eeacee4d 1480 if (qemu_log_enabled()) { \
a0762859 1481 log_cpu_state(cs, 0); \
eeacee4d 1482 } \
e1833e1f
JM		 1483} while (0)
1484
56f066bb
NF		 1485static int do_store_exclusive(CPUPPCState *env)
1486{
1487 target_ulong addr;
1488 target_ulong page_addr;
e22c357b 1489 target_ulong val, val2 __attribute__((unused)) = 0;
56f066bb
NF		 1490 int flags;
1491 int segv = 0;
1492
1493 addr = env->reserve_ea;
1494 page_addr = addr & TARGET_PAGE_MASK;
1495 start_exclusive();
1496 mmap_lock();
1497 flags = page_get_flags(page_addr);
1498 if ((flags & PAGE_READ) == 0) {
1499 segv = 1;
1500 } else {
1501 int reg = env->reserve_info & 0x1f;
4b1daa72 1502 int size = env->reserve_info >> 5;
56f066bb
NF		 1503 int stored = 0;
1504
1505 if (addr == env->reserve_addr) {
1506 switch (size) {
1507 case 1: segv = get_user_u8(val, addr); break;
1508 case 2: segv = get_user_u16(val, addr); break;
1509 case 4: segv = get_user_u32(val, addr); break;
1510#if defined(TARGET_PPC64)
1511 case 8: segv = get_user_u64(val, addr); break;
27b95bfe
TM		 1512 case 16: {
1513 segv = get_user_u64(val, addr);
1514 if (!segv) {
1515 segv = get_user_u64(val2, addr + 8);
1516 }
1517 break;
1518 }
56f066bb
NF		 1519#endif
1520 default: abort();
1521 }
1522 if (!segv && val == env->reserve_val) {
1523 val = env->gpr[reg];
1524 switch (size) {
1525 case 1: segv = put_user_u8(val, addr); break;
1526 case 2: segv = put_user_u16(val, addr); break;
1527 case 4: segv = put_user_u32(val, addr); break;
1528#if defined(TARGET_PPC64)
1529 case 8: segv = put_user_u64(val, addr); break;
27b95bfe
TM		 1530 case 16: {
1531 if (val2 == env->reserve_val2) {
e22c357b
DK		 1532 if (msr_le) {
1533 val2 = val;
1534 val = env->gpr[reg+1];
1535 } else {
1536 val2 = env->gpr[reg+1];
1537 }
27b95bfe
TM		 1538 segv = put_user_u64(val, addr);
1539 if (!segv) {
1540 segv = put_user_u64(val2, addr + 8);
1541 }
1542 }
1543 break;
1544 }
56f066bb
NF		 1545#endif
1546 default: abort();
1547 }
1548 if (!segv) {
1549 stored = 1;
1550 }
1551 }
1552 }
1553 env->crf[0] = (stored << 1) | xer_so;
1554 env->reserve_addr = (target_ulong)-1;
1555 }
1556 if (!segv) {
1557 env->nip += 4;
1558 }
1559 mmap_unlock();
1560 end_exclusive();
1561 return segv;
1562}
1563
67867308
FB		 1564void cpu_loop(CPUPPCState *env)
1565{
0315c31c 1566 CPUState *cs = CPU(ppc_env_get_cpu(env));
c227f099 1567 target_siginfo_t info;
61190b14 1568 int trapnr;
9e0e2f96 1569 target_ulong ret;
3b46e624 1570
67867308 1571 for(;;) {
0315c31c 1572 cpu_exec_start(cs);
67867308 1573 trapnr = cpu_ppc_exec(env);
0315c31c 1574 cpu_exec_end(cs);
67867308 1575 switch(trapnr) {
e1833e1f
JM		 1576 case POWERPC_EXCP_NONE:
1577 /* Just go on */
67867308 1578 break;
e1833e1f 1579 case POWERPC_EXCP_CRITICAL: /* Critical input */
a47dddd7 1580 cpu_abort(cs, "Critical interrupt while in user mode. "
e1833e1f 1581 "Aborting\n");
61190b14 1582 break;
e1833e1f 1583 case POWERPC_EXCP_MCHECK: /* Machine check exception */
a47dddd7 1584 cpu_abort(cs, "Machine check exception while in user mode. "
e1833e1f
JM		 1585 "Aborting\n");
1586 break;
1587 case POWERPC_EXCP_DSI: /* Data storage exception */
90e189ec 1588 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
e1833e1f
JM		 1589 env->spr[SPR_DAR]);
1590 /* XXX: check this. Seems bugged */
2be0071f
FB		 1591 switch (env->error_code & 0xFF000000) {
1592 case 0x40000000:
61190b14
FB		 1593 info.si_signo = TARGET_SIGSEGV;
1594 info.si_errno = 0;
1595 info.si_code = TARGET_SEGV_MAPERR;
1596 break;
2be0071f 1597 case 0x04000000:
61190b14
FB		 1598 info.si_signo = TARGET_SIGILL;
1599 info.si_errno = 0;
1600 info.si_code = TARGET_ILL_ILLADR;
1601 break;
2be0071f 1602 case 0x08000000:
61190b14
FB		 1603 info.si_signo = TARGET_SIGSEGV;
1604 info.si_errno = 0;
1605 info.si_code = TARGET_SEGV_ACCERR;
1606 break;
61190b14
FB		 1607 default:
1608 /* Let's send a regular segfault... */
e1833e1f
JM		 1609 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1610 env->error_code);
61190b14
FB		 1611 info.si_signo = TARGET_SIGSEGV;
1612 info.si_errno = 0;
1613 info.si_code = TARGET_SEGV_MAPERR;
1614 break;
1615 }
67867308 1616 info._sifields._sigfault._addr = env->nip;
624f7979 1617 queue_signal(env, info.si_signo, &info);
67867308 1618 break;
e1833e1f 1619 case POWERPC_EXCP_ISI: /* Instruction storage exception */
90e189ec
BS		 1620 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1621 "\n", env->spr[SPR_SRR0]);
e1833e1f 1622 /* XXX: check this */
2be0071f
FB		 1623 switch (env->error_code & 0xFF000000) {
1624 case 0x40000000:
61190b14 1625 info.si_signo = TARGET_SIGSEGV;
67867308 1626 info.si_errno = 0;
61190b14
FB		 1627 info.si_code = TARGET_SEGV_MAPERR;
1628 break;
2be0071f
FB		 1629 case 0x10000000:
1630 case 0x08000000:
61190b14
FB		 1631 info.si_signo = TARGET_SIGSEGV;
1632 info.si_errno = 0;
1633 info.si_code = TARGET_SEGV_ACCERR;
1634 break;
1635 default:
1636 /* Let's send a regular segfault... */
e1833e1f
JM		 1637 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1638 env->error_code);
61190b14
FB		 1639 info.si_signo = TARGET_SIGSEGV;
1640 info.si_errno = 0;
1641 info.si_code = TARGET_SEGV_MAPERR;
1642 break;
1643 }
1644 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1645 queue_signal(env, info.si_signo, &info);
67867308 1646 break;
e1833e1f 1647 case POWERPC_EXCP_EXTERNAL: /* External input */
a47dddd7 1648 cpu_abort(cs, "External interrupt while in user mode. "
e1833e1f
JM		 1649 "Aborting\n");
1650 break;
1651 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1652 EXCP_DUMP(env, "Unaligned memory access\n");
1653 /* XXX: check this */
61190b14 1654 info.si_signo = TARGET_SIGBUS;
67867308 1655 info.si_errno = 0;
61190b14
FB		 1656 info.si_code = TARGET_BUS_ADRALN;
1657 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1658 queue_signal(env, info.si_signo, &info);
67867308 1659 break;
e1833e1f
JM		 1660 case POWERPC_EXCP_PROGRAM: /* Program exception */
1661 /* XXX: check this */
61190b14 1662 switch (env->error_code & ~0xF) {
e1833e1f
JM		 1663 case POWERPC_EXCP_FP:
1664 EXCP_DUMP(env, "Floating point program exception\n");
61190b14
FB		 1665 info.si_signo = TARGET_SIGFPE;
1666 info.si_errno = 0;
1667 switch (env->error_code & 0xF) {
e1833e1f 1668 case POWERPC_EXCP_FP_OX:
61190b14
FB		 1669 info.si_code = TARGET_FPE_FLTOVF;
1670 break;
e1833e1f 1671 case POWERPC_EXCP_FP_UX:
61190b14
FB		 1672 info.si_code = TARGET_FPE_FLTUND;
1673 break;
e1833e1f
JM		 1674 case POWERPC_EXCP_FP_ZX:
1675 case POWERPC_EXCP_FP_VXZDZ:
61190b14
FB		 1676 info.si_code = TARGET_FPE_FLTDIV;
1677 break;
e1833e1f 1678 case POWERPC_EXCP_FP_XX:
61190b14
FB		 1679 info.si_code = TARGET_FPE_FLTRES;
1680 break;
e1833e1f 1681 case POWERPC_EXCP_FP_VXSOFT:
61190b14
FB		 1682 info.si_code = TARGET_FPE_FLTINV;
1683 break;
7c58044c 1684 case POWERPC_EXCP_FP_VXSNAN:
e1833e1f
JM		 1685 case POWERPC_EXCP_FP_VXISI:
1686 case POWERPC_EXCP_FP_VXIDI:
1687 case POWERPC_EXCP_FP_VXIMZ:
1688 case POWERPC_EXCP_FP_VXVC:
1689 case POWERPC_EXCP_FP_VXSQRT:
1690 case POWERPC_EXCP_FP_VXCVI:
61190b14
FB		 1691 info.si_code = TARGET_FPE_FLTSUB;
1692 break;
1693 default:
e1833e1f
JM		 1694 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1695 env->error_code);
1696 break;
61190b14 1697 }
e1833e1f
JM		 1698 break;
1699 case POWERPC_EXCP_INVAL:
1700 EXCP_DUMP(env, "Invalid instruction\n");
61190b14
FB		 1701 info.si_signo = TARGET_SIGILL;
1702 info.si_errno = 0;
1703 switch (env->error_code & 0xF) {
e1833e1f 1704 case POWERPC_EXCP_INVAL_INVAL:
61190b14
FB		 1705 info.si_code = TARGET_ILL_ILLOPC;
1706 break;
e1833e1f 1707 case POWERPC_EXCP_INVAL_LSWX:
a750fc0b 1708 info.si_code = TARGET_ILL_ILLOPN;
61190b14 1709 break;
e1833e1f 1710 case POWERPC_EXCP_INVAL_SPR:
61190b14
FB		 1711 info.si_code = TARGET_ILL_PRVREG;
1712 break;
e1833e1f 1713 case POWERPC_EXCP_INVAL_FP:
61190b14
FB		 1714 info.si_code = TARGET_ILL_COPROC;
1715 break;
1716 default:
e1833e1f
JM		 1717 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1718 env->error_code & 0xF);
61190b14
FB		 1719 info.si_code = TARGET_ILL_ILLADR;
1720 break;
1721 }
1722 break;
e1833e1f
JM		 1723 case POWERPC_EXCP_PRIV:
1724 EXCP_DUMP(env, "Privilege violation\n");
61190b14
FB		 1725 info.si_signo = TARGET_SIGILL;
1726 info.si_errno = 0;
1727 switch (env->error_code & 0xF) {
e1833e1f 1728 case POWERPC_EXCP_PRIV_OPC:
61190b14
FB		 1729 info.si_code = TARGET_ILL_PRVOPC;
1730 break;
e1833e1f 1731 case POWERPC_EXCP_PRIV_REG:
61190b14 1732 info.si_code = TARGET_ILL_PRVREG;
e1833e1f 1733 break;
61190b14 1734 default:
e1833e1f
JM		 1735 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1736 env->error_code & 0xF);
61190b14
FB		 1737 info.si_code = TARGET_ILL_PRVOPC;
1738 break;
1739 }
1740 break;
e1833e1f 1741 case POWERPC_EXCP_TRAP:
a47dddd7 1742 cpu_abort(cs, "Tried to call a TRAP\n");
e1833e1f 1743 break;
61190b14
FB		 1744 default:
1745 /* Should not happen ! */
a47dddd7 1746 cpu_abort(cs, "Unknown program exception (%02x)\n",
e1833e1f
JM		 1747 env->error_code);
1748 break;
61190b14
FB		 1749 }
1750 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1751 queue_signal(env, info.si_signo, &info);
67867308 1752 break;
e1833e1f
JM		 1753 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1754 EXCP_DUMP(env, "No floating point allowed\n");
61190b14 1755 info.si_signo = TARGET_SIGILL;
67867308 1756 info.si_errno = 0;
61190b14
FB		 1757 info.si_code = TARGET_ILL_COPROC;
1758 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1759 queue_signal(env, info.si_signo, &info);
67867308 1760 break;
e1833e1f 1761 case POWERPC_EXCP_SYSCALL: /* System call exception */
a47dddd7 1762 cpu_abort(cs, "Syscall exception while in user mode. "
e1833e1f 1763 "Aborting\n");
61190b14 1764 break;
e1833e1f
JM		 1765 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1766 EXCP_DUMP(env, "No APU instruction allowed\n");
1767 info.si_signo = TARGET_SIGILL;
1768 info.si_errno = 0;
1769 info.si_code = TARGET_ILL_COPROC;
1770 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1771 queue_signal(env, info.si_signo, &info);
61190b14 1772 break;
e1833e1f 1773 case POWERPC_EXCP_DECR: /* Decrementer exception */
a47dddd7 1774 cpu_abort(cs, "Decrementer interrupt while in user mode. "
e1833e1f 1775 "Aborting\n");
61190b14 1776 break;
e1833e1f 1777 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
a47dddd7 1778 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
e1833e1f
JM		 1779 "Aborting\n");
1780 break;
1781 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
a47dddd7 1782 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
e1833e1f
JM		 1783 "Aborting\n");
1784 break;
1785 case POWERPC_EXCP_DTLB: /* Data TLB error */
a47dddd7 1786 cpu_abort(cs, "Data TLB exception while in user mode. "
e1833e1f
JM		 1787 "Aborting\n");
1788 break;
1789 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
a47dddd7 1790 cpu_abort(cs, "Instruction TLB exception while in user mode. "
e1833e1f
JM		 1791 "Aborting\n");
1792 break;
e1833e1f
JM		 1793 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1794 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1795 info.si_signo = TARGET_SIGILL;
1796 info.si_errno = 0;
1797 info.si_code = TARGET_ILL_COPROC;
1798 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1799 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1800 break;
1801 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
a47dddd7 1802 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
e1833e1f
JM		 1803 break;
1804 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
a47dddd7 1805 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
e1833e1f
JM		 1806 break;
1807 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
a47dddd7 1808 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1809 break;
1810 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
a47dddd7 1811 cpu_abort(cs, "Doorbell interrupt while in user mode. "
e1833e1f
JM		 1812 "Aborting\n");
1813 break;
1814 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
a47dddd7 1815 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
e1833e1f
JM		 1816 "Aborting\n");
1817 break;
1818 case POWERPC_EXCP_RESET: /* System reset exception */
a47dddd7 1819 cpu_abort(cs, "Reset interrupt while in user mode. "
e1833e1f
JM		 1820 "Aborting\n");
1821 break;
e1833e1f 1822 case POWERPC_EXCP_DSEG: /* Data segment exception */
a47dddd7 1823 cpu_abort(cs, "Data segment exception while in user mode. "
e1833e1f
JM		 1824 "Aborting\n");
1825 break;
1826 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
a47dddd7 1827 cpu_abort(cs, "Instruction segment exception "
e1833e1f
JM		 1828 "while in user mode. Aborting\n");
1829 break;
e85e7c6e 1830 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1831 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
a47dddd7 1832 cpu_abort(cs, "Hypervisor decrementer interrupt "
e1833e1f
JM		 1833 "while in user mode. Aborting\n");
1834 break;
e1833e1f
JM		 1835 case POWERPC_EXCP_TRACE: /* Trace exception */
1836 /* Nothing to do:
1837 * we use this exception to emulate step-by-step execution mode.
1838 */
1839 break;
e85e7c6e 1840 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1841 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
a47dddd7 1842 cpu_abort(cs, "Hypervisor data storage exception "
e1833e1f
JM		 1843 "while in user mode. Aborting\n");
1844 break;
1845 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
a47dddd7 1846 cpu_abort(cs, "Hypervisor instruction storage exception "
e1833e1f
JM		 1847 "while in user mode. Aborting\n");
1848 break;
1849 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
a47dddd7 1850 cpu_abort(cs, "Hypervisor data segment exception "
e1833e1f
JM		 1851 "while in user mode. Aborting\n");
1852 break;
1853 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
a47dddd7 1854 cpu_abort(cs, "Hypervisor instruction segment exception "
e1833e1f
JM		 1855 "while in user mode. Aborting\n");
1856 break;
e1833e1f
JM		 1857 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1858 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1859 info.si_signo = TARGET_SIGILL;
1860 info.si_errno = 0;
1861 info.si_code = TARGET_ILL_COPROC;
1862 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1863 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1864 break;
1865 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
a47dddd7 1866 cpu_abort(cs, "Programmable interval timer interrupt "
e1833e1f
JM		 1867 "while in user mode. Aborting\n");
1868 break;
1869 case POWERPC_EXCP_IO: /* IO error exception */
a47dddd7 1870 cpu_abort(cs, "IO error exception while in user mode. "
e1833e1f
JM		 1871 "Aborting\n");
1872 break;
1873 case POWERPC_EXCP_RUNM: /* Run mode exception */
a47dddd7 1874 cpu_abort(cs, "Run mode exception while in user mode. "
e1833e1f
JM		 1875 "Aborting\n");
1876 break;
1877 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
a47dddd7 1878 cpu_abort(cs, "Emulation trap exception not handled\n");
e1833e1f
JM		 1879 break;
1880 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
a47dddd7 1881 cpu_abort(cs, "Instruction fetch TLB exception "
e1833e1f
JM		 1882 "while in user-mode. Aborting");
1883 break;
1884 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
a47dddd7 1885 cpu_abort(cs, "Data load TLB exception while in user-mode. "
e1833e1f
JM		 1886 "Aborting");
1887 break;
1888 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
a47dddd7 1889 cpu_abort(cs, "Data store TLB exception while in user-mode. "
e1833e1f
JM		 1890 "Aborting");
1891 break;
1892 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
a47dddd7 1893 cpu_abort(cs, "Floating-point assist exception not handled\n");
e1833e1f
JM		 1894 break;
1895 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
a47dddd7 1896 cpu_abort(cs, "Instruction address breakpoint exception "
e1833e1f
JM		 1897 "not handled\n");
1898 break;
1899 case POWERPC_EXCP_SMI: /* System management interrupt */
a47dddd7 1900 cpu_abort(cs, "System management interrupt while in user mode. "
e1833e1f
JM		 1901 "Aborting\n");
1902 break;
1903 case POWERPC_EXCP_THERM: /* Thermal interrupt */
a47dddd7 1904 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
e1833e1f
JM		 1905 "Aborting\n");
1906 break;
1907 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
a47dddd7 1908 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1909 break;
1910 case POWERPC_EXCP_VPUA: /* Vector assist exception */
a47dddd7 1911 cpu_abort(cs, "Vector assist exception not handled\n");
e1833e1f
JM		 1912 break;
1913 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
a47dddd7 1914 cpu_abort(cs, "Soft patch exception not handled\n");
e1833e1f
JM		 1915 break;
1916 case POWERPC_EXCP_MAINT: /* Maintenance exception */
a47dddd7 1917 cpu_abort(cs, "Maintenance exception while in user mode. "
e1833e1f
JM		 1918 "Aborting\n");
1919 break;
1920 case POWERPC_EXCP_STOP: /* stop translation */
1921 /* We did invalidate the instruction cache. Go on */
1922 break;
1923 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1924 /* We just stopped because of a branch. Go on */
1925 break;
1926 case POWERPC_EXCP_SYSCALL_USER:
1927 /* system call in user-mode emulation */
1928 /* WARNING:
1929 * PPC ABI uses overflow flag in cr0 to signal an error
1930 * in syscalls.
1931 */
e1833e1f
JM		 1932 env->crf[0] &= ~0x1;
1933 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1934 env->gpr[5], env->gpr[6], env->gpr[7],
5945cfcb 1935 env->gpr[8], 0, 0);
9e0e2f96 1936 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
bcd4933a
NF		 1937 /* Returning from a successful sigreturn syscall.
1938 Avoid corrupting register state. */
1939 break;
1940 }
9e0e2f96 1941 if (ret > (target_ulong)(-515)) {
e1833e1f
JM		 1942 env->crf[0] |= 0x1;
1943 ret = -ret;
61190b14 1944 }
e1833e1f 1945 env->gpr[3] = ret;
e1833e1f 1946 break;
56f066bb
NF		 1947 case POWERPC_EXCP_STCX:
1948 if (do_store_exclusive(env)) {
1949 info.si_signo = TARGET_SIGSEGV;
1950 info.si_errno = 0;
1951 info.si_code = TARGET_SEGV_MAPERR;
1952 info._sifields._sigfault._addr = env->nip;
1953 queue_signal(env, info.si_signo, &info);
1954 }
1955 break;
71f75756
AJ		 1956 case EXCP_DEBUG:
1957 {
1958 int sig;
1959
db6b81d4 1960 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
71f75756
AJ		 1961 if (sig) {
1962 info.si_signo = sig;
1963 info.si_errno = 0;
1964 info.si_code = TARGET_TRAP_BRKPT;
1965 queue_signal(env, info.si_signo, &info);
1966 }
1967 }
1968 break;
56ba31ff
JM		 1969 case EXCP_INTERRUPT:
1970 /* just indicate that signals should be handled asap */
1971 break;
e1833e1f 1972 default:
a47dddd7 1973 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
e1833e1f 1974 break;
67867308
FB		 1975 }
1976 process_pending_signals(env);
1977 }
1978}
1979#endif
1980
048f6b4d
FB		 1981#ifdef TARGET_MIPS
1982
ff4f7382
RH		 1983# ifdef TARGET_ABI_MIPSO32
1984# define MIPS_SYS(name, args) args,
048f6b4d 1985static const uint8_t mips_syscall_args[] = {
29fb0f25 1986 MIPS_SYS(sys_syscall , 8) /* 4000 */
048f6b4d
FB		 1987 MIPS_SYS(sys_exit , 1)
1988 MIPS_SYS(sys_fork , 0)
1989 MIPS_SYS(sys_read , 3)
1990 MIPS_SYS(sys_write , 3)
1991 MIPS_SYS(sys_open , 3) /* 4005 */
1992 MIPS_SYS(sys_close , 1)
1993 MIPS_SYS(sys_waitpid , 3)
1994 MIPS_SYS(sys_creat , 2)
1995 MIPS_SYS(sys_link , 2)
1996 MIPS_SYS(sys_unlink , 1) /* 4010 */
1997 MIPS_SYS(sys_execve , 0)
1998 MIPS_SYS(sys_chdir , 1)
1999 MIPS_SYS(sys_time , 1)
2000 MIPS_SYS(sys_mknod , 3)
2001 MIPS_SYS(sys_chmod , 2) /* 4015 */
2002 MIPS_SYS(sys_lchown , 3)
2003 MIPS_SYS(sys_ni_syscall , 0)
2004 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2005 MIPS_SYS(sys_lseek , 3)
2006 MIPS_SYS(sys_getpid , 0) /* 4020 */
2007 MIPS_SYS(sys_mount , 5)
868e34d7 2008 MIPS_SYS(sys_umount , 1)
048f6b4d
FB		 2009 MIPS_SYS(sys_setuid , 1)
2010 MIPS_SYS(sys_getuid , 0)
2011 MIPS_SYS(sys_stime , 1) /* 4025 */
2012 MIPS_SYS(sys_ptrace , 4)
2013 MIPS_SYS(sys_alarm , 1)
2014 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2015 MIPS_SYS(sys_pause , 0)
2016 MIPS_SYS(sys_utime , 2) /* 4030 */
2017 MIPS_SYS(sys_ni_syscall , 0)
2018 MIPS_SYS(sys_ni_syscall , 0)
2019 MIPS_SYS(sys_access , 2)
2020 MIPS_SYS(sys_nice , 1)
2021 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2022 MIPS_SYS(sys_sync , 0)
2023 MIPS_SYS(sys_kill , 2)
2024 MIPS_SYS(sys_rename , 2)
2025 MIPS_SYS(sys_mkdir , 2)
2026 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2027 MIPS_SYS(sys_dup , 1)
2028 MIPS_SYS(sys_pipe , 0)
2029 MIPS_SYS(sys_times , 1)
2030 MIPS_SYS(sys_ni_syscall , 0)
2031 MIPS_SYS(sys_brk , 1) /* 4045 */
2032 MIPS_SYS(sys_setgid , 1)
2033 MIPS_SYS(sys_getgid , 0)
2034 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2035 MIPS_SYS(sys_geteuid , 0)
2036 MIPS_SYS(sys_getegid , 0) /* 4050 */
2037 MIPS_SYS(sys_acct , 0)
868e34d7 2038 MIPS_SYS(sys_umount2 , 2)
048f6b4d
FB		 2039 MIPS_SYS(sys_ni_syscall , 0)
2040 MIPS_SYS(sys_ioctl , 3)
2041 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2042 MIPS_SYS(sys_ni_syscall , 2)
2043 MIPS_SYS(sys_setpgid , 2)
2044 MIPS_SYS(sys_ni_syscall , 0)
2045 MIPS_SYS(sys_olduname , 1)
2046 MIPS_SYS(sys_umask , 1) /* 4060 */
2047 MIPS_SYS(sys_chroot , 1)
2048 MIPS_SYS(sys_ustat , 2)
2049 MIPS_SYS(sys_dup2 , 2)
2050 MIPS_SYS(sys_getppid , 0)
2051 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2052 MIPS_SYS(sys_setsid , 0)
2053 MIPS_SYS(sys_sigaction , 3)
2054 MIPS_SYS(sys_sgetmask , 0)
2055 MIPS_SYS(sys_ssetmask , 1)
2056 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2057 MIPS_SYS(sys_setregid , 2)
2058 MIPS_SYS(sys_sigsuspend , 0)
2059 MIPS_SYS(sys_sigpending , 1)
2060 MIPS_SYS(sys_sethostname , 2)
2061 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2062 MIPS_SYS(sys_getrlimit , 2)
2063 MIPS_SYS(sys_getrusage , 2)
2064 MIPS_SYS(sys_gettimeofday, 2)
2065 MIPS_SYS(sys_settimeofday, 2)
2066 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2067 MIPS_SYS(sys_setgroups , 2)
2068 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2069 MIPS_SYS(sys_symlink , 2)
2070 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2071 MIPS_SYS(sys_readlink , 3) /* 4085 */
2072 MIPS_SYS(sys_uselib , 1)
2073 MIPS_SYS(sys_swapon , 2)
2074 MIPS_SYS(sys_reboot , 3)
2075 MIPS_SYS(old_readdir , 3)
2076 MIPS_SYS(old_mmap , 6) /* 4090 */
2077 MIPS_SYS(sys_munmap , 2)
2078 MIPS_SYS(sys_truncate , 2)
2079 MIPS_SYS(sys_ftruncate , 2)
2080 MIPS_SYS(sys_fchmod , 2)
2081 MIPS_SYS(sys_fchown , 3) /* 4095 */
2082 MIPS_SYS(sys_getpriority , 2)
2083 MIPS_SYS(sys_setpriority , 3)
2084 MIPS_SYS(sys_ni_syscall , 0)
2085 MIPS_SYS(sys_statfs , 2)
2086 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2087 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2088 MIPS_SYS(sys_socketcall , 2)
2089 MIPS_SYS(sys_syslog , 3)
2090 MIPS_SYS(sys_setitimer , 3)
2091 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2092 MIPS_SYS(sys_newstat , 2)
2093 MIPS_SYS(sys_newlstat , 2)
2094 MIPS_SYS(sys_newfstat , 2)
2095 MIPS_SYS(sys_uname , 1)
2096 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2097 MIPS_SYS(sys_vhangup , 0)
2098 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2099 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2100 MIPS_SYS(sys_wait4 , 4)
2101 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2102 MIPS_SYS(sys_sysinfo , 1)
2103 MIPS_SYS(sys_ipc , 6)
2104 MIPS_SYS(sys_fsync , 1)
2105 MIPS_SYS(sys_sigreturn , 0)
18113962 2106 MIPS_SYS(sys_clone , 6) /* 4120 */
048f6b4d
FB		 2107 MIPS_SYS(sys_setdomainname, 2)
2108 MIPS_SYS(sys_newuname , 1)
2109 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2110 MIPS_SYS(sys_adjtimex , 1)
2111 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2112 MIPS_SYS(sys_sigprocmask , 3)
2113 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2114 MIPS_SYS(sys_init_module , 5)
2115 MIPS_SYS(sys_delete_module, 1)
2116 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2117 MIPS_SYS(sys_quotactl , 0)
2118 MIPS_SYS(sys_getpgid , 1)
2119 MIPS_SYS(sys_fchdir , 1)
2120 MIPS_SYS(sys_bdflush , 2)
2121 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2122 MIPS_SYS(sys_personality , 1)
2123 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2124 MIPS_SYS(sys_setfsuid , 1)
2125 MIPS_SYS(sys_setfsgid , 1)
2126 MIPS_SYS(sys_llseek , 5) /* 4140 */
2127 MIPS_SYS(sys_getdents , 3)
2128 MIPS_SYS(sys_select , 5)
2129 MIPS_SYS(sys_flock , 2)
2130 MIPS_SYS(sys_msync , 3)
2131 MIPS_SYS(sys_readv , 3) /* 4145 */
2132 MIPS_SYS(sys_writev , 3)
2133 MIPS_SYS(sys_cacheflush , 3)
2134 MIPS_SYS(sys_cachectl , 3)
2135 MIPS_SYS(sys_sysmips , 4)
2136 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2137 MIPS_SYS(sys_getsid , 1)
2138 MIPS_SYS(sys_fdatasync , 0)
2139 MIPS_SYS(sys_sysctl , 1)
2140 MIPS_SYS(sys_mlock , 2)
2141 MIPS_SYS(sys_munlock , 2) /* 4155 */
2142 MIPS_SYS(sys_mlockall , 1)
2143 MIPS_SYS(sys_munlockall , 0)
2144 MIPS_SYS(sys_sched_setparam, 2)
2145 MIPS_SYS(sys_sched_getparam, 2)
2146 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2147 MIPS_SYS(sys_sched_getscheduler, 1)
2148 MIPS_SYS(sys_sched_yield , 0)
2149 MIPS_SYS(sys_sched_get_priority_max, 1)
2150 MIPS_SYS(sys_sched_get_priority_min, 1)
2151 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2152 MIPS_SYS(sys_nanosleep, 2)
b0932e06 2153 MIPS_SYS(sys_mremap , 5)
048f6b4d
FB		 2154 MIPS_SYS(sys_accept , 3)
2155 MIPS_SYS(sys_bind , 3)
2156 MIPS_SYS(sys_connect , 3) /* 4170 */
2157 MIPS_SYS(sys_getpeername , 3)
2158 MIPS_SYS(sys_getsockname , 3)
2159 MIPS_SYS(sys_getsockopt , 5)
2160 MIPS_SYS(sys_listen , 2)
2161 MIPS_SYS(sys_recv , 4) /* 4175 */
2162 MIPS_SYS(sys_recvfrom , 6)
2163 MIPS_SYS(sys_recvmsg , 3)
2164 MIPS_SYS(sys_send , 4)
2165 MIPS_SYS(sys_sendmsg , 3)
2166 MIPS_SYS(sys_sendto , 6) /* 4180 */
2167 MIPS_SYS(sys_setsockopt , 5)
2168 MIPS_SYS(sys_shutdown , 2)
2169 MIPS_SYS(sys_socket , 3)
2170 MIPS_SYS(sys_socketpair , 4)
2171 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2172 MIPS_SYS(sys_getresuid , 3)
2173 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2174 MIPS_SYS(sys_poll , 3)
2175 MIPS_SYS(sys_nfsservctl , 3)
2176 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2177 MIPS_SYS(sys_getresgid , 3)
2178 MIPS_SYS(sys_prctl , 5)
2179 MIPS_SYS(sys_rt_sigreturn, 0)
2180 MIPS_SYS(sys_rt_sigaction, 4)
2181 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2182 MIPS_SYS(sys_rt_sigpending, 2)
2183 MIPS_SYS(sys_rt_sigtimedwait, 4)
2184 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2185 MIPS_SYS(sys_rt_sigsuspend, 0)
2186 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2187 MIPS_SYS(sys_pwrite64 , 6)
2188 MIPS_SYS(sys_chown , 3)
2189 MIPS_SYS(sys_getcwd , 2)
2190 MIPS_SYS(sys_capget , 2)
2191 MIPS_SYS(sys_capset , 2) /* 4205 */
053ebb27 2192 MIPS_SYS(sys_sigaltstack , 2)
048f6b4d
FB		 2193 MIPS_SYS(sys_sendfile , 4)
2194 MIPS_SYS(sys_ni_syscall , 0)
2195 MIPS_SYS(sys_ni_syscall , 0)
2196 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2197 MIPS_SYS(sys_truncate64 , 4)
2198 MIPS_SYS(sys_ftruncate64 , 4)
2199 MIPS_SYS(sys_stat64 , 2)
2200 MIPS_SYS(sys_lstat64 , 2)
2201 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2202 MIPS_SYS(sys_pivot_root , 2)
2203 MIPS_SYS(sys_mincore , 3)
2204 MIPS_SYS(sys_madvise , 3)
2205 MIPS_SYS(sys_getdents64 , 3)
2206 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2207 MIPS_SYS(sys_ni_syscall , 0)
2208 MIPS_SYS(sys_gettid , 0)
2209 MIPS_SYS(sys_readahead , 5)
2210 MIPS_SYS(sys_setxattr , 5)
2211 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2212 MIPS_SYS(sys_fsetxattr , 5)
2213 MIPS_SYS(sys_getxattr , 4)
2214 MIPS_SYS(sys_lgetxattr , 4)
2215 MIPS_SYS(sys_fgetxattr , 4)
2216 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2217 MIPS_SYS(sys_llistxattr , 3)
2218 MIPS_SYS(sys_flistxattr , 3)
2219 MIPS_SYS(sys_removexattr , 2)
2220 MIPS_SYS(sys_lremovexattr, 2)
2221 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2222 MIPS_SYS(sys_tkill , 2)
2223 MIPS_SYS(sys_sendfile64 , 5)
43be1343 2224 MIPS_SYS(sys_futex , 6)
048f6b4d
FB		 2225 MIPS_SYS(sys_sched_setaffinity, 3)
2226 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2227 MIPS_SYS(sys_io_setup , 2)
2228 MIPS_SYS(sys_io_destroy , 1)
2229 MIPS_SYS(sys_io_getevents, 5)
2230 MIPS_SYS(sys_io_submit , 3)
2231 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2232 MIPS_SYS(sys_exit_group , 1)
2233 MIPS_SYS(sys_lookup_dcookie, 3)
2234 MIPS_SYS(sys_epoll_create, 1)
2235 MIPS_SYS(sys_epoll_ctl , 4)
2236 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2237 MIPS_SYS(sys_remap_file_pages, 5)
2238 MIPS_SYS(sys_set_tid_address, 1)
2239 MIPS_SYS(sys_restart_syscall, 0)
2240 MIPS_SYS(sys_fadvise64_64, 7)
2241 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2242 MIPS_SYS(sys_fstatfs64 , 2)
2243 MIPS_SYS(sys_timer_create, 3)
2244 MIPS_SYS(sys_timer_settime, 4)
2245 MIPS_SYS(sys_timer_gettime, 2)
2246 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2247 MIPS_SYS(sys_timer_delete, 1)
2248 MIPS_SYS(sys_clock_settime, 2)
2249 MIPS_SYS(sys_clock_gettime, 2)
2250 MIPS_SYS(sys_clock_getres, 2)
2251 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2252 MIPS_SYS(sys_tgkill , 3)
2253 MIPS_SYS(sys_utimes , 2)
2254 MIPS_SYS(sys_mbind , 4)
2255 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2256 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2257 MIPS_SYS(sys_mq_open , 4)
2258 MIPS_SYS(sys_mq_unlink , 1)
2259 MIPS_SYS(sys_mq_timedsend, 5)
2260 MIPS_SYS(sys_mq_timedreceive, 5)
2261 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2262 MIPS_SYS(sys_mq_getsetattr, 3)
2263 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2264 MIPS_SYS(sys_waitid , 4)
2265 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2266 MIPS_SYS(sys_add_key , 5)
388bb21a 2267 MIPS_SYS(sys_request_key, 4)
048f6b4d 2268 MIPS_SYS(sys_keyctl , 5)
6f5b89a0 2269 MIPS_SYS(sys_set_thread_area, 1)
388bb21a
TS		 2270 MIPS_SYS(sys_inotify_init, 0)
2271 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2272 MIPS_SYS(sys_inotify_rm_watch, 2)
2273 MIPS_SYS(sys_migrate_pages, 4)
2274 MIPS_SYS(sys_openat, 4)
2275 MIPS_SYS(sys_mkdirat, 3)
2276 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2277 MIPS_SYS(sys_fchownat, 5)
2278 MIPS_SYS(sys_futimesat, 3)
2279 MIPS_SYS(sys_fstatat64, 4)
2280 MIPS_SYS(sys_unlinkat, 3)
2281 MIPS_SYS(sys_renameat, 4) /* 4295 */
2282 MIPS_SYS(sys_linkat, 5)
2283 MIPS_SYS(sys_symlinkat, 3)
2284 MIPS_SYS(sys_readlinkat, 4)
2285 MIPS_SYS(sys_fchmodat, 3)
2286 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2287 MIPS_SYS(sys_pselect6, 6)
2288 MIPS_SYS(sys_ppoll, 5)
2289 MIPS_SYS(sys_unshare, 1)
b0932e06 2290 MIPS_SYS(sys_splice, 6)
388bb21a
TS		 2291 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2292 MIPS_SYS(sys_tee, 4)
2293 MIPS_SYS(sys_vmsplice, 4)
2294 MIPS_SYS(sys_move_pages, 6)
2295 MIPS_SYS(sys_set_robust_list, 2)
2296 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2297 MIPS_SYS(sys_kexec_load, 4)
2298 MIPS_SYS(sys_getcpu, 3)
2299 MIPS_SYS(sys_epoll_pwait, 6)
2300 MIPS_SYS(sys_ioprio_set, 3)
2301 MIPS_SYS(sys_ioprio_get, 2)
d979e8eb
PM		 2302 MIPS_SYS(sys_utimensat, 4)
2303 MIPS_SYS(sys_signalfd, 3)
2304 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2305 MIPS_SYS(sys_eventfd, 1)
2306 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2307 MIPS_SYS(sys_timerfd_create, 2)
2308 MIPS_SYS(sys_timerfd_gettime, 2)
2309 MIPS_SYS(sys_timerfd_settime, 4)
2310 MIPS_SYS(sys_signalfd4, 4)
2311 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2312 MIPS_SYS(sys_epoll_create1, 1)
2313 MIPS_SYS(sys_dup3, 3)
2314 MIPS_SYS(sys_pipe2, 2)
2315 MIPS_SYS(sys_inotify_init1, 1)
2316 MIPS_SYS(sys_preadv, 6) /* 4330 */
2317 MIPS_SYS(sys_pwritev, 6)
2318 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2319 MIPS_SYS(sys_perf_event_open, 5)
2320 MIPS_SYS(sys_accept4, 4)
2321 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2322 MIPS_SYS(sys_fanotify_init, 2)
2323 MIPS_SYS(sys_fanotify_mark, 6)
2324 MIPS_SYS(sys_prlimit64, 4)
2325 MIPS_SYS(sys_name_to_handle_at, 5)
2326 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2327 MIPS_SYS(sys_clock_adjtime, 2)
2328 MIPS_SYS(sys_syncfs, 1)
048f6b4d 2329};
ff4f7382
RH		 2330# undef MIPS_SYS
2331# endif /* O32 */
048f6b4d 2332
590bc601
PB		 2333static int do_store_exclusive(CPUMIPSState *env)
2334{
2335 target_ulong addr;
2336 target_ulong page_addr;
2337 target_ulong val;
2338 int flags;
2339 int segv = 0;
2340 int reg;
2341 int d;
2342
5499b6ff 2343 addr = env->lladdr;
590bc601
PB		 2344 page_addr = addr & TARGET_PAGE_MASK;
2345 start_exclusive();
2346 mmap_lock();
2347 flags = page_get_flags(page_addr);
2348 if ((flags & PAGE_READ) == 0) {
2349 segv = 1;
2350 } else {
2351 reg = env->llreg & 0x1f;
2352 d = (env->llreg & 0x20) != 0;
2353 if (d) {
2354 segv = get_user_s64(val, addr);
2355 } else {
2356 segv = get_user_s32(val, addr);
2357 }
2358 if (!segv) {
2359 if (val != env->llval) {
2360 env->active_tc.gpr[reg] = 0;
2361 } else {
2362 if (d) {
2363 segv = put_user_u64(env->llnewval, addr);
2364 } else {
2365 segv = put_user_u32(env->llnewval, addr);
2366 }
2367 if (!segv) {
2368 env->active_tc.gpr[reg] = 1;
2369 }
2370 }
2371 }
2372 }
5499b6ff 2373 env->lladdr = -1;
590bc601
PB		 2374 if (!segv) {
2375 env->active_tc.PC += 4;
2376 }
2377 mmap_unlock();
2378 end_exclusive();
2379 return segv;
2380}
2381
54b2f42c
MI		 2382/* Break codes */
2383enum {
2384 BRK_OVERFLOW = 6,
2385 BRK_DIVZERO = 7
2386};
2387
2388static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2389 unsigned int code)
2390{
2391 int ret = -1;
2392
2393 switch (code) {
2394 case BRK_OVERFLOW:
2395 case BRK_DIVZERO:
2396 info->si_signo = TARGET_SIGFPE;
2397 info->si_errno = 0;
2398 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2399 queue_signal(env, info->si_signo, &*info);
2400 ret = 0;
2401 break;
2402 default:
b51910ba
PJ		 2403 info->si_signo = TARGET_SIGTRAP;
2404 info->si_errno = 0;
2405 queue_signal(env, info->si_signo, &*info);
2406 ret = 0;
54b2f42c
MI		 2407 break;
2408 }
2409
2410 return ret;
2411}
2412
048f6b4d
FB		 2413void cpu_loop(CPUMIPSState *env)
2414{
0315c31c 2415 CPUState *cs = CPU(mips_env_get_cpu(env));
c227f099 2416 target_siginfo_t info;
ff4f7382
RH		 2417 int trapnr;
2418 abi_long ret;
2419# ifdef TARGET_ABI_MIPSO32
048f6b4d 2420 unsigned int syscall_num;
ff4f7382 2421# endif
048f6b4d
FB		 2422
2423 for(;;) {
0315c31c 2424 cpu_exec_start(cs);
048f6b4d 2425 trapnr = cpu_mips_exec(env);
0315c31c 2426 cpu_exec_end(cs);
048f6b4d
FB		 2427 switch(trapnr) {
2428 case EXCP_SYSCALL:
b5dc7732 2429 env->active_tc.PC += 4;
ff4f7382
RH		 2430# ifdef TARGET_ABI_MIPSO32
2431 syscall_num = env->active_tc.gpr[2] - 4000;
388bb21a 2432 if (syscall_num >= sizeof(mips_syscall_args)) {
7c2f6157 2433 ret = -TARGET_ENOSYS;
388bb21a
TS		 2434 } else {
2435 int nb_args;
992f48a0
BS		 2436 abi_ulong sp_reg;
2437 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
388bb21a
TS		 2438
2439 nb_args = mips_syscall_args[syscall_num];
b5dc7732 2440 sp_reg = env->active_tc.gpr[29];
388bb21a
TS		 2441 switch (nb_args) {
2442 /* these arguments are taken from the stack */
94c19610
ACH		 2443 case 8:
2444 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2445 goto done_syscall;
2446 }
2447 case 7:
2448 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2449 goto done_syscall;
2450 }
2451 case 6:
2452 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2453 goto done_syscall;
2454 }
2455 case 5:
2456 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2457 goto done_syscall;
2458 }
388bb21a
TS		 2459 default:
2460 break;
048f6b4d 2461 }
b5dc7732
TS		 2462 ret = do_syscall(env, env->active_tc.gpr[2],
2463 env->active_tc.gpr[4],
2464 env->active_tc.gpr[5],
2465 env->active_tc.gpr[6],
2466 env->active_tc.gpr[7],
5945cfcb 2467 arg5, arg6, arg7, arg8);
388bb21a 2468 }
94c19610 2469done_syscall:
ff4f7382
RH		 2470# else
2471 ret = do_syscall(env, env->active_tc.gpr[2],
2472 env->active_tc.gpr[4], env->active_tc.gpr[5],
2473 env->active_tc.gpr[6], env->active_tc.gpr[7],
2474 env->active_tc.gpr[8], env->active_tc.gpr[9],
2475 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2476# endif /* O32 */
0b1bcb00
PB		 2477 if (ret == -TARGET_QEMU_ESIGRETURN) {
2478 /* Returning from a successful sigreturn syscall.
2479 Avoid clobbering register state. */
2480 break;
2481 }
ff4f7382 2482 if ((abi_ulong)ret >= (abi_ulong)-1133) {
b5dc7732 2483 env->active_tc.gpr[7] = 1; /* error flag */
388bb21a
TS		 2484 ret = -ret;
2485 } else {
b5dc7732 2486 env->active_tc.gpr[7] = 0; /* error flag */
048f6b4d 2487 }
b5dc7732 2488 env->active_tc.gpr[2] = ret;
048f6b4d 2489 break;
ca7c2b1b
TS		 2490 case EXCP_TLBL:
2491 case EXCP_TLBS:
e6e5bd2d
WT		 2492 case EXCP_AdEL:
2493 case EXCP_AdES:
e4474235
PB		 2494 info.si_signo = TARGET_SIGSEGV;
2495 info.si_errno = 0;
2496 /* XXX: check env->error_code */
2497 info.si_code = TARGET_SEGV_MAPERR;
2498 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2499 queue_signal(env, info.si_signo, &info);
2500 break;
6900e84b 2501 case EXCP_CpU:
048f6b4d 2502 case EXCP_RI:
bc1ad2de
FB		 2503 info.si_signo = TARGET_SIGILL;
2504 info.si_errno = 0;
2505 info.si_code = 0;
624f7979 2506 queue_signal(env, info.si_signo, &info);
048f6b4d 2507 break;
106ec879
FB		 2508 case EXCP_INTERRUPT:
2509 /* just indicate that signals should be handled asap */
2510 break;
d08b2a28
PB		 2511 case EXCP_DEBUG:
2512 {
2513 int sig;
2514
db6b81d4 2515 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d08b2a28
PB		 2516 if (sig)
2517 {
2518 info.si_signo = sig;
2519 info.si_errno = 0;
2520 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2521 queue_signal(env, info.si_signo, &info);
d08b2a28
PB		 2522 }
2523 }
2524 break;
590bc601
PB		 2525 case EXCP_SC:
2526 if (do_store_exclusive(env)) {
2527 info.si_signo = TARGET_SIGSEGV;
2528 info.si_errno = 0;
2529 info.si_code = TARGET_SEGV_MAPERR;
2530 info._sifields._sigfault._addr = env->active_tc.PC;
2531 queue_signal(env, info.si_signo, &info);
2532 }
2533 break;
853c3240
JL		 2534 case EXCP_DSPDIS:
2535 info.si_signo = TARGET_SIGILL;
2536 info.si_errno = 0;
2537 info.si_code = TARGET_ILL_ILLOPC;
2538 queue_signal(env, info.si_signo, &info);
2539 break;
54b2f42c
MI		 2540 /* The code below was inspired by the MIPS Linux kernel trap
2541 * handling code in arch/mips/kernel/traps.c.
2542 */
2543 case EXCP_BREAK:
2544 {
2545 abi_ulong trap_instr;
2546 unsigned int code;
2547
a0333817
KCY		 2548 if (env->hflags & MIPS_HFLAG_M16) {
2549 if (env->insn_flags & ASE_MICROMIPS) {
2550 /* microMIPS mode */
1308c464
KCY		 2551 ret = get_user_u16(trap_instr, env->active_tc.PC);
2552 if (ret != 0) {
2553 goto error;
2554 }
a0333817 2555
1308c464
KCY		 2556 if ((trap_instr >> 10) == 0x11) {
2557 /* 16-bit instruction */
2558 code = trap_instr & 0xf;
2559 } else {
2560 /* 32-bit instruction */
2561 abi_ulong instr_lo;
2562
2563 ret = get_user_u16(instr_lo,
2564 env->active_tc.PC + 2);
2565 if (ret != 0) {
2566 goto error;
2567 }
2568 trap_instr = (trap_instr << 16) | instr_lo;
2569 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2570 /* Unfortunately, microMIPS also suffers from
2571 the old assembler bug... */
2572 if (code >= (1 << 10)) {
2573 code >>= 10;
2574 }
2575 }
a0333817
KCY		 2576 } else {
2577 /* MIPS16e mode */
2578 ret = get_user_u16(trap_instr, env->active_tc.PC);
2579 if (ret != 0) {
2580 goto error;
2581 }
2582 code = (trap_instr >> 6) & 0x3f;
a0333817
KCY		 2583 }
2584 } else {
2585 ret = get_user_ual(trap_instr, env->active_tc.PC);
1308c464
KCY		 2586 if (ret != 0) {
2587 goto error;
2588 }
54b2f42c 2589
1308c464
KCY		 2590 /* As described in the original Linux kernel code, the
2591 * below checks on 'code' are to work around an old
2592 * assembly bug.
2593 */
2594 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2595 if (code >= (1 << 10)) {
2596 code >>= 10;
2597 }
54b2f42c
MI		 2598 }
2599
2600 if (do_break(env, &info, code) != 0) {
2601 goto error;
2602 }
2603 }
2604 break;
2605 case EXCP_TRAP:
2606 {
2607 abi_ulong trap_instr;
2608 unsigned int code = 0;
2609
a0333817
KCY		 2610 if (env->hflags & MIPS_HFLAG_M16) {
2611 /* microMIPS mode */
2612 abi_ulong instr[2];
2613
2614 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2615 get_user_u16(instr[1], env->active_tc.PC + 2);
2616
2617 trap_instr = (instr[0] << 16) | instr[1];
2618 } else {
2619 ret = get_user_ual(trap_instr, env->active_tc.PC);
2620 }
2621
54b2f42c
MI		 2622 if (ret != 0) {
2623 goto error;
2624 }
2625
2626 /* The immediate versions don't provide a code. */
2627 if (!(trap_instr & 0xFC000000)) {
a0333817
KCY		 2628 if (env->hflags & MIPS_HFLAG_M16) {
2629 /* microMIPS mode */
2630 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2631 } else {
2632 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2633 }
54b2f42c
MI		 2634 }
2635
2636 if (do_break(env, &info, code) != 0) {
2637 goto error;
2638 }
2639 }
2640 break;
048f6b4d 2641 default:
54b2f42c 2642error:
5fafdf24 2643 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
048f6b4d 2644 trapnr);
878096ee 2645 cpu_dump_state(cs, stderr, fprintf, 0);
048f6b4d
FB		 2646 abort();
2647 }
2648 process_pending_signals(env);
2649 }
2650}
2651#endif
2652
d962783e
JL		 2653#ifdef TARGET_OPENRISC
2654
2655void cpu_loop(CPUOpenRISCState *env)
2656{
878096ee 2657 CPUState *cs = CPU(openrisc_env_get_cpu(env));
d962783e
JL		 2658 int trapnr, gdbsig;
2659
2660 for (;;) {
b040bc9c 2661 cpu_exec_start(cs);
d962783e 2662 trapnr = cpu_exec(env);
b040bc9c 2663 cpu_exec_end(cs);
d962783e
JL		 2664 gdbsig = 0;
2665
2666 switch (trapnr) {
2667 case EXCP_RESET:
2668 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2669 exit(1);
2670 break;
2671 case EXCP_BUSERR:
2672 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
a86b3c64 2673 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2674 break;
2675 case EXCP_DPF:
2676 case EXCP_IPF:
878096ee 2677 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2678 gdbsig = TARGET_SIGSEGV;
2679 break;
2680 case EXCP_TICK:
2681 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2682 break;
2683 case EXCP_ALIGN:
2684 qemu_log("\nAlignment pc is %#x\n", env->pc);
a86b3c64 2685 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2686 break;
2687 case EXCP_ILLEGAL:
2688 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
a86b3c64 2689 gdbsig = TARGET_SIGILL;
d962783e
JL		 2690 break;
2691 case EXCP_INT:
2692 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2693 break;
2694 case EXCP_DTLBMISS:
2695 case EXCP_ITLBMISS:
2696 qemu_log("\nTLB miss\n");
2697 break;
2698 case EXCP_RANGE:
2699 qemu_log("\nRange\n");
a86b3c64 2700 gdbsig = TARGET_SIGSEGV;
d962783e
JL		 2701 break;
2702 case EXCP_SYSCALL:
2703 env->pc += 4; /* 0xc00; */
2704 env->gpr[11] = do_syscall(env,
2705 env->gpr[11], /* return value */
2706 env->gpr[3], /* r3 - r7 are params */
2707 env->gpr[4],
2708 env->gpr[5],
2709 env->gpr[6],
2710 env->gpr[7],
2711 env->gpr[8], 0, 0);
2712 break;
2713 case EXCP_FPE:
2714 qemu_log("\nFloating point error\n");
2715 break;
2716 case EXCP_TRAP:
2717 qemu_log("\nTrap\n");
a86b3c64 2718 gdbsig = TARGET_SIGTRAP;
d962783e
JL		 2719 break;
2720 case EXCP_NR:
2721 qemu_log("\nNR\n");
2722 break;
2723 default:
2724 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2725 trapnr);
878096ee 2726 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2727 gdbsig = TARGET_SIGILL;
2728 break;
2729 }
2730 if (gdbsig) {
db6b81d4 2731 gdb_handlesig(cs, gdbsig);
d962783e
JL		 2732 if (gdbsig != TARGET_SIGTRAP) {
2733 exit(1);
2734 }
2735 }
2736
2737 process_pending_signals(env);
2738 }
2739}
2740
2741#endif /* TARGET_OPENRISC */
2742
fdf9b3e8 2743#ifdef TARGET_SH4
05390248 2744void cpu_loop(CPUSH4State *env)
fdf9b3e8 2745{
878096ee 2746 CPUState *cs = CPU(sh_env_get_cpu(env));
fdf9b3e8 2747 int trapnr, ret;
c227f099 2748 target_siginfo_t info;
3b46e624 2749
fdf9b3e8 2750 while (1) {
b040bc9c 2751 cpu_exec_start(cs);
fdf9b3e8 2752 trapnr = cpu_sh4_exec (env);
b040bc9c 2753 cpu_exec_end(cs);
3b46e624 2754
fdf9b3e8
FB		 2755 switch (trapnr) {
2756 case 0x160:
0b6d3ae0 2757 env->pc += 2;
5fafdf24
TS		 2758 ret = do_syscall(env,
2759 env->gregs[3],
2760 env->gregs[4],
2761 env->gregs[5],
2762 env->gregs[6],
2763 env->gregs[7],
2764 env->gregs[0],
5945cfcb
PM		 2765 env->gregs[1],
2766 0, 0);
9c2a9ea1 2767 env->gregs[0] = ret;
fdf9b3e8 2768 break;
c3b5bc8a
TS		 2769 case EXCP_INTERRUPT:
2770 /* just indicate that signals should be handled asap */
2771 break;
355fb23d
PB		 2772 case EXCP_DEBUG:
2773 {
2774 int sig;
2775
db6b81d4 2776 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
355fb23d
PB		 2777 if (sig)
2778 {
2779 info.si_signo = sig;
2780 info.si_errno = 0;
2781 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2782 queue_signal(env, info.si_signo, &info);
355fb23d
PB		 2783 }
2784 }
2785 break;
c3b5bc8a
TS		 2786 case 0xa0:
2787 case 0xc0:
a86b3c64 2788 info.si_signo = TARGET_SIGSEGV;
c3b5bc8a
TS		 2789 info.si_errno = 0;
2790 info.si_code = TARGET_SEGV_MAPERR;
2791 info._sifields._sigfault._addr = env->tea;
624f7979 2792 queue_signal(env, info.si_signo, &info);
c3b5bc8a
TS		 2793 break;
2794
fdf9b3e8
FB		 2795 default:
2796 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2797 cpu_dump_state(cs, stderr, fprintf, 0);
fdf9b3e8
FB		 2798 exit (1);
2799 }
2800 process_pending_signals (env);
2801 }
2802}
2803#endif
2804
48733d19 2805#ifdef TARGET_CRIS
05390248 2806void cpu_loop(CPUCRISState *env)
48733d19 2807{
878096ee 2808 CPUState *cs = CPU(cris_env_get_cpu(env));
48733d19 2809 int trapnr, ret;
c227f099 2810 target_siginfo_t info;
48733d19
TS		 2811
2812 while (1) {
b040bc9c 2813 cpu_exec_start(cs);
48733d19 2814 trapnr = cpu_cris_exec (env);
b040bc9c 2815 cpu_exec_end(cs);
48733d19
TS		 2816 switch (trapnr) {
2817 case 0xaa:
2818 {
a86b3c64 2819 info.si_signo = TARGET_SIGSEGV;
48733d19
TS		 2820 info.si_errno = 0;
2821 /* XXX: check env->error_code */
2822 info.si_code = TARGET_SEGV_MAPERR;
e00c1e71 2823 info._sifields._sigfault._addr = env->pregs[PR_EDA];
624f7979 2824 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2825 }
2826 break;
b6d3abda
EI		 2827 case EXCP_INTERRUPT:
2828 /* just indicate that signals should be handled asap */
2829 break;
48733d19
TS		 2830 case EXCP_BREAK:
2831 ret = do_syscall(env,
2832 env->regs[9],
2833 env->regs[10],
2834 env->regs[11],
2835 env->regs[12],
2836 env->regs[13],
2837 env->pregs[7],
5945cfcb
PM		 2838 env->pregs[11],
2839 0, 0);
48733d19 2840 env->regs[10] = ret;
48733d19
TS		 2841 break;
2842 case EXCP_DEBUG:
2843 {
2844 int sig;
2845
db6b81d4 2846 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
48733d19
TS		 2847 if (sig)
2848 {
2849 info.si_signo = sig;
2850 info.si_errno = 0;
2851 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2852 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2853 }
2854 }
2855 break;
2856 default:
2857 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2858 cpu_dump_state(cs, stderr, fprintf, 0);
48733d19
TS		 2859 exit (1);
2860 }
2861 process_pending_signals (env);
2862 }
2863}
2864#endif
2865
b779e29e 2866#ifdef TARGET_MICROBLAZE
05390248 2867void cpu_loop(CPUMBState *env)
b779e29e 2868{
878096ee 2869 CPUState *cs = CPU(mb_env_get_cpu(env));
b779e29e 2870 int trapnr, ret;
c227f099 2871 target_siginfo_t info;
b779e29e
EI		 2872
2873 while (1) {
b040bc9c 2874 cpu_exec_start(cs);
b779e29e 2875 trapnr = cpu_mb_exec (env);
b040bc9c 2876 cpu_exec_end(cs);
b779e29e
EI		 2877 switch (trapnr) {
2878 case 0xaa:
2879 {
a86b3c64 2880 info.si_signo = TARGET_SIGSEGV;
b779e29e
EI		 2881 info.si_errno = 0;
2882 /* XXX: check env->error_code */
2883 info.si_code = TARGET_SEGV_MAPERR;
2884 info._sifields._sigfault._addr = 0;
2885 queue_signal(env, info.si_signo, &info);
2886 }
2887 break;
2888 case EXCP_INTERRUPT:
2889 /* just indicate that signals should be handled asap */
2890 break;
2891 case EXCP_BREAK:
2892 /* Return address is 4 bytes after the call. */
2893 env->regs[14] += 4;
d7dce494 2894 env->sregs[SR_PC] = env->regs[14];
b779e29e
EI		 2895 ret = do_syscall(env,
2896 env->regs[12],
2897 env->regs[5],
2898 env->regs[6],
2899 env->regs[7],
2900 env->regs[8],
2901 env->regs[9],
5945cfcb
PM		 2902 env->regs[10],
2903 0, 0);
b779e29e 2904 env->regs[3] = ret;
b779e29e 2905 break;
b76da7e3
EI		 2906 case EXCP_HW_EXCP:
2907 env->regs[17] = env->sregs[SR_PC] + 4;
2908 if (env->iflags & D_FLAG) {
2909 env->sregs[SR_ESR] |= 1 << 12;
2910 env->sregs[SR_PC] -= 4;
b4916d7b 2911 /* FIXME: if branch was immed, replay the imm as well. */
b76da7e3
EI		 2912 }
2913
2914 env->iflags &= ~(IMM_FLAG | D_FLAG);
2915
2916 switch (env->sregs[SR_ESR] & 31) {
22a78d64 2917 case ESR_EC_DIVZERO:
a86b3c64 2918 info.si_signo = TARGET_SIGFPE;
22a78d64
EI		 2919 info.si_errno = 0;
2920 info.si_code = TARGET_FPE_FLTDIV;
2921 info._sifields._sigfault._addr = 0;
2922 queue_signal(env, info.si_signo, &info);
2923 break;
b76da7e3 2924 case ESR_EC_FPU:
a86b3c64 2925 info.si_signo = TARGET_SIGFPE;
b76da7e3
EI		 2926 info.si_errno = 0;
2927 if (env->sregs[SR_FSR] & FSR_IO) {
2928 info.si_code = TARGET_FPE_FLTINV;
2929 }
2930 if (env->sregs[SR_FSR] & FSR_DZ) {
2931 info.si_code = TARGET_FPE_FLTDIV;
2932 }
2933 info._sifields._sigfault._addr = 0;
2934 queue_signal(env, info.si_signo, &info);
2935 break;
2936 default:
2937 printf ("Unhandled hw-exception: 0x%x\n",
2e42d52d 2938 env->sregs[SR_ESR] & ESR_EC_MASK);
878096ee 2939 cpu_dump_state(cs, stderr, fprintf, 0);
b76da7e3
EI		 2940 exit (1);
2941 break;
2942 }
2943 break;
b779e29e
EI		 2944 case EXCP_DEBUG:
2945 {
2946 int sig;
2947
db6b81d4 2948 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
b779e29e
EI		 2949 if (sig)
2950 {
2951 info.si_signo = sig;
2952 info.si_errno = 0;
2953 info.si_code = TARGET_TRAP_BRKPT;
2954 queue_signal(env, info.si_signo, &info);
2955 }
2956 }
2957 break;
2958 default:
2959 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2960 cpu_dump_state(cs, stderr, fprintf, 0);
b779e29e
EI		 2961 exit (1);
2962 }
2963 process_pending_signals (env);
2964 }
2965}
2966#endif
2967
e6e5906b
PB		 2968#ifdef TARGET_M68K
2969
2970void cpu_loop(CPUM68KState *env)
2971{
878096ee 2972 CPUState *cs = CPU(m68k_env_get_cpu(env));
e6e5906b
PB		 2973 int trapnr;
2974 unsigned int n;
c227f099 2975 target_siginfo_t info;
0429a971 2976 TaskState *ts = cs->opaque;
3b46e624 2977
e6e5906b 2978 for(;;) {
b040bc9c 2979 cpu_exec_start(cs);
e6e5906b 2980 trapnr = cpu_m68k_exec(env);
b040bc9c 2981 cpu_exec_end(cs);
e6e5906b
PB		 2982 switch(trapnr) {
2983 case EXCP_ILLEGAL:
2984 {
2985 if (ts->sim_syscalls) {
2986 uint16_t nr;
d8d5119c 2987 get_user_u16(nr, env->pc + 2);
e6e5906b
PB		 2988 env->pc += 4;
2989 do_m68k_simcall(env, nr);
2990 } else {
2991 goto do_sigill;
2992 }
2993 }
2994 break;
a87295e8 2995 case EXCP_HALT_INSN:
e6e5906b 2996 /* Semihosing syscall. */
a87295e8 2997 env->pc += 4;
e6e5906b
PB		 2998 do_m68k_semihosting(env, env->dregs[0]);
2999 break;
3000 case EXCP_LINEA:
3001 case EXCP_LINEF:
3002 case EXCP_UNSUPPORTED:
3003 do_sigill:
a86b3c64 3004 info.si_signo = TARGET_SIGILL;
e6e5906b
PB		 3005 info.si_errno = 0;
3006 info.si_code = TARGET_ILL_ILLOPN;
3007 info._sifields._sigfault._addr = env->pc;
624f7979 3008 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3009 break;
3010 case EXCP_TRAP0:
3011 {
3012 ts->sim_syscalls = 0;
3013 n = env->dregs[0];
3014 env->pc += 2;
5fafdf24
TS		 3015 env->dregs[0] = do_syscall(env,
3016 n,
e6e5906b
PB		 3017 env->dregs[1],
3018 env->dregs[2],
3019 env->dregs[3],
3020 env->dregs[4],
3021 env->dregs[5],
5945cfcb
PM		 3022 env->aregs[0],
3023 0, 0);
e6e5906b
PB		 3024 }
3025 break;
3026 case EXCP_INTERRUPT:
3027 /* just indicate that signals should be handled asap */
3028 break;
3029 case EXCP_ACCESS:
3030 {
a86b3c64 3031 info.si_signo = TARGET_SIGSEGV;
e6e5906b
PB		 3032 info.si_errno = 0;
3033 /* XXX: check env->error_code */
3034 info.si_code = TARGET_SEGV_MAPERR;
3035 info._sifields._sigfault._addr = env->mmu.ar;
624f7979 3036 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3037 }
3038 break;
3039 case EXCP_DEBUG:
3040 {
3041 int sig;
3042
db6b81d4 3043 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
e6e5906b
PB		 3044 if (sig)
3045 {
3046 info.si_signo = sig;
3047 info.si_errno = 0;
3048 info.si_code = TARGET_TRAP_BRKPT;
624f7979 3049 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3050 }
3051 }
3052 break;
3053 default:
5fafdf24 3054 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
e6e5906b 3055 trapnr);
878096ee 3056 cpu_dump_state(cs, stderr, fprintf, 0);
e6e5906b
PB		 3057 abort();
3058 }
3059 process_pending_signals(env);
3060 }
3061}
3062#endif /* TARGET_M68K */
3063
7a3148a9 3064#ifdef TARGET_ALPHA
6910b8f6
RH		 3065static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3066{
3067 target_ulong addr, val, tmp;
3068 target_siginfo_t info;
3069 int ret = 0;
3070
3071 addr = env->lock_addr;
3072 tmp = env->lock_st_addr;
3073 env->lock_addr = -1;
3074 env->lock_st_addr = 0;
3075
3076 start_exclusive();
3077 mmap_lock();
3078
3079 if (addr == tmp) {
3080 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3081 goto do_sigsegv;
3082 }
3083
3084 if (val == env->lock_value) {
3085 tmp = env->ir[reg];
3086 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3087 goto do_sigsegv;
3088 }
3089 ret = 1;
3090 }
3091 }
3092 env->ir[reg] = ret;
3093 env->pc += 4;
3094
3095 mmap_unlock();
3096 end_exclusive();
3097 return;
3098
3099 do_sigsegv:
3100 mmap_unlock();
3101 end_exclusive();
3102
3103 info.si_signo = TARGET_SIGSEGV;
3104 info.si_errno = 0;
3105 info.si_code = TARGET_SEGV_MAPERR;
3106 info._sifields._sigfault._addr = addr;
3107 queue_signal(env, TARGET_SIGSEGV, &info);
3108}
3109
05390248 3110void cpu_loop(CPUAlphaState *env)
7a3148a9 3111{
878096ee 3112 CPUState *cs = CPU(alpha_env_get_cpu(env));
e96efcfc 3113 int trapnr;
c227f099 3114 target_siginfo_t info;
6049f4f8 3115 abi_long sysret;
3b46e624 3116
7a3148a9 3117 while (1) {
b040bc9c 3118 cpu_exec_start(cs);
7a3148a9 3119 trapnr = cpu_alpha_exec (env);
b040bc9c 3120 cpu_exec_end(cs);
3b46e624 3121
ac316ca4
RH		 3122 /* All of the traps imply a transition through PALcode, which
3123 implies an REI instruction has been executed. Which means
3124 that the intr_flag should be cleared. */
3125 env->intr_flag = 0;
3126
7a3148a9
JM		 3127 switch (trapnr) {
3128 case EXCP_RESET:
3129 fprintf(stderr, "Reset requested. Exit\n");
3130 exit(1);
3131 break;
3132 case EXCP_MCHK:
3133 fprintf(stderr, "Machine check exception. Exit\n");
3134 exit(1);
3135 break;
07b6c13b
RH		 3136 case EXCP_SMP_INTERRUPT:
3137 case EXCP_CLK_INTERRUPT:
3138 case EXCP_DEV_INTERRUPT:
5fafdf24 3139 fprintf(stderr, "External interrupt. Exit\n");
7a3148a9
JM		 3140 exit(1);
3141 break;
07b6c13b 3142 case EXCP_MMFAULT:
6910b8f6 3143 env->lock_addr = -1;
6049f4f8
RH		 3144 info.si_signo = TARGET_SIGSEGV;
3145 info.si_errno = 0;
129d8aa5 3146 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
0be1d07c 3147 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
129d8aa5 3148 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3149 queue_signal(env, info.si_signo, &info);
7a3148a9 3150 break;
7a3148a9 3151 case EXCP_UNALIGN:
6910b8f6 3152 env->lock_addr = -1;
6049f4f8
RH		 3153 info.si_signo = TARGET_SIGBUS;
3154 info.si_errno = 0;
3155 info.si_code = TARGET_BUS_ADRALN;
129d8aa5 3156 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3157 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3158 break;
3159 case EXCP_OPCDEC:
6049f4f8 3160 do_sigill:
6910b8f6 3161 env->lock_addr = -1;
6049f4f8
RH		 3162 info.si_signo = TARGET_SIGILL;
3163 info.si_errno = 0;
3164 info.si_code = TARGET_ILL_ILLOPC;
3165 info._sifields._sigfault._addr = env->pc;
3166 queue_signal(env, info.si_signo, &info);
7a3148a9 3167 break;
07b6c13b
RH		 3168 case EXCP_ARITH:
3169 env->lock_addr = -1;
3170 info.si_signo = TARGET_SIGFPE;
3171 info.si_errno = 0;
3172 info.si_code = TARGET_FPE_FLTINV;
3173 info._sifields._sigfault._addr = env->pc;
3174 queue_signal(env, info.si_signo, &info);
3175 break;
7a3148a9 3176 case EXCP_FEN:
6049f4f8 3177 /* No-op. Linux simply re-enables the FPU. */
7a3148a9 3178 break;
07b6c13b 3179 case EXCP_CALL_PAL:
6910b8f6 3180 env->lock_addr = -1;
07b6c13b 3181 switch (env->error_code) {
6049f4f8
RH		 3182 case 0x80:
3183 /* BPT */
3184 info.si_signo = TARGET_SIGTRAP;
3185 info.si_errno = 0;
3186 info.si_code = TARGET_TRAP_BRKPT;
3187 info._sifields._sigfault._addr = env->pc;
3188 queue_signal(env, info.si_signo, &info);
3189 break;
3190 case 0x81:
3191 /* BUGCHK */
3192 info.si_signo = TARGET_SIGTRAP;
3193 info.si_errno = 0;
3194 info.si_code = 0;
3195 info._sifields._sigfault._addr = env->pc;
3196 queue_signal(env, info.si_signo, &info);
3197 break;
3198 case 0x83:
3199 /* CALLSYS */
3200 trapnr = env->ir[IR_V0];
3201 sysret = do_syscall(env, trapnr,
3202 env->ir[IR_A0], env->ir[IR_A1],
3203 env->ir[IR_A2], env->ir[IR_A3],
5945cfcb
PM		 3204 env->ir[IR_A4], env->ir[IR_A5],
3205 0, 0);
a5b3b13b
RH		 3206 if (trapnr == TARGET_NR_sigreturn
3207 || trapnr == TARGET_NR_rt_sigreturn) {
3208 break;
3209 }
3210 /* Syscall writes 0 to V0 to bypass error check, similar
0e141977
RH		 3211 to how this is handled internal to Linux kernel.
3212 (Ab)use trapnr temporarily as boolean indicating error. */
3213 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3214 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3215 env->ir[IR_A3] = trapnr;
6049f4f8
RH		 3216 break;
3217 case 0x86:
3218 /* IMB */
3219 /* ??? We can probably elide the code using page_unprotect
3220 that is checking for self-modifying code. Instead we
3221 could simply call tb_flush here. Until we work out the
3222 changes required to turn off the extra write protection,
3223 this can be a no-op. */
3224 break;
3225 case 0x9E:
3226 /* RDUNIQUE */
3227 /* Handled in the translator for usermode. */
3228 abort();
3229 case 0x9F:
3230 /* WRUNIQUE */
3231 /* Handled in the translator for usermode. */
3232 abort();
3233 case 0xAA:
3234 /* GENTRAP */
3235 info.si_signo = TARGET_SIGFPE;
3236 switch (env->ir[IR_A0]) {
3237 case TARGET_GEN_INTOVF:
3238 info.si_code = TARGET_FPE_INTOVF;
3239 break;
3240 case TARGET_GEN_INTDIV:
3241 info.si_code = TARGET_FPE_INTDIV;
3242 break;
3243 case TARGET_GEN_FLTOVF:
3244 info.si_code = TARGET_FPE_FLTOVF;
3245 break;
3246 case TARGET_GEN_FLTUND:
3247 info.si_code = TARGET_FPE_FLTUND;
3248 break;
3249 case TARGET_GEN_FLTINV:
3250 info.si_code = TARGET_FPE_FLTINV;
3251 break;
3252 case TARGET_GEN_FLTINE:
3253 info.si_code = TARGET_FPE_FLTRES;
3254 break;
3255 case TARGET_GEN_ROPRAND:
3256 info.si_code = 0;
3257 break;
3258 default:
3259 info.si_signo = TARGET_SIGTRAP;
3260 info.si_code = 0;
3261 break;
3262 }
3263 info.si_errno = 0;
3264 info._sifields._sigfault._addr = env->pc;
3265 queue_signal(env, info.si_signo, &info);
3266 break;
3267 default:
3268 goto do_sigill;
3269 }
7a3148a9 3270 break;
7a3148a9 3271 case EXCP_DEBUG:
db6b81d4 3272 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
6049f4f8 3273 if (info.si_signo) {
6910b8f6 3274 env->lock_addr = -1;
6049f4f8
RH		 3275 info.si_errno = 0;
3276 info.si_code = TARGET_TRAP_BRKPT;
3277 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3278 }
3279 break;
6910b8f6
RH		 3280 case EXCP_STL_C:
3281 case EXCP_STQ_C:
3282 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3283 break;
d0f20495
RH		 3284 case EXCP_INTERRUPT:
3285 /* Just indicate that signals should be handled asap. */
3286 break;
7a3148a9
JM		 3287 default:
3288 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3289 cpu_dump_state(cs, stderr, fprintf, 0);
7a3148a9
JM		 3290 exit (1);
3291 }
3292 process_pending_signals (env);
3293 }
3294}
3295#endif /* TARGET_ALPHA */
3296
a4c075f1
UH		 3297#ifdef TARGET_S390X
3298void cpu_loop(CPUS390XState *env)
3299{
878096ee 3300 CPUState *cs = CPU(s390_env_get_cpu(env));
d5a103cd 3301 int trapnr, n, sig;
a4c075f1 3302 target_siginfo_t info;
d5a103cd 3303 target_ulong addr;
a4c075f1
UH		 3304
3305 while (1) {
b040bc9c 3306 cpu_exec_start(cs);
d5a103cd 3307 trapnr = cpu_s390x_exec(env);
b040bc9c 3308 cpu_exec_end(cs);
a4c075f1
UH		 3309 switch (trapnr) {
3310 case EXCP_INTERRUPT:
d5a103cd 3311 /* Just indicate that signals should be handled asap. */
a4c075f1 3312 break;
a4c075f1 3313
d5a103cd
RH		 3314 case EXCP_SVC:
3315 n = env->int_svc_code;
3316 if (!n) {
3317 /* syscalls > 255 */
3318 n = env->regs[1];
a4c075f1 3319 }
d5a103cd
RH		 3320 env->psw.addr += env->int_svc_ilen;
3321 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3322 env->regs[4], env->regs[5],
3323 env->regs[6], env->regs[7], 0, 0);
a4c075f1 3324 break;
d5a103cd
RH		 3325
3326 case EXCP_DEBUG:
db6b81d4 3327 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d5a103cd
RH		 3328 if (sig) {
3329 n = TARGET_TRAP_BRKPT;
3330 goto do_signal_pc;
a4c075f1
UH		 3331 }
3332 break;
d5a103cd
RH		 3333 case EXCP_PGM:
3334 n = env->int_pgm_code;
3335 switch (n) {
3336 case PGM_OPERATION:
3337 case PGM_PRIVILEGED:
a86b3c64 3338 sig = TARGET_SIGILL;
d5a103cd
RH		 3339 n = TARGET_ILL_ILLOPC;
3340 goto do_signal_pc;
3341 case PGM_PROTECTION:
3342 case PGM_ADDRESSING:
a86b3c64 3343 sig = TARGET_SIGSEGV;
a4c075f1 3344 /* XXX: check env->error_code */
d5a103cd
RH		 3345 n = TARGET_SEGV_MAPERR;
3346 addr = env->__excp_addr;
3347 goto do_signal;
3348 case PGM_EXECUTE:
3349 case PGM_SPECIFICATION:
3350 case PGM_SPECIAL_OP:
3351 case PGM_OPERAND:
3352 do_sigill_opn:
a86b3c64 3353 sig = TARGET_SIGILL;
d5a103cd
RH		 3354 n = TARGET_ILL_ILLOPN;
3355 goto do_signal_pc;
3356
3357 case PGM_FIXPT_OVERFLOW:
a86b3c64 3358 sig = TARGET_SIGFPE;
d5a103cd
RH		 3359 n = TARGET_FPE_INTOVF;
3360 goto do_signal_pc;
3361 case PGM_FIXPT_DIVIDE:
a86b3c64 3362 sig = TARGET_SIGFPE;
d5a103cd
RH		 3363 n = TARGET_FPE_INTDIV;
3364 goto do_signal_pc;
3365
3366 case PGM_DATA:
3367 n = (env->fpc >> 8) & 0xff;
3368 if (n == 0xff) {
3369 /* compare-and-trap */
3370 goto do_sigill_opn;
3371 } else {
3372 /* An IEEE exception, simulated or otherwise. */
3373 if (n & 0x80) {
3374 n = TARGET_FPE_FLTINV;
3375 } else if (n & 0x40) {
3376 n = TARGET_FPE_FLTDIV;
3377 } else if (n & 0x20) {
3378 n = TARGET_FPE_FLTOVF;
3379 } else if (n & 0x10) {
3380 n = TARGET_FPE_FLTUND;
3381 } else if (n & 0x08) {
3382 n = TARGET_FPE_FLTRES;
3383 } else {
3384 /* ??? Quantum exception; BFP, DFP error. */
3385 goto do_sigill_opn;
3386 }
a86b3c64 3387 sig = TARGET_SIGFPE;
d5a103cd
RH		 3388 goto do_signal_pc;
3389 }
3390
3391 default:
3392 fprintf(stderr, "Unhandled program exception: %#x\n", n);
878096ee 3393 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3394 exit(1);
a4c075f1
UH		 3395 }
3396 break;
d5a103cd
RH		 3397
3398 do_signal_pc:
3399 addr = env->psw.addr;
3400 do_signal:
3401 info.si_signo = sig;
3402 info.si_errno = 0;
3403 info.si_code = n;
3404 info._sifields._sigfault._addr = addr;
3405 queue_signal(env, info.si_signo, &info);
a4c075f1 3406 break;
d5a103cd 3407
a4c075f1 3408 default:
d5a103cd 3409 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
878096ee 3410 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3411 exit(1);
a4c075f1
UH		 3412 }
3413 process_pending_signals (env);
3414 }
3415}
3416
3417#endif /* TARGET_S390X */
3418
a2247f8e 3419THREAD CPUState *thread_cpu;
59faf6d6 3420
edf8e2af
MW		 3421void task_settid(TaskState *ts)
3422{
3423 if (ts->ts_tid == 0) {
edf8e2af 3424 ts->ts_tid = (pid_t)syscall(SYS_gettid);
edf8e2af
MW		 3425 }
3426}
3427
3428void stop_all_tasks(void)
3429{
3430 /*
3431 * We trust that when using NPTL, start_exclusive()
3432 * handles thread stopping correctly.
3433 */
3434 start_exclusive();
3435}
3436
c3a92833 3437/* Assumes contents are already zeroed. */
624f7979
PB		 3438void init_task_state(TaskState *ts)
3439{
3440 int i;
3441
624f7979
PB		 3442 ts->used = 1;
3443 ts->first_free = ts->sigqueue_table;
3444 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3445 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3446 }
3447 ts->sigqueue_table[i].next = NULL;
3448}
fc9c5412 3449
30ba0ee5
AF		 3450CPUArchState *cpu_copy(CPUArchState *env)
3451{
ff4700b0 3452 CPUState *cpu = ENV_GET_CPU(env);
2994fd96 3453 CPUState *new_cpu = cpu_init(cpu_model);
61c7480f 3454 CPUArchState *new_env = new_cpu->env_ptr;
30ba0ee5
AF		 3455 CPUBreakpoint *bp;
3456 CPUWatchpoint *wp;
30ba0ee5
AF		 3457
3458 /* Reset non arch specific state */
75a34036 3459 cpu_reset(new_cpu);
30ba0ee5
AF		 3460
3461 memcpy(new_env, env, sizeof(CPUArchState));
3462
3463 /* Clone all break/watchpoints.
3464 Note: Once we support ptrace with hw-debug register access, make sure
3465 BP_CPU break/watchpoints are handled correctly on clone. */
f0c3c505 3466 QTAILQ_INIT(&cpu->breakpoints);
ff4700b0 3467 QTAILQ_INIT(&cpu->watchpoints);
f0c3c505 3468 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
b3310ab3 3469 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
30ba0ee5 3470 }
ff4700b0 3471 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
05068c0d 3472 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
30ba0ee5 3473 }
30ba0ee5
AF		 3474
3475 return new_env;
3476}
3477
fc9c5412
JS		 3478static void handle_arg_help(const char *arg)
3479{
3480 usage();
3481}
3482
3483static void handle_arg_log(const char *arg)
3484{
3485 int mask;
fc9c5412 3486
4fde1eba 3487 mask = qemu_str_to_log_mask(arg);
fc9c5412 3488 if (!mask) {
59a6fa6e 3489 qemu_print_log_usage(stdout);
fc9c5412
JS		 3490 exit(1);
3491 }
24537a01 3492 qemu_set_log(mask);
fc9c5412
JS		 3493}
3494
50171d42
CWR		 3495static void handle_arg_log_filename(const char *arg)
3496{
9a7e5424 3497 qemu_set_log_filename(arg);
50171d42
CWR		 3498}
3499
fc9c5412
JS		 3500static void handle_arg_set_env(const char *arg)
3501{
3502 char *r, *p, *token;
3503 r = p = strdup(arg);
3504 while ((token = strsep(&p, ",")) != NULL) {
3505 if (envlist_setenv(envlist, token) != 0) {
3506 usage();
3507 }
3508 }
3509 free(r);
3510}
3511
3512static void handle_arg_unset_env(const char *arg)
3513{
3514 char *r, *p, *token;
3515 r = p = strdup(arg);
3516 while ((token = strsep(&p, ",")) != NULL) {
3517 if (envlist_unsetenv(envlist, token) != 0) {
3518 usage();
3519 }
3520 }
3521 free(r);
3522}
3523
3524static void handle_arg_argv0(const char *arg)
3525{
3526 argv0 = strdup(arg);
3527}
3528
3529static void handle_arg_stack_size(const char *arg)
3530{
3531 char *p;
3532 guest_stack_size = strtoul(arg, &p, 0);
3533 if (guest_stack_size == 0) {
3534 usage();
3535 }
3536
3537 if (*p == 'M') {
3538 guest_stack_size *= 1024 * 1024;
3539 } else if (*p == 'k' || *p == 'K') {
3540 guest_stack_size *= 1024;
3541 }
3542}
3543
3544static void handle_arg_ld_prefix(const char *arg)
3545{
3546 interp_prefix = strdup(arg);
3547}
3548
3549static void handle_arg_pagesize(const char *arg)
3550{
3551 qemu_host_page_size = atoi(arg);
3552 if (qemu_host_page_size == 0 ||
3553 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3554 fprintf(stderr, "page size must be a power of two\n");
3555 exit(1);
3556 }
3557}
3558
c5e4a5a9
MR		 3559static void handle_arg_randseed(const char *arg)
3560{
3561 unsigned long long seed;
3562
3563 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3564 fprintf(stderr, "Invalid seed number: %s\n", arg);
3565 exit(1);
3566 }
3567 srand(seed);
3568}
3569
fc9c5412
JS		 3570static void handle_arg_gdb(const char *arg)
3571{
3572 gdbstub_port = atoi(arg);
3573}
3574
3575static void handle_arg_uname(const char *arg)
3576{
3577 qemu_uname_release = strdup(arg);
3578}
3579
3580static void handle_arg_cpu(const char *arg)
3581{
3582 cpu_model = strdup(arg);
c8057f95 3583 if (cpu_model == NULL || is_help_option(cpu_model)) {
fc9c5412 3584 /* XXX: implement xxx_cpu_list for targets that still miss it */
e916cbf8
PM		 3585#if defined(cpu_list)
3586 cpu_list(stdout, &fprintf);
fc9c5412
JS		 3587#endif
3588 exit(1);
3589 }
3590}
3591
3592#if defined(CONFIG_USE_GUEST_BASE)
3593static void handle_arg_guest_base(const char *arg)
3594{
3595 guest_base = strtol(arg, NULL, 0);
3596 have_guest_base = 1;
3597}
3598
3599static void handle_arg_reserved_va(const char *arg)
3600{
3601 char *p;
3602 int shift = 0;
3603 reserved_va = strtoul(arg, &p, 0);
3604 switch (*p) {
3605 case 'k':
3606 case 'K':
3607 shift = 10;
3608 break;
3609 case 'M':
3610 shift = 20;
3611 break;
3612 case 'G':
3613 shift = 30;
3614 break;
3615 }
3616 if (shift) {
3617 unsigned long unshifted = reserved_va;
3618 p++;
3619 reserved_va <<= shift;
3620 if (((reserved_va >> shift) != unshifted)
3621#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3622 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3623#endif
3624 ) {
3625 fprintf(stderr, "Reserved virtual address too big\n");
3626 exit(1);
3627 }
3628 }
3629 if (*p) {
3630 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3631 exit(1);
3632 }
3633}
3634#endif
3635
3636static void handle_arg_singlestep(const char *arg)
3637{
3638 singlestep = 1;
3639}
3640
3641static void handle_arg_strace(const char *arg)
3642{
3643 do_strace = 1;
3644}
3645
3646static void handle_arg_version(const char *arg)
3647{
2e59915d 3648 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
fc9c5412 3649 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
1386d4c0 3650 exit(0);
fc9c5412
JS		 3651}
3652
3653struct qemu_argument {
3654 const char *argv;
3655 const char *env;
3656 bool has_arg;
3657 void (*handle_opt)(const char *arg);
3658 const char *example;
3659 const char *help;
3660};
3661
42644cee 3662static const struct qemu_argument arg_table[] = {
fc9c5412
JS		 3663 {"h", "", false, handle_arg_help,
3664 "", "print this help"},
3665 {"g", "QEMU_GDB", true, handle_arg_gdb,
3666 "port", "wait gdb connection to 'port'"},
3667 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3668 "path", "set the elf interpreter prefix to 'path'"},
3669 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3670 "size", "set the stack size to 'size' bytes"},
3671 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
c8057f95 3672 "model", "select CPU (-cpu help for list)"},
fc9c5412
JS		 3673 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3674 "var=value", "sets targets environment variable (see below)"},
3675 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3676 "var", "unsets targets environment variable (see below)"},
3677 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3678 "argv0", "forces target process argv[0] to be 'argv0'"},
3679 {"r", "QEMU_UNAME", true, handle_arg_uname,
3680 "uname", "set qemu uname release string to 'uname'"},
3681#if defined(CONFIG_USE_GUEST_BASE)
3682 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3683 "address", "set guest_base address to 'address'"},
3684 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3685 "size", "reserve 'size' bytes for guest virtual address space"},
3686#endif
3687 {"d", "QEMU_LOG", true, handle_arg_log,
989b697d
PM		 3688 "item[,...]", "enable logging of specified items "
3689 "(use '-d help' for a list of items)"},
50171d42 3690 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
989b697d 3691 "logfile", "write logs to 'logfile' (default stderr)"},
fc9c5412
JS		 3692 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3693 "pagesize", "set the host page size to 'pagesize'"},
3694 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3695 "", "run in singlestep mode"},
3696 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3697 "", "log system calls"},
c5e4a5a9
MR		 3698 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
3699 "", "Seed for pseudo-random number generator"},
fc9c5412 3700 {"version", "QEMU_VERSION", false, handle_arg_version,
1386d4c0 3701 "", "display version information and exit"},
fc9c5412
JS		 3702 {NULL, NULL, false, NULL, NULL, NULL}
3703};
3704
3705static void usage(void)
3706{
42644cee 3707 const struct qemu_argument *arginfo;
fc9c5412
JS		 3708 int maxarglen;
3709 int maxenvlen;
3710
2e59915d
PB		 3711 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3712 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
fc9c5412
JS		 3713 "\n"
3714 "Options and associated environment variables:\n"
3715 "\n");
3716
63ec54d7
PM		 3717 /* Calculate column widths. We must always have at least enough space
3718 * for the column header.
3719 */
3720 maxarglen = strlen("Argument");
3721 maxenvlen = strlen("Env-variable");
fc9c5412
JS		 3722
3723 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
63ec54d7
PM		 3724 int arglen = strlen(arginfo->argv);
3725 if (arginfo->has_arg) {
3726 arglen += strlen(arginfo->example) + 1;
3727 }
fc9c5412
JS		 3728 if (strlen(arginfo->env) > maxenvlen) {
3729 maxenvlen = strlen(arginfo->env);
3730 }
63ec54d7
PM		 3731 if (arglen > maxarglen) {
3732 maxarglen = arglen;
fc9c5412
JS		 3733 }
3734 }
3735
63ec54d7
PM		 3736 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3737 maxenvlen, "Env-variable");
fc9c5412
JS		 3738
3739 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3740 if (arginfo->has_arg) {
3741 printf("-%s %-*s %-*s %s\n", arginfo->argv,
63ec54d7
PM		 3742 (int)(maxarglen - strlen(arginfo->argv) - 1),
3743 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
fc9c5412 3744 } else {
63ec54d7 3745 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
fc9c5412
JS		 3746 maxenvlen, arginfo->env,
3747 arginfo->help);
3748 }
3749 }
3750
3751 printf("\n"
3752 "Defaults:\n"
3753 "QEMU_LD_PREFIX = %s\n"
989b697d 3754 "QEMU_STACK_SIZE = %ld byte\n",
fc9c5412 3755 interp_prefix,
989b697d 3756 guest_stack_size);
fc9c5412
JS		 3757
3758 printf("\n"
3759 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3760 "QEMU_UNSET_ENV environment variables to set and unset\n"
3761 "environment variables for the target process.\n"
3762 "It is possible to provide several variables by separating them\n"
3763 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3764 "provide the -E and -U options multiple times.\n"
3765 "The following lines are equivalent:\n"
3766 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3767 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3768 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3769 "Note that if you provide several changes to a single variable\n"
3770 "the last change will stay in effect.\n");
3771
3772 exit(1);
3773}
3774
3775static int parse_args(int argc, char **argv)
3776{
3777 const char *r;
3778 int optind;
42644cee 3779 const struct qemu_argument *arginfo;
fc9c5412
JS		 3780
3781 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3782 if (arginfo->env == NULL) {
3783 continue;
3784 }
3785
3786 r = getenv(arginfo->env);
3787 if (r != NULL) {
3788 arginfo->handle_opt(r);
3789 }
3790 }
3791
3792 optind = 1;
3793 for (;;) {
3794 if (optind >= argc) {
3795 break;
3796 }
3797 r = argv[optind];
3798 if (r[0] != '-') {
3799 break;
3800 }
3801 optind++;
3802 r++;
3803 if (!strcmp(r, "-")) {
3804 break;
3805 }
3806
3807 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3808 if (!strcmp(r, arginfo->argv)) {
fc9c5412 3809 if (arginfo->has_arg) {
1386d4c0
PM		 3810 if (optind >= argc) {
3811 usage();
3812 }
3813 arginfo->handle_opt(argv[optind]);
fc9c5412 3814 optind++;
1386d4c0
PM		 3815 } else {
3816 arginfo->handle_opt(NULL);
fc9c5412 3817 }
fc9c5412
JS		 3818 break;
3819 }
3820 }
3821
3822 /* no option matched the current argv */
3823 if (arginfo->handle_opt == NULL) {
3824 usage();
3825 }
3826 }
3827
3828 if (optind >= argc) {
3829 usage();
3830 }
3831
3832 filename = argv[optind];
3833 exec_path = argv[optind];
3834
3835 return optind;
3836}
3837
902b3d5c 3838int main(int argc, char **argv, char **envp)
31e31b8a 3839{
01ffc75b 3840 struct target_pt_regs regs1, *regs = &regs1;
31e31b8a 3841 struct image_info info1, *info = &info1;
edf8e2af 3842 struct linux_binprm bprm;
48e15fc2 3843 TaskState *ts;
9349b4f9 3844 CPUArchState *env;
db6b81d4 3845 CPUState *cpu;
586314f2 3846 int optind;
04a6dfeb 3847 char **target_environ, **wrk;
7d8cec95
AJ		 3848 char **target_argv;
3849 int target_argc;
7d8cec95 3850 int i;
fd4d81dd 3851 int ret;
03cfd8fa 3852 int execfd;
b12b6a18 3853
ce008c1f
AF		 3854 module_call_init(MODULE_INIT_QOM);
3855
04a6dfeb
AJ		 3856 if ((envlist = envlist_create()) == NULL) {
3857 (void) fprintf(stderr, "Unable to allocate envlist\n");
3858 exit(1);
3859 }
3860
3861 /* add current environment into the list */
3862 for (wrk = environ; *wrk != NULL; wrk++) {
3863 (void) envlist_setenv(envlist, *wrk);
3864 }
3865
703e0e89
RH		 3866 /* Read the stack limit from the kernel. If it's "unlimited",
3867 then we can do little else besides use the default. */
3868 {
3869 struct rlimit lim;
3870 if (getrlimit(RLIMIT_STACK, &lim) == 0
81bbe906
TY		 3871 && lim.rlim_cur != RLIM_INFINITY
3872 && lim.rlim_cur == (target_long)lim.rlim_cur) {
703e0e89
RH		 3873 guest_stack_size = lim.rlim_cur;
3874 }
3875 }
3876
b1f9be31 3877 cpu_model = NULL;
b5ec5ce0 3878#if defined(cpudef_setup)
3879 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3880#endif
3881
c5e4a5a9
MR		 3882 srand(time(NULL));
3883
fc9c5412 3884 optind = parse_args(argc, argv);
586314f2 3885
31e31b8a 3886 /* Zero out regs */
01ffc75b 3887 memset(regs, 0, sizeof(struct target_pt_regs));
31e31b8a
FB		 3888
3889 /* Zero out image_info */
3890 memset(info, 0, sizeof(struct image_info));
3891
edf8e2af
MW		 3892 memset(&bprm, 0, sizeof (bprm));
3893
74cd30b8
FB		 3894 /* Scan interp_prefix dir for replacement files. */
3895 init_paths(interp_prefix);
3896
4a24a758
PM		 3897 init_qemu_uname_release();
3898
46027c07 3899 if (cpu_model == NULL) {
aaed909a 3900#if defined(TARGET_I386)
46027c07
FB		 3901#ifdef TARGET_X86_64
3902 cpu_model = "qemu64";
3903#else
3904 cpu_model = "qemu32";
3905#endif
aaed909a 3906#elif defined(TARGET_ARM)
088ab16c 3907 cpu_model = "any";
d2fbca94
GX		 3908#elif defined(TARGET_UNICORE32)
3909 cpu_model = "any";
aaed909a
FB		 3910#elif defined(TARGET_M68K)
3911 cpu_model = "any";
3912#elif defined(TARGET_SPARC)
3913#ifdef TARGET_SPARC64
3914 cpu_model = "TI UltraSparc II";
3915#else
3916 cpu_model = "Fujitsu MB86904";
46027c07 3917#endif
aaed909a
FB		 3918#elif defined(TARGET_MIPS)
3919#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
74797f40 3920 cpu_model = "5KEf";
aaed909a
FB		 3921#else
3922 cpu_model = "24Kf";
3923#endif
d962783e
JL		 3924#elif defined TARGET_OPENRISC
3925 cpu_model = "or1200";
aaed909a 3926#elif defined(TARGET_PPC)
a74029f6
RH		 3927# ifdef TARGET_PPC64
3928 cpu_model = "POWER7";
3929# else
aaed909a 3930 cpu_model = "750";
a74029f6 3931# endif
aaed909a
FB		 3932#else
3933 cpu_model = "any";
3934#endif
3935 }
d5ab9713 3936 tcg_exec_init(0);
83fb7adf
FB		 3937 /* NOTE: we need to init the CPU at this stage to get
3938 qemu_host_page_size */
2994fd96
EH		 3939 cpu = cpu_init(cpu_model);
3940 if (!cpu) {
aaed909a
FB		 3941 fprintf(stderr, "Unable to find CPU definition\n");
3942 exit(1);
3943 }
2994fd96 3944 env = cpu->env_ptr;
0ac46af3 3945 cpu_reset(cpu);
b55a37c9 3946
db6b81d4 3947 thread_cpu = cpu;
3b46e624 3948
b6741956
FB		 3949 if (getenv("QEMU_STRACE")) {
3950 do_strace = 1;
b92c47c1
TS		 3951 }
3952
c5e4a5a9
MR		 3953 if (getenv("QEMU_RAND_SEED")) {
3954 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
3955 }
3956
04a6dfeb
AJ		 3957 target_environ = envlist_to_environ(envlist, NULL);
3958 envlist_free(envlist);
b12b6a18 3959
379f6698
PB		 3960#if defined(CONFIG_USE_GUEST_BASE)
3961 /*
3962 * Now that page sizes are configured in cpu_init() we can do
3963 * proper page alignment for guest_base.
3964 */
3965 guest_base = HOST_PAGE_ALIGN(guest_base);
68a1c816 3966
806d1021
MI		 3967 if (reserved_va || have_guest_base) {
3968 guest_base = init_guest_space(guest_base, reserved_va, 0,
3969 have_guest_base);
3970 if (guest_base == (unsigned long)-1) {
097b8cb8
PM		 3971 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
3972 "space for use as guest address space (check your virtual "
3973 "memory ulimit setting or reserve less using -R option)\n",
3974 reserved_va);
68a1c816
PB		 3975 exit(1);
3976 }
97cc7560 3977
806d1021
MI		 3978 if (reserved_va) {
3979 mmap_next_start = reserved_va;
97cc7560
DDAG		 3980 }
3981 }
14f24e14 3982#endif /* CONFIG_USE_GUEST_BASE */
379f6698
PB		 3983
3984 /*
3985 * Read in mmap_min_addr kernel parameter. This value is used
3986 * When loading the ELF image to determine whether guest_base
14f24e14 3987 * is needed. It is also used in mmap_find_vma.
379f6698 3988 */
14f24e14 3989 {
379f6698
PB		 3990 FILE *fp;
3991
3992 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
3993 unsigned long tmp;
3994 if (fscanf(fp, "%lu", &tmp) == 1) {
3995 mmap_min_addr = tmp;
3996 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
3997 }
3998 fclose(fp);
3999 }
4000 }
379f6698 4001
7d8cec95
AJ		 4002 /*
4003 * Prepare copy of argv vector for target.
4004 */
4005 target_argc = argc - optind;
4006 target_argv = calloc(target_argc + 1, sizeof (char *));
4007 if (target_argv == NULL) {
4008 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4009 exit(1);
4010 }
4011
4012 /*
4013 * If argv0 is specified (using '-0' switch) we replace
4014 * argv[0] pointer with the given one.
4015 */
4016 i = 0;
4017 if (argv0 != NULL) {
4018 target_argv[i++] = strdup(argv0);
4019 }
4020 for (; i < target_argc; i++) {
4021 target_argv[i] = strdup(argv[optind + i]);
4022 }
4023 target_argv[target_argc] = NULL;
4024
7267c094 4025 ts = g_malloc0 (sizeof(TaskState));
edf8e2af
MW		 4026 init_task_state(ts);
4027 /* build Task State */
4028 ts->info = info;
4029 ts->bprm = &bprm;
0429a971 4030 cpu->opaque = ts;
edf8e2af
MW		 4031 task_settid(ts);
4032
0b959cf5
RH		 4033 execfd = qemu_getauxval(AT_EXECFD);
4034 if (execfd == 0) {
03cfd8fa 4035 execfd = open(filename, O_RDONLY);
0b959cf5
RH		 4036 if (execfd < 0) {
4037 printf("Error while loading %s: %s\n", filename, strerror(errno));
4038 _exit(1);
4039 }
03cfd8fa
LV		 4040 }
4041
4042 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
fd4d81dd
AP		 4043 info, &bprm);
4044 if (ret != 0) {
885c1d10 4045 printf("Error while loading %s: %s\n", filename, strerror(-ret));
b12b6a18
TS		 4046 _exit(1);
4047 }
4048
4049 for (wrk = target_environ; *wrk; wrk++) {
4050 free(*wrk);
31e31b8a 4051 }
3b46e624 4052
b12b6a18
TS		 4053 free(target_environ);
4054
2e77eac6 4055 if (qemu_log_enabled()) {
379f6698
PB		 4056#if defined(CONFIG_USE_GUEST_BASE)
4057 qemu_log("guest_base 0x%lx\n", guest_base);
4058#endif
2e77eac6
BS		 4059 log_page_dump();
4060
4061 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4062 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4063 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4064 info->start_code);
4065 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4066 info->start_data);
4067 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4068 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4069 info->start_stack);
4070 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4071 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4072 }
31e31b8a 4073
53a5960a 4074 target_set_brk(info->brk);
31e31b8a 4075 syscall_init();
66fb9763 4076 signal_init();
31e31b8a 4077
9002ec79
RH		 4078#if defined(CONFIG_USE_GUEST_BASE)
4079 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4080 generating the prologue until now so that the prologue can take
4081 the real value of GUEST_BASE into account. */
4082 tcg_prologue_init(&tcg_ctx);
4083#endif
4084
b346ff46 4085#if defined(TARGET_I386)
3802ce26 4086 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
b98dbc90 4087 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
0514ef2f 4088 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
1bde465e
FB		 4089 env->cr[4] |= CR4_OSFXSR_MASK;
4090 env->hflags |= HF_OSFXSR_MASK;
4091 }
d2fd1af7 4092#ifndef TARGET_ABI32
4dbc422b 4093 /* enable 64 bit mode if possible */
0514ef2f 4094 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4dbc422b
FB		 4095 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4096 exit(1);
4097 }
d2fd1af7 4098 env->cr[4] |= CR4_PAE_MASK;
4dbc422b 4099 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
d2fd1af7
FB		 4100 env->hflags |= HF_LMA_MASK;
4101#endif
1bde465e 4102
415e561f
FB		 4103 /* flags setup : we activate the IRQs by default as in user mode */
4104 env->eflags |= IF_MASK;
3b46e624 4105
6dbad63e 4106 /* linux register setup */
d2fd1af7 4107#ifndef TARGET_ABI32
84409ddb
JM		 4108 env->regs[R_EAX] = regs->rax;
4109 env->regs[R_EBX] = regs->rbx;
4110 env->regs[R_ECX] = regs->rcx;
4111 env->regs[R_EDX] = regs->rdx;
4112 env->regs[R_ESI] = regs->rsi;
4113 env->regs[R_EDI] = regs->rdi;
4114 env->regs[R_EBP] = regs->rbp;
4115 env->regs[R_ESP] = regs->rsp;
4116 env->eip = regs->rip;
4117#else
0ecfa993
FB		 4118 env->regs[R_EAX] = regs->eax;
4119 env->regs[R_EBX] = regs->ebx;
4120 env->regs[R_ECX] = regs->ecx;
4121 env->regs[R_EDX] = regs->edx;
4122 env->regs[R_ESI] = regs->esi;
4123 env->regs[R_EDI] = regs->edi;
4124 env->regs[R_EBP] = regs->ebp;
4125 env->regs[R_ESP] = regs->esp;
dab2ed99 4126 env->eip = regs->eip;
84409ddb 4127#endif
31e31b8a 4128
f4beb510 4129 /* linux interrupt setup */
e441570f
AZ		 4130#ifndef TARGET_ABI32
4131 env->idt.limit = 511;
4132#else
4133 env->idt.limit = 255;
4134#endif
4135 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4136 PROT_READ|PROT_WRITE,
4137 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4138 idt_table = g2h(env->idt.base);
f4beb510
FB		 4139 set_idt(0, 0);
4140 set_idt(1, 0);
4141 set_idt(2, 0);
4142 set_idt(3, 3);
4143 set_idt(4, 3);
ec95da6c 4144 set_idt(5, 0);
f4beb510
FB		 4145 set_idt(6, 0);
4146 set_idt(7, 0);
4147 set_idt(8, 0);
4148 set_idt(9, 0);
4149 set_idt(10, 0);
4150 set_idt(11, 0);
4151 set_idt(12, 0);
4152 set_idt(13, 0);
4153 set_idt(14, 0);
4154 set_idt(15, 0);
4155 set_idt(16, 0);
4156 set_idt(17, 0);
4157 set_idt(18, 0);
4158 set_idt(19, 0);
4159 set_idt(0x80, 3);
4160
6dbad63e 4161 /* linux segment setup */
8d18e893
FB		 4162 {
4163 uint64_t *gdt_table;
e441570f
AZ		 4164 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4165 PROT_READ|PROT_WRITE,
4166 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
8d18e893 4167 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
e441570f 4168 gdt_table = g2h(env->gdt.base);
d2fd1af7 4169#ifdef TARGET_ABI32
8d18e893
FB		 4170 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4171 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4172 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
d2fd1af7
FB		 4173#else
4174 /* 64 bit code segment */
4175 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4176 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4177 DESC_L_MASK |
4178 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4179#endif
8d18e893
FB		 4180 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4181 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4182 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4183 }
6dbad63e 4184 cpu_x86_load_seg(env, R_CS, __USER_CS);
d2fd1af7
FB		 4185 cpu_x86_load_seg(env, R_SS, __USER_DS);
4186#ifdef TARGET_ABI32
6dbad63e
FB		 4187 cpu_x86_load_seg(env, R_DS, __USER_DS);
4188 cpu_x86_load_seg(env, R_ES, __USER_DS);
6dbad63e
FB		 4189 cpu_x86_load_seg(env, R_FS, __USER_DS);
4190 cpu_x86_load_seg(env, R_GS, __USER_DS);
d6eb40f6
TS		 4191 /* This hack makes Wine work... */
4192 env->segs[R_FS].selector = 0;
d2fd1af7
FB		 4193#else
4194 cpu_x86_load_seg(env, R_DS, 0);
4195 cpu_x86_load_seg(env, R_ES, 0);
4196 cpu_x86_load_seg(env, R_FS, 0);
4197 cpu_x86_load_seg(env, R_GS, 0);
4198#endif
99033cae
AG		 4199#elif defined(TARGET_AARCH64)
4200 {
4201 int i;
4202
4203 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4204 fprintf(stderr,
4205 "The selected ARM CPU does not support 64 bit mode\n");
4206 exit(1);
4207 }
4208
4209 for (i = 0; i < 31; i++) {
4210 env->xregs[i] = regs->regs[i];
4211 }
4212 env->pc = regs->pc;
4213 env->xregs[31] = regs->sp;
4214 }
b346ff46
FB		 4215#elif defined(TARGET_ARM)
4216 {
4217 int i;
b5ff1b31 4218 cpsr_write(env, regs->uregs[16], 0xffffffff);
b346ff46
FB		 4219 for(i = 0; i < 16; i++) {
4220 env->regs[i] = regs->uregs[i];
4221 }
d8fd2954
PB		 4222 /* Enable BE8. */
4223 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4224 && (info->elf_flags & EF_ARM_BE8)) {
4225 env->bswap_code = 1;
4226 }
b346ff46 4227 }
d2fbca94
GX		 4228#elif defined(TARGET_UNICORE32)
4229 {
4230 int i;
4231 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4232 for (i = 0; i < 32; i++) {
4233 env->regs[i] = regs->uregs[i];
4234 }
4235 }
93ac68bc 4236#elif defined(TARGET_SPARC)
060366c5
FB		 4237 {
4238 int i;
4239 env->pc = regs->pc;
4240 env->npc = regs->npc;
4241 env->y = regs->y;
4242 for(i = 0; i < 8; i++)
4243 env->gregs[i] = regs->u_regs[i];
4244 for(i = 0; i < 8; i++)
4245 env->regwptr[i] = regs->u_regs[i + 8];
4246 }
67867308
FB		 4247#elif defined(TARGET_PPC)
4248 {
4249 int i;
3fc6c082 4250
0411a972
JM		 4251#if defined(TARGET_PPC64)
4252#if defined(TARGET_ABI32)
4253 env->msr &= ~((target_ulong)1 << MSR_SF);
e85e7c6e 4254#else
0411a972
JM		 4255 env->msr |= (target_ulong)1 << MSR_SF;
4256#endif
84409ddb 4257#endif
67867308
FB		 4258 env->nip = regs->nip;
4259 for(i = 0; i < 32; i++) {
4260 env->gpr[i] = regs->gpr[i];
4261 }
4262 }
e6e5906b
PB		 4263#elif defined(TARGET_M68K)
4264 {
e6e5906b
PB		 4265 env->pc = regs->pc;
4266 env->dregs[0] = regs->d0;
4267 env->dregs[1] = regs->d1;
4268 env->dregs[2] = regs->d2;
4269 env->dregs[3] = regs->d3;
4270 env->dregs[4] = regs->d4;
4271 env->dregs[5] = regs->d5;
4272 env->dregs[6] = regs->d6;
4273 env->dregs[7] = regs->d7;
4274 env->aregs[0] = regs->a0;
4275 env->aregs[1] = regs->a1;
4276 env->aregs[2] = regs->a2;
4277 env->aregs[3] = regs->a3;
4278 env->aregs[4] = regs->a4;
4279 env->aregs[5] = regs->a5;
4280 env->aregs[6] = regs->a6;
4281 env->aregs[7] = regs->usp;
4282 env->sr = regs->sr;
4283 ts->sim_syscalls = 1;
4284 }
b779e29e
EI		 4285#elif defined(TARGET_MICROBLAZE)
4286 {
4287 env->regs[0] = regs->r0;
4288 env->regs[1] = regs->r1;
4289 env->regs[2] = regs->r2;
4290 env->regs[3] = regs->r3;
4291 env->regs[4] = regs->r4;
4292 env->regs[5] = regs->r5;
4293 env->regs[6] = regs->r6;
4294 env->regs[7] = regs->r7;
4295 env->regs[8] = regs->r8;
4296 env->regs[9] = regs->r9;
4297 env->regs[10] = regs->r10;
4298 env->regs[11] = regs->r11;
4299 env->regs[12] = regs->r12;
4300 env->regs[13] = regs->r13;
4301 env->regs[14] = regs->r14;
4302 env->regs[15] = regs->r15;
4303 env->regs[16] = regs->r16;
4304 env->regs[17] = regs->r17;
4305 env->regs[18] = regs->r18;
4306 env->regs[19] = regs->r19;
4307 env->regs[20] = regs->r20;
4308 env->regs[21] = regs->r21;
4309 env->regs[22] = regs->r22;
4310 env->regs[23] = regs->r23;
4311 env->regs[24] = regs->r24;
4312 env->regs[25] = regs->r25;
4313 env->regs[26] = regs->r26;
4314 env->regs[27] = regs->r27;
4315 env->regs[28] = regs->r28;
4316 env->regs[29] = regs->r29;
4317 env->regs[30] = regs->r30;
4318 env->regs[31] = regs->r31;
4319 env->sregs[SR_PC] = regs->pc;
4320 }
048f6b4d
FB		 4321#elif defined(TARGET_MIPS)
4322 {
4323 int i;
4324
4325 for(i = 0; i < 32; i++) {
b5dc7732 4326 env->active_tc.gpr[i] = regs->regs[i];
048f6b4d 4327 }
0fddbbf2
NF		 4328 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4329 if (regs->cp0_epc & 1) {
4330 env->hflags |= MIPS_HFLAG_M16;
4331 }
048f6b4d 4332 }
d962783e
JL		 4333#elif defined(TARGET_OPENRISC)
4334 {
4335 int i;
4336
4337 for (i = 0; i < 32; i++) {
4338 env->gpr[i] = regs->gpr[i];
4339 }
4340
4341 env->sr = regs->sr;
4342 env->pc = regs->pc;
4343 }
fdf9b3e8
FB		 4344#elif defined(TARGET_SH4)
4345 {
4346 int i;
4347
4348 for(i = 0; i < 16; i++) {
4349 env->gregs[i] = regs->regs[i];
4350 }
4351 env->pc = regs->pc;
4352 }
7a3148a9
JM		 4353#elif defined(TARGET_ALPHA)
4354 {
4355 int i;
4356
4357 for(i = 0; i < 28; i++) {
992f48a0 4358 env->ir[i] = ((abi_ulong *)regs)[i];
7a3148a9 4359 }
dad081ee 4360 env->ir[IR_SP] = regs->usp;
7a3148a9 4361 env->pc = regs->pc;
7a3148a9 4362 }
48733d19
TS		 4363#elif defined(TARGET_CRIS)
4364 {
4365 env->regs[0] = regs->r0;
4366 env->regs[1] = regs->r1;
4367 env->regs[2] = regs->r2;
4368 env->regs[3] = regs->r3;
4369 env->regs[4] = regs->r4;
4370 env->regs[5] = regs->r5;
4371 env->regs[6] = regs->r6;
4372 env->regs[7] = regs->r7;
4373 env->regs[8] = regs->r8;
4374 env->regs[9] = regs->r9;
4375 env->regs[10] = regs->r10;
4376 env->regs[11] = regs->r11;
4377 env->regs[12] = regs->r12;
4378 env->regs[13] = regs->r13;
4379 env->regs[14] = info->start_stack;
4380 env->regs[15] = regs->acr;
4381 env->pc = regs->erp;
4382 }
a4c075f1
UH		 4383#elif defined(TARGET_S390X)
4384 {
4385 int i;
4386 for (i = 0; i < 16; i++) {
4387 env->regs[i] = regs->gprs[i];
4388 }
4389 env->psw.mask = regs->psw.mask;
4390 env->psw.addr = regs->psw.addr;
4391 }
b346ff46
FB		 4392#else
4393#error unsupported target CPU
4394#endif
31e31b8a 4395
d2fbca94 4396#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
a87295e8
PB		 4397 ts->stack_base = info->start_stack;
4398 ts->heap_base = info->brk;
4399 /* This will be filled in on the first SYS_HEAPINFO call. */
4400 ts->heap_limit = 0;
4401#endif
4402
74c33bed 4403 if (gdbstub_port) {
ff7a981a
PM		 4404 if (gdbserver_start(gdbstub_port) < 0) {
4405 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4406 gdbstub_port);
4407 exit(1);
4408 }
db6b81d4 4409 gdb_handlesig(cpu, 0);
1fddef4b 4410 }
1b6b029e
FB		 4411 cpu_loop(env);
4412 /* never exits */
31e31b8a
FB		 4413 return 0;
4414}
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