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tests/test-vmstate.c: add save_buffer util func
[mirror_qemu.git] / linux-user / main.c
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31e31b8a 1/*
93ac68bc 2 * qemu user main
5fafdf24 3 *
68d0f70e 4 * Copyright (c) 2003-2008 Fabrice Bellard
31e31b8a
FB		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
8167ee88 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31e31b8a 18 */
d39594e9 19#include "qemu/osdep.h"
67a1de0d 20#include "qemu-version.h"
edf8e2af 21#include <sys/syscall.h>
703e0e89 22#include <sys/resource.h>
31e31b8a 23
daa76aa4 24#include "qapi/error.h"
3ef693a0 25#include "qemu.h"
f348b6d1 26#include "qemu/path.h"
6533dd6e 27#include "qemu/config-file.h"
f348b6d1
VB		 28#include "qemu/cutils.h"
29#include "qemu/help_option.h"
2b41f10e 30#include "cpu.h"
63c91552 31#include "exec/exec-all.h"
9002ec79 32#include "tcg.h"
1de7afc9
PB		 33#include "qemu/timer.h"
34#include "qemu/envlist.h"
d8fd2954 35#include "elf.h"
508127e2 36#include "exec/log.h"
6533dd6e
LV		 37#include "trace/control.h"
38#include "glib-compat.h"
04a6dfeb 39
d088d664
AJ		 40char *exec_path;
41
1b530a6d 42int singlestep;
8cb76755
SW		 43static const char *filename;
44static const char *argv0;
45static int gdbstub_port;
46static envlist_t *envlist;
51fb256a 47static const char *cpu_model;
379f6698
PB		 48unsigned long mmap_min_addr;
49unsigned long guest_base;
50int have_guest_base;
120a9848
PB		 51
52#define EXCP_DUMP(env, fmt, ...) \
53do { \
54 CPUState *cs = ENV_GET_CPU(env); \
55 fprintf(stderr, fmt , ## __VA_ARGS__); \
56 cpu_dump_state(cs, stderr, fprintf, 0); \
57 if (qemu_log_separate()) { \
58 qemu_log(fmt, ## __VA_ARGS__); \
59 log_cpu_state(cs, 0); \
60 } \
61} while (0)
62
288e65b9
AG		 63#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
64/*
65 * When running 32-on-64 we should make sure we can fit all of the possible
66 * guest address space into a contiguous chunk of virtual host memory.
67 *
68 * This way we will never overlap with our own libraries or binaries or stack
69 * or anything else that QEMU maps.
70 */
314992b1
AG		 71# ifdef TARGET_MIPS
72/* MIPS only supports 31 bits of virtual address space for user space */
73unsigned long reserved_va = 0x77000000;
74# else
288e65b9 75unsigned long reserved_va = 0xf7000000;
314992b1 76# endif
288e65b9 77#else
68a1c816 78unsigned long reserved_va;
379f6698 79#endif
1b530a6d 80
d03f9c32 81static void usage(int exitcode);
fc9c5412 82
7ee2822c 83static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
e586822a 84const char *qemu_uname_release;
586314f2 85
9de5e440
FB		 86/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
87 we allocate a bigger stack. Need a better solution, for example
88 by remapping the process stack directly at the right place */
703e0e89 89unsigned long guest_stack_size = 8 * 1024 * 1024UL;
31e31b8a
FB		 90
91void gemu_log(const char *fmt, ...)
92{
93 va_list ap;
94
95 va_start(ap, fmt);
96 vfprintf(stderr, fmt, ap);
97 va_end(ap);
98}
99
8fcd3692 100#if defined(TARGET_I386)
05390248 101int cpu_get_pic_interrupt(CPUX86State *env)
92ccca6a
FB		 102{
103 return -1;
104}
8fcd3692 105#endif
92ccca6a 106
d5975363
PB		 107/***********************************************************/
108/* Helper routines for implementing atomic operations. */
109
d5975363
PB		 110/* Make sure everything is in a consistent state for calling fork(). */
111void fork_start(void)
112{
267f685b 113 cpu_list_lock();
677ef623 114 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
d032d1b4 115 mmap_fork_start();
d5975363
PB		 116}
117
118void fork_end(int child)
119{
d032d1b4 120 mmap_fork_end(child);
d5975363 121 if (child) {
bdc44640 122 CPUState *cpu, *next_cpu;
d5975363
PB		 123 /* Child processes created by fork() only have a single thread.
124 Discard information about the parent threads. */
bdc44640
AF		 125 CPU_FOREACH_SAFE(cpu, next_cpu) {
126 if (cpu != thread_cpu) {
014628a7 127 QTAILQ_REMOVE(&cpus, cpu, node);
bdc44640
AF		 128 }
129 }
677ef623 130 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
267f685b 131 qemu_init_cpu_list();
f7ec7f7b 132 gdbserver_fork(thread_cpu);
d5975363 133 } else {
677ef623 134 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
267f685b 135 cpu_list_unlock();
d5975363 136 }
d5975363
PB		 137}
138
a541f297
FB		 139#ifdef TARGET_I386
140/***********************************************************/
141/* CPUX86 core interface */
142
28ab0e2e
FB		 143uint64_t cpu_get_tsc(CPUX86State *env)
144{
4a7428c5 145 return cpu_get_host_ticks();
28ab0e2e
FB		 146}
147
5fafdf24 148static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
f4beb510 149 int flags)
6dbad63e 150{
f4beb510 151 unsigned int e1, e2;
53a5960a 152 uint32_t *p;
6dbad63e
FB		 153 e1 = (addr << 16) | (limit & 0xffff);
154 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
f4beb510 155 e2 |= flags;
53a5960a 156 p = ptr;
d538e8f5 157 p[0] = tswap32(e1);
158 p[1] = tswap32(e2);
f4beb510
FB		 159}
160
e441570f 161static uint64_t *idt_table;
eb38c52c 162#ifdef TARGET_X86_64
d2fd1af7
FB		 163static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
164 uint64_t addr, unsigned int sel)
f4beb510 165{
4dbc422b 166 uint32_t *p, e1, e2;
f4beb510
FB		 167 e1 = (addr & 0xffff) | (sel << 16);
168 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
53a5960a 169 p = ptr;
4dbc422b
FB		 170 p[0] = tswap32(e1);
171 p[1] = tswap32(e2);
172 p[2] = tswap32(addr >> 32);
173 p[3] = 0;
6dbad63e 174}
d2fd1af7
FB		 175/* only dpl matters as we do only user space emulation */
176static void set_idt(int n, unsigned int dpl)
177{
178 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
179}
180#else
d2fd1af7
FB		 181static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
182 uint32_t addr, unsigned int sel)
183{
4dbc422b 184 uint32_t *p, e1, e2;
d2fd1af7
FB		 185 e1 = (addr & 0xffff) | (sel << 16);
186 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
187 p = ptr;
4dbc422b
FB		 188 p[0] = tswap32(e1);
189 p[1] = tswap32(e2);
d2fd1af7
FB		 190}
191
f4beb510
FB		 192/* only dpl matters as we do only user space emulation */
193static void set_idt(int n, unsigned int dpl)
194{
195 set_gate(idt_table + n, 0, dpl, 0, 0);
196}
d2fd1af7 197#endif
31e31b8a 198
89e957e7 199void cpu_loop(CPUX86State *env)
1b6b029e 200{
db6b81d4 201 CPUState *cs = CPU(x86_env_get_cpu(env));
bc8a22cc 202 int trapnr;
992f48a0 203 abi_ulong pc;
0284b03b 204 abi_ulong ret;
c227f099 205 target_siginfo_t info;
851e67a1 206
1b6b029e 207 for(;;) {
b040bc9c 208 cpu_exec_start(cs);
8642c1b8 209 trapnr = cpu_exec(cs);
b040bc9c 210 cpu_exec_end(cs);
d148d90e
SF		 211 process_queued_cpu_work(cs);
212
bc8a22cc 213 switch(trapnr) {
f4beb510 214 case 0x80:
d2fd1af7 215 /* linux syscall from int $0x80 */
0284b03b
TB		 216 ret = do_syscall(env,
217 env->regs[R_EAX],
218 env->regs[R_EBX],
219 env->regs[R_ECX],
220 env->regs[R_EDX],
221 env->regs[R_ESI],
222 env->regs[R_EDI],
223 env->regs[R_EBP],
224 0, 0);
225 if (ret == -TARGET_ERESTARTSYS) {
226 env->eip -= 2;
227 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
228 env->regs[R_EAX] = ret;
229 }
f4beb510 230 break;
d2fd1af7
FB		 231#ifndef TARGET_ABI32
232 case EXCP_SYSCALL:
5ba18547 233 /* linux syscall from syscall instruction */
0284b03b
TB		 234 ret = do_syscall(env,
235 env->regs[R_EAX],
236 env->regs[R_EDI],
237 env->regs[R_ESI],
238 env->regs[R_EDX],
239 env->regs[10],
240 env->regs[8],
241 env->regs[9],
242 0, 0);
243 if (ret == -TARGET_ERESTARTSYS) {
244 env->eip -= 2;
245 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
246 env->regs[R_EAX] = ret;
247 }
d2fd1af7
FB		 248 break;
249#endif
f4beb510
FB		 250 case EXCP0B_NOSEG:
251 case EXCP0C_STACK:
a86b3c64 252 info.si_signo = TARGET_SIGBUS;
f4beb510
FB		 253 info.si_errno = 0;
254 info.si_code = TARGET_SI_KERNEL;
255 info._sifields._sigfault._addr = 0;
9d2803f7 256 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
f4beb510 257 break;
1b6b029e 258 case EXCP0D_GPF:
d2fd1af7 259 /* XXX: potential problem if ABI32 */
84409ddb 260#ifndef TARGET_X86_64
851e67a1 261 if (env->eflags & VM_MASK) {
89e957e7 262 handle_vm86_fault(env);
84409ddb
JM		 263 } else
264#endif
265 {
a86b3c64 266 info.si_signo = TARGET_SIGSEGV;
f4beb510
FB		 267 info.si_errno = 0;
268 info.si_code = TARGET_SI_KERNEL;
269 info._sifields._sigfault._addr = 0;
9d2803f7 270 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1b6b029e
FB		 271 }
272 break;
b689bc57 273 case EXCP0E_PAGE:
a86b3c64 274 info.si_signo = TARGET_SIGSEGV;
b689bc57
FB		 275 info.si_errno = 0;
276 if (!(env->error_code & 1))
277 info.si_code = TARGET_SEGV_MAPERR;
278 else
279 info.si_code = TARGET_SEGV_ACCERR;
970a87a6 280 info._sifields._sigfault._addr = env->cr[2];
9d2803f7 281 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
b689bc57 282 break;
9de5e440 283 case EXCP00_DIVZ:
84409ddb 284#ifndef TARGET_X86_64
bc8a22cc 285 if (env->eflags & VM_MASK) {
447db213 286 handle_vm86_trap(env, trapnr);
84409ddb
JM		 287 } else
288#endif
289 {
bc8a22cc 290 /* division by zero */
a86b3c64 291 info.si_signo = TARGET_SIGFPE;
bc8a22cc
FB		 292 info.si_errno = 0;
293 info.si_code = TARGET_FPE_INTDIV;
294 info._sifields._sigfault._addr = env->eip;
9d2803f7 295 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
bc8a22cc 296 }
9de5e440 297 break;
01df040b 298 case EXCP01_DB:
447db213 299 case EXCP03_INT3:
84409ddb 300#ifndef TARGET_X86_64
447db213
FB		 301 if (env->eflags & VM_MASK) {
302 handle_vm86_trap(env, trapnr);
84409ddb
JM		 303 } else
304#endif
305 {
a86b3c64 306 info.si_signo = TARGET_SIGTRAP;
447db213 307 info.si_errno = 0;
01df040b 308 if (trapnr == EXCP01_DB) {
447db213
FB		 309 info.si_code = TARGET_TRAP_BRKPT;
310 info._sifields._sigfault._addr = env->eip;
311 } else {
312 info.si_code = TARGET_SI_KERNEL;
313 info._sifields._sigfault._addr = 0;
314 }
9d2803f7 315 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
447db213
FB		 316 }
317 break;
9de5e440
FB		 318 case EXCP04_INTO:
319 case EXCP05_BOUND:
84409ddb 320#ifndef TARGET_X86_64
bc8a22cc 321 if (env->eflags & VM_MASK) {
447db213 322 handle_vm86_trap(env, trapnr);
84409ddb
JM		 323 } else
324#endif
325 {
a86b3c64 326 info.si_signo = TARGET_SIGSEGV;
bc8a22cc 327 info.si_errno = 0;
b689bc57 328 info.si_code = TARGET_SI_KERNEL;
bc8a22cc 329 info._sifields._sigfault._addr = 0;
9d2803f7 330 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
bc8a22cc 331 }
9de5e440
FB		 332 break;
333 case EXCP06_ILLOP:
a86b3c64 334 info.si_signo = TARGET_SIGILL;
9de5e440
FB		 335 info.si_errno = 0;
336 info.si_code = TARGET_ILL_ILLOPN;
337 info._sifields._sigfault._addr = env->eip;
9d2803f7 338 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
9de5e440
FB		 339 break;
340 case EXCP_INTERRUPT:
341 /* just indicate that signals should be handled asap */
342 break;
1fddef4b
FB		 343 case EXCP_DEBUG:
344 {
345 int sig;
346
db6b81d4 347 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 348 if (sig)
349 {
350 info.si_signo = sig;
351 info.si_errno = 0;
352 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 353 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1fddef4b
FB		 354 }
355 }
356 break;
fdbc2b57
RH		 357 case EXCP_ATOMIC:
358 cpu_exec_step_atomic(cs);
359 break;
1b6b029e 360 default:
970a87a6 361 pc = env->segs[R_CS].base + env->eip;
120a9848
PB		 362 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
363 (long)pc, trapnr);
1b6b029e
FB		 364 abort();
365 }
66fb9763 366 process_pending_signals(env);
1b6b029e
FB		 367 }
368}
b346ff46
FB		 369#endif
370
371#ifdef TARGET_ARM
372
49017bd8 373#define get_user_code_u32(x, gaddr, env) \
d8fd2954 374 ({ abi_long __r = get_user_u32((x), (gaddr)); \
f9fd40eb 375 if (!__r && bswap_code(arm_sctlr_b(env))) { \
d8fd2954
PB		 376 (x) = bswap32(x); \
377 } \
378 __r; \
379 })
380
49017bd8 381#define get_user_code_u16(x, gaddr, env) \
d8fd2954 382 ({ abi_long __r = get_user_u16((x), (gaddr)); \
f9fd40eb 383 if (!__r && bswap_code(arm_sctlr_b(env))) { \
d8fd2954
PB		 384 (x) = bswap16(x); \
385 } \
386 __r; \
387 })
388
c3ae85fc
PB		 389#define get_user_data_u32(x, gaddr, env) \
390 ({ abi_long __r = get_user_u32((x), (gaddr)); \
391 if (!__r && arm_cpu_bswap_data(env)) { \
392 (x) = bswap32(x); \
393 } \
394 __r; \
395 })
396
397#define get_user_data_u16(x, gaddr, env) \
398 ({ abi_long __r = get_user_u16((x), (gaddr)); \
399 if (!__r && arm_cpu_bswap_data(env)) { \
400 (x) = bswap16(x); \
401 } \
402 __r; \
403 })
404
405#define put_user_data_u32(x, gaddr, env) \
406 ({ typeof(x) __x = (x); \
407 if (arm_cpu_bswap_data(env)) { \
408 __x = bswap32(__x); \
409 } \
410 put_user_u32(__x, (gaddr)); \
411 })
412
413#define put_user_data_u16(x, gaddr, env) \
414 ({ typeof(x) __x = (x); \
415 if (arm_cpu_bswap_data(env)) { \
416 __x = bswap16(__x); \
417 } \
418 put_user_u16(__x, (gaddr)); \
419 })
420
1861c454
PM		 421#ifdef TARGET_ABI32
422/* Commpage handling -- there is no commpage for AArch64 */
423
97cc7560
DDAG		 424/*
425 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
426 * Input:
427 * r0 = pointer to oldval
428 * r1 = pointer to newval
429 * r2 = pointer to target value
430 *
431 * Output:
432 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
433 * C set if *ptr was changed, clear if no exchange happened
434 *
435 * Note segv's in kernel helpers are a bit tricky, we can set the
436 * data address sensibly but the PC address is just the entry point.
437 */
438static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
439{
440 uint64_t oldval, newval, val;
441 uint32_t addr, cpsr;
442 target_siginfo_t info;
443
444 /* Based on the 32 bit code in do_kernel_trap */
445
446 /* XXX: This only works between threads, not between processes.
447 It's probably possible to implement this with native host
448 operations. However things like ldrex/strex are much harder so
449 there's not much point trying. */
450 start_exclusive();
451 cpsr = cpsr_read(env);
452 addr = env->regs[2];
453
454 if (get_user_u64(oldval, env->regs[0])) {
abf1172f 455 env->exception.vaddress = env->regs[0];
97cc7560
DDAG		 456 goto segv;
457 };
458
459 if (get_user_u64(newval, env->regs[1])) {
abf1172f 460 env->exception.vaddress = env->regs[1];
97cc7560
DDAG		 461 goto segv;
462 };
463
464 if (get_user_u64(val, addr)) {
abf1172f 465 env->exception.vaddress = addr;
97cc7560
DDAG		 466 goto segv;
467 }
468
469 if (val == oldval) {
470 val = newval;
471
472 if (put_user_u64(val, addr)) {
abf1172f 473 env->exception.vaddress = addr;
97cc7560
DDAG		 474 goto segv;
475 };
476
477 env->regs[0] = 0;
478 cpsr |= CPSR_C;
479 } else {
480 env->regs[0] = -1;
481 cpsr &= ~CPSR_C;
482 }
50866ba5 483 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
97cc7560
DDAG		 484 end_exclusive();
485 return;
486
487segv:
488 end_exclusive();
489 /* We get the PC of the entry address - which is as good as anything,
490 on a real kernel what you get depends on which mode it uses. */
a86b3c64 491 info.si_signo = TARGET_SIGSEGV;
97cc7560
DDAG		 492 info.si_errno = 0;
493 /* XXX: check env->error_code */
494 info.si_code = TARGET_SEGV_MAPERR;
abf1172f 495 info._sifields._sigfault._addr = env->exception.vaddress;
9d2803f7 496 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
97cc7560
DDAG		 497}
498
fbb4a2e3
PB		 499/* Handle a jump to the kernel code page. */
500static int
501do_kernel_trap(CPUARMState *env)
502{
503 uint32_t addr;
504 uint32_t cpsr;
505 uint32_t val;
506
507 switch (env->regs[15]) {
508 case 0xffff0fa0: /* __kernel_memory_barrier */
509 /* ??? No-op. Will need to do better for SMP. */
510 break;
511 case 0xffff0fc0: /* __kernel_cmpxchg */
d5975363
PB		 512 /* XXX: This only works between threads, not between processes.
513 It's probably possible to implement this with native host
514 operations. However things like ldrex/strex are much harder so
515 there's not much point trying. */
516 start_exclusive();
fbb4a2e3
PB		 517 cpsr = cpsr_read(env);
518 addr = env->regs[2];
519 /* FIXME: This should SEGV if the access fails. */
520 if (get_user_u32(val, addr))
521 val = ~env->regs[0];
522 if (val == env->regs[0]) {
523 val = env->regs[1];
524 /* FIXME: Check for segfaults. */
525 put_user_u32(val, addr);
526 env->regs[0] = 0;
527 cpsr |= CPSR_C;
528 } else {
529 env->regs[0] = -1;
530 cpsr &= ~CPSR_C;
531 }
50866ba5 532 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
d5975363 533 end_exclusive();
fbb4a2e3
PB		 534 break;
535 case 0xffff0fe0: /* __kernel_get_tls */
b8d43285 536 env->regs[0] = cpu_get_tls(env);
fbb4a2e3 537 break;
97cc7560
DDAG		 538 case 0xffff0f60: /* __kernel_cmpxchg64 */
539 arm_kernel_cmpxchg64_helper(env);
540 break;
541
fbb4a2e3
PB		 542 default:
543 return 1;
544 }
545 /* Jump back to the caller. */
546 addr = env->regs[14];
547 if (addr & 1) {
548 env->thumb = 1;
549 addr &= ~1;
550 }
551 env->regs[15] = addr;
552
553 return 0;
554}
555
b346ff46
FB		 556void cpu_loop(CPUARMState *env)
557{
0315c31c 558 CPUState *cs = CPU(arm_env_get_cpu(env));
b346ff46
FB		 559 int trapnr;
560 unsigned int n, insn;
c227f099 561 target_siginfo_t info;
b5ff1b31 562 uint32_t addr;
f0267ef7 563 abi_ulong ret;
3b46e624 564
b346ff46 565 for(;;) {
0315c31c 566 cpu_exec_start(cs);
8642c1b8 567 trapnr = cpu_exec(cs);
0315c31c 568 cpu_exec_end(cs);
d148d90e
SF		 569 process_queued_cpu_work(cs);
570
b346ff46
FB		 571 switch(trapnr) {
572 case EXCP_UDEF:
c6981055 573 {
0429a971 574 TaskState *ts = cs->opaque;
c6981055 575 uint32_t opcode;
6d9a42be 576 int rc;
c6981055
FB		 577
578 /* we handle the FPU emulation here, as Linux */
579 /* we get the opcode */
2f619698 580 /* FIXME - what to do if get_user() fails? */
49017bd8 581 get_user_code_u32(opcode, env->regs[15], env);
3b46e624 582
6d9a42be
AJ		 583 rc = EmulateAll(opcode, &ts->fpa, env);
584 if (rc == 0) { /* illegal instruction */
a86b3c64 585 info.si_signo = TARGET_SIGILL;
c6981055
FB		 586 info.si_errno = 0;
587 info.si_code = TARGET_ILL_ILLOPN;
588 info._sifields._sigfault._addr = env->regs[15];
9d2803f7 589 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
6d9a42be
AJ		 590 } else if (rc < 0) { /* FP exception */
591 int arm_fpe=0;
592
593 /* translate softfloat flags to FPSR flags */
594 if (-rc & float_flag_invalid)
595 arm_fpe |= BIT_IOC;
596 if (-rc & float_flag_divbyzero)
597 arm_fpe |= BIT_DZC;
598 if (-rc & float_flag_overflow)
599 arm_fpe |= BIT_OFC;
600 if (-rc & float_flag_underflow)
601 arm_fpe |= BIT_UFC;
602 if (-rc & float_flag_inexact)
603 arm_fpe |= BIT_IXC;
604
605 FPSR fpsr = ts->fpa.fpsr;
606 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
607
608 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
a86b3c64 609 info.si_signo = TARGET_SIGFPE;
6d9a42be
AJ		 610 info.si_errno = 0;
611
612 /* ordered by priority, least first */
613 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
614 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
615 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
616 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
617 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
618
619 info._sifields._sigfault._addr = env->regs[15];
9d2803f7 620 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
6d9a42be
AJ		 621 } else {
622 env->regs[15] += 4;
623 }
624
625 /* accumulate unenabled exceptions */
626 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
627 fpsr |= BIT_IXC;
628 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
629 fpsr |= BIT_UFC;
630 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
631 fpsr |= BIT_OFC;
632 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
633 fpsr |= BIT_DZC;
634 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
635 fpsr |= BIT_IOC;
636 ts->fpa.fpsr=fpsr;
637 } else { /* everything OK */
c6981055
FB		 638 /* increment PC */
639 env->regs[15] += 4;
640 }
641 }
b346ff46
FB		 642 break;
643 case EXCP_SWI:
06c949e6 644 case EXCP_BKPT:
b346ff46 645 {
ce4defa0 646 env->eabi = 1;
b346ff46 647 /* system call */
06c949e6
PB		 648 if (trapnr == EXCP_BKPT) {
649 if (env->thumb) {
2f619698 650 /* FIXME - what to do if get_user() fails? */
49017bd8 651 get_user_code_u16(insn, env->regs[15], env);
06c949e6
PB		 652 n = insn & 0xff;
653 env->regs[15] += 2;
654 } else {
2f619698 655 /* FIXME - what to do if get_user() fails? */
49017bd8 656 get_user_code_u32(insn, env->regs[15], env);
06c949e6
PB		 657 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
658 env->regs[15] += 4;
659 }
192c7bd9 660 } else {
06c949e6 661 if (env->thumb) {
2f619698 662 /* FIXME - what to do if get_user() fails? */
49017bd8 663 get_user_code_u16(insn, env->regs[15] - 2, env);
06c949e6
PB		 664 n = insn & 0xff;
665 } else {
2f619698 666 /* FIXME - what to do if get_user() fails? */
49017bd8 667 get_user_code_u32(insn, env->regs[15] - 4, env);
06c949e6
PB		 668 n = insn & 0xffffff;
669 }
192c7bd9
FB		 670 }
671
6f1f31c0 672 if (n == ARM_NR_cacheflush) {
dcfd14b3 673 /* nop */
a4f81979
FB		 674 } else if (n == ARM_NR_semihosting
675 || n == ARM_NR_thumb_semihosting) {
676 env->regs[0] = do_arm_semihosting (env);
3a1363ac 677 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
b346ff46 678 /* linux syscall */
ce4defa0 679 if (env->thumb || n == 0) {
192c7bd9
FB		 680 n = env->regs[7];
681 } else {
682 n -= ARM_SYSCALL_BASE;
ce4defa0 683 env->eabi = 0;
192c7bd9 684 }
fbb4a2e3
PB		 685 if ( n > ARM_NR_BASE) {
686 switch (n) {
687 case ARM_NR_cacheflush:
dcfd14b3 688 /* nop */
fbb4a2e3
PB		 689 break;
690 case ARM_NR_set_tls:
691 cpu_set_tls(env, env->regs[0]);
692 env->regs[0] = 0;
693 break;
d5355087
HL		 694 case ARM_NR_breakpoint:
695 env->regs[15] -= env->thumb ? 2 : 4;
696 goto excp_debug;
fbb4a2e3
PB		 697 default:
698 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
699 n);
700 env->regs[0] = -TARGET_ENOSYS;
701 break;
702 }
703 } else {
f0267ef7
TB		 704 ret = do_syscall(env,
705 n,
706 env->regs[0],
707 env->regs[1],
708 env->regs[2],
709 env->regs[3],
710 env->regs[4],
711 env->regs[5],
712 0, 0);
713 if (ret == -TARGET_ERESTARTSYS) {
714 env->regs[15] -= env->thumb ? 2 : 4;
715 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
716 env->regs[0] = ret;
717 }
fbb4a2e3 718 }
b346ff46
FB		 719 } else {
720 goto error;
721 }
722 }
723 break;
19a6e31c
PM		 724 case EXCP_SEMIHOST:
725 env->regs[0] = do_arm_semihosting(env);
726 break;
43fff238
FB		 727 case EXCP_INTERRUPT:
728 /* just indicate that signals should be handled asap */
729 break;
68016c62
FB		 730 case EXCP_PREFETCH_ABORT:
731 case EXCP_DATA_ABORT:
abf1172f 732 addr = env->exception.vaddress;
68016c62 733 {
a86b3c64 734 info.si_signo = TARGET_SIGSEGV;
68016c62
FB		 735 info.si_errno = 0;
736 /* XXX: check env->error_code */
737 info.si_code = TARGET_SEGV_MAPERR;
b5ff1b31 738 info._sifields._sigfault._addr = addr;
9d2803f7 739 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
68016c62
FB		 740 }
741 break;
1fddef4b 742 case EXCP_DEBUG:
d5355087 743 excp_debug:
1fddef4b
FB		 744 {
745 int sig;
746
db6b81d4 747 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 748 if (sig)
749 {
750 info.si_signo = sig;
751 info.si_errno = 0;
752 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 753 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1fddef4b
FB		 754 }
755 }
756 break;
fbb4a2e3
PB		 757 case EXCP_KERNEL_TRAP:
758 if (do_kernel_trap(env))
759 goto error;
760 break;
f911e0a3
PM		 761 case EXCP_YIELD:
762 /* nothing to do here for user-mode, just resume guest code */
763 break;
fdbc2b57
RH		 764 case EXCP_ATOMIC:
765 cpu_exec_step_atomic(cs);
766 break;
b346ff46
FB		 767 default:
768 error:
120a9848 769 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
b346ff46
FB		 770 abort();
771 }
772 process_pending_signals(env);
773 }
774}
775
1861c454
PM		 776#else
777
778/* AArch64 main loop */
779void cpu_loop(CPUARMState *env)
780{
781 CPUState *cs = CPU(arm_env_get_cpu(env));
782 int trapnr, sig;
f0267ef7 783 abi_long ret;
1861c454 784 target_siginfo_t info;
1861c454
PM		 785
786 for (;;) {
787 cpu_exec_start(cs);
8642c1b8 788 trapnr = cpu_exec(cs);
1861c454 789 cpu_exec_end(cs);
d148d90e 790 process_queued_cpu_work(cs);
1861c454
PM		 791
792 switch (trapnr) {
793 case EXCP_SWI:
f0267ef7
TB		 794 ret = do_syscall(env,
795 env->xregs[8],
796 env->xregs[0],
797 env->xregs[1],
798 env->xregs[2],
799 env->xregs[3],
800 env->xregs[4],
801 env->xregs[5],
802 0, 0);
803 if (ret == -TARGET_ERESTARTSYS) {
804 env->pc -= 4;
805 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
806 env->xregs[0] = ret;
807 }
1861c454
PM		 808 break;
809 case EXCP_INTERRUPT:
810 /* just indicate that signals should be handled asap */
811 break;
812 case EXCP_UDEF:
a86b3c64 813 info.si_signo = TARGET_SIGILL;
1861c454
PM		 814 info.si_errno = 0;
815 info.si_code = TARGET_ILL_ILLOPN;
816 info._sifields._sigfault._addr = env->pc;
9d2803f7 817 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1861c454
PM		 818 break;
819 case EXCP_PREFETCH_ABORT:
1861c454 820 case EXCP_DATA_ABORT:
a86b3c64 821 info.si_signo = TARGET_SIGSEGV;
1861c454
PM		 822 info.si_errno = 0;
823 /* XXX: check env->error_code */
824 info.si_code = TARGET_SEGV_MAPERR;
686581ad 825 info._sifields._sigfault._addr = env->exception.vaddress;
9d2803f7 826 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1861c454
PM		 827 break;
828 case EXCP_DEBUG:
829 case EXCP_BKPT:
830 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
831 if (sig) {
832 info.si_signo = sig;
833 info.si_errno = 0;
834 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 835 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1861c454
PM		 836 }
837 break;
8012c84f
PM		 838 case EXCP_SEMIHOST:
839 env->xregs[0] = do_arm_semihosting(env);
840 break;
f911e0a3
PM		 841 case EXCP_YIELD:
842 /* nothing to do here for user-mode, just resume guest code */
843 break;
fdbc2b57
RH		 844 case EXCP_ATOMIC:
845 cpu_exec_step_atomic(cs);
846 break;
1861c454 847 default:
120a9848 848 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1861c454
PM		 849 abort();
850 }
851 process_pending_signals(env);
fa2ef212
MM		 852 /* Exception return on AArch64 always clears the exclusive monitor,
853 * so any return to running guest code implies this.
fa2ef212
MM		 854 */
855 env->exclusive_addr = -1;
1861c454
PM		 856 }
857}
858#endif /* ndef TARGET_ABI32 */
859
b346ff46 860#endif
1b6b029e 861
d2fbca94
GX		 862#ifdef TARGET_UNICORE32
863
05390248 864void cpu_loop(CPUUniCore32State *env)
d2fbca94 865{
0315c31c 866 CPUState *cs = CPU(uc32_env_get_cpu(env));
d2fbca94
GX		 867 int trapnr;
868 unsigned int n, insn;
869 target_siginfo_t info;
870
871 for (;;) {
0315c31c 872 cpu_exec_start(cs);
8642c1b8 873 trapnr = cpu_exec(cs);
0315c31c 874 cpu_exec_end(cs);
d148d90e
SF		 875 process_queued_cpu_work(cs);
876
d2fbca94
GX		 877 switch (trapnr) {
878 case UC32_EXCP_PRIV:
879 {
880 /* system call */
881 get_user_u32(insn, env->regs[31] - 4);
882 n = insn & 0xffffff;
883
884 if (n >= UC32_SYSCALL_BASE) {
885 /* linux syscall */
886 n -= UC32_SYSCALL_BASE;
887 if (n == UC32_SYSCALL_NR_set_tls) {
888 cpu_set_tls(env, env->regs[0]);
889 env->regs[0] = 0;
890 } else {
256cb6af 891 abi_long ret = do_syscall(env,
d2fbca94
GX		 892 n,
893 env->regs[0],
894 env->regs[1],
895 env->regs[2],
896 env->regs[3],
897 env->regs[4],
5945cfcb
PM		 898 env->regs[5],
899 0, 0);
256cb6af
TB		 900 if (ret == -TARGET_ERESTARTSYS) {
901 env->regs[31] -= 4;
902 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
903 env->regs[0] = ret;
904 }
d2fbca94
GX		 905 }
906 } else {
907 goto error;
908 }
909 }
910 break;
d48813dd
GX		 911 case UC32_EXCP_DTRAP:
912 case UC32_EXCP_ITRAP:
a86b3c64 913 info.si_signo = TARGET_SIGSEGV;
d2fbca94
GX		 914 info.si_errno = 0;
915 /* XXX: check env->error_code */
916 info.si_code = TARGET_SEGV_MAPERR;
917 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
9d2803f7 918 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
d2fbca94
GX		 919 break;
920 case EXCP_INTERRUPT:
921 /* just indicate that signals should be handled asap */
922 break;
923 case EXCP_DEBUG:
924 {
925 int sig;
926
db6b81d4 927 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d2fbca94
GX		 928 if (sig) {
929 info.si_signo = sig;
930 info.si_errno = 0;
931 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 932 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
d2fbca94
GX		 933 }
934 }
935 break;
fdbc2b57
RH		 936 case EXCP_ATOMIC:
937 cpu_exec_step_atomic(cs);
938 break;
d2fbca94
GX		 939 default:
940 goto error;
941 }
942 process_pending_signals(env);
943 }
944
945error:
120a9848 946 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
d2fbca94
GX		 947 abort();
948}
949#endif
950
93ac68bc 951#ifdef TARGET_SPARC
ed23fbd9 952#define SPARC64_STACK_BIAS 2047
93ac68bc 953
060366c5
FB		 954//#define DEBUG_WIN
955
2623cbaf
FB		 956/* WARNING: dealing with register windows _is_ complicated. More info
957 can be found at http://www.sics.se/~psm/sparcstack.html */
060366c5
FB		 958static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
959{
1a14026e 960 index = (index + cwp * 16) % (16 * env->nwindows);
060366c5
FB		 961 /* wrap handling : if cwp is on the last window, then we use the
962 registers 'after' the end */
1a14026e
BS		 963 if (index < 8 && env->cwp == env->nwindows - 1)
964 index += 16 * env->nwindows;
060366c5
FB		 965 return index;
966}
967
2623cbaf
FB		 968/* save the register window 'cwp1' */
969static inline void save_window_offset(CPUSPARCState *env, int cwp1)
060366c5 970{
2623cbaf 971 unsigned int i;
992f48a0 972 abi_ulong sp_ptr;
3b46e624 973
53a5960a 974 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 975#ifdef TARGET_SPARC64
976 if (sp_ptr & 3)
977 sp_ptr += SPARC64_STACK_BIAS;
978#endif
060366c5 979#if defined(DEBUG_WIN)
2daf0284
BS		 980 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
981 sp_ptr, cwp1);
060366c5 982#endif
2623cbaf 983 for(i = 0; i < 16; i++) {
2f619698
FB		 984 /* FIXME - what to do if put_user() fails? */
985 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 986 sp_ptr += sizeof(abi_ulong);
2623cbaf 987 }
060366c5
FB		 988}
989
990static void save_window(CPUSPARCState *env)
991{
5ef54116 992#ifndef TARGET_SPARC64
2623cbaf 993 unsigned int new_wim;
1a14026e
BS		 994 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
995 ((1LL << env->nwindows) - 1);
996 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
2623cbaf 997 env->wim = new_wim;
5ef54116 998#else
1a14026e 999 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
5ef54116
FB		 1000 env->cansave++;
1001 env->canrestore--;
1002#endif
060366c5
FB		 1003}
1004
1005static void restore_window(CPUSPARCState *env)
1006{
eda52953
BS		 1007#ifndef TARGET_SPARC64
1008 unsigned int new_wim;
1009#endif
1010 unsigned int i, cwp1;
992f48a0 1011 abi_ulong sp_ptr;
3b46e624 1012
eda52953 1013#ifndef TARGET_SPARC64
1a14026e
BS		 1014 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1015 ((1LL << env->nwindows) - 1);
eda52953 1016#endif
3b46e624 1017
060366c5 1018 /* restore the invalid window */
1a14026e 1019 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
53a5960a 1020 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1021#ifdef TARGET_SPARC64
1022 if (sp_ptr & 3)
1023 sp_ptr += SPARC64_STACK_BIAS;
1024#endif
060366c5 1025#if defined(DEBUG_WIN)
2daf0284
BS		 1026 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1027 sp_ptr, cwp1);
060366c5 1028#endif
2623cbaf 1029 for(i = 0; i < 16; i++) {
2f619698
FB		 1030 /* FIXME - what to do if get_user() fails? */
1031 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1032 sp_ptr += sizeof(abi_ulong);
2623cbaf 1033 }
5ef54116
FB		 1034#ifdef TARGET_SPARC64
1035 env->canrestore++;
1a14026e
BS		 1036 if (env->cleanwin < env->nwindows - 1)
1037 env->cleanwin++;
5ef54116 1038 env->cansave--;
eda52953
BS		 1039#else
1040 env->wim = new_wim;
5ef54116 1041#endif
060366c5
FB		 1042}
1043
1044static void flush_windows(CPUSPARCState *env)
1045{
1046 int offset, cwp1;
2623cbaf
FB		 1047
1048 offset = 1;
060366c5
FB		 1049 for(;;) {
1050 /* if restore would invoke restore_window(), then we can stop */
1a14026e 1051 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
eda52953 1052#ifndef TARGET_SPARC64
060366c5
FB		 1053 if (env->wim & (1 << cwp1))
1054 break;
eda52953
BS		 1055#else
1056 if (env->canrestore == 0)
1057 break;
1058 env->cansave++;
1059 env->canrestore--;
1060#endif
2623cbaf 1061 save_window_offset(env, cwp1);
060366c5
FB		 1062 offset++;
1063 }
1a14026e 1064 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
eda52953
BS		 1065#ifndef TARGET_SPARC64
1066 /* set wim so that restore will reload the registers */
2623cbaf 1067 env->wim = 1 << cwp1;
eda52953 1068#endif
2623cbaf
FB		 1069#if defined(DEBUG_WIN)
1070 printf("flush_windows: nb=%d\n", offset - 1);
80a9d035 1071#endif
2623cbaf 1072}
060366c5 1073
93ac68bc
FB		 1074void cpu_loop (CPUSPARCState *env)
1075{
878096ee 1076 CPUState *cs = CPU(sparc_env_get_cpu(env));
2cc20260
RH		 1077 int trapnr;
1078 abi_long ret;
c227f099 1079 target_siginfo_t info;
3b46e624 1080
060366c5 1081 while (1) {
b040bc9c 1082 cpu_exec_start(cs);
8642c1b8 1083 trapnr = cpu_exec(cs);
b040bc9c 1084 cpu_exec_end(cs);
d148d90e 1085 process_queued_cpu_work(cs);
3b46e624 1086
20132b96
RH		 1087 /* Compute PSR before exposing state. */
1088 if (env->cc_op != CC_OP_FLAGS) {
1089 cpu_get_psr(env);
1090 }
1091
060366c5 1092 switch (trapnr) {
5ef54116 1093#ifndef TARGET_SPARC64
5fafdf24 1094 case 0x88:
060366c5 1095 case 0x90:
5ef54116 1096#else
cb33da57 1097 case 0x110:
5ef54116
FB		 1098 case 0x16d:
1099#endif
060366c5 1100 ret = do_syscall (env, env->gregs[1],
5fafdf24
TS		 1101 env->regwptr[0], env->regwptr[1],
1102 env->regwptr[2], env->regwptr[3],
5945cfcb
PM		 1103 env->regwptr[4], env->regwptr[5],
1104 0, 0);
c0bea68f
TB		 1105 if (ret == -TARGET_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) {
1106 break;
1107 }
2cc20260 1108 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
992f48a0 1109#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1110 env->xcc |= PSR_CARRY;
1111#else
060366c5 1112 env->psr |= PSR_CARRY;
27908725 1113#endif
060366c5
FB		 1114 ret = -ret;
1115 } else {
992f48a0 1116#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1117 env->xcc &= ~PSR_CARRY;
1118#else
060366c5 1119 env->psr &= ~PSR_CARRY;
27908725 1120#endif
060366c5
FB		 1121 }
1122 env->regwptr[0] = ret;
1123 /* next instruction */
1124 env->pc = env->npc;
1125 env->npc = env->npc + 4;
1126 break;
1127 case 0x83: /* flush windows */
992f48a0
BS		 1128#ifdef TARGET_ABI32
1129 case 0x103:
1130#endif
2623cbaf 1131 flush_windows(env);
060366c5
FB		 1132 /* next instruction */
1133 env->pc = env->npc;
1134 env->npc = env->npc + 4;
1135 break;
3475187d 1136#ifndef TARGET_SPARC64
060366c5
FB		 1137 case TT_WIN_OVF: /* window overflow */
1138 save_window(env);
1139 break;
1140 case TT_WIN_UNF: /* window underflow */
1141 restore_window(env);
1142 break;
61ff6f58
FB		 1143 case TT_TFAULT:
1144 case TT_DFAULT:
1145 {
59f7182f 1146 info.si_signo = TARGET_SIGSEGV;
61ff6f58
FB		 1147 info.si_errno = 0;
1148 /* XXX: check env->error_code */
1149 info.si_code = TARGET_SEGV_MAPERR;
1150 info._sifields._sigfault._addr = env->mmuregs[4];
9d2803f7 1151 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
61ff6f58
FB		 1152 }
1153 break;
3475187d 1154#else
5ef54116
FB		 1155 case TT_SPILL: /* window overflow */
1156 save_window(env);
1157 break;
1158 case TT_FILL: /* window underflow */
1159 restore_window(env);
1160 break;
7f84a729
BS		 1161 case TT_TFAULT:
1162 case TT_DFAULT:
1163 {
59f7182f 1164 info.si_signo = TARGET_SIGSEGV;
7f84a729
BS		 1165 info.si_errno = 0;
1166 /* XXX: check env->error_code */
1167 info.si_code = TARGET_SEGV_MAPERR;
1168 if (trapnr == TT_DFAULT)
1169 info._sifields._sigfault._addr = env->dmmuregs[4];
1170 else
8194f35a 1171 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
9d2803f7 1172 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
7f84a729
BS		 1173 }
1174 break;
27524dc3 1175#ifndef TARGET_ABI32
5bfb56b2
BS		 1176 case 0x16e:
1177 flush_windows(env);
1178 sparc64_get_context(env);
1179 break;
1180 case 0x16f:
1181 flush_windows(env);
1182 sparc64_set_context(env);
1183 break;
27524dc3 1184#endif
3475187d 1185#endif
48dc41eb
FB		 1186 case EXCP_INTERRUPT:
1187 /* just indicate that signals should be handled asap */
1188 break;
75f22e4e
RH		 1189 case TT_ILL_INSN:
1190 {
1191 info.si_signo = TARGET_SIGILL;
1192 info.si_errno = 0;
1193 info.si_code = TARGET_ILL_ILLOPC;
1194 info._sifields._sigfault._addr = env->pc;
9d2803f7 1195 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
75f22e4e
RH		 1196 }
1197 break;
1fddef4b
FB		 1198 case EXCP_DEBUG:
1199 {
1200 int sig;
1201
db6b81d4 1202 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 1203 if (sig)
1204 {
1205 info.si_signo = sig;
1206 info.si_errno = 0;
1207 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 1208 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1fddef4b
FB		 1209 }
1210 }
1211 break;
fdbc2b57
RH		 1212 case EXCP_ATOMIC:
1213 cpu_exec_step_atomic(cs);
1214 break;
060366c5
FB		 1215 default:
1216 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 1217 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 1218 exit(EXIT_FAILURE);
060366c5
FB		 1219 }
1220 process_pending_signals (env);
1221 }
93ac68bc
FB		 1222}
1223
1224#endif
1225
67867308 1226#ifdef TARGET_PPC
05390248 1227static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
9fddaa0c 1228{
4a7428c5 1229 return cpu_get_host_ticks();
9fddaa0c 1230}
3b46e624 1231
05390248 1232uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
9fddaa0c 1233{
e3ea6529 1234 return cpu_ppc_get_tb(env);
9fddaa0c 1235}
3b46e624 1236
05390248 1237uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
9fddaa0c
FB		 1238{
1239 return cpu_ppc_get_tb(env) >> 32;
1240}
3b46e624 1241
05390248 1242uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
9fddaa0c 1243{
b711de95 1244 return cpu_ppc_get_tb(env);
9fddaa0c 1245}
5fafdf24 1246
05390248 1247uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
9fddaa0c 1248{
a062e36c 1249 return cpu_ppc_get_tb(env) >> 32;
9fddaa0c 1250}
76a66253 1251
05390248 1252uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
76a66253
JM		 1253__attribute__ (( alias ("cpu_ppc_load_tbu") ));
1254
05390248 1255uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
9fddaa0c 1256{
76a66253 1257 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
9fddaa0c 1258}
76a66253 1259
a750fc0b 1260/* XXX: to be fixed */
73b01960 1261int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
a750fc0b
JM		 1262{
1263 return -1;
1264}
1265
73b01960 1266int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
a750fc0b
JM		 1267{
1268 return -1;
1269}
1270
56f066bb
NF		 1271static int do_store_exclusive(CPUPPCState *env)
1272{
1273 target_ulong addr;
1274 target_ulong page_addr;
e22c357b 1275 target_ulong val, val2 __attribute__((unused)) = 0;
56f066bb
NF		 1276 int flags;
1277 int segv = 0;
1278
1279 addr = env->reserve_ea;
1280 page_addr = addr & TARGET_PAGE_MASK;
1281 start_exclusive();
1282 mmap_lock();
1283 flags = page_get_flags(page_addr);
1284 if ((flags & PAGE_READ) == 0) {
1285 segv = 1;
1286 } else {
1287 int reg = env->reserve_info & 0x1f;
4b1daa72 1288 int size = env->reserve_info >> 5;
56f066bb
NF		 1289 int stored = 0;
1290
1291 if (addr == env->reserve_addr) {
1292 switch (size) {
1293 case 1: segv = get_user_u8(val, addr); break;
1294 case 2: segv = get_user_u16(val, addr); break;
1295 case 4: segv = get_user_u32(val, addr); break;
1296#if defined(TARGET_PPC64)
1297 case 8: segv = get_user_u64(val, addr); break;
27b95bfe
TM		 1298 case 16: {
1299 segv = get_user_u64(val, addr);
1300 if (!segv) {
1301 segv = get_user_u64(val2, addr + 8);
1302 }
1303 break;
1304 }
56f066bb
NF		 1305#endif
1306 default: abort();
1307 }
1308 if (!segv && val == env->reserve_val) {
1309 val = env->gpr[reg];
1310 switch (size) {
1311 case 1: segv = put_user_u8(val, addr); break;
1312 case 2: segv = put_user_u16(val, addr); break;
1313 case 4: segv = put_user_u32(val, addr); break;
1314#if defined(TARGET_PPC64)
1315 case 8: segv = put_user_u64(val, addr); break;
27b95bfe
TM		 1316 case 16: {
1317 if (val2 == env->reserve_val2) {
e22c357b
DK		 1318 if (msr_le) {
1319 val2 = val;
1320 val = env->gpr[reg+1];
1321 } else {
1322 val2 = env->gpr[reg+1];
1323 }
27b95bfe
TM		 1324 segv = put_user_u64(val, addr);
1325 if (!segv) {
1326 segv = put_user_u64(val2, addr + 8);
1327 }
1328 }
1329 break;
1330 }
56f066bb
NF		 1331#endif
1332 default: abort();
1333 }
1334 if (!segv) {
1335 stored = 1;
1336 }
1337 }
1338 }
1339 env->crf[0] = (stored << 1) | xer_so;
1340 env->reserve_addr = (target_ulong)-1;
1341 }
1342 if (!segv) {
1343 env->nip += 4;
1344 }
1345 mmap_unlock();
1346 end_exclusive();
1347 return segv;
1348}
1349
67867308
FB		 1350void cpu_loop(CPUPPCState *env)
1351{
0315c31c 1352 CPUState *cs = CPU(ppc_env_get_cpu(env));
c227f099 1353 target_siginfo_t info;
61190b14 1354 int trapnr;
9e0e2f96 1355 target_ulong ret;
3b46e624 1356
67867308 1357 for(;;) {
0315c31c 1358 cpu_exec_start(cs);
8642c1b8 1359 trapnr = cpu_exec(cs);
0315c31c 1360 cpu_exec_end(cs);
d148d90e
SF		 1361 process_queued_cpu_work(cs);
1362
67867308 1363 switch(trapnr) {
e1833e1f
JM		 1364 case POWERPC_EXCP_NONE:
1365 /* Just go on */
67867308 1366 break;
e1833e1f 1367 case POWERPC_EXCP_CRITICAL: /* Critical input */
a47dddd7 1368 cpu_abort(cs, "Critical interrupt while in user mode. "
e1833e1f 1369 "Aborting\n");
61190b14 1370 break;
e1833e1f 1371 case POWERPC_EXCP_MCHECK: /* Machine check exception */
a47dddd7 1372 cpu_abort(cs, "Machine check exception while in user mode. "
e1833e1f
JM		 1373 "Aborting\n");
1374 break;
1375 case POWERPC_EXCP_DSI: /* Data storage exception */
e1833e1f 1376 /* XXX: check this. Seems bugged */
2be0071f
FB		 1377 switch (env->error_code & 0xFF000000) {
1378 case 0x40000000:
ba4a8df8 1379 case 0x42000000:
61190b14
FB		 1380 info.si_signo = TARGET_SIGSEGV;
1381 info.si_errno = 0;
1382 info.si_code = TARGET_SEGV_MAPERR;
1383 break;
2be0071f 1384 case 0x04000000:
61190b14
FB		 1385 info.si_signo = TARGET_SIGILL;
1386 info.si_errno = 0;
1387 info.si_code = TARGET_ILL_ILLADR;
1388 break;
2be0071f 1389 case 0x08000000:
61190b14
FB		 1390 info.si_signo = TARGET_SIGSEGV;
1391 info.si_errno = 0;
1392 info.si_code = TARGET_SEGV_ACCERR;
1393 break;
61190b14
FB		 1394 default:
1395 /* Let's send a regular segfault... */
e1833e1f
JM		 1396 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1397 env->error_code);
61190b14
FB		 1398 info.si_signo = TARGET_SIGSEGV;
1399 info.si_errno = 0;
1400 info.si_code = TARGET_SEGV_MAPERR;
1401 break;
1402 }
67867308 1403 info._sifields._sigfault._addr = env->nip;
9d2803f7 1404 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
67867308 1405 break;
e1833e1f 1406 case POWERPC_EXCP_ISI: /* Instruction storage exception */
e1833e1f 1407 /* XXX: check this */
2be0071f
FB		 1408 switch (env->error_code & 0xFF000000) {
1409 case 0x40000000:
61190b14 1410 info.si_signo = TARGET_SIGSEGV;
67867308 1411 info.si_errno = 0;
61190b14
FB		 1412 info.si_code = TARGET_SEGV_MAPERR;
1413 break;
2be0071f
FB		 1414 case 0x10000000:
1415 case 0x08000000:
61190b14
FB		 1416 info.si_signo = TARGET_SIGSEGV;
1417 info.si_errno = 0;
1418 info.si_code = TARGET_SEGV_ACCERR;
1419 break;
1420 default:
1421 /* Let's send a regular segfault... */
e1833e1f
JM		 1422 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1423 env->error_code);
61190b14
FB		 1424 info.si_signo = TARGET_SIGSEGV;
1425 info.si_errno = 0;
1426 info.si_code = TARGET_SEGV_MAPERR;
1427 break;
1428 }
1429 info._sifields._sigfault._addr = env->nip - 4;
9d2803f7 1430 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
67867308 1431 break;
e1833e1f 1432 case POWERPC_EXCP_EXTERNAL: /* External input */
a47dddd7 1433 cpu_abort(cs, "External interrupt while in user mode. "
e1833e1f
JM		 1434 "Aborting\n");
1435 break;
1436 case POWERPC_EXCP_ALIGN: /* Alignment exception */
e1833e1f 1437 /* XXX: check this */
61190b14 1438 info.si_signo = TARGET_SIGBUS;
67867308 1439 info.si_errno = 0;
61190b14 1440 info.si_code = TARGET_BUS_ADRALN;
6bb9a0a9 1441 info._sifields._sigfault._addr = env->nip;
9d2803f7 1442 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
67867308 1443 break;
e1833e1f 1444 case POWERPC_EXCP_PROGRAM: /* Program exception */
9b2fadda 1445 case POWERPC_EXCP_HV_EMU: /* HV emulation */
e1833e1f 1446 /* XXX: check this */
61190b14 1447 switch (env->error_code & ~0xF) {
e1833e1f 1448 case POWERPC_EXCP_FP:
61190b14
FB		 1449 info.si_signo = TARGET_SIGFPE;
1450 info.si_errno = 0;
1451 switch (env->error_code & 0xF) {
e1833e1f 1452 case POWERPC_EXCP_FP_OX:
61190b14
FB		 1453 info.si_code = TARGET_FPE_FLTOVF;
1454 break;
e1833e1f 1455 case POWERPC_EXCP_FP_UX:
61190b14
FB		 1456 info.si_code = TARGET_FPE_FLTUND;
1457 break;
e1833e1f
JM		 1458 case POWERPC_EXCP_FP_ZX:
1459 case POWERPC_EXCP_FP_VXZDZ:
61190b14
FB		 1460 info.si_code = TARGET_FPE_FLTDIV;
1461 break;
e1833e1f 1462 case POWERPC_EXCP_FP_XX:
61190b14
FB		 1463 info.si_code = TARGET_FPE_FLTRES;
1464 break;
e1833e1f 1465 case POWERPC_EXCP_FP_VXSOFT:
61190b14
FB		 1466 info.si_code = TARGET_FPE_FLTINV;
1467 break;
7c58044c 1468 case POWERPC_EXCP_FP_VXSNAN:
e1833e1f
JM		 1469 case POWERPC_EXCP_FP_VXISI:
1470 case POWERPC_EXCP_FP_VXIDI:
1471 case POWERPC_EXCP_FP_VXIMZ:
1472 case POWERPC_EXCP_FP_VXVC:
1473 case POWERPC_EXCP_FP_VXSQRT:
1474 case POWERPC_EXCP_FP_VXCVI:
61190b14
FB		 1475 info.si_code = TARGET_FPE_FLTSUB;
1476 break;
1477 default:
e1833e1f
JM		 1478 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1479 env->error_code);
1480 break;
61190b14 1481 }
e1833e1f
JM		 1482 break;
1483 case POWERPC_EXCP_INVAL:
61190b14
FB		 1484 info.si_signo = TARGET_SIGILL;
1485 info.si_errno = 0;
1486 switch (env->error_code & 0xF) {
e1833e1f 1487 case POWERPC_EXCP_INVAL_INVAL:
61190b14
FB		 1488 info.si_code = TARGET_ILL_ILLOPC;
1489 break;
e1833e1f 1490 case POWERPC_EXCP_INVAL_LSWX:
a750fc0b 1491 info.si_code = TARGET_ILL_ILLOPN;
61190b14 1492 break;
e1833e1f 1493 case POWERPC_EXCP_INVAL_SPR:
61190b14
FB		 1494 info.si_code = TARGET_ILL_PRVREG;
1495 break;
e1833e1f 1496 case POWERPC_EXCP_INVAL_FP:
61190b14
FB		 1497 info.si_code = TARGET_ILL_COPROC;
1498 break;
1499 default:
e1833e1f
JM		 1500 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1501 env->error_code & 0xF);
61190b14
FB		 1502 info.si_code = TARGET_ILL_ILLADR;
1503 break;
1504 }
1505 break;
e1833e1f 1506 case POWERPC_EXCP_PRIV:
61190b14
FB		 1507 info.si_signo = TARGET_SIGILL;
1508 info.si_errno = 0;
1509 switch (env->error_code & 0xF) {
e1833e1f 1510 case POWERPC_EXCP_PRIV_OPC:
61190b14
FB		 1511 info.si_code = TARGET_ILL_PRVOPC;
1512 break;
e1833e1f 1513 case POWERPC_EXCP_PRIV_REG:
61190b14 1514 info.si_code = TARGET_ILL_PRVREG;
e1833e1f 1515 break;
61190b14 1516 default:
e1833e1f
JM		 1517 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1518 env->error_code & 0xF);
61190b14
FB		 1519 info.si_code = TARGET_ILL_PRVOPC;
1520 break;
1521 }
1522 break;
e1833e1f 1523 case POWERPC_EXCP_TRAP:
a47dddd7 1524 cpu_abort(cs, "Tried to call a TRAP\n");
e1833e1f 1525 break;
61190b14
FB		 1526 default:
1527 /* Should not happen ! */
a47dddd7 1528 cpu_abort(cs, "Unknown program exception (%02x)\n",
e1833e1f
JM		 1529 env->error_code);
1530 break;
61190b14 1531 }
bd6fefe7 1532 info._sifields._sigfault._addr = env->nip;
9d2803f7 1533 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
67867308 1534 break;
e1833e1f 1535 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
61190b14 1536 info.si_signo = TARGET_SIGILL;
67867308 1537 info.si_errno = 0;
61190b14 1538 info.si_code = TARGET_ILL_COPROC;
bd6fefe7 1539 info._sifields._sigfault._addr = env->nip;
9d2803f7 1540 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
67867308 1541 break;
e1833e1f 1542 case POWERPC_EXCP_SYSCALL: /* System call exception */
a47dddd7 1543 cpu_abort(cs, "Syscall exception while in user mode. "
e1833e1f 1544 "Aborting\n");
61190b14 1545 break;
e1833e1f 1546 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
e1833e1f
JM		 1547 info.si_signo = TARGET_SIGILL;
1548 info.si_errno = 0;
1549 info.si_code = TARGET_ILL_COPROC;
bd6fefe7 1550 info._sifields._sigfault._addr = env->nip;
9d2803f7 1551 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
61190b14 1552 break;
e1833e1f 1553 case POWERPC_EXCP_DECR: /* Decrementer exception */
a47dddd7 1554 cpu_abort(cs, "Decrementer interrupt while in user mode. "
e1833e1f 1555 "Aborting\n");
61190b14 1556 break;
e1833e1f 1557 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
a47dddd7 1558 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
e1833e1f
JM		 1559 "Aborting\n");
1560 break;
1561 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
a47dddd7 1562 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
e1833e1f
JM		 1563 "Aborting\n");
1564 break;
1565 case POWERPC_EXCP_DTLB: /* Data TLB error */
a47dddd7 1566 cpu_abort(cs, "Data TLB exception while in user mode. "
e1833e1f
JM		 1567 "Aborting\n");
1568 break;
1569 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
a47dddd7 1570 cpu_abort(cs, "Instruction TLB exception while in user mode. "
e1833e1f
JM		 1571 "Aborting\n");
1572 break;
e1833e1f 1573 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
e1833e1f
JM		 1574 info.si_signo = TARGET_SIGILL;
1575 info.si_errno = 0;
1576 info.si_code = TARGET_ILL_COPROC;
bd6fefe7 1577 info._sifields._sigfault._addr = env->nip;
9d2803f7 1578 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
e1833e1f
JM		 1579 break;
1580 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
a47dddd7 1581 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
e1833e1f
JM		 1582 break;
1583 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
a47dddd7 1584 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
e1833e1f
JM		 1585 break;
1586 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
a47dddd7 1587 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1588 break;
1589 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
a47dddd7 1590 cpu_abort(cs, "Doorbell interrupt while in user mode. "
e1833e1f
JM		 1591 "Aborting\n");
1592 break;
1593 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
a47dddd7 1594 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
e1833e1f
JM		 1595 "Aborting\n");
1596 break;
1597 case POWERPC_EXCP_RESET: /* System reset exception */
a47dddd7 1598 cpu_abort(cs, "Reset interrupt while in user mode. "
e1833e1f
JM		 1599 "Aborting\n");
1600 break;
e1833e1f 1601 case POWERPC_EXCP_DSEG: /* Data segment exception */
a47dddd7 1602 cpu_abort(cs, "Data segment exception while in user mode. "
e1833e1f
JM		 1603 "Aborting\n");
1604 break;
1605 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
a47dddd7 1606 cpu_abort(cs, "Instruction segment exception "
e1833e1f
JM		 1607 "while in user mode. Aborting\n");
1608 break;
e85e7c6e 1609 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1610 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
a47dddd7 1611 cpu_abort(cs, "Hypervisor decrementer interrupt "
e1833e1f
JM		 1612 "while in user mode. Aborting\n");
1613 break;
e1833e1f
JM		 1614 case POWERPC_EXCP_TRACE: /* Trace exception */
1615 /* Nothing to do:
1616 * we use this exception to emulate step-by-step execution mode.
1617 */
1618 break;
e85e7c6e 1619 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1620 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
a47dddd7 1621 cpu_abort(cs, "Hypervisor data storage exception "
e1833e1f
JM		 1622 "while in user mode. Aborting\n");
1623 break;
1624 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
a47dddd7 1625 cpu_abort(cs, "Hypervisor instruction storage exception "
e1833e1f
JM		 1626 "while in user mode. Aborting\n");
1627 break;
1628 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
a47dddd7 1629 cpu_abort(cs, "Hypervisor data segment exception "
e1833e1f
JM		 1630 "while in user mode. Aborting\n");
1631 break;
1632 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
a47dddd7 1633 cpu_abort(cs, "Hypervisor instruction segment exception "
e1833e1f
JM		 1634 "while in user mode. Aborting\n");
1635 break;
e1833e1f 1636 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
e1833e1f
JM		 1637 info.si_signo = TARGET_SIGILL;
1638 info.si_errno = 0;
1639 info.si_code = TARGET_ILL_COPROC;
bd6fefe7 1640 info._sifields._sigfault._addr = env->nip;
9d2803f7 1641 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
e1833e1f
JM		 1642 break;
1643 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
a47dddd7 1644 cpu_abort(cs, "Programmable interval timer interrupt "
e1833e1f
JM		 1645 "while in user mode. Aborting\n");
1646 break;
1647 case POWERPC_EXCP_IO: /* IO error exception */
a47dddd7 1648 cpu_abort(cs, "IO error exception while in user mode. "
e1833e1f
JM		 1649 "Aborting\n");
1650 break;
1651 case POWERPC_EXCP_RUNM: /* Run mode exception */
a47dddd7 1652 cpu_abort(cs, "Run mode exception while in user mode. "
e1833e1f
JM		 1653 "Aborting\n");
1654 break;
1655 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
a47dddd7 1656 cpu_abort(cs, "Emulation trap exception not handled\n");
e1833e1f
JM		 1657 break;
1658 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
a47dddd7 1659 cpu_abort(cs, "Instruction fetch TLB exception "
e1833e1f
JM		 1660 "while in user-mode. Aborting");
1661 break;
1662 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
a47dddd7 1663 cpu_abort(cs, "Data load TLB exception while in user-mode. "
e1833e1f
JM		 1664 "Aborting");
1665 break;
1666 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
a47dddd7 1667 cpu_abort(cs, "Data store TLB exception while in user-mode. "
e1833e1f
JM		 1668 "Aborting");
1669 break;
1670 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
a47dddd7 1671 cpu_abort(cs, "Floating-point assist exception not handled\n");
e1833e1f
JM		 1672 break;
1673 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
a47dddd7 1674 cpu_abort(cs, "Instruction address breakpoint exception "
e1833e1f
JM		 1675 "not handled\n");
1676 break;
1677 case POWERPC_EXCP_SMI: /* System management interrupt */
a47dddd7 1678 cpu_abort(cs, "System management interrupt while in user mode. "
e1833e1f
JM		 1679 "Aborting\n");
1680 break;
1681 case POWERPC_EXCP_THERM: /* Thermal interrupt */
a47dddd7 1682 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
e1833e1f
JM		 1683 "Aborting\n");
1684 break;
1685 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
a47dddd7 1686 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1687 break;
1688 case POWERPC_EXCP_VPUA: /* Vector assist exception */
a47dddd7 1689 cpu_abort(cs, "Vector assist exception not handled\n");
e1833e1f
JM		 1690 break;
1691 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
a47dddd7 1692 cpu_abort(cs, "Soft patch exception not handled\n");
e1833e1f
JM		 1693 break;
1694 case POWERPC_EXCP_MAINT: /* Maintenance exception */
a47dddd7 1695 cpu_abort(cs, "Maintenance exception while in user mode. "
e1833e1f
JM		 1696 "Aborting\n");
1697 break;
1698 case POWERPC_EXCP_STOP: /* stop translation */
1699 /* We did invalidate the instruction cache. Go on */
1700 break;
1701 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1702 /* We just stopped because of a branch. Go on */
1703 break;
1704 case POWERPC_EXCP_SYSCALL_USER:
1705 /* system call in user-mode emulation */
1706 /* WARNING:
1707 * PPC ABI uses overflow flag in cr0 to signal an error
1708 * in syscalls.
1709 */
e1833e1f
JM		 1710 env->crf[0] &= ~0x1;
1711 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1712 env->gpr[5], env->gpr[6], env->gpr[7],
5945cfcb 1713 env->gpr[8], 0, 0);
6db9d00e 1714 if (ret == -TARGET_ERESTARTSYS) {
6db9d00e
TB		 1715 break;
1716 }
9e0e2f96 1717 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
bcd4933a
NF		 1718 /* Returning from a successful sigreturn syscall.
1719 Avoid corrupting register state. */
1720 break;
1721 }
95cda4c4 1722 env->nip += 4;
9e0e2f96 1723 if (ret > (target_ulong)(-515)) {
e1833e1f
JM		 1724 env->crf[0] |= 0x1;
1725 ret = -ret;
61190b14 1726 }
e1833e1f 1727 env->gpr[3] = ret;
e1833e1f 1728 break;
56f066bb
NF		 1729 case POWERPC_EXCP_STCX:
1730 if (do_store_exclusive(env)) {
1731 info.si_signo = TARGET_SIGSEGV;
1732 info.si_errno = 0;
1733 info.si_code = TARGET_SEGV_MAPERR;
1734 info._sifields._sigfault._addr = env->nip;
9d2803f7 1735 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
56f066bb
NF		 1736 }
1737 break;
71f75756
AJ		 1738 case EXCP_DEBUG:
1739 {
1740 int sig;
1741
db6b81d4 1742 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
71f75756
AJ		 1743 if (sig) {
1744 info.si_signo = sig;
1745 info.si_errno = 0;
1746 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 1747 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
71f75756
AJ		 1748 }
1749 }
1750 break;
56ba31ff
JM		 1751 case EXCP_INTERRUPT:
1752 /* just indicate that signals should be handled asap */
1753 break;
fdbc2b57
RH		 1754 case EXCP_ATOMIC:
1755 cpu_exec_step_atomic(cs);
1756 break;
e1833e1f 1757 default:
8223f345 1758 cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr);
e1833e1f 1759 break;
67867308
FB		 1760 }
1761 process_pending_signals(env);
1762 }
1763}
1764#endif
1765
048f6b4d
FB		 1766#ifdef TARGET_MIPS
1767
ff4f7382
RH		 1768# ifdef TARGET_ABI_MIPSO32
1769# define MIPS_SYS(name, args) args,
048f6b4d 1770static const uint8_t mips_syscall_args[] = {
29fb0f25 1771 MIPS_SYS(sys_syscall , 8) /* 4000 */
048f6b4d
FB		 1772 MIPS_SYS(sys_exit , 1)
1773 MIPS_SYS(sys_fork , 0)
1774 MIPS_SYS(sys_read , 3)
1775 MIPS_SYS(sys_write , 3)
1776 MIPS_SYS(sys_open , 3) /* 4005 */
1777 MIPS_SYS(sys_close , 1)
1778 MIPS_SYS(sys_waitpid , 3)
1779 MIPS_SYS(sys_creat , 2)
1780 MIPS_SYS(sys_link , 2)
1781 MIPS_SYS(sys_unlink , 1) /* 4010 */
1782 MIPS_SYS(sys_execve , 0)
1783 MIPS_SYS(sys_chdir , 1)
1784 MIPS_SYS(sys_time , 1)
1785 MIPS_SYS(sys_mknod , 3)
1786 MIPS_SYS(sys_chmod , 2) /* 4015 */
1787 MIPS_SYS(sys_lchown , 3)
1788 MIPS_SYS(sys_ni_syscall , 0)
1789 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1790 MIPS_SYS(sys_lseek , 3)
1791 MIPS_SYS(sys_getpid , 0) /* 4020 */
1792 MIPS_SYS(sys_mount , 5)
868e34d7 1793 MIPS_SYS(sys_umount , 1)
048f6b4d
FB		 1794 MIPS_SYS(sys_setuid , 1)
1795 MIPS_SYS(sys_getuid , 0)
1796 MIPS_SYS(sys_stime , 1) /* 4025 */
1797 MIPS_SYS(sys_ptrace , 4)
1798 MIPS_SYS(sys_alarm , 1)
1799 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1800 MIPS_SYS(sys_pause , 0)
1801 MIPS_SYS(sys_utime , 2) /* 4030 */
1802 MIPS_SYS(sys_ni_syscall , 0)
1803 MIPS_SYS(sys_ni_syscall , 0)
1804 MIPS_SYS(sys_access , 2)
1805 MIPS_SYS(sys_nice , 1)
1806 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1807 MIPS_SYS(sys_sync , 0)
1808 MIPS_SYS(sys_kill , 2)
1809 MIPS_SYS(sys_rename , 2)
1810 MIPS_SYS(sys_mkdir , 2)
1811 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1812 MIPS_SYS(sys_dup , 1)
1813 MIPS_SYS(sys_pipe , 0)
1814 MIPS_SYS(sys_times , 1)
1815 MIPS_SYS(sys_ni_syscall , 0)
1816 MIPS_SYS(sys_brk , 1) /* 4045 */
1817 MIPS_SYS(sys_setgid , 1)
1818 MIPS_SYS(sys_getgid , 0)
1819 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1820 MIPS_SYS(sys_geteuid , 0)
1821 MIPS_SYS(sys_getegid , 0) /* 4050 */
1822 MIPS_SYS(sys_acct , 0)
868e34d7 1823 MIPS_SYS(sys_umount2 , 2)
048f6b4d
FB		 1824 MIPS_SYS(sys_ni_syscall , 0)
1825 MIPS_SYS(sys_ioctl , 3)
1826 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1827 MIPS_SYS(sys_ni_syscall , 2)
1828 MIPS_SYS(sys_setpgid , 2)
1829 MIPS_SYS(sys_ni_syscall , 0)
1830 MIPS_SYS(sys_olduname , 1)
1831 MIPS_SYS(sys_umask , 1) /* 4060 */
1832 MIPS_SYS(sys_chroot , 1)
1833 MIPS_SYS(sys_ustat , 2)
1834 MIPS_SYS(sys_dup2 , 2)
1835 MIPS_SYS(sys_getppid , 0)
1836 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1837 MIPS_SYS(sys_setsid , 0)
1838 MIPS_SYS(sys_sigaction , 3)
1839 MIPS_SYS(sys_sgetmask , 0)
1840 MIPS_SYS(sys_ssetmask , 1)
1841 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1842 MIPS_SYS(sys_setregid , 2)
1843 MIPS_SYS(sys_sigsuspend , 0)
1844 MIPS_SYS(sys_sigpending , 1)
1845 MIPS_SYS(sys_sethostname , 2)
1846 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1847 MIPS_SYS(sys_getrlimit , 2)
1848 MIPS_SYS(sys_getrusage , 2)
1849 MIPS_SYS(sys_gettimeofday, 2)
1850 MIPS_SYS(sys_settimeofday, 2)
1851 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1852 MIPS_SYS(sys_setgroups , 2)
1853 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1854 MIPS_SYS(sys_symlink , 2)
1855 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1856 MIPS_SYS(sys_readlink , 3) /* 4085 */
1857 MIPS_SYS(sys_uselib , 1)
1858 MIPS_SYS(sys_swapon , 2)
1859 MIPS_SYS(sys_reboot , 3)
1860 MIPS_SYS(old_readdir , 3)
1861 MIPS_SYS(old_mmap , 6) /* 4090 */
1862 MIPS_SYS(sys_munmap , 2)
1863 MIPS_SYS(sys_truncate , 2)
1864 MIPS_SYS(sys_ftruncate , 2)
1865 MIPS_SYS(sys_fchmod , 2)
1866 MIPS_SYS(sys_fchown , 3) /* 4095 */
1867 MIPS_SYS(sys_getpriority , 2)
1868 MIPS_SYS(sys_setpriority , 3)
1869 MIPS_SYS(sys_ni_syscall , 0)
1870 MIPS_SYS(sys_statfs , 2)
1871 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1872 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1873 MIPS_SYS(sys_socketcall , 2)
1874 MIPS_SYS(sys_syslog , 3)
1875 MIPS_SYS(sys_setitimer , 3)
1876 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1877 MIPS_SYS(sys_newstat , 2)
1878 MIPS_SYS(sys_newlstat , 2)
1879 MIPS_SYS(sys_newfstat , 2)
1880 MIPS_SYS(sys_uname , 1)
1881 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1882 MIPS_SYS(sys_vhangup , 0)
1883 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1884 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1885 MIPS_SYS(sys_wait4 , 4)
1886 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1887 MIPS_SYS(sys_sysinfo , 1)
1888 MIPS_SYS(sys_ipc , 6)
1889 MIPS_SYS(sys_fsync , 1)
1890 MIPS_SYS(sys_sigreturn , 0)
18113962 1891 MIPS_SYS(sys_clone , 6) /* 4120 */
048f6b4d
FB		 1892 MIPS_SYS(sys_setdomainname, 2)
1893 MIPS_SYS(sys_newuname , 1)
1894 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1895 MIPS_SYS(sys_adjtimex , 1)
1896 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1897 MIPS_SYS(sys_sigprocmask , 3)
1898 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1899 MIPS_SYS(sys_init_module , 5)
1900 MIPS_SYS(sys_delete_module, 1)
1901 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1902 MIPS_SYS(sys_quotactl , 0)
1903 MIPS_SYS(sys_getpgid , 1)
1904 MIPS_SYS(sys_fchdir , 1)
1905 MIPS_SYS(sys_bdflush , 2)
1906 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1907 MIPS_SYS(sys_personality , 1)
1908 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1909 MIPS_SYS(sys_setfsuid , 1)
1910 MIPS_SYS(sys_setfsgid , 1)
1911 MIPS_SYS(sys_llseek , 5) /* 4140 */
1912 MIPS_SYS(sys_getdents , 3)
1913 MIPS_SYS(sys_select , 5)
1914 MIPS_SYS(sys_flock , 2)
1915 MIPS_SYS(sys_msync , 3)
1916 MIPS_SYS(sys_readv , 3) /* 4145 */
1917 MIPS_SYS(sys_writev , 3)
1918 MIPS_SYS(sys_cacheflush , 3)
1919 MIPS_SYS(sys_cachectl , 3)
1920 MIPS_SYS(sys_sysmips , 4)
1921 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1922 MIPS_SYS(sys_getsid , 1)
1923 MIPS_SYS(sys_fdatasync , 0)
1924 MIPS_SYS(sys_sysctl , 1)
1925 MIPS_SYS(sys_mlock , 2)
1926 MIPS_SYS(sys_munlock , 2) /* 4155 */
1927 MIPS_SYS(sys_mlockall , 1)
1928 MIPS_SYS(sys_munlockall , 0)
1929 MIPS_SYS(sys_sched_setparam, 2)
1930 MIPS_SYS(sys_sched_getparam, 2)
1931 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1932 MIPS_SYS(sys_sched_getscheduler, 1)
1933 MIPS_SYS(sys_sched_yield , 0)
1934 MIPS_SYS(sys_sched_get_priority_max, 1)
1935 MIPS_SYS(sys_sched_get_priority_min, 1)
1936 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1937 MIPS_SYS(sys_nanosleep, 2)
b0932e06 1938 MIPS_SYS(sys_mremap , 5)
048f6b4d
FB		 1939 MIPS_SYS(sys_accept , 3)
1940 MIPS_SYS(sys_bind , 3)
1941 MIPS_SYS(sys_connect , 3) /* 4170 */
1942 MIPS_SYS(sys_getpeername , 3)
1943 MIPS_SYS(sys_getsockname , 3)
1944 MIPS_SYS(sys_getsockopt , 5)
1945 MIPS_SYS(sys_listen , 2)
1946 MIPS_SYS(sys_recv , 4) /* 4175 */
1947 MIPS_SYS(sys_recvfrom , 6)
1948 MIPS_SYS(sys_recvmsg , 3)
1949 MIPS_SYS(sys_send , 4)
1950 MIPS_SYS(sys_sendmsg , 3)
1951 MIPS_SYS(sys_sendto , 6) /* 4180 */
1952 MIPS_SYS(sys_setsockopt , 5)
1953 MIPS_SYS(sys_shutdown , 2)
1954 MIPS_SYS(sys_socket , 3)
1955 MIPS_SYS(sys_socketpair , 4)
1956 MIPS_SYS(sys_setresuid , 3) /* 4185 */
1957 MIPS_SYS(sys_getresuid , 3)
1958 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
1959 MIPS_SYS(sys_poll , 3)
1960 MIPS_SYS(sys_nfsservctl , 3)
1961 MIPS_SYS(sys_setresgid , 3) /* 4190 */
1962 MIPS_SYS(sys_getresgid , 3)
1963 MIPS_SYS(sys_prctl , 5)
1964 MIPS_SYS(sys_rt_sigreturn, 0)
1965 MIPS_SYS(sys_rt_sigaction, 4)
1966 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
1967 MIPS_SYS(sys_rt_sigpending, 2)
1968 MIPS_SYS(sys_rt_sigtimedwait, 4)
1969 MIPS_SYS(sys_rt_sigqueueinfo, 3)
1970 MIPS_SYS(sys_rt_sigsuspend, 0)
1971 MIPS_SYS(sys_pread64 , 6) /* 4200 */
1972 MIPS_SYS(sys_pwrite64 , 6)
1973 MIPS_SYS(sys_chown , 3)
1974 MIPS_SYS(sys_getcwd , 2)
1975 MIPS_SYS(sys_capget , 2)
1976 MIPS_SYS(sys_capset , 2) /* 4205 */
053ebb27 1977 MIPS_SYS(sys_sigaltstack , 2)
048f6b4d
FB		 1978 MIPS_SYS(sys_sendfile , 4)
1979 MIPS_SYS(sys_ni_syscall , 0)
1980 MIPS_SYS(sys_ni_syscall , 0)
1981 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
1982 MIPS_SYS(sys_truncate64 , 4)
1983 MIPS_SYS(sys_ftruncate64 , 4)
1984 MIPS_SYS(sys_stat64 , 2)
1985 MIPS_SYS(sys_lstat64 , 2)
1986 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
1987 MIPS_SYS(sys_pivot_root , 2)
1988 MIPS_SYS(sys_mincore , 3)
1989 MIPS_SYS(sys_madvise , 3)
1990 MIPS_SYS(sys_getdents64 , 3)
1991 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
1992 MIPS_SYS(sys_ni_syscall , 0)
1993 MIPS_SYS(sys_gettid , 0)
1994 MIPS_SYS(sys_readahead , 5)
1995 MIPS_SYS(sys_setxattr , 5)
1996 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
1997 MIPS_SYS(sys_fsetxattr , 5)
1998 MIPS_SYS(sys_getxattr , 4)
1999 MIPS_SYS(sys_lgetxattr , 4)
2000 MIPS_SYS(sys_fgetxattr , 4)
2001 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2002 MIPS_SYS(sys_llistxattr , 3)
2003 MIPS_SYS(sys_flistxattr , 3)
2004 MIPS_SYS(sys_removexattr , 2)
2005 MIPS_SYS(sys_lremovexattr, 2)
2006 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2007 MIPS_SYS(sys_tkill , 2)
2008 MIPS_SYS(sys_sendfile64 , 5)
43be1343 2009 MIPS_SYS(sys_futex , 6)
048f6b4d
FB		 2010 MIPS_SYS(sys_sched_setaffinity, 3)
2011 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2012 MIPS_SYS(sys_io_setup , 2)
2013 MIPS_SYS(sys_io_destroy , 1)
2014 MIPS_SYS(sys_io_getevents, 5)
2015 MIPS_SYS(sys_io_submit , 3)
2016 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2017 MIPS_SYS(sys_exit_group , 1)
2018 MIPS_SYS(sys_lookup_dcookie, 3)
2019 MIPS_SYS(sys_epoll_create, 1)
2020 MIPS_SYS(sys_epoll_ctl , 4)
2021 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2022 MIPS_SYS(sys_remap_file_pages, 5)
2023 MIPS_SYS(sys_set_tid_address, 1)
2024 MIPS_SYS(sys_restart_syscall, 0)
2025 MIPS_SYS(sys_fadvise64_64, 7)
2026 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2027 MIPS_SYS(sys_fstatfs64 , 2)
2028 MIPS_SYS(sys_timer_create, 3)
2029 MIPS_SYS(sys_timer_settime, 4)
2030 MIPS_SYS(sys_timer_gettime, 2)
2031 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2032 MIPS_SYS(sys_timer_delete, 1)
2033 MIPS_SYS(sys_clock_settime, 2)
2034 MIPS_SYS(sys_clock_gettime, 2)
2035 MIPS_SYS(sys_clock_getres, 2)
2036 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2037 MIPS_SYS(sys_tgkill , 3)
2038 MIPS_SYS(sys_utimes , 2)
2039 MIPS_SYS(sys_mbind , 4)
2040 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2041 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2042 MIPS_SYS(sys_mq_open , 4)
2043 MIPS_SYS(sys_mq_unlink , 1)
2044 MIPS_SYS(sys_mq_timedsend, 5)
2045 MIPS_SYS(sys_mq_timedreceive, 5)
2046 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2047 MIPS_SYS(sys_mq_getsetattr, 3)
2048 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2049 MIPS_SYS(sys_waitid , 4)
2050 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2051 MIPS_SYS(sys_add_key , 5)
388bb21a 2052 MIPS_SYS(sys_request_key, 4)
048f6b4d 2053 MIPS_SYS(sys_keyctl , 5)
6f5b89a0 2054 MIPS_SYS(sys_set_thread_area, 1)
388bb21a
TS		 2055 MIPS_SYS(sys_inotify_init, 0)
2056 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2057 MIPS_SYS(sys_inotify_rm_watch, 2)
2058 MIPS_SYS(sys_migrate_pages, 4)
2059 MIPS_SYS(sys_openat, 4)
2060 MIPS_SYS(sys_mkdirat, 3)
2061 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2062 MIPS_SYS(sys_fchownat, 5)
2063 MIPS_SYS(sys_futimesat, 3)
2064 MIPS_SYS(sys_fstatat64, 4)
2065 MIPS_SYS(sys_unlinkat, 3)
2066 MIPS_SYS(sys_renameat, 4) /* 4295 */
2067 MIPS_SYS(sys_linkat, 5)
2068 MIPS_SYS(sys_symlinkat, 3)
2069 MIPS_SYS(sys_readlinkat, 4)
2070 MIPS_SYS(sys_fchmodat, 3)
2071 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2072 MIPS_SYS(sys_pselect6, 6)
2073 MIPS_SYS(sys_ppoll, 5)
2074 MIPS_SYS(sys_unshare, 1)
b0932e06 2075 MIPS_SYS(sys_splice, 6)
388bb21a
TS		 2076 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2077 MIPS_SYS(sys_tee, 4)
2078 MIPS_SYS(sys_vmsplice, 4)
2079 MIPS_SYS(sys_move_pages, 6)
2080 MIPS_SYS(sys_set_robust_list, 2)
2081 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2082 MIPS_SYS(sys_kexec_load, 4)
2083 MIPS_SYS(sys_getcpu, 3)
2084 MIPS_SYS(sys_epoll_pwait, 6)
2085 MIPS_SYS(sys_ioprio_set, 3)
2086 MIPS_SYS(sys_ioprio_get, 2)
d979e8eb
PM		 2087 MIPS_SYS(sys_utimensat, 4)
2088 MIPS_SYS(sys_signalfd, 3)
2089 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2090 MIPS_SYS(sys_eventfd, 1)
2091 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2092 MIPS_SYS(sys_timerfd_create, 2)
2093 MIPS_SYS(sys_timerfd_gettime, 2)
2094 MIPS_SYS(sys_timerfd_settime, 4)
2095 MIPS_SYS(sys_signalfd4, 4)
2096 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2097 MIPS_SYS(sys_epoll_create1, 1)
2098 MIPS_SYS(sys_dup3, 3)
2099 MIPS_SYS(sys_pipe2, 2)
2100 MIPS_SYS(sys_inotify_init1, 1)
2e6eeb67
AM		 2101 MIPS_SYS(sys_preadv, 5) /* 4330 */
2102 MIPS_SYS(sys_pwritev, 5)
d979e8eb
PM		 2103 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2104 MIPS_SYS(sys_perf_event_open, 5)
2105 MIPS_SYS(sys_accept4, 4)
2106 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2107 MIPS_SYS(sys_fanotify_init, 2)
2108 MIPS_SYS(sys_fanotify_mark, 6)
2109 MIPS_SYS(sys_prlimit64, 4)
2110 MIPS_SYS(sys_name_to_handle_at, 5)
2111 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2112 MIPS_SYS(sys_clock_adjtime, 2)
2113 MIPS_SYS(sys_syncfs, 1)
2e6eeb67
AM		 2114 MIPS_SYS(sys_sendmmsg, 4)
2115 MIPS_SYS(sys_setns, 2)
2116 MIPS_SYS(sys_process_vm_readv, 6) /* 345 */
2117 MIPS_SYS(sys_process_vm_writev, 6)
2118 MIPS_SYS(sys_kcmp, 5)
2119 MIPS_SYS(sys_finit_module, 3)
2120 MIPS_SYS(sys_sched_setattr, 2)
2121 MIPS_SYS(sys_sched_getattr, 3) /* 350 */
2122 MIPS_SYS(sys_renameat2, 5)
2123 MIPS_SYS(sys_seccomp, 3)
2124 MIPS_SYS(sys_getrandom, 3)
2125 MIPS_SYS(sys_memfd_create, 2)
2126 MIPS_SYS(sys_bpf, 3) /* 355 */
2127 MIPS_SYS(sys_execveat, 5)
2128 MIPS_SYS(sys_userfaultfd, 1)
2129 MIPS_SYS(sys_membarrier, 2)
2130 MIPS_SYS(sys_mlock2, 3)
2131 MIPS_SYS(sys_copy_file_range, 6) /* 360 */
2132 MIPS_SYS(sys_preadv2, 6)
2133 MIPS_SYS(sys_pwritev2, 6)
048f6b4d 2134};
ff4f7382
RH		 2135# undef MIPS_SYS
2136# endif /* O32 */
048f6b4d 2137
590bc601
PB		 2138static int do_store_exclusive(CPUMIPSState *env)
2139{
2140 target_ulong addr;
2141 target_ulong page_addr;
2142 target_ulong val;
2143 int flags;
2144 int segv = 0;
2145 int reg;
2146 int d;
2147
5499b6ff 2148 addr = env->lladdr;
590bc601
PB		 2149 page_addr = addr & TARGET_PAGE_MASK;
2150 start_exclusive();
2151 mmap_lock();
2152 flags = page_get_flags(page_addr);
2153 if ((flags & PAGE_READ) == 0) {
2154 segv = 1;
2155 } else {
2156 reg = env->llreg & 0x1f;
2157 d = (env->llreg & 0x20) != 0;
2158 if (d) {
2159 segv = get_user_s64(val, addr);
2160 } else {
2161 segv = get_user_s32(val, addr);
2162 }
2163 if (!segv) {
2164 if (val != env->llval) {
2165 env->active_tc.gpr[reg] = 0;
2166 } else {
2167 if (d) {
2168 segv = put_user_u64(env->llnewval, addr);
2169 } else {
2170 segv = put_user_u32(env->llnewval, addr);
2171 }
2172 if (!segv) {
2173 env->active_tc.gpr[reg] = 1;
2174 }
2175 }
2176 }
2177 }
5499b6ff 2178 env->lladdr = -1;
590bc601
PB		 2179 if (!segv) {
2180 env->active_tc.PC += 4;
2181 }
2182 mmap_unlock();
2183 end_exclusive();
2184 return segv;
2185}
2186
54b2f42c
MI		 2187/* Break codes */
2188enum {
2189 BRK_OVERFLOW = 6,
2190 BRK_DIVZERO = 7
2191};
2192
2193static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2194 unsigned int code)
2195{
2196 int ret = -1;
2197
2198 switch (code) {
2199 case BRK_OVERFLOW:
2200 case BRK_DIVZERO:
2201 info->si_signo = TARGET_SIGFPE;
2202 info->si_errno = 0;
2203 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
9d2803f7 2204 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info);
54b2f42c
MI		 2205 ret = 0;
2206 break;
2207 default:
b51910ba
PJ		 2208 info->si_signo = TARGET_SIGTRAP;
2209 info->si_errno = 0;
9d2803f7 2210 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info);
b51910ba 2211 ret = 0;
54b2f42c
MI		 2212 break;
2213 }
2214
2215 return ret;
2216}
2217
048f6b4d
FB		 2218void cpu_loop(CPUMIPSState *env)
2219{
0315c31c 2220 CPUState *cs = CPU(mips_env_get_cpu(env));
c227f099 2221 target_siginfo_t info;
ff4f7382
RH		 2222 int trapnr;
2223 abi_long ret;
2224# ifdef TARGET_ABI_MIPSO32
048f6b4d 2225 unsigned int syscall_num;
ff4f7382 2226# endif
048f6b4d
FB		 2227
2228 for(;;) {
0315c31c 2229 cpu_exec_start(cs);
8642c1b8 2230 trapnr = cpu_exec(cs);
0315c31c 2231 cpu_exec_end(cs);
d148d90e
SF		 2232 process_queued_cpu_work(cs);
2233
048f6b4d
FB		 2234 switch(trapnr) {
2235 case EXCP_SYSCALL:
b5dc7732 2236 env->active_tc.PC += 4;
ff4f7382
RH		 2237# ifdef TARGET_ABI_MIPSO32
2238 syscall_num = env->active_tc.gpr[2] - 4000;
388bb21a 2239 if (syscall_num >= sizeof(mips_syscall_args)) {
7c2f6157 2240 ret = -TARGET_ENOSYS;
388bb21a
TS		 2241 } else {
2242 int nb_args;
992f48a0
BS		 2243 abi_ulong sp_reg;
2244 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
388bb21a
TS		 2245
2246 nb_args = mips_syscall_args[syscall_num];
b5dc7732 2247 sp_reg = env->active_tc.gpr[29];
388bb21a
TS		 2248 switch (nb_args) {
2249 /* these arguments are taken from the stack */
94c19610
ACH		 2250 case 8:
2251 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2252 goto done_syscall;
2253 }
2254 case 7:
2255 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2256 goto done_syscall;
2257 }
2258 case 6:
2259 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2260 goto done_syscall;
2261 }
2262 case 5:
2263 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2264 goto done_syscall;
2265 }
388bb21a
TS		 2266 default:
2267 break;
048f6b4d 2268 }
b5dc7732
TS		 2269 ret = do_syscall(env, env->active_tc.gpr[2],
2270 env->active_tc.gpr[4],
2271 env->active_tc.gpr[5],
2272 env->active_tc.gpr[6],
2273 env->active_tc.gpr[7],
5945cfcb 2274 arg5, arg6, arg7, arg8);
388bb21a 2275 }
94c19610 2276done_syscall:
ff4f7382
RH		 2277# else
2278 ret = do_syscall(env, env->active_tc.gpr[2],
2279 env->active_tc.gpr[4], env->active_tc.gpr[5],
2280 env->active_tc.gpr[6], env->active_tc.gpr[7],
2281 env->active_tc.gpr[8], env->active_tc.gpr[9],
2282 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2283# endif /* O32 */
2eb3ae27
TB		 2284 if (ret == -TARGET_ERESTARTSYS) {
2285 env->active_tc.PC -= 4;
2286 break;
2287 }
0b1bcb00
PB		 2288 if (ret == -TARGET_QEMU_ESIGRETURN) {
2289 /* Returning from a successful sigreturn syscall.
2290 Avoid clobbering register state. */
2291 break;
2292 }
ff4f7382 2293 if ((abi_ulong)ret >= (abi_ulong)-1133) {
b5dc7732 2294 env->active_tc.gpr[7] = 1; /* error flag */
388bb21a
TS		 2295 ret = -ret;
2296 } else {
b5dc7732 2297 env->active_tc.gpr[7] = 0; /* error flag */
048f6b4d 2298 }
b5dc7732 2299 env->active_tc.gpr[2] = ret;
048f6b4d 2300 break;
ca7c2b1b
TS		 2301 case EXCP_TLBL:
2302 case EXCP_TLBS:
e6e5bd2d
WT		 2303 case EXCP_AdEL:
2304 case EXCP_AdES:
e4474235
PB		 2305 info.si_signo = TARGET_SIGSEGV;
2306 info.si_errno = 0;
2307 /* XXX: check env->error_code */
2308 info.si_code = TARGET_SEGV_MAPERR;
2309 info._sifields._sigfault._addr = env->CP0_BadVAddr;
9d2803f7 2310 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
e4474235 2311 break;
6900e84b 2312 case EXCP_CpU:
048f6b4d 2313 case EXCP_RI:
bc1ad2de
FB		 2314 info.si_signo = TARGET_SIGILL;
2315 info.si_errno = 0;
2316 info.si_code = 0;
9d2803f7 2317 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
048f6b4d 2318 break;
106ec879
FB		 2319 case EXCP_INTERRUPT:
2320 /* just indicate that signals should be handled asap */
2321 break;
d08b2a28
PB		 2322 case EXCP_DEBUG:
2323 {
2324 int sig;
2325
db6b81d4 2326 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d08b2a28
PB		 2327 if (sig)
2328 {
2329 info.si_signo = sig;
2330 info.si_errno = 0;
2331 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 2332 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
d08b2a28
PB		 2333 }
2334 }
2335 break;
590bc601
PB		 2336 case EXCP_SC:
2337 if (do_store_exclusive(env)) {
2338 info.si_signo = TARGET_SIGSEGV;
2339 info.si_errno = 0;
2340 info.si_code = TARGET_SEGV_MAPERR;
2341 info._sifields._sigfault._addr = env->active_tc.PC;
9d2803f7 2342 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
590bc601
PB		 2343 }
2344 break;
853c3240
JL		 2345 case EXCP_DSPDIS:
2346 info.si_signo = TARGET_SIGILL;
2347 info.si_errno = 0;
2348 info.si_code = TARGET_ILL_ILLOPC;
9d2803f7 2349 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
853c3240 2350 break;
54b2f42c
MI		 2351 /* The code below was inspired by the MIPS Linux kernel trap
2352 * handling code in arch/mips/kernel/traps.c.
2353 */
2354 case EXCP_BREAK:
2355 {
2356 abi_ulong trap_instr;
2357 unsigned int code;
2358
a0333817
KCY		 2359 if (env->hflags & MIPS_HFLAG_M16) {
2360 if (env->insn_flags & ASE_MICROMIPS) {
2361 /* microMIPS mode */
1308c464
KCY		 2362 ret = get_user_u16(trap_instr, env->active_tc.PC);
2363 if (ret != 0) {
2364 goto error;
2365 }
a0333817 2366
1308c464
KCY		 2367 if ((trap_instr >> 10) == 0x11) {
2368 /* 16-bit instruction */
2369 code = trap_instr & 0xf;
2370 } else {
2371 /* 32-bit instruction */
2372 abi_ulong instr_lo;
2373
2374 ret = get_user_u16(instr_lo,
2375 env->active_tc.PC + 2);
2376 if (ret != 0) {
2377 goto error;
2378 }
2379 trap_instr = (trap_instr << 16) | instr_lo;
2380 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2381 /* Unfortunately, microMIPS also suffers from
2382 the old assembler bug... */
2383 if (code >= (1 << 10)) {
2384 code >>= 10;
2385 }
2386 }
a0333817
KCY		 2387 } else {
2388 /* MIPS16e mode */
2389 ret = get_user_u16(trap_instr, env->active_tc.PC);
2390 if (ret != 0) {
2391 goto error;
2392 }
2393 code = (trap_instr >> 6) & 0x3f;
a0333817
KCY		 2394 }
2395 } else {
f01a361b 2396 ret = get_user_u32(trap_instr, env->active_tc.PC);
1308c464
KCY		 2397 if (ret != 0) {
2398 goto error;
2399 }
54b2f42c 2400
1308c464
KCY		 2401 /* As described in the original Linux kernel code, the
2402 * below checks on 'code' are to work around an old
2403 * assembly bug.
2404 */
2405 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2406 if (code >= (1 << 10)) {
2407 code >>= 10;
2408 }
54b2f42c
MI		 2409 }
2410
2411 if (do_break(env, &info, code) != 0) {
2412 goto error;
2413 }
2414 }
2415 break;
2416 case EXCP_TRAP:
2417 {
2418 abi_ulong trap_instr;
2419 unsigned int code = 0;
2420
a0333817
KCY		 2421 if (env->hflags & MIPS_HFLAG_M16) {
2422 /* microMIPS mode */
2423 abi_ulong instr[2];
2424
2425 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2426 get_user_u16(instr[1], env->active_tc.PC + 2);
2427
2428 trap_instr = (instr[0] << 16) | instr[1];
2429 } else {
f01a361b 2430 ret = get_user_u32(trap_instr, env->active_tc.PC);
a0333817
KCY		 2431 }
2432
54b2f42c
MI		 2433 if (ret != 0) {
2434 goto error;
2435 }
2436
2437 /* The immediate versions don't provide a code. */
2438 if (!(trap_instr & 0xFC000000)) {
a0333817
KCY		 2439 if (env->hflags & MIPS_HFLAG_M16) {
2440 /* microMIPS mode */
2441 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2442 } else {
2443 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2444 }
54b2f42c
MI		 2445 }
2446
2447 if (do_break(env, &info, code) != 0) {
2448 goto error;
2449 }
2450 }
2451 break;
fdbc2b57
RH		 2452 case EXCP_ATOMIC:
2453 cpu_exec_step_atomic(cs);
2454 break;
048f6b4d 2455 default:
54b2f42c 2456error:
120a9848 2457 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
048f6b4d
FB		 2458 abort();
2459 }
2460 process_pending_signals(env);
2461 }
2462}
2463#endif
2464
d962783e
JL		 2465#ifdef TARGET_OPENRISC
2466
2467void cpu_loop(CPUOpenRISCState *env)
2468{
878096ee 2469 CPUState *cs = CPU(openrisc_env_get_cpu(env));
d962783e 2470 int trapnr, gdbsig;
7fe7231a 2471 abi_long ret;
d962783e
JL		 2472
2473 for (;;) {
b040bc9c 2474 cpu_exec_start(cs);
8642c1b8 2475 trapnr = cpu_exec(cs);
b040bc9c 2476 cpu_exec_end(cs);
d148d90e 2477 process_queued_cpu_work(cs);
d962783e
JL		 2478 gdbsig = 0;
2479
2480 switch (trapnr) {
2481 case EXCP_RESET:
120a9848 2482 qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc);
4d1275c2 2483 exit(EXIT_FAILURE);
d962783e
JL		 2484 break;
2485 case EXCP_BUSERR:
120a9848 2486 qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc);
a86b3c64 2487 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2488 break;
2489 case EXCP_DPF:
2490 case EXCP_IPF:
878096ee 2491 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2492 gdbsig = TARGET_SIGSEGV;
2493 break;
2494 case EXCP_TICK:
120a9848 2495 qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc);
d962783e
JL		 2496 break;
2497 case EXCP_ALIGN:
120a9848 2498 qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc);
a86b3c64 2499 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2500 break;
2501 case EXCP_ILLEGAL:
120a9848 2502 qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc);
a86b3c64 2503 gdbsig = TARGET_SIGILL;
d962783e
JL		 2504 break;
2505 case EXCP_INT:
120a9848 2506 qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc);
d962783e
JL		 2507 break;
2508 case EXCP_DTLBMISS:
2509 case EXCP_ITLBMISS:
120a9848 2510 qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n");
d962783e
JL		 2511 break;
2512 case EXCP_RANGE:
120a9848 2513 qemu_log_mask(CPU_LOG_INT, "\nRange\n");
a86b3c64 2514 gdbsig = TARGET_SIGSEGV;
d962783e
JL		 2515 break;
2516 case EXCP_SYSCALL:
2517 env->pc += 4; /* 0xc00; */
7fe7231a
TB		 2518 ret = do_syscall(env,
2519 env->gpr[11], /* return value */
2520 env->gpr[3], /* r3 - r7 are params */
2521 env->gpr[4],
2522 env->gpr[5],
2523 env->gpr[6],
2524 env->gpr[7],
2525 env->gpr[8], 0, 0);
2526 if (ret == -TARGET_ERESTARTSYS) {
2527 env->pc -= 4;
2528 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2529 env->gpr[11] = ret;
2530 }
d962783e
JL		 2531 break;
2532 case EXCP_FPE:
120a9848 2533 qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n");
d962783e
JL		 2534 break;
2535 case EXCP_TRAP:
120a9848 2536 qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
a86b3c64 2537 gdbsig = TARGET_SIGTRAP;
d962783e
JL		 2538 break;
2539 case EXCP_NR:
120a9848 2540 qemu_log_mask(CPU_LOG_INT, "\nNR\n");
d962783e 2541 break;
fdbc2b57
RH		 2542 case EXCP_ATOMIC:
2543 cpu_exec_step_atomic(cs);
2544 break;
d962783e 2545 default:
120a9848 2546 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
d962783e 2547 trapnr);
d962783e
JL		 2548 gdbsig = TARGET_SIGILL;
2549 break;
2550 }
2551 if (gdbsig) {
db6b81d4 2552 gdb_handlesig(cs, gdbsig);
d962783e 2553 if (gdbsig != TARGET_SIGTRAP) {
4d1275c2 2554 exit(EXIT_FAILURE);
d962783e
JL		 2555 }
2556 }
2557
2558 process_pending_signals(env);
2559 }
2560}
2561
2562#endif /* TARGET_OPENRISC */
2563
fdf9b3e8 2564#ifdef TARGET_SH4
05390248 2565void cpu_loop(CPUSH4State *env)
fdf9b3e8 2566{
878096ee 2567 CPUState *cs = CPU(sh_env_get_cpu(env));
fdf9b3e8 2568 int trapnr, ret;
c227f099 2569 target_siginfo_t info;
3b46e624 2570
fdf9b3e8 2571 while (1) {
b040bc9c 2572 cpu_exec_start(cs);
8642c1b8 2573 trapnr = cpu_exec(cs);
b040bc9c 2574 cpu_exec_end(cs);
d148d90e 2575 process_queued_cpu_work(cs);
3b46e624 2576
fdf9b3e8
FB		 2577 switch (trapnr) {
2578 case 0x160:
0b6d3ae0 2579 env->pc += 2;
5fafdf24
TS		 2580 ret = do_syscall(env,
2581 env->gregs[3],
2582 env->gregs[4],
2583 env->gregs[5],
2584 env->gregs[6],
2585 env->gregs[7],
2586 env->gregs[0],
5945cfcb
PM		 2587 env->gregs[1],
2588 0, 0);
ba412496
TB		 2589 if (ret == -TARGET_ERESTARTSYS) {
2590 env->pc -= 2;
2591 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2592 env->gregs[0] = ret;
2593 }
fdf9b3e8 2594 break;
c3b5bc8a
TS		 2595 case EXCP_INTERRUPT:
2596 /* just indicate that signals should be handled asap */
2597 break;
355fb23d
PB		 2598 case EXCP_DEBUG:
2599 {
2600 int sig;
2601
db6b81d4 2602 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
355fb23d
PB		 2603 if (sig)
2604 {
2605 info.si_signo = sig;
2606 info.si_errno = 0;
2607 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 2608 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
355fb23d
PB		 2609 }
2610 }
2611 break;
c3b5bc8a
TS		 2612 case 0xa0:
2613 case 0xc0:
a86b3c64 2614 info.si_signo = TARGET_SIGSEGV;
c3b5bc8a
TS		 2615 info.si_errno = 0;
2616 info.si_code = TARGET_SEGV_MAPERR;
2617 info._sifields._sigfault._addr = env->tea;
9d2803f7 2618 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
c3b5bc8a
TS		 2619 break;
2620
fdbc2b57
RH		 2621 case EXCP_ATOMIC:
2622 cpu_exec_step_atomic(cs);
2623 break;
fdf9b3e8
FB		 2624 default:
2625 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2626 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 2627 exit(EXIT_FAILURE);
fdf9b3e8
FB		 2628 }
2629 process_pending_signals (env);
2630 }
2631}
2632#endif
2633
48733d19 2634#ifdef TARGET_CRIS
05390248 2635void cpu_loop(CPUCRISState *env)
48733d19 2636{
878096ee 2637 CPUState *cs = CPU(cris_env_get_cpu(env));
48733d19 2638 int trapnr, ret;
c227f099 2639 target_siginfo_t info;
48733d19
TS		 2640
2641 while (1) {
b040bc9c 2642 cpu_exec_start(cs);
8642c1b8 2643 trapnr = cpu_exec(cs);
b040bc9c 2644 cpu_exec_end(cs);
d148d90e
SF		 2645 process_queued_cpu_work(cs);
2646
48733d19
TS		 2647 switch (trapnr) {
2648 case 0xaa:
2649 {
a86b3c64 2650 info.si_signo = TARGET_SIGSEGV;
48733d19
TS		 2651 info.si_errno = 0;
2652 /* XXX: check env->error_code */
2653 info.si_code = TARGET_SEGV_MAPERR;
e00c1e71 2654 info._sifields._sigfault._addr = env->pregs[PR_EDA];
9d2803f7 2655 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
48733d19
TS		 2656 }
2657 break;
b6d3abda
EI		 2658 case EXCP_INTERRUPT:
2659 /* just indicate that signals should be handled asap */
2660 break;
48733d19
TS		 2661 case EXCP_BREAK:
2662 ret = do_syscall(env,
2663 env->regs[9],
2664 env->regs[10],
2665 env->regs[11],
2666 env->regs[12],
2667 env->regs[13],
2668 env->pregs[7],
5945cfcb
PM		 2669 env->pregs[11],
2670 0, 0);
62050865
TB		 2671 if (ret == -TARGET_ERESTARTSYS) {
2672 env->pc -= 2;
2673 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2674 env->regs[10] = ret;
2675 }
48733d19
TS		 2676 break;
2677 case EXCP_DEBUG:
2678 {
2679 int sig;
2680
db6b81d4 2681 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
48733d19
TS		 2682 if (sig)
2683 {
2684 info.si_signo = sig;
2685 info.si_errno = 0;
2686 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 2687 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
48733d19
TS		 2688 }
2689 }
2690 break;
fdbc2b57
RH		 2691 case EXCP_ATOMIC:
2692 cpu_exec_step_atomic(cs);
2693 break;
48733d19
TS		 2694 default:
2695 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2696 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 2697 exit(EXIT_FAILURE);
48733d19
TS		 2698 }
2699 process_pending_signals (env);
2700 }
2701}
2702#endif
2703
b779e29e 2704#ifdef TARGET_MICROBLAZE
05390248 2705void cpu_loop(CPUMBState *env)
b779e29e 2706{
878096ee 2707 CPUState *cs = CPU(mb_env_get_cpu(env));
b779e29e 2708 int trapnr, ret;
c227f099 2709 target_siginfo_t info;
b779e29e
EI		 2710
2711 while (1) {
b040bc9c 2712 cpu_exec_start(cs);
8642c1b8 2713 trapnr = cpu_exec(cs);
b040bc9c 2714 cpu_exec_end(cs);
d148d90e
SF		 2715 process_queued_cpu_work(cs);
2716
b779e29e
EI		 2717 switch (trapnr) {
2718 case 0xaa:
2719 {
a86b3c64 2720 info.si_signo = TARGET_SIGSEGV;
b779e29e
EI		 2721 info.si_errno = 0;
2722 /* XXX: check env->error_code */
2723 info.si_code = TARGET_SEGV_MAPERR;
2724 info._sifields._sigfault._addr = 0;
9d2803f7 2725 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
b779e29e
EI		 2726 }
2727 break;
2728 case EXCP_INTERRUPT:
2729 /* just indicate that signals should be handled asap */
2730 break;
2731 case EXCP_BREAK:
2732 /* Return address is 4 bytes after the call. */
2733 env->regs[14] += 4;
d7dce494 2734 env->sregs[SR_PC] = env->regs[14];
b779e29e
EI		 2735 ret = do_syscall(env,
2736 env->regs[12],
2737 env->regs[5],
2738 env->regs[6],
2739 env->regs[7],
2740 env->regs[8],
2741 env->regs[9],
5945cfcb
PM		 2742 env->regs[10],
2743 0, 0);
4134ecfe
TB		 2744 if (ret == -TARGET_ERESTARTSYS) {
2745 /* Wind back to before the syscall. */
2746 env->sregs[SR_PC] -= 4;
2747 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2748 env->regs[3] = ret;
2749 }
d7749ab7
PM		 2750 /* All syscall exits result in guest r14 being equal to the
2751 * PC we return to, because the kernel syscall exit "rtbd" does
2752 * this. (This is true even for sigreturn(); note that r14 is
2753 * not a userspace-usable register, as the kernel may clobber it
2754 * at any point.)
2755 */
2756 env->regs[14] = env->sregs[SR_PC];
b779e29e 2757 break;
b76da7e3
EI		 2758 case EXCP_HW_EXCP:
2759 env->regs[17] = env->sregs[SR_PC] + 4;
2760 if (env->iflags & D_FLAG) {
2761 env->sregs[SR_ESR] |= 1 << 12;
2762 env->sregs[SR_PC] -= 4;
b4916d7b 2763 /* FIXME: if branch was immed, replay the imm as well. */
b76da7e3
EI		 2764 }
2765
2766 env->iflags &= ~(IMM_FLAG | D_FLAG);
2767
2768 switch (env->sregs[SR_ESR] & 31) {
22a78d64 2769 case ESR_EC_DIVZERO:
a86b3c64 2770 info.si_signo = TARGET_SIGFPE;
22a78d64
EI		 2771 info.si_errno = 0;
2772 info.si_code = TARGET_FPE_FLTDIV;
2773 info._sifields._sigfault._addr = 0;
9d2803f7 2774 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
22a78d64 2775 break;
b76da7e3 2776 case ESR_EC_FPU:
a86b3c64 2777 info.si_signo = TARGET_SIGFPE;
b76da7e3
EI		 2778 info.si_errno = 0;
2779 if (env->sregs[SR_FSR] & FSR_IO) {
2780 info.si_code = TARGET_FPE_FLTINV;
2781 }
2782 if (env->sregs[SR_FSR] & FSR_DZ) {
2783 info.si_code = TARGET_FPE_FLTDIV;
2784 }
2785 info._sifields._sigfault._addr = 0;
9d2803f7 2786 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
b76da7e3
EI		 2787 break;
2788 default:
2789 printf ("Unhandled hw-exception: 0x%x\n",
2e42d52d 2790 env->sregs[SR_ESR] & ESR_EC_MASK);
878096ee 2791 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 2792 exit(EXIT_FAILURE);
b76da7e3
EI		 2793 break;
2794 }
2795 break;
b779e29e
EI		 2796 case EXCP_DEBUG:
2797 {
2798 int sig;
2799
db6b81d4 2800 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
b779e29e
EI		 2801 if (sig)
2802 {
2803 info.si_signo = sig;
2804 info.si_errno = 0;
2805 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 2806 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
b779e29e
EI		 2807 }
2808 }
2809 break;
fdbc2b57
RH		 2810 case EXCP_ATOMIC:
2811 cpu_exec_step_atomic(cs);
2812 break;
b779e29e
EI		 2813 default:
2814 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2815 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 2816 exit(EXIT_FAILURE);
b779e29e
EI		 2817 }
2818 process_pending_signals (env);
2819 }
2820}
2821#endif
2822
e6e5906b
PB		 2823#ifdef TARGET_M68K
2824
2825void cpu_loop(CPUM68KState *env)
2826{
878096ee 2827 CPUState *cs = CPU(m68k_env_get_cpu(env));
e6e5906b
PB		 2828 int trapnr;
2829 unsigned int n;
c227f099 2830 target_siginfo_t info;
0429a971 2831 TaskState *ts = cs->opaque;
3b46e624 2832
e6e5906b 2833 for(;;) {
b040bc9c 2834 cpu_exec_start(cs);
8642c1b8 2835 trapnr = cpu_exec(cs);
b040bc9c 2836 cpu_exec_end(cs);
d148d90e
SF		 2837 process_queued_cpu_work(cs);
2838
e6e5906b
PB		 2839 switch(trapnr) {
2840 case EXCP_ILLEGAL:
2841 {
2842 if (ts->sim_syscalls) {
2843 uint16_t nr;
d8d5119c 2844 get_user_u16(nr, env->pc + 2);
e6e5906b
PB		 2845 env->pc += 4;
2846 do_m68k_simcall(env, nr);
2847 } else {
2848 goto do_sigill;
2849 }
2850 }
2851 break;
a87295e8 2852 case EXCP_HALT_INSN:
e6e5906b 2853 /* Semihosing syscall. */
a87295e8 2854 env->pc += 4;
e6e5906b
PB		 2855 do_m68k_semihosting(env, env->dregs[0]);
2856 break;
2857 case EXCP_LINEA:
2858 case EXCP_LINEF:
2859 case EXCP_UNSUPPORTED:
2860 do_sigill:
a86b3c64 2861 info.si_signo = TARGET_SIGILL;
e6e5906b
PB		 2862 info.si_errno = 0;
2863 info.si_code = TARGET_ILL_ILLOPN;
2864 info._sifields._sigfault._addr = env->pc;
9d2803f7 2865 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
e6e5906b
PB		 2866 break;
2867 case EXCP_TRAP0:
2868 {
7ccb84a9 2869 abi_long ret;
e6e5906b
PB		 2870 ts->sim_syscalls = 0;
2871 n = env->dregs[0];
2872 env->pc += 2;
7ccb84a9
TB		 2873 ret = do_syscall(env,
2874 n,
2875 env->dregs[1],
2876 env->dregs[2],
2877 env->dregs[3],
2878 env->dregs[4],
2879 env->dregs[5],
2880 env->aregs[0],
2881 0, 0);
2882 if (ret == -TARGET_ERESTARTSYS) {
2883 env->pc -= 2;
2884 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2885 env->dregs[0] = ret;
2886 }
e6e5906b
PB		 2887 }
2888 break;
2889 case EXCP_INTERRUPT:
2890 /* just indicate that signals should be handled asap */
2891 break;
2892 case EXCP_ACCESS:
2893 {
a86b3c64 2894 info.si_signo = TARGET_SIGSEGV;
e6e5906b
PB		 2895 info.si_errno = 0;
2896 /* XXX: check env->error_code */
2897 info.si_code = TARGET_SEGV_MAPERR;
2898 info._sifields._sigfault._addr = env->mmu.ar;
9d2803f7 2899 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
e6e5906b
PB		 2900 }
2901 break;
2902 case EXCP_DEBUG:
2903 {
2904 int sig;
2905
db6b81d4 2906 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
e6e5906b
PB		 2907 if (sig)
2908 {
2909 info.si_signo = sig;
2910 info.si_errno = 0;
2911 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 2912 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
e6e5906b
PB		 2913 }
2914 }
2915 break;
fdbc2b57
RH		 2916 case EXCP_ATOMIC:
2917 cpu_exec_step_atomic(cs);
2918 break;
e6e5906b 2919 default:
120a9848 2920 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
e6e5906b
PB		 2921 abort();
2922 }
2923 process_pending_signals(env);
2924 }
2925}
2926#endif /* TARGET_M68K */
2927
7a3148a9 2928#ifdef TARGET_ALPHA
05390248 2929void cpu_loop(CPUAlphaState *env)
7a3148a9 2930{
878096ee 2931 CPUState *cs = CPU(alpha_env_get_cpu(env));
e96efcfc 2932 int trapnr;
c227f099 2933 target_siginfo_t info;
6049f4f8 2934 abi_long sysret;
3b46e624 2935
7a3148a9 2936 while (1) {
b040bc9c 2937 cpu_exec_start(cs);
8642c1b8 2938 trapnr = cpu_exec(cs);
b040bc9c 2939 cpu_exec_end(cs);
d148d90e 2940 process_queued_cpu_work(cs);
3b46e624 2941
ac316ca4
RH		 2942 /* All of the traps imply a transition through PALcode, which
2943 implies an REI instruction has been executed. Which means
2944 that the intr_flag should be cleared. */
2945 env->intr_flag = 0;
2946
7a3148a9
JM		 2947 switch (trapnr) {
2948 case EXCP_RESET:
2949 fprintf(stderr, "Reset requested. Exit\n");
4d1275c2 2950 exit(EXIT_FAILURE);
7a3148a9
JM		 2951 break;
2952 case EXCP_MCHK:
2953 fprintf(stderr, "Machine check exception. Exit\n");
4d1275c2 2954 exit(EXIT_FAILURE);
7a3148a9 2955 break;
07b6c13b
RH		 2956 case EXCP_SMP_INTERRUPT:
2957 case EXCP_CLK_INTERRUPT:
2958 case EXCP_DEV_INTERRUPT:
5fafdf24 2959 fprintf(stderr, "External interrupt. Exit\n");
4d1275c2 2960 exit(EXIT_FAILURE);
7a3148a9 2961 break;
07b6c13b 2962 case EXCP_MMFAULT:
6910b8f6 2963 env->lock_addr = -1;
6049f4f8
RH		 2964 info.si_signo = TARGET_SIGSEGV;
2965 info.si_errno = 0;
129d8aa5 2966 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
0be1d07c 2967 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
129d8aa5 2968 info._sifields._sigfault._addr = env->trap_arg0;
9d2803f7 2969 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
7a3148a9 2970 break;
7a3148a9 2971 case EXCP_UNALIGN:
6910b8f6 2972 env->lock_addr = -1;
6049f4f8
RH		 2973 info.si_signo = TARGET_SIGBUS;
2974 info.si_errno = 0;
2975 info.si_code = TARGET_BUS_ADRALN;
129d8aa5 2976 info._sifields._sigfault._addr = env->trap_arg0;
9d2803f7 2977 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
7a3148a9
JM		 2978 break;
2979 case EXCP_OPCDEC:
6049f4f8 2980 do_sigill:
6910b8f6 2981 env->lock_addr = -1;
6049f4f8
RH		 2982 info.si_signo = TARGET_SIGILL;
2983 info.si_errno = 0;
2984 info.si_code = TARGET_ILL_ILLOPC;
2985 info._sifields._sigfault._addr = env->pc;
9d2803f7 2986 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
7a3148a9 2987 break;
07b6c13b
RH		 2988 case EXCP_ARITH:
2989 env->lock_addr = -1;
2990 info.si_signo = TARGET_SIGFPE;
2991 info.si_errno = 0;
2992 info.si_code = TARGET_FPE_FLTINV;
2993 info._sifields._sigfault._addr = env->pc;
9d2803f7 2994 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
07b6c13b 2995 break;
7a3148a9 2996 case EXCP_FEN:
6049f4f8 2997 /* No-op. Linux simply re-enables the FPU. */
7a3148a9 2998 break;
07b6c13b 2999 case EXCP_CALL_PAL:
6910b8f6 3000 env->lock_addr = -1;
07b6c13b 3001 switch (env->error_code) {
6049f4f8
RH		 3002 case 0x80:
3003 /* BPT */
3004 info.si_signo = TARGET_SIGTRAP;
3005 info.si_errno = 0;
3006 info.si_code = TARGET_TRAP_BRKPT;
3007 info._sifields._sigfault._addr = env->pc;
9d2803f7 3008 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
6049f4f8
RH		 3009 break;
3010 case 0x81:
3011 /* BUGCHK */
3012 info.si_signo = TARGET_SIGTRAP;
3013 info.si_errno = 0;
3014 info.si_code = 0;
3015 info._sifields._sigfault._addr = env->pc;
9d2803f7 3016 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
6049f4f8
RH		 3017 break;
3018 case 0x83:
3019 /* CALLSYS */
3020 trapnr = env->ir[IR_V0];
3021 sysret = do_syscall(env, trapnr,
3022 env->ir[IR_A0], env->ir[IR_A1],
3023 env->ir[IR_A2], env->ir[IR_A3],
5945cfcb
PM		 3024 env->ir[IR_A4], env->ir[IR_A5],
3025 0, 0);
338c858c
TB		 3026 if (sysret == -TARGET_ERESTARTSYS) {
3027 env->pc -= 4;
3028 break;
3029 }
3030 if (sysret == -TARGET_QEMU_ESIGRETURN) {
a5b3b13b
RH		 3031 break;
3032 }
3033 /* Syscall writes 0 to V0 to bypass error check, similar
0e141977
RH		 3034 to how this is handled internal to Linux kernel.
3035 (Ab)use trapnr temporarily as boolean indicating error. */
3036 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3037 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3038 env->ir[IR_A3] = trapnr;
6049f4f8
RH		 3039 break;
3040 case 0x86:
3041 /* IMB */
3042 /* ??? We can probably elide the code using page_unprotect
3043 that is checking for self-modifying code. Instead we
3044 could simply call tb_flush here. Until we work out the
3045 changes required to turn off the extra write protection,
3046 this can be a no-op. */
3047 break;
3048 case 0x9E:
3049 /* RDUNIQUE */
3050 /* Handled in the translator for usermode. */
3051 abort();
3052 case 0x9F:
3053 /* WRUNIQUE */
3054 /* Handled in the translator for usermode. */
3055 abort();
3056 case 0xAA:
3057 /* GENTRAP */
3058 info.si_signo = TARGET_SIGFPE;
3059 switch (env->ir[IR_A0]) {
3060 case TARGET_GEN_INTOVF:
3061 info.si_code = TARGET_FPE_INTOVF;
3062 break;
3063 case TARGET_GEN_INTDIV:
3064 info.si_code = TARGET_FPE_INTDIV;
3065 break;
3066 case TARGET_GEN_FLTOVF:
3067 info.si_code = TARGET_FPE_FLTOVF;
3068 break;
3069 case TARGET_GEN_FLTUND:
3070 info.si_code = TARGET_FPE_FLTUND;
3071 break;
3072 case TARGET_GEN_FLTINV:
3073 info.si_code = TARGET_FPE_FLTINV;
3074 break;
3075 case TARGET_GEN_FLTINE:
3076 info.si_code = TARGET_FPE_FLTRES;
3077 break;
3078 case TARGET_GEN_ROPRAND:
3079 info.si_code = 0;
3080 break;
3081 default:
3082 info.si_signo = TARGET_SIGTRAP;
3083 info.si_code = 0;
3084 break;
3085 }
3086 info.si_errno = 0;
3087 info._sifields._sigfault._addr = env->pc;
9d2803f7 3088 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
6049f4f8
RH		 3089 break;
3090 default:
3091 goto do_sigill;
3092 }
7a3148a9 3093 break;
7a3148a9 3094 case EXCP_DEBUG:
db6b81d4 3095 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
6049f4f8 3096 if (info.si_signo) {
6910b8f6 3097 env->lock_addr = -1;
6049f4f8
RH		 3098 info.si_errno = 0;
3099 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 3100 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
7a3148a9
JM		 3101 }
3102 break;
d0f20495
RH		 3103 case EXCP_INTERRUPT:
3104 /* Just indicate that signals should be handled asap. */
3105 break;
fdbc2b57
RH		 3106 case EXCP_ATOMIC:
3107 cpu_exec_step_atomic(cs);
3108 break;
7a3148a9
JM		 3109 default:
3110 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3111 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3112 exit(EXIT_FAILURE);
7a3148a9
JM		 3113 }
3114 process_pending_signals (env);
3115 }
3116}
3117#endif /* TARGET_ALPHA */
3118
a4c075f1
UH		 3119#ifdef TARGET_S390X
3120void cpu_loop(CPUS390XState *env)
3121{
878096ee 3122 CPUState *cs = CPU(s390_env_get_cpu(env));
d5a103cd 3123 int trapnr, n, sig;
a4c075f1 3124 target_siginfo_t info;
d5a103cd 3125 target_ulong addr;
47405ab6 3126 abi_long ret;
a4c075f1
UH		 3127
3128 while (1) {
b040bc9c 3129 cpu_exec_start(cs);
8642c1b8 3130 trapnr = cpu_exec(cs);
b040bc9c 3131 cpu_exec_end(cs);
d148d90e
SF		 3132 process_queued_cpu_work(cs);
3133
a4c075f1
UH		 3134 switch (trapnr) {
3135 case EXCP_INTERRUPT:
d5a103cd 3136 /* Just indicate that signals should be handled asap. */
a4c075f1 3137 break;
a4c075f1 3138
d5a103cd
RH		 3139 case EXCP_SVC:
3140 n = env->int_svc_code;
3141 if (!n) {
3142 /* syscalls > 255 */
3143 n = env->regs[1];
a4c075f1 3144 }
d5a103cd 3145 env->psw.addr += env->int_svc_ilen;
47405ab6
TB		 3146 ret = do_syscall(env, n, env->regs[2], env->regs[3],
3147 env->regs[4], env->regs[5],
3148 env->regs[6], env->regs[7], 0, 0);
3149 if (ret == -TARGET_ERESTARTSYS) {
3150 env->psw.addr -= env->int_svc_ilen;
3151 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3152 env->regs[2] = ret;
3153 }
a4c075f1 3154 break;
d5a103cd
RH		 3155
3156 case EXCP_DEBUG:
db6b81d4 3157 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d5a103cd
RH		 3158 if (sig) {
3159 n = TARGET_TRAP_BRKPT;
3160 goto do_signal_pc;
a4c075f1
UH		 3161 }
3162 break;
d5a103cd
RH		 3163 case EXCP_PGM:
3164 n = env->int_pgm_code;
3165 switch (n) {
3166 case PGM_OPERATION:
3167 case PGM_PRIVILEGED:
a86b3c64 3168 sig = TARGET_SIGILL;
d5a103cd
RH		 3169 n = TARGET_ILL_ILLOPC;
3170 goto do_signal_pc;
3171 case PGM_PROTECTION:
3172 case PGM_ADDRESSING:
a86b3c64 3173 sig = TARGET_SIGSEGV;
a4c075f1 3174 /* XXX: check env->error_code */
d5a103cd
RH		 3175 n = TARGET_SEGV_MAPERR;
3176 addr = env->__excp_addr;
3177 goto do_signal;
3178 case PGM_EXECUTE:
3179 case PGM_SPECIFICATION:
3180 case PGM_SPECIAL_OP:
3181 case PGM_OPERAND:
3182 do_sigill_opn:
a86b3c64 3183 sig = TARGET_SIGILL;
d5a103cd
RH		 3184 n = TARGET_ILL_ILLOPN;
3185 goto do_signal_pc;
3186
3187 case PGM_FIXPT_OVERFLOW:
a86b3c64 3188 sig = TARGET_SIGFPE;
d5a103cd
RH		 3189 n = TARGET_FPE_INTOVF;
3190 goto do_signal_pc;
3191 case PGM_FIXPT_DIVIDE:
a86b3c64 3192 sig = TARGET_SIGFPE;
d5a103cd
RH		 3193 n = TARGET_FPE_INTDIV;
3194 goto do_signal_pc;
3195
3196 case PGM_DATA:
3197 n = (env->fpc >> 8) & 0xff;
3198 if (n == 0xff) {
3199 /* compare-and-trap */
3200 goto do_sigill_opn;
3201 } else {
3202 /* An IEEE exception, simulated or otherwise. */
3203 if (n & 0x80) {
3204 n = TARGET_FPE_FLTINV;
3205 } else if (n & 0x40) {
3206 n = TARGET_FPE_FLTDIV;
3207 } else if (n & 0x20) {
3208 n = TARGET_FPE_FLTOVF;
3209 } else if (n & 0x10) {
3210 n = TARGET_FPE_FLTUND;
3211 } else if (n & 0x08) {
3212 n = TARGET_FPE_FLTRES;
3213 } else {
3214 /* ??? Quantum exception; BFP, DFP error. */
3215 goto do_sigill_opn;
3216 }
a86b3c64 3217 sig = TARGET_SIGFPE;
d5a103cd
RH		 3218 goto do_signal_pc;
3219 }
3220
3221 default:
3222 fprintf(stderr, "Unhandled program exception: %#x\n", n);
878096ee 3223 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3224 exit(EXIT_FAILURE);
a4c075f1
UH		 3225 }
3226 break;
d5a103cd
RH		 3227
3228 do_signal_pc:
3229 addr = env->psw.addr;
3230 do_signal:
3231 info.si_signo = sig;
3232 info.si_errno = 0;
3233 info.si_code = n;
3234 info._sifields._sigfault._addr = addr;
9d2803f7 3235 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
a4c075f1 3236 break;
d5a103cd 3237
fdbc2b57
RH		 3238 case EXCP_ATOMIC:
3239 cpu_exec_step_atomic(cs);
3240 break;
a4c075f1 3241 default:
d5a103cd 3242 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
878096ee 3243 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3244 exit(EXIT_FAILURE);
a4c075f1
UH		 3245 }
3246 process_pending_signals (env);
3247 }
3248}
3249
3250#endif /* TARGET_S390X */
3251
b16189b2
CG		 3252#ifdef TARGET_TILEGX
3253
b16189b2
CG		 3254static void gen_sigill_reg(CPUTLGState *env)
3255{
3256 target_siginfo_t info;
3257
3258 info.si_signo = TARGET_SIGILL;
3259 info.si_errno = 0;
3260 info.si_code = TARGET_ILL_PRVREG;
3261 info._sifields._sigfault._addr = env->pc;
9d2803f7 3262 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
b16189b2
CG		 3263}
3264
a0577d2a 3265static void do_signal(CPUTLGState *env, int signo, int sigcode)
dd8070d8
CG		 3266{
3267 target_siginfo_t info;
3268
a0577d2a 3269 info.si_signo = signo;
dd8070d8 3270 info.si_errno = 0;
dd8070d8 3271 info._sifields._sigfault._addr = env->pc;
a0577d2a
RH		 3272
3273 if (signo == TARGET_SIGSEGV) {
3274 /* The passed in sigcode is a dummy; check for a page mapping
3275 and pass either MAPERR or ACCERR. */
3276 target_ulong addr = env->excaddr;
3277 info._sifields._sigfault._addr = addr;
3278 if (page_check_range(addr, 1, PAGE_VALID) < 0) {
3279 sigcode = TARGET_SEGV_MAPERR;
3280 } else {
3281 sigcode = TARGET_SEGV_ACCERR;
3282 }
3283 }
3284 info.si_code = sigcode;
3285
9d2803f7 3286 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
dd8070d8
CG		 3287}
3288
a0577d2a
RH		 3289static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
3290{
3291 env->excaddr = addr;
3292 do_signal(env, TARGET_SIGSEGV, 0);
3293}
3294
0583b233
RH		 3295static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
3296{
3297 if (unlikely(reg >= TILEGX_R_COUNT)) {
3298 switch (reg) {
3299 case TILEGX_R_SN:
3300 case TILEGX_R_ZERO:
3301 return;
3302 case TILEGX_R_IDN0:
3303 case TILEGX_R_IDN1:
3304 case TILEGX_R_UDN0:
3305 case TILEGX_R_UDN1:
3306 case TILEGX_R_UDN2:
3307 case TILEGX_R_UDN3:
3308 gen_sigill_reg(env);
3309 return;
3310 default:
3311 g_assert_not_reached();
3312 }
3313 }
3314 env->regs[reg] = val;
3315}
3316
3317/*
3318 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
3319 * memory at the address held in the first source register. If the values are
3320 * not equal, then no memory operation is performed. If the values are equal,
3321 * the 8-byte quantity from the second source register is written into memory
3322 * at the address held in the first source register. In either case, the result
3323 * of the instruction is the value read from memory. The compare and write to
3324 * memory are atomic and thus can be used for synchronization purposes. This
3325 * instruction only operates for addresses aligned to a 8-byte boundary.
3326 * Unaligned memory access causes an Unaligned Data Reference interrupt.
3327 *
3328 * Functional Description (64-bit)
3329 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
3330 * rf[Dest] = memVal;
3331 * if (memVal == SPR[CmpValueSPR])
3332 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
3333 *
3334 * Functional Description (32-bit)
3335 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
3336 * rf[Dest] = memVal;
3337 * if (memVal == signExtend32 (SPR[CmpValueSPR]))
3338 * memoryWriteWord (rf[SrcA], rf[SrcB]);
3339 *
3340 *
3341 * This function also processes exch and exch4 which need not process SPR.
3342 */
3343static void do_exch(CPUTLGState *env, bool quad, bool cmp)
3344{
3345 target_ulong addr;
3346 target_long val, sprval;
3347
3348 start_exclusive();
3349
3350 addr = env->atomic_srca;
3351 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3352 goto sigsegv_maperr;
3353 }
3354
3355 if (cmp) {
3356 if (quad) {
3357 sprval = env->spregs[TILEGX_SPR_CMPEXCH];
3358 } else {
3359 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
3360 }
3361 }
3362
3363 if (!cmp || val == sprval) {
3364 target_long valb = env->atomic_srcb;
3365 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3366 goto sigsegv_maperr;
3367 }
3368 }
3369
3370 set_regval(env, env->atomic_dstr, val);
3371 end_exclusive();
3372 return;
3373
3374 sigsegv_maperr:
3375 end_exclusive();
3376 gen_sigsegv_maperr(env, addr);
3377}
3378
3379static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
3380{
3381 int8_t write = 1;
3382 target_ulong addr;
3383 target_long val, valb;
3384
3385 start_exclusive();
3386
3387 addr = env->atomic_srca;
3388 valb = env->atomic_srcb;
3389 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3390 goto sigsegv_maperr;
3391 }
3392
3393 switch (trapnr) {
3394 case TILEGX_EXCP_OPCODE_FETCHADD:
3395 case TILEGX_EXCP_OPCODE_FETCHADD4:
3396 valb += val;
3397 break;
3398 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3399 valb += val;
3400 if (valb < 0) {
3401 write = 0;
3402 }
3403 break;
3404 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3405 valb += val;
3406 if ((int32_t)valb < 0) {
3407 write = 0;
3408 }
3409 break;
3410 case TILEGX_EXCP_OPCODE_FETCHAND:
3411 case TILEGX_EXCP_OPCODE_FETCHAND4:
3412 valb &= val;
3413 break;
3414 case TILEGX_EXCP_OPCODE_FETCHOR:
3415 case TILEGX_EXCP_OPCODE_FETCHOR4:
3416 valb |= val;
3417 break;
3418 default:
3419 g_assert_not_reached();
3420 }
3421
3422 if (write) {
3423 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3424 goto sigsegv_maperr;
3425 }
3426 }
3427
3428 set_regval(env, env->atomic_dstr, val);
3429 end_exclusive();
3430 return;
3431
3432 sigsegv_maperr:
3433 end_exclusive();
3434 gen_sigsegv_maperr(env, addr);
3435}
3436
b16189b2
CG		 3437void cpu_loop(CPUTLGState *env)
3438{
3439 CPUState *cs = CPU(tilegx_env_get_cpu(env));
3440 int trapnr;
3441
3442 while (1) {
3443 cpu_exec_start(cs);
8642c1b8 3444 trapnr = cpu_exec(cs);
b16189b2 3445 cpu_exec_end(cs);
d148d90e
SF		 3446 process_queued_cpu_work(cs);
3447
b16189b2
CG		 3448 switch (trapnr) {
3449 case TILEGX_EXCP_SYSCALL:
a9175169
PM		 3450 {
3451 abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR],
3452 env->regs[0], env->regs[1],
3453 env->regs[2], env->regs[3],
3454 env->regs[4], env->regs[5],
3455 env->regs[6], env->regs[7]);
3456 if (ret == -TARGET_ERESTARTSYS) {
3457 env->pc -= 8;
3458 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3459 env->regs[TILEGX_R_RE] = ret;
3460 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0;
3461 }
b16189b2 3462 break;
a9175169 3463 }
0583b233
RH		 3464 case TILEGX_EXCP_OPCODE_EXCH:
3465 do_exch(env, true, false);
3466 break;
3467 case TILEGX_EXCP_OPCODE_EXCH4:
3468 do_exch(env, false, false);
3469 break;
3470 case TILEGX_EXCP_OPCODE_CMPEXCH:
3471 do_exch(env, true, true);
3472 break;
3473 case TILEGX_EXCP_OPCODE_CMPEXCH4:
3474 do_exch(env, false, true);
3475 break;
3476 case TILEGX_EXCP_OPCODE_FETCHADD:
3477 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3478 case TILEGX_EXCP_OPCODE_FETCHAND:
3479 case TILEGX_EXCP_OPCODE_FETCHOR:
3480 do_fetch(env, trapnr, true);
3481 break;
3482 case TILEGX_EXCP_OPCODE_FETCHADD4:
3483 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3484 case TILEGX_EXCP_OPCODE_FETCHAND4:
3485 case TILEGX_EXCP_OPCODE_FETCHOR4:
3486 do_fetch(env, trapnr, false);
3487 break;
dd8070d8 3488 case TILEGX_EXCP_SIGNAL:
a0577d2a 3489 do_signal(env, env->signo, env->sigcode);
dd8070d8 3490 break;
b16189b2
CG		 3491 case TILEGX_EXCP_REG_IDN_ACCESS:
3492 case TILEGX_EXCP_REG_UDN_ACCESS:
3493 gen_sigill_reg(env);
3494 break;
fdbc2b57
RH		 3495 case EXCP_ATOMIC:
3496 cpu_exec_step_atomic(cs);
3497 break;
b16189b2
CG		 3498 default:
3499 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
3500 g_assert_not_reached();
3501 }
3502 process_pending_signals(env);
3503 }
3504}
3505
3506#endif
3507
a2247f8e 3508THREAD CPUState *thread_cpu;
59faf6d6 3509
178f9429
SF		 3510bool qemu_cpu_is_self(CPUState *cpu)
3511{
3512 return thread_cpu == cpu;
3513}
3514
3515void qemu_cpu_kick(CPUState *cpu)
3516{
3517 cpu_exit(cpu);
3518}
3519
edf8e2af
MW		 3520void task_settid(TaskState *ts)
3521{
3522 if (ts->ts_tid == 0) {
edf8e2af 3523 ts->ts_tid = (pid_t)syscall(SYS_gettid);
edf8e2af
MW		 3524 }
3525}
3526
3527void stop_all_tasks(void)
3528{
3529 /*
3530 * We trust that when using NPTL, start_exclusive()
3531 * handles thread stopping correctly.
3532 */
3533 start_exclusive();
3534}
3535
c3a92833 3536/* Assumes contents are already zeroed. */
624f7979
PB		 3537void init_task_state(TaskState *ts)
3538{
624f7979 3539 ts->used = 1;
624f7979 3540}
fc9c5412 3541
30ba0ee5
AF		 3542CPUArchState *cpu_copy(CPUArchState *env)
3543{
ff4700b0 3544 CPUState *cpu = ENV_GET_CPU(env);
2994fd96 3545 CPUState *new_cpu = cpu_init(cpu_model);
61c7480f 3546 CPUArchState *new_env = new_cpu->env_ptr;
30ba0ee5
AF		 3547 CPUBreakpoint *bp;
3548 CPUWatchpoint *wp;
30ba0ee5
AF		 3549
3550 /* Reset non arch specific state */
75a34036 3551 cpu_reset(new_cpu);
30ba0ee5
AF		 3552
3553 memcpy(new_env, env, sizeof(CPUArchState));
3554
3555 /* Clone all break/watchpoints.
3556 Note: Once we support ptrace with hw-debug register access, make sure
3557 BP_CPU break/watchpoints are handled correctly on clone. */
1d085f6c
TB		 3558 QTAILQ_INIT(&new_cpu->breakpoints);
3559 QTAILQ_INIT(&new_cpu->watchpoints);
f0c3c505 3560 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
b3310ab3 3561 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
30ba0ee5 3562 }
ff4700b0 3563 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
05068c0d 3564 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
30ba0ee5 3565 }
30ba0ee5
AF		 3566
3567 return new_env;
3568}
3569
fc9c5412
JS		 3570static void handle_arg_help(const char *arg)
3571{
4d1275c2 3572 usage(EXIT_SUCCESS);
fc9c5412
JS		 3573}
3574
3575static void handle_arg_log(const char *arg)
3576{
3577 int mask;
fc9c5412 3578
4fde1eba 3579 mask = qemu_str_to_log_mask(arg);
fc9c5412 3580 if (!mask) {
59a6fa6e 3581 qemu_print_log_usage(stdout);
4d1275c2 3582 exit(EXIT_FAILURE);
fc9c5412 3583 }
f2937a33 3584 qemu_log_needs_buffers();
24537a01 3585 qemu_set_log(mask);
fc9c5412
JS		 3586}
3587
50171d42
CWR		 3588static void handle_arg_log_filename(const char *arg)
3589{
daa76aa4 3590 qemu_set_log_filename(arg, &error_fatal);
50171d42
CWR		 3591}
3592
fc9c5412
JS		 3593static void handle_arg_set_env(const char *arg)
3594{
3595 char *r, *p, *token;
3596 r = p = strdup(arg);
3597 while ((token = strsep(&p, ",")) != NULL) {
3598 if (envlist_setenv(envlist, token) != 0) {
4d1275c2 3599 usage(EXIT_FAILURE);
fc9c5412
JS		 3600 }
3601 }
3602 free(r);
3603}
3604
3605static void handle_arg_unset_env(const char *arg)
3606{
3607 char *r, *p, *token;
3608 r = p = strdup(arg);
3609 while ((token = strsep(&p, ",")) != NULL) {
3610 if (envlist_unsetenv(envlist, token) != 0) {
4d1275c2 3611 usage(EXIT_FAILURE);
fc9c5412
JS		 3612 }
3613 }
3614 free(r);
3615}
3616
3617static void handle_arg_argv0(const char *arg)
3618{
3619 argv0 = strdup(arg);
3620}
3621
3622static void handle_arg_stack_size(const char *arg)
3623{
3624 char *p;
3625 guest_stack_size = strtoul(arg, &p, 0);
3626 if (guest_stack_size == 0) {
4d1275c2 3627 usage(EXIT_FAILURE);
fc9c5412
JS		 3628 }
3629
3630 if (*p == 'M') {
3631 guest_stack_size *= 1024 * 1024;
3632 } else if (*p == 'k' || *p == 'K') {
3633 guest_stack_size *= 1024;
3634 }
3635}
3636
3637static void handle_arg_ld_prefix(const char *arg)
3638{
3639 interp_prefix = strdup(arg);
3640}
3641
3642static void handle_arg_pagesize(const char *arg)
3643{
3644 qemu_host_page_size = atoi(arg);
3645 if (qemu_host_page_size == 0 ||
3646 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3647 fprintf(stderr, "page size must be a power of two\n");
4d1275c2 3648 exit(EXIT_FAILURE);
fc9c5412
JS		 3649 }
3650}
3651
c5e4a5a9
MR		 3652static void handle_arg_randseed(const char *arg)
3653{
3654 unsigned long long seed;
3655
3656 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3657 fprintf(stderr, "Invalid seed number: %s\n", arg);
4d1275c2 3658 exit(EXIT_FAILURE);
c5e4a5a9
MR		 3659 }
3660 srand(seed);
3661}
3662
fc9c5412
JS		 3663static void handle_arg_gdb(const char *arg)
3664{
3665 gdbstub_port = atoi(arg);
3666}
3667
3668static void handle_arg_uname(const char *arg)
3669{
3670 qemu_uname_release = strdup(arg);
3671}
3672
3673static void handle_arg_cpu(const char *arg)
3674{
3675 cpu_model = strdup(arg);
c8057f95 3676 if (cpu_model == NULL || is_help_option(cpu_model)) {
fc9c5412 3677 /* XXX: implement xxx_cpu_list for targets that still miss it */
e916cbf8
PM		 3678#if defined(cpu_list)
3679 cpu_list(stdout, &fprintf);
fc9c5412 3680#endif
4d1275c2 3681 exit(EXIT_FAILURE);
fc9c5412
JS		 3682 }
3683}
3684
fc9c5412
JS		 3685static void handle_arg_guest_base(const char *arg)
3686{
3687 guest_base = strtol(arg, NULL, 0);
3688 have_guest_base = 1;
3689}
3690
3691static void handle_arg_reserved_va(const char *arg)
3692{
3693 char *p;
3694 int shift = 0;
3695 reserved_va = strtoul(arg, &p, 0);
3696 switch (*p) {
3697 case 'k':
3698 case 'K':
3699 shift = 10;
3700 break;
3701 case 'M':
3702 shift = 20;
3703 break;
3704 case 'G':
3705 shift = 30;
3706 break;
3707 }
3708 if (shift) {
3709 unsigned long unshifted = reserved_va;
3710 p++;
3711 reserved_va <<= shift;
3712 if (((reserved_va >> shift) != unshifted)
3713#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3714 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3715#endif
3716 ) {
3717 fprintf(stderr, "Reserved virtual address too big\n");
4d1275c2 3718 exit(EXIT_FAILURE);
fc9c5412
JS		 3719 }
3720 }
3721 if (*p) {
3722 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
4d1275c2 3723 exit(EXIT_FAILURE);
fc9c5412
JS		 3724 }
3725}
fc9c5412
JS		 3726
3727static void handle_arg_singlestep(const char *arg)
3728{
3729 singlestep = 1;
3730}
3731
3732static void handle_arg_strace(const char *arg)
3733{
3734 do_strace = 1;
3735}
3736
3737static void handle_arg_version(const char *arg)
3738{
2e59915d 3739 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
0781dd6e 3740 "\n" QEMU_COPYRIGHT "\n");
4d1275c2 3741 exit(EXIT_SUCCESS);
fc9c5412
JS		 3742}
3743
6533dd6e
LV		 3744static char *trace_file;
3745static void handle_arg_trace(const char *arg)
3746{
3747 g_free(trace_file);
3748 trace_file = trace_opt_parse(arg);
3749}
3750
fc9c5412
JS		 3751struct qemu_argument {
3752 const char *argv;
3753 const char *env;
3754 bool has_arg;
3755 void (*handle_opt)(const char *arg);
3756 const char *example;
3757 const char *help;
3758};
3759
42644cee 3760static const struct qemu_argument arg_table[] = {
fc9c5412
JS		 3761 {"h", "", false, handle_arg_help,
3762 "", "print this help"},
daaf8c8e
MI		 3763 {"help", "", false, handle_arg_help,
3764 "", ""},
fc9c5412
JS		 3765 {"g", "QEMU_GDB", true, handle_arg_gdb,
3766 "port", "wait gdb connection to 'port'"},
3767 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3768 "path", "set the elf interpreter prefix to 'path'"},
3769 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3770 "size", "set the stack size to 'size' bytes"},
3771 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
c8057f95 3772 "model", "select CPU (-cpu help for list)"},
fc9c5412
JS		 3773 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3774 "var=value", "sets targets environment variable (see below)"},
3775 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3776 "var", "unsets targets environment variable (see below)"},
3777 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3778 "argv0", "forces target process argv[0] to be 'argv0'"},
3779 {"r", "QEMU_UNAME", true, handle_arg_uname,
3780 "uname", "set qemu uname release string to 'uname'"},
fc9c5412
JS		 3781 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3782 "address", "set guest_base address to 'address'"},
3783 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3784 "size", "reserve 'size' bytes for guest virtual address space"},
fc9c5412 3785 {"d", "QEMU_LOG", true, handle_arg_log,
989b697d
PM		 3786 "item[,...]", "enable logging of specified items "
3787 "(use '-d help' for a list of items)"},
50171d42 3788 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
989b697d 3789 "logfile", "write logs to 'logfile' (default stderr)"},
fc9c5412
JS		 3790 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3791 "pagesize", "set the host page size to 'pagesize'"},
3792 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3793 "", "run in singlestep mode"},
3794 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3795 "", "log system calls"},
c5e4a5a9
MR		 3796 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
3797 "", "Seed for pseudo-random number generator"},
6533dd6e
LV		 3798 {"trace", "QEMU_TRACE", true, handle_arg_trace,
3799 "", "[[enable=]<pattern>][,events=<file>][,file=<file>]"},
fc9c5412 3800 {"version", "QEMU_VERSION", false, handle_arg_version,
1386d4c0 3801 "", "display version information and exit"},
fc9c5412
JS		 3802 {NULL, NULL, false, NULL, NULL, NULL}
3803};
3804
d03f9c32 3805static void usage(int exitcode)
fc9c5412 3806{
42644cee 3807 const struct qemu_argument *arginfo;
fc9c5412
JS		 3808 int maxarglen;
3809 int maxenvlen;
3810
2e59915d
PB		 3811 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3812 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
fc9c5412
JS		 3813 "\n"
3814 "Options and associated environment variables:\n"
3815 "\n");
3816
63ec54d7
PM		 3817 /* Calculate column widths. We must always have at least enough space
3818 * for the column header.
3819 */
3820 maxarglen = strlen("Argument");
3821 maxenvlen = strlen("Env-variable");
fc9c5412
JS		 3822
3823 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
63ec54d7
PM		 3824 int arglen = strlen(arginfo->argv);
3825 if (arginfo->has_arg) {
3826 arglen += strlen(arginfo->example) + 1;
3827 }
fc9c5412
JS		 3828 if (strlen(arginfo->env) > maxenvlen) {
3829 maxenvlen = strlen(arginfo->env);
3830 }
63ec54d7
PM		 3831 if (arglen > maxarglen) {
3832 maxarglen = arglen;
fc9c5412
JS		 3833 }
3834 }
3835
63ec54d7
PM		 3836 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3837 maxenvlen, "Env-variable");
fc9c5412
JS		 3838
3839 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3840 if (arginfo->has_arg) {
3841 printf("-%s %-*s %-*s %s\n", arginfo->argv,
63ec54d7
PM		 3842 (int)(maxarglen - strlen(arginfo->argv) - 1),
3843 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
fc9c5412 3844 } else {
63ec54d7 3845 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
fc9c5412
JS		 3846 maxenvlen, arginfo->env,
3847 arginfo->help);
3848 }
3849 }
3850
3851 printf("\n"
3852 "Defaults:\n"
3853 "QEMU_LD_PREFIX = %s\n"
989b697d 3854 "QEMU_STACK_SIZE = %ld byte\n",
fc9c5412 3855 interp_prefix,
989b697d 3856 guest_stack_size);
fc9c5412
JS		 3857
3858 printf("\n"
3859 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3860 "QEMU_UNSET_ENV environment variables to set and unset\n"
3861 "environment variables for the target process.\n"
3862 "It is possible to provide several variables by separating them\n"
3863 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3864 "provide the -E and -U options multiple times.\n"
3865 "The following lines are equivalent:\n"
3866 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3867 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3868 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3869 "Note that if you provide several changes to a single variable\n"
3870 "the last change will stay in effect.\n");
3871
d03f9c32 3872 exit(exitcode);
fc9c5412
JS		 3873}
3874
3875static int parse_args(int argc, char **argv)
3876{
3877 const char *r;
3878 int optind;
42644cee 3879 const struct qemu_argument *arginfo;
fc9c5412
JS		 3880
3881 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3882 if (arginfo->env == NULL) {
3883 continue;
3884 }
3885
3886 r = getenv(arginfo->env);
3887 if (r != NULL) {
3888 arginfo->handle_opt(r);
3889 }
3890 }
3891
3892 optind = 1;
3893 for (;;) {
3894 if (optind >= argc) {
3895 break;
3896 }
3897 r = argv[optind];
3898 if (r[0] != '-') {
3899 break;
3900 }
3901 optind++;
3902 r++;
3903 if (!strcmp(r, "-")) {
3904 break;
3905 }
ba02577c
MI		 3906 /* Treat --foo the same as -foo. */
3907 if (r[0] == '-') {
3908 r++;
3909 }
fc9c5412
JS		 3910
3911 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3912 if (!strcmp(r, arginfo->argv)) {
fc9c5412 3913 if (arginfo->has_arg) {
1386d4c0 3914 if (optind >= argc) {
138940bf
MI		 3915 (void) fprintf(stderr,
3916 "qemu: missing argument for option '%s'\n", r);
4d1275c2 3917 exit(EXIT_FAILURE);
1386d4c0
PM		 3918 }
3919 arginfo->handle_opt(argv[optind]);
fc9c5412 3920 optind++;
1386d4c0
PM		 3921 } else {
3922 arginfo->handle_opt(NULL);
fc9c5412 3923 }
fc9c5412
JS		 3924 break;
3925 }
3926 }
3927
3928 /* no option matched the current argv */
3929 if (arginfo->handle_opt == NULL) {
138940bf 3930 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r);
4d1275c2 3931 exit(EXIT_FAILURE);
fc9c5412
JS		 3932 }
3933 }
3934
3935 if (optind >= argc) {
138940bf 3936 (void) fprintf(stderr, "qemu: no user program specified\n");
4d1275c2 3937 exit(EXIT_FAILURE);
fc9c5412
JS		 3938 }
3939
3940 filename = argv[optind];
3941 exec_path = argv[optind];
3942
3943 return optind;
3944}
3945
902b3d5c 3946int main(int argc, char **argv, char **envp)
31e31b8a 3947{
01ffc75b 3948 struct target_pt_regs regs1, *regs = &regs1;
31e31b8a 3949 struct image_info info1, *info = &info1;
edf8e2af 3950 struct linux_binprm bprm;
48e15fc2 3951 TaskState *ts;
9349b4f9 3952 CPUArchState *env;
db6b81d4 3953 CPUState *cpu;
586314f2 3954 int optind;
04a6dfeb 3955 char **target_environ, **wrk;
7d8cec95
AJ		 3956 char **target_argv;
3957 int target_argc;
7d8cec95 3958 int i;
fd4d81dd 3959 int ret;
03cfd8fa 3960 int execfd;
b12b6a18 3961
fe4db84d 3962 module_call_init(MODULE_INIT_TRACE);
267f685b 3963 qemu_init_cpu_list();
ce008c1f
AF		 3964 module_call_init(MODULE_INIT_QOM);
3965
04a6dfeb
AJ		 3966 if ((envlist = envlist_create()) == NULL) {
3967 (void) fprintf(stderr, "Unable to allocate envlist\n");
4d1275c2 3968 exit(EXIT_FAILURE);
04a6dfeb
AJ		 3969 }
3970
3971 /* add current environment into the list */
3972 for (wrk = environ; *wrk != NULL; wrk++) {
3973 (void) envlist_setenv(envlist, *wrk);
3974 }
3975
703e0e89
RH		 3976 /* Read the stack limit from the kernel. If it's "unlimited",
3977 then we can do little else besides use the default. */
3978 {
3979 struct rlimit lim;
3980 if (getrlimit(RLIMIT_STACK, &lim) == 0
81bbe906
TY		 3981 && lim.rlim_cur != RLIM_INFINITY
3982 && lim.rlim_cur == (target_long)lim.rlim_cur) {
703e0e89
RH		 3983 guest_stack_size = lim.rlim_cur;
3984 }
3985 }
3986
b1f9be31 3987 cpu_model = NULL;
b5ec5ce0 3988
c5e4a5a9
MR		 3989 srand(time(NULL));
3990
6533dd6e
LV		 3991 qemu_add_opts(&qemu_trace_opts);
3992
fc9c5412 3993 optind = parse_args(argc, argv);
586314f2 3994
6533dd6e
LV		 3995 if (!trace_init_backends()) {
3996 exit(1);
3997 }
3998 trace_init_file(trace_file);
3999
31e31b8a 4000 /* Zero out regs */
01ffc75b 4001 memset(regs, 0, sizeof(struct target_pt_regs));
31e31b8a
FB		 4002
4003 /* Zero out image_info */
4004 memset(info, 0, sizeof(struct image_info));
4005
edf8e2af
MW		 4006 memset(&bprm, 0, sizeof (bprm));
4007
74cd30b8
FB		 4008 /* Scan interp_prefix dir for replacement files. */
4009 init_paths(interp_prefix);
4010
4a24a758
PM		 4011 init_qemu_uname_release();
4012
46027c07 4013 if (cpu_model == NULL) {
aaed909a 4014#if defined(TARGET_I386)
46027c07
FB		 4015#ifdef TARGET_X86_64
4016 cpu_model = "qemu64";
4017#else
4018 cpu_model = "qemu32";
4019#endif
aaed909a 4020#elif defined(TARGET_ARM)
088ab16c 4021 cpu_model = "any";
d2fbca94
GX		 4022#elif defined(TARGET_UNICORE32)
4023 cpu_model = "any";
aaed909a
FB		 4024#elif defined(TARGET_M68K)
4025 cpu_model = "any";
4026#elif defined(TARGET_SPARC)
4027#ifdef TARGET_SPARC64
4028 cpu_model = "TI UltraSparc II";
4029#else
4030 cpu_model = "Fujitsu MB86904";
46027c07 4031#endif
aaed909a
FB		 4032#elif defined(TARGET_MIPS)
4033#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
74797f40 4034 cpu_model = "5KEf";
aaed909a
FB		 4035#else
4036 cpu_model = "24Kf";
4037#endif
d962783e
JL		 4038#elif defined TARGET_OPENRISC
4039 cpu_model = "or1200";
aaed909a 4040#elif defined(TARGET_PPC)
a74029f6 4041# ifdef TARGET_PPC64
de3f1b98 4042 cpu_model = "POWER8";
a74029f6 4043# else
aaed909a 4044 cpu_model = "750";
a74029f6 4045# endif
91c45a38
RH		 4046#elif defined TARGET_SH4
4047 cpu_model = TYPE_SH7785_CPU;
aaed909a
FB		 4048#else
4049 cpu_model = "any";
4050#endif
4051 }
d5ab9713 4052 tcg_exec_init(0);
83fb7adf
FB		 4053 /* NOTE: we need to init the CPU at this stage to get
4054 qemu_host_page_size */
2994fd96
EH		 4055 cpu = cpu_init(cpu_model);
4056 if (!cpu) {
aaed909a 4057 fprintf(stderr, "Unable to find CPU definition\n");
4d1275c2 4058 exit(EXIT_FAILURE);
aaed909a 4059 }
2994fd96 4060 env = cpu->env_ptr;
0ac46af3 4061 cpu_reset(cpu);
b55a37c9 4062
db6b81d4 4063 thread_cpu = cpu;
3b46e624 4064
b6741956
FB		 4065 if (getenv("QEMU_STRACE")) {
4066 do_strace = 1;
b92c47c1
TS		 4067 }
4068
c5e4a5a9
MR		 4069 if (getenv("QEMU_RAND_SEED")) {
4070 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4071 }
4072
04a6dfeb
AJ		 4073 target_environ = envlist_to_environ(envlist, NULL);
4074 envlist_free(envlist);
b12b6a18 4075
379f6698
PB		 4076 /*
4077 * Now that page sizes are configured in cpu_init() we can do
4078 * proper page alignment for guest_base.
4079 */
4080 guest_base = HOST_PAGE_ALIGN(guest_base);
68a1c816 4081
806d1021
MI		 4082 if (reserved_va || have_guest_base) {
4083 guest_base = init_guest_space(guest_base, reserved_va, 0,
4084 have_guest_base);
4085 if (guest_base == (unsigned long)-1) {
097b8cb8
PM		 4086 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
4087 "space for use as guest address space (check your virtual "
4088 "memory ulimit setting or reserve less using -R option)\n",
4089 reserved_va);
4d1275c2 4090 exit(EXIT_FAILURE);
68a1c816 4091 }
97cc7560 4092
806d1021
MI		 4093 if (reserved_va) {
4094 mmap_next_start = reserved_va;
97cc7560
DDAG		 4095 }
4096 }
379f6698
PB		 4097
4098 /*
4099 * Read in mmap_min_addr kernel parameter. This value is used
4100 * When loading the ELF image to determine whether guest_base
14f24e14 4101 * is needed. It is also used in mmap_find_vma.
379f6698 4102 */
14f24e14 4103 {
379f6698
PB		 4104 FILE *fp;
4105
4106 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
4107 unsigned long tmp;
4108 if (fscanf(fp, "%lu", &tmp) == 1) {
4109 mmap_min_addr = tmp;
13829020 4110 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr);
379f6698
PB		 4111 }
4112 fclose(fp);
4113 }
4114 }
379f6698 4115
7d8cec95
AJ		 4116 /*
4117 * Prepare copy of argv vector for target.
4118 */
4119 target_argc = argc - optind;
4120 target_argv = calloc(target_argc + 1, sizeof (char *));
4121 if (target_argv == NULL) {
4122 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4d1275c2 4123 exit(EXIT_FAILURE);
7d8cec95
AJ		 4124 }
4125
4126 /*
4127 * If argv0 is specified (using '-0' switch) we replace
4128 * argv[0] pointer with the given one.
4129 */
4130 i = 0;
4131 if (argv0 != NULL) {
4132 target_argv[i++] = strdup(argv0);
4133 }
4134 for (; i < target_argc; i++) {
4135 target_argv[i] = strdup(argv[optind + i]);
4136 }
4137 target_argv[target_argc] = NULL;
4138
c78d65e8 4139 ts = g_new0(TaskState, 1);
edf8e2af
MW		 4140 init_task_state(ts);
4141 /* build Task State */
4142 ts->info = info;
4143 ts->bprm = &bprm;
0429a971 4144 cpu->opaque = ts;
edf8e2af
MW		 4145 task_settid(ts);
4146
0b959cf5
RH		 4147 execfd = qemu_getauxval(AT_EXECFD);
4148 if (execfd == 0) {
03cfd8fa 4149 execfd = open(filename, O_RDONLY);
0b959cf5
RH		 4150 if (execfd < 0) {
4151 printf("Error while loading %s: %s\n", filename, strerror(errno));
4d1275c2 4152 _exit(EXIT_FAILURE);
0b959cf5 4153 }
03cfd8fa
LV		 4154 }
4155
4156 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
fd4d81dd
AP		 4157 info, &bprm);
4158 if (ret != 0) {
885c1d10 4159 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4d1275c2 4160 _exit(EXIT_FAILURE);
b12b6a18
TS		 4161 }
4162
4163 for (wrk = target_environ; *wrk; wrk++) {
4164 free(*wrk);
31e31b8a 4165 }
3b46e624 4166
b12b6a18
TS		 4167 free(target_environ);
4168
13829020 4169 if (qemu_loglevel_mask(CPU_LOG_PAGE)) {
379f6698 4170 qemu_log("guest_base 0x%lx\n", guest_base);
2e77eac6
BS		 4171 log_page_dump();
4172
4173 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4174 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4175 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4176 info->start_code);
4177 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4178 info->start_data);
4179 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4180 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4181 info->start_stack);
4182 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4183 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4184 }
31e31b8a 4185
53a5960a 4186 target_set_brk(info->brk);
31e31b8a 4187 syscall_init();
66fb9763 4188 signal_init();
31e31b8a 4189
9002ec79
RH		 4190 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4191 generating the prologue until now so that the prologue can take
4192 the real value of GUEST_BASE into account. */
4193 tcg_prologue_init(&tcg_ctx);
9002ec79 4194
b346ff46 4195#if defined(TARGET_I386)
3802ce26 4196 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
b98dbc90 4197 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
0514ef2f 4198 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
1bde465e
FB		 4199 env->cr[4] |= CR4_OSFXSR_MASK;
4200 env->hflags |= HF_OSFXSR_MASK;
4201 }
d2fd1af7 4202#ifndef TARGET_ABI32
4dbc422b 4203 /* enable 64 bit mode if possible */
0514ef2f 4204 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4dbc422b 4205 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4d1275c2 4206 exit(EXIT_FAILURE);
4dbc422b 4207 }
d2fd1af7 4208 env->cr[4] |= CR4_PAE_MASK;
4dbc422b 4209 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
d2fd1af7
FB		 4210 env->hflags |= HF_LMA_MASK;
4211#endif
1bde465e 4212
415e561f
FB		 4213 /* flags setup : we activate the IRQs by default as in user mode */
4214 env->eflags |= IF_MASK;
3b46e624 4215
6dbad63e 4216 /* linux register setup */
d2fd1af7 4217#ifndef TARGET_ABI32
84409ddb
JM		 4218 env->regs[R_EAX] = regs->rax;
4219 env->regs[R_EBX] = regs->rbx;
4220 env->regs[R_ECX] = regs->rcx;
4221 env->regs[R_EDX] = regs->rdx;
4222 env->regs[R_ESI] = regs->rsi;
4223 env->regs[R_EDI] = regs->rdi;
4224 env->regs[R_EBP] = regs->rbp;
4225 env->regs[R_ESP] = regs->rsp;
4226 env->eip = regs->rip;
4227#else
0ecfa993
FB		 4228 env->regs[R_EAX] = regs->eax;
4229 env->regs[R_EBX] = regs->ebx;
4230 env->regs[R_ECX] = regs->ecx;
4231 env->regs[R_EDX] = regs->edx;
4232 env->regs[R_ESI] = regs->esi;
4233 env->regs[R_EDI] = regs->edi;
4234 env->regs[R_EBP] = regs->ebp;
4235 env->regs[R_ESP] = regs->esp;
dab2ed99 4236 env->eip = regs->eip;
84409ddb 4237#endif
31e31b8a 4238
f4beb510 4239 /* linux interrupt setup */
e441570f
AZ		 4240#ifndef TARGET_ABI32
4241 env->idt.limit = 511;
4242#else
4243 env->idt.limit = 255;
4244#endif
4245 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4246 PROT_READ|PROT_WRITE,
4247 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4248 idt_table = g2h(env->idt.base);
f4beb510
FB		 4249 set_idt(0, 0);
4250 set_idt(1, 0);
4251 set_idt(2, 0);
4252 set_idt(3, 3);
4253 set_idt(4, 3);
ec95da6c 4254 set_idt(5, 0);
f4beb510
FB		 4255 set_idt(6, 0);
4256 set_idt(7, 0);
4257 set_idt(8, 0);
4258 set_idt(9, 0);
4259 set_idt(10, 0);
4260 set_idt(11, 0);
4261 set_idt(12, 0);
4262 set_idt(13, 0);
4263 set_idt(14, 0);
4264 set_idt(15, 0);
4265 set_idt(16, 0);
4266 set_idt(17, 0);
4267 set_idt(18, 0);
4268 set_idt(19, 0);
4269 set_idt(0x80, 3);
4270
6dbad63e 4271 /* linux segment setup */
8d18e893
FB		 4272 {
4273 uint64_t *gdt_table;
e441570f
AZ		 4274 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4275 PROT_READ|PROT_WRITE,
4276 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
8d18e893 4277 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
e441570f 4278 gdt_table = g2h(env->gdt.base);
d2fd1af7 4279#ifdef TARGET_ABI32
8d18e893
FB		 4280 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4281 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4282 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
d2fd1af7
FB		 4283#else
4284 /* 64 bit code segment */
4285 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4286 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4287 DESC_L_MASK |
4288 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4289#endif
8d18e893
FB		 4290 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4291 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4292 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4293 }
6dbad63e 4294 cpu_x86_load_seg(env, R_CS, __USER_CS);
d2fd1af7
FB		 4295 cpu_x86_load_seg(env, R_SS, __USER_DS);
4296#ifdef TARGET_ABI32
6dbad63e
FB		 4297 cpu_x86_load_seg(env, R_DS, __USER_DS);
4298 cpu_x86_load_seg(env, R_ES, __USER_DS);
6dbad63e
FB		 4299 cpu_x86_load_seg(env, R_FS, __USER_DS);
4300 cpu_x86_load_seg(env, R_GS, __USER_DS);
d6eb40f6
TS		 4301 /* This hack makes Wine work... */
4302 env->segs[R_FS].selector = 0;
d2fd1af7
FB		 4303#else
4304 cpu_x86_load_seg(env, R_DS, 0);
4305 cpu_x86_load_seg(env, R_ES, 0);
4306 cpu_x86_load_seg(env, R_FS, 0);
4307 cpu_x86_load_seg(env, R_GS, 0);
4308#endif
99033cae
AG		 4309#elif defined(TARGET_AARCH64)
4310 {
4311 int i;
4312
4313 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4314 fprintf(stderr,
4315 "The selected ARM CPU does not support 64 bit mode\n");
4d1275c2 4316 exit(EXIT_FAILURE);
99033cae
AG		 4317 }
4318
4319 for (i = 0; i < 31; i++) {
4320 env->xregs[i] = regs->regs[i];
4321 }
4322 env->pc = regs->pc;
4323 env->xregs[31] = regs->sp;
4324 }
b346ff46
FB		 4325#elif defined(TARGET_ARM)
4326 {
4327 int i;
ae087923
PM		 4328 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
4329 CPSRWriteByInstr);
b346ff46
FB		 4330 for(i = 0; i < 16; i++) {
4331 env->regs[i] = regs->uregs[i];
4332 }
f9fd40eb 4333#ifdef TARGET_WORDS_BIGENDIAN
d8fd2954
PB		 4334 /* Enable BE8. */
4335 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4336 && (info->elf_flags & EF_ARM_BE8)) {
9c5a7460
PC		 4337 env->uncached_cpsr |= CPSR_E;
4338 env->cp15.sctlr_el[1] |= SCTLR_E0E;
f9fd40eb
PB		 4339 } else {
4340 env->cp15.sctlr_el[1] |= SCTLR_B;
d8fd2954 4341 }
f9fd40eb 4342#endif
b346ff46 4343 }
d2fbca94
GX		 4344#elif defined(TARGET_UNICORE32)
4345 {
4346 int i;
4347 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4348 for (i = 0; i < 32; i++) {
4349 env->regs[i] = regs->uregs[i];
4350 }
4351 }
93ac68bc 4352#elif defined(TARGET_SPARC)
060366c5
FB		 4353 {
4354 int i;
4355 env->pc = regs->pc;
4356 env->npc = regs->npc;
4357 env->y = regs->y;
4358 for(i = 0; i < 8; i++)
4359 env->gregs[i] = regs->u_regs[i];
4360 for(i = 0; i < 8; i++)
4361 env->regwptr[i] = regs->u_regs[i + 8];
4362 }
67867308
FB		 4363#elif defined(TARGET_PPC)
4364 {
4365 int i;
3fc6c082 4366
0411a972 4367#if defined(TARGET_PPC64)
c8361129 4368 int flag = (env->insns_flags2 & PPC2_BOOKE206) ? MSR_CM : MSR_SF;
0411a972 4369#if defined(TARGET_ABI32)
c8361129 4370 env->msr &= ~((target_ulong)1 << flag);
e85e7c6e 4371#else
c8361129 4372 env->msr |= (target_ulong)1 << flag;
0411a972 4373#endif
84409ddb 4374#endif
67867308
FB		 4375 env->nip = regs->nip;
4376 for(i = 0; i < 32; i++) {
4377 env->gpr[i] = regs->gpr[i];
4378 }
4379 }
e6e5906b
PB		 4380#elif defined(TARGET_M68K)
4381 {
e6e5906b
PB		 4382 env->pc = regs->pc;
4383 env->dregs[0] = regs->d0;
4384 env->dregs[1] = regs->d1;
4385 env->dregs[2] = regs->d2;
4386 env->dregs[3] = regs->d3;
4387 env->dregs[4] = regs->d4;
4388 env->dregs[5] = regs->d5;
4389 env->dregs[6] = regs->d6;
4390 env->dregs[7] = regs->d7;
4391 env->aregs[0] = regs->a0;
4392 env->aregs[1] = regs->a1;
4393 env->aregs[2] = regs->a2;
4394 env->aregs[3] = regs->a3;
4395 env->aregs[4] = regs->a4;
4396 env->aregs[5] = regs->a5;
4397 env->aregs[6] = regs->a6;
4398 env->aregs[7] = regs->usp;
4399 env->sr = regs->sr;
4400 ts->sim_syscalls = 1;
4401 }
b779e29e
EI		 4402#elif defined(TARGET_MICROBLAZE)
4403 {
4404 env->regs[0] = regs->r0;
4405 env->regs[1] = regs->r1;
4406 env->regs[2] = regs->r2;
4407 env->regs[3] = regs->r3;
4408 env->regs[4] = regs->r4;
4409 env->regs[5] = regs->r5;
4410 env->regs[6] = regs->r6;
4411 env->regs[7] = regs->r7;
4412 env->regs[8] = regs->r8;
4413 env->regs[9] = regs->r9;
4414 env->regs[10] = regs->r10;
4415 env->regs[11] = regs->r11;
4416 env->regs[12] = regs->r12;
4417 env->regs[13] = regs->r13;
4418 env->regs[14] = regs->r14;
4419 env->regs[15] = regs->r15;
4420 env->regs[16] = regs->r16;
4421 env->regs[17] = regs->r17;
4422 env->regs[18] = regs->r18;
4423 env->regs[19] = regs->r19;
4424 env->regs[20] = regs->r20;
4425 env->regs[21] = regs->r21;
4426 env->regs[22] = regs->r22;
4427 env->regs[23] = regs->r23;
4428 env->regs[24] = regs->r24;
4429 env->regs[25] = regs->r25;
4430 env->regs[26] = regs->r26;
4431 env->regs[27] = regs->r27;
4432 env->regs[28] = regs->r28;
4433 env->regs[29] = regs->r29;
4434 env->regs[30] = regs->r30;
4435 env->regs[31] = regs->r31;
4436 env->sregs[SR_PC] = regs->pc;
4437 }
048f6b4d
FB		 4438#elif defined(TARGET_MIPS)
4439 {
4440 int i;
4441
4442 for(i = 0; i < 32; i++) {
b5dc7732 4443 env->active_tc.gpr[i] = regs->regs[i];
048f6b4d 4444 }
0fddbbf2
NF		 4445 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4446 if (regs->cp0_epc & 1) {
4447 env->hflags |= MIPS_HFLAG_M16;
4448 }
599bc5e8
AM		 4449 if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
4450 ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
4451 if ((env->active_fpu.fcr31_rw_bitmask &
4452 (1 << FCR31_NAN2008)) == 0) {
4453 fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n");
4454 exit(1);
4455 }
4456 if ((info->elf_flags & EF_MIPS_NAN2008) != 0) {
4457 env->active_fpu.fcr31 |= (1 << FCR31_NAN2008);
4458 } else {
4459 env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008);
4460 }
4461 restore_snan_bit_mode(env);
4462 }
048f6b4d 4463 }
d962783e
JL		 4464#elif defined(TARGET_OPENRISC)
4465 {
4466 int i;
4467
4468 for (i = 0; i < 32; i++) {
4469 env->gpr[i] = regs->gpr[i];
4470 }
4471
4472 env->sr = regs->sr;
4473 env->pc = regs->pc;
4474 }
fdf9b3e8
FB		 4475#elif defined(TARGET_SH4)
4476 {
4477 int i;
4478
4479 for(i = 0; i < 16; i++) {
4480 env->gregs[i] = regs->regs[i];
4481 }
4482 env->pc = regs->pc;
4483 }
7a3148a9
JM		 4484#elif defined(TARGET_ALPHA)
4485 {
4486 int i;
4487
4488 for(i = 0; i < 28; i++) {
992f48a0 4489 env->ir[i] = ((abi_ulong *)regs)[i];
7a3148a9 4490 }
dad081ee 4491 env->ir[IR_SP] = regs->usp;
7a3148a9 4492 env->pc = regs->pc;
7a3148a9 4493 }
48733d19
TS		 4494#elif defined(TARGET_CRIS)
4495 {
4496 env->regs[0] = regs->r0;
4497 env->regs[1] = regs->r1;
4498 env->regs[2] = regs->r2;
4499 env->regs[3] = regs->r3;
4500 env->regs[4] = regs->r4;
4501 env->regs[5] = regs->r5;
4502 env->regs[6] = regs->r6;
4503 env->regs[7] = regs->r7;
4504 env->regs[8] = regs->r8;
4505 env->regs[9] = regs->r9;
4506 env->regs[10] = regs->r10;
4507 env->regs[11] = regs->r11;
4508 env->regs[12] = regs->r12;
4509 env->regs[13] = regs->r13;
4510 env->regs[14] = info->start_stack;
4511 env->regs[15] = regs->acr;
4512 env->pc = regs->erp;
4513 }
a4c075f1
UH		 4514#elif defined(TARGET_S390X)
4515 {
4516 int i;
4517 for (i = 0; i < 16; i++) {
4518 env->regs[i] = regs->gprs[i];
4519 }
4520 env->psw.mask = regs->psw.mask;
4521 env->psw.addr = regs->psw.addr;
4522 }
b16189b2
CG		 4523#elif defined(TARGET_TILEGX)
4524 {
4525 int i;
4526 for (i = 0; i < TILEGX_R_COUNT; i++) {
4527 env->regs[i] = regs->regs[i];
4528 }
4529 for (i = 0; i < TILEGX_SPR_COUNT; i++) {
4530 env->spregs[i] = 0;
4531 }
4532 env->pc = regs->pc;
4533 }
b346ff46
FB		 4534#else
4535#error unsupported target CPU
4536#endif
31e31b8a 4537
d2fbca94 4538#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
a87295e8
PB		 4539 ts->stack_base = info->start_stack;
4540 ts->heap_base = info->brk;
4541 /* This will be filled in on the first SYS_HEAPINFO call. */
4542 ts->heap_limit = 0;
4543#endif
4544
74c33bed 4545 if (gdbstub_port) {
ff7a981a
PM		 4546 if (gdbserver_start(gdbstub_port) < 0) {
4547 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4548 gdbstub_port);
4d1275c2 4549 exit(EXIT_FAILURE);
ff7a981a 4550 }
db6b81d4 4551 gdb_handlesig(cpu, 0);
1fddef4b 4552 }
1b6b029e
FB		 4553 cpu_loop(env);
4554 /* never exits */
31e31b8a
FB		 4555 return 0;
4556}
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