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spapr_pci: Add and export DMA resetting helper
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31e31b8a 1/*
93ac68bc 2 * qemu user main
5fafdf24 3 *
68d0f70e 4 * Copyright (c) 2003-2008 Fabrice Bellard
31e31b8a
FB		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
8167ee88 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31e31b8a 18 */
d39594e9 19#include "qemu/osdep.h"
e441570f 20#include <sys/mman.h>
edf8e2af 21#include <sys/syscall.h>
703e0e89 22#include <sys/resource.h>
31e31b8a 23
3ef693a0 24#include "qemu.h"
f348b6d1
VB		 25#include "qemu/path.h"
26#include "qemu/cutils.h"
27#include "qemu/help_option.h"
2b41f10e 28#include "cpu.h"
63c91552 29#include "exec/exec-all.h"
9002ec79 30#include "tcg.h"
1de7afc9
PB		 31#include "qemu/timer.h"
32#include "qemu/envlist.h"
d8fd2954 33#include "elf.h"
508127e2 34#include "exec/log.h"
04a6dfeb 35
d088d664
AJ		 36char *exec_path;
37
1b530a6d 38int singlestep;
8cb76755
SW		 39static const char *filename;
40static const char *argv0;
41static int gdbstub_port;
42static envlist_t *envlist;
51fb256a 43static const char *cpu_model;
379f6698
PB		 44unsigned long mmap_min_addr;
45unsigned long guest_base;
46int have_guest_base;
120a9848
PB		 47
48#define EXCP_DUMP(env, fmt, ...) \
49do { \
50 CPUState *cs = ENV_GET_CPU(env); \
51 fprintf(stderr, fmt , ## __VA_ARGS__); \
52 cpu_dump_state(cs, stderr, fprintf, 0); \
53 if (qemu_log_separate()) { \
54 qemu_log(fmt, ## __VA_ARGS__); \
55 log_cpu_state(cs, 0); \
56 } \
57} while (0)
58
288e65b9
AG		 59#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
60/*
61 * When running 32-on-64 we should make sure we can fit all of the possible
62 * guest address space into a contiguous chunk of virtual host memory.
63 *
64 * This way we will never overlap with our own libraries or binaries or stack
65 * or anything else that QEMU maps.
66 */
314992b1
AG		 67# ifdef TARGET_MIPS
68/* MIPS only supports 31 bits of virtual address space for user space */
69unsigned long reserved_va = 0x77000000;
70# else
288e65b9 71unsigned long reserved_va = 0xf7000000;
314992b1 72# endif
288e65b9 73#else
68a1c816 74unsigned long reserved_va;
379f6698 75#endif
1b530a6d 76
d03f9c32 77static void usage(int exitcode);
fc9c5412 78
7ee2822c 79static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
e586822a 80const char *qemu_uname_release;
586314f2 81
9de5e440
FB		 82/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
83 we allocate a bigger stack. Need a better solution, for example
84 by remapping the process stack directly at the right place */
703e0e89 85unsigned long guest_stack_size = 8 * 1024 * 1024UL;
31e31b8a
FB		 86
87void gemu_log(const char *fmt, ...)
88{
89 va_list ap;
90
91 va_start(ap, fmt);
92 vfprintf(stderr, fmt, ap);
93 va_end(ap);
94}
95
8fcd3692 96#if defined(TARGET_I386)
05390248 97int cpu_get_pic_interrupt(CPUX86State *env)
92ccca6a
FB		 98{
99 return -1;
100}
8fcd3692 101#endif
92ccca6a 102
d5975363
PB		 103/***********************************************************/
104/* Helper routines for implementing atomic operations. */
105
106/* To implement exclusive operations we force all cpus to syncronise.
107 We don't require a full sync, only that no cpus are executing guest code.
108 The alternative is to map target atomic ops onto host equivalents,
109 which requires quite a lot of per host/target work. */
c2764719 110static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
d5975363
PB		 111static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
112static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
113static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
114static int pending_cpus;
115
116/* Make sure everything is in a consistent state for calling fork(). */
117void fork_start(void)
118{
677ef623 119 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 120 pthread_mutex_lock(&exclusive_lock);
d032d1b4 121 mmap_fork_start();
d5975363
PB		 122}
123
124void fork_end(int child)
125{
d032d1b4 126 mmap_fork_end(child);
d5975363 127 if (child) {
bdc44640 128 CPUState *cpu, *next_cpu;
d5975363
PB		 129 /* Child processes created by fork() only have a single thread.
130 Discard information about the parent threads. */
bdc44640
AF		 131 CPU_FOREACH_SAFE(cpu, next_cpu) {
132 if (cpu != thread_cpu) {
133 QTAILQ_REMOVE(&cpus, thread_cpu, node);
134 }
135 }
d5975363
PB		 136 pending_cpus = 0;
137 pthread_mutex_init(&exclusive_lock, NULL);
c2764719 138 pthread_mutex_init(&cpu_list_mutex, NULL);
d5975363
PB		 139 pthread_cond_init(&exclusive_cond, NULL);
140 pthread_cond_init(&exclusive_resume, NULL);
677ef623 141 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
f7ec7f7b 142 gdbserver_fork(thread_cpu);
d5975363
PB		 143 } else {
144 pthread_mutex_unlock(&exclusive_lock);
677ef623 145 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 146 }
d5975363
PB		 147}
148
149/* Wait for pending exclusive operations to complete. The exclusive lock
150 must be held. */
151static inline void exclusive_idle(void)
152{
153 while (pending_cpus) {
154 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
155 }
156}
157
158/* Start an exclusive operation.
159 Must only be called from outside cpu_arm_exec. */
160static inline void start_exclusive(void)
161{
0315c31c
AF		 162 CPUState *other_cpu;
163
d5975363
PB		 164 pthread_mutex_lock(&exclusive_lock);
165 exclusive_idle();
166
167 pending_cpus = 1;
168 /* Make all other cpus stop executing. */
bdc44640 169 CPU_FOREACH(other_cpu) {
0315c31c 170 if (other_cpu->running) {
d5975363 171 pending_cpus++;
60a3e17a 172 cpu_exit(other_cpu);
d5975363
PB		 173 }
174 }
175 if (pending_cpus > 1) {
176 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
177 }
178}
179
180/* Finish an exclusive operation. */
f7e61b22 181static inline void __attribute__((unused)) end_exclusive(void)
d5975363
PB		 182{
183 pending_cpus = 0;
184 pthread_cond_broadcast(&exclusive_resume);
185 pthread_mutex_unlock(&exclusive_lock);
186}
187
188/* Wait for exclusive ops to finish, and begin cpu execution. */
0315c31c 189static inline void cpu_exec_start(CPUState *cpu)
d5975363
PB		 190{
191 pthread_mutex_lock(&exclusive_lock);
192 exclusive_idle();
0315c31c 193 cpu->running = true;
d5975363
PB		 194 pthread_mutex_unlock(&exclusive_lock);
195}
196
197/* Mark cpu as not executing, and release pending exclusive ops. */
0315c31c 198static inline void cpu_exec_end(CPUState *cpu)
d5975363
PB		 199{
200 pthread_mutex_lock(&exclusive_lock);
0315c31c 201 cpu->running = false;
d5975363
PB		 202 if (pending_cpus > 1) {
203 pending_cpus--;
204 if (pending_cpus == 1) {
205 pthread_cond_signal(&exclusive_cond);
206 }
207 }
208 exclusive_idle();
209 pthread_mutex_unlock(&exclusive_lock);
210}
c2764719
PB		 211
212void cpu_list_lock(void)
213{
214 pthread_mutex_lock(&cpu_list_mutex);
215}
216
217void cpu_list_unlock(void)
218{
219 pthread_mutex_unlock(&cpu_list_mutex);
220}
d5975363
PB		 221
222
a541f297
FB		 223#ifdef TARGET_I386
224/***********************************************************/
225/* CPUX86 core interface */
226
28ab0e2e
FB		 227uint64_t cpu_get_tsc(CPUX86State *env)
228{
4a7428c5 229 return cpu_get_host_ticks();
28ab0e2e
FB		 230}
231
5fafdf24 232static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
f4beb510 233 int flags)
6dbad63e 234{
f4beb510 235 unsigned int e1, e2;
53a5960a 236 uint32_t *p;
6dbad63e
FB		 237 e1 = (addr << 16) | (limit & 0xffff);
238 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
f4beb510 239 e2 |= flags;
53a5960a 240 p = ptr;
d538e8f5 241 p[0] = tswap32(e1);
242 p[1] = tswap32(e2);
f4beb510
FB		 243}
244
e441570f 245static uint64_t *idt_table;
eb38c52c 246#ifdef TARGET_X86_64
d2fd1af7
FB		 247static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
248 uint64_t addr, unsigned int sel)
f4beb510 249{
4dbc422b 250 uint32_t *p, e1, e2;
f4beb510
FB		 251 e1 = (addr & 0xffff) | (sel << 16);
252 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
53a5960a 253 p = ptr;
4dbc422b
FB		 254 p[0] = tswap32(e1);
255 p[1] = tswap32(e2);
256 p[2] = tswap32(addr >> 32);
257 p[3] = 0;
6dbad63e 258}
d2fd1af7
FB		 259/* only dpl matters as we do only user space emulation */
260static void set_idt(int n, unsigned int dpl)
261{
262 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
263}
264#else
d2fd1af7
FB		 265static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
266 uint32_t addr, unsigned int sel)
267{
4dbc422b 268 uint32_t *p, e1, e2;
d2fd1af7
FB		 269 e1 = (addr & 0xffff) | (sel << 16);
270 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
271 p = ptr;
4dbc422b
FB		 272 p[0] = tswap32(e1);
273 p[1] = tswap32(e2);
d2fd1af7
FB		 274}
275
f4beb510
FB		 276/* only dpl matters as we do only user space emulation */
277static void set_idt(int n, unsigned int dpl)
278{
279 set_gate(idt_table + n, 0, dpl, 0, 0);
280}
d2fd1af7 281#endif
31e31b8a 282
89e957e7 283void cpu_loop(CPUX86State *env)
1b6b029e 284{
db6b81d4 285 CPUState *cs = CPU(x86_env_get_cpu(env));
bc8a22cc 286 int trapnr;
992f48a0 287 abi_ulong pc;
0284b03b 288 abi_ulong ret;
c227f099 289 target_siginfo_t info;
851e67a1 290
1b6b029e 291 for(;;) {
b040bc9c 292 cpu_exec_start(cs);
ea3e9847 293 trapnr = cpu_x86_exec(cs);
b040bc9c 294 cpu_exec_end(cs);
bc8a22cc 295 switch(trapnr) {
f4beb510 296 case 0x80:
d2fd1af7 297 /* linux syscall from int $0x80 */
0284b03b
TB		 298 ret = do_syscall(env,
299 env->regs[R_EAX],
300 env->regs[R_EBX],
301 env->regs[R_ECX],
302 env->regs[R_EDX],
303 env->regs[R_ESI],
304 env->regs[R_EDI],
305 env->regs[R_EBP],
306 0, 0);
307 if (ret == -TARGET_ERESTARTSYS) {
308 env->eip -= 2;
309 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
310 env->regs[R_EAX] = ret;
311 }
f4beb510 312 break;
d2fd1af7
FB		 313#ifndef TARGET_ABI32
314 case EXCP_SYSCALL:
5ba18547 315 /* linux syscall from syscall instruction */
0284b03b
TB		 316 ret = do_syscall(env,
317 env->regs[R_EAX],
318 env->regs[R_EDI],
319 env->regs[R_ESI],
320 env->regs[R_EDX],
321 env->regs[10],
322 env->regs[8],
323 env->regs[9],
324 0, 0);
325 if (ret == -TARGET_ERESTARTSYS) {
326 env->eip -= 2;
327 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
328 env->regs[R_EAX] = ret;
329 }
d2fd1af7
FB		 330 break;
331#endif
f4beb510
FB		 332 case EXCP0B_NOSEG:
333 case EXCP0C_STACK:
a86b3c64 334 info.si_signo = TARGET_SIGBUS;
f4beb510
FB		 335 info.si_errno = 0;
336 info.si_code = TARGET_SI_KERNEL;
337 info._sifields._sigfault._addr = 0;
624f7979 338 queue_signal(env, info.si_signo, &info);
f4beb510 339 break;
1b6b029e 340 case EXCP0D_GPF:
d2fd1af7 341 /* XXX: potential problem if ABI32 */
84409ddb 342#ifndef TARGET_X86_64
851e67a1 343 if (env->eflags & VM_MASK) {
89e957e7 344 handle_vm86_fault(env);
84409ddb
JM		 345 } else
346#endif
347 {
a86b3c64 348 info.si_signo = TARGET_SIGSEGV;
f4beb510
FB		 349 info.si_errno = 0;
350 info.si_code = TARGET_SI_KERNEL;
351 info._sifields._sigfault._addr = 0;
624f7979 352 queue_signal(env, info.si_signo, &info);
1b6b029e
FB		 353 }
354 break;
b689bc57 355 case EXCP0E_PAGE:
a86b3c64 356 info.si_signo = TARGET_SIGSEGV;
b689bc57
FB		 357 info.si_errno = 0;
358 if (!(env->error_code & 1))
359 info.si_code = TARGET_SEGV_MAPERR;
360 else
361 info.si_code = TARGET_SEGV_ACCERR;
970a87a6 362 info._sifields._sigfault._addr = env->cr[2];
624f7979 363 queue_signal(env, info.si_signo, &info);
b689bc57 364 break;
9de5e440 365 case EXCP00_DIVZ:
84409ddb 366#ifndef TARGET_X86_64
bc8a22cc 367 if (env->eflags & VM_MASK) {
447db213 368 handle_vm86_trap(env, trapnr);
84409ddb
JM		 369 } else
370#endif
371 {
bc8a22cc 372 /* division by zero */
a86b3c64 373 info.si_signo = TARGET_SIGFPE;
bc8a22cc
FB		 374 info.si_errno = 0;
375 info.si_code = TARGET_FPE_INTDIV;
376 info._sifields._sigfault._addr = env->eip;
624f7979 377 queue_signal(env, info.si_signo, &info);
bc8a22cc 378 }
9de5e440 379 break;
01df040b 380 case EXCP01_DB:
447db213 381 case EXCP03_INT3:
84409ddb 382#ifndef TARGET_X86_64
447db213
FB		 383 if (env->eflags & VM_MASK) {
384 handle_vm86_trap(env, trapnr);
84409ddb
JM		 385 } else
386#endif
387 {
a86b3c64 388 info.si_signo = TARGET_SIGTRAP;
447db213 389 info.si_errno = 0;
01df040b 390 if (trapnr == EXCP01_DB) {
447db213
FB		 391 info.si_code = TARGET_TRAP_BRKPT;
392 info._sifields._sigfault._addr = env->eip;
393 } else {
394 info.si_code = TARGET_SI_KERNEL;
395 info._sifields._sigfault._addr = 0;
396 }
624f7979 397 queue_signal(env, info.si_signo, &info);
447db213
FB		 398 }
399 break;
9de5e440
FB		 400 case EXCP04_INTO:
401 case EXCP05_BOUND:
84409ddb 402#ifndef TARGET_X86_64
bc8a22cc 403 if (env->eflags & VM_MASK) {
447db213 404 handle_vm86_trap(env, trapnr);
84409ddb
JM		 405 } else
406#endif
407 {
a86b3c64 408 info.si_signo = TARGET_SIGSEGV;
bc8a22cc 409 info.si_errno = 0;
b689bc57 410 info.si_code = TARGET_SI_KERNEL;
bc8a22cc 411 info._sifields._sigfault._addr = 0;
624f7979 412 queue_signal(env, info.si_signo, &info);
bc8a22cc 413 }
9de5e440
FB		 414 break;
415 case EXCP06_ILLOP:
a86b3c64 416 info.si_signo = TARGET_SIGILL;
9de5e440
FB		 417 info.si_errno = 0;
418 info.si_code = TARGET_ILL_ILLOPN;
419 info._sifields._sigfault._addr = env->eip;
624f7979 420 queue_signal(env, info.si_signo, &info);
9de5e440
FB		 421 break;
422 case EXCP_INTERRUPT:
423 /* just indicate that signals should be handled asap */
424 break;
1fddef4b
FB		 425 case EXCP_DEBUG:
426 {
427 int sig;
428
db6b81d4 429 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 430 if (sig)
431 {
432 info.si_signo = sig;
433 info.si_errno = 0;
434 info.si_code = TARGET_TRAP_BRKPT;
624f7979 435 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 436 }
437 }
438 break;
1b6b029e 439 default:
970a87a6 440 pc = env->segs[R_CS].base + env->eip;
120a9848
PB		 441 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
442 (long)pc, trapnr);
1b6b029e
FB		 443 abort();
444 }
66fb9763 445 process_pending_signals(env);
1b6b029e
FB		 446 }
447}
b346ff46
FB		 448#endif
449
450#ifdef TARGET_ARM
451
49017bd8 452#define get_user_code_u32(x, gaddr, env) \
d8fd2954 453 ({ abi_long __r = get_user_u32((x), (gaddr)); \
f9fd40eb 454 if (!__r && bswap_code(arm_sctlr_b(env))) { \
d8fd2954
PB		 455 (x) = bswap32(x); \
456 } \
457 __r; \
458 })
459
49017bd8 460#define get_user_code_u16(x, gaddr, env) \
d8fd2954 461 ({ abi_long __r = get_user_u16((x), (gaddr)); \
f9fd40eb 462 if (!__r && bswap_code(arm_sctlr_b(env))) { \
d8fd2954
PB		 463 (x) = bswap16(x); \
464 } \
465 __r; \
466 })
467
c3ae85fc
PB		 468#define get_user_data_u32(x, gaddr, env) \
469 ({ abi_long __r = get_user_u32((x), (gaddr)); \
470 if (!__r && arm_cpu_bswap_data(env)) { \
471 (x) = bswap32(x); \
472 } \
473 __r; \
474 })
475
476#define get_user_data_u16(x, gaddr, env) \
477 ({ abi_long __r = get_user_u16((x), (gaddr)); \
478 if (!__r && arm_cpu_bswap_data(env)) { \
479 (x) = bswap16(x); \
480 } \
481 __r; \
482 })
483
484#define put_user_data_u32(x, gaddr, env) \
485 ({ typeof(x) __x = (x); \
486 if (arm_cpu_bswap_data(env)) { \
487 __x = bswap32(__x); \
488 } \
489 put_user_u32(__x, (gaddr)); \
490 })
491
492#define put_user_data_u16(x, gaddr, env) \
493 ({ typeof(x) __x = (x); \
494 if (arm_cpu_bswap_data(env)) { \
495 __x = bswap16(__x); \
496 } \
497 put_user_u16(__x, (gaddr)); \
498 })
499
1861c454
PM		 500#ifdef TARGET_ABI32
501/* Commpage handling -- there is no commpage for AArch64 */
502
97cc7560
DDAG		 503/*
504 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
505 * Input:
506 * r0 = pointer to oldval
507 * r1 = pointer to newval
508 * r2 = pointer to target value
509 *
510 * Output:
511 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
512 * C set if *ptr was changed, clear if no exchange happened
513 *
514 * Note segv's in kernel helpers are a bit tricky, we can set the
515 * data address sensibly but the PC address is just the entry point.
516 */
517static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
518{
519 uint64_t oldval, newval, val;
520 uint32_t addr, cpsr;
521 target_siginfo_t info;
522
523 /* Based on the 32 bit code in do_kernel_trap */
524
525 /* XXX: This only works between threads, not between processes.
526 It's probably possible to implement this with native host
527 operations. However things like ldrex/strex are much harder so
528 there's not much point trying. */
529 start_exclusive();
530 cpsr = cpsr_read(env);
531 addr = env->regs[2];
532
533 if (get_user_u64(oldval, env->regs[0])) {
abf1172f 534 env->exception.vaddress = env->regs[0];
97cc7560
DDAG		 535 goto segv;
536 };
537
538 if (get_user_u64(newval, env->regs[1])) {
abf1172f 539 env->exception.vaddress = env->regs[1];
97cc7560
DDAG		 540 goto segv;
541 };
542
543 if (get_user_u64(val, addr)) {
abf1172f 544 env->exception.vaddress = addr;
97cc7560
DDAG		 545 goto segv;
546 }
547
548 if (val == oldval) {
549 val = newval;
550
551 if (put_user_u64(val, addr)) {
abf1172f 552 env->exception.vaddress = addr;
97cc7560
DDAG		 553 goto segv;
554 };
555
556 env->regs[0] = 0;
557 cpsr |= CPSR_C;
558 } else {
559 env->regs[0] = -1;
560 cpsr &= ~CPSR_C;
561 }
50866ba5 562 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
97cc7560
DDAG		 563 end_exclusive();
564 return;
565
566segv:
567 end_exclusive();
568 /* We get the PC of the entry address - which is as good as anything,
569 on a real kernel what you get depends on which mode it uses. */
a86b3c64 570 info.si_signo = TARGET_SIGSEGV;
97cc7560
DDAG		 571 info.si_errno = 0;
572 /* XXX: check env->error_code */
573 info.si_code = TARGET_SEGV_MAPERR;
abf1172f 574 info._sifields._sigfault._addr = env->exception.vaddress;
97cc7560 575 queue_signal(env, info.si_signo, &info);
97cc7560
DDAG		 576}
577
fbb4a2e3
PB		 578/* Handle a jump to the kernel code page. */
579static int
580do_kernel_trap(CPUARMState *env)
581{
582 uint32_t addr;
583 uint32_t cpsr;
584 uint32_t val;
585
586 switch (env->regs[15]) {
587 case 0xffff0fa0: /* __kernel_memory_barrier */
588 /* ??? No-op. Will need to do better for SMP. */
589 break;
590 case 0xffff0fc0: /* __kernel_cmpxchg */
d5975363
PB		 591 /* XXX: This only works between threads, not between processes.
592 It's probably possible to implement this with native host
593 operations. However things like ldrex/strex are much harder so
594 there's not much point trying. */
595 start_exclusive();
fbb4a2e3
PB		 596 cpsr = cpsr_read(env);
597 addr = env->regs[2];
598 /* FIXME: This should SEGV if the access fails. */
599 if (get_user_u32(val, addr))
600 val = ~env->regs[0];
601 if (val == env->regs[0]) {
602 val = env->regs[1];
603 /* FIXME: Check for segfaults. */
604 put_user_u32(val, addr);
605 env->regs[0] = 0;
606 cpsr |= CPSR_C;
607 } else {
608 env->regs[0] = -1;
609 cpsr &= ~CPSR_C;
610 }
50866ba5 611 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
d5975363 612 end_exclusive();
fbb4a2e3
PB		 613 break;
614 case 0xffff0fe0: /* __kernel_get_tls */
b8d43285 615 env->regs[0] = cpu_get_tls(env);
fbb4a2e3 616 break;
97cc7560
DDAG		 617 case 0xffff0f60: /* __kernel_cmpxchg64 */
618 arm_kernel_cmpxchg64_helper(env);
619 break;
620
fbb4a2e3
PB		 621 default:
622 return 1;
623 }
624 /* Jump back to the caller. */
625 addr = env->regs[14];
626 if (addr & 1) {
627 env->thumb = 1;
628 addr &= ~1;
629 }
630 env->regs[15] = addr;
631
632 return 0;
633}
634
fa2ef212 635/* Store exclusive handling for AArch32 */
426f5abc
PB		 636static int do_strex(CPUARMState *env)
637{
03d05e2d 638 uint64_t val;
426f5abc
PB		 639 int size;
640 int rc = 1;
641 int segv = 0;
642 uint32_t addr;
643 start_exclusive();
03d05e2d 644 if (env->exclusive_addr != env->exclusive_test) {
426f5abc
PB		 645 goto fail;
646 }
03d05e2d
PM		 647 /* We know we're always AArch32 so the address is in uint32_t range
648 * unless it was the -1 exclusive-monitor-lost value (which won't
649 * match exclusive_test above).
650 */
651 assert(extract64(env->exclusive_addr, 32, 32) == 0);
652 addr = env->exclusive_addr;
426f5abc
PB		 653 size = env->exclusive_info & 0xf;
654 switch (size) {
655 case 0:
656 segv = get_user_u8(val, addr);
657 break;
658 case 1:
c3ae85fc 659 segv = get_user_data_u16(val, addr, env);
426f5abc
PB		 660 break;
661 case 2:
662 case 3:
c3ae85fc 663 segv = get_user_data_u32(val, addr, env);
426f5abc 664 break;
f7001a3b
AJ		 665 default:
666 abort();
426f5abc
PB		 667 }
668 if (segv) {
abf1172f 669 env->exception.vaddress = addr;
426f5abc
PB		 670 goto done;
671 }
426f5abc 672 if (size == 3) {
03d05e2d 673 uint32_t valhi;
c3ae85fc 674 segv = get_user_data_u32(valhi, addr + 4, env);
426f5abc 675 if (segv) {
abf1172f 676 env->exception.vaddress = addr + 4;
426f5abc
PB		 677 goto done;
678 }
c3ae85fc
PB		 679 if (arm_cpu_bswap_data(env)) {
680 val = deposit64((uint64_t)valhi, 32, 32, val);
681 } else {
682 val = deposit64(val, 32, 32, valhi);
683 }
426f5abc 684 }
03d05e2d
PM		 685 if (val != env->exclusive_val) {
686 goto fail;
687 }
688
426f5abc
PB		 689 val = env->regs[(env->exclusive_info >> 8) & 0xf];
690 switch (size) {
691 case 0:
692 segv = put_user_u8(val, addr);
693 break;
694 case 1:
c3ae85fc 695 segv = put_user_data_u16(val, addr, env);
426f5abc
PB		 696 break;
697 case 2:
698 case 3:
c3ae85fc 699 segv = put_user_data_u32(val, addr, env);
426f5abc
PB		 700 break;
701 }
702 if (segv) {
abf1172f 703 env->exception.vaddress = addr;
426f5abc
PB		 704 goto done;
705 }
706 if (size == 3) {
707 val = env->regs[(env->exclusive_info >> 12) & 0xf];
c3ae85fc 708 segv = put_user_data_u32(val, addr + 4, env);
426f5abc 709 if (segv) {
abf1172f 710 env->exception.vaddress = addr + 4;
426f5abc
PB		 711 goto done;
712 }
713 }
714 rc = 0;
715fail:
725b8a69 716 env->regs[15] += 4;
426f5abc
PB		 717 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
718done:
719 end_exclusive();
720 return segv;
721}
722
b346ff46
FB		 723void cpu_loop(CPUARMState *env)
724{
0315c31c 725 CPUState *cs = CPU(arm_env_get_cpu(env));
b346ff46
FB		 726 int trapnr;
727 unsigned int n, insn;
c227f099 728 target_siginfo_t info;
b5ff1b31 729 uint32_t addr;
f0267ef7 730 abi_ulong ret;
3b46e624 731
b346ff46 732 for(;;) {
0315c31c 733 cpu_exec_start(cs);
ea3e9847 734 trapnr = cpu_arm_exec(cs);
0315c31c 735 cpu_exec_end(cs);
b346ff46
FB		 736 switch(trapnr) {
737 case EXCP_UDEF:
c6981055 738 {
0429a971 739 TaskState *ts = cs->opaque;
c6981055 740 uint32_t opcode;
6d9a42be 741 int rc;
c6981055
FB		 742
743 /* we handle the FPU emulation here, as Linux */
744 /* we get the opcode */
2f619698 745 /* FIXME - what to do if get_user() fails? */
49017bd8 746 get_user_code_u32(opcode, env->regs[15], env);
3b46e624 747
6d9a42be
AJ		 748 rc = EmulateAll(opcode, &ts->fpa, env);
749 if (rc == 0) { /* illegal instruction */
a86b3c64 750 info.si_signo = TARGET_SIGILL;
c6981055
FB		 751 info.si_errno = 0;
752 info.si_code = TARGET_ILL_ILLOPN;
753 info._sifields._sigfault._addr = env->regs[15];
624f7979 754 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 755 } else if (rc < 0) { /* FP exception */
756 int arm_fpe=0;
757
758 /* translate softfloat flags to FPSR flags */
759 if (-rc & float_flag_invalid)
760 arm_fpe |= BIT_IOC;
761 if (-rc & float_flag_divbyzero)
762 arm_fpe |= BIT_DZC;
763 if (-rc & float_flag_overflow)
764 arm_fpe |= BIT_OFC;
765 if (-rc & float_flag_underflow)
766 arm_fpe |= BIT_UFC;
767 if (-rc & float_flag_inexact)
768 arm_fpe |= BIT_IXC;
769
770 FPSR fpsr = ts->fpa.fpsr;
771 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
772
773 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
a86b3c64 774 info.si_signo = TARGET_SIGFPE;
6d9a42be
AJ		 775 info.si_errno = 0;
776
777 /* ordered by priority, least first */
778 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
779 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
780 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
781 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
782 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
783
784 info._sifields._sigfault._addr = env->regs[15];
624f7979 785 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 786 } else {
787 env->regs[15] += 4;
788 }
789
790 /* accumulate unenabled exceptions */
791 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
792 fpsr |= BIT_IXC;
793 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
794 fpsr |= BIT_UFC;
795 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
796 fpsr |= BIT_OFC;
797 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
798 fpsr |= BIT_DZC;
799 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
800 fpsr |= BIT_IOC;
801 ts->fpa.fpsr=fpsr;
802 } else { /* everything OK */
c6981055
FB		 803 /* increment PC */
804 env->regs[15] += 4;
805 }
806 }
b346ff46
FB		 807 break;
808 case EXCP_SWI:
06c949e6 809 case EXCP_BKPT:
b346ff46 810 {
ce4defa0 811 env->eabi = 1;
b346ff46 812 /* system call */
06c949e6
PB		 813 if (trapnr == EXCP_BKPT) {
814 if (env->thumb) {
2f619698 815 /* FIXME - what to do if get_user() fails? */
49017bd8 816 get_user_code_u16(insn, env->regs[15], env);
06c949e6
PB		 817 n = insn & 0xff;
818 env->regs[15] += 2;
819 } else {
2f619698 820 /* FIXME - what to do if get_user() fails? */
49017bd8 821 get_user_code_u32(insn, env->regs[15], env);
06c949e6
PB		 822 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
823 env->regs[15] += 4;
824 }
192c7bd9 825 } else {
06c949e6 826 if (env->thumb) {
2f619698 827 /* FIXME - what to do if get_user() fails? */
49017bd8 828 get_user_code_u16(insn, env->regs[15] - 2, env);
06c949e6
PB		 829 n = insn & 0xff;
830 } else {
2f619698 831 /* FIXME - what to do if get_user() fails? */
49017bd8 832 get_user_code_u32(insn, env->regs[15] - 4, env);
06c949e6
PB		 833 n = insn & 0xffffff;
834 }
192c7bd9
FB		 835 }
836
6f1f31c0 837 if (n == ARM_NR_cacheflush) {
dcfd14b3 838 /* nop */
a4f81979
FB		 839 } else if (n == ARM_NR_semihosting
840 || n == ARM_NR_thumb_semihosting) {
841 env->regs[0] = do_arm_semihosting (env);
3a1363ac 842 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
b346ff46 843 /* linux syscall */
ce4defa0 844 if (env->thumb || n == 0) {
192c7bd9
FB		 845 n = env->regs[7];
846 } else {
847 n -= ARM_SYSCALL_BASE;
ce4defa0 848 env->eabi = 0;
192c7bd9 849 }
fbb4a2e3
PB		 850 if ( n > ARM_NR_BASE) {
851 switch (n) {
852 case ARM_NR_cacheflush:
dcfd14b3 853 /* nop */
fbb4a2e3
PB		 854 break;
855 case ARM_NR_set_tls:
856 cpu_set_tls(env, env->regs[0]);
857 env->regs[0] = 0;
858 break;
d5355087
HL		 859 case ARM_NR_breakpoint:
860 env->regs[15] -= env->thumb ? 2 : 4;
861 goto excp_debug;
fbb4a2e3
PB		 862 default:
863 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
864 n);
865 env->regs[0] = -TARGET_ENOSYS;
866 break;
867 }
868 } else {
f0267ef7
TB		 869 ret = do_syscall(env,
870 n,
871 env->regs[0],
872 env->regs[1],
873 env->regs[2],
874 env->regs[3],
875 env->regs[4],
876 env->regs[5],
877 0, 0);
878 if (ret == -TARGET_ERESTARTSYS) {
879 env->regs[15] -= env->thumb ? 2 : 4;
880 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
881 env->regs[0] = ret;
882 }
fbb4a2e3 883 }
b346ff46
FB		 884 } else {
885 goto error;
886 }
887 }
888 break;
43fff238
FB		 889 case EXCP_INTERRUPT:
890 /* just indicate that signals should be handled asap */
891 break;
abf1172f
PM		 892 case EXCP_STREX:
893 if (!do_strex(env)) {
894 break;
895 }
896 /* fall through for segv */
68016c62
FB		 897 case EXCP_PREFETCH_ABORT:
898 case EXCP_DATA_ABORT:
abf1172f 899 addr = env->exception.vaddress;
68016c62 900 {
a86b3c64 901 info.si_signo = TARGET_SIGSEGV;
68016c62
FB		 902 info.si_errno = 0;
903 /* XXX: check env->error_code */
904 info.si_code = TARGET_SEGV_MAPERR;
b5ff1b31 905 info._sifields._sigfault._addr = addr;
624f7979 906 queue_signal(env, info.si_signo, &info);
68016c62
FB		 907 }
908 break;
1fddef4b 909 case EXCP_DEBUG:
d5355087 910 excp_debug:
1fddef4b
FB		 911 {
912 int sig;
913
db6b81d4 914 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 915 if (sig)
916 {
917 info.si_signo = sig;
918 info.si_errno = 0;
919 info.si_code = TARGET_TRAP_BRKPT;
624f7979 920 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 921 }
922 }
923 break;
fbb4a2e3
PB		 924 case EXCP_KERNEL_TRAP:
925 if (do_kernel_trap(env))
926 goto error;
927 break;
f911e0a3
PM		 928 case EXCP_YIELD:
929 /* nothing to do here for user-mode, just resume guest code */
930 break;
b346ff46
FB		 931 default:
932 error:
120a9848 933 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
b346ff46
FB		 934 abort();
935 }
936 process_pending_signals(env);
937 }
938}
939
1861c454
PM		 940#else
941
fa2ef212
MM		 942/*
943 * Handle AArch64 store-release exclusive
944 *
945 * rs = gets the status result of store exclusive
946 * rt = is the register that is stored
947 * rt2 = is the second register store (in STP)
948 *
949 */
950static int do_strex_a64(CPUARMState *env)
951{
952 uint64_t val;
953 int size;
954 bool is_pair;
955 int rc = 1;
956 int segv = 0;
957 uint64_t addr;
958 int rs, rt, rt2;
959
960 start_exclusive();
961 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
962 size = extract32(env->exclusive_info, 0, 2);
963 is_pair = extract32(env->exclusive_info, 2, 1);
964 rs = extract32(env->exclusive_info, 4, 5);
965 rt = extract32(env->exclusive_info, 9, 5);
966 rt2 = extract32(env->exclusive_info, 14, 5);
967
968 addr = env->exclusive_addr;
969
970 if (addr != env->exclusive_test) {
971 goto finish;
972 }
973
974 switch (size) {
975 case 0:
976 segv = get_user_u8(val, addr);
977 break;
978 case 1:
979 segv = get_user_u16(val, addr);
980 break;
981 case 2:
982 segv = get_user_u32(val, addr);
983 break;
984 case 3:
985 segv = get_user_u64(val, addr);
986 break;
987 default:
988 abort();
989 }
990 if (segv) {
abf1172f 991 env->exception.vaddress = addr;
fa2ef212
MM		 992 goto error;
993 }
994 if (val != env->exclusive_val) {
995 goto finish;
996 }
997 if (is_pair) {
998 if (size == 2) {
999 segv = get_user_u32(val, addr + 4);
1000 } else {
1001 segv = get_user_u64(val, addr + 8);
1002 }
1003 if (segv) {
abf1172f 1004 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 1005 goto error;
1006 }
1007 if (val != env->exclusive_high) {
1008 goto finish;
1009 }
1010 }
2ea5a2ca
JG		 1011 /* handle the zero register */
1012 val = rt == 31 ? 0 : env->xregs[rt];
fa2ef212
MM		 1013 switch (size) {
1014 case 0:
1015 segv = put_user_u8(val, addr);
1016 break;
1017 case 1:
1018 segv = put_user_u16(val, addr);
1019 break;
1020 case 2:
1021 segv = put_user_u32(val, addr);
1022 break;
1023 case 3:
1024 segv = put_user_u64(val, addr);
1025 break;
1026 }
1027 if (segv) {
1028 goto error;
1029 }
1030 if (is_pair) {
2ea5a2ca
JG		 1031 /* handle the zero register */
1032 val = rt2 == 31 ? 0 : env->xregs[rt2];
fa2ef212
MM		 1033 if (size == 2) {
1034 segv = put_user_u32(val, addr + 4);
1035 } else {
1036 segv = put_user_u64(val, addr + 8);
1037 }
1038 if (segv) {
abf1172f 1039 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 1040 goto error;
1041 }
1042 }
1043 rc = 0;
1044finish:
1045 env->pc += 4;
1046 /* rs == 31 encodes a write to the ZR, thus throwing away
1047 * the status return. This is rather silly but valid.
1048 */
1049 if (rs < 31) {
1050 env->xregs[rs] = rc;
1051 }
1052error:
1053 /* instruction faulted, PC does not advance */
1054 /* either way a strex releases any exclusive lock we have */
1055 env->exclusive_addr = -1;
1056 end_exclusive();
1057 return segv;
1058}
1059
1861c454
PM		 1060/* AArch64 main loop */
1061void cpu_loop(CPUARMState *env)
1062{
1063 CPUState *cs = CPU(arm_env_get_cpu(env));
1064 int trapnr, sig;
f0267ef7 1065 abi_long ret;
1861c454 1066 target_siginfo_t info;
1861c454
PM		 1067
1068 for (;;) {
1069 cpu_exec_start(cs);
ea3e9847 1070 trapnr = cpu_arm_exec(cs);
1861c454
PM		 1071 cpu_exec_end(cs);
1072
1073 switch (trapnr) {
1074 case EXCP_SWI:
f0267ef7
TB		 1075 ret = do_syscall(env,
1076 env->xregs[8],
1077 env->xregs[0],
1078 env->xregs[1],
1079 env->xregs[2],
1080 env->xregs[3],
1081 env->xregs[4],
1082 env->xregs[5],
1083 0, 0);
1084 if (ret == -TARGET_ERESTARTSYS) {
1085 env->pc -= 4;
1086 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
1087 env->xregs[0] = ret;
1088 }
1861c454
PM		 1089 break;
1090 case EXCP_INTERRUPT:
1091 /* just indicate that signals should be handled asap */
1092 break;
1093 case EXCP_UDEF:
a86b3c64 1094 info.si_signo = TARGET_SIGILL;
1861c454
PM		 1095 info.si_errno = 0;
1096 info.si_code = TARGET_ILL_ILLOPN;
1097 info._sifields._sigfault._addr = env->pc;
1098 queue_signal(env, info.si_signo, &info);
1099 break;
abf1172f
PM		 1100 case EXCP_STREX:
1101 if (!do_strex_a64(env)) {
1102 break;
1103 }
1104 /* fall through for segv */
1861c454 1105 case EXCP_PREFETCH_ABORT:
1861c454 1106 case EXCP_DATA_ABORT:
a86b3c64 1107 info.si_signo = TARGET_SIGSEGV;
1861c454
PM		 1108 info.si_errno = 0;
1109 /* XXX: check env->error_code */
1110 info.si_code = TARGET_SEGV_MAPERR;
686581ad 1111 info._sifields._sigfault._addr = env->exception.vaddress;
1861c454
PM		 1112 queue_signal(env, info.si_signo, &info);
1113 break;
1114 case EXCP_DEBUG:
1115 case EXCP_BKPT:
1116 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1117 if (sig) {
1118 info.si_signo = sig;
1119 info.si_errno = 0;
1120 info.si_code = TARGET_TRAP_BRKPT;
1121 queue_signal(env, info.si_signo, &info);
1122 }
1123 break;
8012c84f
PM		 1124 case EXCP_SEMIHOST:
1125 env->xregs[0] = do_arm_semihosting(env);
1126 break;
f911e0a3
PM		 1127 case EXCP_YIELD:
1128 /* nothing to do here for user-mode, just resume guest code */
1129 break;
1861c454 1130 default:
120a9848 1131 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1861c454
PM		 1132 abort();
1133 }
1134 process_pending_signals(env);
fa2ef212
MM		 1135 /* Exception return on AArch64 always clears the exclusive monitor,
1136 * so any return to running guest code implies this.
1137 * A strex (successful or otherwise) also clears the monitor, so
1138 * we don't need to specialcase EXCP_STREX.
1139 */
1140 env->exclusive_addr = -1;
1861c454
PM		 1141 }
1142}
1143#endif /* ndef TARGET_ABI32 */
1144
b346ff46 1145#endif
1b6b029e 1146
d2fbca94
GX		 1147#ifdef TARGET_UNICORE32
1148
05390248 1149void cpu_loop(CPUUniCore32State *env)
d2fbca94 1150{
0315c31c 1151 CPUState *cs = CPU(uc32_env_get_cpu(env));
d2fbca94
GX		 1152 int trapnr;
1153 unsigned int n, insn;
1154 target_siginfo_t info;
1155
1156 for (;;) {
0315c31c 1157 cpu_exec_start(cs);
ea3e9847 1158 trapnr = uc32_cpu_exec(cs);
0315c31c 1159 cpu_exec_end(cs);
d2fbca94
GX		 1160 switch (trapnr) {
1161 case UC32_EXCP_PRIV:
1162 {
1163 /* system call */
1164 get_user_u32(insn, env->regs[31] - 4);
1165 n = insn & 0xffffff;
1166
1167 if (n >= UC32_SYSCALL_BASE) {
1168 /* linux syscall */
1169 n -= UC32_SYSCALL_BASE;
1170 if (n == UC32_SYSCALL_NR_set_tls) {
1171 cpu_set_tls(env, env->regs[0]);
1172 env->regs[0] = 0;
1173 } else {
256cb6af 1174 abi_long ret = do_syscall(env,
d2fbca94
GX		 1175 n,
1176 env->regs[0],
1177 env->regs[1],
1178 env->regs[2],
1179 env->regs[3],
1180 env->regs[4],
5945cfcb
PM		 1181 env->regs[5],
1182 0, 0);
256cb6af
TB		 1183 if (ret == -TARGET_ERESTARTSYS) {
1184 env->regs[31] -= 4;
1185 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
1186 env->regs[0] = ret;
1187 }
d2fbca94
GX		 1188 }
1189 } else {
1190 goto error;
1191 }
1192 }
1193 break;
d48813dd
GX		 1194 case UC32_EXCP_DTRAP:
1195 case UC32_EXCP_ITRAP:
a86b3c64 1196 info.si_signo = TARGET_SIGSEGV;
d2fbca94
GX		 1197 info.si_errno = 0;
1198 /* XXX: check env->error_code */
1199 info.si_code = TARGET_SEGV_MAPERR;
1200 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1201 queue_signal(env, info.si_signo, &info);
1202 break;
1203 case EXCP_INTERRUPT:
1204 /* just indicate that signals should be handled asap */
1205 break;
1206 case EXCP_DEBUG:
1207 {
1208 int sig;
1209
db6b81d4 1210 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d2fbca94
GX		 1211 if (sig) {
1212 info.si_signo = sig;
1213 info.si_errno = 0;
1214 info.si_code = TARGET_TRAP_BRKPT;
1215 queue_signal(env, info.si_signo, &info);
1216 }
1217 }
1218 break;
1219 default:
1220 goto error;
1221 }
1222 process_pending_signals(env);
1223 }
1224
1225error:
120a9848 1226 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
d2fbca94
GX		 1227 abort();
1228}
1229#endif
1230
93ac68bc 1231#ifdef TARGET_SPARC
ed23fbd9 1232#define SPARC64_STACK_BIAS 2047
93ac68bc 1233
060366c5
FB		 1234//#define DEBUG_WIN
1235
2623cbaf
FB		 1236/* WARNING: dealing with register windows _is_ complicated. More info
1237 can be found at http://www.sics.se/~psm/sparcstack.html */
060366c5
FB		 1238static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1239{
1a14026e 1240 index = (index + cwp * 16) % (16 * env->nwindows);
060366c5
FB		 1241 /* wrap handling : if cwp is on the last window, then we use the
1242 registers 'after' the end */
1a14026e
BS		 1243 if (index < 8 && env->cwp == env->nwindows - 1)
1244 index += 16 * env->nwindows;
060366c5
FB		 1245 return index;
1246}
1247
2623cbaf
FB		 1248/* save the register window 'cwp1' */
1249static inline void save_window_offset(CPUSPARCState *env, int cwp1)
060366c5 1250{
2623cbaf 1251 unsigned int i;
992f48a0 1252 abi_ulong sp_ptr;
3b46e624 1253
53a5960a 1254 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1255#ifdef TARGET_SPARC64
1256 if (sp_ptr & 3)
1257 sp_ptr += SPARC64_STACK_BIAS;
1258#endif
060366c5 1259#if defined(DEBUG_WIN)
2daf0284
BS		 1260 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1261 sp_ptr, cwp1);
060366c5 1262#endif
2623cbaf 1263 for(i = 0; i < 16; i++) {
2f619698
FB		 1264 /* FIXME - what to do if put_user() fails? */
1265 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1266 sp_ptr += sizeof(abi_ulong);
2623cbaf 1267 }
060366c5
FB		 1268}
1269
1270static void save_window(CPUSPARCState *env)
1271{
5ef54116 1272#ifndef TARGET_SPARC64
2623cbaf 1273 unsigned int new_wim;
1a14026e
BS		 1274 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1275 ((1LL << env->nwindows) - 1);
1276 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
2623cbaf 1277 env->wim = new_wim;
5ef54116 1278#else
1a14026e 1279 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
5ef54116
FB		 1280 env->cansave++;
1281 env->canrestore--;
1282#endif
060366c5
FB		 1283}
1284
1285static void restore_window(CPUSPARCState *env)
1286{
eda52953
BS		 1287#ifndef TARGET_SPARC64
1288 unsigned int new_wim;
1289#endif
1290 unsigned int i, cwp1;
992f48a0 1291 abi_ulong sp_ptr;
3b46e624 1292
eda52953 1293#ifndef TARGET_SPARC64
1a14026e
BS		 1294 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1295 ((1LL << env->nwindows) - 1);
eda52953 1296#endif
3b46e624 1297
060366c5 1298 /* restore the invalid window */
1a14026e 1299 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
53a5960a 1300 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1301#ifdef TARGET_SPARC64
1302 if (sp_ptr & 3)
1303 sp_ptr += SPARC64_STACK_BIAS;
1304#endif
060366c5 1305#if defined(DEBUG_WIN)
2daf0284
BS		 1306 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1307 sp_ptr, cwp1);
060366c5 1308#endif
2623cbaf 1309 for(i = 0; i < 16; i++) {
2f619698
FB		 1310 /* FIXME - what to do if get_user() fails? */
1311 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1312 sp_ptr += sizeof(abi_ulong);
2623cbaf 1313 }
5ef54116
FB		 1314#ifdef TARGET_SPARC64
1315 env->canrestore++;
1a14026e
BS		 1316 if (env->cleanwin < env->nwindows - 1)
1317 env->cleanwin++;
5ef54116 1318 env->cansave--;
eda52953
BS		 1319#else
1320 env->wim = new_wim;
5ef54116 1321#endif
060366c5
FB		 1322}
1323
1324static void flush_windows(CPUSPARCState *env)
1325{
1326 int offset, cwp1;
2623cbaf
FB		 1327
1328 offset = 1;
060366c5
FB		 1329 for(;;) {
1330 /* if restore would invoke restore_window(), then we can stop */
1a14026e 1331 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
eda52953 1332#ifndef TARGET_SPARC64
060366c5
FB		 1333 if (env->wim & (1 << cwp1))
1334 break;
eda52953
BS		 1335#else
1336 if (env->canrestore == 0)
1337 break;
1338 env->cansave++;
1339 env->canrestore--;
1340#endif
2623cbaf 1341 save_window_offset(env, cwp1);
060366c5
FB		 1342 offset++;
1343 }
1a14026e 1344 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
eda52953
BS		 1345#ifndef TARGET_SPARC64
1346 /* set wim so that restore will reload the registers */
2623cbaf 1347 env->wim = 1 << cwp1;
eda52953 1348#endif
2623cbaf
FB		 1349#if defined(DEBUG_WIN)
1350 printf("flush_windows: nb=%d\n", offset - 1);
80a9d035 1351#endif
2623cbaf 1352}
060366c5 1353
93ac68bc
FB		 1354void cpu_loop (CPUSPARCState *env)
1355{
878096ee 1356 CPUState *cs = CPU(sparc_env_get_cpu(env));
2cc20260
RH		 1357 int trapnr;
1358 abi_long ret;
c227f099 1359 target_siginfo_t info;
3b46e624 1360
060366c5 1361 while (1) {
b040bc9c 1362 cpu_exec_start(cs);
ea3e9847 1363 trapnr = cpu_sparc_exec(cs);
b040bc9c 1364 cpu_exec_end(cs);
3b46e624 1365
20132b96
RH		 1366 /* Compute PSR before exposing state. */
1367 if (env->cc_op != CC_OP_FLAGS) {
1368 cpu_get_psr(env);
1369 }
1370
060366c5 1371 switch (trapnr) {
5ef54116 1372#ifndef TARGET_SPARC64
5fafdf24 1373 case 0x88:
060366c5 1374 case 0x90:
5ef54116 1375#else
cb33da57 1376 case 0x110:
5ef54116
FB		 1377 case 0x16d:
1378#endif
060366c5 1379 ret = do_syscall (env, env->gregs[1],
5fafdf24
TS		 1380 env->regwptr[0], env->regwptr[1],
1381 env->regwptr[2], env->regwptr[3],
5945cfcb
PM		 1382 env->regwptr[4], env->regwptr[5],
1383 0, 0);
c0bea68f
TB		 1384 if (ret == -TARGET_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) {
1385 break;
1386 }
2cc20260 1387 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
992f48a0 1388#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1389 env->xcc |= PSR_CARRY;
1390#else
060366c5 1391 env->psr |= PSR_CARRY;
27908725 1392#endif
060366c5
FB		 1393 ret = -ret;
1394 } else {
992f48a0 1395#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1396 env->xcc &= ~PSR_CARRY;
1397#else
060366c5 1398 env->psr &= ~PSR_CARRY;
27908725 1399#endif
060366c5
FB		 1400 }
1401 env->regwptr[0] = ret;
1402 /* next instruction */
1403 env->pc = env->npc;
1404 env->npc = env->npc + 4;
1405 break;
1406 case 0x83: /* flush windows */
992f48a0
BS		 1407#ifdef TARGET_ABI32
1408 case 0x103:
1409#endif
2623cbaf 1410 flush_windows(env);
060366c5
FB		 1411 /* next instruction */
1412 env->pc = env->npc;
1413 env->npc = env->npc + 4;
1414 break;
3475187d 1415#ifndef TARGET_SPARC64
060366c5
FB		 1416 case TT_WIN_OVF: /* window overflow */
1417 save_window(env);
1418 break;
1419 case TT_WIN_UNF: /* window underflow */
1420 restore_window(env);
1421 break;
61ff6f58
FB		 1422 case TT_TFAULT:
1423 case TT_DFAULT:
1424 {
59f7182f 1425 info.si_signo = TARGET_SIGSEGV;
61ff6f58
FB		 1426 info.si_errno = 0;
1427 /* XXX: check env->error_code */
1428 info.si_code = TARGET_SEGV_MAPERR;
1429 info._sifields._sigfault._addr = env->mmuregs[4];
624f7979 1430 queue_signal(env, info.si_signo, &info);
61ff6f58
FB		 1431 }
1432 break;
3475187d 1433#else
5ef54116
FB		 1434 case TT_SPILL: /* window overflow */
1435 save_window(env);
1436 break;
1437 case TT_FILL: /* window underflow */
1438 restore_window(env);
1439 break;
7f84a729
BS		 1440 case TT_TFAULT:
1441 case TT_DFAULT:
1442 {
59f7182f 1443 info.si_signo = TARGET_SIGSEGV;
7f84a729
BS		 1444 info.si_errno = 0;
1445 /* XXX: check env->error_code */
1446 info.si_code = TARGET_SEGV_MAPERR;
1447 if (trapnr == TT_DFAULT)
1448 info._sifields._sigfault._addr = env->dmmuregs[4];
1449 else
8194f35a 1450 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
624f7979 1451 queue_signal(env, info.si_signo, &info);
7f84a729
BS		 1452 }
1453 break;
27524dc3 1454#ifndef TARGET_ABI32
5bfb56b2
BS		 1455 case 0x16e:
1456 flush_windows(env);
1457 sparc64_get_context(env);
1458 break;
1459 case 0x16f:
1460 flush_windows(env);
1461 sparc64_set_context(env);
1462 break;
27524dc3 1463#endif
3475187d 1464#endif
48dc41eb
FB		 1465 case EXCP_INTERRUPT:
1466 /* just indicate that signals should be handled asap */
1467 break;
75f22e4e
RH		 1468 case TT_ILL_INSN:
1469 {
1470 info.si_signo = TARGET_SIGILL;
1471 info.si_errno = 0;
1472 info.si_code = TARGET_ILL_ILLOPC;
1473 info._sifields._sigfault._addr = env->pc;
1474 queue_signal(env, info.si_signo, &info);
1475 }
1476 break;
1fddef4b
FB		 1477 case EXCP_DEBUG:
1478 {
1479 int sig;
1480
db6b81d4 1481 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 1482 if (sig)
1483 {
1484 info.si_signo = sig;
1485 info.si_errno = 0;
1486 info.si_code = TARGET_TRAP_BRKPT;
624f7979 1487 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 1488 }
1489 }
1490 break;
060366c5
FB		 1491 default:
1492 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 1493 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 1494 exit(EXIT_FAILURE);
060366c5
FB		 1495 }
1496 process_pending_signals (env);
1497 }
93ac68bc
FB		 1498}
1499
1500#endif
1501
67867308 1502#ifdef TARGET_PPC
05390248 1503static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
9fddaa0c 1504{
4a7428c5 1505 return cpu_get_host_ticks();
9fddaa0c 1506}
3b46e624 1507
05390248 1508uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
9fddaa0c 1509{
e3ea6529 1510 return cpu_ppc_get_tb(env);
9fddaa0c 1511}
3b46e624 1512
05390248 1513uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
9fddaa0c
FB		 1514{
1515 return cpu_ppc_get_tb(env) >> 32;
1516}
3b46e624 1517
05390248 1518uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
9fddaa0c 1519{
b711de95 1520 return cpu_ppc_get_tb(env);
9fddaa0c 1521}
5fafdf24 1522
05390248 1523uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
9fddaa0c 1524{
a062e36c 1525 return cpu_ppc_get_tb(env) >> 32;
9fddaa0c 1526}
76a66253 1527
05390248 1528uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
76a66253
JM		 1529__attribute__ (( alias ("cpu_ppc_load_tbu") ));
1530
05390248 1531uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
9fddaa0c 1532{
76a66253 1533 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
9fddaa0c 1534}
76a66253 1535
a750fc0b 1536/* XXX: to be fixed */
73b01960 1537int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
a750fc0b
JM		 1538{
1539 return -1;
1540}
1541
73b01960 1542int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
a750fc0b
JM		 1543{
1544 return -1;
1545}
1546
56f066bb
NF		 1547static int do_store_exclusive(CPUPPCState *env)
1548{
1549 target_ulong addr;
1550 target_ulong page_addr;
e22c357b 1551 target_ulong val, val2 __attribute__((unused)) = 0;
56f066bb
NF		 1552 int flags;
1553 int segv = 0;
1554
1555 addr = env->reserve_ea;
1556 page_addr = addr & TARGET_PAGE_MASK;
1557 start_exclusive();
1558 mmap_lock();
1559 flags = page_get_flags(page_addr);
1560 if ((flags & PAGE_READ) == 0) {
1561 segv = 1;
1562 } else {
1563 int reg = env->reserve_info & 0x1f;
4b1daa72 1564 int size = env->reserve_info >> 5;
56f066bb
NF		 1565 int stored = 0;
1566
1567 if (addr == env->reserve_addr) {
1568 switch (size) {
1569 case 1: segv = get_user_u8(val, addr); break;
1570 case 2: segv = get_user_u16(val, addr); break;
1571 case 4: segv = get_user_u32(val, addr); break;
1572#if defined(TARGET_PPC64)
1573 case 8: segv = get_user_u64(val, addr); break;
27b95bfe
TM		 1574 case 16: {
1575 segv = get_user_u64(val, addr);
1576 if (!segv) {
1577 segv = get_user_u64(val2, addr + 8);
1578 }
1579 break;
1580 }
56f066bb
NF		 1581#endif
1582 default: abort();
1583 }
1584 if (!segv && val == env->reserve_val) {
1585 val = env->gpr[reg];
1586 switch (size) {
1587 case 1: segv = put_user_u8(val, addr); break;
1588 case 2: segv = put_user_u16(val, addr); break;
1589 case 4: segv = put_user_u32(val, addr); break;
1590#if defined(TARGET_PPC64)
1591 case 8: segv = put_user_u64(val, addr); break;
27b95bfe
TM		 1592 case 16: {
1593 if (val2 == env->reserve_val2) {
e22c357b
DK		 1594 if (msr_le) {
1595 val2 = val;
1596 val = env->gpr[reg+1];
1597 } else {
1598 val2 = env->gpr[reg+1];
1599 }
27b95bfe
TM		 1600 segv = put_user_u64(val, addr);
1601 if (!segv) {
1602 segv = put_user_u64(val2, addr + 8);
1603 }
1604 }
1605 break;
1606 }
56f066bb
NF		 1607#endif
1608 default: abort();
1609 }
1610 if (!segv) {
1611 stored = 1;
1612 }
1613 }
1614 }
1615 env->crf[0] = (stored << 1) | xer_so;
1616 env->reserve_addr = (target_ulong)-1;
1617 }
1618 if (!segv) {
1619 env->nip += 4;
1620 }
1621 mmap_unlock();
1622 end_exclusive();
1623 return segv;
1624}
1625
67867308
FB		 1626void cpu_loop(CPUPPCState *env)
1627{
0315c31c 1628 CPUState *cs = CPU(ppc_env_get_cpu(env));
c227f099 1629 target_siginfo_t info;
61190b14 1630 int trapnr;
9e0e2f96 1631 target_ulong ret;
3b46e624 1632
67867308 1633 for(;;) {
0315c31c 1634 cpu_exec_start(cs);
ea3e9847 1635 trapnr = cpu_ppc_exec(cs);
0315c31c 1636 cpu_exec_end(cs);
67867308 1637 switch(trapnr) {
e1833e1f
JM		 1638 case POWERPC_EXCP_NONE:
1639 /* Just go on */
67867308 1640 break;
e1833e1f 1641 case POWERPC_EXCP_CRITICAL: /* Critical input */
a47dddd7 1642 cpu_abort(cs, "Critical interrupt while in user mode. "
e1833e1f 1643 "Aborting\n");
61190b14 1644 break;
e1833e1f 1645 case POWERPC_EXCP_MCHECK: /* Machine check exception */
a47dddd7 1646 cpu_abort(cs, "Machine check exception while in user mode. "
e1833e1f
JM		 1647 "Aborting\n");
1648 break;
1649 case POWERPC_EXCP_DSI: /* Data storage exception */
90e189ec 1650 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
e1833e1f
JM		 1651 env->spr[SPR_DAR]);
1652 /* XXX: check this. Seems bugged */
2be0071f
FB		 1653 switch (env->error_code & 0xFF000000) {
1654 case 0x40000000:
61190b14
FB		 1655 info.si_signo = TARGET_SIGSEGV;
1656 info.si_errno = 0;
1657 info.si_code = TARGET_SEGV_MAPERR;
1658 break;
2be0071f 1659 case 0x04000000:
61190b14
FB		 1660 info.si_signo = TARGET_SIGILL;
1661 info.si_errno = 0;
1662 info.si_code = TARGET_ILL_ILLADR;
1663 break;
2be0071f 1664 case 0x08000000:
61190b14
FB		 1665 info.si_signo = TARGET_SIGSEGV;
1666 info.si_errno = 0;
1667 info.si_code = TARGET_SEGV_ACCERR;
1668 break;
61190b14
FB		 1669 default:
1670 /* Let's send a regular segfault... */
e1833e1f
JM		 1671 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1672 env->error_code);
61190b14
FB		 1673 info.si_signo = TARGET_SIGSEGV;
1674 info.si_errno = 0;
1675 info.si_code = TARGET_SEGV_MAPERR;
1676 break;
1677 }
67867308 1678 info._sifields._sigfault._addr = env->nip;
624f7979 1679 queue_signal(env, info.si_signo, &info);
67867308 1680 break;
e1833e1f 1681 case POWERPC_EXCP_ISI: /* Instruction storage exception */
90e189ec
BS		 1682 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1683 "\n", env->spr[SPR_SRR0]);
e1833e1f 1684 /* XXX: check this */
2be0071f
FB		 1685 switch (env->error_code & 0xFF000000) {
1686 case 0x40000000:
61190b14 1687 info.si_signo = TARGET_SIGSEGV;
67867308 1688 info.si_errno = 0;
61190b14
FB		 1689 info.si_code = TARGET_SEGV_MAPERR;
1690 break;
2be0071f
FB		 1691 case 0x10000000:
1692 case 0x08000000:
61190b14
FB		 1693 info.si_signo = TARGET_SIGSEGV;
1694 info.si_errno = 0;
1695 info.si_code = TARGET_SEGV_ACCERR;
1696 break;
1697 default:
1698 /* Let's send a regular segfault... */
e1833e1f
JM		 1699 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1700 env->error_code);
61190b14
FB		 1701 info.si_signo = TARGET_SIGSEGV;
1702 info.si_errno = 0;
1703 info.si_code = TARGET_SEGV_MAPERR;
1704 break;
1705 }
1706 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1707 queue_signal(env, info.si_signo, &info);
67867308 1708 break;
e1833e1f 1709 case POWERPC_EXCP_EXTERNAL: /* External input */
a47dddd7 1710 cpu_abort(cs, "External interrupt while in user mode. "
e1833e1f
JM		 1711 "Aborting\n");
1712 break;
1713 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1714 EXCP_DUMP(env, "Unaligned memory access\n");
1715 /* XXX: check this */
61190b14 1716 info.si_signo = TARGET_SIGBUS;
67867308 1717 info.si_errno = 0;
61190b14 1718 info.si_code = TARGET_BUS_ADRALN;
6bb9a0a9 1719 info._sifields._sigfault._addr = env->nip;
624f7979 1720 queue_signal(env, info.si_signo, &info);
67867308 1721 break;
e1833e1f
JM		 1722 case POWERPC_EXCP_PROGRAM: /* Program exception */
1723 /* XXX: check this */
61190b14 1724 switch (env->error_code & ~0xF) {
e1833e1f
JM		 1725 case POWERPC_EXCP_FP:
1726 EXCP_DUMP(env, "Floating point program exception\n");
61190b14
FB		 1727 info.si_signo = TARGET_SIGFPE;
1728 info.si_errno = 0;
1729 switch (env->error_code & 0xF) {
e1833e1f 1730 case POWERPC_EXCP_FP_OX:
61190b14
FB		 1731 info.si_code = TARGET_FPE_FLTOVF;
1732 break;
e1833e1f 1733 case POWERPC_EXCP_FP_UX:
61190b14
FB		 1734 info.si_code = TARGET_FPE_FLTUND;
1735 break;
e1833e1f
JM		 1736 case POWERPC_EXCP_FP_ZX:
1737 case POWERPC_EXCP_FP_VXZDZ:
61190b14
FB		 1738 info.si_code = TARGET_FPE_FLTDIV;
1739 break;
e1833e1f 1740 case POWERPC_EXCP_FP_XX:
61190b14
FB		 1741 info.si_code = TARGET_FPE_FLTRES;
1742 break;
e1833e1f 1743 case POWERPC_EXCP_FP_VXSOFT:
61190b14
FB		 1744 info.si_code = TARGET_FPE_FLTINV;
1745 break;
7c58044c 1746 case POWERPC_EXCP_FP_VXSNAN:
e1833e1f
JM		 1747 case POWERPC_EXCP_FP_VXISI:
1748 case POWERPC_EXCP_FP_VXIDI:
1749 case POWERPC_EXCP_FP_VXIMZ:
1750 case POWERPC_EXCP_FP_VXVC:
1751 case POWERPC_EXCP_FP_VXSQRT:
1752 case POWERPC_EXCP_FP_VXCVI:
61190b14
FB		 1753 info.si_code = TARGET_FPE_FLTSUB;
1754 break;
1755 default:
e1833e1f
JM		 1756 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1757 env->error_code);
1758 break;
61190b14 1759 }
e1833e1f
JM		 1760 break;
1761 case POWERPC_EXCP_INVAL:
1762 EXCP_DUMP(env, "Invalid instruction\n");
61190b14
FB		 1763 info.si_signo = TARGET_SIGILL;
1764 info.si_errno = 0;
1765 switch (env->error_code & 0xF) {
e1833e1f 1766 case POWERPC_EXCP_INVAL_INVAL:
61190b14
FB		 1767 info.si_code = TARGET_ILL_ILLOPC;
1768 break;
e1833e1f 1769 case POWERPC_EXCP_INVAL_LSWX:
a750fc0b 1770 info.si_code = TARGET_ILL_ILLOPN;
61190b14 1771 break;
e1833e1f 1772 case POWERPC_EXCP_INVAL_SPR:
61190b14
FB		 1773 info.si_code = TARGET_ILL_PRVREG;
1774 break;
e1833e1f 1775 case POWERPC_EXCP_INVAL_FP:
61190b14
FB		 1776 info.si_code = TARGET_ILL_COPROC;
1777 break;
1778 default:
e1833e1f
JM		 1779 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1780 env->error_code & 0xF);
61190b14
FB		 1781 info.si_code = TARGET_ILL_ILLADR;
1782 break;
1783 }
1784 break;
e1833e1f
JM		 1785 case POWERPC_EXCP_PRIV:
1786 EXCP_DUMP(env, "Privilege violation\n");
61190b14
FB		 1787 info.si_signo = TARGET_SIGILL;
1788 info.si_errno = 0;
1789 switch (env->error_code & 0xF) {
e1833e1f 1790 case POWERPC_EXCP_PRIV_OPC:
61190b14
FB		 1791 info.si_code = TARGET_ILL_PRVOPC;
1792 break;
e1833e1f 1793 case POWERPC_EXCP_PRIV_REG:
61190b14 1794 info.si_code = TARGET_ILL_PRVREG;
e1833e1f 1795 break;
61190b14 1796 default:
e1833e1f
JM		 1797 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1798 env->error_code & 0xF);
61190b14
FB		 1799 info.si_code = TARGET_ILL_PRVOPC;
1800 break;
1801 }
1802 break;
e1833e1f 1803 case POWERPC_EXCP_TRAP:
a47dddd7 1804 cpu_abort(cs, "Tried to call a TRAP\n");
e1833e1f 1805 break;
61190b14
FB		 1806 default:
1807 /* Should not happen ! */
a47dddd7 1808 cpu_abort(cs, "Unknown program exception (%02x)\n",
e1833e1f
JM		 1809 env->error_code);
1810 break;
61190b14
FB		 1811 }
1812 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1813 queue_signal(env, info.si_signo, &info);
67867308 1814 break;
e1833e1f
JM		 1815 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1816 EXCP_DUMP(env, "No floating point allowed\n");
61190b14 1817 info.si_signo = TARGET_SIGILL;
67867308 1818 info.si_errno = 0;
61190b14
FB		 1819 info.si_code = TARGET_ILL_COPROC;
1820 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1821 queue_signal(env, info.si_signo, &info);
67867308 1822 break;
e1833e1f 1823 case POWERPC_EXCP_SYSCALL: /* System call exception */
a47dddd7 1824 cpu_abort(cs, "Syscall exception while in user mode. "
e1833e1f 1825 "Aborting\n");
61190b14 1826 break;
e1833e1f
JM		 1827 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1828 EXCP_DUMP(env, "No APU instruction allowed\n");
1829 info.si_signo = TARGET_SIGILL;
1830 info.si_errno = 0;
1831 info.si_code = TARGET_ILL_COPROC;
1832 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1833 queue_signal(env, info.si_signo, &info);
61190b14 1834 break;
e1833e1f 1835 case POWERPC_EXCP_DECR: /* Decrementer exception */
a47dddd7 1836 cpu_abort(cs, "Decrementer interrupt while in user mode. "
e1833e1f 1837 "Aborting\n");
61190b14 1838 break;
e1833e1f 1839 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
a47dddd7 1840 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
e1833e1f
JM		 1841 "Aborting\n");
1842 break;
1843 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
a47dddd7 1844 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
e1833e1f
JM		 1845 "Aborting\n");
1846 break;
1847 case POWERPC_EXCP_DTLB: /* Data TLB error */
a47dddd7 1848 cpu_abort(cs, "Data TLB exception while in user mode. "
e1833e1f
JM		 1849 "Aborting\n");
1850 break;
1851 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
a47dddd7 1852 cpu_abort(cs, "Instruction TLB exception while in user mode. "
e1833e1f
JM		 1853 "Aborting\n");
1854 break;
e1833e1f
JM		 1855 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1856 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1857 info.si_signo = TARGET_SIGILL;
1858 info.si_errno = 0;
1859 info.si_code = TARGET_ILL_COPROC;
1860 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1861 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1862 break;
1863 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
a47dddd7 1864 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
e1833e1f
JM		 1865 break;
1866 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
a47dddd7 1867 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
e1833e1f
JM		 1868 break;
1869 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
a47dddd7 1870 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1871 break;
1872 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
a47dddd7 1873 cpu_abort(cs, "Doorbell interrupt while in user mode. "
e1833e1f
JM		 1874 "Aborting\n");
1875 break;
1876 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
a47dddd7 1877 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
e1833e1f
JM		 1878 "Aborting\n");
1879 break;
1880 case POWERPC_EXCP_RESET: /* System reset exception */
a47dddd7 1881 cpu_abort(cs, "Reset interrupt while in user mode. "
e1833e1f
JM		 1882 "Aborting\n");
1883 break;
e1833e1f 1884 case POWERPC_EXCP_DSEG: /* Data segment exception */
a47dddd7 1885 cpu_abort(cs, "Data segment exception while in user mode. "
e1833e1f
JM		 1886 "Aborting\n");
1887 break;
1888 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
a47dddd7 1889 cpu_abort(cs, "Instruction segment exception "
e1833e1f
JM		 1890 "while in user mode. Aborting\n");
1891 break;
e85e7c6e 1892 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1893 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
a47dddd7 1894 cpu_abort(cs, "Hypervisor decrementer interrupt "
e1833e1f
JM		 1895 "while in user mode. Aborting\n");
1896 break;
e1833e1f
JM		 1897 case POWERPC_EXCP_TRACE: /* Trace exception */
1898 /* Nothing to do:
1899 * we use this exception to emulate step-by-step execution mode.
1900 */
1901 break;
e85e7c6e 1902 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1903 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
a47dddd7 1904 cpu_abort(cs, "Hypervisor data storage exception "
e1833e1f
JM		 1905 "while in user mode. Aborting\n");
1906 break;
1907 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
a47dddd7 1908 cpu_abort(cs, "Hypervisor instruction storage exception "
e1833e1f
JM		 1909 "while in user mode. Aborting\n");
1910 break;
1911 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
a47dddd7 1912 cpu_abort(cs, "Hypervisor data segment exception "
e1833e1f
JM		 1913 "while in user mode. Aborting\n");
1914 break;
1915 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
a47dddd7 1916 cpu_abort(cs, "Hypervisor instruction segment exception "
e1833e1f
JM		 1917 "while in user mode. Aborting\n");
1918 break;
e1833e1f
JM		 1919 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1920 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1921 info.si_signo = TARGET_SIGILL;
1922 info.si_errno = 0;
1923 info.si_code = TARGET_ILL_COPROC;
1924 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1925 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1926 break;
1927 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
a47dddd7 1928 cpu_abort(cs, "Programmable interval timer interrupt "
e1833e1f
JM		 1929 "while in user mode. Aborting\n");
1930 break;
1931 case POWERPC_EXCP_IO: /* IO error exception */
a47dddd7 1932 cpu_abort(cs, "IO error exception while in user mode. "
e1833e1f
JM		 1933 "Aborting\n");
1934 break;
1935 case POWERPC_EXCP_RUNM: /* Run mode exception */
a47dddd7 1936 cpu_abort(cs, "Run mode exception while in user mode. "
e1833e1f
JM		 1937 "Aborting\n");
1938 break;
1939 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
a47dddd7 1940 cpu_abort(cs, "Emulation trap exception not handled\n");
e1833e1f
JM		 1941 break;
1942 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
a47dddd7 1943 cpu_abort(cs, "Instruction fetch TLB exception "
e1833e1f
JM		 1944 "while in user-mode. Aborting");
1945 break;
1946 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
a47dddd7 1947 cpu_abort(cs, "Data load TLB exception while in user-mode. "
e1833e1f
JM		 1948 "Aborting");
1949 break;
1950 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
a47dddd7 1951 cpu_abort(cs, "Data store TLB exception while in user-mode. "
e1833e1f
JM		 1952 "Aborting");
1953 break;
1954 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
a47dddd7 1955 cpu_abort(cs, "Floating-point assist exception not handled\n");
e1833e1f
JM		 1956 break;
1957 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
a47dddd7 1958 cpu_abort(cs, "Instruction address breakpoint exception "
e1833e1f
JM		 1959 "not handled\n");
1960 break;
1961 case POWERPC_EXCP_SMI: /* System management interrupt */
a47dddd7 1962 cpu_abort(cs, "System management interrupt while in user mode. "
e1833e1f
JM		 1963 "Aborting\n");
1964 break;
1965 case POWERPC_EXCP_THERM: /* Thermal interrupt */
a47dddd7 1966 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
e1833e1f
JM		 1967 "Aborting\n");
1968 break;
1969 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
a47dddd7 1970 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1971 break;
1972 case POWERPC_EXCP_VPUA: /* Vector assist exception */
a47dddd7 1973 cpu_abort(cs, "Vector assist exception not handled\n");
e1833e1f
JM		 1974 break;
1975 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
a47dddd7 1976 cpu_abort(cs, "Soft patch exception not handled\n");
e1833e1f
JM		 1977 break;
1978 case POWERPC_EXCP_MAINT: /* Maintenance exception */
a47dddd7 1979 cpu_abort(cs, "Maintenance exception while in user mode. "
e1833e1f
JM		 1980 "Aborting\n");
1981 break;
1982 case POWERPC_EXCP_STOP: /* stop translation */
1983 /* We did invalidate the instruction cache. Go on */
1984 break;
1985 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1986 /* We just stopped because of a branch. Go on */
1987 break;
1988 case POWERPC_EXCP_SYSCALL_USER:
1989 /* system call in user-mode emulation */
1990 /* WARNING:
1991 * PPC ABI uses overflow flag in cr0 to signal an error
1992 * in syscalls.
1993 */
e1833e1f
JM		 1994 env->crf[0] &= ~0x1;
1995 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1996 env->gpr[5], env->gpr[6], env->gpr[7],
5945cfcb 1997 env->gpr[8], 0, 0);
6db9d00e
TB		 1998 if (ret == -TARGET_ERESTARTSYS) {
1999 env->nip -= 4;
2000 break;
2001 }
9e0e2f96 2002 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
bcd4933a
NF		 2003 /* Returning from a successful sigreturn syscall.
2004 Avoid corrupting register state. */
2005 break;
2006 }
9e0e2f96 2007 if (ret > (target_ulong)(-515)) {
e1833e1f
JM		 2008 env->crf[0] |= 0x1;
2009 ret = -ret;
61190b14 2010 }
e1833e1f 2011 env->gpr[3] = ret;
e1833e1f 2012 break;
56f066bb
NF		 2013 case POWERPC_EXCP_STCX:
2014 if (do_store_exclusive(env)) {
2015 info.si_signo = TARGET_SIGSEGV;
2016 info.si_errno = 0;
2017 info.si_code = TARGET_SEGV_MAPERR;
2018 info._sifields._sigfault._addr = env->nip;
2019 queue_signal(env, info.si_signo, &info);
2020 }
2021 break;
71f75756
AJ		 2022 case EXCP_DEBUG:
2023 {
2024 int sig;
2025
db6b81d4 2026 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
71f75756
AJ		 2027 if (sig) {
2028 info.si_signo = sig;
2029 info.si_errno = 0;
2030 info.si_code = TARGET_TRAP_BRKPT;
2031 queue_signal(env, info.si_signo, &info);
2032 }
2033 }
2034 break;
56ba31ff
JM		 2035 case EXCP_INTERRUPT:
2036 /* just indicate that signals should be handled asap */
2037 break;
e1833e1f 2038 default:
a47dddd7 2039 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
e1833e1f 2040 break;
67867308
FB		 2041 }
2042 process_pending_signals(env);
2043 }
2044}
2045#endif
2046
048f6b4d
FB		 2047#ifdef TARGET_MIPS
2048
ff4f7382
RH		 2049# ifdef TARGET_ABI_MIPSO32
2050# define MIPS_SYS(name, args) args,
048f6b4d 2051static const uint8_t mips_syscall_args[] = {
29fb0f25 2052 MIPS_SYS(sys_syscall , 8) /* 4000 */
048f6b4d
FB		 2053 MIPS_SYS(sys_exit , 1)
2054 MIPS_SYS(sys_fork , 0)
2055 MIPS_SYS(sys_read , 3)
2056 MIPS_SYS(sys_write , 3)
2057 MIPS_SYS(sys_open , 3) /* 4005 */
2058 MIPS_SYS(sys_close , 1)
2059 MIPS_SYS(sys_waitpid , 3)
2060 MIPS_SYS(sys_creat , 2)
2061 MIPS_SYS(sys_link , 2)
2062 MIPS_SYS(sys_unlink , 1) /* 4010 */
2063 MIPS_SYS(sys_execve , 0)
2064 MIPS_SYS(sys_chdir , 1)
2065 MIPS_SYS(sys_time , 1)
2066 MIPS_SYS(sys_mknod , 3)
2067 MIPS_SYS(sys_chmod , 2) /* 4015 */
2068 MIPS_SYS(sys_lchown , 3)
2069 MIPS_SYS(sys_ni_syscall , 0)
2070 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2071 MIPS_SYS(sys_lseek , 3)
2072 MIPS_SYS(sys_getpid , 0) /* 4020 */
2073 MIPS_SYS(sys_mount , 5)
868e34d7 2074 MIPS_SYS(sys_umount , 1)
048f6b4d
FB		 2075 MIPS_SYS(sys_setuid , 1)
2076 MIPS_SYS(sys_getuid , 0)
2077 MIPS_SYS(sys_stime , 1) /* 4025 */
2078 MIPS_SYS(sys_ptrace , 4)
2079 MIPS_SYS(sys_alarm , 1)
2080 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2081 MIPS_SYS(sys_pause , 0)
2082 MIPS_SYS(sys_utime , 2) /* 4030 */
2083 MIPS_SYS(sys_ni_syscall , 0)
2084 MIPS_SYS(sys_ni_syscall , 0)
2085 MIPS_SYS(sys_access , 2)
2086 MIPS_SYS(sys_nice , 1)
2087 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2088 MIPS_SYS(sys_sync , 0)
2089 MIPS_SYS(sys_kill , 2)
2090 MIPS_SYS(sys_rename , 2)
2091 MIPS_SYS(sys_mkdir , 2)
2092 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2093 MIPS_SYS(sys_dup , 1)
2094 MIPS_SYS(sys_pipe , 0)
2095 MIPS_SYS(sys_times , 1)
2096 MIPS_SYS(sys_ni_syscall , 0)
2097 MIPS_SYS(sys_brk , 1) /* 4045 */
2098 MIPS_SYS(sys_setgid , 1)
2099 MIPS_SYS(sys_getgid , 0)
2100 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2101 MIPS_SYS(sys_geteuid , 0)
2102 MIPS_SYS(sys_getegid , 0) /* 4050 */
2103 MIPS_SYS(sys_acct , 0)
868e34d7 2104 MIPS_SYS(sys_umount2 , 2)
048f6b4d
FB		 2105 MIPS_SYS(sys_ni_syscall , 0)
2106 MIPS_SYS(sys_ioctl , 3)
2107 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2108 MIPS_SYS(sys_ni_syscall , 2)
2109 MIPS_SYS(sys_setpgid , 2)
2110 MIPS_SYS(sys_ni_syscall , 0)
2111 MIPS_SYS(sys_olduname , 1)
2112 MIPS_SYS(sys_umask , 1) /* 4060 */
2113 MIPS_SYS(sys_chroot , 1)
2114 MIPS_SYS(sys_ustat , 2)
2115 MIPS_SYS(sys_dup2 , 2)
2116 MIPS_SYS(sys_getppid , 0)
2117 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2118 MIPS_SYS(sys_setsid , 0)
2119 MIPS_SYS(sys_sigaction , 3)
2120 MIPS_SYS(sys_sgetmask , 0)
2121 MIPS_SYS(sys_ssetmask , 1)
2122 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2123 MIPS_SYS(sys_setregid , 2)
2124 MIPS_SYS(sys_sigsuspend , 0)
2125 MIPS_SYS(sys_sigpending , 1)
2126 MIPS_SYS(sys_sethostname , 2)
2127 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2128 MIPS_SYS(sys_getrlimit , 2)
2129 MIPS_SYS(sys_getrusage , 2)
2130 MIPS_SYS(sys_gettimeofday, 2)
2131 MIPS_SYS(sys_settimeofday, 2)
2132 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2133 MIPS_SYS(sys_setgroups , 2)
2134 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2135 MIPS_SYS(sys_symlink , 2)
2136 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2137 MIPS_SYS(sys_readlink , 3) /* 4085 */
2138 MIPS_SYS(sys_uselib , 1)
2139 MIPS_SYS(sys_swapon , 2)
2140 MIPS_SYS(sys_reboot , 3)
2141 MIPS_SYS(old_readdir , 3)
2142 MIPS_SYS(old_mmap , 6) /* 4090 */
2143 MIPS_SYS(sys_munmap , 2)
2144 MIPS_SYS(sys_truncate , 2)
2145 MIPS_SYS(sys_ftruncate , 2)
2146 MIPS_SYS(sys_fchmod , 2)
2147 MIPS_SYS(sys_fchown , 3) /* 4095 */
2148 MIPS_SYS(sys_getpriority , 2)
2149 MIPS_SYS(sys_setpriority , 3)
2150 MIPS_SYS(sys_ni_syscall , 0)
2151 MIPS_SYS(sys_statfs , 2)
2152 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2153 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2154 MIPS_SYS(sys_socketcall , 2)
2155 MIPS_SYS(sys_syslog , 3)
2156 MIPS_SYS(sys_setitimer , 3)
2157 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2158 MIPS_SYS(sys_newstat , 2)
2159 MIPS_SYS(sys_newlstat , 2)
2160 MIPS_SYS(sys_newfstat , 2)
2161 MIPS_SYS(sys_uname , 1)
2162 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2163 MIPS_SYS(sys_vhangup , 0)
2164 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2165 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2166 MIPS_SYS(sys_wait4 , 4)
2167 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2168 MIPS_SYS(sys_sysinfo , 1)
2169 MIPS_SYS(sys_ipc , 6)
2170 MIPS_SYS(sys_fsync , 1)
2171 MIPS_SYS(sys_sigreturn , 0)
18113962 2172 MIPS_SYS(sys_clone , 6) /* 4120 */
048f6b4d
FB		 2173 MIPS_SYS(sys_setdomainname, 2)
2174 MIPS_SYS(sys_newuname , 1)
2175 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2176 MIPS_SYS(sys_adjtimex , 1)
2177 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2178 MIPS_SYS(sys_sigprocmask , 3)
2179 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2180 MIPS_SYS(sys_init_module , 5)
2181 MIPS_SYS(sys_delete_module, 1)
2182 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2183 MIPS_SYS(sys_quotactl , 0)
2184 MIPS_SYS(sys_getpgid , 1)
2185 MIPS_SYS(sys_fchdir , 1)
2186 MIPS_SYS(sys_bdflush , 2)
2187 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2188 MIPS_SYS(sys_personality , 1)
2189 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2190 MIPS_SYS(sys_setfsuid , 1)
2191 MIPS_SYS(sys_setfsgid , 1)
2192 MIPS_SYS(sys_llseek , 5) /* 4140 */
2193 MIPS_SYS(sys_getdents , 3)
2194 MIPS_SYS(sys_select , 5)
2195 MIPS_SYS(sys_flock , 2)
2196 MIPS_SYS(sys_msync , 3)
2197 MIPS_SYS(sys_readv , 3) /* 4145 */
2198 MIPS_SYS(sys_writev , 3)
2199 MIPS_SYS(sys_cacheflush , 3)
2200 MIPS_SYS(sys_cachectl , 3)
2201 MIPS_SYS(sys_sysmips , 4)
2202 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2203 MIPS_SYS(sys_getsid , 1)
2204 MIPS_SYS(sys_fdatasync , 0)
2205 MIPS_SYS(sys_sysctl , 1)
2206 MIPS_SYS(sys_mlock , 2)
2207 MIPS_SYS(sys_munlock , 2) /* 4155 */
2208 MIPS_SYS(sys_mlockall , 1)
2209 MIPS_SYS(sys_munlockall , 0)
2210 MIPS_SYS(sys_sched_setparam, 2)
2211 MIPS_SYS(sys_sched_getparam, 2)
2212 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2213 MIPS_SYS(sys_sched_getscheduler, 1)
2214 MIPS_SYS(sys_sched_yield , 0)
2215 MIPS_SYS(sys_sched_get_priority_max, 1)
2216 MIPS_SYS(sys_sched_get_priority_min, 1)
2217 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2218 MIPS_SYS(sys_nanosleep, 2)
b0932e06 2219 MIPS_SYS(sys_mremap , 5)
048f6b4d
FB		 2220 MIPS_SYS(sys_accept , 3)
2221 MIPS_SYS(sys_bind , 3)
2222 MIPS_SYS(sys_connect , 3) /* 4170 */
2223 MIPS_SYS(sys_getpeername , 3)
2224 MIPS_SYS(sys_getsockname , 3)
2225 MIPS_SYS(sys_getsockopt , 5)
2226 MIPS_SYS(sys_listen , 2)
2227 MIPS_SYS(sys_recv , 4) /* 4175 */
2228 MIPS_SYS(sys_recvfrom , 6)
2229 MIPS_SYS(sys_recvmsg , 3)
2230 MIPS_SYS(sys_send , 4)
2231 MIPS_SYS(sys_sendmsg , 3)
2232 MIPS_SYS(sys_sendto , 6) /* 4180 */
2233 MIPS_SYS(sys_setsockopt , 5)
2234 MIPS_SYS(sys_shutdown , 2)
2235 MIPS_SYS(sys_socket , 3)
2236 MIPS_SYS(sys_socketpair , 4)
2237 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2238 MIPS_SYS(sys_getresuid , 3)
2239 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2240 MIPS_SYS(sys_poll , 3)
2241 MIPS_SYS(sys_nfsservctl , 3)
2242 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2243 MIPS_SYS(sys_getresgid , 3)
2244 MIPS_SYS(sys_prctl , 5)
2245 MIPS_SYS(sys_rt_sigreturn, 0)
2246 MIPS_SYS(sys_rt_sigaction, 4)
2247 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2248 MIPS_SYS(sys_rt_sigpending, 2)
2249 MIPS_SYS(sys_rt_sigtimedwait, 4)
2250 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2251 MIPS_SYS(sys_rt_sigsuspend, 0)
2252 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2253 MIPS_SYS(sys_pwrite64 , 6)
2254 MIPS_SYS(sys_chown , 3)
2255 MIPS_SYS(sys_getcwd , 2)
2256 MIPS_SYS(sys_capget , 2)
2257 MIPS_SYS(sys_capset , 2) /* 4205 */
053ebb27 2258 MIPS_SYS(sys_sigaltstack , 2)
048f6b4d
FB		 2259 MIPS_SYS(sys_sendfile , 4)
2260 MIPS_SYS(sys_ni_syscall , 0)
2261 MIPS_SYS(sys_ni_syscall , 0)
2262 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2263 MIPS_SYS(sys_truncate64 , 4)
2264 MIPS_SYS(sys_ftruncate64 , 4)
2265 MIPS_SYS(sys_stat64 , 2)
2266 MIPS_SYS(sys_lstat64 , 2)
2267 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2268 MIPS_SYS(sys_pivot_root , 2)
2269 MIPS_SYS(sys_mincore , 3)
2270 MIPS_SYS(sys_madvise , 3)
2271 MIPS_SYS(sys_getdents64 , 3)
2272 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2273 MIPS_SYS(sys_ni_syscall , 0)
2274 MIPS_SYS(sys_gettid , 0)
2275 MIPS_SYS(sys_readahead , 5)
2276 MIPS_SYS(sys_setxattr , 5)
2277 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2278 MIPS_SYS(sys_fsetxattr , 5)
2279 MIPS_SYS(sys_getxattr , 4)
2280 MIPS_SYS(sys_lgetxattr , 4)
2281 MIPS_SYS(sys_fgetxattr , 4)
2282 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2283 MIPS_SYS(sys_llistxattr , 3)
2284 MIPS_SYS(sys_flistxattr , 3)
2285 MIPS_SYS(sys_removexattr , 2)
2286 MIPS_SYS(sys_lremovexattr, 2)
2287 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2288 MIPS_SYS(sys_tkill , 2)
2289 MIPS_SYS(sys_sendfile64 , 5)
43be1343 2290 MIPS_SYS(sys_futex , 6)
048f6b4d
FB		 2291 MIPS_SYS(sys_sched_setaffinity, 3)
2292 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2293 MIPS_SYS(sys_io_setup , 2)
2294 MIPS_SYS(sys_io_destroy , 1)
2295 MIPS_SYS(sys_io_getevents, 5)
2296 MIPS_SYS(sys_io_submit , 3)
2297 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2298 MIPS_SYS(sys_exit_group , 1)
2299 MIPS_SYS(sys_lookup_dcookie, 3)
2300 MIPS_SYS(sys_epoll_create, 1)
2301 MIPS_SYS(sys_epoll_ctl , 4)
2302 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2303 MIPS_SYS(sys_remap_file_pages, 5)
2304 MIPS_SYS(sys_set_tid_address, 1)
2305 MIPS_SYS(sys_restart_syscall, 0)
2306 MIPS_SYS(sys_fadvise64_64, 7)
2307 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2308 MIPS_SYS(sys_fstatfs64 , 2)
2309 MIPS_SYS(sys_timer_create, 3)
2310 MIPS_SYS(sys_timer_settime, 4)
2311 MIPS_SYS(sys_timer_gettime, 2)
2312 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2313 MIPS_SYS(sys_timer_delete, 1)
2314 MIPS_SYS(sys_clock_settime, 2)
2315 MIPS_SYS(sys_clock_gettime, 2)
2316 MIPS_SYS(sys_clock_getres, 2)
2317 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2318 MIPS_SYS(sys_tgkill , 3)
2319 MIPS_SYS(sys_utimes , 2)
2320 MIPS_SYS(sys_mbind , 4)
2321 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2322 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2323 MIPS_SYS(sys_mq_open , 4)
2324 MIPS_SYS(sys_mq_unlink , 1)
2325 MIPS_SYS(sys_mq_timedsend, 5)
2326 MIPS_SYS(sys_mq_timedreceive, 5)
2327 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2328 MIPS_SYS(sys_mq_getsetattr, 3)
2329 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2330 MIPS_SYS(sys_waitid , 4)
2331 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2332 MIPS_SYS(sys_add_key , 5)
388bb21a 2333 MIPS_SYS(sys_request_key, 4)
048f6b4d 2334 MIPS_SYS(sys_keyctl , 5)
6f5b89a0 2335 MIPS_SYS(sys_set_thread_area, 1)
388bb21a
TS		 2336 MIPS_SYS(sys_inotify_init, 0)
2337 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2338 MIPS_SYS(sys_inotify_rm_watch, 2)
2339 MIPS_SYS(sys_migrate_pages, 4)
2340 MIPS_SYS(sys_openat, 4)
2341 MIPS_SYS(sys_mkdirat, 3)
2342 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2343 MIPS_SYS(sys_fchownat, 5)
2344 MIPS_SYS(sys_futimesat, 3)
2345 MIPS_SYS(sys_fstatat64, 4)
2346 MIPS_SYS(sys_unlinkat, 3)
2347 MIPS_SYS(sys_renameat, 4) /* 4295 */
2348 MIPS_SYS(sys_linkat, 5)
2349 MIPS_SYS(sys_symlinkat, 3)
2350 MIPS_SYS(sys_readlinkat, 4)
2351 MIPS_SYS(sys_fchmodat, 3)
2352 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2353 MIPS_SYS(sys_pselect6, 6)
2354 MIPS_SYS(sys_ppoll, 5)
2355 MIPS_SYS(sys_unshare, 1)
b0932e06 2356 MIPS_SYS(sys_splice, 6)
388bb21a
TS		 2357 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2358 MIPS_SYS(sys_tee, 4)
2359 MIPS_SYS(sys_vmsplice, 4)
2360 MIPS_SYS(sys_move_pages, 6)
2361 MIPS_SYS(sys_set_robust_list, 2)
2362 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2363 MIPS_SYS(sys_kexec_load, 4)
2364 MIPS_SYS(sys_getcpu, 3)
2365 MIPS_SYS(sys_epoll_pwait, 6)
2366 MIPS_SYS(sys_ioprio_set, 3)
2367 MIPS_SYS(sys_ioprio_get, 2)
d979e8eb
PM		 2368 MIPS_SYS(sys_utimensat, 4)
2369 MIPS_SYS(sys_signalfd, 3)
2370 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2371 MIPS_SYS(sys_eventfd, 1)
2372 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2373 MIPS_SYS(sys_timerfd_create, 2)
2374 MIPS_SYS(sys_timerfd_gettime, 2)
2375 MIPS_SYS(sys_timerfd_settime, 4)
2376 MIPS_SYS(sys_signalfd4, 4)
2377 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2378 MIPS_SYS(sys_epoll_create1, 1)
2379 MIPS_SYS(sys_dup3, 3)
2380 MIPS_SYS(sys_pipe2, 2)
2381 MIPS_SYS(sys_inotify_init1, 1)
2382 MIPS_SYS(sys_preadv, 6) /* 4330 */
2383 MIPS_SYS(sys_pwritev, 6)
2384 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2385 MIPS_SYS(sys_perf_event_open, 5)
2386 MIPS_SYS(sys_accept4, 4)
2387 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2388 MIPS_SYS(sys_fanotify_init, 2)
2389 MIPS_SYS(sys_fanotify_mark, 6)
2390 MIPS_SYS(sys_prlimit64, 4)
2391 MIPS_SYS(sys_name_to_handle_at, 5)
2392 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2393 MIPS_SYS(sys_clock_adjtime, 2)
2394 MIPS_SYS(sys_syncfs, 1)
048f6b4d 2395};
ff4f7382
RH		 2396# undef MIPS_SYS
2397# endif /* O32 */
048f6b4d 2398
590bc601
PB		 2399static int do_store_exclusive(CPUMIPSState *env)
2400{
2401 target_ulong addr;
2402 target_ulong page_addr;
2403 target_ulong val;
2404 int flags;
2405 int segv = 0;
2406 int reg;
2407 int d;
2408
5499b6ff 2409 addr = env->lladdr;
590bc601
PB		 2410 page_addr = addr & TARGET_PAGE_MASK;
2411 start_exclusive();
2412 mmap_lock();
2413 flags = page_get_flags(page_addr);
2414 if ((flags & PAGE_READ) == 0) {
2415 segv = 1;
2416 } else {
2417 reg = env->llreg & 0x1f;
2418 d = (env->llreg & 0x20) != 0;
2419 if (d) {
2420 segv = get_user_s64(val, addr);
2421 } else {
2422 segv = get_user_s32(val, addr);
2423 }
2424 if (!segv) {
2425 if (val != env->llval) {
2426 env->active_tc.gpr[reg] = 0;
2427 } else {
2428 if (d) {
2429 segv = put_user_u64(env->llnewval, addr);
2430 } else {
2431 segv = put_user_u32(env->llnewval, addr);
2432 }
2433 if (!segv) {
2434 env->active_tc.gpr[reg] = 1;
2435 }
2436 }
2437 }
2438 }
5499b6ff 2439 env->lladdr = -1;
590bc601
PB		 2440 if (!segv) {
2441 env->active_tc.PC += 4;
2442 }
2443 mmap_unlock();
2444 end_exclusive();
2445 return segv;
2446}
2447
54b2f42c
MI		 2448/* Break codes */
2449enum {
2450 BRK_OVERFLOW = 6,
2451 BRK_DIVZERO = 7
2452};
2453
2454static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2455 unsigned int code)
2456{
2457 int ret = -1;
2458
2459 switch (code) {
2460 case BRK_OVERFLOW:
2461 case BRK_DIVZERO:
2462 info->si_signo = TARGET_SIGFPE;
2463 info->si_errno = 0;
2464 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2465 queue_signal(env, info->si_signo, &*info);
2466 ret = 0;
2467 break;
2468 default:
b51910ba
PJ		 2469 info->si_signo = TARGET_SIGTRAP;
2470 info->si_errno = 0;
2471 queue_signal(env, info->si_signo, &*info);
2472 ret = 0;
54b2f42c
MI		 2473 break;
2474 }
2475
2476 return ret;
2477}
2478
048f6b4d
FB		 2479void cpu_loop(CPUMIPSState *env)
2480{
0315c31c 2481 CPUState *cs = CPU(mips_env_get_cpu(env));
c227f099 2482 target_siginfo_t info;
ff4f7382
RH		 2483 int trapnr;
2484 abi_long ret;
2485# ifdef TARGET_ABI_MIPSO32
048f6b4d 2486 unsigned int syscall_num;
ff4f7382 2487# endif
048f6b4d
FB		 2488
2489 for(;;) {
0315c31c 2490 cpu_exec_start(cs);
ea3e9847 2491 trapnr = cpu_mips_exec(cs);
0315c31c 2492 cpu_exec_end(cs);
048f6b4d
FB		 2493 switch(trapnr) {
2494 case EXCP_SYSCALL:
b5dc7732 2495 env->active_tc.PC += 4;
ff4f7382
RH		 2496# ifdef TARGET_ABI_MIPSO32
2497 syscall_num = env->active_tc.gpr[2] - 4000;
388bb21a 2498 if (syscall_num >= sizeof(mips_syscall_args)) {
7c2f6157 2499 ret = -TARGET_ENOSYS;
388bb21a
TS		 2500 } else {
2501 int nb_args;
992f48a0
BS		 2502 abi_ulong sp_reg;
2503 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
388bb21a
TS		 2504
2505 nb_args = mips_syscall_args[syscall_num];
b5dc7732 2506 sp_reg = env->active_tc.gpr[29];
388bb21a
TS		 2507 switch (nb_args) {
2508 /* these arguments are taken from the stack */
94c19610
ACH		 2509 case 8:
2510 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2511 goto done_syscall;
2512 }
2513 case 7:
2514 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2515 goto done_syscall;
2516 }
2517 case 6:
2518 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2519 goto done_syscall;
2520 }
2521 case 5:
2522 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2523 goto done_syscall;
2524 }
388bb21a
TS		 2525 default:
2526 break;
048f6b4d 2527 }
b5dc7732
TS		 2528 ret = do_syscall(env, env->active_tc.gpr[2],
2529 env->active_tc.gpr[4],
2530 env->active_tc.gpr[5],
2531 env->active_tc.gpr[6],
2532 env->active_tc.gpr[7],
5945cfcb 2533 arg5, arg6, arg7, arg8);
388bb21a 2534 }
94c19610 2535done_syscall:
ff4f7382
RH		 2536# else
2537 ret = do_syscall(env, env->active_tc.gpr[2],
2538 env->active_tc.gpr[4], env->active_tc.gpr[5],
2539 env->active_tc.gpr[6], env->active_tc.gpr[7],
2540 env->active_tc.gpr[8], env->active_tc.gpr[9],
2541 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2542# endif /* O32 */
2eb3ae27
TB		 2543 if (ret == -TARGET_ERESTARTSYS) {
2544 env->active_tc.PC -= 4;
2545 break;
2546 }
0b1bcb00
PB		 2547 if (ret == -TARGET_QEMU_ESIGRETURN) {
2548 /* Returning from a successful sigreturn syscall.
2549 Avoid clobbering register state. */
2550 break;
2551 }
ff4f7382 2552 if ((abi_ulong)ret >= (abi_ulong)-1133) {
b5dc7732 2553 env->active_tc.gpr[7] = 1; /* error flag */
388bb21a
TS		 2554 ret = -ret;
2555 } else {
b5dc7732 2556 env->active_tc.gpr[7] = 0; /* error flag */
048f6b4d 2557 }
b5dc7732 2558 env->active_tc.gpr[2] = ret;
048f6b4d 2559 break;
ca7c2b1b
TS		 2560 case EXCP_TLBL:
2561 case EXCP_TLBS:
e6e5bd2d
WT		 2562 case EXCP_AdEL:
2563 case EXCP_AdES:
e4474235
PB		 2564 info.si_signo = TARGET_SIGSEGV;
2565 info.si_errno = 0;
2566 /* XXX: check env->error_code */
2567 info.si_code = TARGET_SEGV_MAPERR;
2568 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2569 queue_signal(env, info.si_signo, &info);
2570 break;
6900e84b 2571 case EXCP_CpU:
048f6b4d 2572 case EXCP_RI:
bc1ad2de
FB		 2573 info.si_signo = TARGET_SIGILL;
2574 info.si_errno = 0;
2575 info.si_code = 0;
624f7979 2576 queue_signal(env, info.si_signo, &info);
048f6b4d 2577 break;
106ec879
FB		 2578 case EXCP_INTERRUPT:
2579 /* just indicate that signals should be handled asap */
2580 break;
d08b2a28
PB		 2581 case EXCP_DEBUG:
2582 {
2583 int sig;
2584
db6b81d4 2585 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d08b2a28
PB		 2586 if (sig)
2587 {
2588 info.si_signo = sig;
2589 info.si_errno = 0;
2590 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2591 queue_signal(env, info.si_signo, &info);
d08b2a28
PB		 2592 }
2593 }
2594 break;
590bc601
PB		 2595 case EXCP_SC:
2596 if (do_store_exclusive(env)) {
2597 info.si_signo = TARGET_SIGSEGV;
2598 info.si_errno = 0;
2599 info.si_code = TARGET_SEGV_MAPERR;
2600 info._sifields._sigfault._addr = env->active_tc.PC;
2601 queue_signal(env, info.si_signo, &info);
2602 }
2603 break;
853c3240
JL		 2604 case EXCP_DSPDIS:
2605 info.si_signo = TARGET_SIGILL;
2606 info.si_errno = 0;
2607 info.si_code = TARGET_ILL_ILLOPC;
2608 queue_signal(env, info.si_signo, &info);
2609 break;
54b2f42c
MI		 2610 /* The code below was inspired by the MIPS Linux kernel trap
2611 * handling code in arch/mips/kernel/traps.c.
2612 */
2613 case EXCP_BREAK:
2614 {
2615 abi_ulong trap_instr;
2616 unsigned int code;
2617
a0333817
KCY		 2618 if (env->hflags & MIPS_HFLAG_M16) {
2619 if (env->insn_flags & ASE_MICROMIPS) {
2620 /* microMIPS mode */
1308c464
KCY		 2621 ret = get_user_u16(trap_instr, env->active_tc.PC);
2622 if (ret != 0) {
2623 goto error;
2624 }
a0333817 2625
1308c464
KCY		 2626 if ((trap_instr >> 10) == 0x11) {
2627 /* 16-bit instruction */
2628 code = trap_instr & 0xf;
2629 } else {
2630 /* 32-bit instruction */
2631 abi_ulong instr_lo;
2632
2633 ret = get_user_u16(instr_lo,
2634 env->active_tc.PC + 2);
2635 if (ret != 0) {
2636 goto error;
2637 }
2638 trap_instr = (trap_instr << 16) | instr_lo;
2639 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2640 /* Unfortunately, microMIPS also suffers from
2641 the old assembler bug... */
2642 if (code >= (1 << 10)) {
2643 code >>= 10;
2644 }
2645 }
a0333817
KCY		 2646 } else {
2647 /* MIPS16e mode */
2648 ret = get_user_u16(trap_instr, env->active_tc.PC);
2649 if (ret != 0) {
2650 goto error;
2651 }
2652 code = (trap_instr >> 6) & 0x3f;
a0333817
KCY		 2653 }
2654 } else {
f01a361b 2655 ret = get_user_u32(trap_instr, env->active_tc.PC);
1308c464
KCY		 2656 if (ret != 0) {
2657 goto error;
2658 }
54b2f42c 2659
1308c464
KCY		 2660 /* As described in the original Linux kernel code, the
2661 * below checks on 'code' are to work around an old
2662 * assembly bug.
2663 */
2664 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2665 if (code >= (1 << 10)) {
2666 code >>= 10;
2667 }
54b2f42c
MI		 2668 }
2669
2670 if (do_break(env, &info, code) != 0) {
2671 goto error;
2672 }
2673 }
2674 break;
2675 case EXCP_TRAP:
2676 {
2677 abi_ulong trap_instr;
2678 unsigned int code = 0;
2679
a0333817
KCY		 2680 if (env->hflags & MIPS_HFLAG_M16) {
2681 /* microMIPS mode */
2682 abi_ulong instr[2];
2683
2684 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2685 get_user_u16(instr[1], env->active_tc.PC + 2);
2686
2687 trap_instr = (instr[0] << 16) | instr[1];
2688 } else {
f01a361b 2689 ret = get_user_u32(trap_instr, env->active_tc.PC);
a0333817
KCY		 2690 }
2691
54b2f42c
MI		 2692 if (ret != 0) {
2693 goto error;
2694 }
2695
2696 /* The immediate versions don't provide a code. */
2697 if (!(trap_instr & 0xFC000000)) {
a0333817
KCY		 2698 if (env->hflags & MIPS_HFLAG_M16) {
2699 /* microMIPS mode */
2700 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2701 } else {
2702 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2703 }
54b2f42c
MI		 2704 }
2705
2706 if (do_break(env, &info, code) != 0) {
2707 goto error;
2708 }
2709 }
2710 break;
048f6b4d 2711 default:
54b2f42c 2712error:
120a9848 2713 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
048f6b4d
FB		 2714 abort();
2715 }
2716 process_pending_signals(env);
2717 }
2718}
2719#endif
2720
d962783e
JL		 2721#ifdef TARGET_OPENRISC
2722
2723void cpu_loop(CPUOpenRISCState *env)
2724{
878096ee 2725 CPUState *cs = CPU(openrisc_env_get_cpu(env));
d962783e 2726 int trapnr, gdbsig;
7fe7231a 2727 abi_long ret;
d962783e
JL		 2728
2729 for (;;) {
b040bc9c 2730 cpu_exec_start(cs);
ea3e9847 2731 trapnr = cpu_openrisc_exec(cs);
b040bc9c 2732 cpu_exec_end(cs);
d962783e
JL		 2733 gdbsig = 0;
2734
2735 switch (trapnr) {
2736 case EXCP_RESET:
120a9848 2737 qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc);
4d1275c2 2738 exit(EXIT_FAILURE);
d962783e
JL		 2739 break;
2740 case EXCP_BUSERR:
120a9848 2741 qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc);
a86b3c64 2742 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2743 break;
2744 case EXCP_DPF:
2745 case EXCP_IPF:
878096ee 2746 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2747 gdbsig = TARGET_SIGSEGV;
2748 break;
2749 case EXCP_TICK:
120a9848 2750 qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc);
d962783e
JL		 2751 break;
2752 case EXCP_ALIGN:
120a9848 2753 qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc);
a86b3c64 2754 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2755 break;
2756 case EXCP_ILLEGAL:
120a9848 2757 qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc);
a86b3c64 2758 gdbsig = TARGET_SIGILL;
d962783e
JL		 2759 break;
2760 case EXCP_INT:
120a9848 2761 qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc);
d962783e
JL		 2762 break;
2763 case EXCP_DTLBMISS:
2764 case EXCP_ITLBMISS:
120a9848 2765 qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n");
d962783e
JL		 2766 break;
2767 case EXCP_RANGE:
120a9848 2768 qemu_log_mask(CPU_LOG_INT, "\nRange\n");
a86b3c64 2769 gdbsig = TARGET_SIGSEGV;
d962783e
JL		 2770 break;
2771 case EXCP_SYSCALL:
2772 env->pc += 4; /* 0xc00; */
7fe7231a
TB		 2773 ret = do_syscall(env,
2774 env->gpr[11], /* return value */
2775 env->gpr[3], /* r3 - r7 are params */
2776 env->gpr[4],
2777 env->gpr[5],
2778 env->gpr[6],
2779 env->gpr[7],
2780 env->gpr[8], 0, 0);
2781 if (ret == -TARGET_ERESTARTSYS) {
2782 env->pc -= 4;
2783 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2784 env->gpr[11] = ret;
2785 }
d962783e
JL		 2786 break;
2787 case EXCP_FPE:
120a9848 2788 qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n");
d962783e
JL		 2789 break;
2790 case EXCP_TRAP:
120a9848 2791 qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
a86b3c64 2792 gdbsig = TARGET_SIGTRAP;
d962783e
JL		 2793 break;
2794 case EXCP_NR:
120a9848 2795 qemu_log_mask(CPU_LOG_INT, "\nNR\n");
d962783e
JL		 2796 break;
2797 default:
120a9848 2798 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
d962783e 2799 trapnr);
d962783e
JL		 2800 gdbsig = TARGET_SIGILL;
2801 break;
2802 }
2803 if (gdbsig) {
db6b81d4 2804 gdb_handlesig(cs, gdbsig);
d962783e 2805 if (gdbsig != TARGET_SIGTRAP) {
4d1275c2 2806 exit(EXIT_FAILURE);
d962783e
JL		 2807 }
2808 }
2809
2810 process_pending_signals(env);
2811 }
2812}
2813
2814#endif /* TARGET_OPENRISC */
2815
fdf9b3e8 2816#ifdef TARGET_SH4
05390248 2817void cpu_loop(CPUSH4State *env)
fdf9b3e8 2818{
878096ee 2819 CPUState *cs = CPU(sh_env_get_cpu(env));
fdf9b3e8 2820 int trapnr, ret;
c227f099 2821 target_siginfo_t info;
3b46e624 2822
fdf9b3e8 2823 while (1) {
b040bc9c 2824 cpu_exec_start(cs);
ea3e9847 2825 trapnr = cpu_sh4_exec(cs);
b040bc9c 2826 cpu_exec_end(cs);
3b46e624 2827
fdf9b3e8
FB		 2828 switch (trapnr) {
2829 case 0x160:
0b6d3ae0 2830 env->pc += 2;
5fafdf24
TS		 2831 ret = do_syscall(env,
2832 env->gregs[3],
2833 env->gregs[4],
2834 env->gregs[5],
2835 env->gregs[6],
2836 env->gregs[7],
2837 env->gregs[0],
5945cfcb
PM		 2838 env->gregs[1],
2839 0, 0);
ba412496
TB		 2840 if (ret == -TARGET_ERESTARTSYS) {
2841 env->pc -= 2;
2842 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2843 env->gregs[0] = ret;
2844 }
fdf9b3e8 2845 break;
c3b5bc8a
TS		 2846 case EXCP_INTERRUPT:
2847 /* just indicate that signals should be handled asap */
2848 break;
355fb23d
PB		 2849 case EXCP_DEBUG:
2850 {
2851 int sig;
2852
db6b81d4 2853 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
355fb23d
PB		 2854 if (sig)
2855 {
2856 info.si_signo = sig;
2857 info.si_errno = 0;
2858 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2859 queue_signal(env, info.si_signo, &info);
355fb23d
PB		 2860 }
2861 }
2862 break;
c3b5bc8a
TS		 2863 case 0xa0:
2864 case 0xc0:
a86b3c64 2865 info.si_signo = TARGET_SIGSEGV;
c3b5bc8a
TS		 2866 info.si_errno = 0;
2867 info.si_code = TARGET_SEGV_MAPERR;
2868 info._sifields._sigfault._addr = env->tea;
624f7979 2869 queue_signal(env, info.si_signo, &info);
c3b5bc8a
TS		 2870 break;
2871
fdf9b3e8
FB		 2872 default:
2873 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2874 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 2875 exit(EXIT_FAILURE);
fdf9b3e8
FB		 2876 }
2877 process_pending_signals (env);
2878 }
2879}
2880#endif
2881
48733d19 2882#ifdef TARGET_CRIS
05390248 2883void cpu_loop(CPUCRISState *env)
48733d19 2884{
878096ee 2885 CPUState *cs = CPU(cris_env_get_cpu(env));
48733d19 2886 int trapnr, ret;
c227f099 2887 target_siginfo_t info;
48733d19
TS		 2888
2889 while (1) {
b040bc9c 2890 cpu_exec_start(cs);
ea3e9847 2891 trapnr = cpu_cris_exec(cs);
b040bc9c 2892 cpu_exec_end(cs);
48733d19
TS		 2893 switch (trapnr) {
2894 case 0xaa:
2895 {
a86b3c64 2896 info.si_signo = TARGET_SIGSEGV;
48733d19
TS		 2897 info.si_errno = 0;
2898 /* XXX: check env->error_code */
2899 info.si_code = TARGET_SEGV_MAPERR;
e00c1e71 2900 info._sifields._sigfault._addr = env->pregs[PR_EDA];
624f7979 2901 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2902 }
2903 break;
b6d3abda
EI		 2904 case EXCP_INTERRUPT:
2905 /* just indicate that signals should be handled asap */
2906 break;
48733d19
TS		 2907 case EXCP_BREAK:
2908 ret = do_syscall(env,
2909 env->regs[9],
2910 env->regs[10],
2911 env->regs[11],
2912 env->regs[12],
2913 env->regs[13],
2914 env->pregs[7],
5945cfcb
PM		 2915 env->pregs[11],
2916 0, 0);
62050865
TB		 2917 if (ret == -TARGET_ERESTARTSYS) {
2918 env->pc -= 2;
2919 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2920 env->regs[10] = ret;
2921 }
48733d19
TS		 2922 break;
2923 case EXCP_DEBUG:
2924 {
2925 int sig;
2926
db6b81d4 2927 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
48733d19
TS		 2928 if (sig)
2929 {
2930 info.si_signo = sig;
2931 info.si_errno = 0;
2932 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2933 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2934 }
2935 }
2936 break;
2937 default:
2938 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2939 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 2940 exit(EXIT_FAILURE);
48733d19
TS		 2941 }
2942 process_pending_signals (env);
2943 }
2944}
2945#endif
2946
b779e29e 2947#ifdef TARGET_MICROBLAZE
05390248 2948void cpu_loop(CPUMBState *env)
b779e29e 2949{
878096ee 2950 CPUState *cs = CPU(mb_env_get_cpu(env));
b779e29e 2951 int trapnr, ret;
c227f099 2952 target_siginfo_t info;
b779e29e
EI		 2953
2954 while (1) {
b040bc9c 2955 cpu_exec_start(cs);
ea3e9847 2956 trapnr = cpu_mb_exec(cs);
b040bc9c 2957 cpu_exec_end(cs);
b779e29e
EI		 2958 switch (trapnr) {
2959 case 0xaa:
2960 {
a86b3c64 2961 info.si_signo = TARGET_SIGSEGV;
b779e29e
EI		 2962 info.si_errno = 0;
2963 /* XXX: check env->error_code */
2964 info.si_code = TARGET_SEGV_MAPERR;
2965 info._sifields._sigfault._addr = 0;
2966 queue_signal(env, info.si_signo, &info);
2967 }
2968 break;
2969 case EXCP_INTERRUPT:
2970 /* just indicate that signals should be handled asap */
2971 break;
2972 case EXCP_BREAK:
2973 /* Return address is 4 bytes after the call. */
2974 env->regs[14] += 4;
d7dce494 2975 env->sregs[SR_PC] = env->regs[14];
b779e29e
EI		 2976 ret = do_syscall(env,
2977 env->regs[12],
2978 env->regs[5],
2979 env->regs[6],
2980 env->regs[7],
2981 env->regs[8],
2982 env->regs[9],
5945cfcb
PM		 2983 env->regs[10],
2984 0, 0);
4134ecfe
TB		 2985 if (ret == -TARGET_ERESTARTSYS) {
2986 /* Wind back to before the syscall. */
2987 env->sregs[SR_PC] -= 4;
2988 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2989 env->regs[3] = ret;
2990 }
d7749ab7
PM		 2991 /* All syscall exits result in guest r14 being equal to the
2992 * PC we return to, because the kernel syscall exit "rtbd" does
2993 * this. (This is true even for sigreturn(); note that r14 is
2994 * not a userspace-usable register, as the kernel may clobber it
2995 * at any point.)
2996 */
2997 env->regs[14] = env->sregs[SR_PC];
b779e29e 2998 break;
b76da7e3
EI		 2999 case EXCP_HW_EXCP:
3000 env->regs[17] = env->sregs[SR_PC] + 4;
3001 if (env->iflags & D_FLAG) {
3002 env->sregs[SR_ESR] |= 1 << 12;
3003 env->sregs[SR_PC] -= 4;
b4916d7b 3004 /* FIXME: if branch was immed, replay the imm as well. */
b76da7e3
EI		 3005 }
3006
3007 env->iflags &= ~(IMM_FLAG | D_FLAG);
3008
3009 switch (env->sregs[SR_ESR] & 31) {
22a78d64 3010 case ESR_EC_DIVZERO:
a86b3c64 3011 info.si_signo = TARGET_SIGFPE;
22a78d64
EI		 3012 info.si_errno = 0;
3013 info.si_code = TARGET_FPE_FLTDIV;
3014 info._sifields._sigfault._addr = 0;
3015 queue_signal(env, info.si_signo, &info);
3016 break;
b76da7e3 3017 case ESR_EC_FPU:
a86b3c64 3018 info.si_signo = TARGET_SIGFPE;
b76da7e3
EI		 3019 info.si_errno = 0;
3020 if (env->sregs[SR_FSR] & FSR_IO) {
3021 info.si_code = TARGET_FPE_FLTINV;
3022 }
3023 if (env->sregs[SR_FSR] & FSR_DZ) {
3024 info.si_code = TARGET_FPE_FLTDIV;
3025 }
3026 info._sifields._sigfault._addr = 0;
3027 queue_signal(env, info.si_signo, &info);
3028 break;
3029 default:
3030 printf ("Unhandled hw-exception: 0x%x\n",
2e42d52d 3031 env->sregs[SR_ESR] & ESR_EC_MASK);
878096ee 3032 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3033 exit(EXIT_FAILURE);
b76da7e3
EI		 3034 break;
3035 }
3036 break;
b779e29e
EI		 3037 case EXCP_DEBUG:
3038 {
3039 int sig;
3040
db6b81d4 3041 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
b779e29e
EI		 3042 if (sig)
3043 {
3044 info.si_signo = sig;
3045 info.si_errno = 0;
3046 info.si_code = TARGET_TRAP_BRKPT;
3047 queue_signal(env, info.si_signo, &info);
3048 }
3049 }
3050 break;
3051 default:
3052 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3053 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3054 exit(EXIT_FAILURE);
b779e29e
EI		 3055 }
3056 process_pending_signals (env);
3057 }
3058}
3059#endif
3060
e6e5906b
PB		 3061#ifdef TARGET_M68K
3062
3063void cpu_loop(CPUM68KState *env)
3064{
878096ee 3065 CPUState *cs = CPU(m68k_env_get_cpu(env));
e6e5906b
PB		 3066 int trapnr;
3067 unsigned int n;
c227f099 3068 target_siginfo_t info;
0429a971 3069 TaskState *ts = cs->opaque;
3b46e624 3070
e6e5906b 3071 for(;;) {
b040bc9c 3072 cpu_exec_start(cs);
ea3e9847 3073 trapnr = cpu_m68k_exec(cs);
b040bc9c 3074 cpu_exec_end(cs);
e6e5906b
PB		 3075 switch(trapnr) {
3076 case EXCP_ILLEGAL:
3077 {
3078 if (ts->sim_syscalls) {
3079 uint16_t nr;
d8d5119c 3080 get_user_u16(nr, env->pc + 2);
e6e5906b
PB		 3081 env->pc += 4;
3082 do_m68k_simcall(env, nr);
3083 } else {
3084 goto do_sigill;
3085 }
3086 }
3087 break;
a87295e8 3088 case EXCP_HALT_INSN:
e6e5906b 3089 /* Semihosing syscall. */
a87295e8 3090 env->pc += 4;
e6e5906b
PB		 3091 do_m68k_semihosting(env, env->dregs[0]);
3092 break;
3093 case EXCP_LINEA:
3094 case EXCP_LINEF:
3095 case EXCP_UNSUPPORTED:
3096 do_sigill:
a86b3c64 3097 info.si_signo = TARGET_SIGILL;
e6e5906b
PB		 3098 info.si_errno = 0;
3099 info.si_code = TARGET_ILL_ILLOPN;
3100 info._sifields._sigfault._addr = env->pc;
624f7979 3101 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3102 break;
3103 case EXCP_TRAP0:
3104 {
7ccb84a9 3105 abi_long ret;
e6e5906b
PB		 3106 ts->sim_syscalls = 0;
3107 n = env->dregs[0];
3108 env->pc += 2;
7ccb84a9
TB		 3109 ret = do_syscall(env,
3110 n,
3111 env->dregs[1],
3112 env->dregs[2],
3113 env->dregs[3],
3114 env->dregs[4],
3115 env->dregs[5],
3116 env->aregs[0],
3117 0, 0);
3118 if (ret == -TARGET_ERESTARTSYS) {
3119 env->pc -= 2;
3120 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3121 env->dregs[0] = ret;
3122 }
e6e5906b
PB		 3123 }
3124 break;
3125 case EXCP_INTERRUPT:
3126 /* just indicate that signals should be handled asap */
3127 break;
3128 case EXCP_ACCESS:
3129 {
a86b3c64 3130 info.si_signo = TARGET_SIGSEGV;
e6e5906b
PB		 3131 info.si_errno = 0;
3132 /* XXX: check env->error_code */
3133 info.si_code = TARGET_SEGV_MAPERR;
3134 info._sifields._sigfault._addr = env->mmu.ar;
624f7979 3135 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3136 }
3137 break;
3138 case EXCP_DEBUG:
3139 {
3140 int sig;
3141
db6b81d4 3142 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
e6e5906b
PB		 3143 if (sig)
3144 {
3145 info.si_signo = sig;
3146 info.si_errno = 0;
3147 info.si_code = TARGET_TRAP_BRKPT;
624f7979 3148 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3149 }
3150 }
3151 break;
3152 default:
120a9848 3153 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
e6e5906b
PB		 3154 abort();
3155 }
3156 process_pending_signals(env);
3157 }
3158}
3159#endif /* TARGET_M68K */
3160
7a3148a9 3161#ifdef TARGET_ALPHA
6910b8f6
RH		 3162static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3163{
3164 target_ulong addr, val, tmp;
3165 target_siginfo_t info;
3166 int ret = 0;
3167
3168 addr = env->lock_addr;
3169 tmp = env->lock_st_addr;
3170 env->lock_addr = -1;
3171 env->lock_st_addr = 0;
3172
3173 start_exclusive();
3174 mmap_lock();
3175
3176 if (addr == tmp) {
3177 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3178 goto do_sigsegv;
3179 }
3180
3181 if (val == env->lock_value) {
3182 tmp = env->ir[reg];
3183 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3184 goto do_sigsegv;
3185 }
3186 ret = 1;
3187 }
3188 }
3189 env->ir[reg] = ret;
3190 env->pc += 4;
3191
3192 mmap_unlock();
3193 end_exclusive();
3194 return;
3195
3196 do_sigsegv:
3197 mmap_unlock();
3198 end_exclusive();
3199
3200 info.si_signo = TARGET_SIGSEGV;
3201 info.si_errno = 0;
3202 info.si_code = TARGET_SEGV_MAPERR;
3203 info._sifields._sigfault._addr = addr;
3204 queue_signal(env, TARGET_SIGSEGV, &info);
3205}
3206
05390248 3207void cpu_loop(CPUAlphaState *env)
7a3148a9 3208{
878096ee 3209 CPUState *cs = CPU(alpha_env_get_cpu(env));
e96efcfc 3210 int trapnr;
c227f099 3211 target_siginfo_t info;
6049f4f8 3212 abi_long sysret;
3b46e624 3213
7a3148a9 3214 while (1) {
b040bc9c 3215 cpu_exec_start(cs);
ea3e9847 3216 trapnr = cpu_alpha_exec(cs);
b040bc9c 3217 cpu_exec_end(cs);
3b46e624 3218
ac316ca4
RH		 3219 /* All of the traps imply a transition through PALcode, which
3220 implies an REI instruction has been executed. Which means
3221 that the intr_flag should be cleared. */
3222 env->intr_flag = 0;
3223
7a3148a9
JM		 3224 switch (trapnr) {
3225 case EXCP_RESET:
3226 fprintf(stderr, "Reset requested. Exit\n");
4d1275c2 3227 exit(EXIT_FAILURE);
7a3148a9
JM		 3228 break;
3229 case EXCP_MCHK:
3230 fprintf(stderr, "Machine check exception. Exit\n");
4d1275c2 3231 exit(EXIT_FAILURE);
7a3148a9 3232 break;
07b6c13b
RH		 3233 case EXCP_SMP_INTERRUPT:
3234 case EXCP_CLK_INTERRUPT:
3235 case EXCP_DEV_INTERRUPT:
5fafdf24 3236 fprintf(stderr, "External interrupt. Exit\n");
4d1275c2 3237 exit(EXIT_FAILURE);
7a3148a9 3238 break;
07b6c13b 3239 case EXCP_MMFAULT:
6910b8f6 3240 env->lock_addr = -1;
6049f4f8
RH		 3241 info.si_signo = TARGET_SIGSEGV;
3242 info.si_errno = 0;
129d8aa5 3243 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
0be1d07c 3244 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
129d8aa5 3245 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3246 queue_signal(env, info.si_signo, &info);
7a3148a9 3247 break;
7a3148a9 3248 case EXCP_UNALIGN:
6910b8f6 3249 env->lock_addr = -1;
6049f4f8
RH		 3250 info.si_signo = TARGET_SIGBUS;
3251 info.si_errno = 0;
3252 info.si_code = TARGET_BUS_ADRALN;
129d8aa5 3253 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3254 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3255 break;
3256 case EXCP_OPCDEC:
6049f4f8 3257 do_sigill:
6910b8f6 3258 env->lock_addr = -1;
6049f4f8
RH		 3259 info.si_signo = TARGET_SIGILL;
3260 info.si_errno = 0;
3261 info.si_code = TARGET_ILL_ILLOPC;
3262 info._sifields._sigfault._addr = env->pc;
3263 queue_signal(env, info.si_signo, &info);
7a3148a9 3264 break;
07b6c13b
RH		 3265 case EXCP_ARITH:
3266 env->lock_addr = -1;
3267 info.si_signo = TARGET_SIGFPE;
3268 info.si_errno = 0;
3269 info.si_code = TARGET_FPE_FLTINV;
3270 info._sifields._sigfault._addr = env->pc;
3271 queue_signal(env, info.si_signo, &info);
3272 break;
7a3148a9 3273 case EXCP_FEN:
6049f4f8 3274 /* No-op. Linux simply re-enables the FPU. */
7a3148a9 3275 break;
07b6c13b 3276 case EXCP_CALL_PAL:
6910b8f6 3277 env->lock_addr = -1;
07b6c13b 3278 switch (env->error_code) {
6049f4f8
RH		 3279 case 0x80:
3280 /* BPT */
3281 info.si_signo = TARGET_SIGTRAP;
3282 info.si_errno = 0;
3283 info.si_code = TARGET_TRAP_BRKPT;
3284 info._sifields._sigfault._addr = env->pc;
3285 queue_signal(env, info.si_signo, &info);
3286 break;
3287 case 0x81:
3288 /* BUGCHK */
3289 info.si_signo = TARGET_SIGTRAP;
3290 info.si_errno = 0;
3291 info.si_code = 0;
3292 info._sifields._sigfault._addr = env->pc;
3293 queue_signal(env, info.si_signo, &info);
3294 break;
3295 case 0x83:
3296 /* CALLSYS */
3297 trapnr = env->ir[IR_V0];
3298 sysret = do_syscall(env, trapnr,
3299 env->ir[IR_A0], env->ir[IR_A1],
3300 env->ir[IR_A2], env->ir[IR_A3],
5945cfcb
PM		 3301 env->ir[IR_A4], env->ir[IR_A5],
3302 0, 0);
338c858c
TB		 3303 if (sysret == -TARGET_ERESTARTSYS) {
3304 env->pc -= 4;
3305 break;
3306 }
3307 if (sysret == -TARGET_QEMU_ESIGRETURN) {
a5b3b13b
RH		 3308 break;
3309 }
3310 /* Syscall writes 0 to V0 to bypass error check, similar
0e141977
RH		 3311 to how this is handled internal to Linux kernel.
3312 (Ab)use trapnr temporarily as boolean indicating error. */
3313 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3314 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3315 env->ir[IR_A3] = trapnr;
6049f4f8
RH		 3316 break;
3317 case 0x86:
3318 /* IMB */
3319 /* ??? We can probably elide the code using page_unprotect
3320 that is checking for self-modifying code. Instead we
3321 could simply call tb_flush here. Until we work out the
3322 changes required to turn off the extra write protection,
3323 this can be a no-op. */
3324 break;
3325 case 0x9E:
3326 /* RDUNIQUE */
3327 /* Handled in the translator for usermode. */
3328 abort();
3329 case 0x9F:
3330 /* WRUNIQUE */
3331 /* Handled in the translator for usermode. */
3332 abort();
3333 case 0xAA:
3334 /* GENTRAP */
3335 info.si_signo = TARGET_SIGFPE;
3336 switch (env->ir[IR_A0]) {
3337 case TARGET_GEN_INTOVF:
3338 info.si_code = TARGET_FPE_INTOVF;
3339 break;
3340 case TARGET_GEN_INTDIV:
3341 info.si_code = TARGET_FPE_INTDIV;
3342 break;
3343 case TARGET_GEN_FLTOVF:
3344 info.si_code = TARGET_FPE_FLTOVF;
3345 break;
3346 case TARGET_GEN_FLTUND:
3347 info.si_code = TARGET_FPE_FLTUND;
3348 break;
3349 case TARGET_GEN_FLTINV:
3350 info.si_code = TARGET_FPE_FLTINV;
3351 break;
3352 case TARGET_GEN_FLTINE:
3353 info.si_code = TARGET_FPE_FLTRES;
3354 break;
3355 case TARGET_GEN_ROPRAND:
3356 info.si_code = 0;
3357 break;
3358 default:
3359 info.si_signo = TARGET_SIGTRAP;
3360 info.si_code = 0;
3361 break;
3362 }
3363 info.si_errno = 0;
3364 info._sifields._sigfault._addr = env->pc;
3365 queue_signal(env, info.si_signo, &info);
3366 break;
3367 default:
3368 goto do_sigill;
3369 }
7a3148a9 3370 break;
7a3148a9 3371 case EXCP_DEBUG:
db6b81d4 3372 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
6049f4f8 3373 if (info.si_signo) {
6910b8f6 3374 env->lock_addr = -1;
6049f4f8
RH		 3375 info.si_errno = 0;
3376 info.si_code = TARGET_TRAP_BRKPT;
3377 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3378 }
3379 break;
6910b8f6
RH		 3380 case EXCP_STL_C:
3381 case EXCP_STQ_C:
3382 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3383 break;
d0f20495
RH		 3384 case EXCP_INTERRUPT:
3385 /* Just indicate that signals should be handled asap. */
3386 break;
7a3148a9
JM		 3387 default:
3388 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3389 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3390 exit(EXIT_FAILURE);
7a3148a9
JM		 3391 }
3392 process_pending_signals (env);
3393 }
3394}
3395#endif /* TARGET_ALPHA */
3396
a4c075f1
UH		 3397#ifdef TARGET_S390X
3398void cpu_loop(CPUS390XState *env)
3399{
878096ee 3400 CPUState *cs = CPU(s390_env_get_cpu(env));
d5a103cd 3401 int trapnr, n, sig;
a4c075f1 3402 target_siginfo_t info;
d5a103cd 3403 target_ulong addr;
47405ab6 3404 abi_long ret;
a4c075f1
UH		 3405
3406 while (1) {
b040bc9c 3407 cpu_exec_start(cs);
ea3e9847 3408 trapnr = cpu_s390x_exec(cs);
b040bc9c 3409 cpu_exec_end(cs);
a4c075f1
UH		 3410 switch (trapnr) {
3411 case EXCP_INTERRUPT:
d5a103cd 3412 /* Just indicate that signals should be handled asap. */
a4c075f1 3413 break;
a4c075f1 3414
d5a103cd
RH		 3415 case EXCP_SVC:
3416 n = env->int_svc_code;
3417 if (!n) {
3418 /* syscalls > 255 */
3419 n = env->regs[1];
a4c075f1 3420 }
d5a103cd 3421 env->psw.addr += env->int_svc_ilen;
47405ab6
TB		 3422 ret = do_syscall(env, n, env->regs[2], env->regs[3],
3423 env->regs[4], env->regs[5],
3424 env->regs[6], env->regs[7], 0, 0);
3425 if (ret == -TARGET_ERESTARTSYS) {
3426 env->psw.addr -= env->int_svc_ilen;
3427 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3428 env->regs[2] = ret;
3429 }
a4c075f1 3430 break;
d5a103cd
RH		 3431
3432 case EXCP_DEBUG:
db6b81d4 3433 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d5a103cd
RH		 3434 if (sig) {
3435 n = TARGET_TRAP_BRKPT;
3436 goto do_signal_pc;
a4c075f1
UH		 3437 }
3438 break;
d5a103cd
RH		 3439 case EXCP_PGM:
3440 n = env->int_pgm_code;
3441 switch (n) {
3442 case PGM_OPERATION:
3443 case PGM_PRIVILEGED:
a86b3c64 3444 sig = TARGET_SIGILL;
d5a103cd
RH		 3445 n = TARGET_ILL_ILLOPC;
3446 goto do_signal_pc;
3447 case PGM_PROTECTION:
3448 case PGM_ADDRESSING:
a86b3c64 3449 sig = TARGET_SIGSEGV;
a4c075f1 3450 /* XXX: check env->error_code */
d5a103cd
RH		 3451 n = TARGET_SEGV_MAPERR;
3452 addr = env->__excp_addr;
3453 goto do_signal;
3454 case PGM_EXECUTE:
3455 case PGM_SPECIFICATION:
3456 case PGM_SPECIAL_OP:
3457 case PGM_OPERAND:
3458 do_sigill_opn:
a86b3c64 3459 sig = TARGET_SIGILL;
d5a103cd
RH		 3460 n = TARGET_ILL_ILLOPN;
3461 goto do_signal_pc;
3462
3463 case PGM_FIXPT_OVERFLOW:
a86b3c64 3464 sig = TARGET_SIGFPE;
d5a103cd
RH		 3465 n = TARGET_FPE_INTOVF;
3466 goto do_signal_pc;
3467 case PGM_FIXPT_DIVIDE:
a86b3c64 3468 sig = TARGET_SIGFPE;
d5a103cd
RH		 3469 n = TARGET_FPE_INTDIV;
3470 goto do_signal_pc;
3471
3472 case PGM_DATA:
3473 n = (env->fpc >> 8) & 0xff;
3474 if (n == 0xff) {
3475 /* compare-and-trap */
3476 goto do_sigill_opn;
3477 } else {
3478 /* An IEEE exception, simulated or otherwise. */
3479 if (n & 0x80) {
3480 n = TARGET_FPE_FLTINV;
3481 } else if (n & 0x40) {
3482 n = TARGET_FPE_FLTDIV;
3483 } else if (n & 0x20) {
3484 n = TARGET_FPE_FLTOVF;
3485 } else if (n & 0x10) {
3486 n = TARGET_FPE_FLTUND;
3487 } else if (n & 0x08) {
3488 n = TARGET_FPE_FLTRES;
3489 } else {
3490 /* ??? Quantum exception; BFP, DFP error. */
3491 goto do_sigill_opn;
3492 }
a86b3c64 3493 sig = TARGET_SIGFPE;
d5a103cd
RH		 3494 goto do_signal_pc;
3495 }
3496
3497 default:
3498 fprintf(stderr, "Unhandled program exception: %#x\n", n);
878096ee 3499 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3500 exit(EXIT_FAILURE);
a4c075f1
UH		 3501 }
3502 break;
d5a103cd
RH		 3503
3504 do_signal_pc:
3505 addr = env->psw.addr;
3506 do_signal:
3507 info.si_signo = sig;
3508 info.si_errno = 0;
3509 info.si_code = n;
3510 info._sifields._sigfault._addr = addr;
3511 queue_signal(env, info.si_signo, &info);
a4c075f1 3512 break;
d5a103cd 3513
a4c075f1 3514 default:
d5a103cd 3515 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
878096ee 3516 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3517 exit(EXIT_FAILURE);
a4c075f1
UH		 3518 }
3519 process_pending_signals (env);
3520 }
3521}
3522
3523#endif /* TARGET_S390X */
3524
b16189b2
CG		 3525#ifdef TARGET_TILEGX
3526
b16189b2
CG		 3527static void gen_sigill_reg(CPUTLGState *env)
3528{
3529 target_siginfo_t info;
3530
3531 info.si_signo = TARGET_SIGILL;
3532 info.si_errno = 0;
3533 info.si_code = TARGET_ILL_PRVREG;
3534 info._sifields._sigfault._addr = env->pc;
3535 queue_signal(env, info.si_signo, &info);
3536}
3537
a0577d2a 3538static void do_signal(CPUTLGState *env, int signo, int sigcode)
dd8070d8
CG		 3539{
3540 target_siginfo_t info;
3541
a0577d2a 3542 info.si_signo = signo;
dd8070d8 3543 info.si_errno = 0;
dd8070d8 3544 info._sifields._sigfault._addr = env->pc;
a0577d2a
RH		 3545
3546 if (signo == TARGET_SIGSEGV) {
3547 /* The passed in sigcode is a dummy; check for a page mapping
3548 and pass either MAPERR or ACCERR. */
3549 target_ulong addr = env->excaddr;
3550 info._sifields._sigfault._addr = addr;
3551 if (page_check_range(addr, 1, PAGE_VALID) < 0) {
3552 sigcode = TARGET_SEGV_MAPERR;
3553 } else {
3554 sigcode = TARGET_SEGV_ACCERR;
3555 }
3556 }
3557 info.si_code = sigcode;
3558
dd8070d8
CG		 3559 queue_signal(env, info.si_signo, &info);
3560}
3561
a0577d2a
RH		 3562static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
3563{
3564 env->excaddr = addr;
3565 do_signal(env, TARGET_SIGSEGV, 0);
3566}
3567
0583b233
RH		 3568static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
3569{
3570 if (unlikely(reg >= TILEGX_R_COUNT)) {
3571 switch (reg) {
3572 case TILEGX_R_SN:
3573 case TILEGX_R_ZERO:
3574 return;
3575 case TILEGX_R_IDN0:
3576 case TILEGX_R_IDN1:
3577 case TILEGX_R_UDN0:
3578 case TILEGX_R_UDN1:
3579 case TILEGX_R_UDN2:
3580 case TILEGX_R_UDN3:
3581 gen_sigill_reg(env);
3582 return;
3583 default:
3584 g_assert_not_reached();
3585 }
3586 }
3587 env->regs[reg] = val;
3588}
3589
3590/*
3591 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
3592 * memory at the address held in the first source register. If the values are
3593 * not equal, then no memory operation is performed. If the values are equal,
3594 * the 8-byte quantity from the second source register is written into memory
3595 * at the address held in the first source register. In either case, the result
3596 * of the instruction is the value read from memory. The compare and write to
3597 * memory are atomic and thus can be used for synchronization purposes. This
3598 * instruction only operates for addresses aligned to a 8-byte boundary.
3599 * Unaligned memory access causes an Unaligned Data Reference interrupt.
3600 *
3601 * Functional Description (64-bit)
3602 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
3603 * rf[Dest] = memVal;
3604 * if (memVal == SPR[CmpValueSPR])
3605 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
3606 *
3607 * Functional Description (32-bit)
3608 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
3609 * rf[Dest] = memVal;
3610 * if (memVal == signExtend32 (SPR[CmpValueSPR]))
3611 * memoryWriteWord (rf[SrcA], rf[SrcB]);
3612 *
3613 *
3614 * This function also processes exch and exch4 which need not process SPR.
3615 */
3616static void do_exch(CPUTLGState *env, bool quad, bool cmp)
3617{
3618 target_ulong addr;
3619 target_long val, sprval;
3620
3621 start_exclusive();
3622
3623 addr = env->atomic_srca;
3624 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3625 goto sigsegv_maperr;
3626 }
3627
3628 if (cmp) {
3629 if (quad) {
3630 sprval = env->spregs[TILEGX_SPR_CMPEXCH];
3631 } else {
3632 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
3633 }
3634 }
3635
3636 if (!cmp || val == sprval) {
3637 target_long valb = env->atomic_srcb;
3638 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3639 goto sigsegv_maperr;
3640 }
3641 }
3642
3643 set_regval(env, env->atomic_dstr, val);
3644 end_exclusive();
3645 return;
3646
3647 sigsegv_maperr:
3648 end_exclusive();
3649 gen_sigsegv_maperr(env, addr);
3650}
3651
3652static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
3653{
3654 int8_t write = 1;
3655 target_ulong addr;
3656 target_long val, valb;
3657
3658 start_exclusive();
3659
3660 addr = env->atomic_srca;
3661 valb = env->atomic_srcb;
3662 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3663 goto sigsegv_maperr;
3664 }
3665
3666 switch (trapnr) {
3667 case TILEGX_EXCP_OPCODE_FETCHADD:
3668 case TILEGX_EXCP_OPCODE_FETCHADD4:
3669 valb += val;
3670 break;
3671 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3672 valb += val;
3673 if (valb < 0) {
3674 write = 0;
3675 }
3676 break;
3677 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3678 valb += val;
3679 if ((int32_t)valb < 0) {
3680 write = 0;
3681 }
3682 break;
3683 case TILEGX_EXCP_OPCODE_FETCHAND:
3684 case TILEGX_EXCP_OPCODE_FETCHAND4:
3685 valb &= val;
3686 break;
3687 case TILEGX_EXCP_OPCODE_FETCHOR:
3688 case TILEGX_EXCP_OPCODE_FETCHOR4:
3689 valb |= val;
3690 break;
3691 default:
3692 g_assert_not_reached();
3693 }
3694
3695 if (write) {
3696 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3697 goto sigsegv_maperr;
3698 }
3699 }
3700
3701 set_regval(env, env->atomic_dstr, val);
3702 end_exclusive();
3703 return;
3704
3705 sigsegv_maperr:
3706 end_exclusive();
3707 gen_sigsegv_maperr(env, addr);
3708}
3709
b16189b2
CG		 3710void cpu_loop(CPUTLGState *env)
3711{
3712 CPUState *cs = CPU(tilegx_env_get_cpu(env));
3713 int trapnr;
3714
3715 while (1) {
3716 cpu_exec_start(cs);
3717 trapnr = cpu_tilegx_exec(cs);
3718 cpu_exec_end(cs);
3719 switch (trapnr) {
3720 case TILEGX_EXCP_SYSCALL:
a9175169
PM		 3721 {
3722 abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR],
3723 env->regs[0], env->regs[1],
3724 env->regs[2], env->regs[3],
3725 env->regs[4], env->regs[5],
3726 env->regs[6], env->regs[7]);
3727 if (ret == -TARGET_ERESTARTSYS) {
3728 env->pc -= 8;
3729 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3730 env->regs[TILEGX_R_RE] = ret;
3731 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0;
3732 }
b16189b2 3733 break;
a9175169 3734 }
0583b233
RH		 3735 case TILEGX_EXCP_OPCODE_EXCH:
3736 do_exch(env, true, false);
3737 break;
3738 case TILEGX_EXCP_OPCODE_EXCH4:
3739 do_exch(env, false, false);
3740 break;
3741 case TILEGX_EXCP_OPCODE_CMPEXCH:
3742 do_exch(env, true, true);
3743 break;
3744 case TILEGX_EXCP_OPCODE_CMPEXCH4:
3745 do_exch(env, false, true);
3746 break;
3747 case TILEGX_EXCP_OPCODE_FETCHADD:
3748 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3749 case TILEGX_EXCP_OPCODE_FETCHAND:
3750 case TILEGX_EXCP_OPCODE_FETCHOR:
3751 do_fetch(env, trapnr, true);
3752 break;
3753 case TILEGX_EXCP_OPCODE_FETCHADD4:
3754 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3755 case TILEGX_EXCP_OPCODE_FETCHAND4:
3756 case TILEGX_EXCP_OPCODE_FETCHOR4:
3757 do_fetch(env, trapnr, false);
3758 break;
dd8070d8 3759 case TILEGX_EXCP_SIGNAL:
a0577d2a 3760 do_signal(env, env->signo, env->sigcode);
dd8070d8 3761 break;
b16189b2
CG		 3762 case TILEGX_EXCP_REG_IDN_ACCESS:
3763 case TILEGX_EXCP_REG_UDN_ACCESS:
3764 gen_sigill_reg(env);
3765 break;
3766 default:
3767 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
3768 g_assert_not_reached();
3769 }
3770 process_pending_signals(env);
3771 }
3772}
3773
3774#endif
3775
a2247f8e 3776THREAD CPUState *thread_cpu;
59faf6d6 3777
edf8e2af
MW		 3778void task_settid(TaskState *ts)
3779{
3780 if (ts->ts_tid == 0) {
edf8e2af 3781 ts->ts_tid = (pid_t)syscall(SYS_gettid);
edf8e2af
MW		 3782 }
3783}
3784
3785void stop_all_tasks(void)
3786{
3787 /*
3788 * We trust that when using NPTL, start_exclusive()
3789 * handles thread stopping correctly.
3790 */
3791 start_exclusive();
3792}
3793
c3a92833 3794/* Assumes contents are already zeroed. */
624f7979
PB		 3795void init_task_state(TaskState *ts)
3796{
3797 int i;
3798
624f7979
PB		 3799 ts->used = 1;
3800 ts->first_free = ts->sigqueue_table;
3801 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3802 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3803 }
3804 ts->sigqueue_table[i].next = NULL;
3805}
fc9c5412 3806
30ba0ee5
AF		 3807CPUArchState *cpu_copy(CPUArchState *env)
3808{
ff4700b0 3809 CPUState *cpu = ENV_GET_CPU(env);
2994fd96 3810 CPUState *new_cpu = cpu_init(cpu_model);
61c7480f 3811 CPUArchState *new_env = new_cpu->env_ptr;
30ba0ee5
AF		 3812 CPUBreakpoint *bp;
3813 CPUWatchpoint *wp;
30ba0ee5
AF		 3814
3815 /* Reset non arch specific state */
75a34036 3816 cpu_reset(new_cpu);
30ba0ee5
AF		 3817
3818 memcpy(new_env, env, sizeof(CPUArchState));
3819
3820 /* Clone all break/watchpoints.
3821 Note: Once we support ptrace with hw-debug register access, make sure
3822 BP_CPU break/watchpoints are handled correctly on clone. */
1d085f6c
TB		 3823 QTAILQ_INIT(&new_cpu->breakpoints);
3824 QTAILQ_INIT(&new_cpu->watchpoints);
f0c3c505 3825 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
b3310ab3 3826 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
30ba0ee5 3827 }
ff4700b0 3828 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
05068c0d 3829 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
30ba0ee5 3830 }
30ba0ee5
AF		 3831
3832 return new_env;
3833}
3834
fc9c5412
JS		 3835static void handle_arg_help(const char *arg)
3836{
4d1275c2 3837 usage(EXIT_SUCCESS);
fc9c5412
JS		 3838}
3839
3840static void handle_arg_log(const char *arg)
3841{
3842 int mask;
fc9c5412 3843
4fde1eba 3844 mask = qemu_str_to_log_mask(arg);
fc9c5412 3845 if (!mask) {
59a6fa6e 3846 qemu_print_log_usage(stdout);
4d1275c2 3847 exit(EXIT_FAILURE);
fc9c5412 3848 }
f2937a33 3849 qemu_log_needs_buffers();
24537a01 3850 qemu_set_log(mask);
fc9c5412
JS		 3851}
3852
50171d42
CWR		 3853static void handle_arg_log_filename(const char *arg)
3854{
9a7e5424 3855 qemu_set_log_filename(arg);
50171d42
CWR		 3856}
3857
fc9c5412
JS		 3858static void handle_arg_set_env(const char *arg)
3859{
3860 char *r, *p, *token;
3861 r = p = strdup(arg);
3862 while ((token = strsep(&p, ",")) != NULL) {
3863 if (envlist_setenv(envlist, token) != 0) {
4d1275c2 3864 usage(EXIT_FAILURE);
fc9c5412
JS		 3865 }
3866 }
3867 free(r);
3868}
3869
3870static void handle_arg_unset_env(const char *arg)
3871{
3872 char *r, *p, *token;
3873 r = p = strdup(arg);
3874 while ((token = strsep(&p, ",")) != NULL) {
3875 if (envlist_unsetenv(envlist, token) != 0) {
4d1275c2 3876 usage(EXIT_FAILURE);
fc9c5412
JS		 3877 }
3878 }
3879 free(r);
3880}
3881
3882static void handle_arg_argv0(const char *arg)
3883{
3884 argv0 = strdup(arg);
3885}
3886
3887static void handle_arg_stack_size(const char *arg)
3888{
3889 char *p;
3890 guest_stack_size = strtoul(arg, &p, 0);
3891 if (guest_stack_size == 0) {
4d1275c2 3892 usage(EXIT_FAILURE);
fc9c5412
JS		 3893 }
3894
3895 if (*p == 'M') {
3896 guest_stack_size *= 1024 * 1024;
3897 } else if (*p == 'k' || *p == 'K') {
3898 guest_stack_size *= 1024;
3899 }
3900}
3901
3902static void handle_arg_ld_prefix(const char *arg)
3903{
3904 interp_prefix = strdup(arg);
3905}
3906
3907static void handle_arg_pagesize(const char *arg)
3908{
3909 qemu_host_page_size = atoi(arg);
3910 if (qemu_host_page_size == 0 ||
3911 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3912 fprintf(stderr, "page size must be a power of two\n");
4d1275c2 3913 exit(EXIT_FAILURE);
fc9c5412
JS		 3914 }
3915}
3916
c5e4a5a9
MR		 3917static void handle_arg_randseed(const char *arg)
3918{
3919 unsigned long long seed;
3920
3921 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3922 fprintf(stderr, "Invalid seed number: %s\n", arg);
4d1275c2 3923 exit(EXIT_FAILURE);
c5e4a5a9
MR		 3924 }
3925 srand(seed);
3926}
3927
fc9c5412
JS		 3928static void handle_arg_gdb(const char *arg)
3929{
3930 gdbstub_port = atoi(arg);
3931}
3932
3933static void handle_arg_uname(const char *arg)
3934{
3935 qemu_uname_release = strdup(arg);
3936}
3937
3938static void handle_arg_cpu(const char *arg)
3939{
3940 cpu_model = strdup(arg);
c8057f95 3941 if (cpu_model == NULL || is_help_option(cpu_model)) {
fc9c5412 3942 /* XXX: implement xxx_cpu_list for targets that still miss it */
e916cbf8
PM		 3943#if defined(cpu_list)
3944 cpu_list(stdout, &fprintf);
fc9c5412 3945#endif
4d1275c2 3946 exit(EXIT_FAILURE);
fc9c5412
JS		 3947 }
3948}
3949
fc9c5412
JS		 3950static void handle_arg_guest_base(const char *arg)
3951{
3952 guest_base = strtol(arg, NULL, 0);
3953 have_guest_base = 1;
3954}
3955
3956static void handle_arg_reserved_va(const char *arg)
3957{
3958 char *p;
3959 int shift = 0;
3960 reserved_va = strtoul(arg, &p, 0);
3961 switch (*p) {
3962 case 'k':
3963 case 'K':
3964 shift = 10;
3965 break;
3966 case 'M':
3967 shift = 20;
3968 break;
3969 case 'G':
3970 shift = 30;
3971 break;
3972 }
3973 if (shift) {
3974 unsigned long unshifted = reserved_va;
3975 p++;
3976 reserved_va <<= shift;
3977 if (((reserved_va >> shift) != unshifted)
3978#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3979 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3980#endif
3981 ) {
3982 fprintf(stderr, "Reserved virtual address too big\n");
4d1275c2 3983 exit(EXIT_FAILURE);
fc9c5412
JS		 3984 }
3985 }
3986 if (*p) {
3987 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
4d1275c2 3988 exit(EXIT_FAILURE);
fc9c5412
JS		 3989 }
3990}
fc9c5412
JS		 3991
3992static void handle_arg_singlestep(const char *arg)
3993{
3994 singlestep = 1;
3995}
3996
3997static void handle_arg_strace(const char *arg)
3998{
3999 do_strace = 1;
4000}
4001
4002static void handle_arg_version(const char *arg)
4003{
2e59915d 4004 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
fc9c5412 4005 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
4d1275c2 4006 exit(EXIT_SUCCESS);
fc9c5412
JS		 4007}
4008
4009struct qemu_argument {
4010 const char *argv;
4011 const char *env;
4012 bool has_arg;
4013 void (*handle_opt)(const char *arg);
4014 const char *example;
4015 const char *help;
4016};
4017
42644cee 4018static const struct qemu_argument arg_table[] = {
fc9c5412
JS		 4019 {"h", "", false, handle_arg_help,
4020 "", "print this help"},
daaf8c8e
MI		 4021 {"help", "", false, handle_arg_help,
4022 "", ""},
fc9c5412
JS		 4023 {"g", "QEMU_GDB", true, handle_arg_gdb,
4024 "port", "wait gdb connection to 'port'"},
4025 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
4026 "path", "set the elf interpreter prefix to 'path'"},
4027 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
4028 "size", "set the stack size to 'size' bytes"},
4029 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
c8057f95 4030 "model", "select CPU (-cpu help for list)"},
fc9c5412
JS		 4031 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
4032 "var=value", "sets targets environment variable (see below)"},
4033 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
4034 "var", "unsets targets environment variable (see below)"},
4035 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
4036 "argv0", "forces target process argv[0] to be 'argv0'"},
4037 {"r", "QEMU_UNAME", true, handle_arg_uname,
4038 "uname", "set qemu uname release string to 'uname'"},
fc9c5412
JS		 4039 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
4040 "address", "set guest_base address to 'address'"},
4041 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
4042 "size", "reserve 'size' bytes for guest virtual address space"},
fc9c5412 4043 {"d", "QEMU_LOG", true, handle_arg_log,
989b697d
PM		 4044 "item[,...]", "enable logging of specified items "
4045 "(use '-d help' for a list of items)"},
50171d42 4046 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
989b697d 4047 "logfile", "write logs to 'logfile' (default stderr)"},
fc9c5412
JS		 4048 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
4049 "pagesize", "set the host page size to 'pagesize'"},
4050 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
4051 "", "run in singlestep mode"},
4052 {"strace", "QEMU_STRACE", false, handle_arg_strace,
4053 "", "log system calls"},
c5e4a5a9
MR		 4054 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
4055 "", "Seed for pseudo-random number generator"},
fc9c5412 4056 {"version", "QEMU_VERSION", false, handle_arg_version,
1386d4c0 4057 "", "display version information and exit"},
fc9c5412
JS		 4058 {NULL, NULL, false, NULL, NULL, NULL}
4059};
4060
d03f9c32 4061static void usage(int exitcode)
fc9c5412 4062{
42644cee 4063 const struct qemu_argument *arginfo;
fc9c5412
JS		 4064 int maxarglen;
4065 int maxenvlen;
4066
2e59915d
PB		 4067 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
4068 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
fc9c5412
JS		 4069 "\n"
4070 "Options and associated environment variables:\n"
4071 "\n");
4072
63ec54d7
PM		 4073 /* Calculate column widths. We must always have at least enough space
4074 * for the column header.
4075 */
4076 maxarglen = strlen("Argument");
4077 maxenvlen = strlen("Env-variable");
fc9c5412
JS		 4078
4079 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
63ec54d7
PM		 4080 int arglen = strlen(arginfo->argv);
4081 if (arginfo->has_arg) {
4082 arglen += strlen(arginfo->example) + 1;
4083 }
fc9c5412
JS		 4084 if (strlen(arginfo->env) > maxenvlen) {
4085 maxenvlen = strlen(arginfo->env);
4086 }
63ec54d7
PM		 4087 if (arglen > maxarglen) {
4088 maxarglen = arglen;
fc9c5412
JS		 4089 }
4090 }
4091
63ec54d7
PM		 4092 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
4093 maxenvlen, "Env-variable");
fc9c5412
JS		 4094
4095 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4096 if (arginfo->has_arg) {
4097 printf("-%s %-*s %-*s %s\n", arginfo->argv,
63ec54d7
PM		 4098 (int)(maxarglen - strlen(arginfo->argv) - 1),
4099 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
fc9c5412 4100 } else {
63ec54d7 4101 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
fc9c5412
JS		 4102 maxenvlen, arginfo->env,
4103 arginfo->help);
4104 }
4105 }
4106
4107 printf("\n"
4108 "Defaults:\n"
4109 "QEMU_LD_PREFIX = %s\n"
989b697d 4110 "QEMU_STACK_SIZE = %ld byte\n",
fc9c5412 4111 interp_prefix,
989b697d 4112 guest_stack_size);
fc9c5412
JS		 4113
4114 printf("\n"
4115 "You can use -E and -U options or the QEMU_SET_ENV and\n"
4116 "QEMU_UNSET_ENV environment variables to set and unset\n"
4117 "environment variables for the target process.\n"
4118 "It is possible to provide several variables by separating them\n"
4119 "by commas in getsubopt(3) style. Additionally it is possible to\n"
4120 "provide the -E and -U options multiple times.\n"
4121 "The following lines are equivalent:\n"
4122 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
4123 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
4124 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
4125 "Note that if you provide several changes to a single variable\n"
4126 "the last change will stay in effect.\n");
4127
d03f9c32 4128 exit(exitcode);
fc9c5412
JS		 4129}
4130
4131static int parse_args(int argc, char **argv)
4132{
4133 const char *r;
4134 int optind;
42644cee 4135 const struct qemu_argument *arginfo;
fc9c5412
JS		 4136
4137 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4138 if (arginfo->env == NULL) {
4139 continue;
4140 }
4141
4142 r = getenv(arginfo->env);
4143 if (r != NULL) {
4144 arginfo->handle_opt(r);
4145 }
4146 }
4147
4148 optind = 1;
4149 for (;;) {
4150 if (optind >= argc) {
4151 break;
4152 }
4153 r = argv[optind];
4154 if (r[0] != '-') {
4155 break;
4156 }
4157 optind++;
4158 r++;
4159 if (!strcmp(r, "-")) {
4160 break;
4161 }
ba02577c
MI		 4162 /* Treat --foo the same as -foo. */
4163 if (r[0] == '-') {
4164 r++;
4165 }
fc9c5412
JS		 4166
4167 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4168 if (!strcmp(r, arginfo->argv)) {
fc9c5412 4169 if (arginfo->has_arg) {
1386d4c0 4170 if (optind >= argc) {
138940bf
MI		 4171 (void) fprintf(stderr,
4172 "qemu: missing argument for option '%s'\n", r);
4d1275c2 4173 exit(EXIT_FAILURE);
1386d4c0
PM		 4174 }
4175 arginfo->handle_opt(argv[optind]);
fc9c5412 4176 optind++;
1386d4c0
PM		 4177 } else {
4178 arginfo->handle_opt(NULL);
fc9c5412 4179 }
fc9c5412
JS		 4180 break;
4181 }
4182 }
4183
4184 /* no option matched the current argv */
4185 if (arginfo->handle_opt == NULL) {
138940bf 4186 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r);
4d1275c2 4187 exit(EXIT_FAILURE);
fc9c5412
JS		 4188 }
4189 }
4190
4191 if (optind >= argc) {
138940bf 4192 (void) fprintf(stderr, "qemu: no user program specified\n");
4d1275c2 4193 exit(EXIT_FAILURE);
fc9c5412
JS		 4194 }
4195
4196 filename = argv[optind];
4197 exec_path = argv[optind];
4198
4199 return optind;
4200}
4201
902b3d5c 4202int main(int argc, char **argv, char **envp)
31e31b8a 4203{
01ffc75b 4204 struct target_pt_regs regs1, *regs = &regs1;
31e31b8a 4205 struct image_info info1, *info = &info1;
edf8e2af 4206 struct linux_binprm bprm;
48e15fc2 4207 TaskState *ts;
9349b4f9 4208 CPUArchState *env;
db6b81d4 4209 CPUState *cpu;
586314f2 4210 int optind;
04a6dfeb 4211 char **target_environ, **wrk;
7d8cec95
AJ		 4212 char **target_argv;
4213 int target_argc;
7d8cec95 4214 int i;
fd4d81dd 4215 int ret;
03cfd8fa 4216 int execfd;
b12b6a18 4217
ce008c1f
AF		 4218 module_call_init(MODULE_INIT_QOM);
4219
04a6dfeb
AJ		 4220 if ((envlist = envlist_create()) == NULL) {
4221 (void) fprintf(stderr, "Unable to allocate envlist\n");
4d1275c2 4222 exit(EXIT_FAILURE);
04a6dfeb
AJ		 4223 }
4224
4225 /* add current environment into the list */
4226 for (wrk = environ; *wrk != NULL; wrk++) {
4227 (void) envlist_setenv(envlist, *wrk);
4228 }
4229
703e0e89
RH		 4230 /* Read the stack limit from the kernel. If it's "unlimited",
4231 then we can do little else besides use the default. */
4232 {
4233 struct rlimit lim;
4234 if (getrlimit(RLIMIT_STACK, &lim) == 0
81bbe906
TY		 4235 && lim.rlim_cur != RLIM_INFINITY
4236 && lim.rlim_cur == (target_long)lim.rlim_cur) {
703e0e89
RH		 4237 guest_stack_size = lim.rlim_cur;
4238 }
4239 }
4240
b1f9be31 4241 cpu_model = NULL;
b5ec5ce0 4242
c5e4a5a9
MR		 4243 srand(time(NULL));
4244
fc9c5412 4245 optind = parse_args(argc, argv);
586314f2 4246
31e31b8a 4247 /* Zero out regs */
01ffc75b 4248 memset(regs, 0, sizeof(struct target_pt_regs));
31e31b8a
FB		 4249
4250 /* Zero out image_info */
4251 memset(info, 0, sizeof(struct image_info));
4252
edf8e2af
MW		 4253 memset(&bprm, 0, sizeof (bprm));
4254
74cd30b8
FB		 4255 /* Scan interp_prefix dir for replacement files. */
4256 init_paths(interp_prefix);
4257
4a24a758
PM		 4258 init_qemu_uname_release();
4259
46027c07 4260 if (cpu_model == NULL) {
aaed909a 4261#if defined(TARGET_I386)
46027c07
FB		 4262#ifdef TARGET_X86_64
4263 cpu_model = "qemu64";
4264#else
4265 cpu_model = "qemu32";
4266#endif
aaed909a 4267#elif defined(TARGET_ARM)
088ab16c 4268 cpu_model = "any";
d2fbca94
GX		 4269#elif defined(TARGET_UNICORE32)
4270 cpu_model = "any";
aaed909a
FB		 4271#elif defined(TARGET_M68K)
4272 cpu_model = "any";
4273#elif defined(TARGET_SPARC)
4274#ifdef TARGET_SPARC64
4275 cpu_model = "TI UltraSparc II";
4276#else
4277 cpu_model = "Fujitsu MB86904";
46027c07 4278#endif
aaed909a
FB		 4279#elif defined(TARGET_MIPS)
4280#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
74797f40 4281 cpu_model = "5KEf";
aaed909a
FB		 4282#else
4283 cpu_model = "24Kf";
4284#endif
d962783e
JL		 4285#elif defined TARGET_OPENRISC
4286 cpu_model = "or1200";
aaed909a 4287#elif defined(TARGET_PPC)
a74029f6 4288# ifdef TARGET_PPC64
de3f1b98 4289 cpu_model = "POWER8";
a74029f6 4290# else
aaed909a 4291 cpu_model = "750";
a74029f6 4292# endif
91c45a38
RH		 4293#elif defined TARGET_SH4
4294 cpu_model = TYPE_SH7785_CPU;
aaed909a
FB		 4295#else
4296 cpu_model = "any";
4297#endif
4298 }
d5ab9713 4299 tcg_exec_init(0);
83fb7adf
FB		 4300 /* NOTE: we need to init the CPU at this stage to get
4301 qemu_host_page_size */
2994fd96
EH		 4302 cpu = cpu_init(cpu_model);
4303 if (!cpu) {
aaed909a 4304 fprintf(stderr, "Unable to find CPU definition\n");
4d1275c2 4305 exit(EXIT_FAILURE);
aaed909a 4306 }
2994fd96 4307 env = cpu->env_ptr;
0ac46af3 4308 cpu_reset(cpu);
b55a37c9 4309
db6b81d4 4310 thread_cpu = cpu;
3b46e624 4311
b6741956
FB		 4312 if (getenv("QEMU_STRACE")) {
4313 do_strace = 1;
b92c47c1
TS		 4314 }
4315
c5e4a5a9
MR		 4316 if (getenv("QEMU_RAND_SEED")) {
4317 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4318 }
4319
04a6dfeb
AJ		 4320 target_environ = envlist_to_environ(envlist, NULL);
4321 envlist_free(envlist);
b12b6a18 4322
379f6698
PB		 4323 /*
4324 * Now that page sizes are configured in cpu_init() we can do
4325 * proper page alignment for guest_base.
4326 */
4327 guest_base = HOST_PAGE_ALIGN(guest_base);
68a1c816 4328
806d1021
MI		 4329 if (reserved_va || have_guest_base) {
4330 guest_base = init_guest_space(guest_base, reserved_va, 0,
4331 have_guest_base);
4332 if (guest_base == (unsigned long)-1) {
097b8cb8
PM		 4333 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
4334 "space for use as guest address space (check your virtual "
4335 "memory ulimit setting or reserve less using -R option)\n",
4336 reserved_va);
4d1275c2 4337 exit(EXIT_FAILURE);
68a1c816 4338 }
97cc7560 4339
806d1021
MI		 4340 if (reserved_va) {
4341 mmap_next_start = reserved_va;
97cc7560
DDAG		 4342 }
4343 }
379f6698
PB		 4344
4345 /*
4346 * Read in mmap_min_addr kernel parameter. This value is used
4347 * When loading the ELF image to determine whether guest_base
14f24e14 4348 * is needed. It is also used in mmap_find_vma.
379f6698 4349 */
14f24e14 4350 {
379f6698
PB		 4351 FILE *fp;
4352
4353 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
4354 unsigned long tmp;
4355 if (fscanf(fp, "%lu", &tmp) == 1) {
4356 mmap_min_addr = tmp;
13829020 4357 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr);
379f6698
PB		 4358 }
4359 fclose(fp);
4360 }
4361 }
379f6698 4362
7d8cec95
AJ		 4363 /*
4364 * Prepare copy of argv vector for target.
4365 */
4366 target_argc = argc - optind;
4367 target_argv = calloc(target_argc + 1, sizeof (char *));
4368 if (target_argv == NULL) {
4369 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4d1275c2 4370 exit(EXIT_FAILURE);
7d8cec95
AJ		 4371 }
4372
4373 /*
4374 * If argv0 is specified (using '-0' switch) we replace
4375 * argv[0] pointer with the given one.
4376 */
4377 i = 0;
4378 if (argv0 != NULL) {
4379 target_argv[i++] = strdup(argv0);
4380 }
4381 for (; i < target_argc; i++) {
4382 target_argv[i] = strdup(argv[optind + i]);
4383 }
4384 target_argv[target_argc] = NULL;
4385
c78d65e8 4386 ts = g_new0(TaskState, 1);
edf8e2af
MW		 4387 init_task_state(ts);
4388 /* build Task State */
4389 ts->info = info;
4390 ts->bprm = &bprm;
0429a971 4391 cpu->opaque = ts;
edf8e2af
MW		 4392 task_settid(ts);
4393
0b959cf5
RH		 4394 execfd = qemu_getauxval(AT_EXECFD);
4395 if (execfd == 0) {
03cfd8fa 4396 execfd = open(filename, O_RDONLY);
0b959cf5
RH		 4397 if (execfd < 0) {
4398 printf("Error while loading %s: %s\n", filename, strerror(errno));
4d1275c2 4399 _exit(EXIT_FAILURE);
0b959cf5 4400 }
03cfd8fa
LV		 4401 }
4402
4403 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
fd4d81dd
AP		 4404 info, &bprm);
4405 if (ret != 0) {
885c1d10 4406 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4d1275c2 4407 _exit(EXIT_FAILURE);
b12b6a18
TS		 4408 }
4409
4410 for (wrk = target_environ; *wrk; wrk++) {
4411 free(*wrk);
31e31b8a 4412 }
3b46e624 4413
b12b6a18
TS		 4414 free(target_environ);
4415
13829020 4416 if (qemu_loglevel_mask(CPU_LOG_PAGE)) {
379f6698 4417 qemu_log("guest_base 0x%lx\n", guest_base);
2e77eac6
BS		 4418 log_page_dump();
4419
4420 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4421 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4422 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4423 info->start_code);
4424 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4425 info->start_data);
4426 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4427 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4428 info->start_stack);
4429 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4430 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4431 }
31e31b8a 4432
53a5960a 4433 target_set_brk(info->brk);
31e31b8a 4434 syscall_init();
66fb9763 4435 signal_init();
31e31b8a 4436
9002ec79
RH		 4437 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4438 generating the prologue until now so that the prologue can take
4439 the real value of GUEST_BASE into account. */
4440 tcg_prologue_init(&tcg_ctx);
9002ec79 4441
b346ff46 4442#if defined(TARGET_I386)
3802ce26 4443 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
b98dbc90 4444 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
0514ef2f 4445 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
1bde465e
FB		 4446 env->cr[4] |= CR4_OSFXSR_MASK;
4447 env->hflags |= HF_OSFXSR_MASK;
4448 }
d2fd1af7 4449#ifndef TARGET_ABI32
4dbc422b 4450 /* enable 64 bit mode if possible */
0514ef2f 4451 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4dbc422b 4452 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4d1275c2 4453 exit(EXIT_FAILURE);
4dbc422b 4454 }
d2fd1af7 4455 env->cr[4] |= CR4_PAE_MASK;
4dbc422b 4456 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
d2fd1af7
FB		 4457 env->hflags |= HF_LMA_MASK;
4458#endif
1bde465e 4459
415e561f
FB		 4460 /* flags setup : we activate the IRQs by default as in user mode */
4461 env->eflags |= IF_MASK;
3b46e624 4462
6dbad63e 4463 /* linux register setup */
d2fd1af7 4464#ifndef TARGET_ABI32
84409ddb
JM		 4465 env->regs[R_EAX] = regs->rax;
4466 env->regs[R_EBX] = regs->rbx;
4467 env->regs[R_ECX] = regs->rcx;
4468 env->regs[R_EDX] = regs->rdx;
4469 env->regs[R_ESI] = regs->rsi;
4470 env->regs[R_EDI] = regs->rdi;
4471 env->regs[R_EBP] = regs->rbp;
4472 env->regs[R_ESP] = regs->rsp;
4473 env->eip = regs->rip;
4474#else
0ecfa993
FB		 4475 env->regs[R_EAX] = regs->eax;
4476 env->regs[R_EBX] = regs->ebx;
4477 env->regs[R_ECX] = regs->ecx;
4478 env->regs[R_EDX] = regs->edx;
4479 env->regs[R_ESI] = regs->esi;
4480 env->regs[R_EDI] = regs->edi;
4481 env->regs[R_EBP] = regs->ebp;
4482 env->regs[R_ESP] = regs->esp;
dab2ed99 4483 env->eip = regs->eip;
84409ddb 4484#endif
31e31b8a 4485
f4beb510 4486 /* linux interrupt setup */
e441570f
AZ		 4487#ifndef TARGET_ABI32
4488 env->idt.limit = 511;
4489#else
4490 env->idt.limit = 255;
4491#endif
4492 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4493 PROT_READ|PROT_WRITE,
4494 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4495 idt_table = g2h(env->idt.base);
f4beb510
FB		 4496 set_idt(0, 0);
4497 set_idt(1, 0);
4498 set_idt(2, 0);
4499 set_idt(3, 3);
4500 set_idt(4, 3);
ec95da6c 4501 set_idt(5, 0);
f4beb510
FB		 4502 set_idt(6, 0);
4503 set_idt(7, 0);
4504 set_idt(8, 0);
4505 set_idt(9, 0);
4506 set_idt(10, 0);
4507 set_idt(11, 0);
4508 set_idt(12, 0);
4509 set_idt(13, 0);
4510 set_idt(14, 0);
4511 set_idt(15, 0);
4512 set_idt(16, 0);
4513 set_idt(17, 0);
4514 set_idt(18, 0);
4515 set_idt(19, 0);
4516 set_idt(0x80, 3);
4517
6dbad63e 4518 /* linux segment setup */
8d18e893
FB		 4519 {
4520 uint64_t *gdt_table;
e441570f
AZ		 4521 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4522 PROT_READ|PROT_WRITE,
4523 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
8d18e893 4524 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
e441570f 4525 gdt_table = g2h(env->gdt.base);
d2fd1af7 4526#ifdef TARGET_ABI32
8d18e893
FB		 4527 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4528 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4529 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
d2fd1af7
FB		 4530#else
4531 /* 64 bit code segment */
4532 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4533 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4534 DESC_L_MASK |
4535 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4536#endif
8d18e893
FB		 4537 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4538 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4539 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4540 }
6dbad63e 4541 cpu_x86_load_seg(env, R_CS, __USER_CS);
d2fd1af7
FB		 4542 cpu_x86_load_seg(env, R_SS, __USER_DS);
4543#ifdef TARGET_ABI32
6dbad63e
FB		 4544 cpu_x86_load_seg(env, R_DS, __USER_DS);
4545 cpu_x86_load_seg(env, R_ES, __USER_DS);
6dbad63e
FB		 4546 cpu_x86_load_seg(env, R_FS, __USER_DS);
4547 cpu_x86_load_seg(env, R_GS, __USER_DS);
d6eb40f6
TS		 4548 /* This hack makes Wine work... */
4549 env->segs[R_FS].selector = 0;
d2fd1af7
FB		 4550#else
4551 cpu_x86_load_seg(env, R_DS, 0);
4552 cpu_x86_load_seg(env, R_ES, 0);
4553 cpu_x86_load_seg(env, R_FS, 0);
4554 cpu_x86_load_seg(env, R_GS, 0);
4555#endif
99033cae
AG		 4556#elif defined(TARGET_AARCH64)
4557 {
4558 int i;
4559
4560 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4561 fprintf(stderr,
4562 "The selected ARM CPU does not support 64 bit mode\n");
4d1275c2 4563 exit(EXIT_FAILURE);
99033cae
AG		 4564 }
4565
4566 for (i = 0; i < 31; i++) {
4567 env->xregs[i] = regs->regs[i];
4568 }
4569 env->pc = regs->pc;
4570 env->xregs[31] = regs->sp;
4571 }
b346ff46
FB		 4572#elif defined(TARGET_ARM)
4573 {
4574 int i;
ae087923
PM		 4575 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
4576 CPSRWriteByInstr);
b346ff46
FB		 4577 for(i = 0; i < 16; i++) {
4578 env->regs[i] = regs->uregs[i];
4579 }
f9fd40eb 4580#ifdef TARGET_WORDS_BIGENDIAN
d8fd2954
PB		 4581 /* Enable BE8. */
4582 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4583 && (info->elf_flags & EF_ARM_BE8)) {
9c5a7460
PC		 4584 env->uncached_cpsr |= CPSR_E;
4585 env->cp15.sctlr_el[1] |= SCTLR_E0E;
f9fd40eb
PB		 4586 } else {
4587 env->cp15.sctlr_el[1] |= SCTLR_B;
d8fd2954 4588 }
f9fd40eb 4589#endif
b346ff46 4590 }
d2fbca94
GX		 4591#elif defined(TARGET_UNICORE32)
4592 {
4593 int i;
4594 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4595 for (i = 0; i < 32; i++) {
4596 env->regs[i] = regs->uregs[i];
4597 }
4598 }
93ac68bc 4599#elif defined(TARGET_SPARC)
060366c5
FB		 4600 {
4601 int i;
4602 env->pc = regs->pc;
4603 env->npc = regs->npc;
4604 env->y = regs->y;
4605 for(i = 0; i < 8; i++)
4606 env->gregs[i] = regs->u_regs[i];
4607 for(i = 0; i < 8; i++)
4608 env->regwptr[i] = regs->u_regs[i + 8];
4609 }
67867308
FB		 4610#elif defined(TARGET_PPC)
4611 {
4612 int i;
3fc6c082 4613
0411a972
JM		 4614#if defined(TARGET_PPC64)
4615#if defined(TARGET_ABI32)
4616 env->msr &= ~((target_ulong)1 << MSR_SF);
e85e7c6e 4617#else
0411a972
JM		 4618 env->msr |= (target_ulong)1 << MSR_SF;
4619#endif
84409ddb 4620#endif
67867308
FB		 4621 env->nip = regs->nip;
4622 for(i = 0; i < 32; i++) {
4623 env->gpr[i] = regs->gpr[i];
4624 }
4625 }
e6e5906b
PB		 4626#elif defined(TARGET_M68K)
4627 {
e6e5906b
PB		 4628 env->pc = regs->pc;
4629 env->dregs[0] = regs->d0;
4630 env->dregs[1] = regs->d1;
4631 env->dregs[2] = regs->d2;
4632 env->dregs[3] = regs->d3;
4633 env->dregs[4] = regs->d4;
4634 env->dregs[5] = regs->d5;
4635 env->dregs[6] = regs->d6;
4636 env->dregs[7] = regs->d7;
4637 env->aregs[0] = regs->a0;
4638 env->aregs[1] = regs->a1;
4639 env->aregs[2] = regs->a2;
4640 env->aregs[3] = regs->a3;
4641 env->aregs[4] = regs->a4;
4642 env->aregs[5] = regs->a5;
4643 env->aregs[6] = regs->a6;
4644 env->aregs[7] = regs->usp;
4645 env->sr = regs->sr;
4646 ts->sim_syscalls = 1;
4647 }
b779e29e
EI		 4648#elif defined(TARGET_MICROBLAZE)
4649 {
4650 env->regs[0] = regs->r0;
4651 env->regs[1] = regs->r1;
4652 env->regs[2] = regs->r2;
4653 env->regs[3] = regs->r3;
4654 env->regs[4] = regs->r4;
4655 env->regs[5] = regs->r5;
4656 env->regs[6] = regs->r6;
4657 env->regs[7] = regs->r7;
4658 env->regs[8] = regs->r8;
4659 env->regs[9] = regs->r9;
4660 env->regs[10] = regs->r10;
4661 env->regs[11] = regs->r11;
4662 env->regs[12] = regs->r12;
4663 env->regs[13] = regs->r13;
4664 env->regs[14] = regs->r14;
4665 env->regs[15] = regs->r15;
4666 env->regs[16] = regs->r16;
4667 env->regs[17] = regs->r17;
4668 env->regs[18] = regs->r18;
4669 env->regs[19] = regs->r19;
4670 env->regs[20] = regs->r20;
4671 env->regs[21] = regs->r21;
4672 env->regs[22] = regs->r22;
4673 env->regs[23] = regs->r23;
4674 env->regs[24] = regs->r24;
4675 env->regs[25] = regs->r25;
4676 env->regs[26] = regs->r26;
4677 env->regs[27] = regs->r27;
4678 env->regs[28] = regs->r28;
4679 env->regs[29] = regs->r29;
4680 env->regs[30] = regs->r30;
4681 env->regs[31] = regs->r31;
4682 env->sregs[SR_PC] = regs->pc;
4683 }
048f6b4d
FB		 4684#elif defined(TARGET_MIPS)
4685 {
4686 int i;
4687
4688 for(i = 0; i < 32; i++) {
b5dc7732 4689 env->active_tc.gpr[i] = regs->regs[i];
048f6b4d 4690 }
0fddbbf2
NF		 4691 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4692 if (regs->cp0_epc & 1) {
4693 env->hflags |= MIPS_HFLAG_M16;
4694 }
048f6b4d 4695 }
d962783e
JL		 4696#elif defined(TARGET_OPENRISC)
4697 {
4698 int i;
4699
4700 for (i = 0; i < 32; i++) {
4701 env->gpr[i] = regs->gpr[i];
4702 }
4703
4704 env->sr = regs->sr;
4705 env->pc = regs->pc;
4706 }
fdf9b3e8
FB		 4707#elif defined(TARGET_SH4)
4708 {
4709 int i;
4710
4711 for(i = 0; i < 16; i++) {
4712 env->gregs[i] = regs->regs[i];
4713 }
4714 env->pc = regs->pc;
4715 }
7a3148a9
JM		 4716#elif defined(TARGET_ALPHA)
4717 {
4718 int i;
4719
4720 for(i = 0; i < 28; i++) {
992f48a0 4721 env->ir[i] = ((abi_ulong *)regs)[i];
7a3148a9 4722 }
dad081ee 4723 env->ir[IR_SP] = regs->usp;
7a3148a9 4724 env->pc = regs->pc;
7a3148a9 4725 }
48733d19
TS		 4726#elif defined(TARGET_CRIS)
4727 {
4728 env->regs[0] = regs->r0;
4729 env->regs[1] = regs->r1;
4730 env->regs[2] = regs->r2;
4731 env->regs[3] = regs->r3;
4732 env->regs[4] = regs->r4;
4733 env->regs[5] = regs->r5;
4734 env->regs[6] = regs->r6;
4735 env->regs[7] = regs->r7;
4736 env->regs[8] = regs->r8;
4737 env->regs[9] = regs->r9;
4738 env->regs[10] = regs->r10;
4739 env->regs[11] = regs->r11;
4740 env->regs[12] = regs->r12;
4741 env->regs[13] = regs->r13;
4742 env->regs[14] = info->start_stack;
4743 env->regs[15] = regs->acr;
4744 env->pc = regs->erp;
4745 }
a4c075f1
UH		 4746#elif defined(TARGET_S390X)
4747 {
4748 int i;
4749 for (i = 0; i < 16; i++) {
4750 env->regs[i] = regs->gprs[i];
4751 }
4752 env->psw.mask = regs->psw.mask;
4753 env->psw.addr = regs->psw.addr;
4754 }
b16189b2
CG		 4755#elif defined(TARGET_TILEGX)
4756 {
4757 int i;
4758 for (i = 0; i < TILEGX_R_COUNT; i++) {
4759 env->regs[i] = regs->regs[i];
4760 }
4761 for (i = 0; i < TILEGX_SPR_COUNT; i++) {
4762 env->spregs[i] = 0;
4763 }
4764 env->pc = regs->pc;
4765 }
b346ff46
FB		 4766#else
4767#error unsupported target CPU
4768#endif
31e31b8a 4769
d2fbca94 4770#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
a87295e8
PB		 4771 ts->stack_base = info->start_stack;
4772 ts->heap_base = info->brk;
4773 /* This will be filled in on the first SYS_HEAPINFO call. */
4774 ts->heap_limit = 0;
4775#endif
4776
74c33bed 4777 if (gdbstub_port) {
ff7a981a
PM		 4778 if (gdbserver_start(gdbstub_port) < 0) {
4779 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4780 gdbstub_port);
4d1275c2 4781 exit(EXIT_FAILURE);
ff7a981a 4782 }
db6b81d4 4783 gdb_handlesig(cpu, 0);
1fddef4b 4784 }
1b6b029e
FB		 4785 cpu_loop(env);
4786 /* never exits */
31e31b8a
FB		 4787 return 0;
4788}
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