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linux-user: Support for restarting system calls for PPC targets
[mirror_qemu.git] / linux-user / main.c
CommitLineData
31e31b8a 1/*
93ac68bc 2 * qemu user main
5fafdf24 3 *
68d0f70e 4 * Copyright (c) 2003-2008 Fabrice Bellard
31e31b8a
FB		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
8167ee88 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31e31b8a 18 */
d39594e9 19#include "qemu/osdep.h"
e441570f 20#include <sys/mman.h>
edf8e2af 21#include <sys/syscall.h>
703e0e89 22#include <sys/resource.h>
31e31b8a 23
3ef693a0 24#include "qemu.h"
f348b6d1
VB		 25#include "qemu/path.h"
26#include "qemu/cutils.h"
27#include "qemu/help_option.h"
2b41f10e 28#include "cpu.h"
63c91552 29#include "exec/exec-all.h"
9002ec79 30#include "tcg.h"
1de7afc9
PB		 31#include "qemu/timer.h"
32#include "qemu/envlist.h"
d8fd2954 33#include "elf.h"
508127e2 34#include "exec/log.h"
04a6dfeb 35
d088d664
AJ		 36char *exec_path;
37
1b530a6d 38int singlestep;
8cb76755
SW		 39static const char *filename;
40static const char *argv0;
41static int gdbstub_port;
42static envlist_t *envlist;
51fb256a 43static const char *cpu_model;
379f6698
PB		 44unsigned long mmap_min_addr;
45unsigned long guest_base;
46int have_guest_base;
120a9848
PB		 47
48#define EXCP_DUMP(env, fmt, ...) \
49do { \
50 CPUState *cs = ENV_GET_CPU(env); \
51 fprintf(stderr, fmt , ## __VA_ARGS__); \
52 cpu_dump_state(cs, stderr, fprintf, 0); \
53 if (qemu_log_separate()) { \
54 qemu_log(fmt, ## __VA_ARGS__); \
55 log_cpu_state(cs, 0); \
56 } \
57} while (0)
58
288e65b9
AG		 59#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
60/*
61 * When running 32-on-64 we should make sure we can fit all of the possible
62 * guest address space into a contiguous chunk of virtual host memory.
63 *
64 * This way we will never overlap with our own libraries or binaries or stack
65 * or anything else that QEMU maps.
66 */
314992b1
AG		 67# ifdef TARGET_MIPS
68/* MIPS only supports 31 bits of virtual address space for user space */
69unsigned long reserved_va = 0x77000000;
70# else
288e65b9 71unsigned long reserved_va = 0xf7000000;
314992b1 72# endif
288e65b9 73#else
68a1c816 74unsigned long reserved_va;
379f6698 75#endif
1b530a6d 76
d03f9c32 77static void usage(int exitcode);
fc9c5412 78
7ee2822c 79static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
e586822a 80const char *qemu_uname_release;
586314f2 81
9de5e440
FB		 82/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
83 we allocate a bigger stack. Need a better solution, for example
84 by remapping the process stack directly at the right place */
703e0e89 85unsigned long guest_stack_size = 8 * 1024 * 1024UL;
31e31b8a
FB		 86
87void gemu_log(const char *fmt, ...)
88{
89 va_list ap;
90
91 va_start(ap, fmt);
92 vfprintf(stderr, fmt, ap);
93 va_end(ap);
94}
95
8fcd3692 96#if defined(TARGET_I386)
05390248 97int cpu_get_pic_interrupt(CPUX86State *env)
92ccca6a
FB		 98{
99 return -1;
100}
8fcd3692 101#endif
92ccca6a 102
d5975363
PB		 103/***********************************************************/
104/* Helper routines for implementing atomic operations. */
105
106/* To implement exclusive operations we force all cpus to syncronise.
107 We don't require a full sync, only that no cpus are executing guest code.
108 The alternative is to map target atomic ops onto host equivalents,
109 which requires quite a lot of per host/target work. */
c2764719 110static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
d5975363
PB		 111static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
112static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
113static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
114static int pending_cpus;
115
116/* Make sure everything is in a consistent state for calling fork(). */
117void fork_start(void)
118{
677ef623 119 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 120 pthread_mutex_lock(&exclusive_lock);
d032d1b4 121 mmap_fork_start();
d5975363
PB		 122}
123
124void fork_end(int child)
125{
d032d1b4 126 mmap_fork_end(child);
d5975363 127 if (child) {
bdc44640 128 CPUState *cpu, *next_cpu;
d5975363
PB		 129 /* Child processes created by fork() only have a single thread.
130 Discard information about the parent threads. */
bdc44640
AF		 131 CPU_FOREACH_SAFE(cpu, next_cpu) {
132 if (cpu != thread_cpu) {
133 QTAILQ_REMOVE(&cpus, thread_cpu, node);
134 }
135 }
d5975363
PB		 136 pending_cpus = 0;
137 pthread_mutex_init(&exclusive_lock, NULL);
c2764719 138 pthread_mutex_init(&cpu_list_mutex, NULL);
d5975363
PB		 139 pthread_cond_init(&exclusive_cond, NULL);
140 pthread_cond_init(&exclusive_resume, NULL);
677ef623 141 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
f7ec7f7b 142 gdbserver_fork(thread_cpu);
d5975363
PB		 143 } else {
144 pthread_mutex_unlock(&exclusive_lock);
677ef623 145 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 146 }
d5975363
PB		 147}
148
149/* Wait for pending exclusive operations to complete. The exclusive lock
150 must be held. */
151static inline void exclusive_idle(void)
152{
153 while (pending_cpus) {
154 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
155 }
156}
157
158/* Start an exclusive operation.
159 Must only be called from outside cpu_arm_exec. */
160static inline void start_exclusive(void)
161{
0315c31c
AF		 162 CPUState *other_cpu;
163
d5975363
PB		 164 pthread_mutex_lock(&exclusive_lock);
165 exclusive_idle();
166
167 pending_cpus = 1;
168 /* Make all other cpus stop executing. */
bdc44640 169 CPU_FOREACH(other_cpu) {
0315c31c 170 if (other_cpu->running) {
d5975363 171 pending_cpus++;
60a3e17a 172 cpu_exit(other_cpu);
d5975363
PB		 173 }
174 }
175 if (pending_cpus > 1) {
176 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
177 }
178}
179
180/* Finish an exclusive operation. */
f7e61b22 181static inline void __attribute__((unused)) end_exclusive(void)
d5975363
PB		 182{
183 pending_cpus = 0;
184 pthread_cond_broadcast(&exclusive_resume);
185 pthread_mutex_unlock(&exclusive_lock);
186}
187
188/* Wait for exclusive ops to finish, and begin cpu execution. */
0315c31c 189static inline void cpu_exec_start(CPUState *cpu)
d5975363
PB		 190{
191 pthread_mutex_lock(&exclusive_lock);
192 exclusive_idle();
0315c31c 193 cpu->running = true;
d5975363
PB		 194 pthread_mutex_unlock(&exclusive_lock);
195}
196
197/* Mark cpu as not executing, and release pending exclusive ops. */
0315c31c 198static inline void cpu_exec_end(CPUState *cpu)
d5975363
PB		 199{
200 pthread_mutex_lock(&exclusive_lock);
0315c31c 201 cpu->running = false;
d5975363
PB		 202 if (pending_cpus > 1) {
203 pending_cpus--;
204 if (pending_cpus == 1) {
205 pthread_cond_signal(&exclusive_cond);
206 }
207 }
208 exclusive_idle();
209 pthread_mutex_unlock(&exclusive_lock);
210}
c2764719
PB		 211
212void cpu_list_lock(void)
213{
214 pthread_mutex_lock(&cpu_list_mutex);
215}
216
217void cpu_list_unlock(void)
218{
219 pthread_mutex_unlock(&cpu_list_mutex);
220}
d5975363
PB		 221
222
a541f297
FB		 223#ifdef TARGET_I386
224/***********************************************************/
225/* CPUX86 core interface */
226
28ab0e2e
FB		 227uint64_t cpu_get_tsc(CPUX86State *env)
228{
4a7428c5 229 return cpu_get_host_ticks();
28ab0e2e
FB		 230}
231
5fafdf24 232static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
f4beb510 233 int flags)
6dbad63e 234{
f4beb510 235 unsigned int e1, e2;
53a5960a 236 uint32_t *p;
6dbad63e
FB		 237 e1 = (addr << 16) | (limit & 0xffff);
238 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
f4beb510 239 e2 |= flags;
53a5960a 240 p = ptr;
d538e8f5 241 p[0] = tswap32(e1);
242 p[1] = tswap32(e2);
f4beb510
FB		 243}
244
e441570f 245static uint64_t *idt_table;
eb38c52c 246#ifdef TARGET_X86_64
d2fd1af7
FB		 247static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
248 uint64_t addr, unsigned int sel)
f4beb510 249{
4dbc422b 250 uint32_t *p, e1, e2;
f4beb510
FB		 251 e1 = (addr & 0xffff) | (sel << 16);
252 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
53a5960a 253 p = ptr;
4dbc422b
FB		 254 p[0] = tswap32(e1);
255 p[1] = tswap32(e2);
256 p[2] = tswap32(addr >> 32);
257 p[3] = 0;
6dbad63e 258}
d2fd1af7
FB		 259/* only dpl matters as we do only user space emulation */
260static void set_idt(int n, unsigned int dpl)
261{
262 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
263}
264#else
d2fd1af7
FB		 265static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
266 uint32_t addr, unsigned int sel)
267{
4dbc422b 268 uint32_t *p, e1, e2;
d2fd1af7
FB		 269 e1 = (addr & 0xffff) | (sel << 16);
270 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
271 p = ptr;
4dbc422b
FB		 272 p[0] = tswap32(e1);
273 p[1] = tswap32(e2);
d2fd1af7
FB		 274}
275
f4beb510
FB		 276/* only dpl matters as we do only user space emulation */
277static void set_idt(int n, unsigned int dpl)
278{
279 set_gate(idt_table + n, 0, dpl, 0, 0);
280}
d2fd1af7 281#endif
31e31b8a 282
89e957e7 283void cpu_loop(CPUX86State *env)
1b6b029e 284{
db6b81d4 285 CPUState *cs = CPU(x86_env_get_cpu(env));
bc8a22cc 286 int trapnr;
992f48a0 287 abi_ulong pc;
0284b03b 288 abi_ulong ret;
c227f099 289 target_siginfo_t info;
851e67a1 290
1b6b029e 291 for(;;) {
b040bc9c 292 cpu_exec_start(cs);
ea3e9847 293 trapnr = cpu_x86_exec(cs);
b040bc9c 294 cpu_exec_end(cs);
bc8a22cc 295 switch(trapnr) {
f4beb510 296 case 0x80:
d2fd1af7 297 /* linux syscall from int $0x80 */
0284b03b
TB		 298 ret = do_syscall(env,
299 env->regs[R_EAX],
300 env->regs[R_EBX],
301 env->regs[R_ECX],
302 env->regs[R_EDX],
303 env->regs[R_ESI],
304 env->regs[R_EDI],
305 env->regs[R_EBP],
306 0, 0);
307 if (ret == -TARGET_ERESTARTSYS) {
308 env->eip -= 2;
309 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
310 env->regs[R_EAX] = ret;
311 }
f4beb510 312 break;
d2fd1af7
FB		 313#ifndef TARGET_ABI32
314 case EXCP_SYSCALL:
5ba18547 315 /* linux syscall from syscall instruction */
0284b03b
TB		 316 ret = do_syscall(env,
317 env->regs[R_EAX],
318 env->regs[R_EDI],
319 env->regs[R_ESI],
320 env->regs[R_EDX],
321 env->regs[10],
322 env->regs[8],
323 env->regs[9],
324 0, 0);
325 if (ret == -TARGET_ERESTARTSYS) {
326 env->eip -= 2;
327 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
328 env->regs[R_EAX] = ret;
329 }
d2fd1af7
FB		 330 break;
331#endif
f4beb510
FB		 332 case EXCP0B_NOSEG:
333 case EXCP0C_STACK:
a86b3c64 334 info.si_signo = TARGET_SIGBUS;
f4beb510
FB		 335 info.si_errno = 0;
336 info.si_code = TARGET_SI_KERNEL;
337 info._sifields._sigfault._addr = 0;
624f7979 338 queue_signal(env, info.si_signo, &info);
f4beb510 339 break;
1b6b029e 340 case EXCP0D_GPF:
d2fd1af7 341 /* XXX: potential problem if ABI32 */
84409ddb 342#ifndef TARGET_X86_64
851e67a1 343 if (env->eflags & VM_MASK) {
89e957e7 344 handle_vm86_fault(env);
84409ddb
JM		 345 } else
346#endif
347 {
a86b3c64 348 info.si_signo = TARGET_SIGSEGV;
f4beb510
FB		 349 info.si_errno = 0;
350 info.si_code = TARGET_SI_KERNEL;
351 info._sifields._sigfault._addr = 0;
624f7979 352 queue_signal(env, info.si_signo, &info);
1b6b029e
FB		 353 }
354 break;
b689bc57 355 case EXCP0E_PAGE:
a86b3c64 356 info.si_signo = TARGET_SIGSEGV;
b689bc57
FB		 357 info.si_errno = 0;
358 if (!(env->error_code & 1))
359 info.si_code = TARGET_SEGV_MAPERR;
360 else
361 info.si_code = TARGET_SEGV_ACCERR;
970a87a6 362 info._sifields._sigfault._addr = env->cr[2];
624f7979 363 queue_signal(env, info.si_signo, &info);
b689bc57 364 break;
9de5e440 365 case EXCP00_DIVZ:
84409ddb 366#ifndef TARGET_X86_64
bc8a22cc 367 if (env->eflags & VM_MASK) {
447db213 368 handle_vm86_trap(env, trapnr);
84409ddb
JM		 369 } else
370#endif
371 {
bc8a22cc 372 /* division by zero */
a86b3c64 373 info.si_signo = TARGET_SIGFPE;
bc8a22cc
FB		 374 info.si_errno = 0;
375 info.si_code = TARGET_FPE_INTDIV;
376 info._sifields._sigfault._addr = env->eip;
624f7979 377 queue_signal(env, info.si_signo, &info);
bc8a22cc 378 }
9de5e440 379 break;
01df040b 380 case EXCP01_DB:
447db213 381 case EXCP03_INT3:
84409ddb 382#ifndef TARGET_X86_64
447db213
FB		 383 if (env->eflags & VM_MASK) {
384 handle_vm86_trap(env, trapnr);
84409ddb
JM		 385 } else
386#endif
387 {
a86b3c64 388 info.si_signo = TARGET_SIGTRAP;
447db213 389 info.si_errno = 0;
01df040b 390 if (trapnr == EXCP01_DB) {
447db213
FB		 391 info.si_code = TARGET_TRAP_BRKPT;
392 info._sifields._sigfault._addr = env->eip;
393 } else {
394 info.si_code = TARGET_SI_KERNEL;
395 info._sifields._sigfault._addr = 0;
396 }
624f7979 397 queue_signal(env, info.si_signo, &info);
447db213
FB		 398 }
399 break;
9de5e440
FB		 400 case EXCP04_INTO:
401 case EXCP05_BOUND:
84409ddb 402#ifndef TARGET_X86_64
bc8a22cc 403 if (env->eflags & VM_MASK) {
447db213 404 handle_vm86_trap(env, trapnr);
84409ddb
JM		 405 } else
406#endif
407 {
a86b3c64 408 info.si_signo = TARGET_SIGSEGV;
bc8a22cc 409 info.si_errno = 0;
b689bc57 410 info.si_code = TARGET_SI_KERNEL;
bc8a22cc 411 info._sifields._sigfault._addr = 0;
624f7979 412 queue_signal(env, info.si_signo, &info);
bc8a22cc 413 }
9de5e440
FB		 414 break;
415 case EXCP06_ILLOP:
a86b3c64 416 info.si_signo = TARGET_SIGILL;
9de5e440
FB		 417 info.si_errno = 0;
418 info.si_code = TARGET_ILL_ILLOPN;
419 info._sifields._sigfault._addr = env->eip;
624f7979 420 queue_signal(env, info.si_signo, &info);
9de5e440
FB		 421 break;
422 case EXCP_INTERRUPT:
423 /* just indicate that signals should be handled asap */
424 break;
1fddef4b
FB		 425 case EXCP_DEBUG:
426 {
427 int sig;
428
db6b81d4 429 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 430 if (sig)
431 {
432 info.si_signo = sig;
433 info.si_errno = 0;
434 info.si_code = TARGET_TRAP_BRKPT;
624f7979 435 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 436 }
437 }
438 break;
1b6b029e 439 default:
970a87a6 440 pc = env->segs[R_CS].base + env->eip;
120a9848
PB		 441 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
442 (long)pc, trapnr);
1b6b029e
FB		 443 abort();
444 }
66fb9763 445 process_pending_signals(env);
1b6b029e
FB		 446 }
447}
b346ff46
FB		 448#endif
449
450#ifdef TARGET_ARM
451
49017bd8 452#define get_user_code_u32(x, gaddr, env) \
d8fd2954 453 ({ abi_long __r = get_user_u32((x), (gaddr)); \
f9fd40eb 454 if (!__r && bswap_code(arm_sctlr_b(env))) { \
d8fd2954
PB		 455 (x) = bswap32(x); \
456 } \
457 __r; \
458 })
459
49017bd8 460#define get_user_code_u16(x, gaddr, env) \
d8fd2954 461 ({ abi_long __r = get_user_u16((x), (gaddr)); \
f9fd40eb 462 if (!__r && bswap_code(arm_sctlr_b(env))) { \
d8fd2954
PB		 463 (x) = bswap16(x); \
464 } \
465 __r; \
466 })
467
c3ae85fc
PB		 468#define get_user_data_u32(x, gaddr, env) \
469 ({ abi_long __r = get_user_u32((x), (gaddr)); \
470 if (!__r && arm_cpu_bswap_data(env)) { \
471 (x) = bswap32(x); \
472 } \
473 __r; \
474 })
475
476#define get_user_data_u16(x, gaddr, env) \
477 ({ abi_long __r = get_user_u16((x), (gaddr)); \
478 if (!__r && arm_cpu_bswap_data(env)) { \
479 (x) = bswap16(x); \
480 } \
481 __r; \
482 })
483
484#define put_user_data_u32(x, gaddr, env) \
485 ({ typeof(x) __x = (x); \
486 if (arm_cpu_bswap_data(env)) { \
487 __x = bswap32(__x); \
488 } \
489 put_user_u32(__x, (gaddr)); \
490 })
491
492#define put_user_data_u16(x, gaddr, env) \
493 ({ typeof(x) __x = (x); \
494 if (arm_cpu_bswap_data(env)) { \
495 __x = bswap16(__x); \
496 } \
497 put_user_u16(__x, (gaddr)); \
498 })
499
1861c454
PM		 500#ifdef TARGET_ABI32
501/* Commpage handling -- there is no commpage for AArch64 */
502
97cc7560
DDAG		 503/*
504 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
505 * Input:
506 * r0 = pointer to oldval
507 * r1 = pointer to newval
508 * r2 = pointer to target value
509 *
510 * Output:
511 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
512 * C set if *ptr was changed, clear if no exchange happened
513 *
514 * Note segv's in kernel helpers are a bit tricky, we can set the
515 * data address sensibly but the PC address is just the entry point.
516 */
517static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
518{
519 uint64_t oldval, newval, val;
520 uint32_t addr, cpsr;
521 target_siginfo_t info;
522
523 /* Based on the 32 bit code in do_kernel_trap */
524
525 /* XXX: This only works between threads, not between processes.
526 It's probably possible to implement this with native host
527 operations. However things like ldrex/strex are much harder so
528 there's not much point trying. */
529 start_exclusive();
530 cpsr = cpsr_read(env);
531 addr = env->regs[2];
532
533 if (get_user_u64(oldval, env->regs[0])) {
abf1172f 534 env->exception.vaddress = env->regs[0];
97cc7560
DDAG		 535 goto segv;
536 };
537
538 if (get_user_u64(newval, env->regs[1])) {
abf1172f 539 env->exception.vaddress = env->regs[1];
97cc7560
DDAG		 540 goto segv;
541 };
542
543 if (get_user_u64(val, addr)) {
abf1172f 544 env->exception.vaddress = addr;
97cc7560
DDAG		 545 goto segv;
546 }
547
548 if (val == oldval) {
549 val = newval;
550
551 if (put_user_u64(val, addr)) {
abf1172f 552 env->exception.vaddress = addr;
97cc7560
DDAG		 553 goto segv;
554 };
555
556 env->regs[0] = 0;
557 cpsr |= CPSR_C;
558 } else {
559 env->regs[0] = -1;
560 cpsr &= ~CPSR_C;
561 }
50866ba5 562 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
97cc7560
DDAG		 563 end_exclusive();
564 return;
565
566segv:
567 end_exclusive();
568 /* We get the PC of the entry address - which is as good as anything,
569 on a real kernel what you get depends on which mode it uses. */
a86b3c64 570 info.si_signo = TARGET_SIGSEGV;
97cc7560
DDAG		 571 info.si_errno = 0;
572 /* XXX: check env->error_code */
573 info.si_code = TARGET_SEGV_MAPERR;
abf1172f 574 info._sifields._sigfault._addr = env->exception.vaddress;
97cc7560 575 queue_signal(env, info.si_signo, &info);
97cc7560
DDAG		 576}
577
fbb4a2e3
PB		 578/* Handle a jump to the kernel code page. */
579static int
580do_kernel_trap(CPUARMState *env)
581{
582 uint32_t addr;
583 uint32_t cpsr;
584 uint32_t val;
585
586 switch (env->regs[15]) {
587 case 0xffff0fa0: /* __kernel_memory_barrier */
588 /* ??? No-op. Will need to do better for SMP. */
589 break;
590 case 0xffff0fc0: /* __kernel_cmpxchg */
d5975363
PB		 591 /* XXX: This only works between threads, not between processes.
592 It's probably possible to implement this with native host
593 operations. However things like ldrex/strex are much harder so
594 there's not much point trying. */
595 start_exclusive();
fbb4a2e3
PB		 596 cpsr = cpsr_read(env);
597 addr = env->regs[2];
598 /* FIXME: This should SEGV if the access fails. */
599 if (get_user_u32(val, addr))
600 val = ~env->regs[0];
601 if (val == env->regs[0]) {
602 val = env->regs[1];
603 /* FIXME: Check for segfaults. */
604 put_user_u32(val, addr);
605 env->regs[0] = 0;
606 cpsr |= CPSR_C;
607 } else {
608 env->regs[0] = -1;
609 cpsr &= ~CPSR_C;
610 }
50866ba5 611 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
d5975363 612 end_exclusive();
fbb4a2e3
PB		 613 break;
614 case 0xffff0fe0: /* __kernel_get_tls */
b8d43285 615 env->regs[0] = cpu_get_tls(env);
fbb4a2e3 616 break;
97cc7560
DDAG		 617 case 0xffff0f60: /* __kernel_cmpxchg64 */
618 arm_kernel_cmpxchg64_helper(env);
619 break;
620
fbb4a2e3
PB		 621 default:
622 return 1;
623 }
624 /* Jump back to the caller. */
625 addr = env->regs[14];
626 if (addr & 1) {
627 env->thumb = 1;
628 addr &= ~1;
629 }
630 env->regs[15] = addr;
631
632 return 0;
633}
634
fa2ef212 635/* Store exclusive handling for AArch32 */
426f5abc
PB		 636static int do_strex(CPUARMState *env)
637{
03d05e2d 638 uint64_t val;
426f5abc
PB		 639 int size;
640 int rc = 1;
641 int segv = 0;
642 uint32_t addr;
643 start_exclusive();
03d05e2d 644 if (env->exclusive_addr != env->exclusive_test) {
426f5abc
PB		 645 goto fail;
646 }
03d05e2d
PM		 647 /* We know we're always AArch32 so the address is in uint32_t range
648 * unless it was the -1 exclusive-monitor-lost value (which won't
649 * match exclusive_test above).
650 */
651 assert(extract64(env->exclusive_addr, 32, 32) == 0);
652 addr = env->exclusive_addr;
426f5abc
PB		 653 size = env->exclusive_info & 0xf;
654 switch (size) {
655 case 0:
656 segv = get_user_u8(val, addr);
657 break;
658 case 1:
c3ae85fc 659 segv = get_user_data_u16(val, addr, env);
426f5abc
PB		 660 break;
661 case 2:
662 case 3:
c3ae85fc 663 segv = get_user_data_u32(val, addr, env);
426f5abc 664 break;
f7001a3b
AJ		 665 default:
666 abort();
426f5abc
PB		 667 }
668 if (segv) {
abf1172f 669 env->exception.vaddress = addr;
426f5abc
PB		 670 goto done;
671 }
426f5abc 672 if (size == 3) {
03d05e2d 673 uint32_t valhi;
c3ae85fc 674 segv = get_user_data_u32(valhi, addr + 4, env);
426f5abc 675 if (segv) {
abf1172f 676 env->exception.vaddress = addr + 4;
426f5abc
PB		 677 goto done;
678 }
c3ae85fc
PB		 679 if (arm_cpu_bswap_data(env)) {
680 val = deposit64((uint64_t)valhi, 32, 32, val);
681 } else {
682 val = deposit64(val, 32, 32, valhi);
683 }
426f5abc 684 }
03d05e2d
PM		 685 if (val != env->exclusive_val) {
686 goto fail;
687 }
688
426f5abc
PB		 689 val = env->regs[(env->exclusive_info >> 8) & 0xf];
690 switch (size) {
691 case 0:
692 segv = put_user_u8(val, addr);
693 break;
694 case 1:
c3ae85fc 695 segv = put_user_data_u16(val, addr, env);
426f5abc
PB		 696 break;
697 case 2:
698 case 3:
c3ae85fc 699 segv = put_user_data_u32(val, addr, env);
426f5abc
PB		 700 break;
701 }
702 if (segv) {
abf1172f 703 env->exception.vaddress = addr;
426f5abc
PB		 704 goto done;
705 }
706 if (size == 3) {
707 val = env->regs[(env->exclusive_info >> 12) & 0xf];
c3ae85fc 708 segv = put_user_data_u32(val, addr + 4, env);
426f5abc 709 if (segv) {
abf1172f 710 env->exception.vaddress = addr + 4;
426f5abc
PB		 711 goto done;
712 }
713 }
714 rc = 0;
715fail:
725b8a69 716 env->regs[15] += 4;
426f5abc
PB		 717 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
718done:
719 end_exclusive();
720 return segv;
721}
722
b346ff46
FB		 723void cpu_loop(CPUARMState *env)
724{
0315c31c 725 CPUState *cs = CPU(arm_env_get_cpu(env));
b346ff46
FB		 726 int trapnr;
727 unsigned int n, insn;
c227f099 728 target_siginfo_t info;
b5ff1b31 729 uint32_t addr;
f0267ef7 730 abi_ulong ret;
3b46e624 731
b346ff46 732 for(;;) {
0315c31c 733 cpu_exec_start(cs);
ea3e9847 734 trapnr = cpu_arm_exec(cs);
0315c31c 735 cpu_exec_end(cs);
b346ff46
FB		 736 switch(trapnr) {
737 case EXCP_UDEF:
c6981055 738 {
0429a971 739 TaskState *ts = cs->opaque;
c6981055 740 uint32_t opcode;
6d9a42be 741 int rc;
c6981055
FB		 742
743 /* we handle the FPU emulation here, as Linux */
744 /* we get the opcode */
2f619698 745 /* FIXME - what to do if get_user() fails? */
49017bd8 746 get_user_code_u32(opcode, env->regs[15], env);
3b46e624 747
6d9a42be
AJ		 748 rc = EmulateAll(opcode, &ts->fpa, env);
749 if (rc == 0) { /* illegal instruction */
a86b3c64 750 info.si_signo = TARGET_SIGILL;
c6981055
FB		 751 info.si_errno = 0;
752 info.si_code = TARGET_ILL_ILLOPN;
753 info._sifields._sigfault._addr = env->regs[15];
624f7979 754 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 755 } else if (rc < 0) { /* FP exception */
756 int arm_fpe=0;
757
758 /* translate softfloat flags to FPSR flags */
759 if (-rc & float_flag_invalid)
760 arm_fpe |= BIT_IOC;
761 if (-rc & float_flag_divbyzero)
762 arm_fpe |= BIT_DZC;
763 if (-rc & float_flag_overflow)
764 arm_fpe |= BIT_OFC;
765 if (-rc & float_flag_underflow)
766 arm_fpe |= BIT_UFC;
767 if (-rc & float_flag_inexact)
768 arm_fpe |= BIT_IXC;
769
770 FPSR fpsr = ts->fpa.fpsr;
771 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
772
773 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
a86b3c64 774 info.si_signo = TARGET_SIGFPE;
6d9a42be
AJ		 775 info.si_errno = 0;
776
777 /* ordered by priority, least first */
778 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
779 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
780 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
781 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
782 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
783
784 info._sifields._sigfault._addr = env->regs[15];
624f7979 785 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 786 } else {
787 env->regs[15] += 4;
788 }
789
790 /* accumulate unenabled exceptions */
791 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
792 fpsr |= BIT_IXC;
793 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
794 fpsr |= BIT_UFC;
795 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
796 fpsr |= BIT_OFC;
797 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
798 fpsr |= BIT_DZC;
799 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
800 fpsr |= BIT_IOC;
801 ts->fpa.fpsr=fpsr;
802 } else { /* everything OK */
c6981055
FB		 803 /* increment PC */
804 env->regs[15] += 4;
805 }
806 }
b346ff46
FB		 807 break;
808 case EXCP_SWI:
06c949e6 809 case EXCP_BKPT:
b346ff46 810 {
ce4defa0 811 env->eabi = 1;
b346ff46 812 /* system call */
06c949e6
PB		 813 if (trapnr == EXCP_BKPT) {
814 if (env->thumb) {
2f619698 815 /* FIXME - what to do if get_user() fails? */
49017bd8 816 get_user_code_u16(insn, env->regs[15], env);
06c949e6
PB		 817 n = insn & 0xff;
818 env->regs[15] += 2;
819 } else {
2f619698 820 /* FIXME - what to do if get_user() fails? */
49017bd8 821 get_user_code_u32(insn, env->regs[15], env);
06c949e6
PB		 822 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
823 env->regs[15] += 4;
824 }
192c7bd9 825 } else {
06c949e6 826 if (env->thumb) {
2f619698 827 /* FIXME - what to do if get_user() fails? */
49017bd8 828 get_user_code_u16(insn, env->regs[15] - 2, env);
06c949e6
PB		 829 n = insn & 0xff;
830 } else {
2f619698 831 /* FIXME - what to do if get_user() fails? */
49017bd8 832 get_user_code_u32(insn, env->regs[15] - 4, env);
06c949e6
PB		 833 n = insn & 0xffffff;
834 }
192c7bd9
FB		 835 }
836
6f1f31c0 837 if (n == ARM_NR_cacheflush) {
dcfd14b3 838 /* nop */
a4f81979
FB		 839 } else if (n == ARM_NR_semihosting
840 || n == ARM_NR_thumb_semihosting) {
841 env->regs[0] = do_arm_semihosting (env);
3a1363ac 842 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
b346ff46 843 /* linux syscall */
ce4defa0 844 if (env->thumb || n == 0) {
192c7bd9
FB		 845 n = env->regs[7];
846 } else {
847 n -= ARM_SYSCALL_BASE;
ce4defa0 848 env->eabi = 0;
192c7bd9 849 }
fbb4a2e3
PB		 850 if ( n > ARM_NR_BASE) {
851 switch (n) {
852 case ARM_NR_cacheflush:
dcfd14b3 853 /* nop */
fbb4a2e3
PB		 854 break;
855 case ARM_NR_set_tls:
856 cpu_set_tls(env, env->regs[0]);
857 env->regs[0] = 0;
858 break;
d5355087
HL		 859 case ARM_NR_breakpoint:
860 env->regs[15] -= env->thumb ? 2 : 4;
861 goto excp_debug;
fbb4a2e3
PB		 862 default:
863 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
864 n);
865 env->regs[0] = -TARGET_ENOSYS;
866 break;
867 }
868 } else {
f0267ef7
TB		 869 ret = do_syscall(env,
870 n,
871 env->regs[0],
872 env->regs[1],
873 env->regs[2],
874 env->regs[3],
875 env->regs[4],
876 env->regs[5],
877 0, 0);
878 if (ret == -TARGET_ERESTARTSYS) {
879 env->regs[15] -= env->thumb ? 2 : 4;
880 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
881 env->regs[0] = ret;
882 }
fbb4a2e3 883 }
b346ff46
FB		 884 } else {
885 goto error;
886 }
887 }
888 break;
43fff238
FB		 889 case EXCP_INTERRUPT:
890 /* just indicate that signals should be handled asap */
891 break;
abf1172f
PM		 892 case EXCP_STREX:
893 if (!do_strex(env)) {
894 break;
895 }
896 /* fall through for segv */
68016c62
FB		 897 case EXCP_PREFETCH_ABORT:
898 case EXCP_DATA_ABORT:
abf1172f 899 addr = env->exception.vaddress;
68016c62 900 {
a86b3c64 901 info.si_signo = TARGET_SIGSEGV;
68016c62
FB		 902 info.si_errno = 0;
903 /* XXX: check env->error_code */
904 info.si_code = TARGET_SEGV_MAPERR;
b5ff1b31 905 info._sifields._sigfault._addr = addr;
624f7979 906 queue_signal(env, info.si_signo, &info);
68016c62
FB		 907 }
908 break;
1fddef4b 909 case EXCP_DEBUG:
d5355087 910 excp_debug:
1fddef4b
FB		 911 {
912 int sig;
913
db6b81d4 914 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 915 if (sig)
916 {
917 info.si_signo = sig;
918 info.si_errno = 0;
919 info.si_code = TARGET_TRAP_BRKPT;
624f7979 920 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 921 }
922 }
923 break;
fbb4a2e3
PB		 924 case EXCP_KERNEL_TRAP:
925 if (do_kernel_trap(env))
926 goto error;
927 break;
f911e0a3
PM		 928 case EXCP_YIELD:
929 /* nothing to do here for user-mode, just resume guest code */
930 break;
b346ff46
FB		 931 default:
932 error:
120a9848 933 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
b346ff46
FB		 934 abort();
935 }
936 process_pending_signals(env);
937 }
938}
939
1861c454
PM		 940#else
941
fa2ef212
MM		 942/*
943 * Handle AArch64 store-release exclusive
944 *
945 * rs = gets the status result of store exclusive
946 * rt = is the register that is stored
947 * rt2 = is the second register store (in STP)
948 *
949 */
950static int do_strex_a64(CPUARMState *env)
951{
952 uint64_t val;
953 int size;
954 bool is_pair;
955 int rc = 1;
956 int segv = 0;
957 uint64_t addr;
958 int rs, rt, rt2;
959
960 start_exclusive();
961 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
962 size = extract32(env->exclusive_info, 0, 2);
963 is_pair = extract32(env->exclusive_info, 2, 1);
964 rs = extract32(env->exclusive_info, 4, 5);
965 rt = extract32(env->exclusive_info, 9, 5);
966 rt2 = extract32(env->exclusive_info, 14, 5);
967
968 addr = env->exclusive_addr;
969
970 if (addr != env->exclusive_test) {
971 goto finish;
972 }
973
974 switch (size) {
975 case 0:
976 segv = get_user_u8(val, addr);
977 break;
978 case 1:
979 segv = get_user_u16(val, addr);
980 break;
981 case 2:
982 segv = get_user_u32(val, addr);
983 break;
984 case 3:
985 segv = get_user_u64(val, addr);
986 break;
987 default:
988 abort();
989 }
990 if (segv) {
abf1172f 991 env->exception.vaddress = addr;
fa2ef212
MM		 992 goto error;
993 }
994 if (val != env->exclusive_val) {
995 goto finish;
996 }
997 if (is_pair) {
998 if (size == 2) {
999 segv = get_user_u32(val, addr + 4);
1000 } else {
1001 segv = get_user_u64(val, addr + 8);
1002 }
1003 if (segv) {
abf1172f 1004 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 1005 goto error;
1006 }
1007 if (val != env->exclusive_high) {
1008 goto finish;
1009 }
1010 }
2ea5a2ca
JG		 1011 /* handle the zero register */
1012 val = rt == 31 ? 0 : env->xregs[rt];
fa2ef212
MM		 1013 switch (size) {
1014 case 0:
1015 segv = put_user_u8(val, addr);
1016 break;
1017 case 1:
1018 segv = put_user_u16(val, addr);
1019 break;
1020 case 2:
1021 segv = put_user_u32(val, addr);
1022 break;
1023 case 3:
1024 segv = put_user_u64(val, addr);
1025 break;
1026 }
1027 if (segv) {
1028 goto error;
1029 }
1030 if (is_pair) {
2ea5a2ca
JG		 1031 /* handle the zero register */
1032 val = rt2 == 31 ? 0 : env->xregs[rt2];
fa2ef212
MM		 1033 if (size == 2) {
1034 segv = put_user_u32(val, addr + 4);
1035 } else {
1036 segv = put_user_u64(val, addr + 8);
1037 }
1038 if (segv) {
abf1172f 1039 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 1040 goto error;
1041 }
1042 }
1043 rc = 0;
1044finish:
1045 env->pc += 4;
1046 /* rs == 31 encodes a write to the ZR, thus throwing away
1047 * the status return. This is rather silly but valid.
1048 */
1049 if (rs < 31) {
1050 env->xregs[rs] = rc;
1051 }
1052error:
1053 /* instruction faulted, PC does not advance */
1054 /* either way a strex releases any exclusive lock we have */
1055 env->exclusive_addr = -1;
1056 end_exclusive();
1057 return segv;
1058}
1059
1861c454
PM		 1060/* AArch64 main loop */
1061void cpu_loop(CPUARMState *env)
1062{
1063 CPUState *cs = CPU(arm_env_get_cpu(env));
1064 int trapnr, sig;
f0267ef7 1065 abi_long ret;
1861c454 1066 target_siginfo_t info;
1861c454
PM		 1067
1068 for (;;) {
1069 cpu_exec_start(cs);
ea3e9847 1070 trapnr = cpu_arm_exec(cs);
1861c454
PM		 1071 cpu_exec_end(cs);
1072
1073 switch (trapnr) {
1074 case EXCP_SWI:
f0267ef7
TB		 1075 ret = do_syscall(env,
1076 env->xregs[8],
1077 env->xregs[0],
1078 env->xregs[1],
1079 env->xregs[2],
1080 env->xregs[3],
1081 env->xregs[4],
1082 env->xregs[5],
1083 0, 0);
1084 if (ret == -TARGET_ERESTARTSYS) {
1085 env->pc -= 4;
1086 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
1087 env->xregs[0] = ret;
1088 }
1861c454
PM		 1089 break;
1090 case EXCP_INTERRUPT:
1091 /* just indicate that signals should be handled asap */
1092 break;
1093 case EXCP_UDEF:
a86b3c64 1094 info.si_signo = TARGET_SIGILL;
1861c454
PM		 1095 info.si_errno = 0;
1096 info.si_code = TARGET_ILL_ILLOPN;
1097 info._sifields._sigfault._addr = env->pc;
1098 queue_signal(env, info.si_signo, &info);
1099 break;
abf1172f
PM		 1100 case EXCP_STREX:
1101 if (!do_strex_a64(env)) {
1102 break;
1103 }
1104 /* fall through for segv */
1861c454 1105 case EXCP_PREFETCH_ABORT:
1861c454 1106 case EXCP_DATA_ABORT:
a86b3c64 1107 info.si_signo = TARGET_SIGSEGV;
1861c454
PM		 1108 info.si_errno = 0;
1109 /* XXX: check env->error_code */
1110 info.si_code = TARGET_SEGV_MAPERR;
686581ad 1111 info._sifields._sigfault._addr = env->exception.vaddress;
1861c454
PM		 1112 queue_signal(env, info.si_signo, &info);
1113 break;
1114 case EXCP_DEBUG:
1115 case EXCP_BKPT:
1116 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1117 if (sig) {
1118 info.si_signo = sig;
1119 info.si_errno = 0;
1120 info.si_code = TARGET_TRAP_BRKPT;
1121 queue_signal(env, info.si_signo, &info);
1122 }
1123 break;
8012c84f
PM		 1124 case EXCP_SEMIHOST:
1125 env->xregs[0] = do_arm_semihosting(env);
1126 break;
f911e0a3
PM		 1127 case EXCP_YIELD:
1128 /* nothing to do here for user-mode, just resume guest code */
1129 break;
1861c454 1130 default:
120a9848 1131 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1861c454
PM		 1132 abort();
1133 }
1134 process_pending_signals(env);
fa2ef212
MM		 1135 /* Exception return on AArch64 always clears the exclusive monitor,
1136 * so any return to running guest code implies this.
1137 * A strex (successful or otherwise) also clears the monitor, so
1138 * we don't need to specialcase EXCP_STREX.
1139 */
1140 env->exclusive_addr = -1;
1861c454
PM		 1141 }
1142}
1143#endif /* ndef TARGET_ABI32 */
1144
b346ff46 1145#endif
1b6b029e 1146
d2fbca94
GX		 1147#ifdef TARGET_UNICORE32
1148
05390248 1149void cpu_loop(CPUUniCore32State *env)
d2fbca94 1150{
0315c31c 1151 CPUState *cs = CPU(uc32_env_get_cpu(env));
d2fbca94
GX		 1152 int trapnr;
1153 unsigned int n, insn;
1154 target_siginfo_t info;
1155
1156 for (;;) {
0315c31c 1157 cpu_exec_start(cs);
ea3e9847 1158 trapnr = uc32_cpu_exec(cs);
0315c31c 1159 cpu_exec_end(cs);
d2fbca94
GX		 1160 switch (trapnr) {
1161 case UC32_EXCP_PRIV:
1162 {
1163 /* system call */
1164 get_user_u32(insn, env->regs[31] - 4);
1165 n = insn & 0xffffff;
1166
1167 if (n >= UC32_SYSCALL_BASE) {
1168 /* linux syscall */
1169 n -= UC32_SYSCALL_BASE;
1170 if (n == UC32_SYSCALL_NR_set_tls) {
1171 cpu_set_tls(env, env->regs[0]);
1172 env->regs[0] = 0;
1173 } else {
1174 env->regs[0] = do_syscall(env,
1175 n,
1176 env->regs[0],
1177 env->regs[1],
1178 env->regs[2],
1179 env->regs[3],
1180 env->regs[4],
5945cfcb
PM		 1181 env->regs[5],
1182 0, 0);
d2fbca94
GX		 1183 }
1184 } else {
1185 goto error;
1186 }
1187 }
1188 break;
d48813dd
GX		 1189 case UC32_EXCP_DTRAP:
1190 case UC32_EXCP_ITRAP:
a86b3c64 1191 info.si_signo = TARGET_SIGSEGV;
d2fbca94
GX		 1192 info.si_errno = 0;
1193 /* XXX: check env->error_code */
1194 info.si_code = TARGET_SEGV_MAPERR;
1195 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1196 queue_signal(env, info.si_signo, &info);
1197 break;
1198 case EXCP_INTERRUPT:
1199 /* just indicate that signals should be handled asap */
1200 break;
1201 case EXCP_DEBUG:
1202 {
1203 int sig;
1204
db6b81d4 1205 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d2fbca94
GX		 1206 if (sig) {
1207 info.si_signo = sig;
1208 info.si_errno = 0;
1209 info.si_code = TARGET_TRAP_BRKPT;
1210 queue_signal(env, info.si_signo, &info);
1211 }
1212 }
1213 break;
1214 default:
1215 goto error;
1216 }
1217 process_pending_signals(env);
1218 }
1219
1220error:
120a9848 1221 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
d2fbca94
GX		 1222 abort();
1223}
1224#endif
1225
93ac68bc 1226#ifdef TARGET_SPARC
ed23fbd9 1227#define SPARC64_STACK_BIAS 2047
93ac68bc 1228
060366c5
FB		 1229//#define DEBUG_WIN
1230
2623cbaf
FB		 1231/* WARNING: dealing with register windows _is_ complicated. More info
1232 can be found at http://www.sics.se/~psm/sparcstack.html */
060366c5
FB		 1233static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1234{
1a14026e 1235 index = (index + cwp * 16) % (16 * env->nwindows);
060366c5
FB		 1236 /* wrap handling : if cwp is on the last window, then we use the
1237 registers 'after' the end */
1a14026e
BS		 1238 if (index < 8 && env->cwp == env->nwindows - 1)
1239 index += 16 * env->nwindows;
060366c5
FB		 1240 return index;
1241}
1242
2623cbaf
FB		 1243/* save the register window 'cwp1' */
1244static inline void save_window_offset(CPUSPARCState *env, int cwp1)
060366c5 1245{
2623cbaf 1246 unsigned int i;
992f48a0 1247 abi_ulong sp_ptr;
3b46e624 1248
53a5960a 1249 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1250#ifdef TARGET_SPARC64
1251 if (sp_ptr & 3)
1252 sp_ptr += SPARC64_STACK_BIAS;
1253#endif
060366c5 1254#if defined(DEBUG_WIN)
2daf0284
BS		 1255 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1256 sp_ptr, cwp1);
060366c5 1257#endif
2623cbaf 1258 for(i = 0; i < 16; i++) {
2f619698
FB		 1259 /* FIXME - what to do if put_user() fails? */
1260 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1261 sp_ptr += sizeof(abi_ulong);
2623cbaf 1262 }
060366c5
FB		 1263}
1264
1265static void save_window(CPUSPARCState *env)
1266{
5ef54116 1267#ifndef TARGET_SPARC64
2623cbaf 1268 unsigned int new_wim;
1a14026e
BS		 1269 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1270 ((1LL << env->nwindows) - 1);
1271 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
2623cbaf 1272 env->wim = new_wim;
5ef54116 1273#else
1a14026e 1274 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
5ef54116
FB		 1275 env->cansave++;
1276 env->canrestore--;
1277#endif
060366c5
FB		 1278}
1279
1280static void restore_window(CPUSPARCState *env)
1281{
eda52953
BS		 1282#ifndef TARGET_SPARC64
1283 unsigned int new_wim;
1284#endif
1285 unsigned int i, cwp1;
992f48a0 1286 abi_ulong sp_ptr;
3b46e624 1287
eda52953 1288#ifndef TARGET_SPARC64
1a14026e
BS		 1289 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1290 ((1LL << env->nwindows) - 1);
eda52953 1291#endif
3b46e624 1292
060366c5 1293 /* restore the invalid window */
1a14026e 1294 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
53a5960a 1295 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1296#ifdef TARGET_SPARC64
1297 if (sp_ptr & 3)
1298 sp_ptr += SPARC64_STACK_BIAS;
1299#endif
060366c5 1300#if defined(DEBUG_WIN)
2daf0284
BS		 1301 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1302 sp_ptr, cwp1);
060366c5 1303#endif
2623cbaf 1304 for(i = 0; i < 16; i++) {
2f619698
FB		 1305 /* FIXME - what to do if get_user() fails? */
1306 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1307 sp_ptr += sizeof(abi_ulong);
2623cbaf 1308 }
5ef54116
FB		 1309#ifdef TARGET_SPARC64
1310 env->canrestore++;
1a14026e
BS		 1311 if (env->cleanwin < env->nwindows - 1)
1312 env->cleanwin++;
5ef54116 1313 env->cansave--;
eda52953
BS		 1314#else
1315 env->wim = new_wim;
5ef54116 1316#endif
060366c5
FB		 1317}
1318
1319static void flush_windows(CPUSPARCState *env)
1320{
1321 int offset, cwp1;
2623cbaf
FB		 1322
1323 offset = 1;
060366c5
FB		 1324 for(;;) {
1325 /* if restore would invoke restore_window(), then we can stop */
1a14026e 1326 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
eda52953 1327#ifndef TARGET_SPARC64
060366c5
FB		 1328 if (env->wim & (1 << cwp1))
1329 break;
eda52953
BS		 1330#else
1331 if (env->canrestore == 0)
1332 break;
1333 env->cansave++;
1334 env->canrestore--;
1335#endif
2623cbaf 1336 save_window_offset(env, cwp1);
060366c5
FB		 1337 offset++;
1338 }
1a14026e 1339 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
eda52953
BS		 1340#ifndef TARGET_SPARC64
1341 /* set wim so that restore will reload the registers */
2623cbaf 1342 env->wim = 1 << cwp1;
eda52953 1343#endif
2623cbaf
FB		 1344#if defined(DEBUG_WIN)
1345 printf("flush_windows: nb=%d\n", offset - 1);
80a9d035 1346#endif
2623cbaf 1347}
060366c5 1348
93ac68bc
FB		 1349void cpu_loop (CPUSPARCState *env)
1350{
878096ee 1351 CPUState *cs = CPU(sparc_env_get_cpu(env));
2cc20260
RH		 1352 int trapnr;
1353 abi_long ret;
c227f099 1354 target_siginfo_t info;
3b46e624 1355
060366c5 1356 while (1) {
b040bc9c 1357 cpu_exec_start(cs);
ea3e9847 1358 trapnr = cpu_sparc_exec(cs);
b040bc9c 1359 cpu_exec_end(cs);
3b46e624 1360
20132b96
RH		 1361 /* Compute PSR before exposing state. */
1362 if (env->cc_op != CC_OP_FLAGS) {
1363 cpu_get_psr(env);
1364 }
1365
060366c5 1366 switch (trapnr) {
5ef54116 1367#ifndef TARGET_SPARC64
5fafdf24 1368 case 0x88:
060366c5 1369 case 0x90:
5ef54116 1370#else
cb33da57 1371 case 0x110:
5ef54116
FB		 1372 case 0x16d:
1373#endif
060366c5 1374 ret = do_syscall (env, env->gregs[1],
5fafdf24
TS		 1375 env->regwptr[0], env->regwptr[1],
1376 env->regwptr[2], env->regwptr[3],
5945cfcb
PM		 1377 env->regwptr[4], env->regwptr[5],
1378 0, 0);
2cc20260 1379 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
992f48a0 1380#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1381 env->xcc |= PSR_CARRY;
1382#else
060366c5 1383 env->psr |= PSR_CARRY;
27908725 1384#endif
060366c5
FB		 1385 ret = -ret;
1386 } else {
992f48a0 1387#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1388 env->xcc &= ~PSR_CARRY;
1389#else
060366c5 1390 env->psr &= ~PSR_CARRY;
27908725 1391#endif
060366c5
FB		 1392 }
1393 env->regwptr[0] = ret;
1394 /* next instruction */
1395 env->pc = env->npc;
1396 env->npc = env->npc + 4;
1397 break;
1398 case 0x83: /* flush windows */
992f48a0
BS		 1399#ifdef TARGET_ABI32
1400 case 0x103:
1401#endif
2623cbaf 1402 flush_windows(env);
060366c5
FB		 1403 /* next instruction */
1404 env->pc = env->npc;
1405 env->npc = env->npc + 4;
1406 break;
3475187d 1407#ifndef TARGET_SPARC64
060366c5
FB		 1408 case TT_WIN_OVF: /* window overflow */
1409 save_window(env);
1410 break;
1411 case TT_WIN_UNF: /* window underflow */
1412 restore_window(env);
1413 break;
61ff6f58
FB		 1414 case TT_TFAULT:
1415 case TT_DFAULT:
1416 {
59f7182f 1417 info.si_signo = TARGET_SIGSEGV;
61ff6f58
FB		 1418 info.si_errno = 0;
1419 /* XXX: check env->error_code */
1420 info.si_code = TARGET_SEGV_MAPERR;
1421 info._sifields._sigfault._addr = env->mmuregs[4];
624f7979 1422 queue_signal(env, info.si_signo, &info);
61ff6f58
FB		 1423 }
1424 break;
3475187d 1425#else
5ef54116
FB		 1426 case TT_SPILL: /* window overflow */
1427 save_window(env);
1428 break;
1429 case TT_FILL: /* window underflow */
1430 restore_window(env);
1431 break;
7f84a729
BS		 1432 case TT_TFAULT:
1433 case TT_DFAULT:
1434 {
59f7182f 1435 info.si_signo = TARGET_SIGSEGV;
7f84a729
BS		 1436 info.si_errno = 0;
1437 /* XXX: check env->error_code */
1438 info.si_code = TARGET_SEGV_MAPERR;
1439 if (trapnr == TT_DFAULT)
1440 info._sifields._sigfault._addr = env->dmmuregs[4];
1441 else
8194f35a 1442 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
624f7979 1443 queue_signal(env, info.si_signo, &info);
7f84a729
BS		 1444 }
1445 break;
27524dc3 1446#ifndef TARGET_ABI32
5bfb56b2
BS		 1447 case 0x16e:
1448 flush_windows(env);
1449 sparc64_get_context(env);
1450 break;
1451 case 0x16f:
1452 flush_windows(env);
1453 sparc64_set_context(env);
1454 break;
27524dc3 1455#endif
3475187d 1456#endif
48dc41eb
FB		 1457 case EXCP_INTERRUPT:
1458 /* just indicate that signals should be handled asap */
1459 break;
75f22e4e
RH		 1460 case TT_ILL_INSN:
1461 {
1462 info.si_signo = TARGET_SIGILL;
1463 info.si_errno = 0;
1464 info.si_code = TARGET_ILL_ILLOPC;
1465 info._sifields._sigfault._addr = env->pc;
1466 queue_signal(env, info.si_signo, &info);
1467 }
1468 break;
1fddef4b
FB		 1469 case EXCP_DEBUG:
1470 {
1471 int sig;
1472
db6b81d4 1473 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 1474 if (sig)
1475 {
1476 info.si_signo = sig;
1477 info.si_errno = 0;
1478 info.si_code = TARGET_TRAP_BRKPT;
624f7979 1479 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 1480 }
1481 }
1482 break;
060366c5
FB		 1483 default:
1484 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 1485 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 1486 exit(EXIT_FAILURE);
060366c5
FB		 1487 }
1488 process_pending_signals (env);
1489 }
93ac68bc
FB		 1490}
1491
1492#endif
1493
67867308 1494#ifdef TARGET_PPC
05390248 1495static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
9fddaa0c 1496{
4a7428c5 1497 return cpu_get_host_ticks();
9fddaa0c 1498}
3b46e624 1499
05390248 1500uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
9fddaa0c 1501{
e3ea6529 1502 return cpu_ppc_get_tb(env);
9fddaa0c 1503}
3b46e624 1504
05390248 1505uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
9fddaa0c
FB		 1506{
1507 return cpu_ppc_get_tb(env) >> 32;
1508}
3b46e624 1509
05390248 1510uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
9fddaa0c 1511{
b711de95 1512 return cpu_ppc_get_tb(env);
9fddaa0c 1513}
5fafdf24 1514
05390248 1515uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
9fddaa0c 1516{
a062e36c 1517 return cpu_ppc_get_tb(env) >> 32;
9fddaa0c 1518}
76a66253 1519
05390248 1520uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
76a66253
JM		 1521__attribute__ (( alias ("cpu_ppc_load_tbu") ));
1522
05390248 1523uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
9fddaa0c 1524{
76a66253 1525 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
9fddaa0c 1526}
76a66253 1527
a750fc0b 1528/* XXX: to be fixed */
73b01960 1529int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
a750fc0b
JM		 1530{
1531 return -1;
1532}
1533
73b01960 1534int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
a750fc0b
JM		 1535{
1536 return -1;
1537}
1538
56f066bb
NF		 1539static int do_store_exclusive(CPUPPCState *env)
1540{
1541 target_ulong addr;
1542 target_ulong page_addr;
e22c357b 1543 target_ulong val, val2 __attribute__((unused)) = 0;
56f066bb
NF		 1544 int flags;
1545 int segv = 0;
1546
1547 addr = env->reserve_ea;
1548 page_addr = addr & TARGET_PAGE_MASK;
1549 start_exclusive();
1550 mmap_lock();
1551 flags = page_get_flags(page_addr);
1552 if ((flags & PAGE_READ) == 0) {
1553 segv = 1;
1554 } else {
1555 int reg = env->reserve_info & 0x1f;
4b1daa72 1556 int size = env->reserve_info >> 5;
56f066bb
NF		 1557 int stored = 0;
1558
1559 if (addr == env->reserve_addr) {
1560 switch (size) {
1561 case 1: segv = get_user_u8(val, addr); break;
1562 case 2: segv = get_user_u16(val, addr); break;
1563 case 4: segv = get_user_u32(val, addr); break;
1564#if defined(TARGET_PPC64)
1565 case 8: segv = get_user_u64(val, addr); break;
27b95bfe
TM		 1566 case 16: {
1567 segv = get_user_u64(val, addr);
1568 if (!segv) {
1569 segv = get_user_u64(val2, addr + 8);
1570 }
1571 break;
1572 }
56f066bb
NF		 1573#endif
1574 default: abort();
1575 }
1576 if (!segv && val == env->reserve_val) {
1577 val = env->gpr[reg];
1578 switch (size) {
1579 case 1: segv = put_user_u8(val, addr); break;
1580 case 2: segv = put_user_u16(val, addr); break;
1581 case 4: segv = put_user_u32(val, addr); break;
1582#if defined(TARGET_PPC64)
1583 case 8: segv = put_user_u64(val, addr); break;
27b95bfe
TM		 1584 case 16: {
1585 if (val2 == env->reserve_val2) {
e22c357b
DK		 1586 if (msr_le) {
1587 val2 = val;
1588 val = env->gpr[reg+1];
1589 } else {
1590 val2 = env->gpr[reg+1];
1591 }
27b95bfe
TM		 1592 segv = put_user_u64(val, addr);
1593 if (!segv) {
1594 segv = put_user_u64(val2, addr + 8);
1595 }
1596 }
1597 break;
1598 }
56f066bb
NF		 1599#endif
1600 default: abort();
1601 }
1602 if (!segv) {
1603 stored = 1;
1604 }
1605 }
1606 }
1607 env->crf[0] = (stored << 1) | xer_so;
1608 env->reserve_addr = (target_ulong)-1;
1609 }
1610 if (!segv) {
1611 env->nip += 4;
1612 }
1613 mmap_unlock();
1614 end_exclusive();
1615 return segv;
1616}
1617
67867308
FB		 1618void cpu_loop(CPUPPCState *env)
1619{
0315c31c 1620 CPUState *cs = CPU(ppc_env_get_cpu(env));
c227f099 1621 target_siginfo_t info;
61190b14 1622 int trapnr;
9e0e2f96 1623 target_ulong ret;
3b46e624 1624
67867308 1625 for(;;) {
0315c31c 1626 cpu_exec_start(cs);
ea3e9847 1627 trapnr = cpu_ppc_exec(cs);
0315c31c 1628 cpu_exec_end(cs);
67867308 1629 switch(trapnr) {
e1833e1f
JM		 1630 case POWERPC_EXCP_NONE:
1631 /* Just go on */
67867308 1632 break;
e1833e1f 1633 case POWERPC_EXCP_CRITICAL: /* Critical input */
a47dddd7 1634 cpu_abort(cs, "Critical interrupt while in user mode. "
e1833e1f 1635 "Aborting\n");
61190b14 1636 break;
e1833e1f 1637 case POWERPC_EXCP_MCHECK: /* Machine check exception */
a47dddd7 1638 cpu_abort(cs, "Machine check exception while in user mode. "
e1833e1f
JM		 1639 "Aborting\n");
1640 break;
1641 case POWERPC_EXCP_DSI: /* Data storage exception */
90e189ec 1642 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
e1833e1f
JM		 1643 env->spr[SPR_DAR]);
1644 /* XXX: check this. Seems bugged */
2be0071f
FB		 1645 switch (env->error_code & 0xFF000000) {
1646 case 0x40000000:
61190b14
FB		 1647 info.si_signo = TARGET_SIGSEGV;
1648 info.si_errno = 0;
1649 info.si_code = TARGET_SEGV_MAPERR;
1650 break;
2be0071f 1651 case 0x04000000:
61190b14
FB		 1652 info.si_signo = TARGET_SIGILL;
1653 info.si_errno = 0;
1654 info.si_code = TARGET_ILL_ILLADR;
1655 break;
2be0071f 1656 case 0x08000000:
61190b14
FB		 1657 info.si_signo = TARGET_SIGSEGV;
1658 info.si_errno = 0;
1659 info.si_code = TARGET_SEGV_ACCERR;
1660 break;
61190b14
FB		 1661 default:
1662 /* Let's send a regular segfault... */
e1833e1f
JM		 1663 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1664 env->error_code);
61190b14
FB		 1665 info.si_signo = TARGET_SIGSEGV;
1666 info.si_errno = 0;
1667 info.si_code = TARGET_SEGV_MAPERR;
1668 break;
1669 }
67867308 1670 info._sifields._sigfault._addr = env->nip;
624f7979 1671 queue_signal(env, info.si_signo, &info);
67867308 1672 break;
e1833e1f 1673 case POWERPC_EXCP_ISI: /* Instruction storage exception */
90e189ec
BS		 1674 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1675 "\n", env->spr[SPR_SRR0]);
e1833e1f 1676 /* XXX: check this */
2be0071f
FB		 1677 switch (env->error_code & 0xFF000000) {
1678 case 0x40000000:
61190b14 1679 info.si_signo = TARGET_SIGSEGV;
67867308 1680 info.si_errno = 0;
61190b14
FB		 1681 info.si_code = TARGET_SEGV_MAPERR;
1682 break;
2be0071f
FB		 1683 case 0x10000000:
1684 case 0x08000000:
61190b14
FB		 1685 info.si_signo = TARGET_SIGSEGV;
1686 info.si_errno = 0;
1687 info.si_code = TARGET_SEGV_ACCERR;
1688 break;
1689 default:
1690 /* Let's send a regular segfault... */
e1833e1f
JM		 1691 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1692 env->error_code);
61190b14
FB		 1693 info.si_signo = TARGET_SIGSEGV;
1694 info.si_errno = 0;
1695 info.si_code = TARGET_SEGV_MAPERR;
1696 break;
1697 }
1698 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1699 queue_signal(env, info.si_signo, &info);
67867308 1700 break;
e1833e1f 1701 case POWERPC_EXCP_EXTERNAL: /* External input */
a47dddd7 1702 cpu_abort(cs, "External interrupt while in user mode. "
e1833e1f
JM		 1703 "Aborting\n");
1704 break;
1705 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1706 EXCP_DUMP(env, "Unaligned memory access\n");
1707 /* XXX: check this */
61190b14 1708 info.si_signo = TARGET_SIGBUS;
67867308 1709 info.si_errno = 0;
61190b14 1710 info.si_code = TARGET_BUS_ADRALN;
6bb9a0a9 1711 info._sifields._sigfault._addr = env->nip;
624f7979 1712 queue_signal(env, info.si_signo, &info);
67867308 1713 break;
e1833e1f
JM		 1714 case POWERPC_EXCP_PROGRAM: /* Program exception */
1715 /* XXX: check this */
61190b14 1716 switch (env->error_code & ~0xF) {
e1833e1f
JM		 1717 case POWERPC_EXCP_FP:
1718 EXCP_DUMP(env, "Floating point program exception\n");
61190b14
FB		 1719 info.si_signo = TARGET_SIGFPE;
1720 info.si_errno = 0;
1721 switch (env->error_code & 0xF) {
e1833e1f 1722 case POWERPC_EXCP_FP_OX:
61190b14
FB		 1723 info.si_code = TARGET_FPE_FLTOVF;
1724 break;
e1833e1f 1725 case POWERPC_EXCP_FP_UX:
61190b14
FB		 1726 info.si_code = TARGET_FPE_FLTUND;
1727 break;
e1833e1f
JM		 1728 case POWERPC_EXCP_FP_ZX:
1729 case POWERPC_EXCP_FP_VXZDZ:
61190b14
FB		 1730 info.si_code = TARGET_FPE_FLTDIV;
1731 break;
e1833e1f 1732 case POWERPC_EXCP_FP_XX:
61190b14
FB		 1733 info.si_code = TARGET_FPE_FLTRES;
1734 break;
e1833e1f 1735 case POWERPC_EXCP_FP_VXSOFT:
61190b14
FB		 1736 info.si_code = TARGET_FPE_FLTINV;
1737 break;
7c58044c 1738 case POWERPC_EXCP_FP_VXSNAN:
e1833e1f
JM		 1739 case POWERPC_EXCP_FP_VXISI:
1740 case POWERPC_EXCP_FP_VXIDI:
1741 case POWERPC_EXCP_FP_VXIMZ:
1742 case POWERPC_EXCP_FP_VXVC:
1743 case POWERPC_EXCP_FP_VXSQRT:
1744 case POWERPC_EXCP_FP_VXCVI:
61190b14
FB		 1745 info.si_code = TARGET_FPE_FLTSUB;
1746 break;
1747 default:
e1833e1f
JM		 1748 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1749 env->error_code);
1750 break;
61190b14 1751 }
e1833e1f
JM		 1752 break;
1753 case POWERPC_EXCP_INVAL:
1754 EXCP_DUMP(env, "Invalid instruction\n");
61190b14
FB		 1755 info.si_signo = TARGET_SIGILL;
1756 info.si_errno = 0;
1757 switch (env->error_code & 0xF) {
e1833e1f 1758 case POWERPC_EXCP_INVAL_INVAL:
61190b14
FB		 1759 info.si_code = TARGET_ILL_ILLOPC;
1760 break;
e1833e1f 1761 case POWERPC_EXCP_INVAL_LSWX:
a750fc0b 1762 info.si_code = TARGET_ILL_ILLOPN;
61190b14 1763 break;
e1833e1f 1764 case POWERPC_EXCP_INVAL_SPR:
61190b14
FB		 1765 info.si_code = TARGET_ILL_PRVREG;
1766 break;
e1833e1f 1767 case POWERPC_EXCP_INVAL_FP:
61190b14
FB		 1768 info.si_code = TARGET_ILL_COPROC;
1769 break;
1770 default:
e1833e1f
JM		 1771 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1772 env->error_code & 0xF);
61190b14
FB		 1773 info.si_code = TARGET_ILL_ILLADR;
1774 break;
1775 }
1776 break;
e1833e1f
JM		 1777 case POWERPC_EXCP_PRIV:
1778 EXCP_DUMP(env, "Privilege violation\n");
61190b14
FB		 1779 info.si_signo = TARGET_SIGILL;
1780 info.si_errno = 0;
1781 switch (env->error_code & 0xF) {
e1833e1f 1782 case POWERPC_EXCP_PRIV_OPC:
61190b14
FB		 1783 info.si_code = TARGET_ILL_PRVOPC;
1784 break;
e1833e1f 1785 case POWERPC_EXCP_PRIV_REG:
61190b14 1786 info.si_code = TARGET_ILL_PRVREG;
e1833e1f 1787 break;
61190b14 1788 default:
e1833e1f
JM		 1789 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1790 env->error_code & 0xF);
61190b14
FB		 1791 info.si_code = TARGET_ILL_PRVOPC;
1792 break;
1793 }
1794 break;
e1833e1f 1795 case POWERPC_EXCP_TRAP:
a47dddd7 1796 cpu_abort(cs, "Tried to call a TRAP\n");
e1833e1f 1797 break;
61190b14
FB		 1798 default:
1799 /* Should not happen ! */
a47dddd7 1800 cpu_abort(cs, "Unknown program exception (%02x)\n",
e1833e1f
JM		 1801 env->error_code);
1802 break;
61190b14
FB		 1803 }
1804 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1805 queue_signal(env, info.si_signo, &info);
67867308 1806 break;
e1833e1f
JM		 1807 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1808 EXCP_DUMP(env, "No floating point allowed\n");
61190b14 1809 info.si_signo = TARGET_SIGILL;
67867308 1810 info.si_errno = 0;
61190b14
FB		 1811 info.si_code = TARGET_ILL_COPROC;
1812 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1813 queue_signal(env, info.si_signo, &info);
67867308 1814 break;
e1833e1f 1815 case POWERPC_EXCP_SYSCALL: /* System call exception */
a47dddd7 1816 cpu_abort(cs, "Syscall exception while in user mode. "
e1833e1f 1817 "Aborting\n");
61190b14 1818 break;
e1833e1f
JM		 1819 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1820 EXCP_DUMP(env, "No APU instruction allowed\n");
1821 info.si_signo = TARGET_SIGILL;
1822 info.si_errno = 0;
1823 info.si_code = TARGET_ILL_COPROC;
1824 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1825 queue_signal(env, info.si_signo, &info);
61190b14 1826 break;
e1833e1f 1827 case POWERPC_EXCP_DECR: /* Decrementer exception */
a47dddd7 1828 cpu_abort(cs, "Decrementer interrupt while in user mode. "
e1833e1f 1829 "Aborting\n");
61190b14 1830 break;
e1833e1f 1831 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
a47dddd7 1832 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
e1833e1f
JM		 1833 "Aborting\n");
1834 break;
1835 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
a47dddd7 1836 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
e1833e1f
JM		 1837 "Aborting\n");
1838 break;
1839 case POWERPC_EXCP_DTLB: /* Data TLB error */
a47dddd7 1840 cpu_abort(cs, "Data TLB exception while in user mode. "
e1833e1f
JM		 1841 "Aborting\n");
1842 break;
1843 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
a47dddd7 1844 cpu_abort(cs, "Instruction TLB exception while in user mode. "
e1833e1f
JM		 1845 "Aborting\n");
1846 break;
e1833e1f
JM		 1847 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1848 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1849 info.si_signo = TARGET_SIGILL;
1850 info.si_errno = 0;
1851 info.si_code = TARGET_ILL_COPROC;
1852 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1853 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1854 break;
1855 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
a47dddd7 1856 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
e1833e1f
JM		 1857 break;
1858 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
a47dddd7 1859 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
e1833e1f
JM		 1860 break;
1861 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
a47dddd7 1862 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1863 break;
1864 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
a47dddd7 1865 cpu_abort(cs, "Doorbell interrupt while in user mode. "
e1833e1f
JM		 1866 "Aborting\n");
1867 break;
1868 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
a47dddd7 1869 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
e1833e1f
JM		 1870 "Aborting\n");
1871 break;
1872 case POWERPC_EXCP_RESET: /* System reset exception */
a47dddd7 1873 cpu_abort(cs, "Reset interrupt while in user mode. "
e1833e1f
JM		 1874 "Aborting\n");
1875 break;
e1833e1f 1876 case POWERPC_EXCP_DSEG: /* Data segment exception */
a47dddd7 1877 cpu_abort(cs, "Data segment exception while in user mode. "
e1833e1f
JM		 1878 "Aborting\n");
1879 break;
1880 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
a47dddd7 1881 cpu_abort(cs, "Instruction segment exception "
e1833e1f
JM		 1882 "while in user mode. Aborting\n");
1883 break;
e85e7c6e 1884 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1885 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
a47dddd7 1886 cpu_abort(cs, "Hypervisor decrementer interrupt "
e1833e1f
JM		 1887 "while in user mode. Aborting\n");
1888 break;
e1833e1f
JM		 1889 case POWERPC_EXCP_TRACE: /* Trace exception */
1890 /* Nothing to do:
1891 * we use this exception to emulate step-by-step execution mode.
1892 */
1893 break;
e85e7c6e 1894 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1895 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
a47dddd7 1896 cpu_abort(cs, "Hypervisor data storage exception "
e1833e1f
JM		 1897 "while in user mode. Aborting\n");
1898 break;
1899 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
a47dddd7 1900 cpu_abort(cs, "Hypervisor instruction storage exception "
e1833e1f
JM		 1901 "while in user mode. Aborting\n");
1902 break;
1903 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
a47dddd7 1904 cpu_abort(cs, "Hypervisor data segment exception "
e1833e1f
JM		 1905 "while in user mode. Aborting\n");
1906 break;
1907 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
a47dddd7 1908 cpu_abort(cs, "Hypervisor instruction segment exception "
e1833e1f
JM		 1909 "while in user mode. Aborting\n");
1910 break;
e1833e1f
JM		 1911 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1912 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1913 info.si_signo = TARGET_SIGILL;
1914 info.si_errno = 0;
1915 info.si_code = TARGET_ILL_COPROC;
1916 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1917 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1918 break;
1919 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
a47dddd7 1920 cpu_abort(cs, "Programmable interval timer interrupt "
e1833e1f
JM		 1921 "while in user mode. Aborting\n");
1922 break;
1923 case POWERPC_EXCP_IO: /* IO error exception */
a47dddd7 1924 cpu_abort(cs, "IO error exception while in user mode. "
e1833e1f
JM		 1925 "Aborting\n");
1926 break;
1927 case POWERPC_EXCP_RUNM: /* Run mode exception */
a47dddd7 1928 cpu_abort(cs, "Run mode exception while in user mode. "
e1833e1f
JM		 1929 "Aborting\n");
1930 break;
1931 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
a47dddd7 1932 cpu_abort(cs, "Emulation trap exception not handled\n");
e1833e1f
JM		 1933 break;
1934 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
a47dddd7 1935 cpu_abort(cs, "Instruction fetch TLB exception "
e1833e1f
JM		 1936 "while in user-mode. Aborting");
1937 break;
1938 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
a47dddd7 1939 cpu_abort(cs, "Data load TLB exception while in user-mode. "
e1833e1f
JM		 1940 "Aborting");
1941 break;
1942 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
a47dddd7 1943 cpu_abort(cs, "Data store TLB exception while in user-mode. "
e1833e1f
JM		 1944 "Aborting");
1945 break;
1946 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
a47dddd7 1947 cpu_abort(cs, "Floating-point assist exception not handled\n");
e1833e1f
JM		 1948 break;
1949 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
a47dddd7 1950 cpu_abort(cs, "Instruction address breakpoint exception "
e1833e1f
JM		 1951 "not handled\n");
1952 break;
1953 case POWERPC_EXCP_SMI: /* System management interrupt */
a47dddd7 1954 cpu_abort(cs, "System management interrupt while in user mode. "
e1833e1f
JM		 1955 "Aborting\n");
1956 break;
1957 case POWERPC_EXCP_THERM: /* Thermal interrupt */
a47dddd7 1958 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
e1833e1f
JM		 1959 "Aborting\n");
1960 break;
1961 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
a47dddd7 1962 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1963 break;
1964 case POWERPC_EXCP_VPUA: /* Vector assist exception */
a47dddd7 1965 cpu_abort(cs, "Vector assist exception not handled\n");
e1833e1f
JM		 1966 break;
1967 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
a47dddd7 1968 cpu_abort(cs, "Soft patch exception not handled\n");
e1833e1f
JM		 1969 break;
1970 case POWERPC_EXCP_MAINT: /* Maintenance exception */
a47dddd7 1971 cpu_abort(cs, "Maintenance exception while in user mode. "
e1833e1f
JM		 1972 "Aborting\n");
1973 break;
1974 case POWERPC_EXCP_STOP: /* stop translation */
1975 /* We did invalidate the instruction cache. Go on */
1976 break;
1977 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1978 /* We just stopped because of a branch. Go on */
1979 break;
1980 case POWERPC_EXCP_SYSCALL_USER:
1981 /* system call in user-mode emulation */
1982 /* WARNING:
1983 * PPC ABI uses overflow flag in cr0 to signal an error
1984 * in syscalls.
1985 */
e1833e1f
JM		 1986 env->crf[0] &= ~0x1;
1987 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1988 env->gpr[5], env->gpr[6], env->gpr[7],
5945cfcb 1989 env->gpr[8], 0, 0);
6db9d00e
TB		 1990 if (ret == -TARGET_ERESTARTSYS) {
1991 env->nip -= 4;
1992 break;
1993 }
9e0e2f96 1994 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
bcd4933a
NF		 1995 /* Returning from a successful sigreturn syscall.
1996 Avoid corrupting register state. */
1997 break;
1998 }
9e0e2f96 1999 if (ret > (target_ulong)(-515)) {
e1833e1f
JM		 2000 env->crf[0] |= 0x1;
2001 ret = -ret;
61190b14 2002 }
e1833e1f 2003 env->gpr[3] = ret;
e1833e1f 2004 break;
56f066bb
NF		 2005 case POWERPC_EXCP_STCX:
2006 if (do_store_exclusive(env)) {
2007 info.si_signo = TARGET_SIGSEGV;
2008 info.si_errno = 0;
2009 info.si_code = TARGET_SEGV_MAPERR;
2010 info._sifields._sigfault._addr = env->nip;
2011 queue_signal(env, info.si_signo, &info);
2012 }
2013 break;
71f75756
AJ		 2014 case EXCP_DEBUG:
2015 {
2016 int sig;
2017
db6b81d4 2018 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
71f75756
AJ		 2019 if (sig) {
2020 info.si_signo = sig;
2021 info.si_errno = 0;
2022 info.si_code = TARGET_TRAP_BRKPT;
2023 queue_signal(env, info.si_signo, &info);
2024 }
2025 }
2026 break;
56ba31ff
JM		 2027 case EXCP_INTERRUPT:
2028 /* just indicate that signals should be handled asap */
2029 break;
e1833e1f 2030 default:
a47dddd7 2031 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
e1833e1f 2032 break;
67867308
FB		 2033 }
2034 process_pending_signals(env);
2035 }
2036}
2037#endif
2038
048f6b4d
FB		 2039#ifdef TARGET_MIPS
2040
ff4f7382
RH		 2041# ifdef TARGET_ABI_MIPSO32
2042# define MIPS_SYS(name, args) args,
048f6b4d 2043static const uint8_t mips_syscall_args[] = {
29fb0f25 2044 MIPS_SYS(sys_syscall , 8) /* 4000 */
048f6b4d
FB		 2045 MIPS_SYS(sys_exit , 1)
2046 MIPS_SYS(sys_fork , 0)
2047 MIPS_SYS(sys_read , 3)
2048 MIPS_SYS(sys_write , 3)
2049 MIPS_SYS(sys_open , 3) /* 4005 */
2050 MIPS_SYS(sys_close , 1)
2051 MIPS_SYS(sys_waitpid , 3)
2052 MIPS_SYS(sys_creat , 2)
2053 MIPS_SYS(sys_link , 2)
2054 MIPS_SYS(sys_unlink , 1) /* 4010 */
2055 MIPS_SYS(sys_execve , 0)
2056 MIPS_SYS(sys_chdir , 1)
2057 MIPS_SYS(sys_time , 1)
2058 MIPS_SYS(sys_mknod , 3)
2059 MIPS_SYS(sys_chmod , 2) /* 4015 */
2060 MIPS_SYS(sys_lchown , 3)
2061 MIPS_SYS(sys_ni_syscall , 0)
2062 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2063 MIPS_SYS(sys_lseek , 3)
2064 MIPS_SYS(sys_getpid , 0) /* 4020 */
2065 MIPS_SYS(sys_mount , 5)
868e34d7 2066 MIPS_SYS(sys_umount , 1)
048f6b4d
FB		 2067 MIPS_SYS(sys_setuid , 1)
2068 MIPS_SYS(sys_getuid , 0)
2069 MIPS_SYS(sys_stime , 1) /* 4025 */
2070 MIPS_SYS(sys_ptrace , 4)
2071 MIPS_SYS(sys_alarm , 1)
2072 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2073 MIPS_SYS(sys_pause , 0)
2074 MIPS_SYS(sys_utime , 2) /* 4030 */
2075 MIPS_SYS(sys_ni_syscall , 0)
2076 MIPS_SYS(sys_ni_syscall , 0)
2077 MIPS_SYS(sys_access , 2)
2078 MIPS_SYS(sys_nice , 1)
2079 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2080 MIPS_SYS(sys_sync , 0)
2081 MIPS_SYS(sys_kill , 2)
2082 MIPS_SYS(sys_rename , 2)
2083 MIPS_SYS(sys_mkdir , 2)
2084 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2085 MIPS_SYS(sys_dup , 1)
2086 MIPS_SYS(sys_pipe , 0)
2087 MIPS_SYS(sys_times , 1)
2088 MIPS_SYS(sys_ni_syscall , 0)
2089 MIPS_SYS(sys_brk , 1) /* 4045 */
2090 MIPS_SYS(sys_setgid , 1)
2091 MIPS_SYS(sys_getgid , 0)
2092 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2093 MIPS_SYS(sys_geteuid , 0)
2094 MIPS_SYS(sys_getegid , 0) /* 4050 */
2095 MIPS_SYS(sys_acct , 0)
868e34d7 2096 MIPS_SYS(sys_umount2 , 2)
048f6b4d
FB		 2097 MIPS_SYS(sys_ni_syscall , 0)
2098 MIPS_SYS(sys_ioctl , 3)
2099 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2100 MIPS_SYS(sys_ni_syscall , 2)
2101 MIPS_SYS(sys_setpgid , 2)
2102 MIPS_SYS(sys_ni_syscall , 0)
2103 MIPS_SYS(sys_olduname , 1)
2104 MIPS_SYS(sys_umask , 1) /* 4060 */
2105 MIPS_SYS(sys_chroot , 1)
2106 MIPS_SYS(sys_ustat , 2)
2107 MIPS_SYS(sys_dup2 , 2)
2108 MIPS_SYS(sys_getppid , 0)
2109 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2110 MIPS_SYS(sys_setsid , 0)
2111 MIPS_SYS(sys_sigaction , 3)
2112 MIPS_SYS(sys_sgetmask , 0)
2113 MIPS_SYS(sys_ssetmask , 1)
2114 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2115 MIPS_SYS(sys_setregid , 2)
2116 MIPS_SYS(sys_sigsuspend , 0)
2117 MIPS_SYS(sys_sigpending , 1)
2118 MIPS_SYS(sys_sethostname , 2)
2119 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2120 MIPS_SYS(sys_getrlimit , 2)
2121 MIPS_SYS(sys_getrusage , 2)
2122 MIPS_SYS(sys_gettimeofday, 2)
2123 MIPS_SYS(sys_settimeofday, 2)
2124 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2125 MIPS_SYS(sys_setgroups , 2)
2126 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2127 MIPS_SYS(sys_symlink , 2)
2128 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2129 MIPS_SYS(sys_readlink , 3) /* 4085 */
2130 MIPS_SYS(sys_uselib , 1)
2131 MIPS_SYS(sys_swapon , 2)
2132 MIPS_SYS(sys_reboot , 3)
2133 MIPS_SYS(old_readdir , 3)
2134 MIPS_SYS(old_mmap , 6) /* 4090 */
2135 MIPS_SYS(sys_munmap , 2)
2136 MIPS_SYS(sys_truncate , 2)
2137 MIPS_SYS(sys_ftruncate , 2)
2138 MIPS_SYS(sys_fchmod , 2)
2139 MIPS_SYS(sys_fchown , 3) /* 4095 */
2140 MIPS_SYS(sys_getpriority , 2)
2141 MIPS_SYS(sys_setpriority , 3)
2142 MIPS_SYS(sys_ni_syscall , 0)
2143 MIPS_SYS(sys_statfs , 2)
2144 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2145 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2146 MIPS_SYS(sys_socketcall , 2)
2147 MIPS_SYS(sys_syslog , 3)
2148 MIPS_SYS(sys_setitimer , 3)
2149 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2150 MIPS_SYS(sys_newstat , 2)
2151 MIPS_SYS(sys_newlstat , 2)
2152 MIPS_SYS(sys_newfstat , 2)
2153 MIPS_SYS(sys_uname , 1)
2154 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2155 MIPS_SYS(sys_vhangup , 0)
2156 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2157 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2158 MIPS_SYS(sys_wait4 , 4)
2159 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2160 MIPS_SYS(sys_sysinfo , 1)
2161 MIPS_SYS(sys_ipc , 6)
2162 MIPS_SYS(sys_fsync , 1)
2163 MIPS_SYS(sys_sigreturn , 0)
18113962 2164 MIPS_SYS(sys_clone , 6) /* 4120 */
048f6b4d
FB		 2165 MIPS_SYS(sys_setdomainname, 2)
2166 MIPS_SYS(sys_newuname , 1)
2167 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2168 MIPS_SYS(sys_adjtimex , 1)
2169 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2170 MIPS_SYS(sys_sigprocmask , 3)
2171 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2172 MIPS_SYS(sys_init_module , 5)
2173 MIPS_SYS(sys_delete_module, 1)
2174 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2175 MIPS_SYS(sys_quotactl , 0)
2176 MIPS_SYS(sys_getpgid , 1)
2177 MIPS_SYS(sys_fchdir , 1)
2178 MIPS_SYS(sys_bdflush , 2)
2179 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2180 MIPS_SYS(sys_personality , 1)
2181 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2182 MIPS_SYS(sys_setfsuid , 1)
2183 MIPS_SYS(sys_setfsgid , 1)
2184 MIPS_SYS(sys_llseek , 5) /* 4140 */
2185 MIPS_SYS(sys_getdents , 3)
2186 MIPS_SYS(sys_select , 5)
2187 MIPS_SYS(sys_flock , 2)
2188 MIPS_SYS(sys_msync , 3)
2189 MIPS_SYS(sys_readv , 3) /* 4145 */
2190 MIPS_SYS(sys_writev , 3)
2191 MIPS_SYS(sys_cacheflush , 3)
2192 MIPS_SYS(sys_cachectl , 3)
2193 MIPS_SYS(sys_sysmips , 4)
2194 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2195 MIPS_SYS(sys_getsid , 1)
2196 MIPS_SYS(sys_fdatasync , 0)
2197 MIPS_SYS(sys_sysctl , 1)
2198 MIPS_SYS(sys_mlock , 2)
2199 MIPS_SYS(sys_munlock , 2) /* 4155 */
2200 MIPS_SYS(sys_mlockall , 1)
2201 MIPS_SYS(sys_munlockall , 0)
2202 MIPS_SYS(sys_sched_setparam, 2)
2203 MIPS_SYS(sys_sched_getparam, 2)
2204 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2205 MIPS_SYS(sys_sched_getscheduler, 1)
2206 MIPS_SYS(sys_sched_yield , 0)
2207 MIPS_SYS(sys_sched_get_priority_max, 1)
2208 MIPS_SYS(sys_sched_get_priority_min, 1)
2209 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2210 MIPS_SYS(sys_nanosleep, 2)
b0932e06 2211 MIPS_SYS(sys_mremap , 5)
048f6b4d
FB		 2212 MIPS_SYS(sys_accept , 3)
2213 MIPS_SYS(sys_bind , 3)
2214 MIPS_SYS(sys_connect , 3) /* 4170 */
2215 MIPS_SYS(sys_getpeername , 3)
2216 MIPS_SYS(sys_getsockname , 3)
2217 MIPS_SYS(sys_getsockopt , 5)
2218 MIPS_SYS(sys_listen , 2)
2219 MIPS_SYS(sys_recv , 4) /* 4175 */
2220 MIPS_SYS(sys_recvfrom , 6)
2221 MIPS_SYS(sys_recvmsg , 3)
2222 MIPS_SYS(sys_send , 4)
2223 MIPS_SYS(sys_sendmsg , 3)
2224 MIPS_SYS(sys_sendto , 6) /* 4180 */
2225 MIPS_SYS(sys_setsockopt , 5)
2226 MIPS_SYS(sys_shutdown , 2)
2227 MIPS_SYS(sys_socket , 3)
2228 MIPS_SYS(sys_socketpair , 4)
2229 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2230 MIPS_SYS(sys_getresuid , 3)
2231 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2232 MIPS_SYS(sys_poll , 3)
2233 MIPS_SYS(sys_nfsservctl , 3)
2234 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2235 MIPS_SYS(sys_getresgid , 3)
2236 MIPS_SYS(sys_prctl , 5)
2237 MIPS_SYS(sys_rt_sigreturn, 0)
2238 MIPS_SYS(sys_rt_sigaction, 4)
2239 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2240 MIPS_SYS(sys_rt_sigpending, 2)
2241 MIPS_SYS(sys_rt_sigtimedwait, 4)
2242 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2243 MIPS_SYS(sys_rt_sigsuspend, 0)
2244 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2245 MIPS_SYS(sys_pwrite64 , 6)
2246 MIPS_SYS(sys_chown , 3)
2247 MIPS_SYS(sys_getcwd , 2)
2248 MIPS_SYS(sys_capget , 2)
2249 MIPS_SYS(sys_capset , 2) /* 4205 */
053ebb27 2250 MIPS_SYS(sys_sigaltstack , 2)
048f6b4d
FB		 2251 MIPS_SYS(sys_sendfile , 4)
2252 MIPS_SYS(sys_ni_syscall , 0)
2253 MIPS_SYS(sys_ni_syscall , 0)
2254 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2255 MIPS_SYS(sys_truncate64 , 4)
2256 MIPS_SYS(sys_ftruncate64 , 4)
2257 MIPS_SYS(sys_stat64 , 2)
2258 MIPS_SYS(sys_lstat64 , 2)
2259 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2260 MIPS_SYS(sys_pivot_root , 2)
2261 MIPS_SYS(sys_mincore , 3)
2262 MIPS_SYS(sys_madvise , 3)
2263 MIPS_SYS(sys_getdents64 , 3)
2264 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2265 MIPS_SYS(sys_ni_syscall , 0)
2266 MIPS_SYS(sys_gettid , 0)
2267 MIPS_SYS(sys_readahead , 5)
2268 MIPS_SYS(sys_setxattr , 5)
2269 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2270 MIPS_SYS(sys_fsetxattr , 5)
2271 MIPS_SYS(sys_getxattr , 4)
2272 MIPS_SYS(sys_lgetxattr , 4)
2273 MIPS_SYS(sys_fgetxattr , 4)
2274 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2275 MIPS_SYS(sys_llistxattr , 3)
2276 MIPS_SYS(sys_flistxattr , 3)
2277 MIPS_SYS(sys_removexattr , 2)
2278 MIPS_SYS(sys_lremovexattr, 2)
2279 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2280 MIPS_SYS(sys_tkill , 2)
2281 MIPS_SYS(sys_sendfile64 , 5)
43be1343 2282 MIPS_SYS(sys_futex , 6)
048f6b4d
FB		 2283 MIPS_SYS(sys_sched_setaffinity, 3)
2284 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2285 MIPS_SYS(sys_io_setup , 2)
2286 MIPS_SYS(sys_io_destroy , 1)
2287 MIPS_SYS(sys_io_getevents, 5)
2288 MIPS_SYS(sys_io_submit , 3)
2289 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2290 MIPS_SYS(sys_exit_group , 1)
2291 MIPS_SYS(sys_lookup_dcookie, 3)
2292 MIPS_SYS(sys_epoll_create, 1)
2293 MIPS_SYS(sys_epoll_ctl , 4)
2294 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2295 MIPS_SYS(sys_remap_file_pages, 5)
2296 MIPS_SYS(sys_set_tid_address, 1)
2297 MIPS_SYS(sys_restart_syscall, 0)
2298 MIPS_SYS(sys_fadvise64_64, 7)
2299 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2300 MIPS_SYS(sys_fstatfs64 , 2)
2301 MIPS_SYS(sys_timer_create, 3)
2302 MIPS_SYS(sys_timer_settime, 4)
2303 MIPS_SYS(sys_timer_gettime, 2)
2304 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2305 MIPS_SYS(sys_timer_delete, 1)
2306 MIPS_SYS(sys_clock_settime, 2)
2307 MIPS_SYS(sys_clock_gettime, 2)
2308 MIPS_SYS(sys_clock_getres, 2)
2309 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2310 MIPS_SYS(sys_tgkill , 3)
2311 MIPS_SYS(sys_utimes , 2)
2312 MIPS_SYS(sys_mbind , 4)
2313 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2314 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2315 MIPS_SYS(sys_mq_open , 4)
2316 MIPS_SYS(sys_mq_unlink , 1)
2317 MIPS_SYS(sys_mq_timedsend, 5)
2318 MIPS_SYS(sys_mq_timedreceive, 5)
2319 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2320 MIPS_SYS(sys_mq_getsetattr, 3)
2321 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2322 MIPS_SYS(sys_waitid , 4)
2323 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2324 MIPS_SYS(sys_add_key , 5)
388bb21a 2325 MIPS_SYS(sys_request_key, 4)
048f6b4d 2326 MIPS_SYS(sys_keyctl , 5)
6f5b89a0 2327 MIPS_SYS(sys_set_thread_area, 1)
388bb21a
TS		 2328 MIPS_SYS(sys_inotify_init, 0)
2329 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2330 MIPS_SYS(sys_inotify_rm_watch, 2)
2331 MIPS_SYS(sys_migrate_pages, 4)
2332 MIPS_SYS(sys_openat, 4)
2333 MIPS_SYS(sys_mkdirat, 3)
2334 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2335 MIPS_SYS(sys_fchownat, 5)
2336 MIPS_SYS(sys_futimesat, 3)
2337 MIPS_SYS(sys_fstatat64, 4)
2338 MIPS_SYS(sys_unlinkat, 3)
2339 MIPS_SYS(sys_renameat, 4) /* 4295 */
2340 MIPS_SYS(sys_linkat, 5)
2341 MIPS_SYS(sys_symlinkat, 3)
2342 MIPS_SYS(sys_readlinkat, 4)
2343 MIPS_SYS(sys_fchmodat, 3)
2344 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2345 MIPS_SYS(sys_pselect6, 6)
2346 MIPS_SYS(sys_ppoll, 5)
2347 MIPS_SYS(sys_unshare, 1)
b0932e06 2348 MIPS_SYS(sys_splice, 6)
388bb21a
TS		 2349 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2350 MIPS_SYS(sys_tee, 4)
2351 MIPS_SYS(sys_vmsplice, 4)
2352 MIPS_SYS(sys_move_pages, 6)
2353 MIPS_SYS(sys_set_robust_list, 2)
2354 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2355 MIPS_SYS(sys_kexec_load, 4)
2356 MIPS_SYS(sys_getcpu, 3)
2357 MIPS_SYS(sys_epoll_pwait, 6)
2358 MIPS_SYS(sys_ioprio_set, 3)
2359 MIPS_SYS(sys_ioprio_get, 2)
d979e8eb
PM		 2360 MIPS_SYS(sys_utimensat, 4)
2361 MIPS_SYS(sys_signalfd, 3)
2362 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2363 MIPS_SYS(sys_eventfd, 1)
2364 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2365 MIPS_SYS(sys_timerfd_create, 2)
2366 MIPS_SYS(sys_timerfd_gettime, 2)
2367 MIPS_SYS(sys_timerfd_settime, 4)
2368 MIPS_SYS(sys_signalfd4, 4)
2369 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2370 MIPS_SYS(sys_epoll_create1, 1)
2371 MIPS_SYS(sys_dup3, 3)
2372 MIPS_SYS(sys_pipe2, 2)
2373 MIPS_SYS(sys_inotify_init1, 1)
2374 MIPS_SYS(sys_preadv, 6) /* 4330 */
2375 MIPS_SYS(sys_pwritev, 6)
2376 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2377 MIPS_SYS(sys_perf_event_open, 5)
2378 MIPS_SYS(sys_accept4, 4)
2379 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2380 MIPS_SYS(sys_fanotify_init, 2)
2381 MIPS_SYS(sys_fanotify_mark, 6)
2382 MIPS_SYS(sys_prlimit64, 4)
2383 MIPS_SYS(sys_name_to_handle_at, 5)
2384 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2385 MIPS_SYS(sys_clock_adjtime, 2)
2386 MIPS_SYS(sys_syncfs, 1)
048f6b4d 2387};
ff4f7382
RH		 2388# undef MIPS_SYS
2389# endif /* O32 */
048f6b4d 2390
590bc601
PB		 2391static int do_store_exclusive(CPUMIPSState *env)
2392{
2393 target_ulong addr;
2394 target_ulong page_addr;
2395 target_ulong val;
2396 int flags;
2397 int segv = 0;
2398 int reg;
2399 int d;
2400
5499b6ff 2401 addr = env->lladdr;
590bc601
PB		 2402 page_addr = addr & TARGET_PAGE_MASK;
2403 start_exclusive();
2404 mmap_lock();
2405 flags = page_get_flags(page_addr);
2406 if ((flags & PAGE_READ) == 0) {
2407 segv = 1;
2408 } else {
2409 reg = env->llreg & 0x1f;
2410 d = (env->llreg & 0x20) != 0;
2411 if (d) {
2412 segv = get_user_s64(val, addr);
2413 } else {
2414 segv = get_user_s32(val, addr);
2415 }
2416 if (!segv) {
2417 if (val != env->llval) {
2418 env->active_tc.gpr[reg] = 0;
2419 } else {
2420 if (d) {
2421 segv = put_user_u64(env->llnewval, addr);
2422 } else {
2423 segv = put_user_u32(env->llnewval, addr);
2424 }
2425 if (!segv) {
2426 env->active_tc.gpr[reg] = 1;
2427 }
2428 }
2429 }
2430 }
5499b6ff 2431 env->lladdr = -1;
590bc601
PB		 2432 if (!segv) {
2433 env->active_tc.PC += 4;
2434 }
2435 mmap_unlock();
2436 end_exclusive();
2437 return segv;
2438}
2439
54b2f42c
MI		 2440/* Break codes */
2441enum {
2442 BRK_OVERFLOW = 6,
2443 BRK_DIVZERO = 7
2444};
2445
2446static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2447 unsigned int code)
2448{
2449 int ret = -1;
2450
2451 switch (code) {
2452 case BRK_OVERFLOW:
2453 case BRK_DIVZERO:
2454 info->si_signo = TARGET_SIGFPE;
2455 info->si_errno = 0;
2456 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2457 queue_signal(env, info->si_signo, &*info);
2458 ret = 0;
2459 break;
2460 default:
b51910ba
PJ		 2461 info->si_signo = TARGET_SIGTRAP;
2462 info->si_errno = 0;
2463 queue_signal(env, info->si_signo, &*info);
2464 ret = 0;
54b2f42c
MI		 2465 break;
2466 }
2467
2468 return ret;
2469}
2470
048f6b4d
FB		 2471void cpu_loop(CPUMIPSState *env)
2472{
0315c31c 2473 CPUState *cs = CPU(mips_env_get_cpu(env));
c227f099 2474 target_siginfo_t info;
ff4f7382
RH		 2475 int trapnr;
2476 abi_long ret;
2477# ifdef TARGET_ABI_MIPSO32
048f6b4d 2478 unsigned int syscall_num;
ff4f7382 2479# endif
048f6b4d
FB		 2480
2481 for(;;) {
0315c31c 2482 cpu_exec_start(cs);
ea3e9847 2483 trapnr = cpu_mips_exec(cs);
0315c31c 2484 cpu_exec_end(cs);
048f6b4d
FB		 2485 switch(trapnr) {
2486 case EXCP_SYSCALL:
b5dc7732 2487 env->active_tc.PC += 4;
ff4f7382
RH		 2488# ifdef TARGET_ABI_MIPSO32
2489 syscall_num = env->active_tc.gpr[2] - 4000;
388bb21a 2490 if (syscall_num >= sizeof(mips_syscall_args)) {
7c2f6157 2491 ret = -TARGET_ENOSYS;
388bb21a
TS		 2492 } else {
2493 int nb_args;
992f48a0
BS		 2494 abi_ulong sp_reg;
2495 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
388bb21a
TS		 2496
2497 nb_args = mips_syscall_args[syscall_num];
b5dc7732 2498 sp_reg = env->active_tc.gpr[29];
388bb21a
TS		 2499 switch (nb_args) {
2500 /* these arguments are taken from the stack */
94c19610
ACH		 2501 case 8:
2502 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2503 goto done_syscall;
2504 }
2505 case 7:
2506 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2507 goto done_syscall;
2508 }
2509 case 6:
2510 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2511 goto done_syscall;
2512 }
2513 case 5:
2514 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2515 goto done_syscall;
2516 }
388bb21a
TS		 2517 default:
2518 break;
048f6b4d 2519 }
b5dc7732
TS		 2520 ret = do_syscall(env, env->active_tc.gpr[2],
2521 env->active_tc.gpr[4],
2522 env->active_tc.gpr[5],
2523 env->active_tc.gpr[6],
2524 env->active_tc.gpr[7],
5945cfcb 2525 arg5, arg6, arg7, arg8);
388bb21a 2526 }
94c19610 2527done_syscall:
ff4f7382
RH		 2528# else
2529 ret = do_syscall(env, env->active_tc.gpr[2],
2530 env->active_tc.gpr[4], env->active_tc.gpr[5],
2531 env->active_tc.gpr[6], env->active_tc.gpr[7],
2532 env->active_tc.gpr[8], env->active_tc.gpr[9],
2533 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2534# endif /* O32 */
2eb3ae27
TB		 2535 if (ret == -TARGET_ERESTARTSYS) {
2536 env->active_tc.PC -= 4;
2537 break;
2538 }
0b1bcb00
PB		 2539 if (ret == -TARGET_QEMU_ESIGRETURN) {
2540 /* Returning from a successful sigreturn syscall.
2541 Avoid clobbering register state. */
2542 break;
2543 }
ff4f7382 2544 if ((abi_ulong)ret >= (abi_ulong)-1133) {
b5dc7732 2545 env->active_tc.gpr[7] = 1; /* error flag */
388bb21a
TS		 2546 ret = -ret;
2547 } else {
b5dc7732 2548 env->active_tc.gpr[7] = 0; /* error flag */
048f6b4d 2549 }
b5dc7732 2550 env->active_tc.gpr[2] = ret;
048f6b4d 2551 break;
ca7c2b1b
TS		 2552 case EXCP_TLBL:
2553 case EXCP_TLBS:
e6e5bd2d
WT		 2554 case EXCP_AdEL:
2555 case EXCP_AdES:
e4474235
PB		 2556 info.si_signo = TARGET_SIGSEGV;
2557 info.si_errno = 0;
2558 /* XXX: check env->error_code */
2559 info.si_code = TARGET_SEGV_MAPERR;
2560 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2561 queue_signal(env, info.si_signo, &info);
2562 break;
6900e84b 2563 case EXCP_CpU:
048f6b4d 2564 case EXCP_RI:
bc1ad2de
FB		 2565 info.si_signo = TARGET_SIGILL;
2566 info.si_errno = 0;
2567 info.si_code = 0;
624f7979 2568 queue_signal(env, info.si_signo, &info);
048f6b4d 2569 break;
106ec879
FB		 2570 case EXCP_INTERRUPT:
2571 /* just indicate that signals should be handled asap */
2572 break;
d08b2a28
PB		 2573 case EXCP_DEBUG:
2574 {
2575 int sig;
2576
db6b81d4 2577 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d08b2a28
PB		 2578 if (sig)
2579 {
2580 info.si_signo = sig;
2581 info.si_errno = 0;
2582 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2583 queue_signal(env, info.si_signo, &info);
d08b2a28
PB		 2584 }
2585 }
2586 break;
590bc601
PB		 2587 case EXCP_SC:
2588 if (do_store_exclusive(env)) {
2589 info.si_signo = TARGET_SIGSEGV;
2590 info.si_errno = 0;
2591 info.si_code = TARGET_SEGV_MAPERR;
2592 info._sifields._sigfault._addr = env->active_tc.PC;
2593 queue_signal(env, info.si_signo, &info);
2594 }
2595 break;
853c3240
JL		 2596 case EXCP_DSPDIS:
2597 info.si_signo = TARGET_SIGILL;
2598 info.si_errno = 0;
2599 info.si_code = TARGET_ILL_ILLOPC;
2600 queue_signal(env, info.si_signo, &info);
2601 break;
54b2f42c
MI		 2602 /* The code below was inspired by the MIPS Linux kernel trap
2603 * handling code in arch/mips/kernel/traps.c.
2604 */
2605 case EXCP_BREAK:
2606 {
2607 abi_ulong trap_instr;
2608 unsigned int code;
2609
a0333817
KCY		 2610 if (env->hflags & MIPS_HFLAG_M16) {
2611 if (env->insn_flags & ASE_MICROMIPS) {
2612 /* microMIPS mode */
1308c464
KCY		 2613 ret = get_user_u16(trap_instr, env->active_tc.PC);
2614 if (ret != 0) {
2615 goto error;
2616 }
a0333817 2617
1308c464
KCY		 2618 if ((trap_instr >> 10) == 0x11) {
2619 /* 16-bit instruction */
2620 code = trap_instr & 0xf;
2621 } else {
2622 /* 32-bit instruction */
2623 abi_ulong instr_lo;
2624
2625 ret = get_user_u16(instr_lo,
2626 env->active_tc.PC + 2);
2627 if (ret != 0) {
2628 goto error;
2629 }
2630 trap_instr = (trap_instr << 16) | instr_lo;
2631 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2632 /* Unfortunately, microMIPS also suffers from
2633 the old assembler bug... */
2634 if (code >= (1 << 10)) {
2635 code >>= 10;
2636 }
2637 }
a0333817
KCY		 2638 } else {
2639 /* MIPS16e mode */
2640 ret = get_user_u16(trap_instr, env->active_tc.PC);
2641 if (ret != 0) {
2642 goto error;
2643 }
2644 code = (trap_instr >> 6) & 0x3f;
a0333817
KCY		 2645 }
2646 } else {
f01a361b 2647 ret = get_user_u32(trap_instr, env->active_tc.PC);
1308c464
KCY		 2648 if (ret != 0) {
2649 goto error;
2650 }
54b2f42c 2651
1308c464
KCY		 2652 /* As described in the original Linux kernel code, the
2653 * below checks on 'code' are to work around an old
2654 * assembly bug.
2655 */
2656 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2657 if (code >= (1 << 10)) {
2658 code >>= 10;
2659 }
54b2f42c
MI		 2660 }
2661
2662 if (do_break(env, &info, code) != 0) {
2663 goto error;
2664 }
2665 }
2666 break;
2667 case EXCP_TRAP:
2668 {
2669 abi_ulong trap_instr;
2670 unsigned int code = 0;
2671
a0333817
KCY		 2672 if (env->hflags & MIPS_HFLAG_M16) {
2673 /* microMIPS mode */
2674 abi_ulong instr[2];
2675
2676 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2677 get_user_u16(instr[1], env->active_tc.PC + 2);
2678
2679 trap_instr = (instr[0] << 16) | instr[1];
2680 } else {
f01a361b 2681 ret = get_user_u32(trap_instr, env->active_tc.PC);
a0333817
KCY		 2682 }
2683
54b2f42c
MI		 2684 if (ret != 0) {
2685 goto error;
2686 }
2687
2688 /* The immediate versions don't provide a code. */
2689 if (!(trap_instr & 0xFC000000)) {
a0333817
KCY		 2690 if (env->hflags & MIPS_HFLAG_M16) {
2691 /* microMIPS mode */
2692 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2693 } else {
2694 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2695 }
54b2f42c
MI		 2696 }
2697
2698 if (do_break(env, &info, code) != 0) {
2699 goto error;
2700 }
2701 }
2702 break;
048f6b4d 2703 default:
54b2f42c 2704error:
120a9848 2705 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
048f6b4d
FB		 2706 abort();
2707 }
2708 process_pending_signals(env);
2709 }
2710}
2711#endif
2712
d962783e
JL		 2713#ifdef TARGET_OPENRISC
2714
2715void cpu_loop(CPUOpenRISCState *env)
2716{
878096ee 2717 CPUState *cs = CPU(openrisc_env_get_cpu(env));
d962783e
JL		 2718 int trapnr, gdbsig;
2719
2720 for (;;) {
b040bc9c 2721 cpu_exec_start(cs);
ea3e9847 2722 trapnr = cpu_openrisc_exec(cs);
b040bc9c 2723 cpu_exec_end(cs);
d962783e
JL		 2724 gdbsig = 0;
2725
2726 switch (trapnr) {
2727 case EXCP_RESET:
120a9848 2728 qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc);
4d1275c2 2729 exit(EXIT_FAILURE);
d962783e
JL		 2730 break;
2731 case EXCP_BUSERR:
120a9848 2732 qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc);
a86b3c64 2733 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2734 break;
2735 case EXCP_DPF:
2736 case EXCP_IPF:
878096ee 2737 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2738 gdbsig = TARGET_SIGSEGV;
2739 break;
2740 case EXCP_TICK:
120a9848 2741 qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc);
d962783e
JL		 2742 break;
2743 case EXCP_ALIGN:
120a9848 2744 qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc);
a86b3c64 2745 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2746 break;
2747 case EXCP_ILLEGAL:
120a9848 2748 qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc);
a86b3c64 2749 gdbsig = TARGET_SIGILL;
d962783e
JL		 2750 break;
2751 case EXCP_INT:
120a9848 2752 qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc);
d962783e
JL		 2753 break;
2754 case EXCP_DTLBMISS:
2755 case EXCP_ITLBMISS:
120a9848 2756 qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n");
d962783e
JL		 2757 break;
2758 case EXCP_RANGE:
120a9848 2759 qemu_log_mask(CPU_LOG_INT, "\nRange\n");
a86b3c64 2760 gdbsig = TARGET_SIGSEGV;
d962783e
JL		 2761 break;
2762 case EXCP_SYSCALL:
2763 env->pc += 4; /* 0xc00; */
2764 env->gpr[11] = do_syscall(env,
2765 env->gpr[11], /* return value */
2766 env->gpr[3], /* r3 - r7 are params */
2767 env->gpr[4],
2768 env->gpr[5],
2769 env->gpr[6],
2770 env->gpr[7],
2771 env->gpr[8], 0, 0);
2772 break;
2773 case EXCP_FPE:
120a9848 2774 qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n");
d962783e
JL		 2775 break;
2776 case EXCP_TRAP:
120a9848 2777 qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
a86b3c64 2778 gdbsig = TARGET_SIGTRAP;
d962783e
JL		 2779 break;
2780 case EXCP_NR:
120a9848 2781 qemu_log_mask(CPU_LOG_INT, "\nNR\n");
d962783e
JL		 2782 break;
2783 default:
120a9848 2784 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
d962783e 2785 trapnr);
d962783e
JL		 2786 gdbsig = TARGET_SIGILL;
2787 break;
2788 }
2789 if (gdbsig) {
db6b81d4 2790 gdb_handlesig(cs, gdbsig);
d962783e 2791 if (gdbsig != TARGET_SIGTRAP) {
4d1275c2 2792 exit(EXIT_FAILURE);
d962783e
JL		 2793 }
2794 }
2795
2796 process_pending_signals(env);
2797 }
2798}
2799
2800#endif /* TARGET_OPENRISC */
2801
fdf9b3e8 2802#ifdef TARGET_SH4
05390248 2803void cpu_loop(CPUSH4State *env)
fdf9b3e8 2804{
878096ee 2805 CPUState *cs = CPU(sh_env_get_cpu(env));
fdf9b3e8 2806 int trapnr, ret;
c227f099 2807 target_siginfo_t info;
3b46e624 2808
fdf9b3e8 2809 while (1) {
b040bc9c 2810 cpu_exec_start(cs);
ea3e9847 2811 trapnr = cpu_sh4_exec(cs);
b040bc9c 2812 cpu_exec_end(cs);
3b46e624 2813
fdf9b3e8
FB		 2814 switch (trapnr) {
2815 case 0x160:
0b6d3ae0 2816 env->pc += 2;
5fafdf24
TS		 2817 ret = do_syscall(env,
2818 env->gregs[3],
2819 env->gregs[4],
2820 env->gregs[5],
2821 env->gregs[6],
2822 env->gregs[7],
2823 env->gregs[0],
5945cfcb
PM		 2824 env->gregs[1],
2825 0, 0);
9c2a9ea1 2826 env->gregs[0] = ret;
fdf9b3e8 2827 break;
c3b5bc8a
TS		 2828 case EXCP_INTERRUPT:
2829 /* just indicate that signals should be handled asap */
2830 break;
355fb23d
PB		 2831 case EXCP_DEBUG:
2832 {
2833 int sig;
2834
db6b81d4 2835 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
355fb23d
PB		 2836 if (sig)
2837 {
2838 info.si_signo = sig;
2839 info.si_errno = 0;
2840 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2841 queue_signal(env, info.si_signo, &info);
355fb23d
PB		 2842 }
2843 }
2844 break;
c3b5bc8a
TS		 2845 case 0xa0:
2846 case 0xc0:
a86b3c64 2847 info.si_signo = TARGET_SIGSEGV;
c3b5bc8a
TS		 2848 info.si_errno = 0;
2849 info.si_code = TARGET_SEGV_MAPERR;
2850 info._sifields._sigfault._addr = env->tea;
624f7979 2851 queue_signal(env, info.si_signo, &info);
c3b5bc8a
TS		 2852 break;
2853
fdf9b3e8
FB		 2854 default:
2855 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2856 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 2857 exit(EXIT_FAILURE);
fdf9b3e8
FB		 2858 }
2859 process_pending_signals (env);
2860 }
2861}
2862#endif
2863
48733d19 2864#ifdef TARGET_CRIS
05390248 2865void cpu_loop(CPUCRISState *env)
48733d19 2866{
878096ee 2867 CPUState *cs = CPU(cris_env_get_cpu(env));
48733d19 2868 int trapnr, ret;
c227f099 2869 target_siginfo_t info;
48733d19
TS		 2870
2871 while (1) {
b040bc9c 2872 cpu_exec_start(cs);
ea3e9847 2873 trapnr = cpu_cris_exec(cs);
b040bc9c 2874 cpu_exec_end(cs);
48733d19
TS		 2875 switch (trapnr) {
2876 case 0xaa:
2877 {
a86b3c64 2878 info.si_signo = TARGET_SIGSEGV;
48733d19
TS		 2879 info.si_errno = 0;
2880 /* XXX: check env->error_code */
2881 info.si_code = TARGET_SEGV_MAPERR;
e00c1e71 2882 info._sifields._sigfault._addr = env->pregs[PR_EDA];
624f7979 2883 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2884 }
2885 break;
b6d3abda
EI		 2886 case EXCP_INTERRUPT:
2887 /* just indicate that signals should be handled asap */
2888 break;
48733d19
TS		 2889 case EXCP_BREAK:
2890 ret = do_syscall(env,
2891 env->regs[9],
2892 env->regs[10],
2893 env->regs[11],
2894 env->regs[12],
2895 env->regs[13],
2896 env->pregs[7],
5945cfcb
PM		 2897 env->pregs[11],
2898 0, 0);
48733d19 2899 env->regs[10] = ret;
48733d19
TS		 2900 break;
2901 case EXCP_DEBUG:
2902 {
2903 int sig;
2904
db6b81d4 2905 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
48733d19
TS		 2906 if (sig)
2907 {
2908 info.si_signo = sig;
2909 info.si_errno = 0;
2910 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2911 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2912 }
2913 }
2914 break;
2915 default:
2916 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2917 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 2918 exit(EXIT_FAILURE);
48733d19
TS		 2919 }
2920 process_pending_signals (env);
2921 }
2922}
2923#endif
2924
b779e29e 2925#ifdef TARGET_MICROBLAZE
05390248 2926void cpu_loop(CPUMBState *env)
b779e29e 2927{
878096ee 2928 CPUState *cs = CPU(mb_env_get_cpu(env));
b779e29e 2929 int trapnr, ret;
c227f099 2930 target_siginfo_t info;
b779e29e
EI		 2931
2932 while (1) {
b040bc9c 2933 cpu_exec_start(cs);
ea3e9847 2934 trapnr = cpu_mb_exec(cs);
b040bc9c 2935 cpu_exec_end(cs);
b779e29e
EI		 2936 switch (trapnr) {
2937 case 0xaa:
2938 {
a86b3c64 2939 info.si_signo = TARGET_SIGSEGV;
b779e29e
EI		 2940 info.si_errno = 0;
2941 /* XXX: check env->error_code */
2942 info.si_code = TARGET_SEGV_MAPERR;
2943 info._sifields._sigfault._addr = 0;
2944 queue_signal(env, info.si_signo, &info);
2945 }
2946 break;
2947 case EXCP_INTERRUPT:
2948 /* just indicate that signals should be handled asap */
2949 break;
2950 case EXCP_BREAK:
2951 /* Return address is 4 bytes after the call. */
2952 env->regs[14] += 4;
d7dce494 2953 env->sregs[SR_PC] = env->regs[14];
b779e29e
EI		 2954 ret = do_syscall(env,
2955 env->regs[12],
2956 env->regs[5],
2957 env->regs[6],
2958 env->regs[7],
2959 env->regs[8],
2960 env->regs[9],
5945cfcb
PM		 2961 env->regs[10],
2962 0, 0);
b779e29e 2963 env->regs[3] = ret;
b779e29e 2964 break;
b76da7e3
EI		 2965 case EXCP_HW_EXCP:
2966 env->regs[17] = env->sregs[SR_PC] + 4;
2967 if (env->iflags & D_FLAG) {
2968 env->sregs[SR_ESR] |= 1 << 12;
2969 env->sregs[SR_PC] -= 4;
b4916d7b 2970 /* FIXME: if branch was immed, replay the imm as well. */
b76da7e3
EI		 2971 }
2972
2973 env->iflags &= ~(IMM_FLAG | D_FLAG);
2974
2975 switch (env->sregs[SR_ESR] & 31) {
22a78d64 2976 case ESR_EC_DIVZERO:
a86b3c64 2977 info.si_signo = TARGET_SIGFPE;
22a78d64
EI		 2978 info.si_errno = 0;
2979 info.si_code = TARGET_FPE_FLTDIV;
2980 info._sifields._sigfault._addr = 0;
2981 queue_signal(env, info.si_signo, &info);
2982 break;
b76da7e3 2983 case ESR_EC_FPU:
a86b3c64 2984 info.si_signo = TARGET_SIGFPE;
b76da7e3
EI		 2985 info.si_errno = 0;
2986 if (env->sregs[SR_FSR] & FSR_IO) {
2987 info.si_code = TARGET_FPE_FLTINV;
2988 }
2989 if (env->sregs[SR_FSR] & FSR_DZ) {
2990 info.si_code = TARGET_FPE_FLTDIV;
2991 }
2992 info._sifields._sigfault._addr = 0;
2993 queue_signal(env, info.si_signo, &info);
2994 break;
2995 default:
2996 printf ("Unhandled hw-exception: 0x%x\n",
2e42d52d 2997 env->sregs[SR_ESR] & ESR_EC_MASK);
878096ee 2998 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 2999 exit(EXIT_FAILURE);
b76da7e3
EI		 3000 break;
3001 }
3002 break;
b779e29e
EI		 3003 case EXCP_DEBUG:
3004 {
3005 int sig;
3006
db6b81d4 3007 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
b779e29e
EI		 3008 if (sig)
3009 {
3010 info.si_signo = sig;
3011 info.si_errno = 0;
3012 info.si_code = TARGET_TRAP_BRKPT;
3013 queue_signal(env, info.si_signo, &info);
3014 }
3015 }
3016 break;
3017 default:
3018 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3019 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3020 exit(EXIT_FAILURE);
b779e29e
EI		 3021 }
3022 process_pending_signals (env);
3023 }
3024}
3025#endif
3026
e6e5906b
PB		 3027#ifdef TARGET_M68K
3028
3029void cpu_loop(CPUM68KState *env)
3030{
878096ee 3031 CPUState *cs = CPU(m68k_env_get_cpu(env));
e6e5906b
PB		 3032 int trapnr;
3033 unsigned int n;
c227f099 3034 target_siginfo_t info;
0429a971 3035 TaskState *ts = cs->opaque;
3b46e624 3036
e6e5906b 3037 for(;;) {
b040bc9c 3038 cpu_exec_start(cs);
ea3e9847 3039 trapnr = cpu_m68k_exec(cs);
b040bc9c 3040 cpu_exec_end(cs);
e6e5906b
PB		 3041 switch(trapnr) {
3042 case EXCP_ILLEGAL:
3043 {
3044 if (ts->sim_syscalls) {
3045 uint16_t nr;
d8d5119c 3046 get_user_u16(nr, env->pc + 2);
e6e5906b
PB		 3047 env->pc += 4;
3048 do_m68k_simcall(env, nr);
3049 } else {
3050 goto do_sigill;
3051 }
3052 }
3053 break;
a87295e8 3054 case EXCP_HALT_INSN:
e6e5906b 3055 /* Semihosing syscall. */
a87295e8 3056 env->pc += 4;
e6e5906b
PB		 3057 do_m68k_semihosting(env, env->dregs[0]);
3058 break;
3059 case EXCP_LINEA:
3060 case EXCP_LINEF:
3061 case EXCP_UNSUPPORTED:
3062 do_sigill:
a86b3c64 3063 info.si_signo = TARGET_SIGILL;
e6e5906b
PB		 3064 info.si_errno = 0;
3065 info.si_code = TARGET_ILL_ILLOPN;
3066 info._sifields._sigfault._addr = env->pc;
624f7979 3067 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3068 break;
3069 case EXCP_TRAP0:
3070 {
3071 ts->sim_syscalls = 0;
3072 n = env->dregs[0];
3073 env->pc += 2;
5fafdf24
TS		 3074 env->dregs[0] = do_syscall(env,
3075 n,
e6e5906b
PB		 3076 env->dregs[1],
3077 env->dregs[2],
3078 env->dregs[3],
3079 env->dregs[4],
3080 env->dregs[5],
5945cfcb
PM		 3081 env->aregs[0],
3082 0, 0);
e6e5906b
PB		 3083 }
3084 break;
3085 case EXCP_INTERRUPT:
3086 /* just indicate that signals should be handled asap */
3087 break;
3088 case EXCP_ACCESS:
3089 {
a86b3c64 3090 info.si_signo = TARGET_SIGSEGV;
e6e5906b
PB		 3091 info.si_errno = 0;
3092 /* XXX: check env->error_code */
3093 info.si_code = TARGET_SEGV_MAPERR;
3094 info._sifields._sigfault._addr = env->mmu.ar;
624f7979 3095 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3096 }
3097 break;
3098 case EXCP_DEBUG:
3099 {
3100 int sig;
3101
db6b81d4 3102 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
e6e5906b
PB		 3103 if (sig)
3104 {
3105 info.si_signo = sig;
3106 info.si_errno = 0;
3107 info.si_code = TARGET_TRAP_BRKPT;
624f7979 3108 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3109 }
3110 }
3111 break;
3112 default:
120a9848 3113 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
e6e5906b
PB		 3114 abort();
3115 }
3116 process_pending_signals(env);
3117 }
3118}
3119#endif /* TARGET_M68K */
3120
7a3148a9 3121#ifdef TARGET_ALPHA
6910b8f6
RH		 3122static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3123{
3124 target_ulong addr, val, tmp;
3125 target_siginfo_t info;
3126 int ret = 0;
3127
3128 addr = env->lock_addr;
3129 tmp = env->lock_st_addr;
3130 env->lock_addr = -1;
3131 env->lock_st_addr = 0;
3132
3133 start_exclusive();
3134 mmap_lock();
3135
3136 if (addr == tmp) {
3137 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3138 goto do_sigsegv;
3139 }
3140
3141 if (val == env->lock_value) {
3142 tmp = env->ir[reg];
3143 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3144 goto do_sigsegv;
3145 }
3146 ret = 1;
3147 }
3148 }
3149 env->ir[reg] = ret;
3150 env->pc += 4;
3151
3152 mmap_unlock();
3153 end_exclusive();
3154 return;
3155
3156 do_sigsegv:
3157 mmap_unlock();
3158 end_exclusive();
3159
3160 info.si_signo = TARGET_SIGSEGV;
3161 info.si_errno = 0;
3162 info.si_code = TARGET_SEGV_MAPERR;
3163 info._sifields._sigfault._addr = addr;
3164 queue_signal(env, TARGET_SIGSEGV, &info);
3165}
3166
05390248 3167void cpu_loop(CPUAlphaState *env)
7a3148a9 3168{
878096ee 3169 CPUState *cs = CPU(alpha_env_get_cpu(env));
e96efcfc 3170 int trapnr;
c227f099 3171 target_siginfo_t info;
6049f4f8 3172 abi_long sysret;
3b46e624 3173
7a3148a9 3174 while (1) {
b040bc9c 3175 cpu_exec_start(cs);
ea3e9847 3176 trapnr = cpu_alpha_exec(cs);
b040bc9c 3177 cpu_exec_end(cs);
3b46e624 3178
ac316ca4
RH		 3179 /* All of the traps imply a transition through PALcode, which
3180 implies an REI instruction has been executed. Which means
3181 that the intr_flag should be cleared. */
3182 env->intr_flag = 0;
3183
7a3148a9
JM		 3184 switch (trapnr) {
3185 case EXCP_RESET:
3186 fprintf(stderr, "Reset requested. Exit\n");
4d1275c2 3187 exit(EXIT_FAILURE);
7a3148a9
JM		 3188 break;
3189 case EXCP_MCHK:
3190 fprintf(stderr, "Machine check exception. Exit\n");
4d1275c2 3191 exit(EXIT_FAILURE);
7a3148a9 3192 break;
07b6c13b
RH		 3193 case EXCP_SMP_INTERRUPT:
3194 case EXCP_CLK_INTERRUPT:
3195 case EXCP_DEV_INTERRUPT:
5fafdf24 3196 fprintf(stderr, "External interrupt. Exit\n");
4d1275c2 3197 exit(EXIT_FAILURE);
7a3148a9 3198 break;
07b6c13b 3199 case EXCP_MMFAULT:
6910b8f6 3200 env->lock_addr = -1;
6049f4f8
RH		 3201 info.si_signo = TARGET_SIGSEGV;
3202 info.si_errno = 0;
129d8aa5 3203 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
0be1d07c 3204 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
129d8aa5 3205 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3206 queue_signal(env, info.si_signo, &info);
7a3148a9 3207 break;
7a3148a9 3208 case EXCP_UNALIGN:
6910b8f6 3209 env->lock_addr = -1;
6049f4f8
RH		 3210 info.si_signo = TARGET_SIGBUS;
3211 info.si_errno = 0;
3212 info.si_code = TARGET_BUS_ADRALN;
129d8aa5 3213 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3214 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3215 break;
3216 case EXCP_OPCDEC:
6049f4f8 3217 do_sigill:
6910b8f6 3218 env->lock_addr = -1;
6049f4f8
RH		 3219 info.si_signo = TARGET_SIGILL;
3220 info.si_errno = 0;
3221 info.si_code = TARGET_ILL_ILLOPC;
3222 info._sifields._sigfault._addr = env->pc;
3223 queue_signal(env, info.si_signo, &info);
7a3148a9 3224 break;
07b6c13b
RH		 3225 case EXCP_ARITH:
3226 env->lock_addr = -1;
3227 info.si_signo = TARGET_SIGFPE;
3228 info.si_errno = 0;
3229 info.si_code = TARGET_FPE_FLTINV;
3230 info._sifields._sigfault._addr = env->pc;
3231 queue_signal(env, info.si_signo, &info);
3232 break;
7a3148a9 3233 case EXCP_FEN:
6049f4f8 3234 /* No-op. Linux simply re-enables the FPU. */
7a3148a9 3235 break;
07b6c13b 3236 case EXCP_CALL_PAL:
6910b8f6 3237 env->lock_addr = -1;
07b6c13b 3238 switch (env->error_code) {
6049f4f8
RH		 3239 case 0x80:
3240 /* BPT */
3241 info.si_signo = TARGET_SIGTRAP;
3242 info.si_errno = 0;
3243 info.si_code = TARGET_TRAP_BRKPT;
3244 info._sifields._sigfault._addr = env->pc;
3245 queue_signal(env, info.si_signo, &info);
3246 break;
3247 case 0x81:
3248 /* BUGCHK */
3249 info.si_signo = TARGET_SIGTRAP;
3250 info.si_errno = 0;
3251 info.si_code = 0;
3252 info._sifields._sigfault._addr = env->pc;
3253 queue_signal(env, info.si_signo, &info);
3254 break;
3255 case 0x83:
3256 /* CALLSYS */
3257 trapnr = env->ir[IR_V0];
3258 sysret = do_syscall(env, trapnr,
3259 env->ir[IR_A0], env->ir[IR_A1],
3260 env->ir[IR_A2], env->ir[IR_A3],
5945cfcb
PM		 3261 env->ir[IR_A4], env->ir[IR_A5],
3262 0, 0);
a5b3b13b
RH		 3263 if (trapnr == TARGET_NR_sigreturn
3264 || trapnr == TARGET_NR_rt_sigreturn) {
3265 break;
3266 }
3267 /* Syscall writes 0 to V0 to bypass error check, similar
0e141977
RH		 3268 to how this is handled internal to Linux kernel.
3269 (Ab)use trapnr temporarily as boolean indicating error. */
3270 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3271 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3272 env->ir[IR_A3] = trapnr;
6049f4f8
RH		 3273 break;
3274 case 0x86:
3275 /* IMB */
3276 /* ??? We can probably elide the code using page_unprotect
3277 that is checking for self-modifying code. Instead we
3278 could simply call tb_flush here. Until we work out the
3279 changes required to turn off the extra write protection,
3280 this can be a no-op. */
3281 break;
3282 case 0x9E:
3283 /* RDUNIQUE */
3284 /* Handled in the translator for usermode. */
3285 abort();
3286 case 0x9F:
3287 /* WRUNIQUE */
3288 /* Handled in the translator for usermode. */
3289 abort();
3290 case 0xAA:
3291 /* GENTRAP */
3292 info.si_signo = TARGET_SIGFPE;
3293 switch (env->ir[IR_A0]) {
3294 case TARGET_GEN_INTOVF:
3295 info.si_code = TARGET_FPE_INTOVF;
3296 break;
3297 case TARGET_GEN_INTDIV:
3298 info.si_code = TARGET_FPE_INTDIV;
3299 break;
3300 case TARGET_GEN_FLTOVF:
3301 info.si_code = TARGET_FPE_FLTOVF;
3302 break;
3303 case TARGET_GEN_FLTUND:
3304 info.si_code = TARGET_FPE_FLTUND;
3305 break;
3306 case TARGET_GEN_FLTINV:
3307 info.si_code = TARGET_FPE_FLTINV;
3308 break;
3309 case TARGET_GEN_FLTINE:
3310 info.si_code = TARGET_FPE_FLTRES;
3311 break;
3312 case TARGET_GEN_ROPRAND:
3313 info.si_code = 0;
3314 break;
3315 default:
3316 info.si_signo = TARGET_SIGTRAP;
3317 info.si_code = 0;
3318 break;
3319 }
3320 info.si_errno = 0;
3321 info._sifields._sigfault._addr = env->pc;
3322 queue_signal(env, info.si_signo, &info);
3323 break;
3324 default:
3325 goto do_sigill;
3326 }
7a3148a9 3327 break;
7a3148a9 3328 case EXCP_DEBUG:
db6b81d4 3329 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
6049f4f8 3330 if (info.si_signo) {
6910b8f6 3331 env->lock_addr = -1;
6049f4f8
RH		 3332 info.si_errno = 0;
3333 info.si_code = TARGET_TRAP_BRKPT;
3334 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3335 }
3336 break;
6910b8f6
RH		 3337 case EXCP_STL_C:
3338 case EXCP_STQ_C:
3339 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3340 break;
d0f20495
RH		 3341 case EXCP_INTERRUPT:
3342 /* Just indicate that signals should be handled asap. */
3343 break;
7a3148a9
JM		 3344 default:
3345 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3346 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3347 exit(EXIT_FAILURE);
7a3148a9
JM		 3348 }
3349 process_pending_signals (env);
3350 }
3351}
3352#endif /* TARGET_ALPHA */
3353
a4c075f1
UH		 3354#ifdef TARGET_S390X
3355void cpu_loop(CPUS390XState *env)
3356{
878096ee 3357 CPUState *cs = CPU(s390_env_get_cpu(env));
d5a103cd 3358 int trapnr, n, sig;
a4c075f1 3359 target_siginfo_t info;
d5a103cd 3360 target_ulong addr;
a4c075f1
UH		 3361
3362 while (1) {
b040bc9c 3363 cpu_exec_start(cs);
ea3e9847 3364 trapnr = cpu_s390x_exec(cs);
b040bc9c 3365 cpu_exec_end(cs);
a4c075f1
UH		 3366 switch (trapnr) {
3367 case EXCP_INTERRUPT:
d5a103cd 3368 /* Just indicate that signals should be handled asap. */
a4c075f1 3369 break;
a4c075f1 3370
d5a103cd
RH		 3371 case EXCP_SVC:
3372 n = env->int_svc_code;
3373 if (!n) {
3374 /* syscalls > 255 */
3375 n = env->regs[1];
a4c075f1 3376 }
d5a103cd
RH		 3377 env->psw.addr += env->int_svc_ilen;
3378 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3379 env->regs[4], env->regs[5],
3380 env->regs[6], env->regs[7], 0, 0);
a4c075f1 3381 break;
d5a103cd
RH		 3382
3383 case EXCP_DEBUG:
db6b81d4 3384 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d5a103cd
RH		 3385 if (sig) {
3386 n = TARGET_TRAP_BRKPT;
3387 goto do_signal_pc;
a4c075f1
UH		 3388 }
3389 break;
d5a103cd
RH		 3390 case EXCP_PGM:
3391 n = env->int_pgm_code;
3392 switch (n) {
3393 case PGM_OPERATION:
3394 case PGM_PRIVILEGED:
a86b3c64 3395 sig = TARGET_SIGILL;
d5a103cd
RH		 3396 n = TARGET_ILL_ILLOPC;
3397 goto do_signal_pc;
3398 case PGM_PROTECTION:
3399 case PGM_ADDRESSING:
a86b3c64 3400 sig = TARGET_SIGSEGV;
a4c075f1 3401 /* XXX: check env->error_code */
d5a103cd
RH		 3402 n = TARGET_SEGV_MAPERR;
3403 addr = env->__excp_addr;
3404 goto do_signal;
3405 case PGM_EXECUTE:
3406 case PGM_SPECIFICATION:
3407 case PGM_SPECIAL_OP:
3408 case PGM_OPERAND:
3409 do_sigill_opn:
a86b3c64 3410 sig = TARGET_SIGILL;
d5a103cd
RH		 3411 n = TARGET_ILL_ILLOPN;
3412 goto do_signal_pc;
3413
3414 case PGM_FIXPT_OVERFLOW:
a86b3c64 3415 sig = TARGET_SIGFPE;
d5a103cd
RH		 3416 n = TARGET_FPE_INTOVF;
3417 goto do_signal_pc;
3418 case PGM_FIXPT_DIVIDE:
a86b3c64 3419 sig = TARGET_SIGFPE;
d5a103cd
RH		 3420 n = TARGET_FPE_INTDIV;
3421 goto do_signal_pc;
3422
3423 case PGM_DATA:
3424 n = (env->fpc >> 8) & 0xff;
3425 if (n == 0xff) {
3426 /* compare-and-trap */
3427 goto do_sigill_opn;
3428 } else {
3429 /* An IEEE exception, simulated or otherwise. */
3430 if (n & 0x80) {
3431 n = TARGET_FPE_FLTINV;
3432 } else if (n & 0x40) {
3433 n = TARGET_FPE_FLTDIV;
3434 } else if (n & 0x20) {
3435 n = TARGET_FPE_FLTOVF;
3436 } else if (n & 0x10) {
3437 n = TARGET_FPE_FLTUND;
3438 } else if (n & 0x08) {
3439 n = TARGET_FPE_FLTRES;
3440 } else {
3441 /* ??? Quantum exception; BFP, DFP error. */
3442 goto do_sigill_opn;
3443 }
a86b3c64 3444 sig = TARGET_SIGFPE;
d5a103cd
RH		 3445 goto do_signal_pc;
3446 }
3447
3448 default:
3449 fprintf(stderr, "Unhandled program exception: %#x\n", n);
878096ee 3450 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3451 exit(EXIT_FAILURE);
a4c075f1
UH		 3452 }
3453 break;
d5a103cd
RH		 3454
3455 do_signal_pc:
3456 addr = env->psw.addr;
3457 do_signal:
3458 info.si_signo = sig;
3459 info.si_errno = 0;
3460 info.si_code = n;
3461 info._sifields._sigfault._addr = addr;
3462 queue_signal(env, info.si_signo, &info);
a4c075f1 3463 break;
d5a103cd 3464
a4c075f1 3465 default:
d5a103cd 3466 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
878096ee 3467 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3468 exit(EXIT_FAILURE);
a4c075f1
UH		 3469 }
3470 process_pending_signals (env);
3471 }
3472}
3473
3474#endif /* TARGET_S390X */
3475
b16189b2
CG		 3476#ifdef TARGET_TILEGX
3477
b16189b2
CG		 3478static void gen_sigill_reg(CPUTLGState *env)
3479{
3480 target_siginfo_t info;
3481
3482 info.si_signo = TARGET_SIGILL;
3483 info.si_errno = 0;
3484 info.si_code = TARGET_ILL_PRVREG;
3485 info._sifields._sigfault._addr = env->pc;
3486 queue_signal(env, info.si_signo, &info);
3487}
3488
a0577d2a 3489static void do_signal(CPUTLGState *env, int signo, int sigcode)
dd8070d8
CG		 3490{
3491 target_siginfo_t info;
3492
a0577d2a 3493 info.si_signo = signo;
dd8070d8 3494 info.si_errno = 0;
dd8070d8 3495 info._sifields._sigfault._addr = env->pc;
a0577d2a
RH		 3496
3497 if (signo == TARGET_SIGSEGV) {
3498 /* The passed in sigcode is a dummy; check for a page mapping
3499 and pass either MAPERR or ACCERR. */
3500 target_ulong addr = env->excaddr;
3501 info._sifields._sigfault._addr = addr;
3502 if (page_check_range(addr, 1, PAGE_VALID) < 0) {
3503 sigcode = TARGET_SEGV_MAPERR;
3504 } else {
3505 sigcode = TARGET_SEGV_ACCERR;
3506 }
3507 }
3508 info.si_code = sigcode;
3509
dd8070d8
CG		 3510 queue_signal(env, info.si_signo, &info);
3511}
3512
a0577d2a
RH		 3513static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
3514{
3515 env->excaddr = addr;
3516 do_signal(env, TARGET_SIGSEGV, 0);
3517}
3518
0583b233
RH		 3519static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
3520{
3521 if (unlikely(reg >= TILEGX_R_COUNT)) {
3522 switch (reg) {
3523 case TILEGX_R_SN:
3524 case TILEGX_R_ZERO:
3525 return;
3526 case TILEGX_R_IDN0:
3527 case TILEGX_R_IDN1:
3528 case TILEGX_R_UDN0:
3529 case TILEGX_R_UDN1:
3530 case TILEGX_R_UDN2:
3531 case TILEGX_R_UDN3:
3532 gen_sigill_reg(env);
3533 return;
3534 default:
3535 g_assert_not_reached();
3536 }
3537 }
3538 env->regs[reg] = val;
3539}
3540
3541/*
3542 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
3543 * memory at the address held in the first source register. If the values are
3544 * not equal, then no memory operation is performed. If the values are equal,
3545 * the 8-byte quantity from the second source register is written into memory
3546 * at the address held in the first source register. In either case, the result
3547 * of the instruction is the value read from memory. The compare and write to
3548 * memory are atomic and thus can be used for synchronization purposes. This
3549 * instruction only operates for addresses aligned to a 8-byte boundary.
3550 * Unaligned memory access causes an Unaligned Data Reference interrupt.
3551 *
3552 * Functional Description (64-bit)
3553 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
3554 * rf[Dest] = memVal;
3555 * if (memVal == SPR[CmpValueSPR])
3556 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
3557 *
3558 * Functional Description (32-bit)
3559 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
3560 * rf[Dest] = memVal;
3561 * if (memVal == signExtend32 (SPR[CmpValueSPR]))
3562 * memoryWriteWord (rf[SrcA], rf[SrcB]);
3563 *
3564 *
3565 * This function also processes exch and exch4 which need not process SPR.
3566 */
3567static void do_exch(CPUTLGState *env, bool quad, bool cmp)
3568{
3569 target_ulong addr;
3570 target_long val, sprval;
3571
3572 start_exclusive();
3573
3574 addr = env->atomic_srca;
3575 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3576 goto sigsegv_maperr;
3577 }
3578
3579 if (cmp) {
3580 if (quad) {
3581 sprval = env->spregs[TILEGX_SPR_CMPEXCH];
3582 } else {
3583 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
3584 }
3585 }
3586
3587 if (!cmp || val == sprval) {
3588 target_long valb = env->atomic_srcb;
3589 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3590 goto sigsegv_maperr;
3591 }
3592 }
3593
3594 set_regval(env, env->atomic_dstr, val);
3595 end_exclusive();
3596 return;
3597
3598 sigsegv_maperr:
3599 end_exclusive();
3600 gen_sigsegv_maperr(env, addr);
3601}
3602
3603static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
3604{
3605 int8_t write = 1;
3606 target_ulong addr;
3607 target_long val, valb;
3608
3609 start_exclusive();
3610
3611 addr = env->atomic_srca;
3612 valb = env->atomic_srcb;
3613 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3614 goto sigsegv_maperr;
3615 }
3616
3617 switch (trapnr) {
3618 case TILEGX_EXCP_OPCODE_FETCHADD:
3619 case TILEGX_EXCP_OPCODE_FETCHADD4:
3620 valb += val;
3621 break;
3622 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3623 valb += val;
3624 if (valb < 0) {
3625 write = 0;
3626 }
3627 break;
3628 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3629 valb += val;
3630 if ((int32_t)valb < 0) {
3631 write = 0;
3632 }
3633 break;
3634 case TILEGX_EXCP_OPCODE_FETCHAND:
3635 case TILEGX_EXCP_OPCODE_FETCHAND4:
3636 valb &= val;
3637 break;
3638 case TILEGX_EXCP_OPCODE_FETCHOR:
3639 case TILEGX_EXCP_OPCODE_FETCHOR4:
3640 valb |= val;
3641 break;
3642 default:
3643 g_assert_not_reached();
3644 }
3645
3646 if (write) {
3647 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3648 goto sigsegv_maperr;
3649 }
3650 }
3651
3652 set_regval(env, env->atomic_dstr, val);
3653 end_exclusive();
3654 return;
3655
3656 sigsegv_maperr:
3657 end_exclusive();
3658 gen_sigsegv_maperr(env, addr);
3659}
3660
b16189b2
CG		 3661void cpu_loop(CPUTLGState *env)
3662{
3663 CPUState *cs = CPU(tilegx_env_get_cpu(env));
3664 int trapnr;
3665
3666 while (1) {
3667 cpu_exec_start(cs);
3668 trapnr = cpu_tilegx_exec(cs);
3669 cpu_exec_end(cs);
3670 switch (trapnr) {
3671 case TILEGX_EXCP_SYSCALL:
3672 env->regs[TILEGX_R_RE] = do_syscall(env, env->regs[TILEGX_R_NR],
3673 env->regs[0], env->regs[1],
3674 env->regs[2], env->regs[3],
3675 env->regs[4], env->regs[5],
3676 env->regs[6], env->regs[7]);
3677 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(env->regs[TILEGX_R_RE])
3678 ? - env->regs[TILEGX_R_RE]
3679 : 0;
3680 break;
0583b233
RH		 3681 case TILEGX_EXCP_OPCODE_EXCH:
3682 do_exch(env, true, false);
3683 break;
3684 case TILEGX_EXCP_OPCODE_EXCH4:
3685 do_exch(env, false, false);
3686 break;
3687 case TILEGX_EXCP_OPCODE_CMPEXCH:
3688 do_exch(env, true, true);
3689 break;
3690 case TILEGX_EXCP_OPCODE_CMPEXCH4:
3691 do_exch(env, false, true);
3692 break;
3693 case TILEGX_EXCP_OPCODE_FETCHADD:
3694 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3695 case TILEGX_EXCP_OPCODE_FETCHAND:
3696 case TILEGX_EXCP_OPCODE_FETCHOR:
3697 do_fetch(env, trapnr, true);
3698 break;
3699 case TILEGX_EXCP_OPCODE_FETCHADD4:
3700 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3701 case TILEGX_EXCP_OPCODE_FETCHAND4:
3702 case TILEGX_EXCP_OPCODE_FETCHOR4:
3703 do_fetch(env, trapnr, false);
3704 break;
dd8070d8 3705 case TILEGX_EXCP_SIGNAL:
a0577d2a 3706 do_signal(env, env->signo, env->sigcode);
dd8070d8 3707 break;
b16189b2
CG		 3708 case TILEGX_EXCP_REG_IDN_ACCESS:
3709 case TILEGX_EXCP_REG_UDN_ACCESS:
3710 gen_sigill_reg(env);
3711 break;
3712 default:
3713 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
3714 g_assert_not_reached();
3715 }
3716 process_pending_signals(env);
3717 }
3718}
3719
3720#endif
3721
a2247f8e 3722THREAD CPUState *thread_cpu;
59faf6d6 3723
edf8e2af
MW		 3724void task_settid(TaskState *ts)
3725{
3726 if (ts->ts_tid == 0) {
edf8e2af 3727 ts->ts_tid = (pid_t)syscall(SYS_gettid);
edf8e2af
MW		 3728 }
3729}
3730
3731void stop_all_tasks(void)
3732{
3733 /*
3734 * We trust that when using NPTL, start_exclusive()
3735 * handles thread stopping correctly.
3736 */
3737 start_exclusive();
3738}
3739
c3a92833 3740/* Assumes contents are already zeroed. */
624f7979
PB		 3741void init_task_state(TaskState *ts)
3742{
3743 int i;
3744
624f7979
PB		 3745 ts->used = 1;
3746 ts->first_free = ts->sigqueue_table;
3747 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3748 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3749 }
3750 ts->sigqueue_table[i].next = NULL;
3751}
fc9c5412 3752
30ba0ee5
AF		 3753CPUArchState *cpu_copy(CPUArchState *env)
3754{
ff4700b0 3755 CPUState *cpu = ENV_GET_CPU(env);
2994fd96 3756 CPUState *new_cpu = cpu_init(cpu_model);
61c7480f 3757 CPUArchState *new_env = new_cpu->env_ptr;
30ba0ee5
AF		 3758 CPUBreakpoint *bp;
3759 CPUWatchpoint *wp;
30ba0ee5
AF		 3760
3761 /* Reset non arch specific state */
75a34036 3762 cpu_reset(new_cpu);
30ba0ee5
AF		 3763
3764 memcpy(new_env, env, sizeof(CPUArchState));
3765
3766 /* Clone all break/watchpoints.
3767 Note: Once we support ptrace with hw-debug register access, make sure
3768 BP_CPU break/watchpoints are handled correctly on clone. */
1d085f6c
TB		 3769 QTAILQ_INIT(&new_cpu->breakpoints);
3770 QTAILQ_INIT(&new_cpu->watchpoints);
f0c3c505 3771 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
b3310ab3 3772 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
30ba0ee5 3773 }
ff4700b0 3774 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
05068c0d 3775 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
30ba0ee5 3776 }
30ba0ee5
AF		 3777
3778 return new_env;
3779}
3780
fc9c5412
JS		 3781static void handle_arg_help(const char *arg)
3782{
4d1275c2 3783 usage(EXIT_SUCCESS);
fc9c5412
JS		 3784}
3785
3786static void handle_arg_log(const char *arg)
3787{
3788 int mask;
fc9c5412 3789
4fde1eba 3790 mask = qemu_str_to_log_mask(arg);
fc9c5412 3791 if (!mask) {
59a6fa6e 3792 qemu_print_log_usage(stdout);
4d1275c2 3793 exit(EXIT_FAILURE);
fc9c5412 3794 }
f2937a33 3795 qemu_log_needs_buffers();
24537a01 3796 qemu_set_log(mask);
fc9c5412
JS		 3797}
3798
50171d42
CWR		 3799static void handle_arg_log_filename(const char *arg)
3800{
9a7e5424 3801 qemu_set_log_filename(arg);
50171d42
CWR		 3802}
3803
fc9c5412
JS		 3804static void handle_arg_set_env(const char *arg)
3805{
3806 char *r, *p, *token;
3807 r = p = strdup(arg);
3808 while ((token = strsep(&p, ",")) != NULL) {
3809 if (envlist_setenv(envlist, token) != 0) {
4d1275c2 3810 usage(EXIT_FAILURE);
fc9c5412
JS		 3811 }
3812 }
3813 free(r);
3814}
3815
3816static void handle_arg_unset_env(const char *arg)
3817{
3818 char *r, *p, *token;
3819 r = p = strdup(arg);
3820 while ((token = strsep(&p, ",")) != NULL) {
3821 if (envlist_unsetenv(envlist, token) != 0) {
4d1275c2 3822 usage(EXIT_FAILURE);
fc9c5412
JS		 3823 }
3824 }
3825 free(r);
3826}
3827
3828static void handle_arg_argv0(const char *arg)
3829{
3830 argv0 = strdup(arg);
3831}
3832
3833static void handle_arg_stack_size(const char *arg)
3834{
3835 char *p;
3836 guest_stack_size = strtoul(arg, &p, 0);
3837 if (guest_stack_size == 0) {
4d1275c2 3838 usage(EXIT_FAILURE);
fc9c5412
JS		 3839 }
3840
3841 if (*p == 'M') {
3842 guest_stack_size *= 1024 * 1024;
3843 } else if (*p == 'k' || *p == 'K') {
3844 guest_stack_size *= 1024;
3845 }
3846}
3847
3848static void handle_arg_ld_prefix(const char *arg)
3849{
3850 interp_prefix = strdup(arg);
3851}
3852
3853static void handle_arg_pagesize(const char *arg)
3854{
3855 qemu_host_page_size = atoi(arg);
3856 if (qemu_host_page_size == 0 ||
3857 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3858 fprintf(stderr, "page size must be a power of two\n");
4d1275c2 3859 exit(EXIT_FAILURE);
fc9c5412
JS		 3860 }
3861}
3862
c5e4a5a9
MR		 3863static void handle_arg_randseed(const char *arg)
3864{
3865 unsigned long long seed;
3866
3867 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3868 fprintf(stderr, "Invalid seed number: %s\n", arg);
4d1275c2 3869 exit(EXIT_FAILURE);
c5e4a5a9
MR		 3870 }
3871 srand(seed);
3872}
3873
fc9c5412
JS		 3874static void handle_arg_gdb(const char *arg)
3875{
3876 gdbstub_port = atoi(arg);
3877}
3878
3879static void handle_arg_uname(const char *arg)
3880{
3881 qemu_uname_release = strdup(arg);
3882}
3883
3884static void handle_arg_cpu(const char *arg)
3885{
3886 cpu_model = strdup(arg);
c8057f95 3887 if (cpu_model == NULL || is_help_option(cpu_model)) {
fc9c5412 3888 /* XXX: implement xxx_cpu_list for targets that still miss it */
e916cbf8
PM		 3889#if defined(cpu_list)
3890 cpu_list(stdout, &fprintf);
fc9c5412 3891#endif
4d1275c2 3892 exit(EXIT_FAILURE);
fc9c5412
JS		 3893 }
3894}
3895
fc9c5412
JS		 3896static void handle_arg_guest_base(const char *arg)
3897{
3898 guest_base = strtol(arg, NULL, 0);
3899 have_guest_base = 1;
3900}
3901
3902static void handle_arg_reserved_va(const char *arg)
3903{
3904 char *p;
3905 int shift = 0;
3906 reserved_va = strtoul(arg, &p, 0);
3907 switch (*p) {
3908 case 'k':
3909 case 'K':
3910 shift = 10;
3911 break;
3912 case 'M':
3913 shift = 20;
3914 break;
3915 case 'G':
3916 shift = 30;
3917 break;
3918 }
3919 if (shift) {
3920 unsigned long unshifted = reserved_va;
3921 p++;
3922 reserved_va <<= shift;
3923 if (((reserved_va >> shift) != unshifted)
3924#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3925 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3926#endif
3927 ) {
3928 fprintf(stderr, "Reserved virtual address too big\n");
4d1275c2 3929 exit(EXIT_FAILURE);
fc9c5412
JS		 3930 }
3931 }
3932 if (*p) {
3933 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
4d1275c2 3934 exit(EXIT_FAILURE);
fc9c5412
JS		 3935 }
3936}
fc9c5412
JS		 3937
3938static void handle_arg_singlestep(const char *arg)
3939{
3940 singlestep = 1;
3941}
3942
3943static void handle_arg_strace(const char *arg)
3944{
3945 do_strace = 1;
3946}
3947
3948static void handle_arg_version(const char *arg)
3949{
2e59915d 3950 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
fc9c5412 3951 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
4d1275c2 3952 exit(EXIT_SUCCESS);
fc9c5412
JS		 3953}
3954
3955struct qemu_argument {
3956 const char *argv;
3957 const char *env;
3958 bool has_arg;
3959 void (*handle_opt)(const char *arg);
3960 const char *example;
3961 const char *help;
3962};
3963
42644cee 3964static const struct qemu_argument arg_table[] = {
fc9c5412
JS		 3965 {"h", "", false, handle_arg_help,
3966 "", "print this help"},
daaf8c8e
MI		 3967 {"help", "", false, handle_arg_help,
3968 "", ""},
fc9c5412
JS		 3969 {"g", "QEMU_GDB", true, handle_arg_gdb,
3970 "port", "wait gdb connection to 'port'"},
3971 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3972 "path", "set the elf interpreter prefix to 'path'"},
3973 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3974 "size", "set the stack size to 'size' bytes"},
3975 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
c8057f95 3976 "model", "select CPU (-cpu help for list)"},
fc9c5412
JS		 3977 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3978 "var=value", "sets targets environment variable (see below)"},
3979 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3980 "var", "unsets targets environment variable (see below)"},
3981 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3982 "argv0", "forces target process argv[0] to be 'argv0'"},
3983 {"r", "QEMU_UNAME", true, handle_arg_uname,
3984 "uname", "set qemu uname release string to 'uname'"},
fc9c5412
JS		 3985 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3986 "address", "set guest_base address to 'address'"},
3987 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3988 "size", "reserve 'size' bytes for guest virtual address space"},
fc9c5412 3989 {"d", "QEMU_LOG", true, handle_arg_log,
989b697d
PM		 3990 "item[,...]", "enable logging of specified items "
3991 "(use '-d help' for a list of items)"},
50171d42 3992 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
989b697d 3993 "logfile", "write logs to 'logfile' (default stderr)"},
fc9c5412
JS		 3994 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3995 "pagesize", "set the host page size to 'pagesize'"},
3996 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3997 "", "run in singlestep mode"},
3998 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3999 "", "log system calls"},
c5e4a5a9
MR		 4000 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
4001 "", "Seed for pseudo-random number generator"},
fc9c5412 4002 {"version", "QEMU_VERSION", false, handle_arg_version,
1386d4c0 4003 "", "display version information and exit"},
fc9c5412
JS		 4004 {NULL, NULL, false, NULL, NULL, NULL}
4005};
4006
d03f9c32 4007static void usage(int exitcode)
fc9c5412 4008{
42644cee 4009 const struct qemu_argument *arginfo;
fc9c5412
JS		 4010 int maxarglen;
4011 int maxenvlen;
4012
2e59915d
PB		 4013 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
4014 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
fc9c5412
JS		 4015 "\n"
4016 "Options and associated environment variables:\n"
4017 "\n");
4018
63ec54d7
PM		 4019 /* Calculate column widths. We must always have at least enough space
4020 * for the column header.
4021 */
4022 maxarglen = strlen("Argument");
4023 maxenvlen = strlen("Env-variable");
fc9c5412
JS		 4024
4025 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
63ec54d7
PM		 4026 int arglen = strlen(arginfo->argv);
4027 if (arginfo->has_arg) {
4028 arglen += strlen(arginfo->example) + 1;
4029 }
fc9c5412
JS		 4030 if (strlen(arginfo->env) > maxenvlen) {
4031 maxenvlen = strlen(arginfo->env);
4032 }
63ec54d7
PM		 4033 if (arglen > maxarglen) {
4034 maxarglen = arglen;
fc9c5412
JS		 4035 }
4036 }
4037
63ec54d7
PM		 4038 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
4039 maxenvlen, "Env-variable");
fc9c5412
JS		 4040
4041 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4042 if (arginfo->has_arg) {
4043 printf("-%s %-*s %-*s %s\n", arginfo->argv,
63ec54d7
PM		 4044 (int)(maxarglen - strlen(arginfo->argv) - 1),
4045 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
fc9c5412 4046 } else {
63ec54d7 4047 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
fc9c5412
JS		 4048 maxenvlen, arginfo->env,
4049 arginfo->help);
4050 }
4051 }
4052
4053 printf("\n"
4054 "Defaults:\n"
4055 "QEMU_LD_PREFIX = %s\n"
989b697d 4056 "QEMU_STACK_SIZE = %ld byte\n",
fc9c5412 4057 interp_prefix,
989b697d 4058 guest_stack_size);
fc9c5412
JS		 4059
4060 printf("\n"
4061 "You can use -E and -U options or the QEMU_SET_ENV and\n"
4062 "QEMU_UNSET_ENV environment variables to set and unset\n"
4063 "environment variables for the target process.\n"
4064 "It is possible to provide several variables by separating them\n"
4065 "by commas in getsubopt(3) style. Additionally it is possible to\n"
4066 "provide the -E and -U options multiple times.\n"
4067 "The following lines are equivalent:\n"
4068 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
4069 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
4070 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
4071 "Note that if you provide several changes to a single variable\n"
4072 "the last change will stay in effect.\n");
4073
d03f9c32 4074 exit(exitcode);
fc9c5412
JS		 4075}
4076
4077static int parse_args(int argc, char **argv)
4078{
4079 const char *r;
4080 int optind;
42644cee 4081 const struct qemu_argument *arginfo;
fc9c5412
JS		 4082
4083 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4084 if (arginfo->env == NULL) {
4085 continue;
4086 }
4087
4088 r = getenv(arginfo->env);
4089 if (r != NULL) {
4090 arginfo->handle_opt(r);
4091 }
4092 }
4093
4094 optind = 1;
4095 for (;;) {
4096 if (optind >= argc) {
4097 break;
4098 }
4099 r = argv[optind];
4100 if (r[0] != '-') {
4101 break;
4102 }
4103 optind++;
4104 r++;
4105 if (!strcmp(r, "-")) {
4106 break;
4107 }
ba02577c
MI		 4108 /* Treat --foo the same as -foo. */
4109 if (r[0] == '-') {
4110 r++;
4111 }
fc9c5412
JS		 4112
4113 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4114 if (!strcmp(r, arginfo->argv)) {
fc9c5412 4115 if (arginfo->has_arg) {
1386d4c0 4116 if (optind >= argc) {
138940bf
MI		 4117 (void) fprintf(stderr,
4118 "qemu: missing argument for option '%s'\n", r);
4d1275c2 4119 exit(EXIT_FAILURE);
1386d4c0
PM		 4120 }
4121 arginfo->handle_opt(argv[optind]);
fc9c5412 4122 optind++;
1386d4c0
PM		 4123 } else {
4124 arginfo->handle_opt(NULL);
fc9c5412 4125 }
fc9c5412
JS		 4126 break;
4127 }
4128 }
4129
4130 /* no option matched the current argv */
4131 if (arginfo->handle_opt == NULL) {
138940bf 4132 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r);
4d1275c2 4133 exit(EXIT_FAILURE);
fc9c5412
JS		 4134 }
4135 }
4136
4137 if (optind >= argc) {
138940bf 4138 (void) fprintf(stderr, "qemu: no user program specified\n");
4d1275c2 4139 exit(EXIT_FAILURE);
fc9c5412
JS		 4140 }
4141
4142 filename = argv[optind];
4143 exec_path = argv[optind];
4144
4145 return optind;
4146}
4147
902b3d5c 4148int main(int argc, char **argv, char **envp)
31e31b8a 4149{
01ffc75b 4150 struct target_pt_regs regs1, *regs = &regs1;
31e31b8a 4151 struct image_info info1, *info = &info1;
edf8e2af 4152 struct linux_binprm bprm;
48e15fc2 4153 TaskState *ts;
9349b4f9 4154 CPUArchState *env;
db6b81d4 4155 CPUState *cpu;
586314f2 4156 int optind;
04a6dfeb 4157 char **target_environ, **wrk;
7d8cec95
AJ		 4158 char **target_argv;
4159 int target_argc;
7d8cec95 4160 int i;
fd4d81dd 4161 int ret;
03cfd8fa 4162 int execfd;
b12b6a18 4163
ce008c1f
AF		 4164 module_call_init(MODULE_INIT_QOM);
4165
04a6dfeb
AJ		 4166 if ((envlist = envlist_create()) == NULL) {
4167 (void) fprintf(stderr, "Unable to allocate envlist\n");
4d1275c2 4168 exit(EXIT_FAILURE);
04a6dfeb
AJ		 4169 }
4170
4171 /* add current environment into the list */
4172 for (wrk = environ; *wrk != NULL; wrk++) {
4173 (void) envlist_setenv(envlist, *wrk);
4174 }
4175
703e0e89
RH		 4176 /* Read the stack limit from the kernel. If it's "unlimited",
4177 then we can do little else besides use the default. */
4178 {
4179 struct rlimit lim;
4180 if (getrlimit(RLIMIT_STACK, &lim) == 0
81bbe906
TY		 4181 && lim.rlim_cur != RLIM_INFINITY
4182 && lim.rlim_cur == (target_long)lim.rlim_cur) {
703e0e89
RH		 4183 guest_stack_size = lim.rlim_cur;
4184 }
4185 }
4186
b1f9be31 4187 cpu_model = NULL;
b5ec5ce0 4188
c5e4a5a9
MR		 4189 srand(time(NULL));
4190
fc9c5412 4191 optind = parse_args(argc, argv);
586314f2 4192
31e31b8a 4193 /* Zero out regs */
01ffc75b 4194 memset(regs, 0, sizeof(struct target_pt_regs));
31e31b8a
FB		 4195
4196 /* Zero out image_info */
4197 memset(info, 0, sizeof(struct image_info));
4198
edf8e2af
MW		 4199 memset(&bprm, 0, sizeof (bprm));
4200
74cd30b8
FB		 4201 /* Scan interp_prefix dir for replacement files. */
4202 init_paths(interp_prefix);
4203
4a24a758
PM		 4204 init_qemu_uname_release();
4205
46027c07 4206 if (cpu_model == NULL) {
aaed909a 4207#if defined(TARGET_I386)
46027c07
FB		 4208#ifdef TARGET_X86_64
4209 cpu_model = "qemu64";
4210#else
4211 cpu_model = "qemu32";
4212#endif
aaed909a 4213#elif defined(TARGET_ARM)
088ab16c 4214 cpu_model = "any";
d2fbca94
GX		 4215#elif defined(TARGET_UNICORE32)
4216 cpu_model = "any";
aaed909a
FB		 4217#elif defined(TARGET_M68K)
4218 cpu_model = "any";
4219#elif defined(TARGET_SPARC)
4220#ifdef TARGET_SPARC64
4221 cpu_model = "TI UltraSparc II";
4222#else
4223 cpu_model = "Fujitsu MB86904";
46027c07 4224#endif
aaed909a
FB		 4225#elif defined(TARGET_MIPS)
4226#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
74797f40 4227 cpu_model = "5KEf";
aaed909a
FB		 4228#else
4229 cpu_model = "24Kf";
4230#endif
d962783e
JL		 4231#elif defined TARGET_OPENRISC
4232 cpu_model = "or1200";
aaed909a 4233#elif defined(TARGET_PPC)
a74029f6 4234# ifdef TARGET_PPC64
de3f1b98 4235 cpu_model = "POWER8";
a74029f6 4236# else
aaed909a 4237 cpu_model = "750";
a74029f6 4238# endif
91c45a38
RH		 4239#elif defined TARGET_SH4
4240 cpu_model = TYPE_SH7785_CPU;
aaed909a
FB		 4241#else
4242 cpu_model = "any";
4243#endif
4244 }
d5ab9713 4245 tcg_exec_init(0);
83fb7adf
FB		 4246 /* NOTE: we need to init the CPU at this stage to get
4247 qemu_host_page_size */
2994fd96
EH		 4248 cpu = cpu_init(cpu_model);
4249 if (!cpu) {
aaed909a 4250 fprintf(stderr, "Unable to find CPU definition\n");
4d1275c2 4251 exit(EXIT_FAILURE);
aaed909a 4252 }
2994fd96 4253 env = cpu->env_ptr;
0ac46af3 4254 cpu_reset(cpu);
b55a37c9 4255
db6b81d4 4256 thread_cpu = cpu;
3b46e624 4257
b6741956
FB		 4258 if (getenv("QEMU_STRACE")) {
4259 do_strace = 1;
b92c47c1
TS		 4260 }
4261
c5e4a5a9
MR		 4262 if (getenv("QEMU_RAND_SEED")) {
4263 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4264 }
4265
04a6dfeb
AJ		 4266 target_environ = envlist_to_environ(envlist, NULL);
4267 envlist_free(envlist);
b12b6a18 4268
379f6698
PB		 4269 /*
4270 * Now that page sizes are configured in cpu_init() we can do
4271 * proper page alignment for guest_base.
4272 */
4273 guest_base = HOST_PAGE_ALIGN(guest_base);
68a1c816 4274
806d1021
MI		 4275 if (reserved_va || have_guest_base) {
4276 guest_base = init_guest_space(guest_base, reserved_va, 0,
4277 have_guest_base);
4278 if (guest_base == (unsigned long)-1) {
097b8cb8
PM		 4279 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
4280 "space for use as guest address space (check your virtual "
4281 "memory ulimit setting or reserve less using -R option)\n",
4282 reserved_va);
4d1275c2 4283 exit(EXIT_FAILURE);
68a1c816 4284 }
97cc7560 4285
806d1021
MI		 4286 if (reserved_va) {
4287 mmap_next_start = reserved_va;
97cc7560
DDAG		 4288 }
4289 }
379f6698
PB		 4290
4291 /*
4292 * Read in mmap_min_addr kernel parameter. This value is used
4293 * When loading the ELF image to determine whether guest_base
14f24e14 4294 * is needed. It is also used in mmap_find_vma.
379f6698 4295 */
14f24e14 4296 {
379f6698
PB		 4297 FILE *fp;
4298
4299 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
4300 unsigned long tmp;
4301 if (fscanf(fp, "%lu", &tmp) == 1) {
4302 mmap_min_addr = tmp;
13829020 4303 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr);
379f6698
PB		 4304 }
4305 fclose(fp);
4306 }
4307 }
379f6698 4308
7d8cec95
AJ		 4309 /*
4310 * Prepare copy of argv vector for target.
4311 */
4312 target_argc = argc - optind;
4313 target_argv = calloc(target_argc + 1, sizeof (char *));
4314 if (target_argv == NULL) {
4315 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4d1275c2 4316 exit(EXIT_FAILURE);
7d8cec95
AJ		 4317 }
4318
4319 /*
4320 * If argv0 is specified (using '-0' switch) we replace
4321 * argv[0] pointer with the given one.
4322 */
4323 i = 0;
4324 if (argv0 != NULL) {
4325 target_argv[i++] = strdup(argv0);
4326 }
4327 for (; i < target_argc; i++) {
4328 target_argv[i] = strdup(argv[optind + i]);
4329 }
4330 target_argv[target_argc] = NULL;
4331
c78d65e8 4332 ts = g_new0(TaskState, 1);
edf8e2af
MW		 4333 init_task_state(ts);
4334 /* build Task State */
4335 ts->info = info;
4336 ts->bprm = &bprm;
0429a971 4337 cpu->opaque = ts;
edf8e2af
MW		 4338 task_settid(ts);
4339
0b959cf5
RH		 4340 execfd = qemu_getauxval(AT_EXECFD);
4341 if (execfd == 0) {
03cfd8fa 4342 execfd = open(filename, O_RDONLY);
0b959cf5
RH		 4343 if (execfd < 0) {
4344 printf("Error while loading %s: %s\n", filename, strerror(errno));
4d1275c2 4345 _exit(EXIT_FAILURE);
0b959cf5 4346 }
03cfd8fa
LV		 4347 }
4348
4349 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
fd4d81dd
AP		 4350 info, &bprm);
4351 if (ret != 0) {
885c1d10 4352 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4d1275c2 4353 _exit(EXIT_FAILURE);
b12b6a18
TS		 4354 }
4355
4356 for (wrk = target_environ; *wrk; wrk++) {
4357 free(*wrk);
31e31b8a 4358 }
3b46e624 4359
b12b6a18
TS		 4360 free(target_environ);
4361
13829020 4362 if (qemu_loglevel_mask(CPU_LOG_PAGE)) {
379f6698 4363 qemu_log("guest_base 0x%lx\n", guest_base);
2e77eac6
BS		 4364 log_page_dump();
4365
4366 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4367 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4368 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4369 info->start_code);
4370 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4371 info->start_data);
4372 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4373 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4374 info->start_stack);
4375 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4376 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4377 }
31e31b8a 4378
53a5960a 4379 target_set_brk(info->brk);
31e31b8a 4380 syscall_init();
66fb9763 4381 signal_init();
31e31b8a 4382
9002ec79
RH		 4383 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4384 generating the prologue until now so that the prologue can take
4385 the real value of GUEST_BASE into account. */
4386 tcg_prologue_init(&tcg_ctx);
9002ec79 4387
b346ff46 4388#if defined(TARGET_I386)
3802ce26 4389 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
b98dbc90 4390 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
0514ef2f 4391 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
1bde465e
FB		 4392 env->cr[4] |= CR4_OSFXSR_MASK;
4393 env->hflags |= HF_OSFXSR_MASK;
4394 }
d2fd1af7 4395#ifndef TARGET_ABI32
4dbc422b 4396 /* enable 64 bit mode if possible */
0514ef2f 4397 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4dbc422b 4398 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4d1275c2 4399 exit(EXIT_FAILURE);
4dbc422b 4400 }
d2fd1af7 4401 env->cr[4] |= CR4_PAE_MASK;
4dbc422b 4402 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
d2fd1af7
FB		 4403 env->hflags |= HF_LMA_MASK;
4404#endif
1bde465e 4405
415e561f
FB		 4406 /* flags setup : we activate the IRQs by default as in user mode */
4407 env->eflags |= IF_MASK;
3b46e624 4408
6dbad63e 4409 /* linux register setup */
d2fd1af7 4410#ifndef TARGET_ABI32
84409ddb
JM		 4411 env->regs[R_EAX] = regs->rax;
4412 env->regs[R_EBX] = regs->rbx;
4413 env->regs[R_ECX] = regs->rcx;
4414 env->regs[R_EDX] = regs->rdx;
4415 env->regs[R_ESI] = regs->rsi;
4416 env->regs[R_EDI] = regs->rdi;
4417 env->regs[R_EBP] = regs->rbp;
4418 env->regs[R_ESP] = regs->rsp;
4419 env->eip = regs->rip;
4420#else
0ecfa993
FB		 4421 env->regs[R_EAX] = regs->eax;
4422 env->regs[R_EBX] = regs->ebx;
4423 env->regs[R_ECX] = regs->ecx;
4424 env->regs[R_EDX] = regs->edx;
4425 env->regs[R_ESI] = regs->esi;
4426 env->regs[R_EDI] = regs->edi;
4427 env->regs[R_EBP] = regs->ebp;
4428 env->regs[R_ESP] = regs->esp;
dab2ed99 4429 env->eip = regs->eip;
84409ddb 4430#endif
31e31b8a 4431
f4beb510 4432 /* linux interrupt setup */
e441570f
AZ		 4433#ifndef TARGET_ABI32
4434 env->idt.limit = 511;
4435#else
4436 env->idt.limit = 255;
4437#endif
4438 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4439 PROT_READ|PROT_WRITE,
4440 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4441 idt_table = g2h(env->idt.base);
f4beb510
FB		 4442 set_idt(0, 0);
4443 set_idt(1, 0);
4444 set_idt(2, 0);
4445 set_idt(3, 3);
4446 set_idt(4, 3);
ec95da6c 4447 set_idt(5, 0);
f4beb510
FB		 4448 set_idt(6, 0);
4449 set_idt(7, 0);
4450 set_idt(8, 0);
4451 set_idt(9, 0);
4452 set_idt(10, 0);
4453 set_idt(11, 0);
4454 set_idt(12, 0);
4455 set_idt(13, 0);
4456 set_idt(14, 0);
4457 set_idt(15, 0);
4458 set_idt(16, 0);
4459 set_idt(17, 0);
4460 set_idt(18, 0);
4461 set_idt(19, 0);
4462 set_idt(0x80, 3);
4463
6dbad63e 4464 /* linux segment setup */
8d18e893
FB		 4465 {
4466 uint64_t *gdt_table;
e441570f
AZ		 4467 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4468 PROT_READ|PROT_WRITE,
4469 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
8d18e893 4470 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
e441570f 4471 gdt_table = g2h(env->gdt.base);
d2fd1af7 4472#ifdef TARGET_ABI32
8d18e893
FB		 4473 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4474 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4475 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
d2fd1af7
FB		 4476#else
4477 /* 64 bit code segment */
4478 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4479 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4480 DESC_L_MASK |
4481 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4482#endif
8d18e893
FB		 4483 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4484 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4485 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4486 }
6dbad63e 4487 cpu_x86_load_seg(env, R_CS, __USER_CS);
d2fd1af7
FB		 4488 cpu_x86_load_seg(env, R_SS, __USER_DS);
4489#ifdef TARGET_ABI32
6dbad63e
FB		 4490 cpu_x86_load_seg(env, R_DS, __USER_DS);
4491 cpu_x86_load_seg(env, R_ES, __USER_DS);
6dbad63e
FB		 4492 cpu_x86_load_seg(env, R_FS, __USER_DS);
4493 cpu_x86_load_seg(env, R_GS, __USER_DS);
d6eb40f6
TS		 4494 /* This hack makes Wine work... */
4495 env->segs[R_FS].selector = 0;
d2fd1af7
FB		 4496#else
4497 cpu_x86_load_seg(env, R_DS, 0);
4498 cpu_x86_load_seg(env, R_ES, 0);
4499 cpu_x86_load_seg(env, R_FS, 0);
4500 cpu_x86_load_seg(env, R_GS, 0);
4501#endif
99033cae
AG		 4502#elif defined(TARGET_AARCH64)
4503 {
4504 int i;
4505
4506 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4507 fprintf(stderr,
4508 "The selected ARM CPU does not support 64 bit mode\n");
4d1275c2 4509 exit(EXIT_FAILURE);
99033cae
AG		 4510 }
4511
4512 for (i = 0; i < 31; i++) {
4513 env->xregs[i] = regs->regs[i];
4514 }
4515 env->pc = regs->pc;
4516 env->xregs[31] = regs->sp;
4517 }
b346ff46
FB		 4518#elif defined(TARGET_ARM)
4519 {
4520 int i;
ae087923
PM		 4521 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
4522 CPSRWriteByInstr);
b346ff46
FB		 4523 for(i = 0; i < 16; i++) {
4524 env->regs[i] = regs->uregs[i];
4525 }
f9fd40eb 4526#ifdef TARGET_WORDS_BIGENDIAN
d8fd2954
PB		 4527 /* Enable BE8. */
4528 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4529 && (info->elf_flags & EF_ARM_BE8)) {
9c5a7460
PC		 4530 env->uncached_cpsr |= CPSR_E;
4531 env->cp15.sctlr_el[1] |= SCTLR_E0E;
f9fd40eb
PB		 4532 } else {
4533 env->cp15.sctlr_el[1] |= SCTLR_B;
d8fd2954 4534 }
f9fd40eb 4535#endif
b346ff46 4536 }
d2fbca94
GX		 4537#elif defined(TARGET_UNICORE32)
4538 {
4539 int i;
4540 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4541 for (i = 0; i < 32; i++) {
4542 env->regs[i] = regs->uregs[i];
4543 }
4544 }
93ac68bc 4545#elif defined(TARGET_SPARC)
060366c5
FB		 4546 {
4547 int i;
4548 env->pc = regs->pc;
4549 env->npc = regs->npc;
4550 env->y = regs->y;
4551 for(i = 0; i < 8; i++)
4552 env->gregs[i] = regs->u_regs[i];
4553 for(i = 0; i < 8; i++)
4554 env->regwptr[i] = regs->u_regs[i + 8];
4555 }
67867308
FB		 4556#elif defined(TARGET_PPC)
4557 {
4558 int i;
3fc6c082 4559
0411a972
JM		 4560#if defined(TARGET_PPC64)
4561#if defined(TARGET_ABI32)
4562 env->msr &= ~((target_ulong)1 << MSR_SF);
e85e7c6e 4563#else
0411a972
JM		 4564 env->msr |= (target_ulong)1 << MSR_SF;
4565#endif
84409ddb 4566#endif
67867308
FB		 4567 env->nip = regs->nip;
4568 for(i = 0; i < 32; i++) {
4569 env->gpr[i] = regs->gpr[i];
4570 }
4571 }
e6e5906b
PB		 4572#elif defined(TARGET_M68K)
4573 {
e6e5906b
PB		 4574 env->pc = regs->pc;
4575 env->dregs[0] = regs->d0;
4576 env->dregs[1] = regs->d1;
4577 env->dregs[2] = regs->d2;
4578 env->dregs[3] = regs->d3;
4579 env->dregs[4] = regs->d4;
4580 env->dregs[5] = regs->d5;
4581 env->dregs[6] = regs->d6;
4582 env->dregs[7] = regs->d7;
4583 env->aregs[0] = regs->a0;
4584 env->aregs[1] = regs->a1;
4585 env->aregs[2] = regs->a2;
4586 env->aregs[3] = regs->a3;
4587 env->aregs[4] = regs->a4;
4588 env->aregs[5] = regs->a5;
4589 env->aregs[6] = regs->a6;
4590 env->aregs[7] = regs->usp;
4591 env->sr = regs->sr;
4592 ts->sim_syscalls = 1;
4593 }
b779e29e
EI		 4594#elif defined(TARGET_MICROBLAZE)
4595 {
4596 env->regs[0] = regs->r0;
4597 env->regs[1] = regs->r1;
4598 env->regs[2] = regs->r2;
4599 env->regs[3] = regs->r3;
4600 env->regs[4] = regs->r4;
4601 env->regs[5] = regs->r5;
4602 env->regs[6] = regs->r6;
4603 env->regs[7] = regs->r7;
4604 env->regs[8] = regs->r8;
4605 env->regs[9] = regs->r9;
4606 env->regs[10] = regs->r10;
4607 env->regs[11] = regs->r11;
4608 env->regs[12] = regs->r12;
4609 env->regs[13] = regs->r13;
4610 env->regs[14] = regs->r14;
4611 env->regs[15] = regs->r15;
4612 env->regs[16] = regs->r16;
4613 env->regs[17] = regs->r17;
4614 env->regs[18] = regs->r18;
4615 env->regs[19] = regs->r19;
4616 env->regs[20] = regs->r20;
4617 env->regs[21] = regs->r21;
4618 env->regs[22] = regs->r22;
4619 env->regs[23] = regs->r23;
4620 env->regs[24] = regs->r24;
4621 env->regs[25] = regs->r25;
4622 env->regs[26] = regs->r26;
4623 env->regs[27] = regs->r27;
4624 env->regs[28] = regs->r28;
4625 env->regs[29] = regs->r29;
4626 env->regs[30] = regs->r30;
4627 env->regs[31] = regs->r31;
4628 env->sregs[SR_PC] = regs->pc;
4629 }
048f6b4d
FB		 4630#elif defined(TARGET_MIPS)
4631 {
4632 int i;
4633
4634 for(i = 0; i < 32; i++) {
b5dc7732 4635 env->active_tc.gpr[i] = regs->regs[i];
048f6b4d 4636 }
0fddbbf2
NF		 4637 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4638 if (regs->cp0_epc & 1) {
4639 env->hflags |= MIPS_HFLAG_M16;
4640 }
048f6b4d 4641 }
d962783e
JL		 4642#elif defined(TARGET_OPENRISC)
4643 {
4644 int i;
4645
4646 for (i = 0; i < 32; i++) {
4647 env->gpr[i] = regs->gpr[i];
4648 }
4649
4650 env->sr = regs->sr;
4651 env->pc = regs->pc;
4652 }
fdf9b3e8
FB		 4653#elif defined(TARGET_SH4)
4654 {
4655 int i;
4656
4657 for(i = 0; i < 16; i++) {
4658 env->gregs[i] = regs->regs[i];
4659 }
4660 env->pc = regs->pc;
4661 }
7a3148a9
JM		 4662#elif defined(TARGET_ALPHA)
4663 {
4664 int i;
4665
4666 for(i = 0; i < 28; i++) {
992f48a0 4667 env->ir[i] = ((abi_ulong *)regs)[i];
7a3148a9 4668 }
dad081ee 4669 env->ir[IR_SP] = regs->usp;
7a3148a9 4670 env->pc = regs->pc;
7a3148a9 4671 }
48733d19
TS		 4672#elif defined(TARGET_CRIS)
4673 {
4674 env->regs[0] = regs->r0;
4675 env->regs[1] = regs->r1;
4676 env->regs[2] = regs->r2;
4677 env->regs[3] = regs->r3;
4678 env->regs[4] = regs->r4;
4679 env->regs[5] = regs->r5;
4680 env->regs[6] = regs->r6;
4681 env->regs[7] = regs->r7;
4682 env->regs[8] = regs->r8;
4683 env->regs[9] = regs->r9;
4684 env->regs[10] = regs->r10;
4685 env->regs[11] = regs->r11;
4686 env->regs[12] = regs->r12;
4687 env->regs[13] = regs->r13;
4688 env->regs[14] = info->start_stack;
4689 env->regs[15] = regs->acr;
4690 env->pc = regs->erp;
4691 }
a4c075f1
UH		 4692#elif defined(TARGET_S390X)
4693 {
4694 int i;
4695 for (i = 0; i < 16; i++) {
4696 env->regs[i] = regs->gprs[i];
4697 }
4698 env->psw.mask = regs->psw.mask;
4699 env->psw.addr = regs->psw.addr;
4700 }
b16189b2
CG		 4701#elif defined(TARGET_TILEGX)
4702 {
4703 int i;
4704 for (i = 0; i < TILEGX_R_COUNT; i++) {
4705 env->regs[i] = regs->regs[i];
4706 }
4707 for (i = 0; i < TILEGX_SPR_COUNT; i++) {
4708 env->spregs[i] = 0;
4709 }
4710 env->pc = regs->pc;
4711 }
b346ff46
FB		 4712#else
4713#error unsupported target CPU
4714#endif
31e31b8a 4715
d2fbca94 4716#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
a87295e8
PB		 4717 ts->stack_base = info->start_stack;
4718 ts->heap_base = info->brk;
4719 /* This will be filled in on the first SYS_HEAPINFO call. */
4720 ts->heap_limit = 0;
4721#endif
4722
74c33bed 4723 if (gdbstub_port) {
ff7a981a
PM		 4724 if (gdbserver_start(gdbstub_port) < 0) {
4725 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4726 gdbstub_port);
4d1275c2 4727 exit(EXIT_FAILURE);
ff7a981a 4728 }
db6b81d4 4729 gdb_handlesig(cpu, 0);
1fddef4b 4730 }
1b6b029e
FB		 4731 cpu_loop(env);
4732 /* never exits */
31e31b8a
FB		 4733 return 0;
4734}
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