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31e31b8a 1/*
93ac68bc 2 * qemu user main
5fafdf24 3 *
68d0f70e 4 * Copyright (c) 2003-2008 Fabrice Bellard
31e31b8a
FB		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
8167ee88 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31e31b8a
FB		 18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <stdarg.h>
04369ff2 22#include <string.h>
31e31b8a 23#include <errno.h>
0ecfa993 24#include <unistd.h>
e441570f 25#include <sys/mman.h>
edf8e2af 26#include <sys/syscall.h>
703e0e89 27#include <sys/resource.h>
31e31b8a 28
3ef693a0 29#include "qemu.h"
ca10f867 30#include "qemu-common.h"
2b41f10e 31#include "cpu.h"
9002ec79 32#include "tcg.h"
1de7afc9
PB		 33#include "qemu/timer.h"
34#include "qemu/envlist.h"
d8fd2954 35#include "elf.h"
04a6dfeb 36
d088d664
AJ		 37char *exec_path;
38
1b530a6d 39int singlestep;
fc9c5412
JS		 40const char *filename;
41const char *argv0;
42int gdbstub_port;
43envlist_t *envlist;
51fb256a 44static const char *cpu_model;
379f6698 45unsigned long mmap_min_addr;
14f24e14 46#if defined(CONFIG_USE_GUEST_BASE)
379f6698
PB		 47unsigned long guest_base;
48int have_guest_base;
288e65b9
AG		 49#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
50/*
51 * When running 32-on-64 we should make sure we can fit all of the possible
52 * guest address space into a contiguous chunk of virtual host memory.
53 *
54 * This way we will never overlap with our own libraries or binaries or stack
55 * or anything else that QEMU maps.
56 */
314992b1
AG		 57# ifdef TARGET_MIPS
58/* MIPS only supports 31 bits of virtual address space for user space */
59unsigned long reserved_va = 0x77000000;
60# else
288e65b9 61unsigned long reserved_va = 0xf7000000;
314992b1 62# endif
288e65b9 63#else
68a1c816 64unsigned long reserved_va;
379f6698 65#endif
288e65b9 66#endif
1b530a6d 67
fc9c5412
JS		 68static void usage(void);
69
7ee2822c 70static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
e586822a 71const char *qemu_uname_release;
586314f2 72
9de5e440
FB		 73/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
74 we allocate a bigger stack. Need a better solution, for example
75 by remapping the process stack directly at the right place */
703e0e89 76unsigned long guest_stack_size = 8 * 1024 * 1024UL;
31e31b8a
FB		 77
78void gemu_log(const char *fmt, ...)
79{
80 va_list ap;
81
82 va_start(ap, fmt);
83 vfprintf(stderr, fmt, ap);
84 va_end(ap);
85}
86
8fcd3692 87#if defined(TARGET_I386)
05390248 88int cpu_get_pic_interrupt(CPUX86State *env)
92ccca6a
FB		 89{
90 return -1;
91}
8fcd3692 92#endif
92ccca6a 93
d5975363
PB		 94/***********************************************************/
95/* Helper routines for implementing atomic operations. */
96
97/* To implement exclusive operations we force all cpus to syncronise.
98 We don't require a full sync, only that no cpus are executing guest code.
99 The alternative is to map target atomic ops onto host equivalents,
100 which requires quite a lot of per host/target work. */
c2764719 101static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
d5975363
PB		 102static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
103static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
104static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
105static int pending_cpus;
106
107/* Make sure everything is in a consistent state for calling fork(). */
108void fork_start(void)
109{
5e5f07e0 110 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 111 pthread_mutex_lock(&exclusive_lock);
d032d1b4 112 mmap_fork_start();
d5975363
PB		 113}
114
115void fork_end(int child)
116{
d032d1b4 117 mmap_fork_end(child);
d5975363 118 if (child) {
bdc44640 119 CPUState *cpu, *next_cpu;
d5975363
PB		 120 /* Child processes created by fork() only have a single thread.
121 Discard information about the parent threads. */
bdc44640
AF		 122 CPU_FOREACH_SAFE(cpu, next_cpu) {
123 if (cpu != thread_cpu) {
124 QTAILQ_REMOVE(&cpus, thread_cpu, node);
125 }
126 }
d5975363
PB		 127 pending_cpus = 0;
128 pthread_mutex_init(&exclusive_lock, NULL);
c2764719 129 pthread_mutex_init(&cpu_list_mutex, NULL);
d5975363
PB		 130 pthread_cond_init(&exclusive_cond, NULL);
131 pthread_cond_init(&exclusive_resume, NULL);
5e5f07e0 132 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
a2247f8e 133 gdbserver_fork((CPUArchState *)thread_cpu->env_ptr);
d5975363
PB		 134 } else {
135 pthread_mutex_unlock(&exclusive_lock);
5e5f07e0 136 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 137 }
d5975363
PB		 138}
139
140/* Wait for pending exclusive operations to complete. The exclusive lock
141 must be held. */
142static inline void exclusive_idle(void)
143{
144 while (pending_cpus) {
145 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
146 }
147}
148
149/* Start an exclusive operation.
150 Must only be called from outside cpu_arm_exec. */
151static inline void start_exclusive(void)
152{
0315c31c
AF		 153 CPUState *other_cpu;
154
d5975363
PB		 155 pthread_mutex_lock(&exclusive_lock);
156 exclusive_idle();
157
158 pending_cpus = 1;
159 /* Make all other cpus stop executing. */
bdc44640 160 CPU_FOREACH(other_cpu) {
0315c31c 161 if (other_cpu->running) {
d5975363 162 pending_cpus++;
60a3e17a 163 cpu_exit(other_cpu);
d5975363
PB		 164 }
165 }
166 if (pending_cpus > 1) {
167 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
168 }
169}
170
171/* Finish an exclusive operation. */
f7e61b22 172static inline void __attribute__((unused)) end_exclusive(void)
d5975363
PB		 173{
174 pending_cpus = 0;
175 pthread_cond_broadcast(&exclusive_resume);
176 pthread_mutex_unlock(&exclusive_lock);
177}
178
179/* Wait for exclusive ops to finish, and begin cpu execution. */
0315c31c 180static inline void cpu_exec_start(CPUState *cpu)
d5975363
PB		 181{
182 pthread_mutex_lock(&exclusive_lock);
183 exclusive_idle();
0315c31c 184 cpu->running = true;
d5975363
PB		 185 pthread_mutex_unlock(&exclusive_lock);
186}
187
188/* Mark cpu as not executing, and release pending exclusive ops. */
0315c31c 189static inline void cpu_exec_end(CPUState *cpu)
d5975363
PB		 190{
191 pthread_mutex_lock(&exclusive_lock);
0315c31c 192 cpu->running = false;
d5975363
PB		 193 if (pending_cpus > 1) {
194 pending_cpus--;
195 if (pending_cpus == 1) {
196 pthread_cond_signal(&exclusive_cond);
197 }
198 }
199 exclusive_idle();
200 pthread_mutex_unlock(&exclusive_lock);
201}
c2764719
PB		 202
203void cpu_list_lock(void)
204{
205 pthread_mutex_lock(&cpu_list_mutex);
206}
207
208void cpu_list_unlock(void)
209{
210 pthread_mutex_unlock(&cpu_list_mutex);
211}
d5975363
PB		 212
213
a541f297
FB		 214#ifdef TARGET_I386
215/***********************************************************/
216/* CPUX86 core interface */
217
05390248 218void cpu_smm_update(CPUX86State *env)
02a1602e
FB		 219{
220}
221
28ab0e2e
FB		 222uint64_t cpu_get_tsc(CPUX86State *env)
223{
224 return cpu_get_real_ticks();
225}
226
5fafdf24 227static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
f4beb510 228 int flags)
6dbad63e 229{
f4beb510 230 unsigned int e1, e2;
53a5960a 231 uint32_t *p;
6dbad63e
FB		 232 e1 = (addr << 16) | (limit & 0xffff);
233 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
f4beb510 234 e2 |= flags;
53a5960a 235 p = ptr;
d538e8f5 236 p[0] = tswap32(e1);
237 p[1] = tswap32(e2);
f4beb510
FB		 238}
239
e441570f 240static uint64_t *idt_table;
eb38c52c 241#ifdef TARGET_X86_64
d2fd1af7
FB		 242static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
243 uint64_t addr, unsigned int sel)
f4beb510 244{
4dbc422b 245 uint32_t *p, e1, e2;
f4beb510
FB		 246 e1 = (addr & 0xffff) | (sel << 16);
247 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
53a5960a 248 p = ptr;
4dbc422b
FB		 249 p[0] = tswap32(e1);
250 p[1] = tswap32(e2);
251 p[2] = tswap32(addr >> 32);
252 p[3] = 0;
6dbad63e 253}
d2fd1af7
FB		 254/* only dpl matters as we do only user space emulation */
255static void set_idt(int n, unsigned int dpl)
256{
257 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
258}
259#else
d2fd1af7
FB		 260static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
261 uint32_t addr, unsigned int sel)
262{
4dbc422b 263 uint32_t *p, e1, e2;
d2fd1af7
FB		 264 e1 = (addr & 0xffff) | (sel << 16);
265 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
266 p = ptr;
4dbc422b
FB		 267 p[0] = tswap32(e1);
268 p[1] = tswap32(e2);
d2fd1af7
FB		 269}
270
f4beb510
FB		 271/* only dpl matters as we do only user space emulation */
272static void set_idt(int n, unsigned int dpl)
273{
274 set_gate(idt_table + n, 0, dpl, 0, 0);
275}
d2fd1af7 276#endif
31e31b8a 277
89e957e7 278void cpu_loop(CPUX86State *env)
1b6b029e 279{
db6b81d4 280 CPUState *cs = CPU(x86_env_get_cpu(env));
bc8a22cc 281 int trapnr;
992f48a0 282 abi_ulong pc;
c227f099 283 target_siginfo_t info;
851e67a1 284
1b6b029e 285 for(;;) {
b040bc9c 286 cpu_exec_start(cs);
bc8a22cc 287 trapnr = cpu_x86_exec(env);
b040bc9c 288 cpu_exec_end(cs);
bc8a22cc 289 switch(trapnr) {
f4beb510 290 case 0x80:
d2fd1af7 291 /* linux syscall from int $0x80 */
5fafdf24
TS		 292 env->regs[R_EAX] = do_syscall(env,
293 env->regs[R_EAX],
f4beb510
FB		 294 env->regs[R_EBX],
295 env->regs[R_ECX],
296 env->regs[R_EDX],
297 env->regs[R_ESI],
298 env->regs[R_EDI],
5945cfcb
PM		 299 env->regs[R_EBP],
300 0, 0);
f4beb510 301 break;
d2fd1af7
FB		 302#ifndef TARGET_ABI32
303 case EXCP_SYSCALL:
5ba18547 304 /* linux syscall from syscall instruction */
d2fd1af7
FB		 305 env->regs[R_EAX] = do_syscall(env,
306 env->regs[R_EAX],
307 env->regs[R_EDI],
308 env->regs[R_ESI],
309 env->regs[R_EDX],
310 env->regs[10],
311 env->regs[8],
5945cfcb
PM		 312 env->regs[9],
313 0, 0);
d2fd1af7
FB		 314 break;
315#endif
f4beb510
FB		 316 case EXCP0B_NOSEG:
317 case EXCP0C_STACK:
a86b3c64 318 info.si_signo = TARGET_SIGBUS;
f4beb510
FB		 319 info.si_errno = 0;
320 info.si_code = TARGET_SI_KERNEL;
321 info._sifields._sigfault._addr = 0;
624f7979 322 queue_signal(env, info.si_signo, &info);
f4beb510 323 break;
1b6b029e 324 case EXCP0D_GPF:
d2fd1af7 325 /* XXX: potential problem if ABI32 */
84409ddb 326#ifndef TARGET_X86_64
851e67a1 327 if (env->eflags & VM_MASK) {
89e957e7 328 handle_vm86_fault(env);
84409ddb
JM		 329 } else
330#endif
331 {
a86b3c64 332 info.si_signo = TARGET_SIGSEGV;
f4beb510
FB		 333 info.si_errno = 0;
334 info.si_code = TARGET_SI_KERNEL;
335 info._sifields._sigfault._addr = 0;
624f7979 336 queue_signal(env, info.si_signo, &info);
1b6b029e
FB		 337 }
338 break;
b689bc57 339 case EXCP0E_PAGE:
a86b3c64 340 info.si_signo = TARGET_SIGSEGV;
b689bc57
FB		 341 info.si_errno = 0;
342 if (!(env->error_code & 1))
343 info.si_code = TARGET_SEGV_MAPERR;
344 else
345 info.si_code = TARGET_SEGV_ACCERR;
970a87a6 346 info._sifields._sigfault._addr = env->cr[2];
624f7979 347 queue_signal(env, info.si_signo, &info);
b689bc57 348 break;
9de5e440 349 case EXCP00_DIVZ:
84409ddb 350#ifndef TARGET_X86_64
bc8a22cc 351 if (env->eflags & VM_MASK) {
447db213 352 handle_vm86_trap(env, trapnr);
84409ddb
JM		 353 } else
354#endif
355 {
bc8a22cc 356 /* division by zero */
a86b3c64 357 info.si_signo = TARGET_SIGFPE;
bc8a22cc
FB		 358 info.si_errno = 0;
359 info.si_code = TARGET_FPE_INTDIV;
360 info._sifields._sigfault._addr = env->eip;
624f7979 361 queue_signal(env, info.si_signo, &info);
bc8a22cc 362 }
9de5e440 363 break;
01df040b 364 case EXCP01_DB:
447db213 365 case EXCP03_INT3:
84409ddb 366#ifndef TARGET_X86_64
447db213
FB		 367 if (env->eflags & VM_MASK) {
368 handle_vm86_trap(env, trapnr);
84409ddb
JM		 369 } else
370#endif
371 {
a86b3c64 372 info.si_signo = TARGET_SIGTRAP;
447db213 373 info.si_errno = 0;
01df040b 374 if (trapnr == EXCP01_DB) {
447db213
FB		 375 info.si_code = TARGET_TRAP_BRKPT;
376 info._sifields._sigfault._addr = env->eip;
377 } else {
378 info.si_code = TARGET_SI_KERNEL;
379 info._sifields._sigfault._addr = 0;
380 }
624f7979 381 queue_signal(env, info.si_signo, &info);
447db213
FB		 382 }
383 break;
9de5e440
FB		 384 case EXCP04_INTO:
385 case EXCP05_BOUND:
84409ddb 386#ifndef TARGET_X86_64
bc8a22cc 387 if (env->eflags & VM_MASK) {
447db213 388 handle_vm86_trap(env, trapnr);
84409ddb
JM		 389 } else
390#endif
391 {
a86b3c64 392 info.si_signo = TARGET_SIGSEGV;
bc8a22cc 393 info.si_errno = 0;
b689bc57 394 info.si_code = TARGET_SI_KERNEL;
bc8a22cc 395 info._sifields._sigfault._addr = 0;
624f7979 396 queue_signal(env, info.si_signo, &info);
bc8a22cc 397 }
9de5e440
FB		 398 break;
399 case EXCP06_ILLOP:
a86b3c64 400 info.si_signo = TARGET_SIGILL;
9de5e440
FB		 401 info.si_errno = 0;
402 info.si_code = TARGET_ILL_ILLOPN;
403 info._sifields._sigfault._addr = env->eip;
624f7979 404 queue_signal(env, info.si_signo, &info);
9de5e440
FB		 405 break;
406 case EXCP_INTERRUPT:
407 /* just indicate that signals should be handled asap */
408 break;
1fddef4b
FB		 409 case EXCP_DEBUG:
410 {
411 int sig;
412
db6b81d4 413 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 414 if (sig)
415 {
416 info.si_signo = sig;
417 info.si_errno = 0;
418 info.si_code = TARGET_TRAP_BRKPT;
624f7979 419 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 420 }
421 }
422 break;
1b6b029e 423 default:
970a87a6 424 pc = env->segs[R_CS].base + env->eip;
5fafdf24 425 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
bc8a22cc 426 (long)pc, trapnr);
1b6b029e
FB		 427 abort();
428 }
66fb9763 429 process_pending_signals(env);
1b6b029e
FB		 430 }
431}
b346ff46
FB		 432#endif
433
434#ifdef TARGET_ARM
435
d8fd2954
PB		 436#define get_user_code_u32(x, gaddr, doswap) \
437 ({ abi_long __r = get_user_u32((x), (gaddr)); \
438 if (!__r && (doswap)) { \
439 (x) = bswap32(x); \
440 } \
441 __r; \
442 })
443
444#define get_user_code_u16(x, gaddr, doswap) \
445 ({ abi_long __r = get_user_u16((x), (gaddr)); \
446 if (!__r && (doswap)) { \
447 (x) = bswap16(x); \
448 } \
449 __r; \
450 })
451
1861c454
PM		 452#ifdef TARGET_ABI32
453/* Commpage handling -- there is no commpage for AArch64 */
454
97cc7560
DDAG		 455/*
456 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
457 * Input:
458 * r0 = pointer to oldval
459 * r1 = pointer to newval
460 * r2 = pointer to target value
461 *
462 * Output:
463 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
464 * C set if *ptr was changed, clear if no exchange happened
465 *
466 * Note segv's in kernel helpers are a bit tricky, we can set the
467 * data address sensibly but the PC address is just the entry point.
468 */
469static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
470{
471 uint64_t oldval, newval, val;
472 uint32_t addr, cpsr;
473 target_siginfo_t info;
474
475 /* Based on the 32 bit code in do_kernel_trap */
476
477 /* XXX: This only works between threads, not between processes.
478 It's probably possible to implement this with native host
479 operations. However things like ldrex/strex are much harder so
480 there's not much point trying. */
481 start_exclusive();
482 cpsr = cpsr_read(env);
483 addr = env->regs[2];
484
485 if (get_user_u64(oldval, env->regs[0])) {
abf1172f 486 env->exception.vaddress = env->regs[0];
97cc7560
DDAG		 487 goto segv;
488 };
489
490 if (get_user_u64(newval, env->regs[1])) {
abf1172f 491 env->exception.vaddress = env->regs[1];
97cc7560
DDAG		 492 goto segv;
493 };
494
495 if (get_user_u64(val, addr)) {
abf1172f 496 env->exception.vaddress = addr;
97cc7560
DDAG		 497 goto segv;
498 }
499
500 if (val == oldval) {
501 val = newval;
502
503 if (put_user_u64(val, addr)) {
abf1172f 504 env->exception.vaddress = addr;
97cc7560
DDAG		 505 goto segv;
506 };
507
508 env->regs[0] = 0;
509 cpsr |= CPSR_C;
510 } else {
511 env->regs[0] = -1;
512 cpsr &= ~CPSR_C;
513 }
514 cpsr_write(env, cpsr, CPSR_C);
515 end_exclusive();
516 return;
517
518segv:
519 end_exclusive();
520 /* We get the PC of the entry address - which is as good as anything,
521 on a real kernel what you get depends on which mode it uses. */
a86b3c64 522 info.si_signo = TARGET_SIGSEGV;
97cc7560
DDAG		 523 info.si_errno = 0;
524 /* XXX: check env->error_code */
525 info.si_code = TARGET_SEGV_MAPERR;
abf1172f 526 info._sifields._sigfault._addr = env->exception.vaddress;
97cc7560
DDAG		 527 queue_signal(env, info.si_signo, &info);
528
529 end_exclusive();
530}
531
fbb4a2e3
PB		 532/* Handle a jump to the kernel code page. */
533static int
534do_kernel_trap(CPUARMState *env)
535{
536 uint32_t addr;
537 uint32_t cpsr;
538 uint32_t val;
539
540 switch (env->regs[15]) {
541 case 0xffff0fa0: /* __kernel_memory_barrier */
542 /* ??? No-op. Will need to do better for SMP. */
543 break;
544 case 0xffff0fc0: /* __kernel_cmpxchg */
d5975363
PB		 545 /* XXX: This only works between threads, not between processes.
546 It's probably possible to implement this with native host
547 operations. However things like ldrex/strex are much harder so
548 there's not much point trying. */
549 start_exclusive();
fbb4a2e3
PB		 550 cpsr = cpsr_read(env);
551 addr = env->regs[2];
552 /* FIXME: This should SEGV if the access fails. */
553 if (get_user_u32(val, addr))
554 val = ~env->regs[0];
555 if (val == env->regs[0]) {
556 val = env->regs[1];
557 /* FIXME: Check for segfaults. */
558 put_user_u32(val, addr);
559 env->regs[0] = 0;
560 cpsr |= CPSR_C;
561 } else {
562 env->regs[0] = -1;
563 cpsr &= ~CPSR_C;
564 }
565 cpsr_write(env, cpsr, CPSR_C);
d5975363 566 end_exclusive();
fbb4a2e3
PB		 567 break;
568 case 0xffff0fe0: /* __kernel_get_tls */
54bf36ed 569 env->regs[0] = env->cp15.tpidrro_el[0];
fbb4a2e3 570 break;
97cc7560
DDAG		 571 case 0xffff0f60: /* __kernel_cmpxchg64 */
572 arm_kernel_cmpxchg64_helper(env);
573 break;
574
fbb4a2e3
PB		 575 default:
576 return 1;
577 }
578 /* Jump back to the caller. */
579 addr = env->regs[14];
580 if (addr & 1) {
581 env->thumb = 1;
582 addr &= ~1;
583 }
584 env->regs[15] = addr;
585
586 return 0;
587}
588
fa2ef212 589/* Store exclusive handling for AArch32 */
426f5abc
PB		 590static int do_strex(CPUARMState *env)
591{
03d05e2d 592 uint64_t val;
426f5abc
PB		 593 int size;
594 int rc = 1;
595 int segv = 0;
596 uint32_t addr;
597 start_exclusive();
03d05e2d 598 if (env->exclusive_addr != env->exclusive_test) {
426f5abc
PB		 599 goto fail;
600 }
03d05e2d
PM		 601 /* We know we're always AArch32 so the address is in uint32_t range
602 * unless it was the -1 exclusive-monitor-lost value (which won't
603 * match exclusive_test above).
604 */
605 assert(extract64(env->exclusive_addr, 32, 32) == 0);
606 addr = env->exclusive_addr;
426f5abc
PB		 607 size = env->exclusive_info & 0xf;
608 switch (size) {
609 case 0:
610 segv = get_user_u8(val, addr);
611 break;
612 case 1:
613 segv = get_user_u16(val, addr);
614 break;
615 case 2:
616 case 3:
617 segv = get_user_u32(val, addr);
618 break;
f7001a3b
AJ		 619 default:
620 abort();
426f5abc
PB		 621 }
622 if (segv) {
abf1172f 623 env->exception.vaddress = addr;
426f5abc
PB		 624 goto done;
625 }
426f5abc 626 if (size == 3) {
03d05e2d
PM		 627 uint32_t valhi;
628 segv = get_user_u32(valhi, addr + 4);
426f5abc 629 if (segv) {
abf1172f 630 env->exception.vaddress = addr + 4;
426f5abc
PB		 631 goto done;
632 }
03d05e2d 633 val = deposit64(val, 32, 32, valhi);
426f5abc 634 }
03d05e2d
PM		 635 if (val != env->exclusive_val) {
636 goto fail;
637 }
638
426f5abc
PB		 639 val = env->regs[(env->exclusive_info >> 8) & 0xf];
640 switch (size) {
641 case 0:
642 segv = put_user_u8(val, addr);
643 break;
644 case 1:
645 segv = put_user_u16(val, addr);
646 break;
647 case 2:
648 case 3:
649 segv = put_user_u32(val, addr);
650 break;
651 }
652 if (segv) {
abf1172f 653 env->exception.vaddress = addr;
426f5abc
PB		 654 goto done;
655 }
656 if (size == 3) {
657 val = env->regs[(env->exclusive_info >> 12) & 0xf];
2c9adbda 658 segv = put_user_u32(val, addr + 4);
426f5abc 659 if (segv) {
abf1172f 660 env->exception.vaddress = addr + 4;
426f5abc
PB		 661 goto done;
662 }
663 }
664 rc = 0;
665fail:
725b8a69 666 env->regs[15] += 4;
426f5abc
PB		 667 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
668done:
669 end_exclusive();
670 return segv;
671}
672
b346ff46
FB		 673void cpu_loop(CPUARMState *env)
674{
0315c31c 675 CPUState *cs = CPU(arm_env_get_cpu(env));
b346ff46
FB		 676 int trapnr;
677 unsigned int n, insn;
c227f099 678 target_siginfo_t info;
b5ff1b31 679 uint32_t addr;
3b46e624 680
b346ff46 681 for(;;) {
0315c31c 682 cpu_exec_start(cs);
b346ff46 683 trapnr = cpu_arm_exec(env);
0315c31c 684 cpu_exec_end(cs);
b346ff46
FB		 685 switch(trapnr) {
686 case EXCP_UDEF:
c6981055 687 {
0429a971 688 TaskState *ts = cs->opaque;
c6981055 689 uint32_t opcode;
6d9a42be 690 int rc;
c6981055
FB		 691
692 /* we handle the FPU emulation here, as Linux */
693 /* we get the opcode */
2f619698 694 /* FIXME - what to do if get_user() fails? */
d8fd2954 695 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
3b46e624 696
6d9a42be
AJ		 697 rc = EmulateAll(opcode, &ts->fpa, env);
698 if (rc == 0) { /* illegal instruction */
a86b3c64 699 info.si_signo = TARGET_SIGILL;
c6981055
FB		 700 info.si_errno = 0;
701 info.si_code = TARGET_ILL_ILLOPN;
702 info._sifields._sigfault._addr = env->regs[15];
624f7979 703 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 704 } else if (rc < 0) { /* FP exception */
705 int arm_fpe=0;
706
707 /* translate softfloat flags to FPSR flags */
708 if (-rc & float_flag_invalid)
709 arm_fpe |= BIT_IOC;
710 if (-rc & float_flag_divbyzero)
711 arm_fpe |= BIT_DZC;
712 if (-rc & float_flag_overflow)
713 arm_fpe |= BIT_OFC;
714 if (-rc & float_flag_underflow)
715 arm_fpe |= BIT_UFC;
716 if (-rc & float_flag_inexact)
717 arm_fpe |= BIT_IXC;
718
719 FPSR fpsr = ts->fpa.fpsr;
720 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
721
722 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
a86b3c64 723 info.si_signo = TARGET_SIGFPE;
6d9a42be
AJ		 724 info.si_errno = 0;
725
726 /* ordered by priority, least first */
727 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
728 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
729 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
730 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
731 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
732
733 info._sifields._sigfault._addr = env->regs[15];
624f7979 734 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 735 } else {
736 env->regs[15] += 4;
737 }
738
739 /* accumulate unenabled exceptions */
740 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
741 fpsr |= BIT_IXC;
742 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
743 fpsr |= BIT_UFC;
744 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
745 fpsr |= BIT_OFC;
746 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
747 fpsr |= BIT_DZC;
748 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
749 fpsr |= BIT_IOC;
750 ts->fpa.fpsr=fpsr;
751 } else { /* everything OK */
c6981055
FB		 752 /* increment PC */
753 env->regs[15] += 4;
754 }
755 }
b346ff46
FB		 756 break;
757 case EXCP_SWI:
06c949e6 758 case EXCP_BKPT:
b346ff46 759 {
ce4defa0 760 env->eabi = 1;
b346ff46 761 /* system call */
06c949e6
PB		 762 if (trapnr == EXCP_BKPT) {
763 if (env->thumb) {
2f619698 764 /* FIXME - what to do if get_user() fails? */
d8fd2954 765 get_user_code_u16(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 766 n = insn & 0xff;
767 env->regs[15] += 2;
768 } else {
2f619698 769 /* FIXME - what to do if get_user() fails? */
d8fd2954 770 get_user_code_u32(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 771 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
772 env->regs[15] += 4;
773 }
192c7bd9 774 } else {
06c949e6 775 if (env->thumb) {
2f619698 776 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 777 get_user_code_u16(insn, env->regs[15] - 2,
778 env->bswap_code);
06c949e6
PB		 779 n = insn & 0xff;
780 } else {
2f619698 781 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 782 get_user_code_u32(insn, env->regs[15] - 4,
783 env->bswap_code);
06c949e6
PB		 784 n = insn & 0xffffff;
785 }
192c7bd9
FB		 786 }
787
6f1f31c0 788 if (n == ARM_NR_cacheflush) {
dcfd14b3 789 /* nop */
a4f81979
FB		 790 } else if (n == ARM_NR_semihosting
791 || n == ARM_NR_thumb_semihosting) {
792 env->regs[0] = do_arm_semihosting (env);
3a1363ac 793 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
b346ff46 794 /* linux syscall */
ce4defa0 795 if (env->thumb || n == 0) {
192c7bd9
FB		 796 n = env->regs[7];
797 } else {
798 n -= ARM_SYSCALL_BASE;
ce4defa0 799 env->eabi = 0;
192c7bd9 800 }
fbb4a2e3
PB		 801 if ( n > ARM_NR_BASE) {
802 switch (n) {
803 case ARM_NR_cacheflush:
dcfd14b3 804 /* nop */
fbb4a2e3
PB		 805 break;
806 case ARM_NR_set_tls:
807 cpu_set_tls(env, env->regs[0]);
808 env->regs[0] = 0;
809 break;
d5355087
HL		 810 case ARM_NR_breakpoint:
811 env->regs[15] -= env->thumb ? 2 : 4;
812 goto excp_debug;
fbb4a2e3
PB		 813 default:
814 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
815 n);
816 env->regs[0] = -TARGET_ENOSYS;
817 break;
818 }
819 } else {
820 env->regs[0] = do_syscall(env,
821 n,
822 env->regs[0],
823 env->regs[1],
824 env->regs[2],
825 env->regs[3],
826 env->regs[4],
5945cfcb
PM		 827 env->regs[5],
828 0, 0);
fbb4a2e3 829 }
b346ff46
FB		 830 } else {
831 goto error;
832 }
833 }
834 break;
43fff238
FB		 835 case EXCP_INTERRUPT:
836 /* just indicate that signals should be handled asap */
837 break;
abf1172f
PM		 838 case EXCP_STREX:
839 if (!do_strex(env)) {
840 break;
841 }
842 /* fall through for segv */
68016c62
FB		 843 case EXCP_PREFETCH_ABORT:
844 case EXCP_DATA_ABORT:
abf1172f 845 addr = env->exception.vaddress;
68016c62 846 {
a86b3c64 847 info.si_signo = TARGET_SIGSEGV;
68016c62
FB		 848 info.si_errno = 0;
849 /* XXX: check env->error_code */
850 info.si_code = TARGET_SEGV_MAPERR;
b5ff1b31 851 info._sifields._sigfault._addr = addr;
624f7979 852 queue_signal(env, info.si_signo, &info);
68016c62
FB		 853 }
854 break;
1fddef4b 855 case EXCP_DEBUG:
d5355087 856 excp_debug:
1fddef4b
FB		 857 {
858 int sig;
859
db6b81d4 860 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 861 if (sig)
862 {
863 info.si_signo = sig;
864 info.si_errno = 0;
865 info.si_code = TARGET_TRAP_BRKPT;
624f7979 866 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 867 }
868 }
869 break;
fbb4a2e3
PB		 870 case EXCP_KERNEL_TRAP:
871 if (do_kernel_trap(env))
872 goto error;
873 break;
b346ff46
FB		 874 default:
875 error:
5fafdf24 876 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
b346ff46 877 trapnr);
878096ee 878 cpu_dump_state(cs, stderr, fprintf, 0);
b346ff46
FB		 879 abort();
880 }
881 process_pending_signals(env);
882 }
883}
884
1861c454
PM		 885#else
886
fa2ef212
MM		 887/*
888 * Handle AArch64 store-release exclusive
889 *
890 * rs = gets the status result of store exclusive
891 * rt = is the register that is stored
892 * rt2 = is the second register store (in STP)
893 *
894 */
895static int do_strex_a64(CPUARMState *env)
896{
897 uint64_t val;
898 int size;
899 bool is_pair;
900 int rc = 1;
901 int segv = 0;
902 uint64_t addr;
903 int rs, rt, rt2;
904
905 start_exclusive();
906 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
907 size = extract32(env->exclusive_info, 0, 2);
908 is_pair = extract32(env->exclusive_info, 2, 1);
909 rs = extract32(env->exclusive_info, 4, 5);
910 rt = extract32(env->exclusive_info, 9, 5);
911 rt2 = extract32(env->exclusive_info, 14, 5);
912
913 addr = env->exclusive_addr;
914
915 if (addr != env->exclusive_test) {
916 goto finish;
917 }
918
919 switch (size) {
920 case 0:
921 segv = get_user_u8(val, addr);
922 break;
923 case 1:
924 segv = get_user_u16(val, addr);
925 break;
926 case 2:
927 segv = get_user_u32(val, addr);
928 break;
929 case 3:
930 segv = get_user_u64(val, addr);
931 break;
932 default:
933 abort();
934 }
935 if (segv) {
abf1172f 936 env->exception.vaddress = addr;
fa2ef212
MM		 937 goto error;
938 }
939 if (val != env->exclusive_val) {
940 goto finish;
941 }
942 if (is_pair) {
943 if (size == 2) {
944 segv = get_user_u32(val, addr + 4);
945 } else {
946 segv = get_user_u64(val, addr + 8);
947 }
948 if (segv) {
abf1172f 949 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 950 goto error;
951 }
952 if (val != env->exclusive_high) {
953 goto finish;
954 }
955 }
2ea5a2ca
JG		 956 /* handle the zero register */
957 val = rt == 31 ? 0 : env->xregs[rt];
fa2ef212
MM		 958 switch (size) {
959 case 0:
960 segv = put_user_u8(val, addr);
961 break;
962 case 1:
963 segv = put_user_u16(val, addr);
964 break;
965 case 2:
966 segv = put_user_u32(val, addr);
967 break;
968 case 3:
969 segv = put_user_u64(val, addr);
970 break;
971 }
972 if (segv) {
973 goto error;
974 }
975 if (is_pair) {
2ea5a2ca
JG		 976 /* handle the zero register */
977 val = rt2 == 31 ? 0 : env->xregs[rt2];
fa2ef212
MM		 978 if (size == 2) {
979 segv = put_user_u32(val, addr + 4);
980 } else {
981 segv = put_user_u64(val, addr + 8);
982 }
983 if (segv) {
abf1172f 984 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 985 goto error;
986 }
987 }
988 rc = 0;
989finish:
990 env->pc += 4;
991 /* rs == 31 encodes a write to the ZR, thus throwing away
992 * the status return. This is rather silly but valid.
993 */
994 if (rs < 31) {
995 env->xregs[rs] = rc;
996 }
997error:
998 /* instruction faulted, PC does not advance */
999 /* either way a strex releases any exclusive lock we have */
1000 env->exclusive_addr = -1;
1001 end_exclusive();
1002 return segv;
1003}
1004
1861c454
PM		 1005/* AArch64 main loop */
1006void cpu_loop(CPUARMState *env)
1007{
1008 CPUState *cs = CPU(arm_env_get_cpu(env));
1009 int trapnr, sig;
1010 target_siginfo_t info;
1861c454
PM		 1011
1012 for (;;) {
1013 cpu_exec_start(cs);
1014 trapnr = cpu_arm_exec(env);
1015 cpu_exec_end(cs);
1016
1017 switch (trapnr) {
1018 case EXCP_SWI:
1019 env->xregs[0] = do_syscall(env,
1020 env->xregs[8],
1021 env->xregs[0],
1022 env->xregs[1],
1023 env->xregs[2],
1024 env->xregs[3],
1025 env->xregs[4],
1026 env->xregs[5],
1027 0, 0);
1028 break;
1029 case EXCP_INTERRUPT:
1030 /* just indicate that signals should be handled asap */
1031 break;
1032 case EXCP_UDEF:
a86b3c64 1033 info.si_signo = TARGET_SIGILL;
1861c454
PM		 1034 info.si_errno = 0;
1035 info.si_code = TARGET_ILL_ILLOPN;
1036 info._sifields._sigfault._addr = env->pc;
1037 queue_signal(env, info.si_signo, &info);
1038 break;
abf1172f
PM		 1039 case EXCP_STREX:
1040 if (!do_strex_a64(env)) {
1041 break;
1042 }
1043 /* fall through for segv */
1861c454 1044 case EXCP_PREFETCH_ABORT:
1861c454 1045 case EXCP_DATA_ABORT:
a86b3c64 1046 info.si_signo = TARGET_SIGSEGV;
1861c454
PM		 1047 info.si_errno = 0;
1048 /* XXX: check env->error_code */
1049 info.si_code = TARGET_SEGV_MAPERR;
686581ad 1050 info._sifields._sigfault._addr = env->exception.vaddress;
1861c454
PM		 1051 queue_signal(env, info.si_signo, &info);
1052 break;
1053 case EXCP_DEBUG:
1054 case EXCP_BKPT:
1055 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1056 if (sig) {
1057 info.si_signo = sig;
1058 info.si_errno = 0;
1059 info.si_code = TARGET_TRAP_BRKPT;
1060 queue_signal(env, info.si_signo, &info);
1061 }
1062 break;
1861c454
PM		 1063 default:
1064 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
1065 trapnr);
1066 cpu_dump_state(cs, stderr, fprintf, 0);
1067 abort();
1068 }
1069 process_pending_signals(env);
fa2ef212
MM		 1070 /* Exception return on AArch64 always clears the exclusive monitor,
1071 * so any return to running guest code implies this.
1072 * A strex (successful or otherwise) also clears the monitor, so
1073 * we don't need to specialcase EXCP_STREX.
1074 */
1075 env->exclusive_addr = -1;
1861c454
PM		 1076 }
1077}
1078#endif /* ndef TARGET_ABI32 */
1079
b346ff46 1080#endif
1b6b029e 1081
d2fbca94
GX		 1082#ifdef TARGET_UNICORE32
1083
05390248 1084void cpu_loop(CPUUniCore32State *env)
d2fbca94 1085{
0315c31c 1086 CPUState *cs = CPU(uc32_env_get_cpu(env));
d2fbca94
GX		 1087 int trapnr;
1088 unsigned int n, insn;
1089 target_siginfo_t info;
1090
1091 for (;;) {
0315c31c 1092 cpu_exec_start(cs);
d2fbca94 1093 trapnr = uc32_cpu_exec(env);
0315c31c 1094 cpu_exec_end(cs);
d2fbca94
GX		 1095 switch (trapnr) {
1096 case UC32_EXCP_PRIV:
1097 {
1098 /* system call */
1099 get_user_u32(insn, env->regs[31] - 4);
1100 n = insn & 0xffffff;
1101
1102 if (n >= UC32_SYSCALL_BASE) {
1103 /* linux syscall */
1104 n -= UC32_SYSCALL_BASE;
1105 if (n == UC32_SYSCALL_NR_set_tls) {
1106 cpu_set_tls(env, env->regs[0]);
1107 env->regs[0] = 0;
1108 } else {
1109 env->regs[0] = do_syscall(env,
1110 n,
1111 env->regs[0],
1112 env->regs[1],
1113 env->regs[2],
1114 env->regs[3],
1115 env->regs[4],
5945cfcb
PM		 1116 env->regs[5],
1117 0, 0);
d2fbca94
GX		 1118 }
1119 } else {
1120 goto error;
1121 }
1122 }
1123 break;
d48813dd
GX		 1124 case UC32_EXCP_DTRAP:
1125 case UC32_EXCP_ITRAP:
a86b3c64 1126 info.si_signo = TARGET_SIGSEGV;
d2fbca94
GX		 1127 info.si_errno = 0;
1128 /* XXX: check env->error_code */
1129 info.si_code = TARGET_SEGV_MAPERR;
1130 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1131 queue_signal(env, info.si_signo, &info);
1132 break;
1133 case EXCP_INTERRUPT:
1134 /* just indicate that signals should be handled asap */
1135 break;
1136 case EXCP_DEBUG:
1137 {
1138 int sig;
1139
db6b81d4 1140 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d2fbca94
GX		 1141 if (sig) {
1142 info.si_signo = sig;
1143 info.si_errno = 0;
1144 info.si_code = TARGET_TRAP_BRKPT;
1145 queue_signal(env, info.si_signo, &info);
1146 }
1147 }
1148 break;
1149 default:
1150 goto error;
1151 }
1152 process_pending_signals(env);
1153 }
1154
1155error:
1156 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
878096ee 1157 cpu_dump_state(cs, stderr, fprintf, 0);
d2fbca94
GX		 1158 abort();
1159}
1160#endif
1161
93ac68bc 1162#ifdef TARGET_SPARC
ed23fbd9 1163#define SPARC64_STACK_BIAS 2047
93ac68bc 1164
060366c5
FB		 1165//#define DEBUG_WIN
1166
2623cbaf
FB		 1167/* WARNING: dealing with register windows _is_ complicated. More info
1168 can be found at http://www.sics.se/~psm/sparcstack.html */
060366c5
FB		 1169static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1170{
1a14026e 1171 index = (index + cwp * 16) % (16 * env->nwindows);
060366c5
FB		 1172 /* wrap handling : if cwp is on the last window, then we use the
1173 registers 'after' the end */
1a14026e
BS		 1174 if (index < 8 && env->cwp == env->nwindows - 1)
1175 index += 16 * env->nwindows;
060366c5
FB		 1176 return index;
1177}
1178
2623cbaf
FB		 1179/* save the register window 'cwp1' */
1180static inline void save_window_offset(CPUSPARCState *env, int cwp1)
060366c5 1181{
2623cbaf 1182 unsigned int i;
992f48a0 1183 abi_ulong sp_ptr;
3b46e624 1184
53a5960a 1185 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1186#ifdef TARGET_SPARC64
1187 if (sp_ptr & 3)
1188 sp_ptr += SPARC64_STACK_BIAS;
1189#endif
060366c5 1190#if defined(DEBUG_WIN)
2daf0284
BS		 1191 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1192 sp_ptr, cwp1);
060366c5 1193#endif
2623cbaf 1194 for(i = 0; i < 16; i++) {
2f619698
FB		 1195 /* FIXME - what to do if put_user() fails? */
1196 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1197 sp_ptr += sizeof(abi_ulong);
2623cbaf 1198 }
060366c5
FB		 1199}
1200
1201static void save_window(CPUSPARCState *env)
1202{
5ef54116 1203#ifndef TARGET_SPARC64
2623cbaf 1204 unsigned int new_wim;
1a14026e
BS		 1205 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1206 ((1LL << env->nwindows) - 1);
1207 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
2623cbaf 1208 env->wim = new_wim;
5ef54116 1209#else
1a14026e 1210 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
5ef54116
FB		 1211 env->cansave++;
1212 env->canrestore--;
1213#endif
060366c5
FB		 1214}
1215
1216static void restore_window(CPUSPARCState *env)
1217{
eda52953
BS		 1218#ifndef TARGET_SPARC64
1219 unsigned int new_wim;
1220#endif
1221 unsigned int i, cwp1;
992f48a0 1222 abi_ulong sp_ptr;
3b46e624 1223
eda52953 1224#ifndef TARGET_SPARC64
1a14026e
BS		 1225 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1226 ((1LL << env->nwindows) - 1);
eda52953 1227#endif
3b46e624 1228
060366c5 1229 /* restore the invalid window */
1a14026e 1230 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
53a5960a 1231 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1232#ifdef TARGET_SPARC64
1233 if (sp_ptr & 3)
1234 sp_ptr += SPARC64_STACK_BIAS;
1235#endif
060366c5 1236#if defined(DEBUG_WIN)
2daf0284
BS		 1237 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1238 sp_ptr, cwp1);
060366c5 1239#endif
2623cbaf 1240 for(i = 0; i < 16; i++) {
2f619698
FB		 1241 /* FIXME - what to do if get_user() fails? */
1242 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1243 sp_ptr += sizeof(abi_ulong);
2623cbaf 1244 }
5ef54116
FB		 1245#ifdef TARGET_SPARC64
1246 env->canrestore++;
1a14026e
BS		 1247 if (env->cleanwin < env->nwindows - 1)
1248 env->cleanwin++;
5ef54116 1249 env->cansave--;
eda52953
BS		 1250#else
1251 env->wim = new_wim;
5ef54116 1252#endif
060366c5
FB		 1253}
1254
1255static void flush_windows(CPUSPARCState *env)
1256{
1257 int offset, cwp1;
2623cbaf
FB		 1258
1259 offset = 1;
060366c5
FB		 1260 for(;;) {
1261 /* if restore would invoke restore_window(), then we can stop */
1a14026e 1262 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
eda52953 1263#ifndef TARGET_SPARC64
060366c5
FB		 1264 if (env->wim & (1 << cwp1))
1265 break;
eda52953
BS		 1266#else
1267 if (env->canrestore == 0)
1268 break;
1269 env->cansave++;
1270 env->canrestore--;
1271#endif
2623cbaf 1272 save_window_offset(env, cwp1);
060366c5
FB		 1273 offset++;
1274 }
1a14026e 1275 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
eda52953
BS		 1276#ifndef TARGET_SPARC64
1277 /* set wim so that restore will reload the registers */
2623cbaf 1278 env->wim = 1 << cwp1;
eda52953 1279#endif
2623cbaf
FB		 1280#if defined(DEBUG_WIN)
1281 printf("flush_windows: nb=%d\n", offset - 1);
80a9d035 1282#endif
2623cbaf 1283}
060366c5 1284
93ac68bc
FB		 1285void cpu_loop (CPUSPARCState *env)
1286{
878096ee 1287 CPUState *cs = CPU(sparc_env_get_cpu(env));
2cc20260
RH		 1288 int trapnr;
1289 abi_long ret;
c227f099 1290 target_siginfo_t info;
3b46e624 1291
060366c5 1292 while (1) {
b040bc9c 1293 cpu_exec_start(cs);
060366c5 1294 trapnr = cpu_sparc_exec (env);
b040bc9c 1295 cpu_exec_end(cs);
3b46e624 1296
20132b96
RH		 1297 /* Compute PSR before exposing state. */
1298 if (env->cc_op != CC_OP_FLAGS) {
1299 cpu_get_psr(env);
1300 }
1301
060366c5 1302 switch (trapnr) {
5ef54116 1303#ifndef TARGET_SPARC64
5fafdf24 1304 case 0x88:
060366c5 1305 case 0x90:
5ef54116 1306#else
cb33da57 1307 case 0x110:
5ef54116
FB		 1308 case 0x16d:
1309#endif
060366c5 1310 ret = do_syscall (env, env->gregs[1],
5fafdf24
TS		 1311 env->regwptr[0], env->regwptr[1],
1312 env->regwptr[2], env->regwptr[3],
5945cfcb
PM		 1313 env->regwptr[4], env->regwptr[5],
1314 0, 0);
2cc20260 1315 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
992f48a0 1316#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1317 env->xcc |= PSR_CARRY;
1318#else
060366c5 1319 env->psr |= PSR_CARRY;
27908725 1320#endif
060366c5
FB		 1321 ret = -ret;
1322 } else {
992f48a0 1323#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1324 env->xcc &= ~PSR_CARRY;
1325#else
060366c5 1326 env->psr &= ~PSR_CARRY;
27908725 1327#endif
060366c5
FB		 1328 }
1329 env->regwptr[0] = ret;
1330 /* next instruction */
1331 env->pc = env->npc;
1332 env->npc = env->npc + 4;
1333 break;
1334 case 0x83: /* flush windows */
992f48a0
BS		 1335#ifdef TARGET_ABI32
1336 case 0x103:
1337#endif
2623cbaf 1338 flush_windows(env);
060366c5
FB		 1339 /* next instruction */
1340 env->pc = env->npc;
1341 env->npc = env->npc + 4;
1342 break;
3475187d 1343#ifndef TARGET_SPARC64
060366c5
FB		 1344 case TT_WIN_OVF: /* window overflow */
1345 save_window(env);
1346 break;
1347 case TT_WIN_UNF: /* window underflow */
1348 restore_window(env);
1349 break;
61ff6f58
FB		 1350 case TT_TFAULT:
1351 case TT_DFAULT:
1352 {
59f7182f 1353 info.si_signo = TARGET_SIGSEGV;
61ff6f58
FB		 1354 info.si_errno = 0;
1355 /* XXX: check env->error_code */
1356 info.si_code = TARGET_SEGV_MAPERR;
1357 info._sifields._sigfault._addr = env->mmuregs[4];
624f7979 1358 queue_signal(env, info.si_signo, &info);
61ff6f58
FB		 1359 }
1360 break;
3475187d 1361#else
5ef54116
FB		 1362 case TT_SPILL: /* window overflow */
1363 save_window(env);
1364 break;
1365 case TT_FILL: /* window underflow */
1366 restore_window(env);
1367 break;
7f84a729
BS		 1368 case TT_TFAULT:
1369 case TT_DFAULT:
1370 {
59f7182f 1371 info.si_signo = TARGET_SIGSEGV;
7f84a729
BS		 1372 info.si_errno = 0;
1373 /* XXX: check env->error_code */
1374 info.si_code = TARGET_SEGV_MAPERR;
1375 if (trapnr == TT_DFAULT)
1376 info._sifields._sigfault._addr = env->dmmuregs[4];
1377 else
8194f35a 1378 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
624f7979 1379 queue_signal(env, info.si_signo, &info);
7f84a729
BS		 1380 }
1381 break;
27524dc3 1382#ifndef TARGET_ABI32
5bfb56b2
BS		 1383 case 0x16e:
1384 flush_windows(env);
1385 sparc64_get_context(env);
1386 break;
1387 case 0x16f:
1388 flush_windows(env);
1389 sparc64_set_context(env);
1390 break;
27524dc3 1391#endif
3475187d 1392#endif
48dc41eb
FB		 1393 case EXCP_INTERRUPT:
1394 /* just indicate that signals should be handled asap */
1395 break;
75f22e4e
RH		 1396 case TT_ILL_INSN:
1397 {
1398 info.si_signo = TARGET_SIGILL;
1399 info.si_errno = 0;
1400 info.si_code = TARGET_ILL_ILLOPC;
1401 info._sifields._sigfault._addr = env->pc;
1402 queue_signal(env, info.si_signo, &info);
1403 }
1404 break;
1fddef4b
FB		 1405 case EXCP_DEBUG:
1406 {
1407 int sig;
1408
db6b81d4 1409 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 1410 if (sig)
1411 {
1412 info.si_signo = sig;
1413 info.si_errno = 0;
1414 info.si_code = TARGET_TRAP_BRKPT;
624f7979 1415 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 1416 }
1417 }
1418 break;
060366c5
FB		 1419 default:
1420 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 1421 cpu_dump_state(cs, stderr, fprintf, 0);
060366c5
FB		 1422 exit (1);
1423 }
1424 process_pending_signals (env);
1425 }
93ac68bc
FB		 1426}
1427
1428#endif
1429
67867308 1430#ifdef TARGET_PPC
05390248 1431static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
9fddaa0c
FB		 1432{
1433 /* TO FIX */
1434 return 0;
1435}
3b46e624 1436
05390248 1437uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
9fddaa0c 1438{
e3ea6529 1439 return cpu_ppc_get_tb(env);
9fddaa0c 1440}
3b46e624 1441
05390248 1442uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
9fddaa0c
FB		 1443{
1444 return cpu_ppc_get_tb(env) >> 32;
1445}
3b46e624 1446
05390248 1447uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
9fddaa0c 1448{
b711de95 1449 return cpu_ppc_get_tb(env);
9fddaa0c 1450}
5fafdf24 1451
05390248 1452uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
9fddaa0c 1453{
a062e36c 1454 return cpu_ppc_get_tb(env) >> 32;
9fddaa0c 1455}
76a66253 1456
05390248 1457uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
76a66253
JM		 1458__attribute__ (( alias ("cpu_ppc_load_tbu") ));
1459
05390248 1460uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
9fddaa0c 1461{
76a66253 1462 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
9fddaa0c 1463}
76a66253 1464
a750fc0b 1465/* XXX: to be fixed */
73b01960 1466int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
a750fc0b
JM		 1467{
1468 return -1;
1469}
1470
73b01960 1471int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
a750fc0b
JM		 1472{
1473 return -1;
1474}
1475
001faf32
BS		 1476#define EXCP_DUMP(env, fmt, ...) \
1477do { \
a0762859 1478 CPUState *cs = ENV_GET_CPU(env); \
001faf32 1479 fprintf(stderr, fmt , ## __VA_ARGS__); \
a0762859 1480 cpu_dump_state(cs, stderr, fprintf, 0); \
001faf32 1481 qemu_log(fmt, ## __VA_ARGS__); \
eeacee4d 1482 if (qemu_log_enabled()) { \
a0762859 1483 log_cpu_state(cs, 0); \
eeacee4d 1484 } \
e1833e1f
JM		 1485} while (0)
1486
56f066bb
NF		 1487static int do_store_exclusive(CPUPPCState *env)
1488{
1489 target_ulong addr;
1490 target_ulong page_addr;
e22c357b 1491 target_ulong val, val2 __attribute__((unused)) = 0;
56f066bb
NF		 1492 int flags;
1493 int segv = 0;
1494
1495 addr = env->reserve_ea;
1496 page_addr = addr & TARGET_PAGE_MASK;
1497 start_exclusive();
1498 mmap_lock();
1499 flags = page_get_flags(page_addr);
1500 if ((flags & PAGE_READ) == 0) {
1501 segv = 1;
1502 } else {
1503 int reg = env->reserve_info & 0x1f;
4b1daa72 1504 int size = env->reserve_info >> 5;
56f066bb
NF		 1505 int stored = 0;
1506
1507 if (addr == env->reserve_addr) {
1508 switch (size) {
1509 case 1: segv = get_user_u8(val, addr); break;
1510 case 2: segv = get_user_u16(val, addr); break;
1511 case 4: segv = get_user_u32(val, addr); break;
1512#if defined(TARGET_PPC64)
1513 case 8: segv = get_user_u64(val, addr); break;
27b95bfe
TM		 1514 case 16: {
1515 segv = get_user_u64(val, addr);
1516 if (!segv) {
1517 segv = get_user_u64(val2, addr + 8);
1518 }
1519 break;
1520 }
56f066bb
NF		 1521#endif
1522 default: abort();
1523 }
1524 if (!segv && val == env->reserve_val) {
1525 val = env->gpr[reg];
1526 switch (size) {
1527 case 1: segv = put_user_u8(val, addr); break;
1528 case 2: segv = put_user_u16(val, addr); break;
1529 case 4: segv = put_user_u32(val, addr); break;
1530#if defined(TARGET_PPC64)
1531 case 8: segv = put_user_u64(val, addr); break;
27b95bfe
TM		 1532 case 16: {
1533 if (val2 == env->reserve_val2) {
e22c357b
DK		 1534 if (msr_le) {
1535 val2 = val;
1536 val = env->gpr[reg+1];
1537 } else {
1538 val2 = env->gpr[reg+1];
1539 }
27b95bfe
TM		 1540 segv = put_user_u64(val, addr);
1541 if (!segv) {
1542 segv = put_user_u64(val2, addr + 8);
1543 }
1544 }
1545 break;
1546 }
56f066bb
NF		 1547#endif
1548 default: abort();
1549 }
1550 if (!segv) {
1551 stored = 1;
1552 }
1553 }
1554 }
1555 env->crf[0] = (stored << 1) | xer_so;
1556 env->reserve_addr = (target_ulong)-1;
1557 }
1558 if (!segv) {
1559 env->nip += 4;
1560 }
1561 mmap_unlock();
1562 end_exclusive();
1563 return segv;
1564}
1565
67867308
FB		 1566void cpu_loop(CPUPPCState *env)
1567{
0315c31c 1568 CPUState *cs = CPU(ppc_env_get_cpu(env));
c227f099 1569 target_siginfo_t info;
61190b14 1570 int trapnr;
9e0e2f96 1571 target_ulong ret;
3b46e624 1572
67867308 1573 for(;;) {
0315c31c 1574 cpu_exec_start(cs);
67867308 1575 trapnr = cpu_ppc_exec(env);
0315c31c 1576 cpu_exec_end(cs);
67867308 1577 switch(trapnr) {
e1833e1f
JM		 1578 case POWERPC_EXCP_NONE:
1579 /* Just go on */
67867308 1580 break;
e1833e1f 1581 case POWERPC_EXCP_CRITICAL: /* Critical input */
a47dddd7 1582 cpu_abort(cs, "Critical interrupt while in user mode. "
e1833e1f 1583 "Aborting\n");
61190b14 1584 break;
e1833e1f 1585 case POWERPC_EXCP_MCHECK: /* Machine check exception */
a47dddd7 1586 cpu_abort(cs, "Machine check exception while in user mode. "
e1833e1f
JM		 1587 "Aborting\n");
1588 break;
1589 case POWERPC_EXCP_DSI: /* Data storage exception */
90e189ec 1590 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
e1833e1f
JM		 1591 env->spr[SPR_DAR]);
1592 /* XXX: check this. Seems bugged */
2be0071f
FB		 1593 switch (env->error_code & 0xFF000000) {
1594 case 0x40000000:
61190b14
FB		 1595 info.si_signo = TARGET_SIGSEGV;
1596 info.si_errno = 0;
1597 info.si_code = TARGET_SEGV_MAPERR;
1598 break;
2be0071f 1599 case 0x04000000:
61190b14
FB		 1600 info.si_signo = TARGET_SIGILL;
1601 info.si_errno = 0;
1602 info.si_code = TARGET_ILL_ILLADR;
1603 break;
2be0071f 1604 case 0x08000000:
61190b14
FB		 1605 info.si_signo = TARGET_SIGSEGV;
1606 info.si_errno = 0;
1607 info.si_code = TARGET_SEGV_ACCERR;
1608 break;
61190b14
FB		 1609 default:
1610 /* Let's send a regular segfault... */
e1833e1f
JM		 1611 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1612 env->error_code);
61190b14
FB		 1613 info.si_signo = TARGET_SIGSEGV;
1614 info.si_errno = 0;
1615 info.si_code = TARGET_SEGV_MAPERR;
1616 break;
1617 }
67867308 1618 info._sifields._sigfault._addr = env->nip;
624f7979 1619 queue_signal(env, info.si_signo, &info);
67867308 1620 break;
e1833e1f 1621 case POWERPC_EXCP_ISI: /* Instruction storage exception */
90e189ec
BS		 1622 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1623 "\n", env->spr[SPR_SRR0]);
e1833e1f 1624 /* XXX: check this */
2be0071f
FB		 1625 switch (env->error_code & 0xFF000000) {
1626 case 0x40000000:
61190b14 1627 info.si_signo = TARGET_SIGSEGV;
67867308 1628 info.si_errno = 0;
61190b14
FB		 1629 info.si_code = TARGET_SEGV_MAPERR;
1630 break;
2be0071f
FB		 1631 case 0x10000000:
1632 case 0x08000000:
61190b14
FB		 1633 info.si_signo = TARGET_SIGSEGV;
1634 info.si_errno = 0;
1635 info.si_code = TARGET_SEGV_ACCERR;
1636 break;
1637 default:
1638 /* Let's send a regular segfault... */
e1833e1f
JM		 1639 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1640 env->error_code);
61190b14
FB		 1641 info.si_signo = TARGET_SIGSEGV;
1642 info.si_errno = 0;
1643 info.si_code = TARGET_SEGV_MAPERR;
1644 break;
1645 }
1646 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1647 queue_signal(env, info.si_signo, &info);
67867308 1648 break;
e1833e1f 1649 case POWERPC_EXCP_EXTERNAL: /* External input */
a47dddd7 1650 cpu_abort(cs, "External interrupt while in user mode. "
e1833e1f
JM		 1651 "Aborting\n");
1652 break;
1653 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1654 EXCP_DUMP(env, "Unaligned memory access\n");
1655 /* XXX: check this */
61190b14 1656 info.si_signo = TARGET_SIGBUS;
67867308 1657 info.si_errno = 0;
61190b14
FB		 1658 info.si_code = TARGET_BUS_ADRALN;
1659 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1660 queue_signal(env, info.si_signo, &info);
67867308 1661 break;
e1833e1f
JM		 1662 case POWERPC_EXCP_PROGRAM: /* Program exception */
1663 /* XXX: check this */
61190b14 1664 switch (env->error_code & ~0xF) {
e1833e1f
JM		 1665 case POWERPC_EXCP_FP:
1666 EXCP_DUMP(env, "Floating point program exception\n");
61190b14
FB		 1667 info.si_signo = TARGET_SIGFPE;
1668 info.si_errno = 0;
1669 switch (env->error_code & 0xF) {
e1833e1f 1670 case POWERPC_EXCP_FP_OX:
61190b14
FB		 1671 info.si_code = TARGET_FPE_FLTOVF;
1672 break;
e1833e1f 1673 case POWERPC_EXCP_FP_UX:
61190b14
FB		 1674 info.si_code = TARGET_FPE_FLTUND;
1675 break;
e1833e1f
JM		 1676 case POWERPC_EXCP_FP_ZX:
1677 case POWERPC_EXCP_FP_VXZDZ:
61190b14
FB		 1678 info.si_code = TARGET_FPE_FLTDIV;
1679 break;
e1833e1f 1680 case POWERPC_EXCP_FP_XX:
61190b14
FB		 1681 info.si_code = TARGET_FPE_FLTRES;
1682 break;
e1833e1f 1683 case POWERPC_EXCP_FP_VXSOFT:
61190b14
FB		 1684 info.si_code = TARGET_FPE_FLTINV;
1685 break;
7c58044c 1686 case POWERPC_EXCP_FP_VXSNAN:
e1833e1f
JM		 1687 case POWERPC_EXCP_FP_VXISI:
1688 case POWERPC_EXCP_FP_VXIDI:
1689 case POWERPC_EXCP_FP_VXIMZ:
1690 case POWERPC_EXCP_FP_VXVC:
1691 case POWERPC_EXCP_FP_VXSQRT:
1692 case POWERPC_EXCP_FP_VXCVI:
61190b14
FB		 1693 info.si_code = TARGET_FPE_FLTSUB;
1694 break;
1695 default:
e1833e1f
JM		 1696 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1697 env->error_code);
1698 break;
61190b14 1699 }
e1833e1f
JM		 1700 break;
1701 case POWERPC_EXCP_INVAL:
1702 EXCP_DUMP(env, "Invalid instruction\n");
61190b14
FB		 1703 info.si_signo = TARGET_SIGILL;
1704 info.si_errno = 0;
1705 switch (env->error_code & 0xF) {
e1833e1f 1706 case POWERPC_EXCP_INVAL_INVAL:
61190b14
FB		 1707 info.si_code = TARGET_ILL_ILLOPC;
1708 break;
e1833e1f 1709 case POWERPC_EXCP_INVAL_LSWX:
a750fc0b 1710 info.si_code = TARGET_ILL_ILLOPN;
61190b14 1711 break;
e1833e1f 1712 case POWERPC_EXCP_INVAL_SPR:
61190b14
FB		 1713 info.si_code = TARGET_ILL_PRVREG;
1714 break;
e1833e1f 1715 case POWERPC_EXCP_INVAL_FP:
61190b14
FB		 1716 info.si_code = TARGET_ILL_COPROC;
1717 break;
1718 default:
e1833e1f
JM		 1719 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1720 env->error_code & 0xF);
61190b14
FB		 1721 info.si_code = TARGET_ILL_ILLADR;
1722 break;
1723 }
1724 break;
e1833e1f
JM		 1725 case POWERPC_EXCP_PRIV:
1726 EXCP_DUMP(env, "Privilege violation\n");
61190b14
FB		 1727 info.si_signo = TARGET_SIGILL;
1728 info.si_errno = 0;
1729 switch (env->error_code & 0xF) {
e1833e1f 1730 case POWERPC_EXCP_PRIV_OPC:
61190b14
FB		 1731 info.si_code = TARGET_ILL_PRVOPC;
1732 break;
e1833e1f 1733 case POWERPC_EXCP_PRIV_REG:
61190b14 1734 info.si_code = TARGET_ILL_PRVREG;
e1833e1f 1735 break;
61190b14 1736 default:
e1833e1f
JM		 1737 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1738 env->error_code & 0xF);
61190b14
FB		 1739 info.si_code = TARGET_ILL_PRVOPC;
1740 break;
1741 }
1742 break;
e1833e1f 1743 case POWERPC_EXCP_TRAP:
a47dddd7 1744 cpu_abort(cs, "Tried to call a TRAP\n");
e1833e1f 1745 break;
61190b14
FB		 1746 default:
1747 /* Should not happen ! */
a47dddd7 1748 cpu_abort(cs, "Unknown program exception (%02x)\n",
e1833e1f
JM		 1749 env->error_code);
1750 break;
61190b14
FB		 1751 }
1752 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1753 queue_signal(env, info.si_signo, &info);
67867308 1754 break;
e1833e1f
JM		 1755 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1756 EXCP_DUMP(env, "No floating point allowed\n");
61190b14 1757 info.si_signo = TARGET_SIGILL;
67867308 1758 info.si_errno = 0;
61190b14
FB		 1759 info.si_code = TARGET_ILL_COPROC;
1760 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1761 queue_signal(env, info.si_signo, &info);
67867308 1762 break;
e1833e1f 1763 case POWERPC_EXCP_SYSCALL: /* System call exception */
a47dddd7 1764 cpu_abort(cs, "Syscall exception while in user mode. "
e1833e1f 1765 "Aborting\n");
61190b14 1766 break;
e1833e1f
JM		 1767 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1768 EXCP_DUMP(env, "No APU instruction allowed\n");
1769 info.si_signo = TARGET_SIGILL;
1770 info.si_errno = 0;
1771 info.si_code = TARGET_ILL_COPROC;
1772 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1773 queue_signal(env, info.si_signo, &info);
61190b14 1774 break;
e1833e1f 1775 case POWERPC_EXCP_DECR: /* Decrementer exception */
a47dddd7 1776 cpu_abort(cs, "Decrementer interrupt while in user mode. "
e1833e1f 1777 "Aborting\n");
61190b14 1778 break;
e1833e1f 1779 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
a47dddd7 1780 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
e1833e1f
JM		 1781 "Aborting\n");
1782 break;
1783 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
a47dddd7 1784 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
e1833e1f
JM		 1785 "Aborting\n");
1786 break;
1787 case POWERPC_EXCP_DTLB: /* Data TLB error */
a47dddd7 1788 cpu_abort(cs, "Data TLB exception while in user mode. "
e1833e1f
JM		 1789 "Aborting\n");
1790 break;
1791 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
a47dddd7 1792 cpu_abort(cs, "Instruction TLB exception while in user mode. "
e1833e1f
JM		 1793 "Aborting\n");
1794 break;
e1833e1f
JM		 1795 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1796 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1797 info.si_signo = TARGET_SIGILL;
1798 info.si_errno = 0;
1799 info.si_code = TARGET_ILL_COPROC;
1800 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1801 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1802 break;
1803 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
a47dddd7 1804 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
e1833e1f
JM		 1805 break;
1806 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
a47dddd7 1807 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
e1833e1f
JM		 1808 break;
1809 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
a47dddd7 1810 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1811 break;
1812 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
a47dddd7 1813 cpu_abort(cs, "Doorbell interrupt while in user mode. "
e1833e1f
JM		 1814 "Aborting\n");
1815 break;
1816 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
a47dddd7 1817 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
e1833e1f
JM		 1818 "Aborting\n");
1819 break;
1820 case POWERPC_EXCP_RESET: /* System reset exception */
a47dddd7 1821 cpu_abort(cs, "Reset interrupt while in user mode. "
e1833e1f
JM		 1822 "Aborting\n");
1823 break;
e1833e1f 1824 case POWERPC_EXCP_DSEG: /* Data segment exception */
a47dddd7 1825 cpu_abort(cs, "Data segment exception while in user mode. "
e1833e1f
JM		 1826 "Aborting\n");
1827 break;
1828 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
a47dddd7 1829 cpu_abort(cs, "Instruction segment exception "
e1833e1f
JM		 1830 "while in user mode. Aborting\n");
1831 break;
e85e7c6e 1832 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1833 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
a47dddd7 1834 cpu_abort(cs, "Hypervisor decrementer interrupt "
e1833e1f
JM		 1835 "while in user mode. Aborting\n");
1836 break;
e1833e1f
JM		 1837 case POWERPC_EXCP_TRACE: /* Trace exception */
1838 /* Nothing to do:
1839 * we use this exception to emulate step-by-step execution mode.
1840 */
1841 break;
e85e7c6e 1842 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1843 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
a47dddd7 1844 cpu_abort(cs, "Hypervisor data storage exception "
e1833e1f
JM		 1845 "while in user mode. Aborting\n");
1846 break;
1847 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
a47dddd7 1848 cpu_abort(cs, "Hypervisor instruction storage exception "
e1833e1f
JM		 1849 "while in user mode. Aborting\n");
1850 break;
1851 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
a47dddd7 1852 cpu_abort(cs, "Hypervisor data segment exception "
e1833e1f
JM		 1853 "while in user mode. Aborting\n");
1854 break;
1855 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
a47dddd7 1856 cpu_abort(cs, "Hypervisor instruction segment exception "
e1833e1f
JM		 1857 "while in user mode. Aborting\n");
1858 break;
e1833e1f
JM		 1859 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1860 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1861 info.si_signo = TARGET_SIGILL;
1862 info.si_errno = 0;
1863 info.si_code = TARGET_ILL_COPROC;
1864 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1865 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1866 break;
1867 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
a47dddd7 1868 cpu_abort(cs, "Programmable interval timer interrupt "
e1833e1f
JM		 1869 "while in user mode. Aborting\n");
1870 break;
1871 case POWERPC_EXCP_IO: /* IO error exception */
a47dddd7 1872 cpu_abort(cs, "IO error exception while in user mode. "
e1833e1f
JM		 1873 "Aborting\n");
1874 break;
1875 case POWERPC_EXCP_RUNM: /* Run mode exception */
a47dddd7 1876 cpu_abort(cs, "Run mode exception while in user mode. "
e1833e1f
JM		 1877 "Aborting\n");
1878 break;
1879 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
a47dddd7 1880 cpu_abort(cs, "Emulation trap exception not handled\n");
e1833e1f
JM		 1881 break;
1882 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
a47dddd7 1883 cpu_abort(cs, "Instruction fetch TLB exception "
e1833e1f
JM		 1884 "while in user-mode. Aborting");
1885 break;
1886 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
a47dddd7 1887 cpu_abort(cs, "Data load TLB exception while in user-mode. "
e1833e1f
JM		 1888 "Aborting");
1889 break;
1890 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
a47dddd7 1891 cpu_abort(cs, "Data store TLB exception while in user-mode. "
e1833e1f
JM		 1892 "Aborting");
1893 break;
1894 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
a47dddd7 1895 cpu_abort(cs, "Floating-point assist exception not handled\n");
e1833e1f
JM		 1896 break;
1897 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
a47dddd7 1898 cpu_abort(cs, "Instruction address breakpoint exception "
e1833e1f
JM		 1899 "not handled\n");
1900 break;
1901 case POWERPC_EXCP_SMI: /* System management interrupt */
a47dddd7 1902 cpu_abort(cs, "System management interrupt while in user mode. "
e1833e1f
JM		 1903 "Aborting\n");
1904 break;
1905 case POWERPC_EXCP_THERM: /* Thermal interrupt */
a47dddd7 1906 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
e1833e1f
JM		 1907 "Aborting\n");
1908 break;
1909 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
a47dddd7 1910 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1911 break;
1912 case POWERPC_EXCP_VPUA: /* Vector assist exception */
a47dddd7 1913 cpu_abort(cs, "Vector assist exception not handled\n");
e1833e1f
JM		 1914 break;
1915 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
a47dddd7 1916 cpu_abort(cs, "Soft patch exception not handled\n");
e1833e1f
JM		 1917 break;
1918 case POWERPC_EXCP_MAINT: /* Maintenance exception */
a47dddd7 1919 cpu_abort(cs, "Maintenance exception while in user mode. "
e1833e1f
JM		 1920 "Aborting\n");
1921 break;
1922 case POWERPC_EXCP_STOP: /* stop translation */
1923 /* We did invalidate the instruction cache. Go on */
1924 break;
1925 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1926 /* We just stopped because of a branch. Go on */
1927 break;
1928 case POWERPC_EXCP_SYSCALL_USER:
1929 /* system call in user-mode emulation */
1930 /* WARNING:
1931 * PPC ABI uses overflow flag in cr0 to signal an error
1932 * in syscalls.
1933 */
e1833e1f
JM		 1934 env->crf[0] &= ~0x1;
1935 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1936 env->gpr[5], env->gpr[6], env->gpr[7],
5945cfcb 1937 env->gpr[8], 0, 0);
9e0e2f96 1938 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
bcd4933a
NF		 1939 /* Returning from a successful sigreturn syscall.
1940 Avoid corrupting register state. */
1941 break;
1942 }
9e0e2f96 1943 if (ret > (target_ulong)(-515)) {
e1833e1f
JM		 1944 env->crf[0] |= 0x1;
1945 ret = -ret;
61190b14 1946 }
e1833e1f 1947 env->gpr[3] = ret;
e1833e1f 1948 break;
56f066bb
NF		 1949 case POWERPC_EXCP_STCX:
1950 if (do_store_exclusive(env)) {
1951 info.si_signo = TARGET_SIGSEGV;
1952 info.si_errno = 0;
1953 info.si_code = TARGET_SEGV_MAPERR;
1954 info._sifields._sigfault._addr = env->nip;
1955 queue_signal(env, info.si_signo, &info);
1956 }
1957 break;
71f75756
AJ		 1958 case EXCP_DEBUG:
1959 {
1960 int sig;
1961
db6b81d4 1962 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
71f75756
AJ		 1963 if (sig) {
1964 info.si_signo = sig;
1965 info.si_errno = 0;
1966 info.si_code = TARGET_TRAP_BRKPT;
1967 queue_signal(env, info.si_signo, &info);
1968 }
1969 }
1970 break;
56ba31ff
JM		 1971 case EXCP_INTERRUPT:
1972 /* just indicate that signals should be handled asap */
1973 break;
e1833e1f 1974 default:
a47dddd7 1975 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
e1833e1f 1976 break;
67867308
FB		 1977 }
1978 process_pending_signals(env);
1979 }
1980}
1981#endif
1982
048f6b4d
FB		 1983#ifdef TARGET_MIPS
1984
ff4f7382
RH		 1985# ifdef TARGET_ABI_MIPSO32
1986# define MIPS_SYS(name, args) args,
048f6b4d 1987static const uint8_t mips_syscall_args[] = {
29fb0f25 1988 MIPS_SYS(sys_syscall , 8) /* 4000 */
048f6b4d
FB		 1989 MIPS_SYS(sys_exit , 1)
1990 MIPS_SYS(sys_fork , 0)
1991 MIPS_SYS(sys_read , 3)
1992 MIPS_SYS(sys_write , 3)
1993 MIPS_SYS(sys_open , 3) /* 4005 */
1994 MIPS_SYS(sys_close , 1)
1995 MIPS_SYS(sys_waitpid , 3)
1996 MIPS_SYS(sys_creat , 2)
1997 MIPS_SYS(sys_link , 2)
1998 MIPS_SYS(sys_unlink , 1) /* 4010 */
1999 MIPS_SYS(sys_execve , 0)
2000 MIPS_SYS(sys_chdir , 1)
2001 MIPS_SYS(sys_time , 1)
2002 MIPS_SYS(sys_mknod , 3)
2003 MIPS_SYS(sys_chmod , 2) /* 4015 */
2004 MIPS_SYS(sys_lchown , 3)
2005 MIPS_SYS(sys_ni_syscall , 0)
2006 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2007 MIPS_SYS(sys_lseek , 3)
2008 MIPS_SYS(sys_getpid , 0) /* 4020 */
2009 MIPS_SYS(sys_mount , 5)
868e34d7 2010 MIPS_SYS(sys_umount , 1)
048f6b4d
FB		 2011 MIPS_SYS(sys_setuid , 1)
2012 MIPS_SYS(sys_getuid , 0)
2013 MIPS_SYS(sys_stime , 1) /* 4025 */
2014 MIPS_SYS(sys_ptrace , 4)
2015 MIPS_SYS(sys_alarm , 1)
2016 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2017 MIPS_SYS(sys_pause , 0)
2018 MIPS_SYS(sys_utime , 2) /* 4030 */
2019 MIPS_SYS(sys_ni_syscall , 0)
2020 MIPS_SYS(sys_ni_syscall , 0)
2021 MIPS_SYS(sys_access , 2)
2022 MIPS_SYS(sys_nice , 1)
2023 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2024 MIPS_SYS(sys_sync , 0)
2025 MIPS_SYS(sys_kill , 2)
2026 MIPS_SYS(sys_rename , 2)
2027 MIPS_SYS(sys_mkdir , 2)
2028 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2029 MIPS_SYS(sys_dup , 1)
2030 MIPS_SYS(sys_pipe , 0)
2031 MIPS_SYS(sys_times , 1)
2032 MIPS_SYS(sys_ni_syscall , 0)
2033 MIPS_SYS(sys_brk , 1) /* 4045 */
2034 MIPS_SYS(sys_setgid , 1)
2035 MIPS_SYS(sys_getgid , 0)
2036 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2037 MIPS_SYS(sys_geteuid , 0)
2038 MIPS_SYS(sys_getegid , 0) /* 4050 */
2039 MIPS_SYS(sys_acct , 0)
868e34d7 2040 MIPS_SYS(sys_umount2 , 2)
048f6b4d
FB		 2041 MIPS_SYS(sys_ni_syscall , 0)
2042 MIPS_SYS(sys_ioctl , 3)
2043 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2044 MIPS_SYS(sys_ni_syscall , 2)
2045 MIPS_SYS(sys_setpgid , 2)
2046 MIPS_SYS(sys_ni_syscall , 0)
2047 MIPS_SYS(sys_olduname , 1)
2048 MIPS_SYS(sys_umask , 1) /* 4060 */
2049 MIPS_SYS(sys_chroot , 1)
2050 MIPS_SYS(sys_ustat , 2)
2051 MIPS_SYS(sys_dup2 , 2)
2052 MIPS_SYS(sys_getppid , 0)
2053 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2054 MIPS_SYS(sys_setsid , 0)
2055 MIPS_SYS(sys_sigaction , 3)
2056 MIPS_SYS(sys_sgetmask , 0)
2057 MIPS_SYS(sys_ssetmask , 1)
2058 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2059 MIPS_SYS(sys_setregid , 2)
2060 MIPS_SYS(sys_sigsuspend , 0)
2061 MIPS_SYS(sys_sigpending , 1)
2062 MIPS_SYS(sys_sethostname , 2)
2063 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2064 MIPS_SYS(sys_getrlimit , 2)
2065 MIPS_SYS(sys_getrusage , 2)
2066 MIPS_SYS(sys_gettimeofday, 2)
2067 MIPS_SYS(sys_settimeofday, 2)
2068 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2069 MIPS_SYS(sys_setgroups , 2)
2070 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2071 MIPS_SYS(sys_symlink , 2)
2072 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2073 MIPS_SYS(sys_readlink , 3) /* 4085 */
2074 MIPS_SYS(sys_uselib , 1)
2075 MIPS_SYS(sys_swapon , 2)
2076 MIPS_SYS(sys_reboot , 3)
2077 MIPS_SYS(old_readdir , 3)
2078 MIPS_SYS(old_mmap , 6) /* 4090 */
2079 MIPS_SYS(sys_munmap , 2)
2080 MIPS_SYS(sys_truncate , 2)
2081 MIPS_SYS(sys_ftruncate , 2)
2082 MIPS_SYS(sys_fchmod , 2)
2083 MIPS_SYS(sys_fchown , 3) /* 4095 */
2084 MIPS_SYS(sys_getpriority , 2)
2085 MIPS_SYS(sys_setpriority , 3)
2086 MIPS_SYS(sys_ni_syscall , 0)
2087 MIPS_SYS(sys_statfs , 2)
2088 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2089 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2090 MIPS_SYS(sys_socketcall , 2)
2091 MIPS_SYS(sys_syslog , 3)
2092 MIPS_SYS(sys_setitimer , 3)
2093 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2094 MIPS_SYS(sys_newstat , 2)
2095 MIPS_SYS(sys_newlstat , 2)
2096 MIPS_SYS(sys_newfstat , 2)
2097 MIPS_SYS(sys_uname , 1)
2098 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2099 MIPS_SYS(sys_vhangup , 0)
2100 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2101 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2102 MIPS_SYS(sys_wait4 , 4)
2103 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2104 MIPS_SYS(sys_sysinfo , 1)
2105 MIPS_SYS(sys_ipc , 6)
2106 MIPS_SYS(sys_fsync , 1)
2107 MIPS_SYS(sys_sigreturn , 0)
18113962 2108 MIPS_SYS(sys_clone , 6) /* 4120 */
048f6b4d
FB		 2109 MIPS_SYS(sys_setdomainname, 2)
2110 MIPS_SYS(sys_newuname , 1)
2111 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2112 MIPS_SYS(sys_adjtimex , 1)
2113 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2114 MIPS_SYS(sys_sigprocmask , 3)
2115 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2116 MIPS_SYS(sys_init_module , 5)
2117 MIPS_SYS(sys_delete_module, 1)
2118 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2119 MIPS_SYS(sys_quotactl , 0)
2120 MIPS_SYS(sys_getpgid , 1)
2121 MIPS_SYS(sys_fchdir , 1)
2122 MIPS_SYS(sys_bdflush , 2)
2123 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2124 MIPS_SYS(sys_personality , 1)
2125 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2126 MIPS_SYS(sys_setfsuid , 1)
2127 MIPS_SYS(sys_setfsgid , 1)
2128 MIPS_SYS(sys_llseek , 5) /* 4140 */
2129 MIPS_SYS(sys_getdents , 3)
2130 MIPS_SYS(sys_select , 5)
2131 MIPS_SYS(sys_flock , 2)
2132 MIPS_SYS(sys_msync , 3)
2133 MIPS_SYS(sys_readv , 3) /* 4145 */
2134 MIPS_SYS(sys_writev , 3)
2135 MIPS_SYS(sys_cacheflush , 3)
2136 MIPS_SYS(sys_cachectl , 3)
2137 MIPS_SYS(sys_sysmips , 4)
2138 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2139 MIPS_SYS(sys_getsid , 1)
2140 MIPS_SYS(sys_fdatasync , 0)
2141 MIPS_SYS(sys_sysctl , 1)
2142 MIPS_SYS(sys_mlock , 2)
2143 MIPS_SYS(sys_munlock , 2) /* 4155 */
2144 MIPS_SYS(sys_mlockall , 1)
2145 MIPS_SYS(sys_munlockall , 0)
2146 MIPS_SYS(sys_sched_setparam, 2)
2147 MIPS_SYS(sys_sched_getparam, 2)
2148 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2149 MIPS_SYS(sys_sched_getscheduler, 1)
2150 MIPS_SYS(sys_sched_yield , 0)
2151 MIPS_SYS(sys_sched_get_priority_max, 1)
2152 MIPS_SYS(sys_sched_get_priority_min, 1)
2153 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2154 MIPS_SYS(sys_nanosleep, 2)
b0932e06 2155 MIPS_SYS(sys_mremap , 5)
048f6b4d
FB		 2156 MIPS_SYS(sys_accept , 3)
2157 MIPS_SYS(sys_bind , 3)
2158 MIPS_SYS(sys_connect , 3) /* 4170 */
2159 MIPS_SYS(sys_getpeername , 3)
2160 MIPS_SYS(sys_getsockname , 3)
2161 MIPS_SYS(sys_getsockopt , 5)
2162 MIPS_SYS(sys_listen , 2)
2163 MIPS_SYS(sys_recv , 4) /* 4175 */
2164 MIPS_SYS(sys_recvfrom , 6)
2165 MIPS_SYS(sys_recvmsg , 3)
2166 MIPS_SYS(sys_send , 4)
2167 MIPS_SYS(sys_sendmsg , 3)
2168 MIPS_SYS(sys_sendto , 6) /* 4180 */
2169 MIPS_SYS(sys_setsockopt , 5)
2170 MIPS_SYS(sys_shutdown , 2)
2171 MIPS_SYS(sys_socket , 3)
2172 MIPS_SYS(sys_socketpair , 4)
2173 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2174 MIPS_SYS(sys_getresuid , 3)
2175 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2176 MIPS_SYS(sys_poll , 3)
2177 MIPS_SYS(sys_nfsservctl , 3)
2178 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2179 MIPS_SYS(sys_getresgid , 3)
2180 MIPS_SYS(sys_prctl , 5)
2181 MIPS_SYS(sys_rt_sigreturn, 0)
2182 MIPS_SYS(sys_rt_sigaction, 4)
2183 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2184 MIPS_SYS(sys_rt_sigpending, 2)
2185 MIPS_SYS(sys_rt_sigtimedwait, 4)
2186 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2187 MIPS_SYS(sys_rt_sigsuspend, 0)
2188 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2189 MIPS_SYS(sys_pwrite64 , 6)
2190 MIPS_SYS(sys_chown , 3)
2191 MIPS_SYS(sys_getcwd , 2)
2192 MIPS_SYS(sys_capget , 2)
2193 MIPS_SYS(sys_capset , 2) /* 4205 */
053ebb27 2194 MIPS_SYS(sys_sigaltstack , 2)
048f6b4d
FB		 2195 MIPS_SYS(sys_sendfile , 4)
2196 MIPS_SYS(sys_ni_syscall , 0)
2197 MIPS_SYS(sys_ni_syscall , 0)
2198 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2199 MIPS_SYS(sys_truncate64 , 4)
2200 MIPS_SYS(sys_ftruncate64 , 4)
2201 MIPS_SYS(sys_stat64 , 2)
2202 MIPS_SYS(sys_lstat64 , 2)
2203 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2204 MIPS_SYS(sys_pivot_root , 2)
2205 MIPS_SYS(sys_mincore , 3)
2206 MIPS_SYS(sys_madvise , 3)
2207 MIPS_SYS(sys_getdents64 , 3)
2208 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2209 MIPS_SYS(sys_ni_syscall , 0)
2210 MIPS_SYS(sys_gettid , 0)
2211 MIPS_SYS(sys_readahead , 5)
2212 MIPS_SYS(sys_setxattr , 5)
2213 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2214 MIPS_SYS(sys_fsetxattr , 5)
2215 MIPS_SYS(sys_getxattr , 4)
2216 MIPS_SYS(sys_lgetxattr , 4)
2217 MIPS_SYS(sys_fgetxattr , 4)
2218 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2219 MIPS_SYS(sys_llistxattr , 3)
2220 MIPS_SYS(sys_flistxattr , 3)
2221 MIPS_SYS(sys_removexattr , 2)
2222 MIPS_SYS(sys_lremovexattr, 2)
2223 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2224 MIPS_SYS(sys_tkill , 2)
2225 MIPS_SYS(sys_sendfile64 , 5)
43be1343 2226 MIPS_SYS(sys_futex , 6)
048f6b4d
FB		 2227 MIPS_SYS(sys_sched_setaffinity, 3)
2228 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2229 MIPS_SYS(sys_io_setup , 2)
2230 MIPS_SYS(sys_io_destroy , 1)
2231 MIPS_SYS(sys_io_getevents, 5)
2232 MIPS_SYS(sys_io_submit , 3)
2233 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2234 MIPS_SYS(sys_exit_group , 1)
2235 MIPS_SYS(sys_lookup_dcookie, 3)
2236 MIPS_SYS(sys_epoll_create, 1)
2237 MIPS_SYS(sys_epoll_ctl , 4)
2238 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2239 MIPS_SYS(sys_remap_file_pages, 5)
2240 MIPS_SYS(sys_set_tid_address, 1)
2241 MIPS_SYS(sys_restart_syscall, 0)
2242 MIPS_SYS(sys_fadvise64_64, 7)
2243 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2244 MIPS_SYS(sys_fstatfs64 , 2)
2245 MIPS_SYS(sys_timer_create, 3)
2246 MIPS_SYS(sys_timer_settime, 4)
2247 MIPS_SYS(sys_timer_gettime, 2)
2248 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2249 MIPS_SYS(sys_timer_delete, 1)
2250 MIPS_SYS(sys_clock_settime, 2)
2251 MIPS_SYS(sys_clock_gettime, 2)
2252 MIPS_SYS(sys_clock_getres, 2)
2253 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2254 MIPS_SYS(sys_tgkill , 3)
2255 MIPS_SYS(sys_utimes , 2)
2256 MIPS_SYS(sys_mbind , 4)
2257 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2258 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2259 MIPS_SYS(sys_mq_open , 4)
2260 MIPS_SYS(sys_mq_unlink , 1)
2261 MIPS_SYS(sys_mq_timedsend, 5)
2262 MIPS_SYS(sys_mq_timedreceive, 5)
2263 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2264 MIPS_SYS(sys_mq_getsetattr, 3)
2265 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2266 MIPS_SYS(sys_waitid , 4)
2267 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2268 MIPS_SYS(sys_add_key , 5)
388bb21a 2269 MIPS_SYS(sys_request_key, 4)
048f6b4d 2270 MIPS_SYS(sys_keyctl , 5)
6f5b89a0 2271 MIPS_SYS(sys_set_thread_area, 1)
388bb21a
TS		 2272 MIPS_SYS(sys_inotify_init, 0)
2273 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2274 MIPS_SYS(sys_inotify_rm_watch, 2)
2275 MIPS_SYS(sys_migrate_pages, 4)
2276 MIPS_SYS(sys_openat, 4)
2277 MIPS_SYS(sys_mkdirat, 3)
2278 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2279 MIPS_SYS(sys_fchownat, 5)
2280 MIPS_SYS(sys_futimesat, 3)
2281 MIPS_SYS(sys_fstatat64, 4)
2282 MIPS_SYS(sys_unlinkat, 3)
2283 MIPS_SYS(sys_renameat, 4) /* 4295 */
2284 MIPS_SYS(sys_linkat, 5)
2285 MIPS_SYS(sys_symlinkat, 3)
2286 MIPS_SYS(sys_readlinkat, 4)
2287 MIPS_SYS(sys_fchmodat, 3)
2288 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2289 MIPS_SYS(sys_pselect6, 6)
2290 MIPS_SYS(sys_ppoll, 5)
2291 MIPS_SYS(sys_unshare, 1)
b0932e06 2292 MIPS_SYS(sys_splice, 6)
388bb21a
TS		 2293 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2294 MIPS_SYS(sys_tee, 4)
2295 MIPS_SYS(sys_vmsplice, 4)
2296 MIPS_SYS(sys_move_pages, 6)
2297 MIPS_SYS(sys_set_robust_list, 2)
2298 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2299 MIPS_SYS(sys_kexec_load, 4)
2300 MIPS_SYS(sys_getcpu, 3)
2301 MIPS_SYS(sys_epoll_pwait, 6)
2302 MIPS_SYS(sys_ioprio_set, 3)
2303 MIPS_SYS(sys_ioprio_get, 2)
d979e8eb
PM		 2304 MIPS_SYS(sys_utimensat, 4)
2305 MIPS_SYS(sys_signalfd, 3)
2306 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2307 MIPS_SYS(sys_eventfd, 1)
2308 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2309 MIPS_SYS(sys_timerfd_create, 2)
2310 MIPS_SYS(sys_timerfd_gettime, 2)
2311 MIPS_SYS(sys_timerfd_settime, 4)
2312 MIPS_SYS(sys_signalfd4, 4)
2313 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2314 MIPS_SYS(sys_epoll_create1, 1)
2315 MIPS_SYS(sys_dup3, 3)
2316 MIPS_SYS(sys_pipe2, 2)
2317 MIPS_SYS(sys_inotify_init1, 1)
2318 MIPS_SYS(sys_preadv, 6) /* 4330 */
2319 MIPS_SYS(sys_pwritev, 6)
2320 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2321 MIPS_SYS(sys_perf_event_open, 5)
2322 MIPS_SYS(sys_accept4, 4)
2323 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2324 MIPS_SYS(sys_fanotify_init, 2)
2325 MIPS_SYS(sys_fanotify_mark, 6)
2326 MIPS_SYS(sys_prlimit64, 4)
2327 MIPS_SYS(sys_name_to_handle_at, 5)
2328 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2329 MIPS_SYS(sys_clock_adjtime, 2)
2330 MIPS_SYS(sys_syncfs, 1)
048f6b4d 2331};
ff4f7382
RH		 2332# undef MIPS_SYS
2333# endif /* O32 */
048f6b4d 2334
590bc601
PB		 2335static int do_store_exclusive(CPUMIPSState *env)
2336{
2337 target_ulong addr;
2338 target_ulong page_addr;
2339 target_ulong val;
2340 int flags;
2341 int segv = 0;
2342 int reg;
2343 int d;
2344
5499b6ff 2345 addr = env->lladdr;
590bc601
PB		 2346 page_addr = addr & TARGET_PAGE_MASK;
2347 start_exclusive();
2348 mmap_lock();
2349 flags = page_get_flags(page_addr);
2350 if ((flags & PAGE_READ) == 0) {
2351 segv = 1;
2352 } else {
2353 reg = env->llreg & 0x1f;
2354 d = (env->llreg & 0x20) != 0;
2355 if (d) {
2356 segv = get_user_s64(val, addr);
2357 } else {
2358 segv = get_user_s32(val, addr);
2359 }
2360 if (!segv) {
2361 if (val != env->llval) {
2362 env->active_tc.gpr[reg] = 0;
2363 } else {
2364 if (d) {
2365 segv = put_user_u64(env->llnewval, addr);
2366 } else {
2367 segv = put_user_u32(env->llnewval, addr);
2368 }
2369 if (!segv) {
2370 env->active_tc.gpr[reg] = 1;
2371 }
2372 }
2373 }
2374 }
5499b6ff 2375 env->lladdr = -1;
590bc601
PB		 2376 if (!segv) {
2377 env->active_tc.PC += 4;
2378 }
2379 mmap_unlock();
2380 end_exclusive();
2381 return segv;
2382}
2383
54b2f42c
MI		 2384/* Break codes */
2385enum {
2386 BRK_OVERFLOW = 6,
2387 BRK_DIVZERO = 7
2388};
2389
2390static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2391 unsigned int code)
2392{
2393 int ret = -1;
2394
2395 switch (code) {
2396 case BRK_OVERFLOW:
2397 case BRK_DIVZERO:
2398 info->si_signo = TARGET_SIGFPE;
2399 info->si_errno = 0;
2400 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2401 queue_signal(env, info->si_signo, &*info);
2402 ret = 0;
2403 break;
2404 default:
b51910ba
PJ		 2405 info->si_signo = TARGET_SIGTRAP;
2406 info->si_errno = 0;
2407 queue_signal(env, info->si_signo, &*info);
2408 ret = 0;
54b2f42c
MI		 2409 break;
2410 }
2411
2412 return ret;
2413}
2414
048f6b4d
FB		 2415void cpu_loop(CPUMIPSState *env)
2416{
0315c31c 2417 CPUState *cs = CPU(mips_env_get_cpu(env));
c227f099 2418 target_siginfo_t info;
ff4f7382
RH		 2419 int trapnr;
2420 abi_long ret;
2421# ifdef TARGET_ABI_MIPSO32
048f6b4d 2422 unsigned int syscall_num;
ff4f7382 2423# endif
048f6b4d
FB		 2424
2425 for(;;) {
0315c31c 2426 cpu_exec_start(cs);
048f6b4d 2427 trapnr = cpu_mips_exec(env);
0315c31c 2428 cpu_exec_end(cs);
048f6b4d
FB		 2429 switch(trapnr) {
2430 case EXCP_SYSCALL:
b5dc7732 2431 env->active_tc.PC += 4;
ff4f7382
RH		 2432# ifdef TARGET_ABI_MIPSO32
2433 syscall_num = env->active_tc.gpr[2] - 4000;
388bb21a 2434 if (syscall_num >= sizeof(mips_syscall_args)) {
7c2f6157 2435 ret = -TARGET_ENOSYS;
388bb21a
TS		 2436 } else {
2437 int nb_args;
992f48a0
BS		 2438 abi_ulong sp_reg;
2439 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
388bb21a
TS		 2440
2441 nb_args = mips_syscall_args[syscall_num];
b5dc7732 2442 sp_reg = env->active_tc.gpr[29];
388bb21a
TS		 2443 switch (nb_args) {
2444 /* these arguments are taken from the stack */
94c19610
ACH		 2445 case 8:
2446 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2447 goto done_syscall;
2448 }
2449 case 7:
2450 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2451 goto done_syscall;
2452 }
2453 case 6:
2454 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2455 goto done_syscall;
2456 }
2457 case 5:
2458 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2459 goto done_syscall;
2460 }
388bb21a
TS		 2461 default:
2462 break;
048f6b4d 2463 }
b5dc7732
TS		 2464 ret = do_syscall(env, env->active_tc.gpr[2],
2465 env->active_tc.gpr[4],
2466 env->active_tc.gpr[5],
2467 env->active_tc.gpr[6],
2468 env->active_tc.gpr[7],
5945cfcb 2469 arg5, arg6, arg7, arg8);
388bb21a 2470 }
94c19610 2471done_syscall:
ff4f7382
RH		 2472# else
2473 ret = do_syscall(env, env->active_tc.gpr[2],
2474 env->active_tc.gpr[4], env->active_tc.gpr[5],
2475 env->active_tc.gpr[6], env->active_tc.gpr[7],
2476 env->active_tc.gpr[8], env->active_tc.gpr[9],
2477 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2478# endif /* O32 */
0b1bcb00
PB		 2479 if (ret == -TARGET_QEMU_ESIGRETURN) {
2480 /* Returning from a successful sigreturn syscall.
2481 Avoid clobbering register state. */
2482 break;
2483 }
ff4f7382 2484 if ((abi_ulong)ret >= (abi_ulong)-1133) {
b5dc7732 2485 env->active_tc.gpr[7] = 1; /* error flag */
388bb21a
TS		 2486 ret = -ret;
2487 } else {
b5dc7732 2488 env->active_tc.gpr[7] = 0; /* error flag */
048f6b4d 2489 }
b5dc7732 2490 env->active_tc.gpr[2] = ret;
048f6b4d 2491 break;
ca7c2b1b
TS		 2492 case EXCP_TLBL:
2493 case EXCP_TLBS:
e6e5bd2d
WT		 2494 case EXCP_AdEL:
2495 case EXCP_AdES:
e4474235
PB		 2496 info.si_signo = TARGET_SIGSEGV;
2497 info.si_errno = 0;
2498 /* XXX: check env->error_code */
2499 info.si_code = TARGET_SEGV_MAPERR;
2500 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2501 queue_signal(env, info.si_signo, &info);
2502 break;
6900e84b 2503 case EXCP_CpU:
048f6b4d 2504 case EXCP_RI:
bc1ad2de
FB		 2505 info.si_signo = TARGET_SIGILL;
2506 info.si_errno = 0;
2507 info.si_code = 0;
624f7979 2508 queue_signal(env, info.si_signo, &info);
048f6b4d 2509 break;
106ec879
FB		 2510 case EXCP_INTERRUPT:
2511 /* just indicate that signals should be handled asap */
2512 break;
d08b2a28
PB		 2513 case EXCP_DEBUG:
2514 {
2515 int sig;
2516
db6b81d4 2517 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d08b2a28
PB		 2518 if (sig)
2519 {
2520 info.si_signo = sig;
2521 info.si_errno = 0;
2522 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2523 queue_signal(env, info.si_signo, &info);
d08b2a28
PB		 2524 }
2525 }
2526 break;
590bc601
PB		 2527 case EXCP_SC:
2528 if (do_store_exclusive(env)) {
2529 info.si_signo = TARGET_SIGSEGV;
2530 info.si_errno = 0;
2531 info.si_code = TARGET_SEGV_MAPERR;
2532 info._sifields._sigfault._addr = env->active_tc.PC;
2533 queue_signal(env, info.si_signo, &info);
2534 }
2535 break;
853c3240
JL		 2536 case EXCP_DSPDIS:
2537 info.si_signo = TARGET_SIGILL;
2538 info.si_errno = 0;
2539 info.si_code = TARGET_ILL_ILLOPC;
2540 queue_signal(env, info.si_signo, &info);
2541 break;
54b2f42c
MI		 2542 /* The code below was inspired by the MIPS Linux kernel trap
2543 * handling code in arch/mips/kernel/traps.c.
2544 */
2545 case EXCP_BREAK:
2546 {
2547 abi_ulong trap_instr;
2548 unsigned int code;
2549
a0333817
KCY		 2550 if (env->hflags & MIPS_HFLAG_M16) {
2551 if (env->insn_flags & ASE_MICROMIPS) {
2552 /* microMIPS mode */
1308c464
KCY		 2553 ret = get_user_u16(trap_instr, env->active_tc.PC);
2554 if (ret != 0) {
2555 goto error;
2556 }
a0333817 2557
1308c464
KCY		 2558 if ((trap_instr >> 10) == 0x11) {
2559 /* 16-bit instruction */
2560 code = trap_instr & 0xf;
2561 } else {
2562 /* 32-bit instruction */
2563 abi_ulong instr_lo;
2564
2565 ret = get_user_u16(instr_lo,
2566 env->active_tc.PC + 2);
2567 if (ret != 0) {
2568 goto error;
2569 }
2570 trap_instr = (trap_instr << 16) | instr_lo;
2571 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2572 /* Unfortunately, microMIPS also suffers from
2573 the old assembler bug... */
2574 if (code >= (1 << 10)) {
2575 code >>= 10;
2576 }
2577 }
a0333817
KCY		 2578 } else {
2579 /* MIPS16e mode */
2580 ret = get_user_u16(trap_instr, env->active_tc.PC);
2581 if (ret != 0) {
2582 goto error;
2583 }
2584 code = (trap_instr >> 6) & 0x3f;
a0333817
KCY		 2585 }
2586 } else {
2587 ret = get_user_ual(trap_instr, env->active_tc.PC);
1308c464
KCY		 2588 if (ret != 0) {
2589 goto error;
2590 }
54b2f42c 2591
1308c464
KCY		 2592 /* As described in the original Linux kernel code, the
2593 * below checks on 'code' are to work around an old
2594 * assembly bug.
2595 */
2596 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2597 if (code >= (1 << 10)) {
2598 code >>= 10;
2599 }
54b2f42c
MI		 2600 }
2601
2602 if (do_break(env, &info, code) != 0) {
2603 goto error;
2604 }
2605 }
2606 break;
2607 case EXCP_TRAP:
2608 {
2609 abi_ulong trap_instr;
2610 unsigned int code = 0;
2611
a0333817
KCY		 2612 if (env->hflags & MIPS_HFLAG_M16) {
2613 /* microMIPS mode */
2614 abi_ulong instr[2];
2615
2616 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2617 get_user_u16(instr[1], env->active_tc.PC + 2);
2618
2619 trap_instr = (instr[0] << 16) | instr[1];
2620 } else {
2621 ret = get_user_ual(trap_instr, env->active_tc.PC);
2622 }
2623
54b2f42c
MI		 2624 if (ret != 0) {
2625 goto error;
2626 }
2627
2628 /* The immediate versions don't provide a code. */
2629 if (!(trap_instr & 0xFC000000)) {
a0333817
KCY		 2630 if (env->hflags & MIPS_HFLAG_M16) {
2631 /* microMIPS mode */
2632 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2633 } else {
2634 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2635 }
54b2f42c
MI		 2636 }
2637
2638 if (do_break(env, &info, code) != 0) {
2639 goto error;
2640 }
2641 }
2642 break;
048f6b4d 2643 default:
54b2f42c 2644error:
5fafdf24 2645 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
048f6b4d 2646 trapnr);
878096ee 2647 cpu_dump_state(cs, stderr, fprintf, 0);
048f6b4d
FB		 2648 abort();
2649 }
2650 process_pending_signals(env);
2651 }
2652}
2653#endif
2654
d962783e
JL		 2655#ifdef TARGET_OPENRISC
2656
2657void cpu_loop(CPUOpenRISCState *env)
2658{
878096ee 2659 CPUState *cs = CPU(openrisc_env_get_cpu(env));
d962783e
JL		 2660 int trapnr, gdbsig;
2661
2662 for (;;) {
b040bc9c 2663 cpu_exec_start(cs);
d962783e 2664 trapnr = cpu_exec(env);
b040bc9c 2665 cpu_exec_end(cs);
d962783e
JL		 2666 gdbsig = 0;
2667
2668 switch (trapnr) {
2669 case EXCP_RESET:
2670 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2671 exit(1);
2672 break;
2673 case EXCP_BUSERR:
2674 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
a86b3c64 2675 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2676 break;
2677 case EXCP_DPF:
2678 case EXCP_IPF:
878096ee 2679 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2680 gdbsig = TARGET_SIGSEGV;
2681 break;
2682 case EXCP_TICK:
2683 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2684 break;
2685 case EXCP_ALIGN:
2686 qemu_log("\nAlignment pc is %#x\n", env->pc);
a86b3c64 2687 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2688 break;
2689 case EXCP_ILLEGAL:
2690 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
a86b3c64 2691 gdbsig = TARGET_SIGILL;
d962783e
JL		 2692 break;
2693 case EXCP_INT:
2694 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2695 break;
2696 case EXCP_DTLBMISS:
2697 case EXCP_ITLBMISS:
2698 qemu_log("\nTLB miss\n");
2699 break;
2700 case EXCP_RANGE:
2701 qemu_log("\nRange\n");
a86b3c64 2702 gdbsig = TARGET_SIGSEGV;
d962783e
JL		 2703 break;
2704 case EXCP_SYSCALL:
2705 env->pc += 4; /* 0xc00; */
2706 env->gpr[11] = do_syscall(env,
2707 env->gpr[11], /* return value */
2708 env->gpr[3], /* r3 - r7 are params */
2709 env->gpr[4],
2710 env->gpr[5],
2711 env->gpr[6],
2712 env->gpr[7],
2713 env->gpr[8], 0, 0);
2714 break;
2715 case EXCP_FPE:
2716 qemu_log("\nFloating point error\n");
2717 break;
2718 case EXCP_TRAP:
2719 qemu_log("\nTrap\n");
a86b3c64 2720 gdbsig = TARGET_SIGTRAP;
d962783e
JL		 2721 break;
2722 case EXCP_NR:
2723 qemu_log("\nNR\n");
2724 break;
2725 default:
2726 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2727 trapnr);
878096ee 2728 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2729 gdbsig = TARGET_SIGILL;
2730 break;
2731 }
2732 if (gdbsig) {
db6b81d4 2733 gdb_handlesig(cs, gdbsig);
d962783e
JL		 2734 if (gdbsig != TARGET_SIGTRAP) {
2735 exit(1);
2736 }
2737 }
2738
2739 process_pending_signals(env);
2740 }
2741}
2742
2743#endif /* TARGET_OPENRISC */
2744
fdf9b3e8 2745#ifdef TARGET_SH4
05390248 2746void cpu_loop(CPUSH4State *env)
fdf9b3e8 2747{
878096ee 2748 CPUState *cs = CPU(sh_env_get_cpu(env));
fdf9b3e8 2749 int trapnr, ret;
c227f099 2750 target_siginfo_t info;
3b46e624 2751
fdf9b3e8 2752 while (1) {
b040bc9c 2753 cpu_exec_start(cs);
fdf9b3e8 2754 trapnr = cpu_sh4_exec (env);
b040bc9c 2755 cpu_exec_end(cs);
3b46e624 2756
fdf9b3e8
FB		 2757 switch (trapnr) {
2758 case 0x160:
0b6d3ae0 2759 env->pc += 2;
5fafdf24
TS		 2760 ret = do_syscall(env,
2761 env->gregs[3],
2762 env->gregs[4],
2763 env->gregs[5],
2764 env->gregs[6],
2765 env->gregs[7],
2766 env->gregs[0],
5945cfcb
PM		 2767 env->gregs[1],
2768 0, 0);
9c2a9ea1 2769 env->gregs[0] = ret;
fdf9b3e8 2770 break;
c3b5bc8a
TS		 2771 case EXCP_INTERRUPT:
2772 /* just indicate that signals should be handled asap */
2773 break;
355fb23d
PB		 2774 case EXCP_DEBUG:
2775 {
2776 int sig;
2777
db6b81d4 2778 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
355fb23d
PB		 2779 if (sig)
2780 {
2781 info.si_signo = sig;
2782 info.si_errno = 0;
2783 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2784 queue_signal(env, info.si_signo, &info);
355fb23d
PB		 2785 }
2786 }
2787 break;
c3b5bc8a
TS		 2788 case 0xa0:
2789 case 0xc0:
a86b3c64 2790 info.si_signo = TARGET_SIGSEGV;
c3b5bc8a
TS		 2791 info.si_errno = 0;
2792 info.si_code = TARGET_SEGV_MAPERR;
2793 info._sifields._sigfault._addr = env->tea;
624f7979 2794 queue_signal(env, info.si_signo, &info);
c3b5bc8a
TS		 2795 break;
2796
fdf9b3e8
FB		 2797 default:
2798 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2799 cpu_dump_state(cs, stderr, fprintf, 0);
fdf9b3e8
FB		 2800 exit (1);
2801 }
2802 process_pending_signals (env);
2803 }
2804}
2805#endif
2806
48733d19 2807#ifdef TARGET_CRIS
05390248 2808void cpu_loop(CPUCRISState *env)
48733d19 2809{
878096ee 2810 CPUState *cs = CPU(cris_env_get_cpu(env));
48733d19 2811 int trapnr, ret;
c227f099 2812 target_siginfo_t info;
48733d19
TS		 2813
2814 while (1) {
b040bc9c 2815 cpu_exec_start(cs);
48733d19 2816 trapnr = cpu_cris_exec (env);
b040bc9c 2817 cpu_exec_end(cs);
48733d19
TS		 2818 switch (trapnr) {
2819 case 0xaa:
2820 {
a86b3c64 2821 info.si_signo = TARGET_SIGSEGV;
48733d19
TS		 2822 info.si_errno = 0;
2823 /* XXX: check env->error_code */
2824 info.si_code = TARGET_SEGV_MAPERR;
e00c1e71 2825 info._sifields._sigfault._addr = env->pregs[PR_EDA];
624f7979 2826 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2827 }
2828 break;
b6d3abda
EI		 2829 case EXCP_INTERRUPT:
2830 /* just indicate that signals should be handled asap */
2831 break;
48733d19
TS		 2832 case EXCP_BREAK:
2833 ret = do_syscall(env,
2834 env->regs[9],
2835 env->regs[10],
2836 env->regs[11],
2837 env->regs[12],
2838 env->regs[13],
2839 env->pregs[7],
5945cfcb
PM		 2840 env->pregs[11],
2841 0, 0);
48733d19 2842 env->regs[10] = ret;
48733d19
TS		 2843 break;
2844 case EXCP_DEBUG:
2845 {
2846 int sig;
2847
db6b81d4 2848 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
48733d19
TS		 2849 if (sig)
2850 {
2851 info.si_signo = sig;
2852 info.si_errno = 0;
2853 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2854 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2855 }
2856 }
2857 break;
2858 default:
2859 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2860 cpu_dump_state(cs, stderr, fprintf, 0);
48733d19
TS		 2861 exit (1);
2862 }
2863 process_pending_signals (env);
2864 }
2865}
2866#endif
2867
b779e29e 2868#ifdef TARGET_MICROBLAZE
05390248 2869void cpu_loop(CPUMBState *env)
b779e29e 2870{
878096ee 2871 CPUState *cs = CPU(mb_env_get_cpu(env));
b779e29e 2872 int trapnr, ret;
c227f099 2873 target_siginfo_t info;
b779e29e
EI		 2874
2875 while (1) {
b040bc9c 2876 cpu_exec_start(cs);
b779e29e 2877 trapnr = cpu_mb_exec (env);
b040bc9c 2878 cpu_exec_end(cs);
b779e29e
EI		 2879 switch (trapnr) {
2880 case 0xaa:
2881 {
a86b3c64 2882 info.si_signo = TARGET_SIGSEGV;
b779e29e
EI		 2883 info.si_errno = 0;
2884 /* XXX: check env->error_code */
2885 info.si_code = TARGET_SEGV_MAPERR;
2886 info._sifields._sigfault._addr = 0;
2887 queue_signal(env, info.si_signo, &info);
2888 }
2889 break;
2890 case EXCP_INTERRUPT:
2891 /* just indicate that signals should be handled asap */
2892 break;
2893 case EXCP_BREAK:
2894 /* Return address is 4 bytes after the call. */
2895 env->regs[14] += 4;
d7dce494 2896 env->sregs[SR_PC] = env->regs[14];
b779e29e
EI		 2897 ret = do_syscall(env,
2898 env->regs[12],
2899 env->regs[5],
2900 env->regs[6],
2901 env->regs[7],
2902 env->regs[8],
2903 env->regs[9],
5945cfcb
PM		 2904 env->regs[10],
2905 0, 0);
b779e29e 2906 env->regs[3] = ret;
b779e29e 2907 break;
b76da7e3
EI		 2908 case EXCP_HW_EXCP:
2909 env->regs[17] = env->sregs[SR_PC] + 4;
2910 if (env->iflags & D_FLAG) {
2911 env->sregs[SR_ESR] |= 1 << 12;
2912 env->sregs[SR_PC] -= 4;
b4916d7b 2913 /* FIXME: if branch was immed, replay the imm as well. */
b76da7e3
EI		 2914 }
2915
2916 env->iflags &= ~(IMM_FLAG | D_FLAG);
2917
2918 switch (env->sregs[SR_ESR] & 31) {
22a78d64 2919 case ESR_EC_DIVZERO:
a86b3c64 2920 info.si_signo = TARGET_SIGFPE;
22a78d64
EI		 2921 info.si_errno = 0;
2922 info.si_code = TARGET_FPE_FLTDIV;
2923 info._sifields._sigfault._addr = 0;
2924 queue_signal(env, info.si_signo, &info);
2925 break;
b76da7e3 2926 case ESR_EC_FPU:
a86b3c64 2927 info.si_signo = TARGET_SIGFPE;
b76da7e3
EI		 2928 info.si_errno = 0;
2929 if (env->sregs[SR_FSR] & FSR_IO) {
2930 info.si_code = TARGET_FPE_FLTINV;
2931 }
2932 if (env->sregs[SR_FSR] & FSR_DZ) {
2933 info.si_code = TARGET_FPE_FLTDIV;
2934 }
2935 info._sifields._sigfault._addr = 0;
2936 queue_signal(env, info.si_signo, &info);
2937 break;
2938 default:
2939 printf ("Unhandled hw-exception: 0x%x\n",
2e42d52d 2940 env->sregs[SR_ESR] & ESR_EC_MASK);
878096ee 2941 cpu_dump_state(cs, stderr, fprintf, 0);
b76da7e3
EI		 2942 exit (1);
2943 break;
2944 }
2945 break;
b779e29e
EI		 2946 case EXCP_DEBUG:
2947 {
2948 int sig;
2949
db6b81d4 2950 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
b779e29e
EI		 2951 if (sig)
2952 {
2953 info.si_signo = sig;
2954 info.si_errno = 0;
2955 info.si_code = TARGET_TRAP_BRKPT;
2956 queue_signal(env, info.si_signo, &info);
2957 }
2958 }
2959 break;
2960 default:
2961 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2962 cpu_dump_state(cs, stderr, fprintf, 0);
b779e29e
EI		 2963 exit (1);
2964 }
2965 process_pending_signals (env);
2966 }
2967}
2968#endif
2969
e6e5906b
PB		 2970#ifdef TARGET_M68K
2971
2972void cpu_loop(CPUM68KState *env)
2973{
878096ee 2974 CPUState *cs = CPU(m68k_env_get_cpu(env));
e6e5906b
PB		 2975 int trapnr;
2976 unsigned int n;
c227f099 2977 target_siginfo_t info;
0429a971 2978 TaskState *ts = cs->opaque;
3b46e624 2979
e6e5906b 2980 for(;;) {
b040bc9c 2981 cpu_exec_start(cs);
e6e5906b 2982 trapnr = cpu_m68k_exec(env);
b040bc9c 2983 cpu_exec_end(cs);
e6e5906b
PB		 2984 switch(trapnr) {
2985 case EXCP_ILLEGAL:
2986 {
2987 if (ts->sim_syscalls) {
2988 uint16_t nr;
d8d5119c 2989 get_user_u16(nr, env->pc + 2);
e6e5906b
PB		 2990 env->pc += 4;
2991 do_m68k_simcall(env, nr);
2992 } else {
2993 goto do_sigill;
2994 }
2995 }
2996 break;
a87295e8 2997 case EXCP_HALT_INSN:
e6e5906b 2998 /* Semihosing syscall. */
a87295e8 2999 env->pc += 4;
e6e5906b
PB		 3000 do_m68k_semihosting(env, env->dregs[0]);
3001 break;
3002 case EXCP_LINEA:
3003 case EXCP_LINEF:
3004 case EXCP_UNSUPPORTED:
3005 do_sigill:
a86b3c64 3006 info.si_signo = TARGET_SIGILL;
e6e5906b
PB		 3007 info.si_errno = 0;
3008 info.si_code = TARGET_ILL_ILLOPN;
3009 info._sifields._sigfault._addr = env->pc;
624f7979 3010 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3011 break;
3012 case EXCP_TRAP0:
3013 {
3014 ts->sim_syscalls = 0;
3015 n = env->dregs[0];
3016 env->pc += 2;
5fafdf24
TS		 3017 env->dregs[0] = do_syscall(env,
3018 n,
e6e5906b
PB		 3019 env->dregs[1],
3020 env->dregs[2],
3021 env->dregs[3],
3022 env->dregs[4],
3023 env->dregs[5],
5945cfcb
PM		 3024 env->aregs[0],
3025 0, 0);
e6e5906b
PB		 3026 }
3027 break;
3028 case EXCP_INTERRUPT:
3029 /* just indicate that signals should be handled asap */
3030 break;
3031 case EXCP_ACCESS:
3032 {
a86b3c64 3033 info.si_signo = TARGET_SIGSEGV;
e6e5906b
PB		 3034 info.si_errno = 0;
3035 /* XXX: check env->error_code */
3036 info.si_code = TARGET_SEGV_MAPERR;
3037 info._sifields._sigfault._addr = env->mmu.ar;
624f7979 3038 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3039 }
3040 break;
3041 case EXCP_DEBUG:
3042 {
3043 int sig;
3044
db6b81d4 3045 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
e6e5906b
PB		 3046 if (sig)
3047 {
3048 info.si_signo = sig;
3049 info.si_errno = 0;
3050 info.si_code = TARGET_TRAP_BRKPT;
624f7979 3051 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3052 }
3053 }
3054 break;
3055 default:
5fafdf24 3056 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
e6e5906b 3057 trapnr);
878096ee 3058 cpu_dump_state(cs, stderr, fprintf, 0);
e6e5906b
PB		 3059 abort();
3060 }
3061 process_pending_signals(env);
3062 }
3063}
3064#endif /* TARGET_M68K */
3065
7a3148a9 3066#ifdef TARGET_ALPHA
6910b8f6
RH		 3067static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3068{
3069 target_ulong addr, val, tmp;
3070 target_siginfo_t info;
3071 int ret = 0;
3072
3073 addr = env->lock_addr;
3074 tmp = env->lock_st_addr;
3075 env->lock_addr = -1;
3076 env->lock_st_addr = 0;
3077
3078 start_exclusive();
3079 mmap_lock();
3080
3081 if (addr == tmp) {
3082 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3083 goto do_sigsegv;
3084 }
3085
3086 if (val == env->lock_value) {
3087 tmp = env->ir[reg];
3088 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3089 goto do_sigsegv;
3090 }
3091 ret = 1;
3092 }
3093 }
3094 env->ir[reg] = ret;
3095 env->pc += 4;
3096
3097 mmap_unlock();
3098 end_exclusive();
3099 return;
3100
3101 do_sigsegv:
3102 mmap_unlock();
3103 end_exclusive();
3104
3105 info.si_signo = TARGET_SIGSEGV;
3106 info.si_errno = 0;
3107 info.si_code = TARGET_SEGV_MAPERR;
3108 info._sifields._sigfault._addr = addr;
3109 queue_signal(env, TARGET_SIGSEGV, &info);
3110}
3111
05390248 3112void cpu_loop(CPUAlphaState *env)
7a3148a9 3113{
878096ee 3114 CPUState *cs = CPU(alpha_env_get_cpu(env));
e96efcfc 3115 int trapnr;
c227f099 3116 target_siginfo_t info;
6049f4f8 3117 abi_long sysret;
3b46e624 3118
7a3148a9 3119 while (1) {
b040bc9c 3120 cpu_exec_start(cs);
7a3148a9 3121 trapnr = cpu_alpha_exec (env);
b040bc9c 3122 cpu_exec_end(cs);
3b46e624 3123
ac316ca4
RH		 3124 /* All of the traps imply a transition through PALcode, which
3125 implies an REI instruction has been executed. Which means
3126 that the intr_flag should be cleared. */
3127 env->intr_flag = 0;
3128
7a3148a9
JM		 3129 switch (trapnr) {
3130 case EXCP_RESET:
3131 fprintf(stderr, "Reset requested. Exit\n");
3132 exit(1);
3133 break;
3134 case EXCP_MCHK:
3135 fprintf(stderr, "Machine check exception. Exit\n");
3136 exit(1);
3137 break;
07b6c13b
RH		 3138 case EXCP_SMP_INTERRUPT:
3139 case EXCP_CLK_INTERRUPT:
3140 case EXCP_DEV_INTERRUPT:
5fafdf24 3141 fprintf(stderr, "External interrupt. Exit\n");
7a3148a9
JM		 3142 exit(1);
3143 break;
07b6c13b 3144 case EXCP_MMFAULT:
6910b8f6 3145 env->lock_addr = -1;
6049f4f8
RH		 3146 info.si_signo = TARGET_SIGSEGV;
3147 info.si_errno = 0;
129d8aa5 3148 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
0be1d07c 3149 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
129d8aa5 3150 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3151 queue_signal(env, info.si_signo, &info);
7a3148a9 3152 break;
7a3148a9 3153 case EXCP_UNALIGN:
6910b8f6 3154 env->lock_addr = -1;
6049f4f8
RH		 3155 info.si_signo = TARGET_SIGBUS;
3156 info.si_errno = 0;
3157 info.si_code = TARGET_BUS_ADRALN;
129d8aa5 3158 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3159 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3160 break;
3161 case EXCP_OPCDEC:
6049f4f8 3162 do_sigill:
6910b8f6 3163 env->lock_addr = -1;
6049f4f8
RH		 3164 info.si_signo = TARGET_SIGILL;
3165 info.si_errno = 0;
3166 info.si_code = TARGET_ILL_ILLOPC;
3167 info._sifields._sigfault._addr = env->pc;
3168 queue_signal(env, info.si_signo, &info);
7a3148a9 3169 break;
07b6c13b
RH		 3170 case EXCP_ARITH:
3171 env->lock_addr = -1;
3172 info.si_signo = TARGET_SIGFPE;
3173 info.si_errno = 0;
3174 info.si_code = TARGET_FPE_FLTINV;
3175 info._sifields._sigfault._addr = env->pc;
3176 queue_signal(env, info.si_signo, &info);
3177 break;
7a3148a9 3178 case EXCP_FEN:
6049f4f8 3179 /* No-op. Linux simply re-enables the FPU. */
7a3148a9 3180 break;
07b6c13b 3181 case EXCP_CALL_PAL:
6910b8f6 3182 env->lock_addr = -1;
07b6c13b 3183 switch (env->error_code) {
6049f4f8
RH		 3184 case 0x80:
3185 /* BPT */
3186 info.si_signo = TARGET_SIGTRAP;
3187 info.si_errno = 0;
3188 info.si_code = TARGET_TRAP_BRKPT;
3189 info._sifields._sigfault._addr = env->pc;
3190 queue_signal(env, info.si_signo, &info);
3191 break;
3192 case 0x81:
3193 /* BUGCHK */
3194 info.si_signo = TARGET_SIGTRAP;
3195 info.si_errno = 0;
3196 info.si_code = 0;
3197 info._sifields._sigfault._addr = env->pc;
3198 queue_signal(env, info.si_signo, &info);
3199 break;
3200 case 0x83:
3201 /* CALLSYS */
3202 trapnr = env->ir[IR_V0];
3203 sysret = do_syscall(env, trapnr,
3204 env->ir[IR_A0], env->ir[IR_A1],
3205 env->ir[IR_A2], env->ir[IR_A3],
5945cfcb
PM		 3206 env->ir[IR_A4], env->ir[IR_A5],
3207 0, 0);
a5b3b13b
RH		 3208 if (trapnr == TARGET_NR_sigreturn
3209 || trapnr == TARGET_NR_rt_sigreturn) {
3210 break;
3211 }
3212 /* Syscall writes 0 to V0 to bypass error check, similar
0e141977
RH		 3213 to how this is handled internal to Linux kernel.
3214 (Ab)use trapnr temporarily as boolean indicating error. */
3215 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3216 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3217 env->ir[IR_A3] = trapnr;
6049f4f8
RH		 3218 break;
3219 case 0x86:
3220 /* IMB */
3221 /* ??? We can probably elide the code using page_unprotect
3222 that is checking for self-modifying code. Instead we
3223 could simply call tb_flush here. Until we work out the
3224 changes required to turn off the extra write protection,
3225 this can be a no-op. */
3226 break;
3227 case 0x9E:
3228 /* RDUNIQUE */
3229 /* Handled in the translator for usermode. */
3230 abort();
3231 case 0x9F:
3232 /* WRUNIQUE */
3233 /* Handled in the translator for usermode. */
3234 abort();
3235 case 0xAA:
3236 /* GENTRAP */
3237 info.si_signo = TARGET_SIGFPE;
3238 switch (env->ir[IR_A0]) {
3239 case TARGET_GEN_INTOVF:
3240 info.si_code = TARGET_FPE_INTOVF;
3241 break;
3242 case TARGET_GEN_INTDIV:
3243 info.si_code = TARGET_FPE_INTDIV;
3244 break;
3245 case TARGET_GEN_FLTOVF:
3246 info.si_code = TARGET_FPE_FLTOVF;
3247 break;
3248 case TARGET_GEN_FLTUND:
3249 info.si_code = TARGET_FPE_FLTUND;
3250 break;
3251 case TARGET_GEN_FLTINV:
3252 info.si_code = TARGET_FPE_FLTINV;
3253 break;
3254 case TARGET_GEN_FLTINE:
3255 info.si_code = TARGET_FPE_FLTRES;
3256 break;
3257 case TARGET_GEN_ROPRAND:
3258 info.si_code = 0;
3259 break;
3260 default:
3261 info.si_signo = TARGET_SIGTRAP;
3262 info.si_code = 0;
3263 break;
3264 }
3265 info.si_errno = 0;
3266 info._sifields._sigfault._addr = env->pc;
3267 queue_signal(env, info.si_signo, &info);
3268 break;
3269 default:
3270 goto do_sigill;
3271 }
7a3148a9 3272 break;
7a3148a9 3273 case EXCP_DEBUG:
db6b81d4 3274 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
6049f4f8 3275 if (info.si_signo) {
6910b8f6 3276 env->lock_addr = -1;
6049f4f8
RH		 3277 info.si_errno = 0;
3278 info.si_code = TARGET_TRAP_BRKPT;
3279 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3280 }
3281 break;
6910b8f6
RH		 3282 case EXCP_STL_C:
3283 case EXCP_STQ_C:
3284 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3285 break;
d0f20495
RH		 3286 case EXCP_INTERRUPT:
3287 /* Just indicate that signals should be handled asap. */
3288 break;
7a3148a9
JM		 3289 default:
3290 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3291 cpu_dump_state(cs, stderr, fprintf, 0);
7a3148a9
JM		 3292 exit (1);
3293 }
3294 process_pending_signals (env);
3295 }
3296}
3297#endif /* TARGET_ALPHA */
3298
a4c075f1
UH		 3299#ifdef TARGET_S390X
3300void cpu_loop(CPUS390XState *env)
3301{
878096ee 3302 CPUState *cs = CPU(s390_env_get_cpu(env));
d5a103cd 3303 int trapnr, n, sig;
a4c075f1 3304 target_siginfo_t info;
d5a103cd 3305 target_ulong addr;
a4c075f1
UH		 3306
3307 while (1) {
b040bc9c 3308 cpu_exec_start(cs);
d5a103cd 3309 trapnr = cpu_s390x_exec(env);
b040bc9c 3310 cpu_exec_end(cs);
a4c075f1
UH		 3311 switch (trapnr) {
3312 case EXCP_INTERRUPT:
d5a103cd 3313 /* Just indicate that signals should be handled asap. */
a4c075f1 3314 break;
a4c075f1 3315
d5a103cd
RH		 3316 case EXCP_SVC:
3317 n = env->int_svc_code;
3318 if (!n) {
3319 /* syscalls > 255 */
3320 n = env->regs[1];
a4c075f1 3321 }
d5a103cd
RH		 3322 env->psw.addr += env->int_svc_ilen;
3323 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3324 env->regs[4], env->regs[5],
3325 env->regs[6], env->regs[7], 0, 0);
a4c075f1 3326 break;
d5a103cd
RH		 3327
3328 case EXCP_DEBUG:
db6b81d4 3329 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d5a103cd
RH		 3330 if (sig) {
3331 n = TARGET_TRAP_BRKPT;
3332 goto do_signal_pc;
a4c075f1
UH		 3333 }
3334 break;
d5a103cd
RH		 3335 case EXCP_PGM:
3336 n = env->int_pgm_code;
3337 switch (n) {
3338 case PGM_OPERATION:
3339 case PGM_PRIVILEGED:
a86b3c64 3340 sig = TARGET_SIGILL;
d5a103cd
RH		 3341 n = TARGET_ILL_ILLOPC;
3342 goto do_signal_pc;
3343 case PGM_PROTECTION:
3344 case PGM_ADDRESSING:
a86b3c64 3345 sig = TARGET_SIGSEGV;
a4c075f1 3346 /* XXX: check env->error_code */
d5a103cd
RH		 3347 n = TARGET_SEGV_MAPERR;
3348 addr = env->__excp_addr;
3349 goto do_signal;
3350 case PGM_EXECUTE:
3351 case PGM_SPECIFICATION:
3352 case PGM_SPECIAL_OP:
3353 case PGM_OPERAND:
3354 do_sigill_opn:
a86b3c64 3355 sig = TARGET_SIGILL;
d5a103cd
RH		 3356 n = TARGET_ILL_ILLOPN;
3357 goto do_signal_pc;
3358
3359 case PGM_FIXPT_OVERFLOW:
a86b3c64 3360 sig = TARGET_SIGFPE;
d5a103cd
RH		 3361 n = TARGET_FPE_INTOVF;
3362 goto do_signal_pc;
3363 case PGM_FIXPT_DIVIDE:
a86b3c64 3364 sig = TARGET_SIGFPE;
d5a103cd
RH		 3365 n = TARGET_FPE_INTDIV;
3366 goto do_signal_pc;
3367
3368 case PGM_DATA:
3369 n = (env->fpc >> 8) & 0xff;
3370 if (n == 0xff) {
3371 /* compare-and-trap */
3372 goto do_sigill_opn;
3373 } else {
3374 /* An IEEE exception, simulated or otherwise. */
3375 if (n & 0x80) {
3376 n = TARGET_FPE_FLTINV;
3377 } else if (n & 0x40) {
3378 n = TARGET_FPE_FLTDIV;
3379 } else if (n & 0x20) {
3380 n = TARGET_FPE_FLTOVF;
3381 } else if (n & 0x10) {
3382 n = TARGET_FPE_FLTUND;
3383 } else if (n & 0x08) {
3384 n = TARGET_FPE_FLTRES;
3385 } else {
3386 /* ??? Quantum exception; BFP, DFP error. */
3387 goto do_sigill_opn;
3388 }
a86b3c64 3389 sig = TARGET_SIGFPE;
d5a103cd
RH		 3390 goto do_signal_pc;
3391 }
3392
3393 default:
3394 fprintf(stderr, "Unhandled program exception: %#x\n", n);
878096ee 3395 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3396 exit(1);
a4c075f1
UH		 3397 }
3398 break;
d5a103cd
RH		 3399
3400 do_signal_pc:
3401 addr = env->psw.addr;
3402 do_signal:
3403 info.si_signo = sig;
3404 info.si_errno = 0;
3405 info.si_code = n;
3406 info._sifields._sigfault._addr = addr;
3407 queue_signal(env, info.si_signo, &info);
a4c075f1 3408 break;
d5a103cd 3409
a4c075f1 3410 default:
d5a103cd 3411 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
878096ee 3412 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3413 exit(1);
a4c075f1
UH		 3414 }
3415 process_pending_signals (env);
3416 }
3417}
3418
3419#endif /* TARGET_S390X */
3420
a2247f8e 3421THREAD CPUState *thread_cpu;
59faf6d6 3422
edf8e2af
MW		 3423void task_settid(TaskState *ts)
3424{
3425 if (ts->ts_tid == 0) {
edf8e2af 3426 ts->ts_tid = (pid_t)syscall(SYS_gettid);
edf8e2af
MW		 3427 }
3428}
3429
3430void stop_all_tasks(void)
3431{
3432 /*
3433 * We trust that when using NPTL, start_exclusive()
3434 * handles thread stopping correctly.
3435 */
3436 start_exclusive();
3437}
3438
c3a92833 3439/* Assumes contents are already zeroed. */
624f7979
PB		 3440void init_task_state(TaskState *ts)
3441{
3442 int i;
3443
624f7979
PB		 3444 ts->used = 1;
3445 ts->first_free = ts->sigqueue_table;
3446 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3447 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3448 }
3449 ts->sigqueue_table[i].next = NULL;
3450}
fc9c5412 3451
30ba0ee5
AF		 3452CPUArchState *cpu_copy(CPUArchState *env)
3453{
ff4700b0 3454 CPUState *cpu = ENV_GET_CPU(env);
51fb256a 3455 CPUArchState *new_env = cpu_init(cpu_model);
0856579c 3456 CPUState *new_cpu = ENV_GET_CPU(new_env);
30ba0ee5
AF		 3457 CPUBreakpoint *bp;
3458 CPUWatchpoint *wp;
30ba0ee5
AF		 3459
3460 /* Reset non arch specific state */
75a34036 3461 cpu_reset(new_cpu);
30ba0ee5
AF		 3462
3463 memcpy(new_env, env, sizeof(CPUArchState));
3464
3465 /* Clone all break/watchpoints.
3466 Note: Once we support ptrace with hw-debug register access, make sure
3467 BP_CPU break/watchpoints are handled correctly on clone. */
f0c3c505 3468 QTAILQ_INIT(&cpu->breakpoints);
ff4700b0 3469 QTAILQ_INIT(&cpu->watchpoints);
f0c3c505 3470 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
b3310ab3 3471 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
30ba0ee5 3472 }
ff4700b0 3473 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
05068c0d 3474 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
30ba0ee5 3475 }
30ba0ee5
AF		 3476
3477 return new_env;
3478}
3479
fc9c5412
JS		 3480static void handle_arg_help(const char *arg)
3481{
3482 usage();
3483}
3484
3485static void handle_arg_log(const char *arg)
3486{
3487 int mask;
fc9c5412 3488
4fde1eba 3489 mask = qemu_str_to_log_mask(arg);
fc9c5412 3490 if (!mask) {
59a6fa6e 3491 qemu_print_log_usage(stdout);
fc9c5412
JS		 3492 exit(1);
3493 }
24537a01 3494 qemu_set_log(mask);
fc9c5412
JS		 3495}
3496
50171d42
CWR		 3497static void handle_arg_log_filename(const char *arg)
3498{
9a7e5424 3499 qemu_set_log_filename(arg);
50171d42
CWR		 3500}
3501
fc9c5412
JS		 3502static void handle_arg_set_env(const char *arg)
3503{
3504 char *r, *p, *token;
3505 r = p = strdup(arg);
3506 while ((token = strsep(&p, ",")) != NULL) {
3507 if (envlist_setenv(envlist, token) != 0) {
3508 usage();
3509 }
3510 }
3511 free(r);
3512}
3513
3514static void handle_arg_unset_env(const char *arg)
3515{
3516 char *r, *p, *token;
3517 r = p = strdup(arg);
3518 while ((token = strsep(&p, ",")) != NULL) {
3519 if (envlist_unsetenv(envlist, token) != 0) {
3520 usage();
3521 }
3522 }
3523 free(r);
3524}
3525
3526static void handle_arg_argv0(const char *arg)
3527{
3528 argv0 = strdup(arg);
3529}
3530
3531static void handle_arg_stack_size(const char *arg)
3532{
3533 char *p;
3534 guest_stack_size = strtoul(arg, &p, 0);
3535 if (guest_stack_size == 0) {
3536 usage();
3537 }
3538
3539 if (*p == 'M') {
3540 guest_stack_size *= 1024 * 1024;
3541 } else if (*p == 'k' || *p == 'K') {
3542 guest_stack_size *= 1024;
3543 }
3544}
3545
3546static void handle_arg_ld_prefix(const char *arg)
3547{
3548 interp_prefix = strdup(arg);
3549}
3550
3551static void handle_arg_pagesize(const char *arg)
3552{
3553 qemu_host_page_size = atoi(arg);
3554 if (qemu_host_page_size == 0 ||
3555 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3556 fprintf(stderr, "page size must be a power of two\n");
3557 exit(1);
3558 }
3559}
3560
c5e4a5a9
MR		 3561static void handle_arg_randseed(const char *arg)
3562{
3563 unsigned long long seed;
3564
3565 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3566 fprintf(stderr, "Invalid seed number: %s\n", arg);
3567 exit(1);
3568 }
3569 srand(seed);
3570}
3571
fc9c5412
JS		 3572static void handle_arg_gdb(const char *arg)
3573{
3574 gdbstub_port = atoi(arg);
3575}
3576
3577static void handle_arg_uname(const char *arg)
3578{
3579 qemu_uname_release = strdup(arg);
3580}
3581
3582static void handle_arg_cpu(const char *arg)
3583{
3584 cpu_model = strdup(arg);
c8057f95 3585 if (cpu_model == NULL || is_help_option(cpu_model)) {
fc9c5412 3586 /* XXX: implement xxx_cpu_list for targets that still miss it */
e916cbf8
PM		 3587#if defined(cpu_list)
3588 cpu_list(stdout, &fprintf);
fc9c5412
JS		 3589#endif
3590 exit(1);
3591 }
3592}
3593
3594#if defined(CONFIG_USE_GUEST_BASE)
3595static void handle_arg_guest_base(const char *arg)
3596{
3597 guest_base = strtol(arg, NULL, 0);
3598 have_guest_base = 1;
3599}
3600
3601static void handle_arg_reserved_va(const char *arg)
3602{
3603 char *p;
3604 int shift = 0;
3605 reserved_va = strtoul(arg, &p, 0);
3606 switch (*p) {
3607 case 'k':
3608 case 'K':
3609 shift = 10;
3610 break;
3611 case 'M':
3612 shift = 20;
3613 break;
3614 case 'G':
3615 shift = 30;
3616 break;
3617 }
3618 if (shift) {
3619 unsigned long unshifted = reserved_va;
3620 p++;
3621 reserved_va <<= shift;
3622 if (((reserved_va >> shift) != unshifted)
3623#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3624 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3625#endif
3626 ) {
3627 fprintf(stderr, "Reserved virtual address too big\n");
3628 exit(1);
3629 }
3630 }
3631 if (*p) {
3632 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3633 exit(1);
3634 }
3635}
3636#endif
3637
3638static void handle_arg_singlestep(const char *arg)
3639{
3640 singlestep = 1;
3641}
3642
3643static void handle_arg_strace(const char *arg)
3644{
3645 do_strace = 1;
3646}
3647
3648static void handle_arg_version(const char *arg)
3649{
2e59915d 3650 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
fc9c5412 3651 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
1386d4c0 3652 exit(0);
fc9c5412
JS		 3653}
3654
3655struct qemu_argument {
3656 const char *argv;
3657 const char *env;
3658 bool has_arg;
3659 void (*handle_opt)(const char *arg);
3660 const char *example;
3661 const char *help;
3662};
3663
42644cee 3664static const struct qemu_argument arg_table[] = {
fc9c5412
JS		 3665 {"h", "", false, handle_arg_help,
3666 "", "print this help"},
3667 {"g", "QEMU_GDB", true, handle_arg_gdb,
3668 "port", "wait gdb connection to 'port'"},
3669 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3670 "path", "set the elf interpreter prefix to 'path'"},
3671 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3672 "size", "set the stack size to 'size' bytes"},
3673 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
c8057f95 3674 "model", "select CPU (-cpu help for list)"},
fc9c5412
JS		 3675 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3676 "var=value", "sets targets environment variable (see below)"},
3677 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3678 "var", "unsets targets environment variable (see below)"},
3679 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3680 "argv0", "forces target process argv[0] to be 'argv0'"},
3681 {"r", "QEMU_UNAME", true, handle_arg_uname,
3682 "uname", "set qemu uname release string to 'uname'"},
3683#if defined(CONFIG_USE_GUEST_BASE)
3684 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3685 "address", "set guest_base address to 'address'"},
3686 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3687 "size", "reserve 'size' bytes for guest virtual address space"},
3688#endif
3689 {"d", "QEMU_LOG", true, handle_arg_log,
989b697d
PM		 3690 "item[,...]", "enable logging of specified items "
3691 "(use '-d help' for a list of items)"},
50171d42 3692 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
989b697d 3693 "logfile", "write logs to 'logfile' (default stderr)"},
fc9c5412
JS		 3694 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3695 "pagesize", "set the host page size to 'pagesize'"},
3696 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3697 "", "run in singlestep mode"},
3698 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3699 "", "log system calls"},
c5e4a5a9
MR		 3700 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
3701 "", "Seed for pseudo-random number generator"},
fc9c5412 3702 {"version", "QEMU_VERSION", false, handle_arg_version,
1386d4c0 3703 "", "display version information and exit"},
fc9c5412
JS		 3704 {NULL, NULL, false, NULL, NULL, NULL}
3705};
3706
3707static void usage(void)
3708{
42644cee 3709 const struct qemu_argument *arginfo;
fc9c5412
JS		 3710 int maxarglen;
3711 int maxenvlen;
3712
2e59915d
PB		 3713 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3714 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
fc9c5412
JS		 3715 "\n"
3716 "Options and associated environment variables:\n"
3717 "\n");
3718
63ec54d7
PM		 3719 /* Calculate column widths. We must always have at least enough space
3720 * for the column header.
3721 */
3722 maxarglen = strlen("Argument");
3723 maxenvlen = strlen("Env-variable");
fc9c5412
JS		 3724
3725 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
63ec54d7
PM		 3726 int arglen = strlen(arginfo->argv);
3727 if (arginfo->has_arg) {
3728 arglen += strlen(arginfo->example) + 1;
3729 }
fc9c5412
JS		 3730 if (strlen(arginfo->env) > maxenvlen) {
3731 maxenvlen = strlen(arginfo->env);
3732 }
63ec54d7
PM		 3733 if (arglen > maxarglen) {
3734 maxarglen = arglen;
fc9c5412
JS		 3735 }
3736 }
3737
63ec54d7
PM		 3738 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3739 maxenvlen, "Env-variable");
fc9c5412
JS		 3740
3741 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3742 if (arginfo->has_arg) {
3743 printf("-%s %-*s %-*s %s\n", arginfo->argv,
63ec54d7
PM		 3744 (int)(maxarglen - strlen(arginfo->argv) - 1),
3745 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
fc9c5412 3746 } else {
63ec54d7 3747 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
fc9c5412
JS		 3748 maxenvlen, arginfo->env,
3749 arginfo->help);
3750 }
3751 }
3752
3753 printf("\n"
3754 "Defaults:\n"
3755 "QEMU_LD_PREFIX = %s\n"
989b697d 3756 "QEMU_STACK_SIZE = %ld byte\n",
fc9c5412 3757 interp_prefix,
989b697d 3758 guest_stack_size);
fc9c5412
JS		 3759
3760 printf("\n"
3761 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3762 "QEMU_UNSET_ENV environment variables to set and unset\n"
3763 "environment variables for the target process.\n"
3764 "It is possible to provide several variables by separating them\n"
3765 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3766 "provide the -E and -U options multiple times.\n"
3767 "The following lines are equivalent:\n"
3768 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3769 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3770 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3771 "Note that if you provide several changes to a single variable\n"
3772 "the last change will stay in effect.\n");
3773
3774 exit(1);
3775}
3776
3777static int parse_args(int argc, char **argv)
3778{
3779 const char *r;
3780 int optind;
42644cee 3781 const struct qemu_argument *arginfo;
fc9c5412
JS		 3782
3783 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3784 if (arginfo->env == NULL) {
3785 continue;
3786 }
3787
3788 r = getenv(arginfo->env);
3789 if (r != NULL) {
3790 arginfo->handle_opt(r);
3791 }
3792 }
3793
3794 optind = 1;
3795 for (;;) {
3796 if (optind >= argc) {
3797 break;
3798 }
3799 r = argv[optind];
3800 if (r[0] != '-') {
3801 break;
3802 }
3803 optind++;
3804 r++;
3805 if (!strcmp(r, "-")) {
3806 break;
3807 }
3808
3809 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3810 if (!strcmp(r, arginfo->argv)) {
fc9c5412 3811 if (arginfo->has_arg) {
1386d4c0
PM		 3812 if (optind >= argc) {
3813 usage();
3814 }
3815 arginfo->handle_opt(argv[optind]);
fc9c5412 3816 optind++;
1386d4c0
PM		 3817 } else {
3818 arginfo->handle_opt(NULL);
fc9c5412 3819 }
fc9c5412
JS		 3820 break;
3821 }
3822 }
3823
3824 /* no option matched the current argv */
3825 if (arginfo->handle_opt == NULL) {
3826 usage();
3827 }
3828 }
3829
3830 if (optind >= argc) {
3831 usage();
3832 }
3833
3834 filename = argv[optind];
3835 exec_path = argv[optind];
3836
3837 return optind;
3838}
3839
902b3d5c 3840int main(int argc, char **argv, char **envp)
31e31b8a 3841{
01ffc75b 3842 struct target_pt_regs regs1, *regs = &regs1;
31e31b8a 3843 struct image_info info1, *info = &info1;
edf8e2af 3844 struct linux_binprm bprm;
48e15fc2 3845 TaskState *ts;
9349b4f9 3846 CPUArchState *env;
db6b81d4 3847 CPUState *cpu;
586314f2 3848 int optind;
04a6dfeb 3849 char **target_environ, **wrk;
7d8cec95
AJ		 3850 char **target_argv;
3851 int target_argc;
7d8cec95 3852 int i;
fd4d81dd 3853 int ret;
03cfd8fa 3854 int execfd;
b12b6a18 3855
ce008c1f
AF		 3856 module_call_init(MODULE_INIT_QOM);
3857
04a6dfeb
AJ		 3858 if ((envlist = envlist_create()) == NULL) {
3859 (void) fprintf(stderr, "Unable to allocate envlist\n");
3860 exit(1);
3861 }
3862
3863 /* add current environment into the list */
3864 for (wrk = environ; *wrk != NULL; wrk++) {
3865 (void) envlist_setenv(envlist, *wrk);
3866 }
3867
703e0e89
RH		 3868 /* Read the stack limit from the kernel. If it's "unlimited",
3869 then we can do little else besides use the default. */
3870 {
3871 struct rlimit lim;
3872 if (getrlimit(RLIMIT_STACK, &lim) == 0
81bbe906
TY		 3873 && lim.rlim_cur != RLIM_INFINITY
3874 && lim.rlim_cur == (target_long)lim.rlim_cur) {
703e0e89
RH		 3875 guest_stack_size = lim.rlim_cur;
3876 }
3877 }
3878
b1f9be31 3879 cpu_model = NULL;
b5ec5ce0 3880#if defined(cpudef_setup)
3881 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3882#endif
3883
c5e4a5a9
MR		 3884 srand(time(NULL));
3885
fc9c5412 3886 optind = parse_args(argc, argv);
586314f2 3887
31e31b8a 3888 /* Zero out regs */
01ffc75b 3889 memset(regs, 0, sizeof(struct target_pt_regs));
31e31b8a
FB		 3890
3891 /* Zero out image_info */
3892 memset(info, 0, sizeof(struct image_info));
3893
edf8e2af
MW		 3894 memset(&bprm, 0, sizeof (bprm));
3895
74cd30b8
FB		 3896 /* Scan interp_prefix dir for replacement files. */
3897 init_paths(interp_prefix);
3898
4a24a758
PM		 3899 init_qemu_uname_release();
3900
46027c07 3901 if (cpu_model == NULL) {
aaed909a 3902#if defined(TARGET_I386)
46027c07
FB		 3903#ifdef TARGET_X86_64
3904 cpu_model = "qemu64";
3905#else
3906 cpu_model = "qemu32";
3907#endif
aaed909a 3908#elif defined(TARGET_ARM)
088ab16c 3909 cpu_model = "any";
d2fbca94
GX		 3910#elif defined(TARGET_UNICORE32)
3911 cpu_model = "any";
aaed909a
FB		 3912#elif defined(TARGET_M68K)
3913 cpu_model = "any";
3914#elif defined(TARGET_SPARC)
3915#ifdef TARGET_SPARC64
3916 cpu_model = "TI UltraSparc II";
3917#else
3918 cpu_model = "Fujitsu MB86904";
46027c07 3919#endif
aaed909a
FB		 3920#elif defined(TARGET_MIPS)
3921#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
74797f40 3922 cpu_model = "5KEf";
aaed909a
FB		 3923#else
3924 cpu_model = "24Kf";
3925#endif
d962783e
JL		 3926#elif defined TARGET_OPENRISC
3927 cpu_model = "or1200";
aaed909a 3928#elif defined(TARGET_PPC)
a74029f6
RH		 3929# ifdef TARGET_PPC64
3930 cpu_model = "POWER7";
3931# else
aaed909a 3932 cpu_model = "750";
a74029f6 3933# endif
aaed909a
FB		 3934#else
3935 cpu_model = "any";
3936#endif
3937 }
d5ab9713
JK		 3938 tcg_exec_init(0);
3939 cpu_exec_init_all();
83fb7adf
FB		 3940 /* NOTE: we need to init the CPU at this stage to get
3941 qemu_host_page_size */
aaed909a
FB		 3942 env = cpu_init(cpu_model);
3943 if (!env) {
3944 fprintf(stderr, "Unable to find CPU definition\n");
3945 exit(1);
3946 }
db6b81d4 3947 cpu = ENV_GET_CPU(env);
0ac46af3 3948 cpu_reset(cpu);
b55a37c9 3949
db6b81d4 3950 thread_cpu = cpu;
3b46e624 3951
b6741956
FB		 3952 if (getenv("QEMU_STRACE")) {
3953 do_strace = 1;
b92c47c1
TS		 3954 }
3955
c5e4a5a9
MR		 3956 if (getenv("QEMU_RAND_SEED")) {
3957 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
3958 }
3959
04a6dfeb
AJ		 3960 target_environ = envlist_to_environ(envlist, NULL);
3961 envlist_free(envlist);
b12b6a18 3962
379f6698
PB		 3963#if defined(CONFIG_USE_GUEST_BASE)
3964 /*
3965 * Now that page sizes are configured in cpu_init() we can do
3966 * proper page alignment for guest_base.
3967 */
3968 guest_base = HOST_PAGE_ALIGN(guest_base);
68a1c816 3969
806d1021
MI		 3970 if (reserved_va || have_guest_base) {
3971 guest_base = init_guest_space(guest_base, reserved_va, 0,
3972 have_guest_base);
3973 if (guest_base == (unsigned long)-1) {
097b8cb8
PM		 3974 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
3975 "space for use as guest address space (check your virtual "
3976 "memory ulimit setting or reserve less using -R option)\n",
3977 reserved_va);
68a1c816
PB		 3978 exit(1);
3979 }
97cc7560 3980
806d1021
MI		 3981 if (reserved_va) {
3982 mmap_next_start = reserved_va;
97cc7560
DDAG		 3983 }
3984 }
14f24e14 3985#endif /* CONFIG_USE_GUEST_BASE */
379f6698
PB		 3986
3987 /*
3988 * Read in mmap_min_addr kernel parameter. This value is used
3989 * When loading the ELF image to determine whether guest_base
14f24e14 3990 * is needed. It is also used in mmap_find_vma.
379f6698 3991 */
14f24e14 3992 {
379f6698
PB		 3993 FILE *fp;
3994
3995 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
3996 unsigned long tmp;
3997 if (fscanf(fp, "%lu", &tmp) == 1) {
3998 mmap_min_addr = tmp;
3999 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
4000 }
4001 fclose(fp);
4002 }
4003 }
379f6698 4004
7d8cec95
AJ		 4005 /*
4006 * Prepare copy of argv vector for target.
4007 */
4008 target_argc = argc - optind;
4009 target_argv = calloc(target_argc + 1, sizeof (char *));
4010 if (target_argv == NULL) {
4011 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4012 exit(1);
4013 }
4014
4015 /*
4016 * If argv0 is specified (using '-0' switch) we replace
4017 * argv[0] pointer with the given one.
4018 */
4019 i = 0;
4020 if (argv0 != NULL) {
4021 target_argv[i++] = strdup(argv0);
4022 }
4023 for (; i < target_argc; i++) {
4024 target_argv[i] = strdup(argv[optind + i]);
4025 }
4026 target_argv[target_argc] = NULL;
4027
7267c094 4028 ts = g_malloc0 (sizeof(TaskState));
edf8e2af
MW		 4029 init_task_state(ts);
4030 /* build Task State */
4031 ts->info = info;
4032 ts->bprm = &bprm;
0429a971 4033 cpu->opaque = ts;
edf8e2af
MW		 4034 task_settid(ts);
4035
0b959cf5
RH		 4036 execfd = qemu_getauxval(AT_EXECFD);
4037 if (execfd == 0) {
03cfd8fa 4038 execfd = open(filename, O_RDONLY);
0b959cf5
RH		 4039 if (execfd < 0) {
4040 printf("Error while loading %s: %s\n", filename, strerror(errno));
4041 _exit(1);
4042 }
03cfd8fa
LV		 4043 }
4044
4045 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
fd4d81dd
AP		 4046 info, &bprm);
4047 if (ret != 0) {
885c1d10 4048 printf("Error while loading %s: %s\n", filename, strerror(-ret));
b12b6a18
TS		 4049 _exit(1);
4050 }
4051
4052 for (wrk = target_environ; *wrk; wrk++) {
4053 free(*wrk);
31e31b8a 4054 }
3b46e624 4055
b12b6a18
TS		 4056 free(target_environ);
4057
2e77eac6 4058 if (qemu_log_enabled()) {
379f6698
PB		 4059#if defined(CONFIG_USE_GUEST_BASE)
4060 qemu_log("guest_base 0x%lx\n", guest_base);
4061#endif
2e77eac6
BS		 4062 log_page_dump();
4063
4064 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4065 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4066 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4067 info->start_code);
4068 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4069 info->start_data);
4070 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4071 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4072 info->start_stack);
4073 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4074 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4075 }
31e31b8a 4076
53a5960a 4077 target_set_brk(info->brk);
31e31b8a 4078 syscall_init();
66fb9763 4079 signal_init();
31e31b8a 4080
9002ec79
RH		 4081#if defined(CONFIG_USE_GUEST_BASE)
4082 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4083 generating the prologue until now so that the prologue can take
4084 the real value of GUEST_BASE into account. */
4085 tcg_prologue_init(&tcg_ctx);
4086#endif
4087
b346ff46 4088#if defined(TARGET_I386)
3802ce26 4089 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
b98dbc90 4090 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
0514ef2f 4091 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
1bde465e
FB		 4092 env->cr[4] |= CR4_OSFXSR_MASK;
4093 env->hflags |= HF_OSFXSR_MASK;
4094 }
d2fd1af7 4095#ifndef TARGET_ABI32
4dbc422b 4096 /* enable 64 bit mode if possible */
0514ef2f 4097 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4dbc422b
FB		 4098 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4099 exit(1);
4100 }
d2fd1af7 4101 env->cr[4] |= CR4_PAE_MASK;
4dbc422b 4102 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
d2fd1af7
FB		 4103 env->hflags |= HF_LMA_MASK;
4104#endif
1bde465e 4105
415e561f
FB		 4106 /* flags setup : we activate the IRQs by default as in user mode */
4107 env->eflags |= IF_MASK;
3b46e624 4108
6dbad63e 4109 /* linux register setup */
d2fd1af7 4110#ifndef TARGET_ABI32
84409ddb
JM		 4111 env->regs[R_EAX] = regs->rax;
4112 env->regs[R_EBX] = regs->rbx;
4113 env->regs[R_ECX] = regs->rcx;
4114 env->regs[R_EDX] = regs->rdx;
4115 env->regs[R_ESI] = regs->rsi;
4116 env->regs[R_EDI] = regs->rdi;
4117 env->regs[R_EBP] = regs->rbp;
4118 env->regs[R_ESP] = regs->rsp;
4119 env->eip = regs->rip;
4120#else
0ecfa993
FB		 4121 env->regs[R_EAX] = regs->eax;
4122 env->regs[R_EBX] = regs->ebx;
4123 env->regs[R_ECX] = regs->ecx;
4124 env->regs[R_EDX] = regs->edx;
4125 env->regs[R_ESI] = regs->esi;
4126 env->regs[R_EDI] = regs->edi;
4127 env->regs[R_EBP] = regs->ebp;
4128 env->regs[R_ESP] = regs->esp;
dab2ed99 4129 env->eip = regs->eip;
84409ddb 4130#endif
31e31b8a 4131
f4beb510 4132 /* linux interrupt setup */
e441570f
AZ		 4133#ifndef TARGET_ABI32
4134 env->idt.limit = 511;
4135#else
4136 env->idt.limit = 255;
4137#endif
4138 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4139 PROT_READ|PROT_WRITE,
4140 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4141 idt_table = g2h(env->idt.base);
f4beb510
FB		 4142 set_idt(0, 0);
4143 set_idt(1, 0);
4144 set_idt(2, 0);
4145 set_idt(3, 3);
4146 set_idt(4, 3);
ec95da6c 4147 set_idt(5, 0);
f4beb510
FB		 4148 set_idt(6, 0);
4149 set_idt(7, 0);
4150 set_idt(8, 0);
4151 set_idt(9, 0);
4152 set_idt(10, 0);
4153 set_idt(11, 0);
4154 set_idt(12, 0);
4155 set_idt(13, 0);
4156 set_idt(14, 0);
4157 set_idt(15, 0);
4158 set_idt(16, 0);
4159 set_idt(17, 0);
4160 set_idt(18, 0);
4161 set_idt(19, 0);
4162 set_idt(0x80, 3);
4163
6dbad63e 4164 /* linux segment setup */
8d18e893
FB		 4165 {
4166 uint64_t *gdt_table;
e441570f
AZ		 4167 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4168 PROT_READ|PROT_WRITE,
4169 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
8d18e893 4170 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
e441570f 4171 gdt_table = g2h(env->gdt.base);
d2fd1af7 4172#ifdef TARGET_ABI32
8d18e893
FB		 4173 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4174 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4175 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
d2fd1af7
FB		 4176#else
4177 /* 64 bit code segment */
4178 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4179 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4180 DESC_L_MASK |
4181 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4182#endif
8d18e893
FB		 4183 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4184 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4185 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4186 }
6dbad63e 4187 cpu_x86_load_seg(env, R_CS, __USER_CS);
d2fd1af7
FB		 4188 cpu_x86_load_seg(env, R_SS, __USER_DS);
4189#ifdef TARGET_ABI32
6dbad63e
FB		 4190 cpu_x86_load_seg(env, R_DS, __USER_DS);
4191 cpu_x86_load_seg(env, R_ES, __USER_DS);
6dbad63e
FB		 4192 cpu_x86_load_seg(env, R_FS, __USER_DS);
4193 cpu_x86_load_seg(env, R_GS, __USER_DS);
d6eb40f6
TS		 4194 /* This hack makes Wine work... */
4195 env->segs[R_FS].selector = 0;
d2fd1af7
FB		 4196#else
4197 cpu_x86_load_seg(env, R_DS, 0);
4198 cpu_x86_load_seg(env, R_ES, 0);
4199 cpu_x86_load_seg(env, R_FS, 0);
4200 cpu_x86_load_seg(env, R_GS, 0);
4201#endif
99033cae
AG		 4202#elif defined(TARGET_AARCH64)
4203 {
4204 int i;
4205
4206 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4207 fprintf(stderr,
4208 "The selected ARM CPU does not support 64 bit mode\n");
4209 exit(1);
4210 }
4211
4212 for (i = 0; i < 31; i++) {
4213 env->xregs[i] = regs->regs[i];
4214 }
4215 env->pc = regs->pc;
4216 env->xregs[31] = regs->sp;
4217 }
b346ff46
FB		 4218#elif defined(TARGET_ARM)
4219 {
4220 int i;
b5ff1b31 4221 cpsr_write(env, regs->uregs[16], 0xffffffff);
b346ff46
FB		 4222 for(i = 0; i < 16; i++) {
4223 env->regs[i] = regs->uregs[i];
4224 }
d8fd2954
PB		 4225 /* Enable BE8. */
4226 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4227 && (info->elf_flags & EF_ARM_BE8)) {
4228 env->bswap_code = 1;
4229 }
b346ff46 4230 }
d2fbca94
GX		 4231#elif defined(TARGET_UNICORE32)
4232 {
4233 int i;
4234 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4235 for (i = 0; i < 32; i++) {
4236 env->regs[i] = regs->uregs[i];
4237 }
4238 }
93ac68bc 4239#elif defined(TARGET_SPARC)
060366c5
FB		 4240 {
4241 int i;
4242 env->pc = regs->pc;
4243 env->npc = regs->npc;
4244 env->y = regs->y;
4245 for(i = 0; i < 8; i++)
4246 env->gregs[i] = regs->u_regs[i];
4247 for(i = 0; i < 8; i++)
4248 env->regwptr[i] = regs->u_regs[i + 8];
4249 }
67867308
FB		 4250#elif defined(TARGET_PPC)
4251 {
4252 int i;
3fc6c082 4253
0411a972
JM		 4254#if defined(TARGET_PPC64)
4255#if defined(TARGET_ABI32)
4256 env->msr &= ~((target_ulong)1 << MSR_SF);
e85e7c6e 4257#else
0411a972
JM		 4258 env->msr |= (target_ulong)1 << MSR_SF;
4259#endif
84409ddb 4260#endif
67867308
FB		 4261 env->nip = regs->nip;
4262 for(i = 0; i < 32; i++) {
4263 env->gpr[i] = regs->gpr[i];
4264 }
4265 }
e6e5906b
PB		 4266#elif defined(TARGET_M68K)
4267 {
e6e5906b
PB		 4268 env->pc = regs->pc;
4269 env->dregs[0] = regs->d0;
4270 env->dregs[1] = regs->d1;
4271 env->dregs[2] = regs->d2;
4272 env->dregs[3] = regs->d3;
4273 env->dregs[4] = regs->d4;
4274 env->dregs[5] = regs->d5;
4275 env->dregs[6] = regs->d6;
4276 env->dregs[7] = regs->d7;
4277 env->aregs[0] = regs->a0;
4278 env->aregs[1] = regs->a1;
4279 env->aregs[2] = regs->a2;
4280 env->aregs[3] = regs->a3;
4281 env->aregs[4] = regs->a4;
4282 env->aregs[5] = regs->a5;
4283 env->aregs[6] = regs->a6;
4284 env->aregs[7] = regs->usp;
4285 env->sr = regs->sr;
4286 ts->sim_syscalls = 1;
4287 }
b779e29e
EI		 4288#elif defined(TARGET_MICROBLAZE)
4289 {
4290 env->regs[0] = regs->r0;
4291 env->regs[1] = regs->r1;
4292 env->regs[2] = regs->r2;
4293 env->regs[3] = regs->r3;
4294 env->regs[4] = regs->r4;
4295 env->regs[5] = regs->r5;
4296 env->regs[6] = regs->r6;
4297 env->regs[7] = regs->r7;
4298 env->regs[8] = regs->r8;
4299 env->regs[9] = regs->r9;
4300 env->regs[10] = regs->r10;
4301 env->regs[11] = regs->r11;
4302 env->regs[12] = regs->r12;
4303 env->regs[13] = regs->r13;
4304 env->regs[14] = regs->r14;
4305 env->regs[15] = regs->r15;
4306 env->regs[16] = regs->r16;
4307 env->regs[17] = regs->r17;
4308 env->regs[18] = regs->r18;
4309 env->regs[19] = regs->r19;
4310 env->regs[20] = regs->r20;
4311 env->regs[21] = regs->r21;
4312 env->regs[22] = regs->r22;
4313 env->regs[23] = regs->r23;
4314 env->regs[24] = regs->r24;
4315 env->regs[25] = regs->r25;
4316 env->regs[26] = regs->r26;
4317 env->regs[27] = regs->r27;
4318 env->regs[28] = regs->r28;
4319 env->regs[29] = regs->r29;
4320 env->regs[30] = regs->r30;
4321 env->regs[31] = regs->r31;
4322 env->sregs[SR_PC] = regs->pc;
4323 }
048f6b4d
FB		 4324#elif defined(TARGET_MIPS)
4325 {
4326 int i;
4327
4328 for(i = 0; i < 32; i++) {
b5dc7732 4329 env->active_tc.gpr[i] = regs->regs[i];
048f6b4d 4330 }
0fddbbf2
NF		 4331 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4332 if (regs->cp0_epc & 1) {
4333 env->hflags |= MIPS_HFLAG_M16;
4334 }
048f6b4d 4335 }
d962783e
JL		 4336#elif defined(TARGET_OPENRISC)
4337 {
4338 int i;
4339
4340 for (i = 0; i < 32; i++) {
4341 env->gpr[i] = regs->gpr[i];
4342 }
4343
4344 env->sr = regs->sr;
4345 env->pc = regs->pc;
4346 }
fdf9b3e8
FB		 4347#elif defined(TARGET_SH4)
4348 {
4349 int i;
4350
4351 for(i = 0; i < 16; i++) {
4352 env->gregs[i] = regs->regs[i];
4353 }
4354 env->pc = regs->pc;
4355 }
7a3148a9
JM		 4356#elif defined(TARGET_ALPHA)
4357 {
4358 int i;
4359
4360 for(i = 0; i < 28; i++) {
992f48a0 4361 env->ir[i] = ((abi_ulong *)regs)[i];
7a3148a9 4362 }
dad081ee 4363 env->ir[IR_SP] = regs->usp;
7a3148a9 4364 env->pc = regs->pc;
7a3148a9 4365 }
48733d19
TS		 4366#elif defined(TARGET_CRIS)
4367 {
4368 env->regs[0] = regs->r0;
4369 env->regs[1] = regs->r1;
4370 env->regs[2] = regs->r2;
4371 env->regs[3] = regs->r3;
4372 env->regs[4] = regs->r4;
4373 env->regs[5] = regs->r5;
4374 env->regs[6] = regs->r6;
4375 env->regs[7] = regs->r7;
4376 env->regs[8] = regs->r8;
4377 env->regs[9] = regs->r9;
4378 env->regs[10] = regs->r10;
4379 env->regs[11] = regs->r11;
4380 env->regs[12] = regs->r12;
4381 env->regs[13] = regs->r13;
4382 env->regs[14] = info->start_stack;
4383 env->regs[15] = regs->acr;
4384 env->pc = regs->erp;
4385 }
a4c075f1
UH		 4386#elif defined(TARGET_S390X)
4387 {
4388 int i;
4389 for (i = 0; i < 16; i++) {
4390 env->regs[i] = regs->gprs[i];
4391 }
4392 env->psw.mask = regs->psw.mask;
4393 env->psw.addr = regs->psw.addr;
4394 }
b346ff46
FB		 4395#else
4396#error unsupported target CPU
4397#endif
31e31b8a 4398
d2fbca94 4399#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
a87295e8
PB		 4400 ts->stack_base = info->start_stack;
4401 ts->heap_base = info->brk;
4402 /* This will be filled in on the first SYS_HEAPINFO call. */
4403 ts->heap_limit = 0;
4404#endif
4405
74c33bed 4406 if (gdbstub_port) {
ff7a981a
PM		 4407 if (gdbserver_start(gdbstub_port) < 0) {
4408 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4409 gdbstub_port);
4410 exit(1);
4411 }
db6b81d4 4412 gdb_handlesig(cpu, 0);
1fddef4b 4413 }
1b6b029e
FB		 4414 cpu_loop(env);
4415 /* never exits */
31e31b8a
FB		 4416 return 0;
4417}
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