]>
Commit | Line | Data |
---|---|---|
31e31b8a | 1 | /* |
93ac68bc | 2 | * qemu user main |
5fafdf24 | 3 | * |
68d0f70e | 4 | * Copyright (c) 2003-2008 Fabrice Bellard |
31e31b8a FB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
8167ee88 | 17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
31e31b8a FB |
18 | */ |
19 | #include <stdlib.h> | |
20 | #include <stdio.h> | |
21 | #include <stdarg.h> | |
04369ff2 | 22 | #include <string.h> |
31e31b8a | 23 | #include <errno.h> |
0ecfa993 | 24 | #include <unistd.h> |
e441570f | 25 | #include <sys/mman.h> |
edf8e2af | 26 | #include <sys/syscall.h> |
703e0e89 | 27 | #include <sys/resource.h> |
31e31b8a | 28 | |
3ef693a0 | 29 | #include "qemu.h" |
ca10f867 | 30 | #include "qemu-common.h" |
1de7afc9 | 31 | #include "qemu/cache-utils.h" |
2b41f10e | 32 | #include "cpu.h" |
9002ec79 | 33 | #include "tcg.h" |
1de7afc9 PB |
34 | #include "qemu/timer.h" |
35 | #include "qemu/envlist.h" | |
d8fd2954 | 36 | #include "elf.h" |
04a6dfeb | 37 | |
d088d664 AJ |
38 | char *exec_path; |
39 | ||
1b530a6d | 40 | int singlestep; |
fc9c5412 JS |
41 | const char *filename; |
42 | const char *argv0; | |
43 | int gdbstub_port; | |
44 | envlist_t *envlist; | |
45 | const char *cpu_model; | |
379f6698 | 46 | unsigned long mmap_min_addr; |
14f24e14 | 47 | #if defined(CONFIG_USE_GUEST_BASE) |
379f6698 PB |
48 | unsigned long guest_base; |
49 | int have_guest_base; | |
288e65b9 AG |
50 | #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64) |
51 | /* | |
52 | * When running 32-on-64 we should make sure we can fit all of the possible | |
53 | * guest address space into a contiguous chunk of virtual host memory. | |
54 | * | |
55 | * This way we will never overlap with our own libraries or binaries or stack | |
56 | * or anything else that QEMU maps. | |
57 | */ | |
314992b1 AG |
58 | # ifdef TARGET_MIPS |
59 | /* MIPS only supports 31 bits of virtual address space for user space */ | |
60 | unsigned long reserved_va = 0x77000000; | |
61 | # else | |
288e65b9 | 62 | unsigned long reserved_va = 0xf7000000; |
314992b1 | 63 | # endif |
288e65b9 | 64 | #else |
68a1c816 | 65 | unsigned long reserved_va; |
379f6698 | 66 | #endif |
288e65b9 | 67 | #endif |
1b530a6d | 68 | |
fc9c5412 JS |
69 | static void usage(void); |
70 | ||
7ee2822c | 71 | static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX; |
c5937220 | 72 | const char *qemu_uname_release = CONFIG_UNAME_RELEASE; |
586314f2 | 73 | |
9de5e440 FB |
74 | /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so |
75 | we allocate a bigger stack. Need a better solution, for example | |
76 | by remapping the process stack directly at the right place */ | |
703e0e89 | 77 | unsigned long guest_stack_size = 8 * 1024 * 1024UL; |
31e31b8a FB |
78 | |
79 | void gemu_log(const char *fmt, ...) | |
80 | { | |
81 | va_list ap; | |
82 | ||
83 | va_start(ap, fmt); | |
84 | vfprintf(stderr, fmt, ap); | |
85 | va_end(ap); | |
86 | } | |
87 | ||
8fcd3692 | 88 | #if defined(TARGET_I386) |
05390248 | 89 | int cpu_get_pic_interrupt(CPUX86State *env) |
92ccca6a FB |
90 | { |
91 | return -1; | |
92 | } | |
8fcd3692 | 93 | #endif |
92ccca6a | 94 | |
2f7bb878 | 95 | #if defined(CONFIG_USE_NPTL) |
d5975363 PB |
96 | /***********************************************************/ |
97 | /* Helper routines for implementing atomic operations. */ | |
98 | ||
99 | /* To implement exclusive operations we force all cpus to syncronise. | |
100 | We don't require a full sync, only that no cpus are executing guest code. | |
101 | The alternative is to map target atomic ops onto host equivalents, | |
102 | which requires quite a lot of per host/target work. */ | |
c2764719 | 103 | static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER; |
d5975363 PB |
104 | static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER; |
105 | static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER; | |
106 | static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER; | |
107 | static int pending_cpus; | |
108 | ||
109 | /* Make sure everything is in a consistent state for calling fork(). */ | |
110 | void fork_start(void) | |
111 | { | |
5e5f07e0 | 112 | pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock); |
d5975363 | 113 | pthread_mutex_lock(&exclusive_lock); |
d032d1b4 | 114 | mmap_fork_start(); |
d5975363 PB |
115 | } |
116 | ||
117 | void fork_end(int child) | |
118 | { | |
d032d1b4 | 119 | mmap_fork_end(child); |
d5975363 PB |
120 | if (child) { |
121 | /* Child processes created by fork() only have a single thread. | |
122 | Discard information about the parent threads. */ | |
a2247f8e | 123 | first_cpu = thread_cpu; |
182735ef | 124 | first_cpu->next_cpu = NULL; |
d5975363 PB |
125 | pending_cpus = 0; |
126 | pthread_mutex_init(&exclusive_lock, NULL); | |
c2764719 | 127 | pthread_mutex_init(&cpu_list_mutex, NULL); |
d5975363 PB |
128 | pthread_cond_init(&exclusive_cond, NULL); |
129 | pthread_cond_init(&exclusive_resume, NULL); | |
5e5f07e0 | 130 | pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL); |
a2247f8e | 131 | gdbserver_fork((CPUArchState *)thread_cpu->env_ptr); |
d5975363 PB |
132 | } else { |
133 | pthread_mutex_unlock(&exclusive_lock); | |
5e5f07e0 | 134 | pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); |
d5975363 | 135 | } |
d5975363 PB |
136 | } |
137 | ||
138 | /* Wait for pending exclusive operations to complete. The exclusive lock | |
139 | must be held. */ | |
140 | static inline void exclusive_idle(void) | |
141 | { | |
142 | while (pending_cpus) { | |
143 | pthread_cond_wait(&exclusive_resume, &exclusive_lock); | |
144 | } | |
145 | } | |
146 | ||
147 | /* Start an exclusive operation. | |
148 | Must only be called from outside cpu_arm_exec. */ | |
149 | static inline void start_exclusive(void) | |
150 | { | |
0315c31c AF |
151 | CPUState *other_cpu; |
152 | ||
d5975363 PB |
153 | pthread_mutex_lock(&exclusive_lock); |
154 | exclusive_idle(); | |
155 | ||
156 | pending_cpus = 1; | |
157 | /* Make all other cpus stop executing. */ | |
182735ef | 158 | for (other_cpu = first_cpu; other_cpu; other_cpu = other_cpu->next_cpu) { |
0315c31c | 159 | if (other_cpu->running) { |
d5975363 | 160 | pending_cpus++; |
60a3e17a | 161 | cpu_exit(other_cpu); |
d5975363 PB |
162 | } |
163 | } | |
164 | if (pending_cpus > 1) { | |
165 | pthread_cond_wait(&exclusive_cond, &exclusive_lock); | |
166 | } | |
167 | } | |
168 | ||
169 | /* Finish an exclusive operation. */ | |
170 | static inline void end_exclusive(void) | |
171 | { | |
172 | pending_cpus = 0; | |
173 | pthread_cond_broadcast(&exclusive_resume); | |
174 | pthread_mutex_unlock(&exclusive_lock); | |
175 | } | |
176 | ||
177 | /* Wait for exclusive ops to finish, and begin cpu execution. */ | |
0315c31c | 178 | static inline void cpu_exec_start(CPUState *cpu) |
d5975363 PB |
179 | { |
180 | pthread_mutex_lock(&exclusive_lock); | |
181 | exclusive_idle(); | |
0315c31c | 182 | cpu->running = true; |
d5975363 PB |
183 | pthread_mutex_unlock(&exclusive_lock); |
184 | } | |
185 | ||
186 | /* Mark cpu as not executing, and release pending exclusive ops. */ | |
0315c31c | 187 | static inline void cpu_exec_end(CPUState *cpu) |
d5975363 PB |
188 | { |
189 | pthread_mutex_lock(&exclusive_lock); | |
0315c31c | 190 | cpu->running = false; |
d5975363 PB |
191 | if (pending_cpus > 1) { |
192 | pending_cpus--; | |
193 | if (pending_cpus == 1) { | |
194 | pthread_cond_signal(&exclusive_cond); | |
195 | } | |
196 | } | |
197 | exclusive_idle(); | |
198 | pthread_mutex_unlock(&exclusive_lock); | |
199 | } | |
c2764719 PB |
200 | |
201 | void cpu_list_lock(void) | |
202 | { | |
203 | pthread_mutex_lock(&cpu_list_mutex); | |
204 | } | |
205 | ||
206 | void cpu_list_unlock(void) | |
207 | { | |
208 | pthread_mutex_unlock(&cpu_list_mutex); | |
209 | } | |
2f7bb878 | 210 | #else /* if !CONFIG_USE_NPTL */ |
d5975363 | 211 | /* These are no-ops because we are not threadsafe. */ |
0315c31c | 212 | static inline void cpu_exec_start(CPUState *cpu) |
d5975363 PB |
213 | { |
214 | } | |
215 | ||
0315c31c | 216 | static inline void cpu_exec_end(CPUState *cpu) |
d5975363 PB |
217 | { |
218 | } | |
219 | ||
220 | static inline void start_exclusive(void) | |
221 | { | |
222 | } | |
223 | ||
224 | static inline void end_exclusive(void) | |
225 | { | |
226 | } | |
227 | ||
228 | void fork_start(void) | |
229 | { | |
230 | } | |
231 | ||
232 | void fork_end(int child) | |
233 | { | |
2b1319c8 | 234 | if (child) { |
a2247f8e | 235 | gdbserver_fork((CPUArchState *)thread_cpu->env_ptr); |
2b1319c8 | 236 | } |
d5975363 | 237 | } |
c2764719 PB |
238 | |
239 | void cpu_list_lock(void) | |
240 | { | |
241 | } | |
242 | ||
243 | void cpu_list_unlock(void) | |
244 | { | |
245 | } | |
d5975363 PB |
246 | #endif |
247 | ||
248 | ||
a541f297 FB |
249 | #ifdef TARGET_I386 |
250 | /***********************************************************/ | |
251 | /* CPUX86 core interface */ | |
252 | ||
05390248 | 253 | void cpu_smm_update(CPUX86State *env) |
02a1602e FB |
254 | { |
255 | } | |
256 | ||
28ab0e2e FB |
257 | uint64_t cpu_get_tsc(CPUX86State *env) |
258 | { | |
259 | return cpu_get_real_ticks(); | |
260 | } | |
261 | ||
5fafdf24 | 262 | static void write_dt(void *ptr, unsigned long addr, unsigned long limit, |
f4beb510 | 263 | int flags) |
6dbad63e | 264 | { |
f4beb510 | 265 | unsigned int e1, e2; |
53a5960a | 266 | uint32_t *p; |
6dbad63e FB |
267 | e1 = (addr << 16) | (limit & 0xffff); |
268 | e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000); | |
f4beb510 | 269 | e2 |= flags; |
53a5960a | 270 | p = ptr; |
d538e8f5 | 271 | p[0] = tswap32(e1); |
272 | p[1] = tswap32(e2); | |
f4beb510 FB |
273 | } |
274 | ||
e441570f | 275 | static uint64_t *idt_table; |
eb38c52c | 276 | #ifdef TARGET_X86_64 |
d2fd1af7 FB |
277 | static void set_gate64(void *ptr, unsigned int type, unsigned int dpl, |
278 | uint64_t addr, unsigned int sel) | |
f4beb510 | 279 | { |
4dbc422b | 280 | uint32_t *p, e1, e2; |
f4beb510 FB |
281 | e1 = (addr & 0xffff) | (sel << 16); |
282 | e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); | |
53a5960a | 283 | p = ptr; |
4dbc422b FB |
284 | p[0] = tswap32(e1); |
285 | p[1] = tswap32(e2); | |
286 | p[2] = tswap32(addr >> 32); | |
287 | p[3] = 0; | |
6dbad63e | 288 | } |
d2fd1af7 FB |
289 | /* only dpl matters as we do only user space emulation */ |
290 | static void set_idt(int n, unsigned int dpl) | |
291 | { | |
292 | set_gate64(idt_table + n * 2, 0, dpl, 0, 0); | |
293 | } | |
294 | #else | |
d2fd1af7 FB |
295 | static void set_gate(void *ptr, unsigned int type, unsigned int dpl, |
296 | uint32_t addr, unsigned int sel) | |
297 | { | |
4dbc422b | 298 | uint32_t *p, e1, e2; |
d2fd1af7 FB |
299 | e1 = (addr & 0xffff) | (sel << 16); |
300 | e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); | |
301 | p = ptr; | |
4dbc422b FB |
302 | p[0] = tswap32(e1); |
303 | p[1] = tswap32(e2); | |
d2fd1af7 FB |
304 | } |
305 | ||
f4beb510 FB |
306 | /* only dpl matters as we do only user space emulation */ |
307 | static void set_idt(int n, unsigned int dpl) | |
308 | { | |
309 | set_gate(idt_table + n, 0, dpl, 0, 0); | |
310 | } | |
d2fd1af7 | 311 | #endif |
31e31b8a | 312 | |
89e957e7 | 313 | void cpu_loop(CPUX86State *env) |
1b6b029e | 314 | { |
bc8a22cc | 315 | int trapnr; |
992f48a0 | 316 | abi_ulong pc; |
c227f099 | 317 | target_siginfo_t info; |
851e67a1 | 318 | |
1b6b029e | 319 | for(;;) { |
bc8a22cc | 320 | trapnr = cpu_x86_exec(env); |
bc8a22cc | 321 | switch(trapnr) { |
f4beb510 | 322 | case 0x80: |
d2fd1af7 | 323 | /* linux syscall from int $0x80 */ |
5fafdf24 TS |
324 | env->regs[R_EAX] = do_syscall(env, |
325 | env->regs[R_EAX], | |
f4beb510 FB |
326 | env->regs[R_EBX], |
327 | env->regs[R_ECX], | |
328 | env->regs[R_EDX], | |
329 | env->regs[R_ESI], | |
330 | env->regs[R_EDI], | |
5945cfcb PM |
331 | env->regs[R_EBP], |
332 | 0, 0); | |
f4beb510 | 333 | break; |
d2fd1af7 FB |
334 | #ifndef TARGET_ABI32 |
335 | case EXCP_SYSCALL: | |
5ba18547 | 336 | /* linux syscall from syscall instruction */ |
d2fd1af7 FB |
337 | env->regs[R_EAX] = do_syscall(env, |
338 | env->regs[R_EAX], | |
339 | env->regs[R_EDI], | |
340 | env->regs[R_ESI], | |
341 | env->regs[R_EDX], | |
342 | env->regs[10], | |
343 | env->regs[8], | |
5945cfcb PM |
344 | env->regs[9], |
345 | 0, 0); | |
d2fd1af7 FB |
346 | env->eip = env->exception_next_eip; |
347 | break; | |
348 | #endif | |
f4beb510 FB |
349 | case EXCP0B_NOSEG: |
350 | case EXCP0C_STACK: | |
351 | info.si_signo = SIGBUS; | |
352 | info.si_errno = 0; | |
353 | info.si_code = TARGET_SI_KERNEL; | |
354 | info._sifields._sigfault._addr = 0; | |
624f7979 | 355 | queue_signal(env, info.si_signo, &info); |
f4beb510 | 356 | break; |
1b6b029e | 357 | case EXCP0D_GPF: |
d2fd1af7 | 358 | /* XXX: potential problem if ABI32 */ |
84409ddb | 359 | #ifndef TARGET_X86_64 |
851e67a1 | 360 | if (env->eflags & VM_MASK) { |
89e957e7 | 361 | handle_vm86_fault(env); |
84409ddb JM |
362 | } else |
363 | #endif | |
364 | { | |
f4beb510 FB |
365 | info.si_signo = SIGSEGV; |
366 | info.si_errno = 0; | |
367 | info.si_code = TARGET_SI_KERNEL; | |
368 | info._sifields._sigfault._addr = 0; | |
624f7979 | 369 | queue_signal(env, info.si_signo, &info); |
1b6b029e FB |
370 | } |
371 | break; | |
b689bc57 FB |
372 | case EXCP0E_PAGE: |
373 | info.si_signo = SIGSEGV; | |
374 | info.si_errno = 0; | |
375 | if (!(env->error_code & 1)) | |
376 | info.si_code = TARGET_SEGV_MAPERR; | |
377 | else | |
378 | info.si_code = TARGET_SEGV_ACCERR; | |
970a87a6 | 379 | info._sifields._sigfault._addr = env->cr[2]; |
624f7979 | 380 | queue_signal(env, info.si_signo, &info); |
b689bc57 | 381 | break; |
9de5e440 | 382 | case EXCP00_DIVZ: |
84409ddb | 383 | #ifndef TARGET_X86_64 |
bc8a22cc | 384 | if (env->eflags & VM_MASK) { |
447db213 | 385 | handle_vm86_trap(env, trapnr); |
84409ddb JM |
386 | } else |
387 | #endif | |
388 | { | |
bc8a22cc FB |
389 | /* division by zero */ |
390 | info.si_signo = SIGFPE; | |
391 | info.si_errno = 0; | |
392 | info.si_code = TARGET_FPE_INTDIV; | |
393 | info._sifields._sigfault._addr = env->eip; | |
624f7979 | 394 | queue_signal(env, info.si_signo, &info); |
bc8a22cc | 395 | } |
9de5e440 | 396 | break; |
01df040b | 397 | case EXCP01_DB: |
447db213 | 398 | case EXCP03_INT3: |
84409ddb | 399 | #ifndef TARGET_X86_64 |
447db213 FB |
400 | if (env->eflags & VM_MASK) { |
401 | handle_vm86_trap(env, trapnr); | |
84409ddb JM |
402 | } else |
403 | #endif | |
404 | { | |
447db213 FB |
405 | info.si_signo = SIGTRAP; |
406 | info.si_errno = 0; | |
01df040b | 407 | if (trapnr == EXCP01_DB) { |
447db213 FB |
408 | info.si_code = TARGET_TRAP_BRKPT; |
409 | info._sifields._sigfault._addr = env->eip; | |
410 | } else { | |
411 | info.si_code = TARGET_SI_KERNEL; | |
412 | info._sifields._sigfault._addr = 0; | |
413 | } | |
624f7979 | 414 | queue_signal(env, info.si_signo, &info); |
447db213 FB |
415 | } |
416 | break; | |
9de5e440 FB |
417 | case EXCP04_INTO: |
418 | case EXCP05_BOUND: | |
84409ddb | 419 | #ifndef TARGET_X86_64 |
bc8a22cc | 420 | if (env->eflags & VM_MASK) { |
447db213 | 421 | handle_vm86_trap(env, trapnr); |
84409ddb JM |
422 | } else |
423 | #endif | |
424 | { | |
bc8a22cc FB |
425 | info.si_signo = SIGSEGV; |
426 | info.si_errno = 0; | |
b689bc57 | 427 | info.si_code = TARGET_SI_KERNEL; |
bc8a22cc | 428 | info._sifields._sigfault._addr = 0; |
624f7979 | 429 | queue_signal(env, info.si_signo, &info); |
bc8a22cc | 430 | } |
9de5e440 FB |
431 | break; |
432 | case EXCP06_ILLOP: | |
433 | info.si_signo = SIGILL; | |
434 | info.si_errno = 0; | |
435 | info.si_code = TARGET_ILL_ILLOPN; | |
436 | info._sifields._sigfault._addr = env->eip; | |
624f7979 | 437 | queue_signal(env, info.si_signo, &info); |
9de5e440 FB |
438 | break; |
439 | case EXCP_INTERRUPT: | |
440 | /* just indicate that signals should be handled asap */ | |
441 | break; | |
1fddef4b FB |
442 | case EXCP_DEBUG: |
443 | { | |
444 | int sig; | |
445 | ||
446 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
447 | if (sig) | |
448 | { | |
449 | info.si_signo = sig; | |
450 | info.si_errno = 0; | |
451 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 452 | queue_signal(env, info.si_signo, &info); |
1fddef4b FB |
453 | } |
454 | } | |
455 | break; | |
1b6b029e | 456 | default: |
970a87a6 | 457 | pc = env->segs[R_CS].base + env->eip; |
5fafdf24 | 458 | fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n", |
bc8a22cc | 459 | (long)pc, trapnr); |
1b6b029e FB |
460 | abort(); |
461 | } | |
66fb9763 | 462 | process_pending_signals(env); |
1b6b029e FB |
463 | } |
464 | } | |
b346ff46 FB |
465 | #endif |
466 | ||
467 | #ifdef TARGET_ARM | |
468 | ||
d8fd2954 PB |
469 | #define get_user_code_u32(x, gaddr, doswap) \ |
470 | ({ abi_long __r = get_user_u32((x), (gaddr)); \ | |
471 | if (!__r && (doswap)) { \ | |
472 | (x) = bswap32(x); \ | |
473 | } \ | |
474 | __r; \ | |
475 | }) | |
476 | ||
477 | #define get_user_code_u16(x, gaddr, doswap) \ | |
478 | ({ abi_long __r = get_user_u16((x), (gaddr)); \ | |
479 | if (!__r && (doswap)) { \ | |
480 | (x) = bswap16(x); \ | |
481 | } \ | |
482 | __r; \ | |
483 | }) | |
484 | ||
97cc7560 DDAG |
485 | /* |
486 | * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt | |
487 | * Input: | |
488 | * r0 = pointer to oldval | |
489 | * r1 = pointer to newval | |
490 | * r2 = pointer to target value | |
491 | * | |
492 | * Output: | |
493 | * r0 = 0 if *ptr was changed, non-0 if no exchange happened | |
494 | * C set if *ptr was changed, clear if no exchange happened | |
495 | * | |
496 | * Note segv's in kernel helpers are a bit tricky, we can set the | |
497 | * data address sensibly but the PC address is just the entry point. | |
498 | */ | |
499 | static void arm_kernel_cmpxchg64_helper(CPUARMState *env) | |
500 | { | |
501 | uint64_t oldval, newval, val; | |
502 | uint32_t addr, cpsr; | |
503 | target_siginfo_t info; | |
504 | ||
505 | /* Based on the 32 bit code in do_kernel_trap */ | |
506 | ||
507 | /* XXX: This only works between threads, not between processes. | |
508 | It's probably possible to implement this with native host | |
509 | operations. However things like ldrex/strex are much harder so | |
510 | there's not much point trying. */ | |
511 | start_exclusive(); | |
512 | cpsr = cpsr_read(env); | |
513 | addr = env->regs[2]; | |
514 | ||
515 | if (get_user_u64(oldval, env->regs[0])) { | |
516 | env->cp15.c6_data = env->regs[0]; | |
517 | goto segv; | |
518 | }; | |
519 | ||
520 | if (get_user_u64(newval, env->regs[1])) { | |
521 | env->cp15.c6_data = env->regs[1]; | |
522 | goto segv; | |
523 | }; | |
524 | ||
525 | if (get_user_u64(val, addr)) { | |
526 | env->cp15.c6_data = addr; | |
527 | goto segv; | |
528 | } | |
529 | ||
530 | if (val == oldval) { | |
531 | val = newval; | |
532 | ||
533 | if (put_user_u64(val, addr)) { | |
534 | env->cp15.c6_data = addr; | |
535 | goto segv; | |
536 | }; | |
537 | ||
538 | env->regs[0] = 0; | |
539 | cpsr |= CPSR_C; | |
540 | } else { | |
541 | env->regs[0] = -1; | |
542 | cpsr &= ~CPSR_C; | |
543 | } | |
544 | cpsr_write(env, cpsr, CPSR_C); | |
545 | end_exclusive(); | |
546 | return; | |
547 | ||
548 | segv: | |
549 | end_exclusive(); | |
550 | /* We get the PC of the entry address - which is as good as anything, | |
551 | on a real kernel what you get depends on which mode it uses. */ | |
552 | info.si_signo = SIGSEGV; | |
553 | info.si_errno = 0; | |
554 | /* XXX: check env->error_code */ | |
555 | info.si_code = TARGET_SEGV_MAPERR; | |
556 | info._sifields._sigfault._addr = env->cp15.c6_data; | |
557 | queue_signal(env, info.si_signo, &info); | |
558 | ||
559 | end_exclusive(); | |
560 | } | |
561 | ||
fbb4a2e3 PB |
562 | /* Handle a jump to the kernel code page. */ |
563 | static int | |
564 | do_kernel_trap(CPUARMState *env) | |
565 | { | |
566 | uint32_t addr; | |
567 | uint32_t cpsr; | |
568 | uint32_t val; | |
569 | ||
570 | switch (env->regs[15]) { | |
571 | case 0xffff0fa0: /* __kernel_memory_barrier */ | |
572 | /* ??? No-op. Will need to do better for SMP. */ | |
573 | break; | |
574 | case 0xffff0fc0: /* __kernel_cmpxchg */ | |
d5975363 PB |
575 | /* XXX: This only works between threads, not between processes. |
576 | It's probably possible to implement this with native host | |
577 | operations. However things like ldrex/strex are much harder so | |
578 | there's not much point trying. */ | |
579 | start_exclusive(); | |
fbb4a2e3 PB |
580 | cpsr = cpsr_read(env); |
581 | addr = env->regs[2]; | |
582 | /* FIXME: This should SEGV if the access fails. */ | |
583 | if (get_user_u32(val, addr)) | |
584 | val = ~env->regs[0]; | |
585 | if (val == env->regs[0]) { | |
586 | val = env->regs[1]; | |
587 | /* FIXME: Check for segfaults. */ | |
588 | put_user_u32(val, addr); | |
589 | env->regs[0] = 0; | |
590 | cpsr |= CPSR_C; | |
591 | } else { | |
592 | env->regs[0] = -1; | |
593 | cpsr &= ~CPSR_C; | |
594 | } | |
595 | cpsr_write(env, cpsr, CPSR_C); | |
d5975363 | 596 | end_exclusive(); |
fbb4a2e3 PB |
597 | break; |
598 | case 0xffff0fe0: /* __kernel_get_tls */ | |
599 | env->regs[0] = env->cp15.c13_tls2; | |
600 | break; | |
97cc7560 DDAG |
601 | case 0xffff0f60: /* __kernel_cmpxchg64 */ |
602 | arm_kernel_cmpxchg64_helper(env); | |
603 | break; | |
604 | ||
fbb4a2e3 PB |
605 | default: |
606 | return 1; | |
607 | } | |
608 | /* Jump back to the caller. */ | |
609 | addr = env->regs[14]; | |
610 | if (addr & 1) { | |
611 | env->thumb = 1; | |
612 | addr &= ~1; | |
613 | } | |
614 | env->regs[15] = addr; | |
615 | ||
616 | return 0; | |
617 | } | |
618 | ||
426f5abc PB |
619 | static int do_strex(CPUARMState *env) |
620 | { | |
621 | uint32_t val; | |
622 | int size; | |
623 | int rc = 1; | |
624 | int segv = 0; | |
625 | uint32_t addr; | |
626 | start_exclusive(); | |
627 | addr = env->exclusive_addr; | |
628 | if (addr != env->exclusive_test) { | |
629 | goto fail; | |
630 | } | |
631 | size = env->exclusive_info & 0xf; | |
632 | switch (size) { | |
633 | case 0: | |
634 | segv = get_user_u8(val, addr); | |
635 | break; | |
636 | case 1: | |
637 | segv = get_user_u16(val, addr); | |
638 | break; | |
639 | case 2: | |
640 | case 3: | |
641 | segv = get_user_u32(val, addr); | |
642 | break; | |
f7001a3b AJ |
643 | default: |
644 | abort(); | |
426f5abc PB |
645 | } |
646 | if (segv) { | |
647 | env->cp15.c6_data = addr; | |
648 | goto done; | |
649 | } | |
650 | if (val != env->exclusive_val) { | |
651 | goto fail; | |
652 | } | |
653 | if (size == 3) { | |
654 | segv = get_user_u32(val, addr + 4); | |
655 | if (segv) { | |
656 | env->cp15.c6_data = addr + 4; | |
657 | goto done; | |
658 | } | |
659 | if (val != env->exclusive_high) { | |
660 | goto fail; | |
661 | } | |
662 | } | |
663 | val = env->regs[(env->exclusive_info >> 8) & 0xf]; | |
664 | switch (size) { | |
665 | case 0: | |
666 | segv = put_user_u8(val, addr); | |
667 | break; | |
668 | case 1: | |
669 | segv = put_user_u16(val, addr); | |
670 | break; | |
671 | case 2: | |
672 | case 3: | |
673 | segv = put_user_u32(val, addr); | |
674 | break; | |
675 | } | |
676 | if (segv) { | |
677 | env->cp15.c6_data = addr; | |
678 | goto done; | |
679 | } | |
680 | if (size == 3) { | |
681 | val = env->regs[(env->exclusive_info >> 12) & 0xf]; | |
2c9adbda | 682 | segv = put_user_u32(val, addr + 4); |
426f5abc PB |
683 | if (segv) { |
684 | env->cp15.c6_data = addr + 4; | |
685 | goto done; | |
686 | } | |
687 | } | |
688 | rc = 0; | |
689 | fail: | |
725b8a69 | 690 | env->regs[15] += 4; |
426f5abc PB |
691 | env->regs[(env->exclusive_info >> 4) & 0xf] = rc; |
692 | done: | |
693 | end_exclusive(); | |
694 | return segv; | |
695 | } | |
696 | ||
b346ff46 FB |
697 | void cpu_loop(CPUARMState *env) |
698 | { | |
0315c31c | 699 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
b346ff46 FB |
700 | int trapnr; |
701 | unsigned int n, insn; | |
c227f099 | 702 | target_siginfo_t info; |
b5ff1b31 | 703 | uint32_t addr; |
3b46e624 | 704 | |
b346ff46 | 705 | for(;;) { |
0315c31c | 706 | cpu_exec_start(cs); |
b346ff46 | 707 | trapnr = cpu_arm_exec(env); |
0315c31c | 708 | cpu_exec_end(cs); |
b346ff46 FB |
709 | switch(trapnr) { |
710 | case EXCP_UDEF: | |
c6981055 FB |
711 | { |
712 | TaskState *ts = env->opaque; | |
713 | uint32_t opcode; | |
6d9a42be | 714 | int rc; |
c6981055 FB |
715 | |
716 | /* we handle the FPU emulation here, as Linux */ | |
717 | /* we get the opcode */ | |
2f619698 | 718 | /* FIXME - what to do if get_user() fails? */ |
d8fd2954 | 719 | get_user_code_u32(opcode, env->regs[15], env->bswap_code); |
3b46e624 | 720 | |
6d9a42be AJ |
721 | rc = EmulateAll(opcode, &ts->fpa, env); |
722 | if (rc == 0) { /* illegal instruction */ | |
c6981055 FB |
723 | info.si_signo = SIGILL; |
724 | info.si_errno = 0; | |
725 | info.si_code = TARGET_ILL_ILLOPN; | |
726 | info._sifields._sigfault._addr = env->regs[15]; | |
624f7979 | 727 | queue_signal(env, info.si_signo, &info); |
6d9a42be AJ |
728 | } else if (rc < 0) { /* FP exception */ |
729 | int arm_fpe=0; | |
730 | ||
731 | /* translate softfloat flags to FPSR flags */ | |
732 | if (-rc & float_flag_invalid) | |
733 | arm_fpe |= BIT_IOC; | |
734 | if (-rc & float_flag_divbyzero) | |
735 | arm_fpe |= BIT_DZC; | |
736 | if (-rc & float_flag_overflow) | |
737 | arm_fpe |= BIT_OFC; | |
738 | if (-rc & float_flag_underflow) | |
739 | arm_fpe |= BIT_UFC; | |
740 | if (-rc & float_flag_inexact) | |
741 | arm_fpe |= BIT_IXC; | |
742 | ||
743 | FPSR fpsr = ts->fpa.fpsr; | |
744 | //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe); | |
745 | ||
746 | if (fpsr & (arm_fpe << 16)) { /* exception enabled? */ | |
747 | info.si_signo = SIGFPE; | |
748 | info.si_errno = 0; | |
749 | ||
750 | /* ordered by priority, least first */ | |
751 | if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES; | |
752 | if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND; | |
753 | if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF; | |
754 | if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV; | |
755 | if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV; | |
756 | ||
757 | info._sifields._sigfault._addr = env->regs[15]; | |
624f7979 | 758 | queue_signal(env, info.si_signo, &info); |
6d9a42be AJ |
759 | } else { |
760 | env->regs[15] += 4; | |
761 | } | |
762 | ||
763 | /* accumulate unenabled exceptions */ | |
764 | if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC)) | |
765 | fpsr |= BIT_IXC; | |
766 | if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC)) | |
767 | fpsr |= BIT_UFC; | |
768 | if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC)) | |
769 | fpsr |= BIT_OFC; | |
770 | if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC)) | |
771 | fpsr |= BIT_DZC; | |
772 | if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC)) | |
773 | fpsr |= BIT_IOC; | |
774 | ts->fpa.fpsr=fpsr; | |
775 | } else { /* everything OK */ | |
c6981055 FB |
776 | /* increment PC */ |
777 | env->regs[15] += 4; | |
778 | } | |
779 | } | |
b346ff46 FB |
780 | break; |
781 | case EXCP_SWI: | |
06c949e6 | 782 | case EXCP_BKPT: |
b346ff46 | 783 | { |
ce4defa0 | 784 | env->eabi = 1; |
b346ff46 | 785 | /* system call */ |
06c949e6 PB |
786 | if (trapnr == EXCP_BKPT) { |
787 | if (env->thumb) { | |
2f619698 | 788 | /* FIXME - what to do if get_user() fails? */ |
d8fd2954 | 789 | get_user_code_u16(insn, env->regs[15], env->bswap_code); |
06c949e6 PB |
790 | n = insn & 0xff; |
791 | env->regs[15] += 2; | |
792 | } else { | |
2f619698 | 793 | /* FIXME - what to do if get_user() fails? */ |
d8fd2954 | 794 | get_user_code_u32(insn, env->regs[15], env->bswap_code); |
06c949e6 PB |
795 | n = (insn & 0xf) | ((insn >> 4) & 0xff0); |
796 | env->regs[15] += 4; | |
797 | } | |
192c7bd9 | 798 | } else { |
06c949e6 | 799 | if (env->thumb) { |
2f619698 | 800 | /* FIXME - what to do if get_user() fails? */ |
d8fd2954 PB |
801 | get_user_code_u16(insn, env->regs[15] - 2, |
802 | env->bswap_code); | |
06c949e6 PB |
803 | n = insn & 0xff; |
804 | } else { | |
2f619698 | 805 | /* FIXME - what to do if get_user() fails? */ |
d8fd2954 PB |
806 | get_user_code_u32(insn, env->regs[15] - 4, |
807 | env->bswap_code); | |
06c949e6 PB |
808 | n = insn & 0xffffff; |
809 | } | |
192c7bd9 FB |
810 | } |
811 | ||
6f1f31c0 | 812 | if (n == ARM_NR_cacheflush) { |
dcfd14b3 | 813 | /* nop */ |
a4f81979 FB |
814 | } else if (n == ARM_NR_semihosting |
815 | || n == ARM_NR_thumb_semihosting) { | |
816 | env->regs[0] = do_arm_semihosting (env); | |
3a1363ac | 817 | } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) { |
b346ff46 | 818 | /* linux syscall */ |
ce4defa0 | 819 | if (env->thumb || n == 0) { |
192c7bd9 FB |
820 | n = env->regs[7]; |
821 | } else { | |
822 | n -= ARM_SYSCALL_BASE; | |
ce4defa0 | 823 | env->eabi = 0; |
192c7bd9 | 824 | } |
fbb4a2e3 PB |
825 | if ( n > ARM_NR_BASE) { |
826 | switch (n) { | |
827 | case ARM_NR_cacheflush: | |
dcfd14b3 | 828 | /* nop */ |
fbb4a2e3 PB |
829 | break; |
830 | case ARM_NR_set_tls: | |
831 | cpu_set_tls(env, env->regs[0]); | |
832 | env->regs[0] = 0; | |
833 | break; | |
834 | default: | |
835 | gemu_log("qemu: Unsupported ARM syscall: 0x%x\n", | |
836 | n); | |
837 | env->regs[0] = -TARGET_ENOSYS; | |
838 | break; | |
839 | } | |
840 | } else { | |
841 | env->regs[0] = do_syscall(env, | |
842 | n, | |
843 | env->regs[0], | |
844 | env->regs[1], | |
845 | env->regs[2], | |
846 | env->regs[3], | |
847 | env->regs[4], | |
5945cfcb PM |
848 | env->regs[5], |
849 | 0, 0); | |
fbb4a2e3 | 850 | } |
b346ff46 FB |
851 | } else { |
852 | goto error; | |
853 | } | |
854 | } | |
855 | break; | |
43fff238 FB |
856 | case EXCP_INTERRUPT: |
857 | /* just indicate that signals should be handled asap */ | |
858 | break; | |
68016c62 | 859 | case EXCP_PREFETCH_ABORT: |
eae473c1 | 860 | addr = env->cp15.c6_insn; |
b5ff1b31 | 861 | goto do_segv; |
68016c62 | 862 | case EXCP_DATA_ABORT: |
eae473c1 | 863 | addr = env->cp15.c6_data; |
b5ff1b31 | 864 | do_segv: |
68016c62 FB |
865 | { |
866 | info.si_signo = SIGSEGV; | |
867 | info.si_errno = 0; | |
868 | /* XXX: check env->error_code */ | |
869 | info.si_code = TARGET_SEGV_MAPERR; | |
b5ff1b31 | 870 | info._sifields._sigfault._addr = addr; |
624f7979 | 871 | queue_signal(env, info.si_signo, &info); |
68016c62 FB |
872 | } |
873 | break; | |
1fddef4b FB |
874 | case EXCP_DEBUG: |
875 | { | |
876 | int sig; | |
877 | ||
878 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
879 | if (sig) | |
880 | { | |
881 | info.si_signo = sig; | |
882 | info.si_errno = 0; | |
883 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 884 | queue_signal(env, info.si_signo, &info); |
1fddef4b FB |
885 | } |
886 | } | |
887 | break; | |
fbb4a2e3 PB |
888 | case EXCP_KERNEL_TRAP: |
889 | if (do_kernel_trap(env)) | |
890 | goto error; | |
891 | break; | |
426f5abc PB |
892 | case EXCP_STREX: |
893 | if (do_strex(env)) { | |
894 | addr = env->cp15.c6_data; | |
895 | goto do_segv; | |
896 | } | |
e9273455 | 897 | break; |
b346ff46 FB |
898 | default: |
899 | error: | |
5fafdf24 | 900 | fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", |
b346ff46 | 901 | trapnr); |
878096ee | 902 | cpu_dump_state(cs, stderr, fprintf, 0); |
b346ff46 FB |
903 | abort(); |
904 | } | |
905 | process_pending_signals(env); | |
906 | } | |
907 | } | |
908 | ||
909 | #endif | |
1b6b029e | 910 | |
d2fbca94 GX |
911 | #ifdef TARGET_UNICORE32 |
912 | ||
05390248 | 913 | void cpu_loop(CPUUniCore32State *env) |
d2fbca94 | 914 | { |
0315c31c | 915 | CPUState *cs = CPU(uc32_env_get_cpu(env)); |
d2fbca94 GX |
916 | int trapnr; |
917 | unsigned int n, insn; | |
918 | target_siginfo_t info; | |
919 | ||
920 | for (;;) { | |
0315c31c | 921 | cpu_exec_start(cs); |
d2fbca94 | 922 | trapnr = uc32_cpu_exec(env); |
0315c31c | 923 | cpu_exec_end(cs); |
d2fbca94 GX |
924 | switch (trapnr) { |
925 | case UC32_EXCP_PRIV: | |
926 | { | |
927 | /* system call */ | |
928 | get_user_u32(insn, env->regs[31] - 4); | |
929 | n = insn & 0xffffff; | |
930 | ||
931 | if (n >= UC32_SYSCALL_BASE) { | |
932 | /* linux syscall */ | |
933 | n -= UC32_SYSCALL_BASE; | |
934 | if (n == UC32_SYSCALL_NR_set_tls) { | |
935 | cpu_set_tls(env, env->regs[0]); | |
936 | env->regs[0] = 0; | |
937 | } else { | |
938 | env->regs[0] = do_syscall(env, | |
939 | n, | |
940 | env->regs[0], | |
941 | env->regs[1], | |
942 | env->regs[2], | |
943 | env->regs[3], | |
944 | env->regs[4], | |
5945cfcb PM |
945 | env->regs[5], |
946 | 0, 0); | |
d2fbca94 GX |
947 | } |
948 | } else { | |
949 | goto error; | |
950 | } | |
951 | } | |
952 | break; | |
d48813dd GX |
953 | case UC32_EXCP_DTRAP: |
954 | case UC32_EXCP_ITRAP: | |
d2fbca94 GX |
955 | info.si_signo = SIGSEGV; |
956 | info.si_errno = 0; | |
957 | /* XXX: check env->error_code */ | |
958 | info.si_code = TARGET_SEGV_MAPERR; | |
959 | info._sifields._sigfault._addr = env->cp0.c4_faultaddr; | |
960 | queue_signal(env, info.si_signo, &info); | |
961 | break; | |
962 | case EXCP_INTERRUPT: | |
963 | /* just indicate that signals should be handled asap */ | |
964 | break; | |
965 | case EXCP_DEBUG: | |
966 | { | |
967 | int sig; | |
968 | ||
969 | sig = gdb_handlesig(env, TARGET_SIGTRAP); | |
970 | if (sig) { | |
971 | info.si_signo = sig; | |
972 | info.si_errno = 0; | |
973 | info.si_code = TARGET_TRAP_BRKPT; | |
974 | queue_signal(env, info.si_signo, &info); | |
975 | } | |
976 | } | |
977 | break; | |
978 | default: | |
979 | goto error; | |
980 | } | |
981 | process_pending_signals(env); | |
982 | } | |
983 | ||
984 | error: | |
985 | fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); | |
878096ee | 986 | cpu_dump_state(cs, stderr, fprintf, 0); |
d2fbca94 GX |
987 | abort(); |
988 | } | |
989 | #endif | |
990 | ||
93ac68bc | 991 | #ifdef TARGET_SPARC |
ed23fbd9 | 992 | #define SPARC64_STACK_BIAS 2047 |
93ac68bc | 993 | |
060366c5 FB |
994 | //#define DEBUG_WIN |
995 | ||
2623cbaf FB |
996 | /* WARNING: dealing with register windows _is_ complicated. More info |
997 | can be found at http://www.sics.se/~psm/sparcstack.html */ | |
060366c5 FB |
998 | static inline int get_reg_index(CPUSPARCState *env, int cwp, int index) |
999 | { | |
1a14026e | 1000 | index = (index + cwp * 16) % (16 * env->nwindows); |
060366c5 FB |
1001 | /* wrap handling : if cwp is on the last window, then we use the |
1002 | registers 'after' the end */ | |
1a14026e BS |
1003 | if (index < 8 && env->cwp == env->nwindows - 1) |
1004 | index += 16 * env->nwindows; | |
060366c5 FB |
1005 | return index; |
1006 | } | |
1007 | ||
2623cbaf FB |
1008 | /* save the register window 'cwp1' */ |
1009 | static inline void save_window_offset(CPUSPARCState *env, int cwp1) | |
060366c5 | 1010 | { |
2623cbaf | 1011 | unsigned int i; |
992f48a0 | 1012 | abi_ulong sp_ptr; |
3b46e624 | 1013 | |
53a5960a | 1014 | sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; |
ed23fbd9 BS |
1015 | #ifdef TARGET_SPARC64 |
1016 | if (sp_ptr & 3) | |
1017 | sp_ptr += SPARC64_STACK_BIAS; | |
1018 | #endif | |
060366c5 | 1019 | #if defined(DEBUG_WIN) |
2daf0284 BS |
1020 | printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n", |
1021 | sp_ptr, cwp1); | |
060366c5 | 1022 | #endif |
2623cbaf | 1023 | for(i = 0; i < 16; i++) { |
2f619698 FB |
1024 | /* FIXME - what to do if put_user() fails? */ |
1025 | put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); | |
992f48a0 | 1026 | sp_ptr += sizeof(abi_ulong); |
2623cbaf | 1027 | } |
060366c5 FB |
1028 | } |
1029 | ||
1030 | static void save_window(CPUSPARCState *env) | |
1031 | { | |
5ef54116 | 1032 | #ifndef TARGET_SPARC64 |
2623cbaf | 1033 | unsigned int new_wim; |
1a14026e BS |
1034 | new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & |
1035 | ((1LL << env->nwindows) - 1); | |
1036 | save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); | |
2623cbaf | 1037 | env->wim = new_wim; |
5ef54116 | 1038 | #else |
1a14026e | 1039 | save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); |
5ef54116 FB |
1040 | env->cansave++; |
1041 | env->canrestore--; | |
1042 | #endif | |
060366c5 FB |
1043 | } |
1044 | ||
1045 | static void restore_window(CPUSPARCState *env) | |
1046 | { | |
eda52953 BS |
1047 | #ifndef TARGET_SPARC64 |
1048 | unsigned int new_wim; | |
1049 | #endif | |
1050 | unsigned int i, cwp1; | |
992f48a0 | 1051 | abi_ulong sp_ptr; |
3b46e624 | 1052 | |
eda52953 | 1053 | #ifndef TARGET_SPARC64 |
1a14026e BS |
1054 | new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) & |
1055 | ((1LL << env->nwindows) - 1); | |
eda52953 | 1056 | #endif |
3b46e624 | 1057 | |
060366c5 | 1058 | /* restore the invalid window */ |
1a14026e | 1059 | cwp1 = cpu_cwp_inc(env, env->cwp + 1); |
53a5960a | 1060 | sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; |
ed23fbd9 BS |
1061 | #ifdef TARGET_SPARC64 |
1062 | if (sp_ptr & 3) | |
1063 | sp_ptr += SPARC64_STACK_BIAS; | |
1064 | #endif | |
060366c5 | 1065 | #if defined(DEBUG_WIN) |
2daf0284 BS |
1066 | printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n", |
1067 | sp_ptr, cwp1); | |
060366c5 | 1068 | #endif |
2623cbaf | 1069 | for(i = 0; i < 16; i++) { |
2f619698 FB |
1070 | /* FIXME - what to do if get_user() fails? */ |
1071 | get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); | |
992f48a0 | 1072 | sp_ptr += sizeof(abi_ulong); |
2623cbaf | 1073 | } |
5ef54116 FB |
1074 | #ifdef TARGET_SPARC64 |
1075 | env->canrestore++; | |
1a14026e BS |
1076 | if (env->cleanwin < env->nwindows - 1) |
1077 | env->cleanwin++; | |
5ef54116 | 1078 | env->cansave--; |
eda52953 BS |
1079 | #else |
1080 | env->wim = new_wim; | |
5ef54116 | 1081 | #endif |
060366c5 FB |
1082 | } |
1083 | ||
1084 | static void flush_windows(CPUSPARCState *env) | |
1085 | { | |
1086 | int offset, cwp1; | |
2623cbaf FB |
1087 | |
1088 | offset = 1; | |
060366c5 FB |
1089 | for(;;) { |
1090 | /* if restore would invoke restore_window(), then we can stop */ | |
1a14026e | 1091 | cwp1 = cpu_cwp_inc(env, env->cwp + offset); |
eda52953 | 1092 | #ifndef TARGET_SPARC64 |
060366c5 FB |
1093 | if (env->wim & (1 << cwp1)) |
1094 | break; | |
eda52953 BS |
1095 | #else |
1096 | if (env->canrestore == 0) | |
1097 | break; | |
1098 | env->cansave++; | |
1099 | env->canrestore--; | |
1100 | #endif | |
2623cbaf | 1101 | save_window_offset(env, cwp1); |
060366c5 FB |
1102 | offset++; |
1103 | } | |
1a14026e | 1104 | cwp1 = cpu_cwp_inc(env, env->cwp + 1); |
eda52953 BS |
1105 | #ifndef TARGET_SPARC64 |
1106 | /* set wim so that restore will reload the registers */ | |
2623cbaf | 1107 | env->wim = 1 << cwp1; |
eda52953 | 1108 | #endif |
2623cbaf FB |
1109 | #if defined(DEBUG_WIN) |
1110 | printf("flush_windows: nb=%d\n", offset - 1); | |
80a9d035 | 1111 | #endif |
2623cbaf | 1112 | } |
060366c5 | 1113 | |
93ac68bc FB |
1114 | void cpu_loop (CPUSPARCState *env) |
1115 | { | |
878096ee | 1116 | CPUState *cs = CPU(sparc_env_get_cpu(env)); |
2cc20260 RH |
1117 | int trapnr; |
1118 | abi_long ret; | |
c227f099 | 1119 | target_siginfo_t info; |
3b46e624 | 1120 | |
060366c5 FB |
1121 | while (1) { |
1122 | trapnr = cpu_sparc_exec (env); | |
3b46e624 | 1123 | |
20132b96 RH |
1124 | /* Compute PSR before exposing state. */ |
1125 | if (env->cc_op != CC_OP_FLAGS) { | |
1126 | cpu_get_psr(env); | |
1127 | } | |
1128 | ||
060366c5 | 1129 | switch (trapnr) { |
5ef54116 | 1130 | #ifndef TARGET_SPARC64 |
5fafdf24 | 1131 | case 0x88: |
060366c5 | 1132 | case 0x90: |
5ef54116 | 1133 | #else |
cb33da57 | 1134 | case 0x110: |
5ef54116 FB |
1135 | case 0x16d: |
1136 | #endif | |
060366c5 | 1137 | ret = do_syscall (env, env->gregs[1], |
5fafdf24 TS |
1138 | env->regwptr[0], env->regwptr[1], |
1139 | env->regwptr[2], env->regwptr[3], | |
5945cfcb PM |
1140 | env->regwptr[4], env->regwptr[5], |
1141 | 0, 0); | |
2cc20260 | 1142 | if ((abi_ulong)ret >= (abi_ulong)(-515)) { |
992f48a0 | 1143 | #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) |
27908725 FB |
1144 | env->xcc |= PSR_CARRY; |
1145 | #else | |
060366c5 | 1146 | env->psr |= PSR_CARRY; |
27908725 | 1147 | #endif |
060366c5 FB |
1148 | ret = -ret; |
1149 | } else { | |
992f48a0 | 1150 | #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) |
27908725 FB |
1151 | env->xcc &= ~PSR_CARRY; |
1152 | #else | |
060366c5 | 1153 | env->psr &= ~PSR_CARRY; |
27908725 | 1154 | #endif |
060366c5 FB |
1155 | } |
1156 | env->regwptr[0] = ret; | |
1157 | /* next instruction */ | |
1158 | env->pc = env->npc; | |
1159 | env->npc = env->npc + 4; | |
1160 | break; | |
1161 | case 0x83: /* flush windows */ | |
992f48a0 BS |
1162 | #ifdef TARGET_ABI32 |
1163 | case 0x103: | |
1164 | #endif | |
2623cbaf | 1165 | flush_windows(env); |
060366c5 FB |
1166 | /* next instruction */ |
1167 | env->pc = env->npc; | |
1168 | env->npc = env->npc + 4; | |
1169 | break; | |
3475187d | 1170 | #ifndef TARGET_SPARC64 |
060366c5 FB |
1171 | case TT_WIN_OVF: /* window overflow */ |
1172 | save_window(env); | |
1173 | break; | |
1174 | case TT_WIN_UNF: /* window underflow */ | |
1175 | restore_window(env); | |
1176 | break; | |
61ff6f58 FB |
1177 | case TT_TFAULT: |
1178 | case TT_DFAULT: | |
1179 | { | |
59f7182f | 1180 | info.si_signo = TARGET_SIGSEGV; |
61ff6f58 FB |
1181 | info.si_errno = 0; |
1182 | /* XXX: check env->error_code */ | |
1183 | info.si_code = TARGET_SEGV_MAPERR; | |
1184 | info._sifields._sigfault._addr = env->mmuregs[4]; | |
624f7979 | 1185 | queue_signal(env, info.si_signo, &info); |
61ff6f58 FB |
1186 | } |
1187 | break; | |
3475187d | 1188 | #else |
5ef54116 FB |
1189 | case TT_SPILL: /* window overflow */ |
1190 | save_window(env); | |
1191 | break; | |
1192 | case TT_FILL: /* window underflow */ | |
1193 | restore_window(env); | |
1194 | break; | |
7f84a729 BS |
1195 | case TT_TFAULT: |
1196 | case TT_DFAULT: | |
1197 | { | |
59f7182f | 1198 | info.si_signo = TARGET_SIGSEGV; |
7f84a729 BS |
1199 | info.si_errno = 0; |
1200 | /* XXX: check env->error_code */ | |
1201 | info.si_code = TARGET_SEGV_MAPERR; | |
1202 | if (trapnr == TT_DFAULT) | |
1203 | info._sifields._sigfault._addr = env->dmmuregs[4]; | |
1204 | else | |
8194f35a | 1205 | info._sifields._sigfault._addr = cpu_tsptr(env)->tpc; |
624f7979 | 1206 | queue_signal(env, info.si_signo, &info); |
7f84a729 BS |
1207 | } |
1208 | break; | |
27524dc3 | 1209 | #ifndef TARGET_ABI32 |
5bfb56b2 BS |
1210 | case 0x16e: |
1211 | flush_windows(env); | |
1212 | sparc64_get_context(env); | |
1213 | break; | |
1214 | case 0x16f: | |
1215 | flush_windows(env); | |
1216 | sparc64_set_context(env); | |
1217 | break; | |
27524dc3 | 1218 | #endif |
3475187d | 1219 | #endif |
48dc41eb FB |
1220 | case EXCP_INTERRUPT: |
1221 | /* just indicate that signals should be handled asap */ | |
1222 | break; | |
75f22e4e RH |
1223 | case TT_ILL_INSN: |
1224 | { | |
1225 | info.si_signo = TARGET_SIGILL; | |
1226 | info.si_errno = 0; | |
1227 | info.si_code = TARGET_ILL_ILLOPC; | |
1228 | info._sifields._sigfault._addr = env->pc; | |
1229 | queue_signal(env, info.si_signo, &info); | |
1230 | } | |
1231 | break; | |
1fddef4b FB |
1232 | case EXCP_DEBUG: |
1233 | { | |
1234 | int sig; | |
1235 | ||
1236 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
1237 | if (sig) | |
1238 | { | |
1239 | info.si_signo = sig; | |
1240 | info.si_errno = 0; | |
1241 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 1242 | queue_signal(env, info.si_signo, &info); |
1fddef4b FB |
1243 | } |
1244 | } | |
1245 | break; | |
060366c5 FB |
1246 | default: |
1247 | printf ("Unhandled trap: 0x%x\n", trapnr); | |
878096ee | 1248 | cpu_dump_state(cs, stderr, fprintf, 0); |
060366c5 FB |
1249 | exit (1); |
1250 | } | |
1251 | process_pending_signals (env); | |
1252 | } | |
93ac68bc FB |
1253 | } |
1254 | ||
1255 | #endif | |
1256 | ||
67867308 | 1257 | #ifdef TARGET_PPC |
05390248 | 1258 | static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env) |
9fddaa0c FB |
1259 | { |
1260 | /* TO FIX */ | |
1261 | return 0; | |
1262 | } | |
3b46e624 | 1263 | |
05390248 | 1264 | uint64_t cpu_ppc_load_tbl(CPUPPCState *env) |
9fddaa0c | 1265 | { |
e3ea6529 | 1266 | return cpu_ppc_get_tb(env); |
9fddaa0c | 1267 | } |
3b46e624 | 1268 | |
05390248 | 1269 | uint32_t cpu_ppc_load_tbu(CPUPPCState *env) |
9fddaa0c FB |
1270 | { |
1271 | return cpu_ppc_get_tb(env) >> 32; | |
1272 | } | |
3b46e624 | 1273 | |
05390248 | 1274 | uint64_t cpu_ppc_load_atbl(CPUPPCState *env) |
9fddaa0c | 1275 | { |
b711de95 | 1276 | return cpu_ppc_get_tb(env); |
9fddaa0c | 1277 | } |
5fafdf24 | 1278 | |
05390248 | 1279 | uint32_t cpu_ppc_load_atbu(CPUPPCState *env) |
9fddaa0c | 1280 | { |
a062e36c | 1281 | return cpu_ppc_get_tb(env) >> 32; |
9fddaa0c | 1282 | } |
76a66253 | 1283 | |
05390248 | 1284 | uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env) |
76a66253 JM |
1285 | __attribute__ (( alias ("cpu_ppc_load_tbu") )); |
1286 | ||
05390248 | 1287 | uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env) |
9fddaa0c | 1288 | { |
76a66253 | 1289 | return cpu_ppc_load_tbl(env) & 0x3FFFFF80; |
9fddaa0c | 1290 | } |
76a66253 | 1291 | |
a750fc0b | 1292 | /* XXX: to be fixed */ |
73b01960 | 1293 | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) |
a750fc0b JM |
1294 | { |
1295 | return -1; | |
1296 | } | |
1297 | ||
73b01960 | 1298 | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) |
a750fc0b JM |
1299 | { |
1300 | return -1; | |
1301 | } | |
1302 | ||
001faf32 BS |
1303 | #define EXCP_DUMP(env, fmt, ...) \ |
1304 | do { \ | |
a0762859 | 1305 | CPUState *cs = ENV_GET_CPU(env); \ |
001faf32 | 1306 | fprintf(stderr, fmt , ## __VA_ARGS__); \ |
a0762859 | 1307 | cpu_dump_state(cs, stderr, fprintf, 0); \ |
001faf32 | 1308 | qemu_log(fmt, ## __VA_ARGS__); \ |
eeacee4d | 1309 | if (qemu_log_enabled()) { \ |
a0762859 | 1310 | log_cpu_state(cs, 0); \ |
eeacee4d | 1311 | } \ |
e1833e1f JM |
1312 | } while (0) |
1313 | ||
56f066bb NF |
1314 | static int do_store_exclusive(CPUPPCState *env) |
1315 | { | |
1316 | target_ulong addr; | |
1317 | target_ulong page_addr; | |
1318 | target_ulong val; | |
1319 | int flags; | |
1320 | int segv = 0; | |
1321 | ||
1322 | addr = env->reserve_ea; | |
1323 | page_addr = addr & TARGET_PAGE_MASK; | |
1324 | start_exclusive(); | |
1325 | mmap_lock(); | |
1326 | flags = page_get_flags(page_addr); | |
1327 | if ((flags & PAGE_READ) == 0) { | |
1328 | segv = 1; | |
1329 | } else { | |
1330 | int reg = env->reserve_info & 0x1f; | |
1331 | int size = (env->reserve_info >> 5) & 0xf; | |
1332 | int stored = 0; | |
1333 | ||
1334 | if (addr == env->reserve_addr) { | |
1335 | switch (size) { | |
1336 | case 1: segv = get_user_u8(val, addr); break; | |
1337 | case 2: segv = get_user_u16(val, addr); break; | |
1338 | case 4: segv = get_user_u32(val, addr); break; | |
1339 | #if defined(TARGET_PPC64) | |
1340 | case 8: segv = get_user_u64(val, addr); break; | |
1341 | #endif | |
1342 | default: abort(); | |
1343 | } | |
1344 | if (!segv && val == env->reserve_val) { | |
1345 | val = env->gpr[reg]; | |
1346 | switch (size) { | |
1347 | case 1: segv = put_user_u8(val, addr); break; | |
1348 | case 2: segv = put_user_u16(val, addr); break; | |
1349 | case 4: segv = put_user_u32(val, addr); break; | |
1350 | #if defined(TARGET_PPC64) | |
1351 | case 8: segv = put_user_u64(val, addr); break; | |
1352 | #endif | |
1353 | default: abort(); | |
1354 | } | |
1355 | if (!segv) { | |
1356 | stored = 1; | |
1357 | } | |
1358 | } | |
1359 | } | |
1360 | env->crf[0] = (stored << 1) | xer_so; | |
1361 | env->reserve_addr = (target_ulong)-1; | |
1362 | } | |
1363 | if (!segv) { | |
1364 | env->nip += 4; | |
1365 | } | |
1366 | mmap_unlock(); | |
1367 | end_exclusive(); | |
1368 | return segv; | |
1369 | } | |
1370 | ||
67867308 FB |
1371 | void cpu_loop(CPUPPCState *env) |
1372 | { | |
0315c31c | 1373 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
c227f099 | 1374 | target_siginfo_t info; |
61190b14 | 1375 | int trapnr; |
9e0e2f96 | 1376 | target_ulong ret; |
3b46e624 | 1377 | |
67867308 | 1378 | for(;;) { |
0315c31c | 1379 | cpu_exec_start(cs); |
67867308 | 1380 | trapnr = cpu_ppc_exec(env); |
0315c31c | 1381 | cpu_exec_end(cs); |
67867308 | 1382 | switch(trapnr) { |
e1833e1f JM |
1383 | case POWERPC_EXCP_NONE: |
1384 | /* Just go on */ | |
67867308 | 1385 | break; |
e1833e1f JM |
1386 | case POWERPC_EXCP_CRITICAL: /* Critical input */ |
1387 | cpu_abort(env, "Critical interrupt while in user mode. " | |
1388 | "Aborting\n"); | |
61190b14 | 1389 | break; |
e1833e1f JM |
1390 | case POWERPC_EXCP_MCHECK: /* Machine check exception */ |
1391 | cpu_abort(env, "Machine check exception while in user mode. " | |
1392 | "Aborting\n"); | |
1393 | break; | |
1394 | case POWERPC_EXCP_DSI: /* Data storage exception */ | |
90e189ec | 1395 | EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n", |
e1833e1f JM |
1396 | env->spr[SPR_DAR]); |
1397 | /* XXX: check this. Seems bugged */ | |
2be0071f FB |
1398 | switch (env->error_code & 0xFF000000) { |
1399 | case 0x40000000: | |
61190b14 FB |
1400 | info.si_signo = TARGET_SIGSEGV; |
1401 | info.si_errno = 0; | |
1402 | info.si_code = TARGET_SEGV_MAPERR; | |
1403 | break; | |
2be0071f | 1404 | case 0x04000000: |
61190b14 FB |
1405 | info.si_signo = TARGET_SIGILL; |
1406 | info.si_errno = 0; | |
1407 | info.si_code = TARGET_ILL_ILLADR; | |
1408 | break; | |
2be0071f | 1409 | case 0x08000000: |
61190b14 FB |
1410 | info.si_signo = TARGET_SIGSEGV; |
1411 | info.si_errno = 0; | |
1412 | info.si_code = TARGET_SEGV_ACCERR; | |
1413 | break; | |
61190b14 FB |
1414 | default: |
1415 | /* Let's send a regular segfault... */ | |
e1833e1f JM |
1416 | EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", |
1417 | env->error_code); | |
61190b14 FB |
1418 | info.si_signo = TARGET_SIGSEGV; |
1419 | info.si_errno = 0; | |
1420 | info.si_code = TARGET_SEGV_MAPERR; | |
1421 | break; | |
1422 | } | |
67867308 | 1423 | info._sifields._sigfault._addr = env->nip; |
624f7979 | 1424 | queue_signal(env, info.si_signo, &info); |
67867308 | 1425 | break; |
e1833e1f | 1426 | case POWERPC_EXCP_ISI: /* Instruction storage exception */ |
90e189ec BS |
1427 | EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx |
1428 | "\n", env->spr[SPR_SRR0]); | |
e1833e1f | 1429 | /* XXX: check this */ |
2be0071f FB |
1430 | switch (env->error_code & 0xFF000000) { |
1431 | case 0x40000000: | |
61190b14 | 1432 | info.si_signo = TARGET_SIGSEGV; |
67867308 | 1433 | info.si_errno = 0; |
61190b14 FB |
1434 | info.si_code = TARGET_SEGV_MAPERR; |
1435 | break; | |
2be0071f FB |
1436 | case 0x10000000: |
1437 | case 0x08000000: | |
61190b14 FB |
1438 | info.si_signo = TARGET_SIGSEGV; |
1439 | info.si_errno = 0; | |
1440 | info.si_code = TARGET_SEGV_ACCERR; | |
1441 | break; | |
1442 | default: | |
1443 | /* Let's send a regular segfault... */ | |
e1833e1f JM |
1444 | EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", |
1445 | env->error_code); | |
61190b14 FB |
1446 | info.si_signo = TARGET_SIGSEGV; |
1447 | info.si_errno = 0; | |
1448 | info.si_code = TARGET_SEGV_MAPERR; | |
1449 | break; | |
1450 | } | |
1451 | info._sifields._sigfault._addr = env->nip - 4; | |
624f7979 | 1452 | queue_signal(env, info.si_signo, &info); |
67867308 | 1453 | break; |
e1833e1f JM |
1454 | case POWERPC_EXCP_EXTERNAL: /* External input */ |
1455 | cpu_abort(env, "External interrupt while in user mode. " | |
1456 | "Aborting\n"); | |
1457 | break; | |
1458 | case POWERPC_EXCP_ALIGN: /* Alignment exception */ | |
1459 | EXCP_DUMP(env, "Unaligned memory access\n"); | |
1460 | /* XXX: check this */ | |
61190b14 | 1461 | info.si_signo = TARGET_SIGBUS; |
67867308 | 1462 | info.si_errno = 0; |
61190b14 FB |
1463 | info.si_code = TARGET_BUS_ADRALN; |
1464 | info._sifields._sigfault._addr = env->nip - 4; | |
624f7979 | 1465 | queue_signal(env, info.si_signo, &info); |
67867308 | 1466 | break; |
e1833e1f JM |
1467 | case POWERPC_EXCP_PROGRAM: /* Program exception */ |
1468 | /* XXX: check this */ | |
61190b14 | 1469 | switch (env->error_code & ~0xF) { |
e1833e1f JM |
1470 | case POWERPC_EXCP_FP: |
1471 | EXCP_DUMP(env, "Floating point program exception\n"); | |
61190b14 FB |
1472 | info.si_signo = TARGET_SIGFPE; |
1473 | info.si_errno = 0; | |
1474 | switch (env->error_code & 0xF) { | |
e1833e1f | 1475 | case POWERPC_EXCP_FP_OX: |
61190b14 FB |
1476 | info.si_code = TARGET_FPE_FLTOVF; |
1477 | break; | |
e1833e1f | 1478 | case POWERPC_EXCP_FP_UX: |
61190b14 FB |
1479 | info.si_code = TARGET_FPE_FLTUND; |
1480 | break; | |
e1833e1f JM |
1481 | case POWERPC_EXCP_FP_ZX: |
1482 | case POWERPC_EXCP_FP_VXZDZ: | |
61190b14 FB |
1483 | info.si_code = TARGET_FPE_FLTDIV; |
1484 | break; | |
e1833e1f | 1485 | case POWERPC_EXCP_FP_XX: |
61190b14 FB |
1486 | info.si_code = TARGET_FPE_FLTRES; |
1487 | break; | |
e1833e1f | 1488 | case POWERPC_EXCP_FP_VXSOFT: |
61190b14 FB |
1489 | info.si_code = TARGET_FPE_FLTINV; |
1490 | break; | |
7c58044c | 1491 | case POWERPC_EXCP_FP_VXSNAN: |
e1833e1f JM |
1492 | case POWERPC_EXCP_FP_VXISI: |
1493 | case POWERPC_EXCP_FP_VXIDI: | |
1494 | case POWERPC_EXCP_FP_VXIMZ: | |
1495 | case POWERPC_EXCP_FP_VXVC: | |
1496 | case POWERPC_EXCP_FP_VXSQRT: | |
1497 | case POWERPC_EXCP_FP_VXCVI: | |
61190b14 FB |
1498 | info.si_code = TARGET_FPE_FLTSUB; |
1499 | break; | |
1500 | default: | |
e1833e1f JM |
1501 | EXCP_DUMP(env, "Unknown floating point exception (%02x)\n", |
1502 | env->error_code); | |
1503 | break; | |
61190b14 | 1504 | } |
e1833e1f JM |
1505 | break; |
1506 | case POWERPC_EXCP_INVAL: | |
1507 | EXCP_DUMP(env, "Invalid instruction\n"); | |
61190b14 FB |
1508 | info.si_signo = TARGET_SIGILL; |
1509 | info.si_errno = 0; | |
1510 | switch (env->error_code & 0xF) { | |
e1833e1f | 1511 | case POWERPC_EXCP_INVAL_INVAL: |
61190b14 FB |
1512 | info.si_code = TARGET_ILL_ILLOPC; |
1513 | break; | |
e1833e1f | 1514 | case POWERPC_EXCP_INVAL_LSWX: |
a750fc0b | 1515 | info.si_code = TARGET_ILL_ILLOPN; |
61190b14 | 1516 | break; |
e1833e1f | 1517 | case POWERPC_EXCP_INVAL_SPR: |
61190b14 FB |
1518 | info.si_code = TARGET_ILL_PRVREG; |
1519 | break; | |
e1833e1f | 1520 | case POWERPC_EXCP_INVAL_FP: |
61190b14 FB |
1521 | info.si_code = TARGET_ILL_COPROC; |
1522 | break; | |
1523 | default: | |
e1833e1f JM |
1524 | EXCP_DUMP(env, "Unknown invalid operation (%02x)\n", |
1525 | env->error_code & 0xF); | |
61190b14 FB |
1526 | info.si_code = TARGET_ILL_ILLADR; |
1527 | break; | |
1528 | } | |
1529 | break; | |
e1833e1f JM |
1530 | case POWERPC_EXCP_PRIV: |
1531 | EXCP_DUMP(env, "Privilege violation\n"); | |
61190b14 FB |
1532 | info.si_signo = TARGET_SIGILL; |
1533 | info.si_errno = 0; | |
1534 | switch (env->error_code & 0xF) { | |
e1833e1f | 1535 | case POWERPC_EXCP_PRIV_OPC: |
61190b14 FB |
1536 | info.si_code = TARGET_ILL_PRVOPC; |
1537 | break; | |
e1833e1f | 1538 | case POWERPC_EXCP_PRIV_REG: |
61190b14 | 1539 | info.si_code = TARGET_ILL_PRVREG; |
e1833e1f | 1540 | break; |
61190b14 | 1541 | default: |
e1833e1f JM |
1542 | EXCP_DUMP(env, "Unknown privilege violation (%02x)\n", |
1543 | env->error_code & 0xF); | |
61190b14 FB |
1544 | info.si_code = TARGET_ILL_PRVOPC; |
1545 | break; | |
1546 | } | |
1547 | break; | |
e1833e1f JM |
1548 | case POWERPC_EXCP_TRAP: |
1549 | cpu_abort(env, "Tried to call a TRAP\n"); | |
1550 | break; | |
61190b14 FB |
1551 | default: |
1552 | /* Should not happen ! */ | |
e1833e1f JM |
1553 | cpu_abort(env, "Unknown program exception (%02x)\n", |
1554 | env->error_code); | |
1555 | break; | |
61190b14 FB |
1556 | } |
1557 | info._sifields._sigfault._addr = env->nip - 4; | |
624f7979 | 1558 | queue_signal(env, info.si_signo, &info); |
67867308 | 1559 | break; |
e1833e1f JM |
1560 | case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ |
1561 | EXCP_DUMP(env, "No floating point allowed\n"); | |
61190b14 | 1562 | info.si_signo = TARGET_SIGILL; |
67867308 | 1563 | info.si_errno = 0; |
61190b14 FB |
1564 | info.si_code = TARGET_ILL_COPROC; |
1565 | info._sifields._sigfault._addr = env->nip - 4; | |
624f7979 | 1566 | queue_signal(env, info.si_signo, &info); |
67867308 | 1567 | break; |
e1833e1f JM |
1568 | case POWERPC_EXCP_SYSCALL: /* System call exception */ |
1569 | cpu_abort(env, "Syscall exception while in user mode. " | |
1570 | "Aborting\n"); | |
61190b14 | 1571 | break; |
e1833e1f JM |
1572 | case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ |
1573 | EXCP_DUMP(env, "No APU instruction allowed\n"); | |
1574 | info.si_signo = TARGET_SIGILL; | |
1575 | info.si_errno = 0; | |
1576 | info.si_code = TARGET_ILL_COPROC; | |
1577 | info._sifields._sigfault._addr = env->nip - 4; | |
624f7979 | 1578 | queue_signal(env, info.si_signo, &info); |
61190b14 | 1579 | break; |
e1833e1f JM |
1580 | case POWERPC_EXCP_DECR: /* Decrementer exception */ |
1581 | cpu_abort(env, "Decrementer interrupt while in user mode. " | |
1582 | "Aborting\n"); | |
61190b14 | 1583 | break; |
e1833e1f JM |
1584 | case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ |
1585 | cpu_abort(env, "Fix interval timer interrupt while in user mode. " | |
1586 | "Aborting\n"); | |
1587 | break; | |
1588 | case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ | |
1589 | cpu_abort(env, "Watchdog timer interrupt while in user mode. " | |
1590 | "Aborting\n"); | |
1591 | break; | |
1592 | case POWERPC_EXCP_DTLB: /* Data TLB error */ | |
1593 | cpu_abort(env, "Data TLB exception while in user mode. " | |
1594 | "Aborting\n"); | |
1595 | break; | |
1596 | case POWERPC_EXCP_ITLB: /* Instruction TLB error */ | |
1597 | cpu_abort(env, "Instruction TLB exception while in user mode. " | |
1598 | "Aborting\n"); | |
1599 | break; | |
e1833e1f JM |
1600 | case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */ |
1601 | EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n"); | |
1602 | info.si_signo = TARGET_SIGILL; | |
1603 | info.si_errno = 0; | |
1604 | info.si_code = TARGET_ILL_COPROC; | |
1605 | info._sifields._sigfault._addr = env->nip - 4; | |
624f7979 | 1606 | queue_signal(env, info.si_signo, &info); |
e1833e1f JM |
1607 | break; |
1608 | case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */ | |
1609 | cpu_abort(env, "Embedded floating-point data IRQ not handled\n"); | |
1610 | break; | |
1611 | case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */ | |
1612 | cpu_abort(env, "Embedded floating-point round IRQ not handled\n"); | |
1613 | break; | |
1614 | case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */ | |
1615 | cpu_abort(env, "Performance monitor exception not handled\n"); | |
1616 | break; | |
1617 | case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ | |
1618 | cpu_abort(env, "Doorbell interrupt while in user mode. " | |
1619 | "Aborting\n"); | |
1620 | break; | |
1621 | case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ | |
1622 | cpu_abort(env, "Doorbell critical interrupt while in user mode. " | |
1623 | "Aborting\n"); | |
1624 | break; | |
1625 | case POWERPC_EXCP_RESET: /* System reset exception */ | |
1626 | cpu_abort(env, "Reset interrupt while in user mode. " | |
1627 | "Aborting\n"); | |
1628 | break; | |
e1833e1f JM |
1629 | case POWERPC_EXCP_DSEG: /* Data segment exception */ |
1630 | cpu_abort(env, "Data segment exception while in user mode. " | |
1631 | "Aborting\n"); | |
1632 | break; | |
1633 | case POWERPC_EXCP_ISEG: /* Instruction segment exception */ | |
1634 | cpu_abort(env, "Instruction segment exception " | |
1635 | "while in user mode. Aborting\n"); | |
1636 | break; | |
e85e7c6e | 1637 | /* PowerPC 64 with hypervisor mode support */ |
e1833e1f JM |
1638 | case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ |
1639 | cpu_abort(env, "Hypervisor decrementer interrupt " | |
1640 | "while in user mode. Aborting\n"); | |
1641 | break; | |
e1833e1f JM |
1642 | case POWERPC_EXCP_TRACE: /* Trace exception */ |
1643 | /* Nothing to do: | |
1644 | * we use this exception to emulate step-by-step execution mode. | |
1645 | */ | |
1646 | break; | |
e85e7c6e | 1647 | /* PowerPC 64 with hypervisor mode support */ |
e1833e1f JM |
1648 | case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ |
1649 | cpu_abort(env, "Hypervisor data storage exception " | |
1650 | "while in user mode. Aborting\n"); | |
1651 | break; | |
1652 | case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */ | |
1653 | cpu_abort(env, "Hypervisor instruction storage exception " | |
1654 | "while in user mode. Aborting\n"); | |
1655 | break; | |
1656 | case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ | |
1657 | cpu_abort(env, "Hypervisor data segment exception " | |
1658 | "while in user mode. Aborting\n"); | |
1659 | break; | |
1660 | case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */ | |
1661 | cpu_abort(env, "Hypervisor instruction segment exception " | |
1662 | "while in user mode. Aborting\n"); | |
1663 | break; | |
e1833e1f JM |
1664 | case POWERPC_EXCP_VPU: /* Vector unavailable exception */ |
1665 | EXCP_DUMP(env, "No Altivec instructions allowed\n"); | |
1666 | info.si_signo = TARGET_SIGILL; | |
1667 | info.si_errno = 0; | |
1668 | info.si_code = TARGET_ILL_COPROC; | |
1669 | info._sifields._sigfault._addr = env->nip - 4; | |
624f7979 | 1670 | queue_signal(env, info.si_signo, &info); |
e1833e1f JM |
1671 | break; |
1672 | case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */ | |
b4916d7b | 1673 | cpu_abort(env, "Programmable interval timer interrupt " |
e1833e1f JM |
1674 | "while in user mode. Aborting\n"); |
1675 | break; | |
1676 | case POWERPC_EXCP_IO: /* IO error exception */ | |
1677 | cpu_abort(env, "IO error exception while in user mode. " | |
1678 | "Aborting\n"); | |
1679 | break; | |
1680 | case POWERPC_EXCP_RUNM: /* Run mode exception */ | |
1681 | cpu_abort(env, "Run mode exception while in user mode. " | |
1682 | "Aborting\n"); | |
1683 | break; | |
1684 | case POWERPC_EXCP_EMUL: /* Emulation trap exception */ | |
1685 | cpu_abort(env, "Emulation trap exception not handled\n"); | |
1686 | break; | |
1687 | case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ | |
1688 | cpu_abort(env, "Instruction fetch TLB exception " | |
1689 | "while in user-mode. Aborting"); | |
1690 | break; | |
1691 | case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ | |
1692 | cpu_abort(env, "Data load TLB exception while in user-mode. " | |
1693 | "Aborting"); | |
1694 | break; | |
1695 | case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ | |
1696 | cpu_abort(env, "Data store TLB exception while in user-mode. " | |
1697 | "Aborting"); | |
1698 | break; | |
1699 | case POWERPC_EXCP_FPA: /* Floating-point assist exception */ | |
1700 | cpu_abort(env, "Floating-point assist exception not handled\n"); | |
1701 | break; | |
1702 | case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ | |
1703 | cpu_abort(env, "Instruction address breakpoint exception " | |
1704 | "not handled\n"); | |
1705 | break; | |
1706 | case POWERPC_EXCP_SMI: /* System management interrupt */ | |
1707 | cpu_abort(env, "System management interrupt while in user mode. " | |
1708 | "Aborting\n"); | |
1709 | break; | |
1710 | case POWERPC_EXCP_THERM: /* Thermal interrupt */ | |
1711 | cpu_abort(env, "Thermal interrupt interrupt while in user mode. " | |
1712 | "Aborting\n"); | |
1713 | break; | |
1714 | case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */ | |
1715 | cpu_abort(env, "Performance monitor exception not handled\n"); | |
1716 | break; | |
1717 | case POWERPC_EXCP_VPUA: /* Vector assist exception */ | |
1718 | cpu_abort(env, "Vector assist exception not handled\n"); | |
1719 | break; | |
1720 | case POWERPC_EXCP_SOFTP: /* Soft patch exception */ | |
1721 | cpu_abort(env, "Soft patch exception not handled\n"); | |
1722 | break; | |
1723 | case POWERPC_EXCP_MAINT: /* Maintenance exception */ | |
1724 | cpu_abort(env, "Maintenance exception while in user mode. " | |
1725 | "Aborting\n"); | |
1726 | break; | |
1727 | case POWERPC_EXCP_STOP: /* stop translation */ | |
1728 | /* We did invalidate the instruction cache. Go on */ | |
1729 | break; | |
1730 | case POWERPC_EXCP_BRANCH: /* branch instruction: */ | |
1731 | /* We just stopped because of a branch. Go on */ | |
1732 | break; | |
1733 | case POWERPC_EXCP_SYSCALL_USER: | |
1734 | /* system call in user-mode emulation */ | |
1735 | /* WARNING: | |
1736 | * PPC ABI uses overflow flag in cr0 to signal an error | |
1737 | * in syscalls. | |
1738 | */ | |
e1833e1f JM |
1739 | env->crf[0] &= ~0x1; |
1740 | ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4], | |
1741 | env->gpr[5], env->gpr[6], env->gpr[7], | |
5945cfcb | 1742 | env->gpr[8], 0, 0); |
9e0e2f96 | 1743 | if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) { |
bcd4933a NF |
1744 | /* Returning from a successful sigreturn syscall. |
1745 | Avoid corrupting register state. */ | |
1746 | break; | |
1747 | } | |
9e0e2f96 | 1748 | if (ret > (target_ulong)(-515)) { |
e1833e1f JM |
1749 | env->crf[0] |= 0x1; |
1750 | ret = -ret; | |
61190b14 | 1751 | } |
e1833e1f | 1752 | env->gpr[3] = ret; |
e1833e1f | 1753 | break; |
56f066bb NF |
1754 | case POWERPC_EXCP_STCX: |
1755 | if (do_store_exclusive(env)) { | |
1756 | info.si_signo = TARGET_SIGSEGV; | |
1757 | info.si_errno = 0; | |
1758 | info.si_code = TARGET_SEGV_MAPERR; | |
1759 | info._sifields._sigfault._addr = env->nip; | |
1760 | queue_signal(env, info.si_signo, &info); | |
1761 | } | |
1762 | break; | |
71f75756 AJ |
1763 | case EXCP_DEBUG: |
1764 | { | |
1765 | int sig; | |
1766 | ||
1767 | sig = gdb_handlesig(env, TARGET_SIGTRAP); | |
1768 | if (sig) { | |
1769 | info.si_signo = sig; | |
1770 | info.si_errno = 0; | |
1771 | info.si_code = TARGET_TRAP_BRKPT; | |
1772 | queue_signal(env, info.si_signo, &info); | |
1773 | } | |
1774 | } | |
1775 | break; | |
56ba31ff JM |
1776 | case EXCP_INTERRUPT: |
1777 | /* just indicate that signals should be handled asap */ | |
1778 | break; | |
e1833e1f JM |
1779 | default: |
1780 | cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr); | |
1781 | break; | |
67867308 FB |
1782 | } |
1783 | process_pending_signals(env); | |
1784 | } | |
1785 | } | |
1786 | #endif | |
1787 | ||
048f6b4d FB |
1788 | #ifdef TARGET_MIPS |
1789 | ||
ff4f7382 RH |
1790 | # ifdef TARGET_ABI_MIPSO32 |
1791 | # define MIPS_SYS(name, args) args, | |
048f6b4d | 1792 | static const uint8_t mips_syscall_args[] = { |
29fb0f25 | 1793 | MIPS_SYS(sys_syscall , 8) /* 4000 */ |
048f6b4d FB |
1794 | MIPS_SYS(sys_exit , 1) |
1795 | MIPS_SYS(sys_fork , 0) | |
1796 | MIPS_SYS(sys_read , 3) | |
1797 | MIPS_SYS(sys_write , 3) | |
1798 | MIPS_SYS(sys_open , 3) /* 4005 */ | |
1799 | MIPS_SYS(sys_close , 1) | |
1800 | MIPS_SYS(sys_waitpid , 3) | |
1801 | MIPS_SYS(sys_creat , 2) | |
1802 | MIPS_SYS(sys_link , 2) | |
1803 | MIPS_SYS(sys_unlink , 1) /* 4010 */ | |
1804 | MIPS_SYS(sys_execve , 0) | |
1805 | MIPS_SYS(sys_chdir , 1) | |
1806 | MIPS_SYS(sys_time , 1) | |
1807 | MIPS_SYS(sys_mknod , 3) | |
1808 | MIPS_SYS(sys_chmod , 2) /* 4015 */ | |
1809 | MIPS_SYS(sys_lchown , 3) | |
1810 | MIPS_SYS(sys_ni_syscall , 0) | |
1811 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */ | |
1812 | MIPS_SYS(sys_lseek , 3) | |
1813 | MIPS_SYS(sys_getpid , 0) /* 4020 */ | |
1814 | MIPS_SYS(sys_mount , 5) | |
1815 | MIPS_SYS(sys_oldumount , 1) | |
1816 | MIPS_SYS(sys_setuid , 1) | |
1817 | MIPS_SYS(sys_getuid , 0) | |
1818 | MIPS_SYS(sys_stime , 1) /* 4025 */ | |
1819 | MIPS_SYS(sys_ptrace , 4) | |
1820 | MIPS_SYS(sys_alarm , 1) | |
1821 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */ | |
1822 | MIPS_SYS(sys_pause , 0) | |
1823 | MIPS_SYS(sys_utime , 2) /* 4030 */ | |
1824 | MIPS_SYS(sys_ni_syscall , 0) | |
1825 | MIPS_SYS(sys_ni_syscall , 0) | |
1826 | MIPS_SYS(sys_access , 2) | |
1827 | MIPS_SYS(sys_nice , 1) | |
1828 | MIPS_SYS(sys_ni_syscall , 0) /* 4035 */ | |
1829 | MIPS_SYS(sys_sync , 0) | |
1830 | MIPS_SYS(sys_kill , 2) | |
1831 | MIPS_SYS(sys_rename , 2) | |
1832 | MIPS_SYS(sys_mkdir , 2) | |
1833 | MIPS_SYS(sys_rmdir , 1) /* 4040 */ | |
1834 | MIPS_SYS(sys_dup , 1) | |
1835 | MIPS_SYS(sys_pipe , 0) | |
1836 | MIPS_SYS(sys_times , 1) | |
1837 | MIPS_SYS(sys_ni_syscall , 0) | |
1838 | MIPS_SYS(sys_brk , 1) /* 4045 */ | |
1839 | MIPS_SYS(sys_setgid , 1) | |
1840 | MIPS_SYS(sys_getgid , 0) | |
1841 | MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */ | |
1842 | MIPS_SYS(sys_geteuid , 0) | |
1843 | MIPS_SYS(sys_getegid , 0) /* 4050 */ | |
1844 | MIPS_SYS(sys_acct , 0) | |
1845 | MIPS_SYS(sys_umount , 2) | |
1846 | MIPS_SYS(sys_ni_syscall , 0) | |
1847 | MIPS_SYS(sys_ioctl , 3) | |
1848 | MIPS_SYS(sys_fcntl , 3) /* 4055 */ | |
1849 | MIPS_SYS(sys_ni_syscall , 2) | |
1850 | MIPS_SYS(sys_setpgid , 2) | |
1851 | MIPS_SYS(sys_ni_syscall , 0) | |
1852 | MIPS_SYS(sys_olduname , 1) | |
1853 | MIPS_SYS(sys_umask , 1) /* 4060 */ | |
1854 | MIPS_SYS(sys_chroot , 1) | |
1855 | MIPS_SYS(sys_ustat , 2) | |
1856 | MIPS_SYS(sys_dup2 , 2) | |
1857 | MIPS_SYS(sys_getppid , 0) | |
1858 | MIPS_SYS(sys_getpgrp , 0) /* 4065 */ | |
1859 | MIPS_SYS(sys_setsid , 0) | |
1860 | MIPS_SYS(sys_sigaction , 3) | |
1861 | MIPS_SYS(sys_sgetmask , 0) | |
1862 | MIPS_SYS(sys_ssetmask , 1) | |
1863 | MIPS_SYS(sys_setreuid , 2) /* 4070 */ | |
1864 | MIPS_SYS(sys_setregid , 2) | |
1865 | MIPS_SYS(sys_sigsuspend , 0) | |
1866 | MIPS_SYS(sys_sigpending , 1) | |
1867 | MIPS_SYS(sys_sethostname , 2) | |
1868 | MIPS_SYS(sys_setrlimit , 2) /* 4075 */ | |
1869 | MIPS_SYS(sys_getrlimit , 2) | |
1870 | MIPS_SYS(sys_getrusage , 2) | |
1871 | MIPS_SYS(sys_gettimeofday, 2) | |
1872 | MIPS_SYS(sys_settimeofday, 2) | |
1873 | MIPS_SYS(sys_getgroups , 2) /* 4080 */ | |
1874 | MIPS_SYS(sys_setgroups , 2) | |
1875 | MIPS_SYS(sys_ni_syscall , 0) /* old_select */ | |
1876 | MIPS_SYS(sys_symlink , 2) | |
1877 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */ | |
1878 | MIPS_SYS(sys_readlink , 3) /* 4085 */ | |
1879 | MIPS_SYS(sys_uselib , 1) | |
1880 | MIPS_SYS(sys_swapon , 2) | |
1881 | MIPS_SYS(sys_reboot , 3) | |
1882 | MIPS_SYS(old_readdir , 3) | |
1883 | MIPS_SYS(old_mmap , 6) /* 4090 */ | |
1884 | MIPS_SYS(sys_munmap , 2) | |
1885 | MIPS_SYS(sys_truncate , 2) | |
1886 | MIPS_SYS(sys_ftruncate , 2) | |
1887 | MIPS_SYS(sys_fchmod , 2) | |
1888 | MIPS_SYS(sys_fchown , 3) /* 4095 */ | |
1889 | MIPS_SYS(sys_getpriority , 2) | |
1890 | MIPS_SYS(sys_setpriority , 3) | |
1891 | MIPS_SYS(sys_ni_syscall , 0) | |
1892 | MIPS_SYS(sys_statfs , 2) | |
1893 | MIPS_SYS(sys_fstatfs , 2) /* 4100 */ | |
1894 | MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */ | |
1895 | MIPS_SYS(sys_socketcall , 2) | |
1896 | MIPS_SYS(sys_syslog , 3) | |
1897 | MIPS_SYS(sys_setitimer , 3) | |
1898 | MIPS_SYS(sys_getitimer , 2) /* 4105 */ | |
1899 | MIPS_SYS(sys_newstat , 2) | |
1900 | MIPS_SYS(sys_newlstat , 2) | |
1901 | MIPS_SYS(sys_newfstat , 2) | |
1902 | MIPS_SYS(sys_uname , 1) | |
1903 | MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */ | |
1904 | MIPS_SYS(sys_vhangup , 0) | |
1905 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */ | |
1906 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */ | |
1907 | MIPS_SYS(sys_wait4 , 4) | |
1908 | MIPS_SYS(sys_swapoff , 1) /* 4115 */ | |
1909 | MIPS_SYS(sys_sysinfo , 1) | |
1910 | MIPS_SYS(sys_ipc , 6) | |
1911 | MIPS_SYS(sys_fsync , 1) | |
1912 | MIPS_SYS(sys_sigreturn , 0) | |
18113962 | 1913 | MIPS_SYS(sys_clone , 6) /* 4120 */ |
048f6b4d FB |
1914 | MIPS_SYS(sys_setdomainname, 2) |
1915 | MIPS_SYS(sys_newuname , 1) | |
1916 | MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */ | |
1917 | MIPS_SYS(sys_adjtimex , 1) | |
1918 | MIPS_SYS(sys_mprotect , 3) /* 4125 */ | |
1919 | MIPS_SYS(sys_sigprocmask , 3) | |
1920 | MIPS_SYS(sys_ni_syscall , 0) /* was create_module */ | |
1921 | MIPS_SYS(sys_init_module , 5) | |
1922 | MIPS_SYS(sys_delete_module, 1) | |
1923 | MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */ | |
1924 | MIPS_SYS(sys_quotactl , 0) | |
1925 | MIPS_SYS(sys_getpgid , 1) | |
1926 | MIPS_SYS(sys_fchdir , 1) | |
1927 | MIPS_SYS(sys_bdflush , 2) | |
1928 | MIPS_SYS(sys_sysfs , 3) /* 4135 */ | |
1929 | MIPS_SYS(sys_personality , 1) | |
1930 | MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */ | |
1931 | MIPS_SYS(sys_setfsuid , 1) | |
1932 | MIPS_SYS(sys_setfsgid , 1) | |
1933 | MIPS_SYS(sys_llseek , 5) /* 4140 */ | |
1934 | MIPS_SYS(sys_getdents , 3) | |
1935 | MIPS_SYS(sys_select , 5) | |
1936 | MIPS_SYS(sys_flock , 2) | |
1937 | MIPS_SYS(sys_msync , 3) | |
1938 | MIPS_SYS(sys_readv , 3) /* 4145 */ | |
1939 | MIPS_SYS(sys_writev , 3) | |
1940 | MIPS_SYS(sys_cacheflush , 3) | |
1941 | MIPS_SYS(sys_cachectl , 3) | |
1942 | MIPS_SYS(sys_sysmips , 4) | |
1943 | MIPS_SYS(sys_ni_syscall , 0) /* 4150 */ | |
1944 | MIPS_SYS(sys_getsid , 1) | |
1945 | MIPS_SYS(sys_fdatasync , 0) | |
1946 | MIPS_SYS(sys_sysctl , 1) | |
1947 | MIPS_SYS(sys_mlock , 2) | |
1948 | MIPS_SYS(sys_munlock , 2) /* 4155 */ | |
1949 | MIPS_SYS(sys_mlockall , 1) | |
1950 | MIPS_SYS(sys_munlockall , 0) | |
1951 | MIPS_SYS(sys_sched_setparam, 2) | |
1952 | MIPS_SYS(sys_sched_getparam, 2) | |
1953 | MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */ | |
1954 | MIPS_SYS(sys_sched_getscheduler, 1) | |
1955 | MIPS_SYS(sys_sched_yield , 0) | |
1956 | MIPS_SYS(sys_sched_get_priority_max, 1) | |
1957 | MIPS_SYS(sys_sched_get_priority_min, 1) | |
1958 | MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */ | |
1959 | MIPS_SYS(sys_nanosleep, 2) | |
1960 | MIPS_SYS(sys_mremap , 4) | |
1961 | MIPS_SYS(sys_accept , 3) | |
1962 | MIPS_SYS(sys_bind , 3) | |
1963 | MIPS_SYS(sys_connect , 3) /* 4170 */ | |
1964 | MIPS_SYS(sys_getpeername , 3) | |
1965 | MIPS_SYS(sys_getsockname , 3) | |
1966 | MIPS_SYS(sys_getsockopt , 5) | |
1967 | MIPS_SYS(sys_listen , 2) | |
1968 | MIPS_SYS(sys_recv , 4) /* 4175 */ | |
1969 | MIPS_SYS(sys_recvfrom , 6) | |
1970 | MIPS_SYS(sys_recvmsg , 3) | |
1971 | MIPS_SYS(sys_send , 4) | |
1972 | MIPS_SYS(sys_sendmsg , 3) | |
1973 | MIPS_SYS(sys_sendto , 6) /* 4180 */ | |
1974 | MIPS_SYS(sys_setsockopt , 5) | |
1975 | MIPS_SYS(sys_shutdown , 2) | |
1976 | MIPS_SYS(sys_socket , 3) | |
1977 | MIPS_SYS(sys_socketpair , 4) | |
1978 | MIPS_SYS(sys_setresuid , 3) /* 4185 */ | |
1979 | MIPS_SYS(sys_getresuid , 3) | |
1980 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */ | |
1981 | MIPS_SYS(sys_poll , 3) | |
1982 | MIPS_SYS(sys_nfsservctl , 3) | |
1983 | MIPS_SYS(sys_setresgid , 3) /* 4190 */ | |
1984 | MIPS_SYS(sys_getresgid , 3) | |
1985 | MIPS_SYS(sys_prctl , 5) | |
1986 | MIPS_SYS(sys_rt_sigreturn, 0) | |
1987 | MIPS_SYS(sys_rt_sigaction, 4) | |
1988 | MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */ | |
1989 | MIPS_SYS(sys_rt_sigpending, 2) | |
1990 | MIPS_SYS(sys_rt_sigtimedwait, 4) | |
1991 | MIPS_SYS(sys_rt_sigqueueinfo, 3) | |
1992 | MIPS_SYS(sys_rt_sigsuspend, 0) | |
1993 | MIPS_SYS(sys_pread64 , 6) /* 4200 */ | |
1994 | MIPS_SYS(sys_pwrite64 , 6) | |
1995 | MIPS_SYS(sys_chown , 3) | |
1996 | MIPS_SYS(sys_getcwd , 2) | |
1997 | MIPS_SYS(sys_capget , 2) | |
1998 | MIPS_SYS(sys_capset , 2) /* 4205 */ | |
053ebb27 | 1999 | MIPS_SYS(sys_sigaltstack , 2) |
048f6b4d FB |
2000 | MIPS_SYS(sys_sendfile , 4) |
2001 | MIPS_SYS(sys_ni_syscall , 0) | |
2002 | MIPS_SYS(sys_ni_syscall , 0) | |
2003 | MIPS_SYS(sys_mmap2 , 6) /* 4210 */ | |
2004 | MIPS_SYS(sys_truncate64 , 4) | |
2005 | MIPS_SYS(sys_ftruncate64 , 4) | |
2006 | MIPS_SYS(sys_stat64 , 2) | |
2007 | MIPS_SYS(sys_lstat64 , 2) | |
2008 | MIPS_SYS(sys_fstat64 , 2) /* 4215 */ | |
2009 | MIPS_SYS(sys_pivot_root , 2) | |
2010 | MIPS_SYS(sys_mincore , 3) | |
2011 | MIPS_SYS(sys_madvise , 3) | |
2012 | MIPS_SYS(sys_getdents64 , 3) | |
2013 | MIPS_SYS(sys_fcntl64 , 3) /* 4220 */ | |
2014 | MIPS_SYS(sys_ni_syscall , 0) | |
2015 | MIPS_SYS(sys_gettid , 0) | |
2016 | MIPS_SYS(sys_readahead , 5) | |
2017 | MIPS_SYS(sys_setxattr , 5) | |
2018 | MIPS_SYS(sys_lsetxattr , 5) /* 4225 */ | |
2019 | MIPS_SYS(sys_fsetxattr , 5) | |
2020 | MIPS_SYS(sys_getxattr , 4) | |
2021 | MIPS_SYS(sys_lgetxattr , 4) | |
2022 | MIPS_SYS(sys_fgetxattr , 4) | |
2023 | MIPS_SYS(sys_listxattr , 3) /* 4230 */ | |
2024 | MIPS_SYS(sys_llistxattr , 3) | |
2025 | MIPS_SYS(sys_flistxattr , 3) | |
2026 | MIPS_SYS(sys_removexattr , 2) | |
2027 | MIPS_SYS(sys_lremovexattr, 2) | |
2028 | MIPS_SYS(sys_fremovexattr, 2) /* 4235 */ | |
2029 | MIPS_SYS(sys_tkill , 2) | |
2030 | MIPS_SYS(sys_sendfile64 , 5) | |
2031 | MIPS_SYS(sys_futex , 2) | |
2032 | MIPS_SYS(sys_sched_setaffinity, 3) | |
2033 | MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */ | |
2034 | MIPS_SYS(sys_io_setup , 2) | |
2035 | MIPS_SYS(sys_io_destroy , 1) | |
2036 | MIPS_SYS(sys_io_getevents, 5) | |
2037 | MIPS_SYS(sys_io_submit , 3) | |
2038 | MIPS_SYS(sys_io_cancel , 3) /* 4245 */ | |
2039 | MIPS_SYS(sys_exit_group , 1) | |
2040 | MIPS_SYS(sys_lookup_dcookie, 3) | |
2041 | MIPS_SYS(sys_epoll_create, 1) | |
2042 | MIPS_SYS(sys_epoll_ctl , 4) | |
2043 | MIPS_SYS(sys_epoll_wait , 3) /* 4250 */ | |
2044 | MIPS_SYS(sys_remap_file_pages, 5) | |
2045 | MIPS_SYS(sys_set_tid_address, 1) | |
2046 | MIPS_SYS(sys_restart_syscall, 0) | |
2047 | MIPS_SYS(sys_fadvise64_64, 7) | |
2048 | MIPS_SYS(sys_statfs64 , 3) /* 4255 */ | |
2049 | MIPS_SYS(sys_fstatfs64 , 2) | |
2050 | MIPS_SYS(sys_timer_create, 3) | |
2051 | MIPS_SYS(sys_timer_settime, 4) | |
2052 | MIPS_SYS(sys_timer_gettime, 2) | |
2053 | MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */ | |
2054 | MIPS_SYS(sys_timer_delete, 1) | |
2055 | MIPS_SYS(sys_clock_settime, 2) | |
2056 | MIPS_SYS(sys_clock_gettime, 2) | |
2057 | MIPS_SYS(sys_clock_getres, 2) | |
2058 | MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */ | |
2059 | MIPS_SYS(sys_tgkill , 3) | |
2060 | MIPS_SYS(sys_utimes , 2) | |
2061 | MIPS_SYS(sys_mbind , 4) | |
2062 | MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */ | |
2063 | MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */ | |
2064 | MIPS_SYS(sys_mq_open , 4) | |
2065 | MIPS_SYS(sys_mq_unlink , 1) | |
2066 | MIPS_SYS(sys_mq_timedsend, 5) | |
2067 | MIPS_SYS(sys_mq_timedreceive, 5) | |
2068 | MIPS_SYS(sys_mq_notify , 2) /* 4275 */ | |
2069 | MIPS_SYS(sys_mq_getsetattr, 3) | |
2070 | MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */ | |
2071 | MIPS_SYS(sys_waitid , 4) | |
2072 | MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */ | |
2073 | MIPS_SYS(sys_add_key , 5) | |
388bb21a | 2074 | MIPS_SYS(sys_request_key, 4) |
048f6b4d | 2075 | MIPS_SYS(sys_keyctl , 5) |
6f5b89a0 | 2076 | MIPS_SYS(sys_set_thread_area, 1) |
388bb21a TS |
2077 | MIPS_SYS(sys_inotify_init, 0) |
2078 | MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */ | |
2079 | MIPS_SYS(sys_inotify_rm_watch, 2) | |
2080 | MIPS_SYS(sys_migrate_pages, 4) | |
2081 | MIPS_SYS(sys_openat, 4) | |
2082 | MIPS_SYS(sys_mkdirat, 3) | |
2083 | MIPS_SYS(sys_mknodat, 4) /* 4290 */ | |
2084 | MIPS_SYS(sys_fchownat, 5) | |
2085 | MIPS_SYS(sys_futimesat, 3) | |
2086 | MIPS_SYS(sys_fstatat64, 4) | |
2087 | MIPS_SYS(sys_unlinkat, 3) | |
2088 | MIPS_SYS(sys_renameat, 4) /* 4295 */ | |
2089 | MIPS_SYS(sys_linkat, 5) | |
2090 | MIPS_SYS(sys_symlinkat, 3) | |
2091 | MIPS_SYS(sys_readlinkat, 4) | |
2092 | MIPS_SYS(sys_fchmodat, 3) | |
2093 | MIPS_SYS(sys_faccessat, 3) /* 4300 */ | |
2094 | MIPS_SYS(sys_pselect6, 6) | |
2095 | MIPS_SYS(sys_ppoll, 5) | |
2096 | MIPS_SYS(sys_unshare, 1) | |
2097 | MIPS_SYS(sys_splice, 4) | |
2098 | MIPS_SYS(sys_sync_file_range, 7) /* 4305 */ | |
2099 | MIPS_SYS(sys_tee, 4) | |
2100 | MIPS_SYS(sys_vmsplice, 4) | |
2101 | MIPS_SYS(sys_move_pages, 6) | |
2102 | MIPS_SYS(sys_set_robust_list, 2) | |
2103 | MIPS_SYS(sys_get_robust_list, 3) /* 4310 */ | |
2104 | MIPS_SYS(sys_kexec_load, 4) | |
2105 | MIPS_SYS(sys_getcpu, 3) | |
2106 | MIPS_SYS(sys_epoll_pwait, 6) | |
2107 | MIPS_SYS(sys_ioprio_set, 3) | |
2108 | MIPS_SYS(sys_ioprio_get, 2) | |
d979e8eb PM |
2109 | MIPS_SYS(sys_utimensat, 4) |
2110 | MIPS_SYS(sys_signalfd, 3) | |
2111 | MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */ | |
2112 | MIPS_SYS(sys_eventfd, 1) | |
2113 | MIPS_SYS(sys_fallocate, 6) /* 4320 */ | |
2114 | MIPS_SYS(sys_timerfd_create, 2) | |
2115 | MIPS_SYS(sys_timerfd_gettime, 2) | |
2116 | MIPS_SYS(sys_timerfd_settime, 4) | |
2117 | MIPS_SYS(sys_signalfd4, 4) | |
2118 | MIPS_SYS(sys_eventfd2, 2) /* 4325 */ | |
2119 | MIPS_SYS(sys_epoll_create1, 1) | |
2120 | MIPS_SYS(sys_dup3, 3) | |
2121 | MIPS_SYS(sys_pipe2, 2) | |
2122 | MIPS_SYS(sys_inotify_init1, 1) | |
2123 | MIPS_SYS(sys_preadv, 6) /* 4330 */ | |
2124 | MIPS_SYS(sys_pwritev, 6) | |
2125 | MIPS_SYS(sys_rt_tgsigqueueinfo, 4) | |
2126 | MIPS_SYS(sys_perf_event_open, 5) | |
2127 | MIPS_SYS(sys_accept4, 4) | |
2128 | MIPS_SYS(sys_recvmmsg, 5) /* 4335 */ | |
2129 | MIPS_SYS(sys_fanotify_init, 2) | |
2130 | MIPS_SYS(sys_fanotify_mark, 6) | |
2131 | MIPS_SYS(sys_prlimit64, 4) | |
2132 | MIPS_SYS(sys_name_to_handle_at, 5) | |
2133 | MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */ | |
2134 | MIPS_SYS(sys_clock_adjtime, 2) | |
2135 | MIPS_SYS(sys_syncfs, 1) | |
048f6b4d | 2136 | }; |
ff4f7382 RH |
2137 | # undef MIPS_SYS |
2138 | # endif /* O32 */ | |
048f6b4d | 2139 | |
590bc601 PB |
2140 | static int do_store_exclusive(CPUMIPSState *env) |
2141 | { | |
2142 | target_ulong addr; | |
2143 | target_ulong page_addr; | |
2144 | target_ulong val; | |
2145 | int flags; | |
2146 | int segv = 0; | |
2147 | int reg; | |
2148 | int d; | |
2149 | ||
5499b6ff | 2150 | addr = env->lladdr; |
590bc601 PB |
2151 | page_addr = addr & TARGET_PAGE_MASK; |
2152 | start_exclusive(); | |
2153 | mmap_lock(); | |
2154 | flags = page_get_flags(page_addr); | |
2155 | if ((flags & PAGE_READ) == 0) { | |
2156 | segv = 1; | |
2157 | } else { | |
2158 | reg = env->llreg & 0x1f; | |
2159 | d = (env->llreg & 0x20) != 0; | |
2160 | if (d) { | |
2161 | segv = get_user_s64(val, addr); | |
2162 | } else { | |
2163 | segv = get_user_s32(val, addr); | |
2164 | } | |
2165 | if (!segv) { | |
2166 | if (val != env->llval) { | |
2167 | env->active_tc.gpr[reg] = 0; | |
2168 | } else { | |
2169 | if (d) { | |
2170 | segv = put_user_u64(env->llnewval, addr); | |
2171 | } else { | |
2172 | segv = put_user_u32(env->llnewval, addr); | |
2173 | } | |
2174 | if (!segv) { | |
2175 | env->active_tc.gpr[reg] = 1; | |
2176 | } | |
2177 | } | |
2178 | } | |
2179 | } | |
5499b6ff | 2180 | env->lladdr = -1; |
590bc601 PB |
2181 | if (!segv) { |
2182 | env->active_tc.PC += 4; | |
2183 | } | |
2184 | mmap_unlock(); | |
2185 | end_exclusive(); | |
2186 | return segv; | |
2187 | } | |
2188 | ||
54b2f42c MI |
2189 | /* Break codes */ |
2190 | enum { | |
2191 | BRK_OVERFLOW = 6, | |
2192 | BRK_DIVZERO = 7 | |
2193 | }; | |
2194 | ||
2195 | static int do_break(CPUMIPSState *env, target_siginfo_t *info, | |
2196 | unsigned int code) | |
2197 | { | |
2198 | int ret = -1; | |
2199 | ||
2200 | switch (code) { | |
2201 | case BRK_OVERFLOW: | |
2202 | case BRK_DIVZERO: | |
2203 | info->si_signo = TARGET_SIGFPE; | |
2204 | info->si_errno = 0; | |
2205 | info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV; | |
2206 | queue_signal(env, info->si_signo, &*info); | |
2207 | ret = 0; | |
2208 | break; | |
2209 | default: | |
2210 | break; | |
2211 | } | |
2212 | ||
2213 | return ret; | |
2214 | } | |
2215 | ||
048f6b4d FB |
2216 | void cpu_loop(CPUMIPSState *env) |
2217 | { | |
0315c31c | 2218 | CPUState *cs = CPU(mips_env_get_cpu(env)); |
c227f099 | 2219 | target_siginfo_t info; |
ff4f7382 RH |
2220 | int trapnr; |
2221 | abi_long ret; | |
2222 | # ifdef TARGET_ABI_MIPSO32 | |
048f6b4d | 2223 | unsigned int syscall_num; |
ff4f7382 | 2224 | # endif |
048f6b4d FB |
2225 | |
2226 | for(;;) { | |
0315c31c | 2227 | cpu_exec_start(cs); |
048f6b4d | 2228 | trapnr = cpu_mips_exec(env); |
0315c31c | 2229 | cpu_exec_end(cs); |
048f6b4d FB |
2230 | switch(trapnr) { |
2231 | case EXCP_SYSCALL: | |
b5dc7732 | 2232 | env->active_tc.PC += 4; |
ff4f7382 RH |
2233 | # ifdef TARGET_ABI_MIPSO32 |
2234 | syscall_num = env->active_tc.gpr[2] - 4000; | |
388bb21a | 2235 | if (syscall_num >= sizeof(mips_syscall_args)) { |
7c2f6157 | 2236 | ret = -TARGET_ENOSYS; |
388bb21a TS |
2237 | } else { |
2238 | int nb_args; | |
992f48a0 BS |
2239 | abi_ulong sp_reg; |
2240 | abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0; | |
388bb21a TS |
2241 | |
2242 | nb_args = mips_syscall_args[syscall_num]; | |
b5dc7732 | 2243 | sp_reg = env->active_tc.gpr[29]; |
388bb21a TS |
2244 | switch (nb_args) { |
2245 | /* these arguments are taken from the stack */ | |
94c19610 ACH |
2246 | case 8: |
2247 | if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) { | |
2248 | goto done_syscall; | |
2249 | } | |
2250 | case 7: | |
2251 | if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) { | |
2252 | goto done_syscall; | |
2253 | } | |
2254 | case 6: | |
2255 | if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) { | |
2256 | goto done_syscall; | |
2257 | } | |
2258 | case 5: | |
2259 | if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) { | |
2260 | goto done_syscall; | |
2261 | } | |
388bb21a TS |
2262 | default: |
2263 | break; | |
048f6b4d | 2264 | } |
b5dc7732 TS |
2265 | ret = do_syscall(env, env->active_tc.gpr[2], |
2266 | env->active_tc.gpr[4], | |
2267 | env->active_tc.gpr[5], | |
2268 | env->active_tc.gpr[6], | |
2269 | env->active_tc.gpr[7], | |
5945cfcb | 2270 | arg5, arg6, arg7, arg8); |
388bb21a | 2271 | } |
94c19610 | 2272 | done_syscall: |
ff4f7382 RH |
2273 | # else |
2274 | ret = do_syscall(env, env->active_tc.gpr[2], | |
2275 | env->active_tc.gpr[4], env->active_tc.gpr[5], | |
2276 | env->active_tc.gpr[6], env->active_tc.gpr[7], | |
2277 | env->active_tc.gpr[8], env->active_tc.gpr[9], | |
2278 | env->active_tc.gpr[10], env->active_tc.gpr[11]); | |
2279 | # endif /* O32 */ | |
0b1bcb00 PB |
2280 | if (ret == -TARGET_QEMU_ESIGRETURN) { |
2281 | /* Returning from a successful sigreturn syscall. | |
2282 | Avoid clobbering register state. */ | |
2283 | break; | |
2284 | } | |
ff4f7382 | 2285 | if ((abi_ulong)ret >= (abi_ulong)-1133) { |
b5dc7732 | 2286 | env->active_tc.gpr[7] = 1; /* error flag */ |
388bb21a TS |
2287 | ret = -ret; |
2288 | } else { | |
b5dc7732 | 2289 | env->active_tc.gpr[7] = 0; /* error flag */ |
048f6b4d | 2290 | } |
b5dc7732 | 2291 | env->active_tc.gpr[2] = ret; |
048f6b4d | 2292 | break; |
ca7c2b1b TS |
2293 | case EXCP_TLBL: |
2294 | case EXCP_TLBS: | |
e6e5bd2d WT |
2295 | case EXCP_AdEL: |
2296 | case EXCP_AdES: | |
e4474235 PB |
2297 | info.si_signo = TARGET_SIGSEGV; |
2298 | info.si_errno = 0; | |
2299 | /* XXX: check env->error_code */ | |
2300 | info.si_code = TARGET_SEGV_MAPERR; | |
2301 | info._sifields._sigfault._addr = env->CP0_BadVAddr; | |
2302 | queue_signal(env, info.si_signo, &info); | |
2303 | break; | |
6900e84b | 2304 | case EXCP_CpU: |
048f6b4d | 2305 | case EXCP_RI: |
bc1ad2de FB |
2306 | info.si_signo = TARGET_SIGILL; |
2307 | info.si_errno = 0; | |
2308 | info.si_code = 0; | |
624f7979 | 2309 | queue_signal(env, info.si_signo, &info); |
048f6b4d | 2310 | break; |
106ec879 FB |
2311 | case EXCP_INTERRUPT: |
2312 | /* just indicate that signals should be handled asap */ | |
2313 | break; | |
d08b2a28 PB |
2314 | case EXCP_DEBUG: |
2315 | { | |
2316 | int sig; | |
2317 | ||
2318 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
2319 | if (sig) | |
2320 | { | |
2321 | info.si_signo = sig; | |
2322 | info.si_errno = 0; | |
2323 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 2324 | queue_signal(env, info.si_signo, &info); |
d08b2a28 PB |
2325 | } |
2326 | } | |
2327 | break; | |
590bc601 PB |
2328 | case EXCP_SC: |
2329 | if (do_store_exclusive(env)) { | |
2330 | info.si_signo = TARGET_SIGSEGV; | |
2331 | info.si_errno = 0; | |
2332 | info.si_code = TARGET_SEGV_MAPERR; | |
2333 | info._sifields._sigfault._addr = env->active_tc.PC; | |
2334 | queue_signal(env, info.si_signo, &info); | |
2335 | } | |
2336 | break; | |
853c3240 JL |
2337 | case EXCP_DSPDIS: |
2338 | info.si_signo = TARGET_SIGILL; | |
2339 | info.si_errno = 0; | |
2340 | info.si_code = TARGET_ILL_ILLOPC; | |
2341 | queue_signal(env, info.si_signo, &info); | |
2342 | break; | |
54b2f42c MI |
2343 | /* The code below was inspired by the MIPS Linux kernel trap |
2344 | * handling code in arch/mips/kernel/traps.c. | |
2345 | */ | |
2346 | case EXCP_BREAK: | |
2347 | { | |
2348 | abi_ulong trap_instr; | |
2349 | unsigned int code; | |
2350 | ||
2351 | ret = get_user_ual(trap_instr, env->active_tc.PC); | |
2352 | if (ret != 0) { | |
2353 | goto error; | |
2354 | } | |
2355 | ||
2356 | /* As described in the original Linux kernel code, the | |
2357 | * below checks on 'code' are to work around an old | |
2358 | * assembly bug. | |
2359 | */ | |
2360 | code = ((trap_instr >> 6) & ((1 << 20) - 1)); | |
2361 | if (code >= (1 << 10)) { | |
2362 | code >>= 10; | |
2363 | } | |
2364 | ||
2365 | if (do_break(env, &info, code) != 0) { | |
2366 | goto error; | |
2367 | } | |
2368 | } | |
2369 | break; | |
2370 | case EXCP_TRAP: | |
2371 | { | |
2372 | abi_ulong trap_instr; | |
2373 | unsigned int code = 0; | |
2374 | ||
2375 | ret = get_user_ual(trap_instr, env->active_tc.PC); | |
2376 | if (ret != 0) { | |
2377 | goto error; | |
2378 | } | |
2379 | ||
2380 | /* The immediate versions don't provide a code. */ | |
2381 | if (!(trap_instr & 0xFC000000)) { | |
2382 | code = ((trap_instr >> 6) & ((1 << 10) - 1)); | |
2383 | } | |
2384 | ||
2385 | if (do_break(env, &info, code) != 0) { | |
2386 | goto error; | |
2387 | } | |
2388 | } | |
2389 | break; | |
048f6b4d | 2390 | default: |
54b2f42c | 2391 | error: |
5fafdf24 | 2392 | fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", |
048f6b4d | 2393 | trapnr); |
878096ee | 2394 | cpu_dump_state(cs, stderr, fprintf, 0); |
048f6b4d FB |
2395 | abort(); |
2396 | } | |
2397 | process_pending_signals(env); | |
2398 | } | |
2399 | } | |
2400 | #endif | |
2401 | ||
d962783e JL |
2402 | #ifdef TARGET_OPENRISC |
2403 | ||
2404 | void cpu_loop(CPUOpenRISCState *env) | |
2405 | { | |
878096ee | 2406 | CPUState *cs = CPU(openrisc_env_get_cpu(env)); |
d962783e JL |
2407 | int trapnr, gdbsig; |
2408 | ||
2409 | for (;;) { | |
2410 | trapnr = cpu_exec(env); | |
2411 | gdbsig = 0; | |
2412 | ||
2413 | switch (trapnr) { | |
2414 | case EXCP_RESET: | |
2415 | qemu_log("\nReset request, exit, pc is %#x\n", env->pc); | |
2416 | exit(1); | |
2417 | break; | |
2418 | case EXCP_BUSERR: | |
2419 | qemu_log("\nBus error, exit, pc is %#x\n", env->pc); | |
2420 | gdbsig = SIGBUS; | |
2421 | break; | |
2422 | case EXCP_DPF: | |
2423 | case EXCP_IPF: | |
878096ee | 2424 | cpu_dump_state(cs, stderr, fprintf, 0); |
d962783e JL |
2425 | gdbsig = TARGET_SIGSEGV; |
2426 | break; | |
2427 | case EXCP_TICK: | |
2428 | qemu_log("\nTick time interrupt pc is %#x\n", env->pc); | |
2429 | break; | |
2430 | case EXCP_ALIGN: | |
2431 | qemu_log("\nAlignment pc is %#x\n", env->pc); | |
2432 | gdbsig = SIGBUS; | |
2433 | break; | |
2434 | case EXCP_ILLEGAL: | |
2435 | qemu_log("\nIllegal instructionpc is %#x\n", env->pc); | |
2436 | gdbsig = SIGILL; | |
2437 | break; | |
2438 | case EXCP_INT: | |
2439 | qemu_log("\nExternal interruptpc is %#x\n", env->pc); | |
2440 | break; | |
2441 | case EXCP_DTLBMISS: | |
2442 | case EXCP_ITLBMISS: | |
2443 | qemu_log("\nTLB miss\n"); | |
2444 | break; | |
2445 | case EXCP_RANGE: | |
2446 | qemu_log("\nRange\n"); | |
2447 | gdbsig = SIGSEGV; | |
2448 | break; | |
2449 | case EXCP_SYSCALL: | |
2450 | env->pc += 4; /* 0xc00; */ | |
2451 | env->gpr[11] = do_syscall(env, | |
2452 | env->gpr[11], /* return value */ | |
2453 | env->gpr[3], /* r3 - r7 are params */ | |
2454 | env->gpr[4], | |
2455 | env->gpr[5], | |
2456 | env->gpr[6], | |
2457 | env->gpr[7], | |
2458 | env->gpr[8], 0, 0); | |
2459 | break; | |
2460 | case EXCP_FPE: | |
2461 | qemu_log("\nFloating point error\n"); | |
2462 | break; | |
2463 | case EXCP_TRAP: | |
2464 | qemu_log("\nTrap\n"); | |
2465 | gdbsig = SIGTRAP; | |
2466 | break; | |
2467 | case EXCP_NR: | |
2468 | qemu_log("\nNR\n"); | |
2469 | break; | |
2470 | default: | |
2471 | qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n", | |
2472 | trapnr); | |
878096ee | 2473 | cpu_dump_state(cs, stderr, fprintf, 0); |
d962783e JL |
2474 | gdbsig = TARGET_SIGILL; |
2475 | break; | |
2476 | } | |
2477 | if (gdbsig) { | |
2478 | gdb_handlesig(env, gdbsig); | |
2479 | if (gdbsig != TARGET_SIGTRAP) { | |
2480 | exit(1); | |
2481 | } | |
2482 | } | |
2483 | ||
2484 | process_pending_signals(env); | |
2485 | } | |
2486 | } | |
2487 | ||
2488 | #endif /* TARGET_OPENRISC */ | |
2489 | ||
fdf9b3e8 | 2490 | #ifdef TARGET_SH4 |
05390248 | 2491 | void cpu_loop(CPUSH4State *env) |
fdf9b3e8 | 2492 | { |
878096ee | 2493 | CPUState *cs = CPU(sh_env_get_cpu(env)); |
fdf9b3e8 | 2494 | int trapnr, ret; |
c227f099 | 2495 | target_siginfo_t info; |
3b46e624 | 2496 | |
fdf9b3e8 FB |
2497 | while (1) { |
2498 | trapnr = cpu_sh4_exec (env); | |
3b46e624 | 2499 | |
fdf9b3e8 FB |
2500 | switch (trapnr) { |
2501 | case 0x160: | |
0b6d3ae0 | 2502 | env->pc += 2; |
5fafdf24 TS |
2503 | ret = do_syscall(env, |
2504 | env->gregs[3], | |
2505 | env->gregs[4], | |
2506 | env->gregs[5], | |
2507 | env->gregs[6], | |
2508 | env->gregs[7], | |
2509 | env->gregs[0], | |
5945cfcb PM |
2510 | env->gregs[1], |
2511 | 0, 0); | |
9c2a9ea1 | 2512 | env->gregs[0] = ret; |
fdf9b3e8 | 2513 | break; |
c3b5bc8a TS |
2514 | case EXCP_INTERRUPT: |
2515 | /* just indicate that signals should be handled asap */ | |
2516 | break; | |
355fb23d PB |
2517 | case EXCP_DEBUG: |
2518 | { | |
2519 | int sig; | |
2520 | ||
2521 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
2522 | if (sig) | |
2523 | { | |
2524 | info.si_signo = sig; | |
2525 | info.si_errno = 0; | |
2526 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 2527 | queue_signal(env, info.si_signo, &info); |
355fb23d PB |
2528 | } |
2529 | } | |
2530 | break; | |
c3b5bc8a TS |
2531 | case 0xa0: |
2532 | case 0xc0: | |
2533 | info.si_signo = SIGSEGV; | |
2534 | info.si_errno = 0; | |
2535 | info.si_code = TARGET_SEGV_MAPERR; | |
2536 | info._sifields._sigfault._addr = env->tea; | |
624f7979 | 2537 | queue_signal(env, info.si_signo, &info); |
c3b5bc8a TS |
2538 | break; |
2539 | ||
fdf9b3e8 FB |
2540 | default: |
2541 | printf ("Unhandled trap: 0x%x\n", trapnr); | |
878096ee | 2542 | cpu_dump_state(cs, stderr, fprintf, 0); |
fdf9b3e8 FB |
2543 | exit (1); |
2544 | } | |
2545 | process_pending_signals (env); | |
2546 | } | |
2547 | } | |
2548 | #endif | |
2549 | ||
48733d19 | 2550 | #ifdef TARGET_CRIS |
05390248 | 2551 | void cpu_loop(CPUCRISState *env) |
48733d19 | 2552 | { |
878096ee | 2553 | CPUState *cs = CPU(cris_env_get_cpu(env)); |
48733d19 | 2554 | int trapnr, ret; |
c227f099 | 2555 | target_siginfo_t info; |
48733d19 TS |
2556 | |
2557 | while (1) { | |
2558 | trapnr = cpu_cris_exec (env); | |
2559 | switch (trapnr) { | |
2560 | case 0xaa: | |
2561 | { | |
2562 | info.si_signo = SIGSEGV; | |
2563 | info.si_errno = 0; | |
2564 | /* XXX: check env->error_code */ | |
2565 | info.si_code = TARGET_SEGV_MAPERR; | |
e00c1e71 | 2566 | info._sifields._sigfault._addr = env->pregs[PR_EDA]; |
624f7979 | 2567 | queue_signal(env, info.si_signo, &info); |
48733d19 TS |
2568 | } |
2569 | break; | |
b6d3abda EI |
2570 | case EXCP_INTERRUPT: |
2571 | /* just indicate that signals should be handled asap */ | |
2572 | break; | |
48733d19 TS |
2573 | case EXCP_BREAK: |
2574 | ret = do_syscall(env, | |
2575 | env->regs[9], | |
2576 | env->regs[10], | |
2577 | env->regs[11], | |
2578 | env->regs[12], | |
2579 | env->regs[13], | |
2580 | env->pregs[7], | |
5945cfcb PM |
2581 | env->pregs[11], |
2582 | 0, 0); | |
48733d19 | 2583 | env->regs[10] = ret; |
48733d19 TS |
2584 | break; |
2585 | case EXCP_DEBUG: | |
2586 | { | |
2587 | int sig; | |
2588 | ||
2589 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
2590 | if (sig) | |
2591 | { | |
2592 | info.si_signo = sig; | |
2593 | info.si_errno = 0; | |
2594 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 2595 | queue_signal(env, info.si_signo, &info); |
48733d19 TS |
2596 | } |
2597 | } | |
2598 | break; | |
2599 | default: | |
2600 | printf ("Unhandled trap: 0x%x\n", trapnr); | |
878096ee | 2601 | cpu_dump_state(cs, stderr, fprintf, 0); |
48733d19 TS |
2602 | exit (1); |
2603 | } | |
2604 | process_pending_signals (env); | |
2605 | } | |
2606 | } | |
2607 | #endif | |
2608 | ||
b779e29e | 2609 | #ifdef TARGET_MICROBLAZE |
05390248 | 2610 | void cpu_loop(CPUMBState *env) |
b779e29e | 2611 | { |
878096ee | 2612 | CPUState *cs = CPU(mb_env_get_cpu(env)); |
b779e29e | 2613 | int trapnr, ret; |
c227f099 | 2614 | target_siginfo_t info; |
b779e29e EI |
2615 | |
2616 | while (1) { | |
2617 | trapnr = cpu_mb_exec (env); | |
2618 | switch (trapnr) { | |
2619 | case 0xaa: | |
2620 | { | |
2621 | info.si_signo = SIGSEGV; | |
2622 | info.si_errno = 0; | |
2623 | /* XXX: check env->error_code */ | |
2624 | info.si_code = TARGET_SEGV_MAPERR; | |
2625 | info._sifields._sigfault._addr = 0; | |
2626 | queue_signal(env, info.si_signo, &info); | |
2627 | } | |
2628 | break; | |
2629 | case EXCP_INTERRUPT: | |
2630 | /* just indicate that signals should be handled asap */ | |
2631 | break; | |
2632 | case EXCP_BREAK: | |
2633 | /* Return address is 4 bytes after the call. */ | |
2634 | env->regs[14] += 4; | |
d7dce494 | 2635 | env->sregs[SR_PC] = env->regs[14]; |
b779e29e EI |
2636 | ret = do_syscall(env, |
2637 | env->regs[12], | |
2638 | env->regs[5], | |
2639 | env->regs[6], | |
2640 | env->regs[7], | |
2641 | env->regs[8], | |
2642 | env->regs[9], | |
5945cfcb PM |
2643 | env->regs[10], |
2644 | 0, 0); | |
b779e29e | 2645 | env->regs[3] = ret; |
b779e29e | 2646 | break; |
b76da7e3 EI |
2647 | case EXCP_HW_EXCP: |
2648 | env->regs[17] = env->sregs[SR_PC] + 4; | |
2649 | if (env->iflags & D_FLAG) { | |
2650 | env->sregs[SR_ESR] |= 1 << 12; | |
2651 | env->sregs[SR_PC] -= 4; | |
b4916d7b | 2652 | /* FIXME: if branch was immed, replay the imm as well. */ |
b76da7e3 EI |
2653 | } |
2654 | ||
2655 | env->iflags &= ~(IMM_FLAG | D_FLAG); | |
2656 | ||
2657 | switch (env->sregs[SR_ESR] & 31) { | |
22a78d64 EI |
2658 | case ESR_EC_DIVZERO: |
2659 | info.si_signo = SIGFPE; | |
2660 | info.si_errno = 0; | |
2661 | info.si_code = TARGET_FPE_FLTDIV; | |
2662 | info._sifields._sigfault._addr = 0; | |
2663 | queue_signal(env, info.si_signo, &info); | |
2664 | break; | |
b76da7e3 EI |
2665 | case ESR_EC_FPU: |
2666 | info.si_signo = SIGFPE; | |
2667 | info.si_errno = 0; | |
2668 | if (env->sregs[SR_FSR] & FSR_IO) { | |
2669 | info.si_code = TARGET_FPE_FLTINV; | |
2670 | } | |
2671 | if (env->sregs[SR_FSR] & FSR_DZ) { | |
2672 | info.si_code = TARGET_FPE_FLTDIV; | |
2673 | } | |
2674 | info._sifields._sigfault._addr = 0; | |
2675 | queue_signal(env, info.si_signo, &info); | |
2676 | break; | |
2677 | default: | |
2678 | printf ("Unhandled hw-exception: 0x%x\n", | |
2e42d52d | 2679 | env->sregs[SR_ESR] & ESR_EC_MASK); |
878096ee | 2680 | cpu_dump_state(cs, stderr, fprintf, 0); |
b76da7e3 EI |
2681 | exit (1); |
2682 | break; | |
2683 | } | |
2684 | break; | |
b779e29e EI |
2685 | case EXCP_DEBUG: |
2686 | { | |
2687 | int sig; | |
2688 | ||
2689 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
2690 | if (sig) | |
2691 | { | |
2692 | info.si_signo = sig; | |
2693 | info.si_errno = 0; | |
2694 | info.si_code = TARGET_TRAP_BRKPT; | |
2695 | queue_signal(env, info.si_signo, &info); | |
2696 | } | |
2697 | } | |
2698 | break; | |
2699 | default: | |
2700 | printf ("Unhandled trap: 0x%x\n", trapnr); | |
878096ee | 2701 | cpu_dump_state(cs, stderr, fprintf, 0); |
b779e29e EI |
2702 | exit (1); |
2703 | } | |
2704 | process_pending_signals (env); | |
2705 | } | |
2706 | } | |
2707 | #endif | |
2708 | ||
e6e5906b PB |
2709 | #ifdef TARGET_M68K |
2710 | ||
2711 | void cpu_loop(CPUM68KState *env) | |
2712 | { | |
878096ee | 2713 | CPUState *cs = CPU(m68k_env_get_cpu(env)); |
e6e5906b PB |
2714 | int trapnr; |
2715 | unsigned int n; | |
c227f099 | 2716 | target_siginfo_t info; |
e6e5906b | 2717 | TaskState *ts = env->opaque; |
3b46e624 | 2718 | |
e6e5906b PB |
2719 | for(;;) { |
2720 | trapnr = cpu_m68k_exec(env); | |
2721 | switch(trapnr) { | |
2722 | case EXCP_ILLEGAL: | |
2723 | { | |
2724 | if (ts->sim_syscalls) { | |
2725 | uint16_t nr; | |
2726 | nr = lduw(env->pc + 2); | |
2727 | env->pc += 4; | |
2728 | do_m68k_simcall(env, nr); | |
2729 | } else { | |
2730 | goto do_sigill; | |
2731 | } | |
2732 | } | |
2733 | break; | |
a87295e8 | 2734 | case EXCP_HALT_INSN: |
e6e5906b | 2735 | /* Semihosing syscall. */ |
a87295e8 | 2736 | env->pc += 4; |
e6e5906b PB |
2737 | do_m68k_semihosting(env, env->dregs[0]); |
2738 | break; | |
2739 | case EXCP_LINEA: | |
2740 | case EXCP_LINEF: | |
2741 | case EXCP_UNSUPPORTED: | |
2742 | do_sigill: | |
2743 | info.si_signo = SIGILL; | |
2744 | info.si_errno = 0; | |
2745 | info.si_code = TARGET_ILL_ILLOPN; | |
2746 | info._sifields._sigfault._addr = env->pc; | |
624f7979 | 2747 | queue_signal(env, info.si_signo, &info); |
e6e5906b PB |
2748 | break; |
2749 | case EXCP_TRAP0: | |
2750 | { | |
2751 | ts->sim_syscalls = 0; | |
2752 | n = env->dregs[0]; | |
2753 | env->pc += 2; | |
5fafdf24 TS |
2754 | env->dregs[0] = do_syscall(env, |
2755 | n, | |
e6e5906b PB |
2756 | env->dregs[1], |
2757 | env->dregs[2], | |
2758 | env->dregs[3], | |
2759 | env->dregs[4], | |
2760 | env->dregs[5], | |
5945cfcb PM |
2761 | env->aregs[0], |
2762 | 0, 0); | |
e6e5906b PB |
2763 | } |
2764 | break; | |
2765 | case EXCP_INTERRUPT: | |
2766 | /* just indicate that signals should be handled asap */ | |
2767 | break; | |
2768 | case EXCP_ACCESS: | |
2769 | { | |
2770 | info.si_signo = SIGSEGV; | |
2771 | info.si_errno = 0; | |
2772 | /* XXX: check env->error_code */ | |
2773 | info.si_code = TARGET_SEGV_MAPERR; | |
2774 | info._sifields._sigfault._addr = env->mmu.ar; | |
624f7979 | 2775 | queue_signal(env, info.si_signo, &info); |
e6e5906b PB |
2776 | } |
2777 | break; | |
2778 | case EXCP_DEBUG: | |
2779 | { | |
2780 | int sig; | |
2781 | ||
2782 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
2783 | if (sig) | |
2784 | { | |
2785 | info.si_signo = sig; | |
2786 | info.si_errno = 0; | |
2787 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 2788 | queue_signal(env, info.si_signo, &info); |
e6e5906b PB |
2789 | } |
2790 | } | |
2791 | break; | |
2792 | default: | |
5fafdf24 | 2793 | fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", |
e6e5906b | 2794 | trapnr); |
878096ee | 2795 | cpu_dump_state(cs, stderr, fprintf, 0); |
e6e5906b PB |
2796 | abort(); |
2797 | } | |
2798 | process_pending_signals(env); | |
2799 | } | |
2800 | } | |
2801 | #endif /* TARGET_M68K */ | |
2802 | ||
7a3148a9 | 2803 | #ifdef TARGET_ALPHA |
6910b8f6 RH |
2804 | static void do_store_exclusive(CPUAlphaState *env, int reg, int quad) |
2805 | { | |
2806 | target_ulong addr, val, tmp; | |
2807 | target_siginfo_t info; | |
2808 | int ret = 0; | |
2809 | ||
2810 | addr = env->lock_addr; | |
2811 | tmp = env->lock_st_addr; | |
2812 | env->lock_addr = -1; | |
2813 | env->lock_st_addr = 0; | |
2814 | ||
2815 | start_exclusive(); | |
2816 | mmap_lock(); | |
2817 | ||
2818 | if (addr == tmp) { | |
2819 | if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { | |
2820 | goto do_sigsegv; | |
2821 | } | |
2822 | ||
2823 | if (val == env->lock_value) { | |
2824 | tmp = env->ir[reg]; | |
2825 | if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) { | |
2826 | goto do_sigsegv; | |
2827 | } | |
2828 | ret = 1; | |
2829 | } | |
2830 | } | |
2831 | env->ir[reg] = ret; | |
2832 | env->pc += 4; | |
2833 | ||
2834 | mmap_unlock(); | |
2835 | end_exclusive(); | |
2836 | return; | |
2837 | ||
2838 | do_sigsegv: | |
2839 | mmap_unlock(); | |
2840 | end_exclusive(); | |
2841 | ||
2842 | info.si_signo = TARGET_SIGSEGV; | |
2843 | info.si_errno = 0; | |
2844 | info.si_code = TARGET_SEGV_MAPERR; | |
2845 | info._sifields._sigfault._addr = addr; | |
2846 | queue_signal(env, TARGET_SIGSEGV, &info); | |
2847 | } | |
2848 | ||
05390248 | 2849 | void cpu_loop(CPUAlphaState *env) |
7a3148a9 | 2850 | { |
878096ee | 2851 | CPUState *cs = CPU(alpha_env_get_cpu(env)); |
e96efcfc | 2852 | int trapnr; |
c227f099 | 2853 | target_siginfo_t info; |
6049f4f8 | 2854 | abi_long sysret; |
3b46e624 | 2855 | |
7a3148a9 JM |
2856 | while (1) { |
2857 | trapnr = cpu_alpha_exec (env); | |
3b46e624 | 2858 | |
ac316ca4 RH |
2859 | /* All of the traps imply a transition through PALcode, which |
2860 | implies an REI instruction has been executed. Which means | |
2861 | that the intr_flag should be cleared. */ | |
2862 | env->intr_flag = 0; | |
2863 | ||
7a3148a9 JM |
2864 | switch (trapnr) { |
2865 | case EXCP_RESET: | |
2866 | fprintf(stderr, "Reset requested. Exit\n"); | |
2867 | exit(1); | |
2868 | break; | |
2869 | case EXCP_MCHK: | |
2870 | fprintf(stderr, "Machine check exception. Exit\n"); | |
2871 | exit(1); | |
2872 | break; | |
07b6c13b RH |
2873 | case EXCP_SMP_INTERRUPT: |
2874 | case EXCP_CLK_INTERRUPT: | |
2875 | case EXCP_DEV_INTERRUPT: | |
5fafdf24 | 2876 | fprintf(stderr, "External interrupt. Exit\n"); |
7a3148a9 JM |
2877 | exit(1); |
2878 | break; | |
07b6c13b | 2879 | case EXCP_MMFAULT: |
6910b8f6 | 2880 | env->lock_addr = -1; |
6049f4f8 RH |
2881 | info.si_signo = TARGET_SIGSEGV; |
2882 | info.si_errno = 0; | |
129d8aa5 | 2883 | info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID |
0be1d07c | 2884 | ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); |
129d8aa5 | 2885 | info._sifields._sigfault._addr = env->trap_arg0; |
6049f4f8 | 2886 | queue_signal(env, info.si_signo, &info); |
7a3148a9 | 2887 | break; |
7a3148a9 | 2888 | case EXCP_UNALIGN: |
6910b8f6 | 2889 | env->lock_addr = -1; |
6049f4f8 RH |
2890 | info.si_signo = TARGET_SIGBUS; |
2891 | info.si_errno = 0; | |
2892 | info.si_code = TARGET_BUS_ADRALN; | |
129d8aa5 | 2893 | info._sifields._sigfault._addr = env->trap_arg0; |
6049f4f8 | 2894 | queue_signal(env, info.si_signo, &info); |
7a3148a9 JM |
2895 | break; |
2896 | case EXCP_OPCDEC: | |
6049f4f8 | 2897 | do_sigill: |
6910b8f6 | 2898 | env->lock_addr = -1; |
6049f4f8 RH |
2899 | info.si_signo = TARGET_SIGILL; |
2900 | info.si_errno = 0; | |
2901 | info.si_code = TARGET_ILL_ILLOPC; | |
2902 | info._sifields._sigfault._addr = env->pc; | |
2903 | queue_signal(env, info.si_signo, &info); | |
7a3148a9 | 2904 | break; |
07b6c13b RH |
2905 | case EXCP_ARITH: |
2906 | env->lock_addr = -1; | |
2907 | info.si_signo = TARGET_SIGFPE; | |
2908 | info.si_errno = 0; | |
2909 | info.si_code = TARGET_FPE_FLTINV; | |
2910 | info._sifields._sigfault._addr = env->pc; | |
2911 | queue_signal(env, info.si_signo, &info); | |
2912 | break; | |
7a3148a9 | 2913 | case EXCP_FEN: |
6049f4f8 | 2914 | /* No-op. Linux simply re-enables the FPU. */ |
7a3148a9 | 2915 | break; |
07b6c13b | 2916 | case EXCP_CALL_PAL: |
6910b8f6 | 2917 | env->lock_addr = -1; |
07b6c13b | 2918 | switch (env->error_code) { |
6049f4f8 RH |
2919 | case 0x80: |
2920 | /* BPT */ | |
2921 | info.si_signo = TARGET_SIGTRAP; | |
2922 | info.si_errno = 0; | |
2923 | info.si_code = TARGET_TRAP_BRKPT; | |
2924 | info._sifields._sigfault._addr = env->pc; | |
2925 | queue_signal(env, info.si_signo, &info); | |
2926 | break; | |
2927 | case 0x81: | |
2928 | /* BUGCHK */ | |
2929 | info.si_signo = TARGET_SIGTRAP; | |
2930 | info.si_errno = 0; | |
2931 | info.si_code = 0; | |
2932 | info._sifields._sigfault._addr = env->pc; | |
2933 | queue_signal(env, info.si_signo, &info); | |
2934 | break; | |
2935 | case 0x83: | |
2936 | /* CALLSYS */ | |
2937 | trapnr = env->ir[IR_V0]; | |
2938 | sysret = do_syscall(env, trapnr, | |
2939 | env->ir[IR_A0], env->ir[IR_A1], | |
2940 | env->ir[IR_A2], env->ir[IR_A3], | |
5945cfcb PM |
2941 | env->ir[IR_A4], env->ir[IR_A5], |
2942 | 0, 0); | |
a5b3b13b RH |
2943 | if (trapnr == TARGET_NR_sigreturn |
2944 | || trapnr == TARGET_NR_rt_sigreturn) { | |
2945 | break; | |
2946 | } | |
2947 | /* Syscall writes 0 to V0 to bypass error check, similar | |
0e141977 RH |
2948 | to how this is handled internal to Linux kernel. |
2949 | (Ab)use trapnr temporarily as boolean indicating error. */ | |
2950 | trapnr = (env->ir[IR_V0] != 0 && sysret < 0); | |
2951 | env->ir[IR_V0] = (trapnr ? -sysret : sysret); | |
2952 | env->ir[IR_A3] = trapnr; | |
6049f4f8 RH |
2953 | break; |
2954 | case 0x86: | |
2955 | /* IMB */ | |
2956 | /* ??? We can probably elide the code using page_unprotect | |
2957 | that is checking for self-modifying code. Instead we | |
2958 | could simply call tb_flush here. Until we work out the | |
2959 | changes required to turn off the extra write protection, | |
2960 | this can be a no-op. */ | |
2961 | break; | |
2962 | case 0x9E: | |
2963 | /* RDUNIQUE */ | |
2964 | /* Handled in the translator for usermode. */ | |
2965 | abort(); | |
2966 | case 0x9F: | |
2967 | /* WRUNIQUE */ | |
2968 | /* Handled in the translator for usermode. */ | |
2969 | abort(); | |
2970 | case 0xAA: | |
2971 | /* GENTRAP */ | |
2972 | info.si_signo = TARGET_SIGFPE; | |
2973 | switch (env->ir[IR_A0]) { | |
2974 | case TARGET_GEN_INTOVF: | |
2975 | info.si_code = TARGET_FPE_INTOVF; | |
2976 | break; | |
2977 | case TARGET_GEN_INTDIV: | |
2978 | info.si_code = TARGET_FPE_INTDIV; | |
2979 | break; | |
2980 | case TARGET_GEN_FLTOVF: | |
2981 | info.si_code = TARGET_FPE_FLTOVF; | |
2982 | break; | |
2983 | case TARGET_GEN_FLTUND: | |
2984 | info.si_code = TARGET_FPE_FLTUND; | |
2985 | break; | |
2986 | case TARGET_GEN_FLTINV: | |
2987 | info.si_code = TARGET_FPE_FLTINV; | |
2988 | break; | |
2989 | case TARGET_GEN_FLTINE: | |
2990 | info.si_code = TARGET_FPE_FLTRES; | |
2991 | break; | |
2992 | case TARGET_GEN_ROPRAND: | |
2993 | info.si_code = 0; | |
2994 | break; | |
2995 | default: | |
2996 | info.si_signo = TARGET_SIGTRAP; | |
2997 | info.si_code = 0; | |
2998 | break; | |
2999 | } | |
3000 | info.si_errno = 0; | |
3001 | info._sifields._sigfault._addr = env->pc; | |
3002 | queue_signal(env, info.si_signo, &info); | |
3003 | break; | |
3004 | default: | |
3005 | goto do_sigill; | |
3006 | } | |
7a3148a9 | 3007 | break; |
7a3148a9 | 3008 | case EXCP_DEBUG: |
6049f4f8 RH |
3009 | info.si_signo = gdb_handlesig (env, TARGET_SIGTRAP); |
3010 | if (info.si_signo) { | |
6910b8f6 | 3011 | env->lock_addr = -1; |
6049f4f8 RH |
3012 | info.si_errno = 0; |
3013 | info.si_code = TARGET_TRAP_BRKPT; | |
3014 | queue_signal(env, info.si_signo, &info); | |
7a3148a9 JM |
3015 | } |
3016 | break; | |
6910b8f6 RH |
3017 | case EXCP_STL_C: |
3018 | case EXCP_STQ_C: | |
3019 | do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C); | |
3020 | break; | |
d0f20495 RH |
3021 | case EXCP_INTERRUPT: |
3022 | /* Just indicate that signals should be handled asap. */ | |
3023 | break; | |
7a3148a9 JM |
3024 | default: |
3025 | printf ("Unhandled trap: 0x%x\n", trapnr); | |
878096ee | 3026 | cpu_dump_state(cs, stderr, fprintf, 0); |
7a3148a9 JM |
3027 | exit (1); |
3028 | } | |
3029 | process_pending_signals (env); | |
3030 | } | |
3031 | } | |
3032 | #endif /* TARGET_ALPHA */ | |
3033 | ||
a4c075f1 UH |
3034 | #ifdef TARGET_S390X |
3035 | void cpu_loop(CPUS390XState *env) | |
3036 | { | |
878096ee | 3037 | CPUState *cs = CPU(s390_env_get_cpu(env)); |
d5a103cd | 3038 | int trapnr, n, sig; |
a4c075f1 | 3039 | target_siginfo_t info; |
d5a103cd | 3040 | target_ulong addr; |
a4c075f1 UH |
3041 | |
3042 | while (1) { | |
d5a103cd | 3043 | trapnr = cpu_s390x_exec(env); |
a4c075f1 UH |
3044 | switch (trapnr) { |
3045 | case EXCP_INTERRUPT: | |
d5a103cd | 3046 | /* Just indicate that signals should be handled asap. */ |
a4c075f1 | 3047 | break; |
a4c075f1 | 3048 | |
d5a103cd RH |
3049 | case EXCP_SVC: |
3050 | n = env->int_svc_code; | |
3051 | if (!n) { | |
3052 | /* syscalls > 255 */ | |
3053 | n = env->regs[1]; | |
a4c075f1 | 3054 | } |
d5a103cd RH |
3055 | env->psw.addr += env->int_svc_ilen; |
3056 | env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3], | |
3057 | env->regs[4], env->regs[5], | |
3058 | env->regs[6], env->regs[7], 0, 0); | |
a4c075f1 | 3059 | break; |
d5a103cd RH |
3060 | |
3061 | case EXCP_DEBUG: | |
3062 | sig = gdb_handlesig(env, TARGET_SIGTRAP); | |
3063 | if (sig) { | |
3064 | n = TARGET_TRAP_BRKPT; | |
3065 | goto do_signal_pc; | |
a4c075f1 UH |
3066 | } |
3067 | break; | |
d5a103cd RH |
3068 | case EXCP_PGM: |
3069 | n = env->int_pgm_code; | |
3070 | switch (n) { | |
3071 | case PGM_OPERATION: | |
3072 | case PGM_PRIVILEGED: | |
3073 | sig = SIGILL; | |
3074 | n = TARGET_ILL_ILLOPC; | |
3075 | goto do_signal_pc; | |
3076 | case PGM_PROTECTION: | |
3077 | case PGM_ADDRESSING: | |
3078 | sig = SIGSEGV; | |
a4c075f1 | 3079 | /* XXX: check env->error_code */ |
d5a103cd RH |
3080 | n = TARGET_SEGV_MAPERR; |
3081 | addr = env->__excp_addr; | |
3082 | goto do_signal; | |
3083 | case PGM_EXECUTE: | |
3084 | case PGM_SPECIFICATION: | |
3085 | case PGM_SPECIAL_OP: | |
3086 | case PGM_OPERAND: | |
3087 | do_sigill_opn: | |
3088 | sig = SIGILL; | |
3089 | n = TARGET_ILL_ILLOPN; | |
3090 | goto do_signal_pc; | |
3091 | ||
3092 | case PGM_FIXPT_OVERFLOW: | |
3093 | sig = SIGFPE; | |
3094 | n = TARGET_FPE_INTOVF; | |
3095 | goto do_signal_pc; | |
3096 | case PGM_FIXPT_DIVIDE: | |
3097 | sig = SIGFPE; | |
3098 | n = TARGET_FPE_INTDIV; | |
3099 | goto do_signal_pc; | |
3100 | ||
3101 | case PGM_DATA: | |
3102 | n = (env->fpc >> 8) & 0xff; | |
3103 | if (n == 0xff) { | |
3104 | /* compare-and-trap */ | |
3105 | goto do_sigill_opn; | |
3106 | } else { | |
3107 | /* An IEEE exception, simulated or otherwise. */ | |
3108 | if (n & 0x80) { | |
3109 | n = TARGET_FPE_FLTINV; | |
3110 | } else if (n & 0x40) { | |
3111 | n = TARGET_FPE_FLTDIV; | |
3112 | } else if (n & 0x20) { | |
3113 | n = TARGET_FPE_FLTOVF; | |
3114 | } else if (n & 0x10) { | |
3115 | n = TARGET_FPE_FLTUND; | |
3116 | } else if (n & 0x08) { | |
3117 | n = TARGET_FPE_FLTRES; | |
3118 | } else { | |
3119 | /* ??? Quantum exception; BFP, DFP error. */ | |
3120 | goto do_sigill_opn; | |
3121 | } | |
3122 | sig = SIGFPE; | |
3123 | goto do_signal_pc; | |
3124 | } | |
3125 | ||
3126 | default: | |
3127 | fprintf(stderr, "Unhandled program exception: %#x\n", n); | |
878096ee | 3128 | cpu_dump_state(cs, stderr, fprintf, 0); |
d5a103cd | 3129 | exit(1); |
a4c075f1 UH |
3130 | } |
3131 | break; | |
d5a103cd RH |
3132 | |
3133 | do_signal_pc: | |
3134 | addr = env->psw.addr; | |
3135 | do_signal: | |
3136 | info.si_signo = sig; | |
3137 | info.si_errno = 0; | |
3138 | info.si_code = n; | |
3139 | info._sifields._sigfault._addr = addr; | |
3140 | queue_signal(env, info.si_signo, &info); | |
a4c075f1 | 3141 | break; |
d5a103cd | 3142 | |
a4c075f1 | 3143 | default: |
d5a103cd | 3144 | fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr); |
878096ee | 3145 | cpu_dump_state(cs, stderr, fprintf, 0); |
d5a103cd | 3146 | exit(1); |
a4c075f1 UH |
3147 | } |
3148 | process_pending_signals (env); | |
3149 | } | |
3150 | } | |
3151 | ||
3152 | #endif /* TARGET_S390X */ | |
3153 | ||
a2247f8e | 3154 | THREAD CPUState *thread_cpu; |
59faf6d6 | 3155 | |
edf8e2af MW |
3156 | void task_settid(TaskState *ts) |
3157 | { | |
3158 | if (ts->ts_tid == 0) { | |
2f7bb878 | 3159 | #ifdef CONFIG_USE_NPTL |
edf8e2af MW |
3160 | ts->ts_tid = (pid_t)syscall(SYS_gettid); |
3161 | #else | |
3162 | /* when no threads are used, tid becomes pid */ | |
3163 | ts->ts_tid = getpid(); | |
3164 | #endif | |
3165 | } | |
3166 | } | |
3167 | ||
3168 | void stop_all_tasks(void) | |
3169 | { | |
3170 | /* | |
3171 | * We trust that when using NPTL, start_exclusive() | |
3172 | * handles thread stopping correctly. | |
3173 | */ | |
3174 | start_exclusive(); | |
3175 | } | |
3176 | ||
c3a92833 | 3177 | /* Assumes contents are already zeroed. */ |
624f7979 PB |
3178 | void init_task_state(TaskState *ts) |
3179 | { | |
3180 | int i; | |
3181 | ||
624f7979 PB |
3182 | ts->used = 1; |
3183 | ts->first_free = ts->sigqueue_table; | |
3184 | for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) { | |
3185 | ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1]; | |
3186 | } | |
3187 | ts->sigqueue_table[i].next = NULL; | |
3188 | } | |
fc9c5412 JS |
3189 | |
3190 | static void handle_arg_help(const char *arg) | |
3191 | { | |
3192 | usage(); | |
3193 | } | |
3194 | ||
3195 | static void handle_arg_log(const char *arg) | |
3196 | { | |
3197 | int mask; | |
fc9c5412 | 3198 | |
4fde1eba | 3199 | mask = qemu_str_to_log_mask(arg); |
fc9c5412 | 3200 | if (!mask) { |
59a6fa6e | 3201 | qemu_print_log_usage(stdout); |
fc9c5412 JS |
3202 | exit(1); |
3203 | } | |
24537a01 | 3204 | qemu_set_log(mask); |
fc9c5412 JS |
3205 | } |
3206 | ||
50171d42 CWR |
3207 | static void handle_arg_log_filename(const char *arg) |
3208 | { | |
9a7e5424 | 3209 | qemu_set_log_filename(arg); |
50171d42 CWR |
3210 | } |
3211 | ||
fc9c5412 JS |
3212 | static void handle_arg_set_env(const char *arg) |
3213 | { | |
3214 | char *r, *p, *token; | |
3215 | r = p = strdup(arg); | |
3216 | while ((token = strsep(&p, ",")) != NULL) { | |
3217 | if (envlist_setenv(envlist, token) != 0) { | |
3218 | usage(); | |
3219 | } | |
3220 | } | |
3221 | free(r); | |
3222 | } | |
3223 | ||
3224 | static void handle_arg_unset_env(const char *arg) | |
3225 | { | |
3226 | char *r, *p, *token; | |
3227 | r = p = strdup(arg); | |
3228 | while ((token = strsep(&p, ",")) != NULL) { | |
3229 | if (envlist_unsetenv(envlist, token) != 0) { | |
3230 | usage(); | |
3231 | } | |
3232 | } | |
3233 | free(r); | |
3234 | } | |
3235 | ||
3236 | static void handle_arg_argv0(const char *arg) | |
3237 | { | |
3238 | argv0 = strdup(arg); | |
3239 | } | |
3240 | ||
3241 | static void handle_arg_stack_size(const char *arg) | |
3242 | { | |
3243 | char *p; | |
3244 | guest_stack_size = strtoul(arg, &p, 0); | |
3245 | if (guest_stack_size == 0) { | |
3246 | usage(); | |
3247 | } | |
3248 | ||
3249 | if (*p == 'M') { | |
3250 | guest_stack_size *= 1024 * 1024; | |
3251 | } else if (*p == 'k' || *p == 'K') { | |
3252 | guest_stack_size *= 1024; | |
3253 | } | |
3254 | } | |
3255 | ||
3256 | static void handle_arg_ld_prefix(const char *arg) | |
3257 | { | |
3258 | interp_prefix = strdup(arg); | |
3259 | } | |
3260 | ||
3261 | static void handle_arg_pagesize(const char *arg) | |
3262 | { | |
3263 | qemu_host_page_size = atoi(arg); | |
3264 | if (qemu_host_page_size == 0 || | |
3265 | (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) { | |
3266 | fprintf(stderr, "page size must be a power of two\n"); | |
3267 | exit(1); | |
3268 | } | |
3269 | } | |
3270 | ||
3271 | static void handle_arg_gdb(const char *arg) | |
3272 | { | |
3273 | gdbstub_port = atoi(arg); | |
3274 | } | |
3275 | ||
3276 | static void handle_arg_uname(const char *arg) | |
3277 | { | |
3278 | qemu_uname_release = strdup(arg); | |
3279 | } | |
3280 | ||
3281 | static void handle_arg_cpu(const char *arg) | |
3282 | { | |
3283 | cpu_model = strdup(arg); | |
c8057f95 | 3284 | if (cpu_model == NULL || is_help_option(cpu_model)) { |
fc9c5412 | 3285 | /* XXX: implement xxx_cpu_list for targets that still miss it */ |
e916cbf8 PM |
3286 | #if defined(cpu_list) |
3287 | cpu_list(stdout, &fprintf); | |
fc9c5412 JS |
3288 | #endif |
3289 | exit(1); | |
3290 | } | |
3291 | } | |
3292 | ||
3293 | #if defined(CONFIG_USE_GUEST_BASE) | |
3294 | static void handle_arg_guest_base(const char *arg) | |
3295 | { | |
3296 | guest_base = strtol(arg, NULL, 0); | |
3297 | have_guest_base = 1; | |
3298 | } | |
3299 | ||
3300 | static void handle_arg_reserved_va(const char *arg) | |
3301 | { | |
3302 | char *p; | |
3303 | int shift = 0; | |
3304 | reserved_va = strtoul(arg, &p, 0); | |
3305 | switch (*p) { | |
3306 | case 'k': | |
3307 | case 'K': | |
3308 | shift = 10; | |
3309 | break; | |
3310 | case 'M': | |
3311 | shift = 20; | |
3312 | break; | |
3313 | case 'G': | |
3314 | shift = 30; | |
3315 | break; | |
3316 | } | |
3317 | if (shift) { | |
3318 | unsigned long unshifted = reserved_va; | |
3319 | p++; | |
3320 | reserved_va <<= shift; | |
3321 | if (((reserved_va >> shift) != unshifted) | |
3322 | #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS | |
3323 | || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) | |
3324 | #endif | |
3325 | ) { | |
3326 | fprintf(stderr, "Reserved virtual address too big\n"); | |
3327 | exit(1); | |
3328 | } | |
3329 | } | |
3330 | if (*p) { | |
3331 | fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p); | |
3332 | exit(1); | |
3333 | } | |
3334 | } | |
3335 | #endif | |
3336 | ||
3337 | static void handle_arg_singlestep(const char *arg) | |
3338 | { | |
3339 | singlestep = 1; | |
3340 | } | |
3341 | ||
3342 | static void handle_arg_strace(const char *arg) | |
3343 | { | |
3344 | do_strace = 1; | |
3345 | } | |
3346 | ||
3347 | static void handle_arg_version(const char *arg) | |
3348 | { | |
2e59915d | 3349 | printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION |
fc9c5412 | 3350 | ", Copyright (c) 2003-2008 Fabrice Bellard\n"); |
1386d4c0 | 3351 | exit(0); |
fc9c5412 JS |
3352 | } |
3353 | ||
3354 | struct qemu_argument { | |
3355 | const char *argv; | |
3356 | const char *env; | |
3357 | bool has_arg; | |
3358 | void (*handle_opt)(const char *arg); | |
3359 | const char *example; | |
3360 | const char *help; | |
3361 | }; | |
3362 | ||
42644cee | 3363 | static const struct qemu_argument arg_table[] = { |
fc9c5412 JS |
3364 | {"h", "", false, handle_arg_help, |
3365 | "", "print this help"}, | |
3366 | {"g", "QEMU_GDB", true, handle_arg_gdb, | |
3367 | "port", "wait gdb connection to 'port'"}, | |
3368 | {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix, | |
3369 | "path", "set the elf interpreter prefix to 'path'"}, | |
3370 | {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size, | |
3371 | "size", "set the stack size to 'size' bytes"}, | |
3372 | {"cpu", "QEMU_CPU", true, handle_arg_cpu, | |
c8057f95 | 3373 | "model", "select CPU (-cpu help for list)"}, |
fc9c5412 JS |
3374 | {"E", "QEMU_SET_ENV", true, handle_arg_set_env, |
3375 | "var=value", "sets targets environment variable (see below)"}, | |
3376 | {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env, | |
3377 | "var", "unsets targets environment variable (see below)"}, | |
3378 | {"0", "QEMU_ARGV0", true, handle_arg_argv0, | |
3379 | "argv0", "forces target process argv[0] to be 'argv0'"}, | |
3380 | {"r", "QEMU_UNAME", true, handle_arg_uname, | |
3381 | "uname", "set qemu uname release string to 'uname'"}, | |
3382 | #if defined(CONFIG_USE_GUEST_BASE) | |
3383 | {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base, | |
3384 | "address", "set guest_base address to 'address'"}, | |
3385 | {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va, | |
3386 | "size", "reserve 'size' bytes for guest virtual address space"}, | |
3387 | #endif | |
3388 | {"d", "QEMU_LOG", true, handle_arg_log, | |
989b697d PM |
3389 | "item[,...]", "enable logging of specified items " |
3390 | "(use '-d help' for a list of items)"}, | |
50171d42 | 3391 | {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename, |
989b697d | 3392 | "logfile", "write logs to 'logfile' (default stderr)"}, |
fc9c5412 JS |
3393 | {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize, |
3394 | "pagesize", "set the host page size to 'pagesize'"}, | |
3395 | {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep, | |
3396 | "", "run in singlestep mode"}, | |
3397 | {"strace", "QEMU_STRACE", false, handle_arg_strace, | |
3398 | "", "log system calls"}, | |
3399 | {"version", "QEMU_VERSION", false, handle_arg_version, | |
1386d4c0 | 3400 | "", "display version information and exit"}, |
fc9c5412 JS |
3401 | {NULL, NULL, false, NULL, NULL, NULL} |
3402 | }; | |
3403 | ||
3404 | static void usage(void) | |
3405 | { | |
42644cee | 3406 | const struct qemu_argument *arginfo; |
fc9c5412 JS |
3407 | int maxarglen; |
3408 | int maxenvlen; | |
3409 | ||
2e59915d PB |
3410 | printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n" |
3411 | "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n" | |
fc9c5412 JS |
3412 | "\n" |
3413 | "Options and associated environment variables:\n" | |
3414 | "\n"); | |
3415 | ||
63ec54d7 PM |
3416 | /* Calculate column widths. We must always have at least enough space |
3417 | * for the column header. | |
3418 | */ | |
3419 | maxarglen = strlen("Argument"); | |
3420 | maxenvlen = strlen("Env-variable"); | |
fc9c5412 JS |
3421 | |
3422 | for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { | |
63ec54d7 PM |
3423 | int arglen = strlen(arginfo->argv); |
3424 | if (arginfo->has_arg) { | |
3425 | arglen += strlen(arginfo->example) + 1; | |
3426 | } | |
fc9c5412 JS |
3427 | if (strlen(arginfo->env) > maxenvlen) { |
3428 | maxenvlen = strlen(arginfo->env); | |
3429 | } | |
63ec54d7 PM |
3430 | if (arglen > maxarglen) { |
3431 | maxarglen = arglen; | |
fc9c5412 JS |
3432 | } |
3433 | } | |
3434 | ||
63ec54d7 PM |
3435 | printf("%-*s %-*s Description\n", maxarglen+1, "Argument", |
3436 | maxenvlen, "Env-variable"); | |
fc9c5412 JS |
3437 | |
3438 | for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { | |
3439 | if (arginfo->has_arg) { | |
3440 | printf("-%s %-*s %-*s %s\n", arginfo->argv, | |
63ec54d7 PM |
3441 | (int)(maxarglen - strlen(arginfo->argv) - 1), |
3442 | arginfo->example, maxenvlen, arginfo->env, arginfo->help); | |
fc9c5412 | 3443 | } else { |
63ec54d7 | 3444 | printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv, |
fc9c5412 JS |
3445 | maxenvlen, arginfo->env, |
3446 | arginfo->help); | |
3447 | } | |
3448 | } | |
3449 | ||
3450 | printf("\n" | |
3451 | "Defaults:\n" | |
3452 | "QEMU_LD_PREFIX = %s\n" | |
989b697d | 3453 | "QEMU_STACK_SIZE = %ld byte\n", |
fc9c5412 | 3454 | interp_prefix, |
989b697d | 3455 | guest_stack_size); |
fc9c5412 JS |
3456 | |
3457 | printf("\n" | |
3458 | "You can use -E and -U options or the QEMU_SET_ENV and\n" | |
3459 | "QEMU_UNSET_ENV environment variables to set and unset\n" | |
3460 | "environment variables for the target process.\n" | |
3461 | "It is possible to provide several variables by separating them\n" | |
3462 | "by commas in getsubopt(3) style. Additionally it is possible to\n" | |
3463 | "provide the -E and -U options multiple times.\n" | |
3464 | "The following lines are equivalent:\n" | |
3465 | " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n" | |
3466 | " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n" | |
3467 | " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n" | |
3468 | "Note that if you provide several changes to a single variable\n" | |
3469 | "the last change will stay in effect.\n"); | |
3470 | ||
3471 | exit(1); | |
3472 | } | |
3473 | ||
3474 | static int parse_args(int argc, char **argv) | |
3475 | { | |
3476 | const char *r; | |
3477 | int optind; | |
42644cee | 3478 | const struct qemu_argument *arginfo; |
fc9c5412 JS |
3479 | |
3480 | for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { | |
3481 | if (arginfo->env == NULL) { | |
3482 | continue; | |
3483 | } | |
3484 | ||
3485 | r = getenv(arginfo->env); | |
3486 | if (r != NULL) { | |
3487 | arginfo->handle_opt(r); | |
3488 | } | |
3489 | } | |
3490 | ||
3491 | optind = 1; | |
3492 | for (;;) { | |
3493 | if (optind >= argc) { | |
3494 | break; | |
3495 | } | |
3496 | r = argv[optind]; | |
3497 | if (r[0] != '-') { | |
3498 | break; | |
3499 | } | |
3500 | optind++; | |
3501 | r++; | |
3502 | if (!strcmp(r, "-")) { | |
3503 | break; | |
3504 | } | |
3505 | ||
3506 | for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { | |
3507 | if (!strcmp(r, arginfo->argv)) { | |
fc9c5412 | 3508 | if (arginfo->has_arg) { |
1386d4c0 PM |
3509 | if (optind >= argc) { |
3510 | usage(); | |
3511 | } | |
3512 | arginfo->handle_opt(argv[optind]); | |
fc9c5412 | 3513 | optind++; |
1386d4c0 PM |
3514 | } else { |
3515 | arginfo->handle_opt(NULL); | |
fc9c5412 | 3516 | } |
fc9c5412 JS |
3517 | break; |
3518 | } | |
3519 | } | |
3520 | ||
3521 | /* no option matched the current argv */ | |
3522 | if (arginfo->handle_opt == NULL) { | |
3523 | usage(); | |
3524 | } | |
3525 | } | |
3526 | ||
3527 | if (optind >= argc) { | |
3528 | usage(); | |
3529 | } | |
3530 | ||
3531 | filename = argv[optind]; | |
3532 | exec_path = argv[optind]; | |
3533 | ||
3534 | return optind; | |
3535 | } | |
3536 | ||
902b3d5c | 3537 | int main(int argc, char **argv, char **envp) |
31e31b8a | 3538 | { |
01ffc75b | 3539 | struct target_pt_regs regs1, *regs = ®s1; |
31e31b8a | 3540 | struct image_info info1, *info = &info1; |
edf8e2af | 3541 | struct linux_binprm bprm; |
48e15fc2 | 3542 | TaskState *ts; |
9349b4f9 | 3543 | CPUArchState *env; |
586314f2 | 3544 | int optind; |
04a6dfeb | 3545 | char **target_environ, **wrk; |
7d8cec95 AJ |
3546 | char **target_argv; |
3547 | int target_argc; | |
7d8cec95 | 3548 | int i; |
fd4d81dd | 3549 | int ret; |
b12b6a18 | 3550 | |
ce008c1f AF |
3551 | module_call_init(MODULE_INIT_QOM); |
3552 | ||
902b3d5c | 3553 | qemu_cache_utils_init(envp); |
3554 | ||
04a6dfeb AJ |
3555 | if ((envlist = envlist_create()) == NULL) { |
3556 | (void) fprintf(stderr, "Unable to allocate envlist\n"); | |
3557 | exit(1); | |
3558 | } | |
3559 | ||
3560 | /* add current environment into the list */ | |
3561 | for (wrk = environ; *wrk != NULL; wrk++) { | |
3562 | (void) envlist_setenv(envlist, *wrk); | |
3563 | } | |
3564 | ||
703e0e89 RH |
3565 | /* Read the stack limit from the kernel. If it's "unlimited", |
3566 | then we can do little else besides use the default. */ | |
3567 | { | |
3568 | struct rlimit lim; | |
3569 | if (getrlimit(RLIMIT_STACK, &lim) == 0 | |
81bbe906 TY |
3570 | && lim.rlim_cur != RLIM_INFINITY |
3571 | && lim.rlim_cur == (target_long)lim.rlim_cur) { | |
703e0e89 RH |
3572 | guest_stack_size = lim.rlim_cur; |
3573 | } | |
3574 | } | |
3575 | ||
b1f9be31 | 3576 | cpu_model = NULL; |
b5ec5ce0 | 3577 | #if defined(cpudef_setup) |
3578 | cpudef_setup(); /* parse cpu definitions in target config file (TBD) */ | |
3579 | #endif | |
3580 | ||
fc9c5412 | 3581 | optind = parse_args(argc, argv); |
586314f2 | 3582 | |
31e31b8a | 3583 | /* Zero out regs */ |
01ffc75b | 3584 | memset(regs, 0, sizeof(struct target_pt_regs)); |
31e31b8a FB |
3585 | |
3586 | /* Zero out image_info */ | |
3587 | memset(info, 0, sizeof(struct image_info)); | |
3588 | ||
edf8e2af MW |
3589 | memset(&bprm, 0, sizeof (bprm)); |
3590 | ||
74cd30b8 FB |
3591 | /* Scan interp_prefix dir for replacement files. */ |
3592 | init_paths(interp_prefix); | |
3593 | ||
46027c07 | 3594 | if (cpu_model == NULL) { |
aaed909a | 3595 | #if defined(TARGET_I386) |
46027c07 FB |
3596 | #ifdef TARGET_X86_64 |
3597 | cpu_model = "qemu64"; | |
3598 | #else | |
3599 | cpu_model = "qemu32"; | |
3600 | #endif | |
aaed909a | 3601 | #elif defined(TARGET_ARM) |
088ab16c | 3602 | cpu_model = "any"; |
d2fbca94 GX |
3603 | #elif defined(TARGET_UNICORE32) |
3604 | cpu_model = "any"; | |
aaed909a FB |
3605 | #elif defined(TARGET_M68K) |
3606 | cpu_model = "any"; | |
3607 | #elif defined(TARGET_SPARC) | |
3608 | #ifdef TARGET_SPARC64 | |
3609 | cpu_model = "TI UltraSparc II"; | |
3610 | #else | |
3611 | cpu_model = "Fujitsu MB86904"; | |
46027c07 | 3612 | #endif |
aaed909a FB |
3613 | #elif defined(TARGET_MIPS) |
3614 | #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) | |
3615 | cpu_model = "20Kc"; | |
3616 | #else | |
3617 | cpu_model = "24Kf"; | |
3618 | #endif | |
d962783e JL |
3619 | #elif defined TARGET_OPENRISC |
3620 | cpu_model = "or1200"; | |
aaed909a | 3621 | #elif defined(TARGET_PPC) |
7ded4f52 | 3622 | #ifdef TARGET_PPC64 |
f7177937 | 3623 | cpu_model = "970fx"; |
7ded4f52 | 3624 | #else |
aaed909a | 3625 | cpu_model = "750"; |
7ded4f52 | 3626 | #endif |
aaed909a FB |
3627 | #else |
3628 | cpu_model = "any"; | |
3629 | #endif | |
3630 | } | |
d5ab9713 JK |
3631 | tcg_exec_init(0); |
3632 | cpu_exec_init_all(); | |
83fb7adf FB |
3633 | /* NOTE: we need to init the CPU at this stage to get |
3634 | qemu_host_page_size */ | |
aaed909a FB |
3635 | env = cpu_init(cpu_model); |
3636 | if (!env) { | |
3637 | fprintf(stderr, "Unable to find CPU definition\n"); | |
3638 | exit(1); | |
3639 | } | |
77868120 | 3640 | #if defined(TARGET_SPARC) || defined(TARGET_PPC) |
ff18b762 | 3641 | cpu_reset(ENV_GET_CPU(env)); |
b55a37c9 BS |
3642 | #endif |
3643 | ||
a2247f8e | 3644 | thread_cpu = ENV_GET_CPU(env); |
3b46e624 | 3645 | |
b6741956 FB |
3646 | if (getenv("QEMU_STRACE")) { |
3647 | do_strace = 1; | |
b92c47c1 TS |
3648 | } |
3649 | ||
04a6dfeb AJ |
3650 | target_environ = envlist_to_environ(envlist, NULL); |
3651 | envlist_free(envlist); | |
b12b6a18 | 3652 | |
379f6698 PB |
3653 | #if defined(CONFIG_USE_GUEST_BASE) |
3654 | /* | |
3655 | * Now that page sizes are configured in cpu_init() we can do | |
3656 | * proper page alignment for guest_base. | |
3657 | */ | |
3658 | guest_base = HOST_PAGE_ALIGN(guest_base); | |
68a1c816 | 3659 | |
806d1021 MI |
3660 | if (reserved_va || have_guest_base) { |
3661 | guest_base = init_guest_space(guest_base, reserved_va, 0, | |
3662 | have_guest_base); | |
3663 | if (guest_base == (unsigned long)-1) { | |
097b8cb8 PM |
3664 | fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address " |
3665 | "space for use as guest address space (check your virtual " | |
3666 | "memory ulimit setting or reserve less using -R option)\n", | |
3667 | reserved_va); | |
68a1c816 PB |
3668 | exit(1); |
3669 | } | |
97cc7560 | 3670 | |
806d1021 MI |
3671 | if (reserved_va) { |
3672 | mmap_next_start = reserved_va; | |
97cc7560 DDAG |
3673 | } |
3674 | } | |
14f24e14 | 3675 | #endif /* CONFIG_USE_GUEST_BASE */ |
379f6698 PB |
3676 | |
3677 | /* | |
3678 | * Read in mmap_min_addr kernel parameter. This value is used | |
3679 | * When loading the ELF image to determine whether guest_base | |
14f24e14 | 3680 | * is needed. It is also used in mmap_find_vma. |
379f6698 | 3681 | */ |
14f24e14 | 3682 | { |
379f6698 PB |
3683 | FILE *fp; |
3684 | ||
3685 | if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) { | |
3686 | unsigned long tmp; | |
3687 | if (fscanf(fp, "%lu", &tmp) == 1) { | |
3688 | mmap_min_addr = tmp; | |
3689 | qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr); | |
3690 | } | |
3691 | fclose(fp); | |
3692 | } | |
3693 | } | |
379f6698 | 3694 | |
7d8cec95 AJ |
3695 | /* |
3696 | * Prepare copy of argv vector for target. | |
3697 | */ | |
3698 | target_argc = argc - optind; | |
3699 | target_argv = calloc(target_argc + 1, sizeof (char *)); | |
3700 | if (target_argv == NULL) { | |
3701 | (void) fprintf(stderr, "Unable to allocate memory for target_argv\n"); | |
3702 | exit(1); | |
3703 | } | |
3704 | ||
3705 | /* | |
3706 | * If argv0 is specified (using '-0' switch) we replace | |
3707 | * argv[0] pointer with the given one. | |
3708 | */ | |
3709 | i = 0; | |
3710 | if (argv0 != NULL) { | |
3711 | target_argv[i++] = strdup(argv0); | |
3712 | } | |
3713 | for (; i < target_argc; i++) { | |
3714 | target_argv[i] = strdup(argv[optind + i]); | |
3715 | } | |
3716 | target_argv[target_argc] = NULL; | |
3717 | ||
7267c094 | 3718 | ts = g_malloc0 (sizeof(TaskState)); |
edf8e2af MW |
3719 | init_task_state(ts); |
3720 | /* build Task State */ | |
3721 | ts->info = info; | |
3722 | ts->bprm = &bprm; | |
3723 | env->opaque = ts; | |
3724 | task_settid(ts); | |
3725 | ||
fd4d81dd AP |
3726 | ret = loader_exec(filename, target_argv, target_environ, regs, |
3727 | info, &bprm); | |
3728 | if (ret != 0) { | |
885c1d10 | 3729 | printf("Error while loading %s: %s\n", filename, strerror(-ret)); |
b12b6a18 TS |
3730 | _exit(1); |
3731 | } | |
3732 | ||
3733 | for (wrk = target_environ; *wrk; wrk++) { | |
3734 | free(*wrk); | |
31e31b8a | 3735 | } |
3b46e624 | 3736 | |
b12b6a18 TS |
3737 | free(target_environ); |
3738 | ||
2e77eac6 | 3739 | if (qemu_log_enabled()) { |
379f6698 PB |
3740 | #if defined(CONFIG_USE_GUEST_BASE) |
3741 | qemu_log("guest_base 0x%lx\n", guest_base); | |
3742 | #endif | |
2e77eac6 BS |
3743 | log_page_dump(); |
3744 | ||
3745 | qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk); | |
3746 | qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code); | |
3747 | qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n", | |
3748 | info->start_code); | |
3749 | qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n", | |
3750 | info->start_data); | |
3751 | qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data); | |
3752 | qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n", | |
3753 | info->start_stack); | |
3754 | qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk); | |
3755 | qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry); | |
3756 | } | |
31e31b8a | 3757 | |
53a5960a | 3758 | target_set_brk(info->brk); |
31e31b8a | 3759 | syscall_init(); |
66fb9763 | 3760 | signal_init(); |
31e31b8a | 3761 | |
9002ec79 RH |
3762 | #if defined(CONFIG_USE_GUEST_BASE) |
3763 | /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay | |
3764 | generating the prologue until now so that the prologue can take | |
3765 | the real value of GUEST_BASE into account. */ | |
3766 | tcg_prologue_init(&tcg_ctx); | |
3767 | #endif | |
3768 | ||
b346ff46 | 3769 | #if defined(TARGET_I386) |
2e255c6b FB |
3770 | cpu_x86_set_cpl(env, 3); |
3771 | ||
3802ce26 | 3772 | env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; |
1bde465e | 3773 | env->hflags |= HF_PE_MASK; |
0514ef2f | 3774 | if (env->features[FEAT_1_EDX] & CPUID_SSE) { |
1bde465e FB |
3775 | env->cr[4] |= CR4_OSFXSR_MASK; |
3776 | env->hflags |= HF_OSFXSR_MASK; | |
3777 | } | |
d2fd1af7 | 3778 | #ifndef TARGET_ABI32 |
4dbc422b | 3779 | /* enable 64 bit mode if possible */ |
0514ef2f | 3780 | if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) { |
4dbc422b FB |
3781 | fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n"); |
3782 | exit(1); | |
3783 | } | |
d2fd1af7 | 3784 | env->cr[4] |= CR4_PAE_MASK; |
4dbc422b | 3785 | env->efer |= MSR_EFER_LMA | MSR_EFER_LME; |
d2fd1af7 FB |
3786 | env->hflags |= HF_LMA_MASK; |
3787 | #endif | |
1bde465e | 3788 | |
415e561f FB |
3789 | /* flags setup : we activate the IRQs by default as in user mode */ |
3790 | env->eflags |= IF_MASK; | |
3b46e624 | 3791 | |
6dbad63e | 3792 | /* linux register setup */ |
d2fd1af7 | 3793 | #ifndef TARGET_ABI32 |
84409ddb JM |
3794 | env->regs[R_EAX] = regs->rax; |
3795 | env->regs[R_EBX] = regs->rbx; | |
3796 | env->regs[R_ECX] = regs->rcx; | |
3797 | env->regs[R_EDX] = regs->rdx; | |
3798 | env->regs[R_ESI] = regs->rsi; | |
3799 | env->regs[R_EDI] = regs->rdi; | |
3800 | env->regs[R_EBP] = regs->rbp; | |
3801 | env->regs[R_ESP] = regs->rsp; | |
3802 | env->eip = regs->rip; | |
3803 | #else | |
0ecfa993 FB |
3804 | env->regs[R_EAX] = regs->eax; |
3805 | env->regs[R_EBX] = regs->ebx; | |
3806 | env->regs[R_ECX] = regs->ecx; | |
3807 | env->regs[R_EDX] = regs->edx; | |
3808 | env->regs[R_ESI] = regs->esi; | |
3809 | env->regs[R_EDI] = regs->edi; | |
3810 | env->regs[R_EBP] = regs->ebp; | |
3811 | env->regs[R_ESP] = regs->esp; | |
dab2ed99 | 3812 | env->eip = regs->eip; |
84409ddb | 3813 | #endif |
31e31b8a | 3814 | |
f4beb510 | 3815 | /* linux interrupt setup */ |
e441570f AZ |
3816 | #ifndef TARGET_ABI32 |
3817 | env->idt.limit = 511; | |
3818 | #else | |
3819 | env->idt.limit = 255; | |
3820 | #endif | |
3821 | env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1), | |
3822 | PROT_READ|PROT_WRITE, | |
3823 | MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); | |
3824 | idt_table = g2h(env->idt.base); | |
f4beb510 FB |
3825 | set_idt(0, 0); |
3826 | set_idt(1, 0); | |
3827 | set_idt(2, 0); | |
3828 | set_idt(3, 3); | |
3829 | set_idt(4, 3); | |
ec95da6c | 3830 | set_idt(5, 0); |
f4beb510 FB |
3831 | set_idt(6, 0); |
3832 | set_idt(7, 0); | |
3833 | set_idt(8, 0); | |
3834 | set_idt(9, 0); | |
3835 | set_idt(10, 0); | |
3836 | set_idt(11, 0); | |
3837 | set_idt(12, 0); | |
3838 | set_idt(13, 0); | |
3839 | set_idt(14, 0); | |
3840 | set_idt(15, 0); | |
3841 | set_idt(16, 0); | |
3842 | set_idt(17, 0); | |
3843 | set_idt(18, 0); | |
3844 | set_idt(19, 0); | |
3845 | set_idt(0x80, 3); | |
3846 | ||
6dbad63e | 3847 | /* linux segment setup */ |
8d18e893 FB |
3848 | { |
3849 | uint64_t *gdt_table; | |
e441570f AZ |
3850 | env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES, |
3851 | PROT_READ|PROT_WRITE, | |
3852 | MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); | |
8d18e893 | 3853 | env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; |
e441570f | 3854 | gdt_table = g2h(env->gdt.base); |
d2fd1af7 | 3855 | #ifdef TARGET_ABI32 |
8d18e893 FB |
3856 | write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, |
3857 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | | |
3858 | (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); | |
d2fd1af7 FB |
3859 | #else |
3860 | /* 64 bit code segment */ | |
3861 | write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, | |
3862 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | | |
3863 | DESC_L_MASK | | |
3864 | (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); | |
3865 | #endif | |
8d18e893 FB |
3866 | write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff, |
3867 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | | |
3868 | (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT)); | |
3869 | } | |
6dbad63e | 3870 | cpu_x86_load_seg(env, R_CS, __USER_CS); |
d2fd1af7 FB |
3871 | cpu_x86_load_seg(env, R_SS, __USER_DS); |
3872 | #ifdef TARGET_ABI32 | |
6dbad63e FB |
3873 | cpu_x86_load_seg(env, R_DS, __USER_DS); |
3874 | cpu_x86_load_seg(env, R_ES, __USER_DS); | |
6dbad63e FB |
3875 | cpu_x86_load_seg(env, R_FS, __USER_DS); |
3876 | cpu_x86_load_seg(env, R_GS, __USER_DS); | |
d6eb40f6 TS |
3877 | /* This hack makes Wine work... */ |
3878 | env->segs[R_FS].selector = 0; | |
d2fd1af7 FB |
3879 | #else |
3880 | cpu_x86_load_seg(env, R_DS, 0); | |
3881 | cpu_x86_load_seg(env, R_ES, 0); | |
3882 | cpu_x86_load_seg(env, R_FS, 0); | |
3883 | cpu_x86_load_seg(env, R_GS, 0); | |
3884 | #endif | |
b346ff46 FB |
3885 | #elif defined(TARGET_ARM) |
3886 | { | |
3887 | int i; | |
b5ff1b31 | 3888 | cpsr_write(env, regs->uregs[16], 0xffffffff); |
b346ff46 FB |
3889 | for(i = 0; i < 16; i++) { |
3890 | env->regs[i] = regs->uregs[i]; | |
3891 | } | |
d8fd2954 PB |
3892 | /* Enable BE8. */ |
3893 | if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4 | |
3894 | && (info->elf_flags & EF_ARM_BE8)) { | |
3895 | env->bswap_code = 1; | |
3896 | } | |
b346ff46 | 3897 | } |
d2fbca94 GX |
3898 | #elif defined(TARGET_UNICORE32) |
3899 | { | |
3900 | int i; | |
3901 | cpu_asr_write(env, regs->uregs[32], 0xffffffff); | |
3902 | for (i = 0; i < 32; i++) { | |
3903 | env->regs[i] = regs->uregs[i]; | |
3904 | } | |
3905 | } | |
93ac68bc | 3906 | #elif defined(TARGET_SPARC) |
060366c5 FB |
3907 | { |
3908 | int i; | |
3909 | env->pc = regs->pc; | |
3910 | env->npc = regs->npc; | |
3911 | env->y = regs->y; | |
3912 | for(i = 0; i < 8; i++) | |
3913 | env->gregs[i] = regs->u_regs[i]; | |
3914 | for(i = 0; i < 8; i++) | |
3915 | env->regwptr[i] = regs->u_regs[i + 8]; | |
3916 | } | |
67867308 FB |
3917 | #elif defined(TARGET_PPC) |
3918 | { | |
3919 | int i; | |
3fc6c082 | 3920 | |
0411a972 JM |
3921 | #if defined(TARGET_PPC64) |
3922 | #if defined(TARGET_ABI32) | |
3923 | env->msr &= ~((target_ulong)1 << MSR_SF); | |
e85e7c6e | 3924 | #else |
0411a972 JM |
3925 | env->msr |= (target_ulong)1 << MSR_SF; |
3926 | #endif | |
84409ddb | 3927 | #endif |
67867308 FB |
3928 | env->nip = regs->nip; |
3929 | for(i = 0; i < 32; i++) { | |
3930 | env->gpr[i] = regs->gpr[i]; | |
3931 | } | |
3932 | } | |
e6e5906b PB |
3933 | #elif defined(TARGET_M68K) |
3934 | { | |
e6e5906b PB |
3935 | env->pc = regs->pc; |
3936 | env->dregs[0] = regs->d0; | |
3937 | env->dregs[1] = regs->d1; | |
3938 | env->dregs[2] = regs->d2; | |
3939 | env->dregs[3] = regs->d3; | |
3940 | env->dregs[4] = regs->d4; | |
3941 | env->dregs[5] = regs->d5; | |
3942 | env->dregs[6] = regs->d6; | |
3943 | env->dregs[7] = regs->d7; | |
3944 | env->aregs[0] = regs->a0; | |
3945 | env->aregs[1] = regs->a1; | |
3946 | env->aregs[2] = regs->a2; | |
3947 | env->aregs[3] = regs->a3; | |
3948 | env->aregs[4] = regs->a4; | |
3949 | env->aregs[5] = regs->a5; | |
3950 | env->aregs[6] = regs->a6; | |
3951 | env->aregs[7] = regs->usp; | |
3952 | env->sr = regs->sr; | |
3953 | ts->sim_syscalls = 1; | |
3954 | } | |
b779e29e EI |
3955 | #elif defined(TARGET_MICROBLAZE) |
3956 | { | |
3957 | env->regs[0] = regs->r0; | |
3958 | env->regs[1] = regs->r1; | |
3959 | env->regs[2] = regs->r2; | |
3960 | env->regs[3] = regs->r3; | |
3961 | env->regs[4] = regs->r4; | |
3962 | env->regs[5] = regs->r5; | |
3963 | env->regs[6] = regs->r6; | |
3964 | env->regs[7] = regs->r7; | |
3965 | env->regs[8] = regs->r8; | |
3966 | env->regs[9] = regs->r9; | |
3967 | env->regs[10] = regs->r10; | |
3968 | env->regs[11] = regs->r11; | |
3969 | env->regs[12] = regs->r12; | |
3970 | env->regs[13] = regs->r13; | |
3971 | env->regs[14] = regs->r14; | |
3972 | env->regs[15] = regs->r15; | |
3973 | env->regs[16] = regs->r16; | |
3974 | env->regs[17] = regs->r17; | |
3975 | env->regs[18] = regs->r18; | |
3976 | env->regs[19] = regs->r19; | |
3977 | env->regs[20] = regs->r20; | |
3978 | env->regs[21] = regs->r21; | |
3979 | env->regs[22] = regs->r22; | |
3980 | env->regs[23] = regs->r23; | |
3981 | env->regs[24] = regs->r24; | |
3982 | env->regs[25] = regs->r25; | |
3983 | env->regs[26] = regs->r26; | |
3984 | env->regs[27] = regs->r27; | |
3985 | env->regs[28] = regs->r28; | |
3986 | env->regs[29] = regs->r29; | |
3987 | env->regs[30] = regs->r30; | |
3988 | env->regs[31] = regs->r31; | |
3989 | env->sregs[SR_PC] = regs->pc; | |
3990 | } | |
048f6b4d FB |
3991 | #elif defined(TARGET_MIPS) |
3992 | { | |
3993 | int i; | |
3994 | ||
3995 | for(i = 0; i < 32; i++) { | |
b5dc7732 | 3996 | env->active_tc.gpr[i] = regs->regs[i]; |
048f6b4d | 3997 | } |
0fddbbf2 NF |
3998 | env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1; |
3999 | if (regs->cp0_epc & 1) { | |
4000 | env->hflags |= MIPS_HFLAG_M16; | |
4001 | } | |
048f6b4d | 4002 | } |
d962783e JL |
4003 | #elif defined(TARGET_OPENRISC) |
4004 | { | |
4005 | int i; | |
4006 | ||
4007 | for (i = 0; i < 32; i++) { | |
4008 | env->gpr[i] = regs->gpr[i]; | |
4009 | } | |
4010 | ||
4011 | env->sr = regs->sr; | |
4012 | env->pc = regs->pc; | |
4013 | } | |
fdf9b3e8 FB |
4014 | #elif defined(TARGET_SH4) |
4015 | { | |
4016 | int i; | |
4017 | ||
4018 | for(i = 0; i < 16; i++) { | |
4019 | env->gregs[i] = regs->regs[i]; | |
4020 | } | |
4021 | env->pc = regs->pc; | |
4022 | } | |
7a3148a9 JM |
4023 | #elif defined(TARGET_ALPHA) |
4024 | { | |
4025 | int i; | |
4026 | ||
4027 | for(i = 0; i < 28; i++) { | |
992f48a0 | 4028 | env->ir[i] = ((abi_ulong *)regs)[i]; |
7a3148a9 | 4029 | } |
dad081ee | 4030 | env->ir[IR_SP] = regs->usp; |
7a3148a9 | 4031 | env->pc = regs->pc; |
7a3148a9 | 4032 | } |
48733d19 TS |
4033 | #elif defined(TARGET_CRIS) |
4034 | { | |
4035 | env->regs[0] = regs->r0; | |
4036 | env->regs[1] = regs->r1; | |
4037 | env->regs[2] = regs->r2; | |
4038 | env->regs[3] = regs->r3; | |
4039 | env->regs[4] = regs->r4; | |
4040 | env->regs[5] = regs->r5; | |
4041 | env->regs[6] = regs->r6; | |
4042 | env->regs[7] = regs->r7; | |
4043 | env->regs[8] = regs->r8; | |
4044 | env->regs[9] = regs->r9; | |
4045 | env->regs[10] = regs->r10; | |
4046 | env->regs[11] = regs->r11; | |
4047 | env->regs[12] = regs->r12; | |
4048 | env->regs[13] = regs->r13; | |
4049 | env->regs[14] = info->start_stack; | |
4050 | env->regs[15] = regs->acr; | |
4051 | env->pc = regs->erp; | |
4052 | } | |
a4c075f1 UH |
4053 | #elif defined(TARGET_S390X) |
4054 | { | |
4055 | int i; | |
4056 | for (i = 0; i < 16; i++) { | |
4057 | env->regs[i] = regs->gprs[i]; | |
4058 | } | |
4059 | env->psw.mask = regs->psw.mask; | |
4060 | env->psw.addr = regs->psw.addr; | |
4061 | } | |
b346ff46 FB |
4062 | #else |
4063 | #error unsupported target CPU | |
4064 | #endif | |
31e31b8a | 4065 | |
d2fbca94 | 4066 | #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32) |
a87295e8 PB |
4067 | ts->stack_base = info->start_stack; |
4068 | ts->heap_base = info->brk; | |
4069 | /* This will be filled in on the first SYS_HEAPINFO call. */ | |
4070 | ts->heap_limit = 0; | |
4071 | #endif | |
4072 | ||
74c33bed | 4073 | if (gdbstub_port) { |
ff7a981a PM |
4074 | if (gdbserver_start(gdbstub_port) < 0) { |
4075 | fprintf(stderr, "qemu: could not open gdbserver on port %d\n", | |
4076 | gdbstub_port); | |
4077 | exit(1); | |
4078 | } | |
1fddef4b FB |
4079 | gdb_handlesig(env, 0); |
4080 | } | |
1b6b029e FB |
4081 | cpu_loop(env); |
4082 | /* never exits */ | |
31e31b8a FB |
4083 | return 0; |
4084 | } |