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target-arm: A64: Implement unprivileged load/store
[mirror_qemu.git] / linux-user / main.c
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31e31b8a 1/*
93ac68bc 2 * qemu user main
5fafdf24 3 *
68d0f70e 4 * Copyright (c) 2003-2008 Fabrice Bellard
31e31b8a
FB		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
8167ee88 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31e31b8a
FB		 18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <stdarg.h>
04369ff2 22#include <string.h>
31e31b8a 23#include <errno.h>
0ecfa993 24#include <unistd.h>
e441570f 25#include <sys/mman.h>
edf8e2af 26#include <sys/syscall.h>
703e0e89 27#include <sys/resource.h>
31e31b8a 28
3ef693a0 29#include "qemu.h"
ca10f867 30#include "qemu-common.h"
1de7afc9 31#include "qemu/cache-utils.h"
2b41f10e 32#include "cpu.h"
9002ec79 33#include "tcg.h"
1de7afc9
PB		 34#include "qemu/timer.h"
35#include "qemu/envlist.h"
d8fd2954 36#include "elf.h"
04a6dfeb 37
d088d664
AJ		 38char *exec_path;
39
1b530a6d 40int singlestep;
fc9c5412
JS		 41const char *filename;
42const char *argv0;
43int gdbstub_port;
44envlist_t *envlist;
51fb256a 45static const char *cpu_model;
379f6698 46unsigned long mmap_min_addr;
14f24e14 47#if defined(CONFIG_USE_GUEST_BASE)
379f6698
PB		 48unsigned long guest_base;
49int have_guest_base;
288e65b9
AG		 50#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
51/*
52 * When running 32-on-64 we should make sure we can fit all of the possible
53 * guest address space into a contiguous chunk of virtual host memory.
54 *
55 * This way we will never overlap with our own libraries or binaries or stack
56 * or anything else that QEMU maps.
57 */
314992b1
AG		 58# ifdef TARGET_MIPS
59/* MIPS only supports 31 bits of virtual address space for user space */
60unsigned long reserved_va = 0x77000000;
61# else
288e65b9 62unsigned long reserved_va = 0xf7000000;
314992b1 63# endif
288e65b9 64#else
68a1c816 65unsigned long reserved_va;
379f6698 66#endif
288e65b9 67#endif
1b530a6d 68
fc9c5412
JS		 69static void usage(void);
70
7ee2822c 71static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
c5937220 72const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
586314f2 73
9de5e440
FB		 74/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
75 we allocate a bigger stack. Need a better solution, for example
76 by remapping the process stack directly at the right place */
703e0e89 77unsigned long guest_stack_size = 8 * 1024 * 1024UL;
31e31b8a
FB		 78
79void gemu_log(const char *fmt, ...)
80{
81 va_list ap;
82
83 va_start(ap, fmt);
84 vfprintf(stderr, fmt, ap);
85 va_end(ap);
86}
87
8fcd3692 88#if defined(TARGET_I386)
05390248 89int cpu_get_pic_interrupt(CPUX86State *env)
92ccca6a
FB		 90{
91 return -1;
92}
8fcd3692 93#endif
92ccca6a 94
d5975363
PB		 95/***********************************************************/
96/* Helper routines for implementing atomic operations. */
97
98/* To implement exclusive operations we force all cpus to syncronise.
99 We don't require a full sync, only that no cpus are executing guest code.
100 The alternative is to map target atomic ops onto host equivalents,
101 which requires quite a lot of per host/target work. */
c2764719 102static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
d5975363
PB		 103static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
104static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
105static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
106static int pending_cpus;
107
108/* Make sure everything is in a consistent state for calling fork(). */
109void fork_start(void)
110{
5e5f07e0 111 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 112 pthread_mutex_lock(&exclusive_lock);
d032d1b4 113 mmap_fork_start();
d5975363
PB		 114}
115
116void fork_end(int child)
117{
d032d1b4 118 mmap_fork_end(child);
d5975363 119 if (child) {
bdc44640 120 CPUState *cpu, *next_cpu;
d5975363
PB		 121 /* Child processes created by fork() only have a single thread.
122 Discard information about the parent threads. */
bdc44640
AF		 123 CPU_FOREACH_SAFE(cpu, next_cpu) {
124 if (cpu != thread_cpu) {
125 QTAILQ_REMOVE(&cpus, thread_cpu, node);
126 }
127 }
d5975363
PB		 128 pending_cpus = 0;
129 pthread_mutex_init(&exclusive_lock, NULL);
c2764719 130 pthread_mutex_init(&cpu_list_mutex, NULL);
d5975363
PB		 131 pthread_cond_init(&exclusive_cond, NULL);
132 pthread_cond_init(&exclusive_resume, NULL);
5e5f07e0 133 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
a2247f8e 134 gdbserver_fork((CPUArchState *)thread_cpu->env_ptr);
d5975363
PB		 135 } else {
136 pthread_mutex_unlock(&exclusive_lock);
5e5f07e0 137 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 138 }
d5975363
PB		 139}
140
141/* Wait for pending exclusive operations to complete. The exclusive lock
142 must be held. */
143static inline void exclusive_idle(void)
144{
145 while (pending_cpus) {
146 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
147 }
148}
149
150/* Start an exclusive operation.
151 Must only be called from outside cpu_arm_exec. */
152static inline void start_exclusive(void)
153{
0315c31c
AF		 154 CPUState *other_cpu;
155
d5975363
PB		 156 pthread_mutex_lock(&exclusive_lock);
157 exclusive_idle();
158
159 pending_cpus = 1;
160 /* Make all other cpus stop executing. */
bdc44640 161 CPU_FOREACH(other_cpu) {
0315c31c 162 if (other_cpu->running) {
d5975363 163 pending_cpus++;
60a3e17a 164 cpu_exit(other_cpu);
d5975363
PB		 165 }
166 }
167 if (pending_cpus > 1) {
168 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
169 }
170}
171
172/* Finish an exclusive operation. */
173static inline void end_exclusive(void)
174{
175 pending_cpus = 0;
176 pthread_cond_broadcast(&exclusive_resume);
177 pthread_mutex_unlock(&exclusive_lock);
178}
179
180/* Wait for exclusive ops to finish, and begin cpu execution. */
0315c31c 181static inline void cpu_exec_start(CPUState *cpu)
d5975363
PB		 182{
183 pthread_mutex_lock(&exclusive_lock);
184 exclusive_idle();
0315c31c 185 cpu->running = true;
d5975363
PB		 186 pthread_mutex_unlock(&exclusive_lock);
187}
188
189/* Mark cpu as not executing, and release pending exclusive ops. */
0315c31c 190static inline void cpu_exec_end(CPUState *cpu)
d5975363
PB		 191{
192 pthread_mutex_lock(&exclusive_lock);
0315c31c 193 cpu->running = false;
d5975363
PB		 194 if (pending_cpus > 1) {
195 pending_cpus--;
196 if (pending_cpus == 1) {
197 pthread_cond_signal(&exclusive_cond);
198 }
199 }
200 exclusive_idle();
201 pthread_mutex_unlock(&exclusive_lock);
202}
c2764719
PB		 203
204void cpu_list_lock(void)
205{
206 pthread_mutex_lock(&cpu_list_mutex);
207}
208
209void cpu_list_unlock(void)
210{
211 pthread_mutex_unlock(&cpu_list_mutex);
212}
d5975363
PB		 213
214
a541f297
FB		 215#ifdef TARGET_I386
216/***********************************************************/
217/* CPUX86 core interface */
218
05390248 219void cpu_smm_update(CPUX86State *env)
02a1602e
FB		 220{
221}
222
28ab0e2e
FB		 223uint64_t cpu_get_tsc(CPUX86State *env)
224{
225 return cpu_get_real_ticks();
226}
227
5fafdf24 228static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
f4beb510 229 int flags)
6dbad63e 230{
f4beb510 231 unsigned int e1, e2;
53a5960a 232 uint32_t *p;
6dbad63e
FB		 233 e1 = (addr << 16) | (limit & 0xffff);
234 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
f4beb510 235 e2 |= flags;
53a5960a 236 p = ptr;
d538e8f5 237 p[0] = tswap32(e1);
238 p[1] = tswap32(e2);
f4beb510
FB		 239}
240
e441570f 241static uint64_t *idt_table;
eb38c52c 242#ifdef TARGET_X86_64
d2fd1af7
FB		 243static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
244 uint64_t addr, unsigned int sel)
f4beb510 245{
4dbc422b 246 uint32_t *p, e1, e2;
f4beb510
FB		 247 e1 = (addr & 0xffff) | (sel << 16);
248 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
53a5960a 249 p = ptr;
4dbc422b
FB		 250 p[0] = tswap32(e1);
251 p[1] = tswap32(e2);
252 p[2] = tswap32(addr >> 32);
253 p[3] = 0;
6dbad63e 254}
d2fd1af7
FB		 255/* only dpl matters as we do only user space emulation */
256static void set_idt(int n, unsigned int dpl)
257{
258 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
259}
260#else
d2fd1af7
FB		 261static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
262 uint32_t addr, unsigned int sel)
263{
4dbc422b 264 uint32_t *p, e1, e2;
d2fd1af7
FB		 265 e1 = (addr & 0xffff) | (sel << 16);
266 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
267 p = ptr;
4dbc422b
FB		 268 p[0] = tswap32(e1);
269 p[1] = tswap32(e2);
d2fd1af7
FB		 270}
271
f4beb510
FB		 272/* only dpl matters as we do only user space emulation */
273static void set_idt(int n, unsigned int dpl)
274{
275 set_gate(idt_table + n, 0, dpl, 0, 0);
276}
d2fd1af7 277#endif
31e31b8a 278
89e957e7 279void cpu_loop(CPUX86State *env)
1b6b029e 280{
db6b81d4 281 CPUState *cs = CPU(x86_env_get_cpu(env));
bc8a22cc 282 int trapnr;
992f48a0 283 abi_ulong pc;
c227f099 284 target_siginfo_t info;
851e67a1 285
1b6b029e 286 for(;;) {
bc8a22cc 287 trapnr = cpu_x86_exec(env);
bc8a22cc 288 switch(trapnr) {
f4beb510 289 case 0x80:
d2fd1af7 290 /* linux syscall from int $0x80 */
5fafdf24
TS		 291 env->regs[R_EAX] = do_syscall(env,
292 env->regs[R_EAX],
f4beb510
FB		 293 env->regs[R_EBX],
294 env->regs[R_ECX],
295 env->regs[R_EDX],
296 env->regs[R_ESI],
297 env->regs[R_EDI],
5945cfcb
PM		 298 env->regs[R_EBP],
299 0, 0);
f4beb510 300 break;
d2fd1af7
FB		 301#ifndef TARGET_ABI32
302 case EXCP_SYSCALL:
5ba18547 303 /* linux syscall from syscall instruction */
d2fd1af7
FB		 304 env->regs[R_EAX] = do_syscall(env,
305 env->regs[R_EAX],
306 env->regs[R_EDI],
307 env->regs[R_ESI],
308 env->regs[R_EDX],
309 env->regs[10],
310 env->regs[8],
5945cfcb
PM		 311 env->regs[9],
312 0, 0);
d2fd1af7
FB		 313 env->eip = env->exception_next_eip;
314 break;
315#endif
f4beb510
FB		 316 case EXCP0B_NOSEG:
317 case EXCP0C_STACK:
318 info.si_signo = SIGBUS;
319 info.si_errno = 0;
320 info.si_code = TARGET_SI_KERNEL;
321 info._sifields._sigfault._addr = 0;
624f7979 322 queue_signal(env, info.si_signo, &info);
f4beb510 323 break;
1b6b029e 324 case EXCP0D_GPF:
d2fd1af7 325 /* XXX: potential problem if ABI32 */
84409ddb 326#ifndef TARGET_X86_64
851e67a1 327 if (env->eflags & VM_MASK) {
89e957e7 328 handle_vm86_fault(env);
84409ddb
JM		 329 } else
330#endif
331 {
f4beb510
FB		 332 info.si_signo = SIGSEGV;
333 info.si_errno = 0;
334 info.si_code = TARGET_SI_KERNEL;
335 info._sifields._sigfault._addr = 0;
624f7979 336 queue_signal(env, info.si_signo, &info);
1b6b029e
FB		 337 }
338 break;
b689bc57
FB		 339 case EXCP0E_PAGE:
340 info.si_signo = SIGSEGV;
341 info.si_errno = 0;
342 if (!(env->error_code & 1))
343 info.si_code = TARGET_SEGV_MAPERR;
344 else
345 info.si_code = TARGET_SEGV_ACCERR;
970a87a6 346 info._sifields._sigfault._addr = env->cr[2];
624f7979 347 queue_signal(env, info.si_signo, &info);
b689bc57 348 break;
9de5e440 349 case EXCP00_DIVZ:
84409ddb 350#ifndef TARGET_X86_64
bc8a22cc 351 if (env->eflags & VM_MASK) {
447db213 352 handle_vm86_trap(env, trapnr);
84409ddb
JM		 353 } else
354#endif
355 {
bc8a22cc
FB		 356 /* division by zero */
357 info.si_signo = SIGFPE;
358 info.si_errno = 0;
359 info.si_code = TARGET_FPE_INTDIV;
360 info._sifields._sigfault._addr = env->eip;
624f7979 361 queue_signal(env, info.si_signo, &info);
bc8a22cc 362 }
9de5e440 363 break;
01df040b 364 case EXCP01_DB:
447db213 365 case EXCP03_INT3:
84409ddb 366#ifndef TARGET_X86_64
447db213
FB		 367 if (env->eflags & VM_MASK) {
368 handle_vm86_trap(env, trapnr);
84409ddb
JM		 369 } else
370#endif
371 {
447db213
FB		 372 info.si_signo = SIGTRAP;
373 info.si_errno = 0;
01df040b 374 if (trapnr == EXCP01_DB) {
447db213
FB		 375 info.si_code = TARGET_TRAP_BRKPT;
376 info._sifields._sigfault._addr = env->eip;
377 } else {
378 info.si_code = TARGET_SI_KERNEL;
379 info._sifields._sigfault._addr = 0;
380 }
624f7979 381 queue_signal(env, info.si_signo, &info);
447db213
FB		 382 }
383 break;
9de5e440
FB		 384 case EXCP04_INTO:
385 case EXCP05_BOUND:
84409ddb 386#ifndef TARGET_X86_64
bc8a22cc 387 if (env->eflags & VM_MASK) {
447db213 388 handle_vm86_trap(env, trapnr);
84409ddb
JM		 389 } else
390#endif
391 {
bc8a22cc
FB		 392 info.si_signo = SIGSEGV;
393 info.si_errno = 0;
b689bc57 394 info.si_code = TARGET_SI_KERNEL;
bc8a22cc 395 info._sifields._sigfault._addr = 0;
624f7979 396 queue_signal(env, info.si_signo, &info);
bc8a22cc 397 }
9de5e440
FB		 398 break;
399 case EXCP06_ILLOP:
400 info.si_signo = SIGILL;
401 info.si_errno = 0;
402 info.si_code = TARGET_ILL_ILLOPN;
403 info._sifields._sigfault._addr = env->eip;
624f7979 404 queue_signal(env, info.si_signo, &info);
9de5e440
FB		 405 break;
406 case EXCP_INTERRUPT:
407 /* just indicate that signals should be handled asap */
408 break;
1fddef4b
FB		 409 case EXCP_DEBUG:
410 {
411 int sig;
412
db6b81d4 413 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 414 if (sig)
415 {
416 info.si_signo = sig;
417 info.si_errno = 0;
418 info.si_code = TARGET_TRAP_BRKPT;
624f7979 419 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 420 }
421 }
422 break;
1b6b029e 423 default:
970a87a6 424 pc = env->segs[R_CS].base + env->eip;
5fafdf24 425 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
bc8a22cc 426 (long)pc, trapnr);
1b6b029e
FB		 427 abort();
428 }
66fb9763 429 process_pending_signals(env);
1b6b029e
FB		 430 }
431}
b346ff46
FB		 432#endif
433
434#ifdef TARGET_ARM
435
d8fd2954
PB		 436#define get_user_code_u32(x, gaddr, doswap) \
437 ({ abi_long __r = get_user_u32((x), (gaddr)); \
438 if (!__r && (doswap)) { \
439 (x) = bswap32(x); \
440 } \
441 __r; \
442 })
443
444#define get_user_code_u16(x, gaddr, doswap) \
445 ({ abi_long __r = get_user_u16((x), (gaddr)); \
446 if (!__r && (doswap)) { \
447 (x) = bswap16(x); \
448 } \
449 __r; \
450 })
451
1861c454
PM		 452#ifdef TARGET_ABI32
453/* Commpage handling -- there is no commpage for AArch64 */
454
97cc7560
DDAG		 455/*
456 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
457 * Input:
458 * r0 = pointer to oldval
459 * r1 = pointer to newval
460 * r2 = pointer to target value
461 *
462 * Output:
463 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
464 * C set if *ptr was changed, clear if no exchange happened
465 *
466 * Note segv's in kernel helpers are a bit tricky, we can set the
467 * data address sensibly but the PC address is just the entry point.
468 */
469static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
470{
471 uint64_t oldval, newval, val;
472 uint32_t addr, cpsr;
473 target_siginfo_t info;
474
475 /* Based on the 32 bit code in do_kernel_trap */
476
477 /* XXX: This only works between threads, not between processes.
478 It's probably possible to implement this with native host
479 operations. However things like ldrex/strex are much harder so
480 there's not much point trying. */
481 start_exclusive();
482 cpsr = cpsr_read(env);
483 addr = env->regs[2];
484
485 if (get_user_u64(oldval, env->regs[0])) {
486 env->cp15.c6_data = env->regs[0];
487 goto segv;
488 };
489
490 if (get_user_u64(newval, env->regs[1])) {
491 env->cp15.c6_data = env->regs[1];
492 goto segv;
493 };
494
495 if (get_user_u64(val, addr)) {
496 env->cp15.c6_data = addr;
497 goto segv;
498 }
499
500 if (val == oldval) {
501 val = newval;
502
503 if (put_user_u64(val, addr)) {
504 env->cp15.c6_data = addr;
505 goto segv;
506 };
507
508 env->regs[0] = 0;
509 cpsr |= CPSR_C;
510 } else {
511 env->regs[0] = -1;
512 cpsr &= ~CPSR_C;
513 }
514 cpsr_write(env, cpsr, CPSR_C);
515 end_exclusive();
516 return;
517
518segv:
519 end_exclusive();
520 /* We get the PC of the entry address - which is as good as anything,
521 on a real kernel what you get depends on which mode it uses. */
522 info.si_signo = SIGSEGV;
523 info.si_errno = 0;
524 /* XXX: check env->error_code */
525 info.si_code = TARGET_SEGV_MAPERR;
526 info._sifields._sigfault._addr = env->cp15.c6_data;
527 queue_signal(env, info.si_signo, &info);
528
529 end_exclusive();
530}
531
fbb4a2e3
PB		 532/* Handle a jump to the kernel code page. */
533static int
534do_kernel_trap(CPUARMState *env)
535{
536 uint32_t addr;
537 uint32_t cpsr;
538 uint32_t val;
539
540 switch (env->regs[15]) {
541 case 0xffff0fa0: /* __kernel_memory_barrier */
542 /* ??? No-op. Will need to do better for SMP. */
543 break;
544 case 0xffff0fc0: /* __kernel_cmpxchg */
d5975363
PB		 545 /* XXX: This only works between threads, not between processes.
546 It's probably possible to implement this with native host
547 operations. However things like ldrex/strex are much harder so
548 there's not much point trying. */
549 start_exclusive();
fbb4a2e3
PB		 550 cpsr = cpsr_read(env);
551 addr = env->regs[2];
552 /* FIXME: This should SEGV if the access fails. */
553 if (get_user_u32(val, addr))
554 val = ~env->regs[0];
555 if (val == env->regs[0]) {
556 val = env->regs[1];
557 /* FIXME: Check for segfaults. */
558 put_user_u32(val, addr);
559 env->regs[0] = 0;
560 cpsr |= CPSR_C;
561 } else {
562 env->regs[0] = -1;
563 cpsr &= ~CPSR_C;
564 }
565 cpsr_write(env, cpsr, CPSR_C);
d5975363 566 end_exclusive();
fbb4a2e3
PB		 567 break;
568 case 0xffff0fe0: /* __kernel_get_tls */
e4fe830b 569 env->regs[0] = env->cp15.tpidrro_el0;
fbb4a2e3 570 break;
97cc7560
DDAG		 571 case 0xffff0f60: /* __kernel_cmpxchg64 */
572 arm_kernel_cmpxchg64_helper(env);
573 break;
574
fbb4a2e3
PB		 575 default:
576 return 1;
577 }
578 /* Jump back to the caller. */
579 addr = env->regs[14];
580 if (addr & 1) {
581 env->thumb = 1;
582 addr &= ~1;
583 }
584 env->regs[15] = addr;
585
586 return 0;
587}
588
fa2ef212 589/* Store exclusive handling for AArch32 */
426f5abc
PB		 590static int do_strex(CPUARMState *env)
591{
03d05e2d 592 uint64_t val;
426f5abc
PB		 593 int size;
594 int rc = 1;
595 int segv = 0;
596 uint32_t addr;
597 start_exclusive();
03d05e2d 598 if (env->exclusive_addr != env->exclusive_test) {
426f5abc
PB		 599 goto fail;
600 }
03d05e2d
PM		 601 /* We know we're always AArch32 so the address is in uint32_t range
602 * unless it was the -1 exclusive-monitor-lost value (which won't
603 * match exclusive_test above).
604 */
605 assert(extract64(env->exclusive_addr, 32, 32) == 0);
606 addr = env->exclusive_addr;
426f5abc
PB		 607 size = env->exclusive_info & 0xf;
608 switch (size) {
609 case 0:
610 segv = get_user_u8(val, addr);
611 break;
612 case 1:
613 segv = get_user_u16(val, addr);
614 break;
615 case 2:
616 case 3:
617 segv = get_user_u32(val, addr);
618 break;
f7001a3b
AJ		 619 default:
620 abort();
426f5abc
PB		 621 }
622 if (segv) {
623 env->cp15.c6_data = addr;
624 goto done;
625 }
426f5abc 626 if (size == 3) {
03d05e2d
PM		 627 uint32_t valhi;
628 segv = get_user_u32(valhi, addr + 4);
426f5abc
PB		 629 if (segv) {
630 env->cp15.c6_data = addr + 4;
631 goto done;
632 }
03d05e2d 633 val = deposit64(val, 32, 32, valhi);
426f5abc 634 }
03d05e2d
PM		 635 if (val != env->exclusive_val) {
636 goto fail;
637 }
638
426f5abc
PB		 639 val = env->regs[(env->exclusive_info >> 8) & 0xf];
640 switch (size) {
641 case 0:
642 segv = put_user_u8(val, addr);
643 break;
644 case 1:
645 segv = put_user_u16(val, addr);
646 break;
647 case 2:
648 case 3:
649 segv = put_user_u32(val, addr);
650 break;
651 }
652 if (segv) {
653 env->cp15.c6_data = addr;
654 goto done;
655 }
656 if (size == 3) {
657 val = env->regs[(env->exclusive_info >> 12) & 0xf];
2c9adbda 658 segv = put_user_u32(val, addr + 4);
426f5abc
PB		 659 if (segv) {
660 env->cp15.c6_data = addr + 4;
661 goto done;
662 }
663 }
664 rc = 0;
665fail:
725b8a69 666 env->regs[15] += 4;
426f5abc
PB		 667 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
668done:
669 end_exclusive();
670 return segv;
671}
672
b346ff46
FB		 673void cpu_loop(CPUARMState *env)
674{
0315c31c 675 CPUState *cs = CPU(arm_env_get_cpu(env));
b346ff46
FB		 676 int trapnr;
677 unsigned int n, insn;
c227f099 678 target_siginfo_t info;
b5ff1b31 679 uint32_t addr;
3b46e624 680
b346ff46 681 for(;;) {
0315c31c 682 cpu_exec_start(cs);
b346ff46 683 trapnr = cpu_arm_exec(env);
0315c31c 684 cpu_exec_end(cs);
b346ff46
FB		 685 switch(trapnr) {
686 case EXCP_UDEF:
c6981055
FB		 687 {
688 TaskState *ts = env->opaque;
689 uint32_t opcode;
6d9a42be 690 int rc;
c6981055
FB		 691
692 /* we handle the FPU emulation here, as Linux */
693 /* we get the opcode */
2f619698 694 /* FIXME - what to do if get_user() fails? */
d8fd2954 695 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
3b46e624 696
6d9a42be
AJ		 697 rc = EmulateAll(opcode, &ts->fpa, env);
698 if (rc == 0) { /* illegal instruction */
c6981055
FB		 699 info.si_signo = SIGILL;
700 info.si_errno = 0;
701 info.si_code = TARGET_ILL_ILLOPN;
702 info._sifields._sigfault._addr = env->regs[15];
624f7979 703 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 704 } else if (rc < 0) { /* FP exception */
705 int arm_fpe=0;
706
707 /* translate softfloat flags to FPSR flags */
708 if (-rc & float_flag_invalid)
709 arm_fpe |= BIT_IOC;
710 if (-rc & float_flag_divbyzero)
711 arm_fpe |= BIT_DZC;
712 if (-rc & float_flag_overflow)
713 arm_fpe |= BIT_OFC;
714 if (-rc & float_flag_underflow)
715 arm_fpe |= BIT_UFC;
716 if (-rc & float_flag_inexact)
717 arm_fpe |= BIT_IXC;
718
719 FPSR fpsr = ts->fpa.fpsr;
720 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
721
722 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
723 info.si_signo = SIGFPE;
724 info.si_errno = 0;
725
726 /* ordered by priority, least first */
727 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
728 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
729 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
730 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
731 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
732
733 info._sifields._sigfault._addr = env->regs[15];
624f7979 734 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 735 } else {
736 env->regs[15] += 4;
737 }
738
739 /* accumulate unenabled exceptions */
740 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
741 fpsr |= BIT_IXC;
742 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
743 fpsr |= BIT_UFC;
744 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
745 fpsr |= BIT_OFC;
746 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
747 fpsr |= BIT_DZC;
748 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
749 fpsr |= BIT_IOC;
750 ts->fpa.fpsr=fpsr;
751 } else { /* everything OK */
c6981055
FB		 752 /* increment PC */
753 env->regs[15] += 4;
754 }
755 }
b346ff46
FB		 756 break;
757 case EXCP_SWI:
06c949e6 758 case EXCP_BKPT:
b346ff46 759 {
ce4defa0 760 env->eabi = 1;
b346ff46 761 /* system call */
06c949e6
PB		 762 if (trapnr == EXCP_BKPT) {
763 if (env->thumb) {
2f619698 764 /* FIXME - what to do if get_user() fails? */
d8fd2954 765 get_user_code_u16(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 766 n = insn & 0xff;
767 env->regs[15] += 2;
768 } else {
2f619698 769 /* FIXME - what to do if get_user() fails? */
d8fd2954 770 get_user_code_u32(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 771 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
772 env->regs[15] += 4;
773 }
192c7bd9 774 } else {
06c949e6 775 if (env->thumb) {
2f619698 776 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 777 get_user_code_u16(insn, env->regs[15] - 2,
778 env->bswap_code);
06c949e6
PB		 779 n = insn & 0xff;
780 } else {
2f619698 781 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 782 get_user_code_u32(insn, env->regs[15] - 4,
783 env->bswap_code);
06c949e6
PB		 784 n = insn & 0xffffff;
785 }
192c7bd9
FB		 786 }
787
6f1f31c0 788 if (n == ARM_NR_cacheflush) {
dcfd14b3 789 /* nop */
a4f81979
FB		 790 } else if (n == ARM_NR_semihosting
791 || n == ARM_NR_thumb_semihosting) {
792 env->regs[0] = do_arm_semihosting (env);
3a1363ac 793 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
b346ff46 794 /* linux syscall */
ce4defa0 795 if (env->thumb || n == 0) {
192c7bd9
FB		 796 n = env->regs[7];
797 } else {
798 n -= ARM_SYSCALL_BASE;
ce4defa0 799 env->eabi = 0;
192c7bd9 800 }
fbb4a2e3
PB		 801 if ( n > ARM_NR_BASE) {
802 switch (n) {
803 case ARM_NR_cacheflush:
dcfd14b3 804 /* nop */
fbb4a2e3
PB		 805 break;
806 case ARM_NR_set_tls:
807 cpu_set_tls(env, env->regs[0]);
808 env->regs[0] = 0;
809 break;
810 default:
811 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
812 n);
813 env->regs[0] = -TARGET_ENOSYS;
814 break;
815 }
816 } else {
817 env->regs[0] = do_syscall(env,
818 n,
819 env->regs[0],
820 env->regs[1],
821 env->regs[2],
822 env->regs[3],
823 env->regs[4],
5945cfcb
PM		 824 env->regs[5],
825 0, 0);
fbb4a2e3 826 }
b346ff46
FB		 827 } else {
828 goto error;
829 }
830 }
831 break;
43fff238
FB		 832 case EXCP_INTERRUPT:
833 /* just indicate that signals should be handled asap */
834 break;
68016c62 835 case EXCP_PREFETCH_ABORT:
eae473c1 836 addr = env->cp15.c6_insn;
b5ff1b31 837 goto do_segv;
68016c62 838 case EXCP_DATA_ABORT:
eae473c1 839 addr = env->cp15.c6_data;
b5ff1b31 840 do_segv:
68016c62
FB		 841 {
842 info.si_signo = SIGSEGV;
843 info.si_errno = 0;
844 /* XXX: check env->error_code */
845 info.si_code = TARGET_SEGV_MAPERR;
b5ff1b31 846 info._sifields._sigfault._addr = addr;
624f7979 847 queue_signal(env, info.si_signo, &info);
68016c62
FB		 848 }
849 break;
1fddef4b
FB		 850 case EXCP_DEBUG:
851 {
852 int sig;
853
db6b81d4 854 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 855 if (sig)
856 {
857 info.si_signo = sig;
858 info.si_errno = 0;
859 info.si_code = TARGET_TRAP_BRKPT;
624f7979 860 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 861 }
862 }
863 break;
fbb4a2e3
PB		 864 case EXCP_KERNEL_TRAP:
865 if (do_kernel_trap(env))
866 goto error;
867 break;
426f5abc
PB		 868 case EXCP_STREX:
869 if (do_strex(env)) {
870 addr = env->cp15.c6_data;
871 goto do_segv;
872 }
e9273455 873 break;
b346ff46
FB		 874 default:
875 error:
5fafdf24 876 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
b346ff46 877 trapnr);
878096ee 878 cpu_dump_state(cs, stderr, fprintf, 0);
b346ff46
FB		 879 abort();
880 }
881 process_pending_signals(env);
882 }
883}
884
1861c454
PM		 885#else
886
fa2ef212
MM		 887/*
888 * Handle AArch64 store-release exclusive
889 *
890 * rs = gets the status result of store exclusive
891 * rt = is the register that is stored
892 * rt2 = is the second register store (in STP)
893 *
894 */
895static int do_strex_a64(CPUARMState *env)
896{
897 uint64_t val;
898 int size;
899 bool is_pair;
900 int rc = 1;
901 int segv = 0;
902 uint64_t addr;
903 int rs, rt, rt2;
904
905 start_exclusive();
906 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
907 size = extract32(env->exclusive_info, 0, 2);
908 is_pair = extract32(env->exclusive_info, 2, 1);
909 rs = extract32(env->exclusive_info, 4, 5);
910 rt = extract32(env->exclusive_info, 9, 5);
911 rt2 = extract32(env->exclusive_info, 14, 5);
912
913 addr = env->exclusive_addr;
914
915 if (addr != env->exclusive_test) {
916 goto finish;
917 }
918
919 switch (size) {
920 case 0:
921 segv = get_user_u8(val, addr);
922 break;
923 case 1:
924 segv = get_user_u16(val, addr);
925 break;
926 case 2:
927 segv = get_user_u32(val, addr);
928 break;
929 case 3:
930 segv = get_user_u64(val, addr);
931 break;
932 default:
933 abort();
934 }
935 if (segv) {
936 env->cp15.c6_data = addr;
937 goto error;
938 }
939 if (val != env->exclusive_val) {
940 goto finish;
941 }
942 if (is_pair) {
943 if (size == 2) {
944 segv = get_user_u32(val, addr + 4);
945 } else {
946 segv = get_user_u64(val, addr + 8);
947 }
948 if (segv) {
949 env->cp15.c6_data = addr + (size == 2 ? 4 : 8);
950 goto error;
951 }
952 if (val != env->exclusive_high) {
953 goto finish;
954 }
955 }
956 val = env->xregs[rt];
957 switch (size) {
958 case 0:
959 segv = put_user_u8(val, addr);
960 break;
961 case 1:
962 segv = put_user_u16(val, addr);
963 break;
964 case 2:
965 segv = put_user_u32(val, addr);
966 break;
967 case 3:
968 segv = put_user_u64(val, addr);
969 break;
970 }
971 if (segv) {
972 goto error;
973 }
974 if (is_pair) {
975 val = env->xregs[rt2];
976 if (size == 2) {
977 segv = put_user_u32(val, addr + 4);
978 } else {
979 segv = put_user_u64(val, addr + 8);
980 }
981 if (segv) {
982 env->cp15.c6_data = addr + (size == 2 ? 4 : 8);
983 goto error;
984 }
985 }
986 rc = 0;
987finish:
988 env->pc += 4;
989 /* rs == 31 encodes a write to the ZR, thus throwing away
990 * the status return. This is rather silly but valid.
991 */
992 if (rs < 31) {
993 env->xregs[rs] = rc;
994 }
995error:
996 /* instruction faulted, PC does not advance */
997 /* either way a strex releases any exclusive lock we have */
998 env->exclusive_addr = -1;
999 end_exclusive();
1000 return segv;
1001}
1002
1861c454
PM		 1003/* AArch64 main loop */
1004void cpu_loop(CPUARMState *env)
1005{
1006 CPUState *cs = CPU(arm_env_get_cpu(env));
1007 int trapnr, sig;
1008 target_siginfo_t info;
1009 uint32_t addr;
1010
1011 for (;;) {
1012 cpu_exec_start(cs);
1013 trapnr = cpu_arm_exec(env);
1014 cpu_exec_end(cs);
1015
1016 switch (trapnr) {
1017 case EXCP_SWI:
1018 env->xregs[0] = do_syscall(env,
1019 env->xregs[8],
1020 env->xregs[0],
1021 env->xregs[1],
1022 env->xregs[2],
1023 env->xregs[3],
1024 env->xregs[4],
1025 env->xregs[5],
1026 0, 0);
1027 break;
1028 case EXCP_INTERRUPT:
1029 /* just indicate that signals should be handled asap */
1030 break;
1031 case EXCP_UDEF:
1032 info.si_signo = SIGILL;
1033 info.si_errno = 0;
1034 info.si_code = TARGET_ILL_ILLOPN;
1035 info._sifields._sigfault._addr = env->pc;
1036 queue_signal(env, info.si_signo, &info);
1037 break;
1038 case EXCP_PREFETCH_ABORT:
1039 addr = env->cp15.c6_insn;
1040 goto do_segv;
1041 case EXCP_DATA_ABORT:
1042 addr = env->cp15.c6_data;
1043 do_segv:
1044 info.si_signo = SIGSEGV;
1045 info.si_errno = 0;
1046 /* XXX: check env->error_code */
1047 info.si_code = TARGET_SEGV_MAPERR;
1048 info._sifields._sigfault._addr = addr;
1049 queue_signal(env, info.si_signo, &info);
1050 break;
1051 case EXCP_DEBUG:
1052 case EXCP_BKPT:
1053 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1054 if (sig) {
1055 info.si_signo = sig;
1056 info.si_errno = 0;
1057 info.si_code = TARGET_TRAP_BRKPT;
1058 queue_signal(env, info.si_signo, &info);
1059 }
1060 break;
1061 case EXCP_STREX:
fa2ef212 1062 if (do_strex_a64(env)) {
1861c454
PM		 1063 addr = env->cp15.c6_data;
1064 goto do_segv;
1065 }
1066 break;
1067 default:
1068 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
1069 trapnr);
1070 cpu_dump_state(cs, stderr, fprintf, 0);
1071 abort();
1072 }
1073 process_pending_signals(env);
fa2ef212
MM		 1074 /* Exception return on AArch64 always clears the exclusive monitor,
1075 * so any return to running guest code implies this.
1076 * A strex (successful or otherwise) also clears the monitor, so
1077 * we don't need to specialcase EXCP_STREX.
1078 */
1079 env->exclusive_addr = -1;
1861c454
PM		 1080 }
1081}
1082#endif /* ndef TARGET_ABI32 */
1083
b346ff46 1084#endif
1b6b029e 1085
d2fbca94
GX		 1086#ifdef TARGET_UNICORE32
1087
05390248 1088void cpu_loop(CPUUniCore32State *env)
d2fbca94 1089{
0315c31c 1090 CPUState *cs = CPU(uc32_env_get_cpu(env));
d2fbca94
GX		 1091 int trapnr;
1092 unsigned int n, insn;
1093 target_siginfo_t info;
1094
1095 for (;;) {
0315c31c 1096 cpu_exec_start(cs);
d2fbca94 1097 trapnr = uc32_cpu_exec(env);
0315c31c 1098 cpu_exec_end(cs);
d2fbca94
GX		 1099 switch (trapnr) {
1100 case UC32_EXCP_PRIV:
1101 {
1102 /* system call */
1103 get_user_u32(insn, env->regs[31] - 4);
1104 n = insn & 0xffffff;
1105
1106 if (n >= UC32_SYSCALL_BASE) {
1107 /* linux syscall */
1108 n -= UC32_SYSCALL_BASE;
1109 if (n == UC32_SYSCALL_NR_set_tls) {
1110 cpu_set_tls(env, env->regs[0]);
1111 env->regs[0] = 0;
1112 } else {
1113 env->regs[0] = do_syscall(env,
1114 n,
1115 env->regs[0],
1116 env->regs[1],
1117 env->regs[2],
1118 env->regs[3],
1119 env->regs[4],
5945cfcb
PM		 1120 env->regs[5],
1121 0, 0);
d2fbca94
GX		 1122 }
1123 } else {
1124 goto error;
1125 }
1126 }
1127 break;
d48813dd
GX		 1128 case UC32_EXCP_DTRAP:
1129 case UC32_EXCP_ITRAP:
d2fbca94
GX		 1130 info.si_signo = SIGSEGV;
1131 info.si_errno = 0;
1132 /* XXX: check env->error_code */
1133 info.si_code = TARGET_SEGV_MAPERR;
1134 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1135 queue_signal(env, info.si_signo, &info);
1136 break;
1137 case EXCP_INTERRUPT:
1138 /* just indicate that signals should be handled asap */
1139 break;
1140 case EXCP_DEBUG:
1141 {
1142 int sig;
1143
db6b81d4 1144 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d2fbca94
GX		 1145 if (sig) {
1146 info.si_signo = sig;
1147 info.si_errno = 0;
1148 info.si_code = TARGET_TRAP_BRKPT;
1149 queue_signal(env, info.si_signo, &info);
1150 }
1151 }
1152 break;
1153 default:
1154 goto error;
1155 }
1156 process_pending_signals(env);
1157 }
1158
1159error:
1160 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
878096ee 1161 cpu_dump_state(cs, stderr, fprintf, 0);
d2fbca94
GX		 1162 abort();
1163}
1164#endif
1165
93ac68bc 1166#ifdef TARGET_SPARC
ed23fbd9 1167#define SPARC64_STACK_BIAS 2047
93ac68bc 1168
060366c5
FB		 1169//#define DEBUG_WIN
1170
2623cbaf
FB		 1171/* WARNING: dealing with register windows _is_ complicated. More info
1172 can be found at http://www.sics.se/~psm/sparcstack.html */
060366c5
FB		 1173static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1174{
1a14026e 1175 index = (index + cwp * 16) % (16 * env->nwindows);
060366c5
FB		 1176 /* wrap handling : if cwp is on the last window, then we use the
1177 registers 'after' the end */
1a14026e
BS		 1178 if (index < 8 && env->cwp == env->nwindows - 1)
1179 index += 16 * env->nwindows;
060366c5
FB		 1180 return index;
1181}
1182
2623cbaf
FB		 1183/* save the register window 'cwp1' */
1184static inline void save_window_offset(CPUSPARCState *env, int cwp1)
060366c5 1185{
2623cbaf 1186 unsigned int i;
992f48a0 1187 abi_ulong sp_ptr;
3b46e624 1188
53a5960a 1189 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1190#ifdef TARGET_SPARC64
1191 if (sp_ptr & 3)
1192 sp_ptr += SPARC64_STACK_BIAS;
1193#endif
060366c5 1194#if defined(DEBUG_WIN)
2daf0284
BS		 1195 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1196 sp_ptr, cwp1);
060366c5 1197#endif
2623cbaf 1198 for(i = 0; i < 16; i++) {
2f619698
FB		 1199 /* FIXME - what to do if put_user() fails? */
1200 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1201 sp_ptr += sizeof(abi_ulong);
2623cbaf 1202 }
060366c5
FB		 1203}
1204
1205static void save_window(CPUSPARCState *env)
1206{
5ef54116 1207#ifndef TARGET_SPARC64
2623cbaf 1208 unsigned int new_wim;
1a14026e
BS		 1209 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1210 ((1LL << env->nwindows) - 1);
1211 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
2623cbaf 1212 env->wim = new_wim;
5ef54116 1213#else
1a14026e 1214 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
5ef54116
FB		 1215 env->cansave++;
1216 env->canrestore--;
1217#endif
060366c5
FB		 1218}
1219
1220static void restore_window(CPUSPARCState *env)
1221{
eda52953
BS		 1222#ifndef TARGET_SPARC64
1223 unsigned int new_wim;
1224#endif
1225 unsigned int i, cwp1;
992f48a0 1226 abi_ulong sp_ptr;
3b46e624 1227
eda52953 1228#ifndef TARGET_SPARC64
1a14026e
BS		 1229 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1230 ((1LL << env->nwindows) - 1);
eda52953 1231#endif
3b46e624 1232
060366c5 1233 /* restore the invalid window */
1a14026e 1234 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
53a5960a 1235 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1236#ifdef TARGET_SPARC64
1237 if (sp_ptr & 3)
1238 sp_ptr += SPARC64_STACK_BIAS;
1239#endif
060366c5 1240#if defined(DEBUG_WIN)
2daf0284
BS		 1241 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1242 sp_ptr, cwp1);
060366c5 1243#endif
2623cbaf 1244 for(i = 0; i < 16; i++) {
2f619698
FB		 1245 /* FIXME - what to do if get_user() fails? */
1246 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1247 sp_ptr += sizeof(abi_ulong);
2623cbaf 1248 }
5ef54116
FB		 1249#ifdef TARGET_SPARC64
1250 env->canrestore++;
1a14026e
BS		 1251 if (env->cleanwin < env->nwindows - 1)
1252 env->cleanwin++;
5ef54116 1253 env->cansave--;
eda52953
BS		 1254#else
1255 env->wim = new_wim;
5ef54116 1256#endif
060366c5
FB		 1257}
1258
1259static void flush_windows(CPUSPARCState *env)
1260{
1261 int offset, cwp1;
2623cbaf
FB		 1262
1263 offset = 1;
060366c5
FB		 1264 for(;;) {
1265 /* if restore would invoke restore_window(), then we can stop */
1a14026e 1266 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
eda52953 1267#ifndef TARGET_SPARC64
060366c5
FB		 1268 if (env->wim & (1 << cwp1))
1269 break;
eda52953
BS		 1270#else
1271 if (env->canrestore == 0)
1272 break;
1273 env->cansave++;
1274 env->canrestore--;
1275#endif
2623cbaf 1276 save_window_offset(env, cwp1);
060366c5
FB		 1277 offset++;
1278 }
1a14026e 1279 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
eda52953
BS		 1280#ifndef TARGET_SPARC64
1281 /* set wim so that restore will reload the registers */
2623cbaf 1282 env->wim = 1 << cwp1;
eda52953 1283#endif
2623cbaf
FB		 1284#if defined(DEBUG_WIN)
1285 printf("flush_windows: nb=%d\n", offset - 1);
80a9d035 1286#endif
2623cbaf 1287}
060366c5 1288
93ac68bc
FB		 1289void cpu_loop (CPUSPARCState *env)
1290{
878096ee 1291 CPUState *cs = CPU(sparc_env_get_cpu(env));
2cc20260
RH		 1292 int trapnr;
1293 abi_long ret;
c227f099 1294 target_siginfo_t info;
3b46e624 1295
060366c5
FB		 1296 while (1) {
1297 trapnr = cpu_sparc_exec (env);
3b46e624 1298
20132b96
RH		 1299 /* Compute PSR before exposing state. */
1300 if (env->cc_op != CC_OP_FLAGS) {
1301 cpu_get_psr(env);
1302 }
1303
060366c5 1304 switch (trapnr) {
5ef54116 1305#ifndef TARGET_SPARC64
5fafdf24 1306 case 0x88:
060366c5 1307 case 0x90:
5ef54116 1308#else
cb33da57 1309 case 0x110:
5ef54116
FB		 1310 case 0x16d:
1311#endif
060366c5 1312 ret = do_syscall (env, env->gregs[1],
5fafdf24
TS		 1313 env->regwptr[0], env->regwptr[1],
1314 env->regwptr[2], env->regwptr[3],
5945cfcb
PM		 1315 env->regwptr[4], env->regwptr[5],
1316 0, 0);
2cc20260 1317 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
992f48a0 1318#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1319 env->xcc |= PSR_CARRY;
1320#else
060366c5 1321 env->psr |= PSR_CARRY;
27908725 1322#endif
060366c5
FB		 1323 ret = -ret;
1324 } else {
992f48a0 1325#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1326 env->xcc &= ~PSR_CARRY;
1327#else
060366c5 1328 env->psr &= ~PSR_CARRY;
27908725 1329#endif
060366c5
FB		 1330 }
1331 env->regwptr[0] = ret;
1332 /* next instruction */
1333 env->pc = env->npc;
1334 env->npc = env->npc + 4;
1335 break;
1336 case 0x83: /* flush windows */
992f48a0
BS		 1337#ifdef TARGET_ABI32
1338 case 0x103:
1339#endif
2623cbaf 1340 flush_windows(env);
060366c5
FB		 1341 /* next instruction */
1342 env->pc = env->npc;
1343 env->npc = env->npc + 4;
1344 break;
3475187d 1345#ifndef TARGET_SPARC64
060366c5
FB		 1346 case TT_WIN_OVF: /* window overflow */
1347 save_window(env);
1348 break;
1349 case TT_WIN_UNF: /* window underflow */
1350 restore_window(env);
1351 break;
61ff6f58
FB		 1352 case TT_TFAULT:
1353 case TT_DFAULT:
1354 {
59f7182f 1355 info.si_signo = TARGET_SIGSEGV;
61ff6f58
FB		 1356 info.si_errno = 0;
1357 /* XXX: check env->error_code */
1358 info.si_code = TARGET_SEGV_MAPERR;
1359 info._sifields._sigfault._addr = env->mmuregs[4];
624f7979 1360 queue_signal(env, info.si_signo, &info);
61ff6f58
FB		 1361 }
1362 break;
3475187d 1363#else
5ef54116
FB		 1364 case TT_SPILL: /* window overflow */
1365 save_window(env);
1366 break;
1367 case TT_FILL: /* window underflow */
1368 restore_window(env);
1369 break;
7f84a729
BS		 1370 case TT_TFAULT:
1371 case TT_DFAULT:
1372 {
59f7182f 1373 info.si_signo = TARGET_SIGSEGV;
7f84a729
BS		 1374 info.si_errno = 0;
1375 /* XXX: check env->error_code */
1376 info.si_code = TARGET_SEGV_MAPERR;
1377 if (trapnr == TT_DFAULT)
1378 info._sifields._sigfault._addr = env->dmmuregs[4];
1379 else
8194f35a 1380 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
624f7979 1381 queue_signal(env, info.si_signo, &info);
7f84a729
BS		 1382 }
1383 break;
27524dc3 1384#ifndef TARGET_ABI32
5bfb56b2
BS		 1385 case 0x16e:
1386 flush_windows(env);
1387 sparc64_get_context(env);
1388 break;
1389 case 0x16f:
1390 flush_windows(env);
1391 sparc64_set_context(env);
1392 break;
27524dc3 1393#endif
3475187d 1394#endif
48dc41eb
FB		 1395 case EXCP_INTERRUPT:
1396 /* just indicate that signals should be handled asap */
1397 break;
75f22e4e
RH		 1398 case TT_ILL_INSN:
1399 {
1400 info.si_signo = TARGET_SIGILL;
1401 info.si_errno = 0;
1402 info.si_code = TARGET_ILL_ILLOPC;
1403 info._sifields._sigfault._addr = env->pc;
1404 queue_signal(env, info.si_signo, &info);
1405 }
1406 break;
1fddef4b
FB		 1407 case EXCP_DEBUG:
1408 {
1409 int sig;
1410
db6b81d4 1411 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 1412 if (sig)
1413 {
1414 info.si_signo = sig;
1415 info.si_errno = 0;
1416 info.si_code = TARGET_TRAP_BRKPT;
624f7979 1417 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 1418 }
1419 }
1420 break;
060366c5
FB		 1421 default:
1422 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 1423 cpu_dump_state(cs, stderr, fprintf, 0);
060366c5
FB		 1424 exit (1);
1425 }
1426 process_pending_signals (env);
1427 }
93ac68bc
FB		 1428}
1429
1430#endif
1431
67867308 1432#ifdef TARGET_PPC
05390248 1433static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
9fddaa0c
FB		 1434{
1435 /* TO FIX */
1436 return 0;
1437}
3b46e624 1438
05390248 1439uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
9fddaa0c 1440{
e3ea6529 1441 return cpu_ppc_get_tb(env);
9fddaa0c 1442}
3b46e624 1443
05390248 1444uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
9fddaa0c
FB		 1445{
1446 return cpu_ppc_get_tb(env) >> 32;
1447}
3b46e624 1448
05390248 1449uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
9fddaa0c 1450{
b711de95 1451 return cpu_ppc_get_tb(env);
9fddaa0c 1452}
5fafdf24 1453
05390248 1454uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
9fddaa0c 1455{
a062e36c 1456 return cpu_ppc_get_tb(env) >> 32;
9fddaa0c 1457}
76a66253 1458
05390248 1459uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
76a66253
JM		 1460__attribute__ (( alias ("cpu_ppc_load_tbu") ));
1461
05390248 1462uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
9fddaa0c 1463{
76a66253 1464 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
9fddaa0c 1465}
76a66253 1466
a750fc0b 1467/* XXX: to be fixed */
73b01960 1468int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
a750fc0b
JM		 1469{
1470 return -1;
1471}
1472
73b01960 1473int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
a750fc0b
JM		 1474{
1475 return -1;
1476}
1477
001faf32
BS		 1478#define EXCP_DUMP(env, fmt, ...) \
1479do { \
a0762859 1480 CPUState *cs = ENV_GET_CPU(env); \
001faf32 1481 fprintf(stderr, fmt , ## __VA_ARGS__); \
a0762859 1482 cpu_dump_state(cs, stderr, fprintf, 0); \
001faf32 1483 qemu_log(fmt, ## __VA_ARGS__); \
eeacee4d 1484 if (qemu_log_enabled()) { \
a0762859 1485 log_cpu_state(cs, 0); \
eeacee4d 1486 } \
e1833e1f
JM		 1487} while (0)
1488
56f066bb
NF		 1489static int do_store_exclusive(CPUPPCState *env)
1490{
1491 target_ulong addr;
1492 target_ulong page_addr;
1493 target_ulong val;
1494 int flags;
1495 int segv = 0;
1496
1497 addr = env->reserve_ea;
1498 page_addr = addr & TARGET_PAGE_MASK;
1499 start_exclusive();
1500 mmap_lock();
1501 flags = page_get_flags(page_addr);
1502 if ((flags & PAGE_READ) == 0) {
1503 segv = 1;
1504 } else {
1505 int reg = env->reserve_info & 0x1f;
1506 int size = (env->reserve_info >> 5) & 0xf;
1507 int stored = 0;
1508
1509 if (addr == env->reserve_addr) {
1510 switch (size) {
1511 case 1: segv = get_user_u8(val, addr); break;
1512 case 2: segv = get_user_u16(val, addr); break;
1513 case 4: segv = get_user_u32(val, addr); break;
1514#if defined(TARGET_PPC64)
1515 case 8: segv = get_user_u64(val, addr); break;
1516#endif
1517 default: abort();
1518 }
1519 if (!segv && val == env->reserve_val) {
1520 val = env->gpr[reg];
1521 switch (size) {
1522 case 1: segv = put_user_u8(val, addr); break;
1523 case 2: segv = put_user_u16(val, addr); break;
1524 case 4: segv = put_user_u32(val, addr); break;
1525#if defined(TARGET_PPC64)
1526 case 8: segv = put_user_u64(val, addr); break;
1527#endif
1528 default: abort();
1529 }
1530 if (!segv) {
1531 stored = 1;
1532 }
1533 }
1534 }
1535 env->crf[0] = (stored << 1) | xer_so;
1536 env->reserve_addr = (target_ulong)-1;
1537 }
1538 if (!segv) {
1539 env->nip += 4;
1540 }
1541 mmap_unlock();
1542 end_exclusive();
1543 return segv;
1544}
1545
67867308
FB		 1546void cpu_loop(CPUPPCState *env)
1547{
0315c31c 1548 CPUState *cs = CPU(ppc_env_get_cpu(env));
c227f099 1549 target_siginfo_t info;
61190b14 1550 int trapnr;
9e0e2f96 1551 target_ulong ret;
3b46e624 1552
67867308 1553 for(;;) {
0315c31c 1554 cpu_exec_start(cs);
67867308 1555 trapnr = cpu_ppc_exec(env);
0315c31c 1556 cpu_exec_end(cs);
67867308 1557 switch(trapnr) {
e1833e1f
JM		 1558 case POWERPC_EXCP_NONE:
1559 /* Just go on */
67867308 1560 break;
e1833e1f
JM		 1561 case POWERPC_EXCP_CRITICAL: /* Critical input */
1562 cpu_abort(env, "Critical interrupt while in user mode. "
1563 "Aborting\n");
61190b14 1564 break;
e1833e1f
JM		 1565 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1566 cpu_abort(env, "Machine check exception while in user mode. "
1567 "Aborting\n");
1568 break;
1569 case POWERPC_EXCP_DSI: /* Data storage exception */
90e189ec 1570 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
e1833e1f
JM		 1571 env->spr[SPR_DAR]);
1572 /* XXX: check this. Seems bugged */
2be0071f
FB		 1573 switch (env->error_code & 0xFF000000) {
1574 case 0x40000000:
61190b14
FB		 1575 info.si_signo = TARGET_SIGSEGV;
1576 info.si_errno = 0;
1577 info.si_code = TARGET_SEGV_MAPERR;
1578 break;
2be0071f 1579 case 0x04000000:
61190b14
FB		 1580 info.si_signo = TARGET_SIGILL;
1581 info.si_errno = 0;
1582 info.si_code = TARGET_ILL_ILLADR;
1583 break;
2be0071f 1584 case 0x08000000:
61190b14
FB		 1585 info.si_signo = TARGET_SIGSEGV;
1586 info.si_errno = 0;
1587 info.si_code = TARGET_SEGV_ACCERR;
1588 break;
61190b14
FB		 1589 default:
1590 /* Let's send a regular segfault... */
e1833e1f
JM		 1591 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1592 env->error_code);
61190b14
FB		 1593 info.si_signo = TARGET_SIGSEGV;
1594 info.si_errno = 0;
1595 info.si_code = TARGET_SEGV_MAPERR;
1596 break;
1597 }
67867308 1598 info._sifields._sigfault._addr = env->nip;
624f7979 1599 queue_signal(env, info.si_signo, &info);
67867308 1600 break;
e1833e1f 1601 case POWERPC_EXCP_ISI: /* Instruction storage exception */
90e189ec
BS		 1602 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1603 "\n", env->spr[SPR_SRR0]);
e1833e1f 1604 /* XXX: check this */
2be0071f
FB		 1605 switch (env->error_code & 0xFF000000) {
1606 case 0x40000000:
61190b14 1607 info.si_signo = TARGET_SIGSEGV;
67867308 1608 info.si_errno = 0;
61190b14
FB		 1609 info.si_code = TARGET_SEGV_MAPERR;
1610 break;
2be0071f
FB		 1611 case 0x10000000:
1612 case 0x08000000:
61190b14
FB		 1613 info.si_signo = TARGET_SIGSEGV;
1614 info.si_errno = 0;
1615 info.si_code = TARGET_SEGV_ACCERR;
1616 break;
1617 default:
1618 /* Let's send a regular segfault... */
e1833e1f
JM		 1619 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1620 env->error_code);
61190b14
FB		 1621 info.si_signo = TARGET_SIGSEGV;
1622 info.si_errno = 0;
1623 info.si_code = TARGET_SEGV_MAPERR;
1624 break;
1625 }
1626 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1627 queue_signal(env, info.si_signo, &info);
67867308 1628 break;
e1833e1f
JM		 1629 case POWERPC_EXCP_EXTERNAL: /* External input */
1630 cpu_abort(env, "External interrupt while in user mode. "
1631 "Aborting\n");
1632 break;
1633 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1634 EXCP_DUMP(env, "Unaligned memory access\n");
1635 /* XXX: check this */
61190b14 1636 info.si_signo = TARGET_SIGBUS;
67867308 1637 info.si_errno = 0;
61190b14
FB		 1638 info.si_code = TARGET_BUS_ADRALN;
1639 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1640 queue_signal(env, info.si_signo, &info);
67867308 1641 break;
e1833e1f
JM		 1642 case POWERPC_EXCP_PROGRAM: /* Program exception */
1643 /* XXX: check this */
61190b14 1644 switch (env->error_code & ~0xF) {
e1833e1f
JM		 1645 case POWERPC_EXCP_FP:
1646 EXCP_DUMP(env, "Floating point program exception\n");
61190b14
FB		 1647 info.si_signo = TARGET_SIGFPE;
1648 info.si_errno = 0;
1649 switch (env->error_code & 0xF) {
e1833e1f 1650 case POWERPC_EXCP_FP_OX:
61190b14
FB		 1651 info.si_code = TARGET_FPE_FLTOVF;
1652 break;
e1833e1f 1653 case POWERPC_EXCP_FP_UX:
61190b14
FB		 1654 info.si_code = TARGET_FPE_FLTUND;
1655 break;
e1833e1f
JM		 1656 case POWERPC_EXCP_FP_ZX:
1657 case POWERPC_EXCP_FP_VXZDZ:
61190b14
FB		 1658 info.si_code = TARGET_FPE_FLTDIV;
1659 break;
e1833e1f 1660 case POWERPC_EXCP_FP_XX:
61190b14
FB		 1661 info.si_code = TARGET_FPE_FLTRES;
1662 break;
e1833e1f 1663 case POWERPC_EXCP_FP_VXSOFT:
61190b14
FB		 1664 info.si_code = TARGET_FPE_FLTINV;
1665 break;
7c58044c 1666 case POWERPC_EXCP_FP_VXSNAN:
e1833e1f
JM		 1667 case POWERPC_EXCP_FP_VXISI:
1668 case POWERPC_EXCP_FP_VXIDI:
1669 case POWERPC_EXCP_FP_VXIMZ:
1670 case POWERPC_EXCP_FP_VXVC:
1671 case POWERPC_EXCP_FP_VXSQRT:
1672 case POWERPC_EXCP_FP_VXCVI:
61190b14
FB		 1673 info.si_code = TARGET_FPE_FLTSUB;
1674 break;
1675 default:
e1833e1f
JM		 1676 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1677 env->error_code);
1678 break;
61190b14 1679 }
e1833e1f
JM		 1680 break;
1681 case POWERPC_EXCP_INVAL:
1682 EXCP_DUMP(env, "Invalid instruction\n");
61190b14
FB		 1683 info.si_signo = TARGET_SIGILL;
1684 info.si_errno = 0;
1685 switch (env->error_code & 0xF) {
e1833e1f 1686 case POWERPC_EXCP_INVAL_INVAL:
61190b14
FB		 1687 info.si_code = TARGET_ILL_ILLOPC;
1688 break;
e1833e1f 1689 case POWERPC_EXCP_INVAL_LSWX:
a750fc0b 1690 info.si_code = TARGET_ILL_ILLOPN;
61190b14 1691 break;
e1833e1f 1692 case POWERPC_EXCP_INVAL_SPR:
61190b14
FB		 1693 info.si_code = TARGET_ILL_PRVREG;
1694 break;
e1833e1f 1695 case POWERPC_EXCP_INVAL_FP:
61190b14
FB		 1696 info.si_code = TARGET_ILL_COPROC;
1697 break;
1698 default:
e1833e1f
JM		 1699 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1700 env->error_code & 0xF);
61190b14
FB		 1701 info.si_code = TARGET_ILL_ILLADR;
1702 break;
1703 }
1704 break;
e1833e1f
JM		 1705 case POWERPC_EXCP_PRIV:
1706 EXCP_DUMP(env, "Privilege violation\n");
61190b14
FB		 1707 info.si_signo = TARGET_SIGILL;
1708 info.si_errno = 0;
1709 switch (env->error_code & 0xF) {
e1833e1f 1710 case POWERPC_EXCP_PRIV_OPC:
61190b14
FB		 1711 info.si_code = TARGET_ILL_PRVOPC;
1712 break;
e1833e1f 1713 case POWERPC_EXCP_PRIV_REG:
61190b14 1714 info.si_code = TARGET_ILL_PRVREG;
e1833e1f 1715 break;
61190b14 1716 default:
e1833e1f
JM		 1717 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1718 env->error_code & 0xF);
61190b14
FB		 1719 info.si_code = TARGET_ILL_PRVOPC;
1720 break;
1721 }
1722 break;
e1833e1f
JM		 1723 case POWERPC_EXCP_TRAP:
1724 cpu_abort(env, "Tried to call a TRAP\n");
1725 break;
61190b14
FB		 1726 default:
1727 /* Should not happen ! */
e1833e1f
JM		 1728 cpu_abort(env, "Unknown program exception (%02x)\n",
1729 env->error_code);
1730 break;
61190b14
FB		 1731 }
1732 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1733 queue_signal(env, info.si_signo, &info);
67867308 1734 break;
e1833e1f
JM		 1735 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1736 EXCP_DUMP(env, "No floating point allowed\n");
61190b14 1737 info.si_signo = TARGET_SIGILL;
67867308 1738 info.si_errno = 0;
61190b14
FB		 1739 info.si_code = TARGET_ILL_COPROC;
1740 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1741 queue_signal(env, info.si_signo, &info);
67867308 1742 break;
e1833e1f
JM		 1743 case POWERPC_EXCP_SYSCALL: /* System call exception */
1744 cpu_abort(env, "Syscall exception while in user mode. "
1745 "Aborting\n");
61190b14 1746 break;
e1833e1f
JM		 1747 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1748 EXCP_DUMP(env, "No APU instruction allowed\n");
1749 info.si_signo = TARGET_SIGILL;
1750 info.si_errno = 0;
1751 info.si_code = TARGET_ILL_COPROC;
1752 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1753 queue_signal(env, info.si_signo, &info);
61190b14 1754 break;
e1833e1f
JM		 1755 case POWERPC_EXCP_DECR: /* Decrementer exception */
1756 cpu_abort(env, "Decrementer interrupt while in user mode. "
1757 "Aborting\n");
61190b14 1758 break;
e1833e1f
JM		 1759 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1760 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1761 "Aborting\n");
1762 break;
1763 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1764 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1765 "Aborting\n");
1766 break;
1767 case POWERPC_EXCP_DTLB: /* Data TLB error */
1768 cpu_abort(env, "Data TLB exception while in user mode. "
1769 "Aborting\n");
1770 break;
1771 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1772 cpu_abort(env, "Instruction TLB exception while in user mode. "
1773 "Aborting\n");
1774 break;
e1833e1f
JM		 1775 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1776 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1777 info.si_signo = TARGET_SIGILL;
1778 info.si_errno = 0;
1779 info.si_code = TARGET_ILL_COPROC;
1780 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1781 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1782 break;
1783 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1784 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1785 break;
1786 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1787 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1788 break;
1789 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1790 cpu_abort(env, "Performance monitor exception not handled\n");
1791 break;
1792 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1793 cpu_abort(env, "Doorbell interrupt while in user mode. "
1794 "Aborting\n");
1795 break;
1796 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1797 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1798 "Aborting\n");
1799 break;
1800 case POWERPC_EXCP_RESET: /* System reset exception */
1801 cpu_abort(env, "Reset interrupt while in user mode. "
1802 "Aborting\n");
1803 break;
e1833e1f
JM		 1804 case POWERPC_EXCP_DSEG: /* Data segment exception */
1805 cpu_abort(env, "Data segment exception while in user mode. "
1806 "Aborting\n");
1807 break;
1808 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1809 cpu_abort(env, "Instruction segment exception "
1810 "while in user mode. Aborting\n");
1811 break;
e85e7c6e 1812 /* PowerPC 64 with hypervisor mode support */
e1833e1f
JM		 1813 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1814 cpu_abort(env, "Hypervisor decrementer interrupt "
1815 "while in user mode. Aborting\n");
1816 break;
e1833e1f
JM		 1817 case POWERPC_EXCP_TRACE: /* Trace exception */
1818 /* Nothing to do:
1819 * we use this exception to emulate step-by-step execution mode.
1820 */
1821 break;
e85e7c6e 1822 /* PowerPC 64 with hypervisor mode support */
e1833e1f
JM		 1823 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1824 cpu_abort(env, "Hypervisor data storage exception "
1825 "while in user mode. Aborting\n");
1826 break;
1827 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1828 cpu_abort(env, "Hypervisor instruction storage exception "
1829 "while in user mode. Aborting\n");
1830 break;
1831 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1832 cpu_abort(env, "Hypervisor data segment exception "
1833 "while in user mode. Aborting\n");
1834 break;
1835 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1836 cpu_abort(env, "Hypervisor instruction segment exception "
1837 "while in user mode. Aborting\n");
1838 break;
e1833e1f
JM		 1839 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1840 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1841 info.si_signo = TARGET_SIGILL;
1842 info.si_errno = 0;
1843 info.si_code = TARGET_ILL_COPROC;
1844 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1845 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1846 break;
1847 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
b4916d7b 1848 cpu_abort(env, "Programmable interval timer interrupt "
e1833e1f
JM		 1849 "while in user mode. Aborting\n");
1850 break;
1851 case POWERPC_EXCP_IO: /* IO error exception */
1852 cpu_abort(env, "IO error exception while in user mode. "
1853 "Aborting\n");
1854 break;
1855 case POWERPC_EXCP_RUNM: /* Run mode exception */
1856 cpu_abort(env, "Run mode exception while in user mode. "
1857 "Aborting\n");
1858 break;
1859 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1860 cpu_abort(env, "Emulation trap exception not handled\n");
1861 break;
1862 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1863 cpu_abort(env, "Instruction fetch TLB exception "
1864 "while in user-mode. Aborting");
1865 break;
1866 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1867 cpu_abort(env, "Data load TLB exception while in user-mode. "
1868 "Aborting");
1869 break;
1870 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1871 cpu_abort(env, "Data store TLB exception while in user-mode. "
1872 "Aborting");
1873 break;
1874 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1875 cpu_abort(env, "Floating-point assist exception not handled\n");
1876 break;
1877 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1878 cpu_abort(env, "Instruction address breakpoint exception "
1879 "not handled\n");
1880 break;
1881 case POWERPC_EXCP_SMI: /* System management interrupt */
1882 cpu_abort(env, "System management interrupt while in user mode. "
1883 "Aborting\n");
1884 break;
1885 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1886 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1887 "Aborting\n");
1888 break;
1889 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1890 cpu_abort(env, "Performance monitor exception not handled\n");
1891 break;
1892 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1893 cpu_abort(env, "Vector assist exception not handled\n");
1894 break;
1895 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1896 cpu_abort(env, "Soft patch exception not handled\n");
1897 break;
1898 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1899 cpu_abort(env, "Maintenance exception while in user mode. "
1900 "Aborting\n");
1901 break;
1902 case POWERPC_EXCP_STOP: /* stop translation */
1903 /* We did invalidate the instruction cache. Go on */
1904 break;
1905 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1906 /* We just stopped because of a branch. Go on */
1907 break;
1908 case POWERPC_EXCP_SYSCALL_USER:
1909 /* system call in user-mode emulation */
1910 /* WARNING:
1911 * PPC ABI uses overflow flag in cr0 to signal an error
1912 * in syscalls.
1913 */
e1833e1f
JM		 1914 env->crf[0] &= ~0x1;
1915 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1916 env->gpr[5], env->gpr[6], env->gpr[7],
5945cfcb 1917 env->gpr[8], 0, 0);
9e0e2f96 1918 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
bcd4933a
NF		 1919 /* Returning from a successful sigreturn syscall.
1920 Avoid corrupting register state. */
1921 break;
1922 }
9e0e2f96 1923 if (ret > (target_ulong)(-515)) {
e1833e1f
JM		 1924 env->crf[0] |= 0x1;
1925 ret = -ret;
61190b14 1926 }
e1833e1f 1927 env->gpr[3] = ret;
e1833e1f 1928 break;
56f066bb
NF		 1929 case POWERPC_EXCP_STCX:
1930 if (do_store_exclusive(env)) {
1931 info.si_signo = TARGET_SIGSEGV;
1932 info.si_errno = 0;
1933 info.si_code = TARGET_SEGV_MAPERR;
1934 info._sifields._sigfault._addr = env->nip;
1935 queue_signal(env, info.si_signo, &info);
1936 }
1937 break;
71f75756
AJ		 1938 case EXCP_DEBUG:
1939 {
1940 int sig;
1941
db6b81d4 1942 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
71f75756
AJ		 1943 if (sig) {
1944 info.si_signo = sig;
1945 info.si_errno = 0;
1946 info.si_code = TARGET_TRAP_BRKPT;
1947 queue_signal(env, info.si_signo, &info);
1948 }
1949 }
1950 break;
56ba31ff
JM		 1951 case EXCP_INTERRUPT:
1952 /* just indicate that signals should be handled asap */
1953 break;
e1833e1f
JM		 1954 default:
1955 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1956 break;
67867308
FB		 1957 }
1958 process_pending_signals(env);
1959 }
1960}
1961#endif
1962
048f6b4d
FB		 1963#ifdef TARGET_MIPS
1964
ff4f7382
RH		 1965# ifdef TARGET_ABI_MIPSO32
1966# define MIPS_SYS(name, args) args,
048f6b4d 1967static const uint8_t mips_syscall_args[] = {
29fb0f25 1968 MIPS_SYS(sys_syscall , 8) /* 4000 */
048f6b4d
FB		 1969 MIPS_SYS(sys_exit , 1)
1970 MIPS_SYS(sys_fork , 0)
1971 MIPS_SYS(sys_read , 3)
1972 MIPS_SYS(sys_write , 3)
1973 MIPS_SYS(sys_open , 3) /* 4005 */
1974 MIPS_SYS(sys_close , 1)
1975 MIPS_SYS(sys_waitpid , 3)
1976 MIPS_SYS(sys_creat , 2)
1977 MIPS_SYS(sys_link , 2)
1978 MIPS_SYS(sys_unlink , 1) /* 4010 */
1979 MIPS_SYS(sys_execve , 0)
1980 MIPS_SYS(sys_chdir , 1)
1981 MIPS_SYS(sys_time , 1)
1982 MIPS_SYS(sys_mknod , 3)
1983 MIPS_SYS(sys_chmod , 2) /* 4015 */
1984 MIPS_SYS(sys_lchown , 3)
1985 MIPS_SYS(sys_ni_syscall , 0)
1986 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1987 MIPS_SYS(sys_lseek , 3)
1988 MIPS_SYS(sys_getpid , 0) /* 4020 */
1989 MIPS_SYS(sys_mount , 5)
868e34d7 1990 MIPS_SYS(sys_umount , 1)
048f6b4d
FB		 1991 MIPS_SYS(sys_setuid , 1)
1992 MIPS_SYS(sys_getuid , 0)
1993 MIPS_SYS(sys_stime , 1) /* 4025 */
1994 MIPS_SYS(sys_ptrace , 4)
1995 MIPS_SYS(sys_alarm , 1)
1996 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1997 MIPS_SYS(sys_pause , 0)
1998 MIPS_SYS(sys_utime , 2) /* 4030 */
1999 MIPS_SYS(sys_ni_syscall , 0)
2000 MIPS_SYS(sys_ni_syscall , 0)
2001 MIPS_SYS(sys_access , 2)
2002 MIPS_SYS(sys_nice , 1)
2003 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2004 MIPS_SYS(sys_sync , 0)
2005 MIPS_SYS(sys_kill , 2)
2006 MIPS_SYS(sys_rename , 2)
2007 MIPS_SYS(sys_mkdir , 2)
2008 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2009 MIPS_SYS(sys_dup , 1)
2010 MIPS_SYS(sys_pipe , 0)
2011 MIPS_SYS(sys_times , 1)
2012 MIPS_SYS(sys_ni_syscall , 0)
2013 MIPS_SYS(sys_brk , 1) /* 4045 */
2014 MIPS_SYS(sys_setgid , 1)
2015 MIPS_SYS(sys_getgid , 0)
2016 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2017 MIPS_SYS(sys_geteuid , 0)
2018 MIPS_SYS(sys_getegid , 0) /* 4050 */
2019 MIPS_SYS(sys_acct , 0)
868e34d7 2020 MIPS_SYS(sys_umount2 , 2)
048f6b4d
FB		 2021 MIPS_SYS(sys_ni_syscall , 0)
2022 MIPS_SYS(sys_ioctl , 3)
2023 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2024 MIPS_SYS(sys_ni_syscall , 2)
2025 MIPS_SYS(sys_setpgid , 2)
2026 MIPS_SYS(sys_ni_syscall , 0)
2027 MIPS_SYS(sys_olduname , 1)
2028 MIPS_SYS(sys_umask , 1) /* 4060 */
2029 MIPS_SYS(sys_chroot , 1)
2030 MIPS_SYS(sys_ustat , 2)
2031 MIPS_SYS(sys_dup2 , 2)
2032 MIPS_SYS(sys_getppid , 0)
2033 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2034 MIPS_SYS(sys_setsid , 0)
2035 MIPS_SYS(sys_sigaction , 3)
2036 MIPS_SYS(sys_sgetmask , 0)
2037 MIPS_SYS(sys_ssetmask , 1)
2038 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2039 MIPS_SYS(sys_setregid , 2)
2040 MIPS_SYS(sys_sigsuspend , 0)
2041 MIPS_SYS(sys_sigpending , 1)
2042 MIPS_SYS(sys_sethostname , 2)
2043 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2044 MIPS_SYS(sys_getrlimit , 2)
2045 MIPS_SYS(sys_getrusage , 2)
2046 MIPS_SYS(sys_gettimeofday, 2)
2047 MIPS_SYS(sys_settimeofday, 2)
2048 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2049 MIPS_SYS(sys_setgroups , 2)
2050 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2051 MIPS_SYS(sys_symlink , 2)
2052 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2053 MIPS_SYS(sys_readlink , 3) /* 4085 */
2054 MIPS_SYS(sys_uselib , 1)
2055 MIPS_SYS(sys_swapon , 2)
2056 MIPS_SYS(sys_reboot , 3)
2057 MIPS_SYS(old_readdir , 3)
2058 MIPS_SYS(old_mmap , 6) /* 4090 */
2059 MIPS_SYS(sys_munmap , 2)
2060 MIPS_SYS(sys_truncate , 2)
2061 MIPS_SYS(sys_ftruncate , 2)
2062 MIPS_SYS(sys_fchmod , 2)
2063 MIPS_SYS(sys_fchown , 3) /* 4095 */
2064 MIPS_SYS(sys_getpriority , 2)
2065 MIPS_SYS(sys_setpriority , 3)
2066 MIPS_SYS(sys_ni_syscall , 0)
2067 MIPS_SYS(sys_statfs , 2)
2068 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2069 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2070 MIPS_SYS(sys_socketcall , 2)
2071 MIPS_SYS(sys_syslog , 3)
2072 MIPS_SYS(sys_setitimer , 3)
2073 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2074 MIPS_SYS(sys_newstat , 2)
2075 MIPS_SYS(sys_newlstat , 2)
2076 MIPS_SYS(sys_newfstat , 2)
2077 MIPS_SYS(sys_uname , 1)
2078 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2079 MIPS_SYS(sys_vhangup , 0)
2080 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2081 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2082 MIPS_SYS(sys_wait4 , 4)
2083 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2084 MIPS_SYS(sys_sysinfo , 1)
2085 MIPS_SYS(sys_ipc , 6)
2086 MIPS_SYS(sys_fsync , 1)
2087 MIPS_SYS(sys_sigreturn , 0)
18113962 2088 MIPS_SYS(sys_clone , 6) /* 4120 */
048f6b4d
FB		 2089 MIPS_SYS(sys_setdomainname, 2)
2090 MIPS_SYS(sys_newuname , 1)
2091 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2092 MIPS_SYS(sys_adjtimex , 1)
2093 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2094 MIPS_SYS(sys_sigprocmask , 3)
2095 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2096 MIPS_SYS(sys_init_module , 5)
2097 MIPS_SYS(sys_delete_module, 1)
2098 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2099 MIPS_SYS(sys_quotactl , 0)
2100 MIPS_SYS(sys_getpgid , 1)
2101 MIPS_SYS(sys_fchdir , 1)
2102 MIPS_SYS(sys_bdflush , 2)
2103 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2104 MIPS_SYS(sys_personality , 1)
2105 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2106 MIPS_SYS(sys_setfsuid , 1)
2107 MIPS_SYS(sys_setfsgid , 1)
2108 MIPS_SYS(sys_llseek , 5) /* 4140 */
2109 MIPS_SYS(sys_getdents , 3)
2110 MIPS_SYS(sys_select , 5)
2111 MIPS_SYS(sys_flock , 2)
2112 MIPS_SYS(sys_msync , 3)
2113 MIPS_SYS(sys_readv , 3) /* 4145 */
2114 MIPS_SYS(sys_writev , 3)
2115 MIPS_SYS(sys_cacheflush , 3)
2116 MIPS_SYS(sys_cachectl , 3)
2117 MIPS_SYS(sys_sysmips , 4)
2118 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2119 MIPS_SYS(sys_getsid , 1)
2120 MIPS_SYS(sys_fdatasync , 0)
2121 MIPS_SYS(sys_sysctl , 1)
2122 MIPS_SYS(sys_mlock , 2)
2123 MIPS_SYS(sys_munlock , 2) /* 4155 */
2124 MIPS_SYS(sys_mlockall , 1)
2125 MIPS_SYS(sys_munlockall , 0)
2126 MIPS_SYS(sys_sched_setparam, 2)
2127 MIPS_SYS(sys_sched_getparam, 2)
2128 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2129 MIPS_SYS(sys_sched_getscheduler, 1)
2130 MIPS_SYS(sys_sched_yield , 0)
2131 MIPS_SYS(sys_sched_get_priority_max, 1)
2132 MIPS_SYS(sys_sched_get_priority_min, 1)
2133 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2134 MIPS_SYS(sys_nanosleep, 2)
b0932e06 2135 MIPS_SYS(sys_mremap , 5)
048f6b4d
FB		 2136 MIPS_SYS(sys_accept , 3)
2137 MIPS_SYS(sys_bind , 3)
2138 MIPS_SYS(sys_connect , 3) /* 4170 */
2139 MIPS_SYS(sys_getpeername , 3)
2140 MIPS_SYS(sys_getsockname , 3)
2141 MIPS_SYS(sys_getsockopt , 5)
2142 MIPS_SYS(sys_listen , 2)
2143 MIPS_SYS(sys_recv , 4) /* 4175 */
2144 MIPS_SYS(sys_recvfrom , 6)
2145 MIPS_SYS(sys_recvmsg , 3)
2146 MIPS_SYS(sys_send , 4)
2147 MIPS_SYS(sys_sendmsg , 3)
2148 MIPS_SYS(sys_sendto , 6) /* 4180 */
2149 MIPS_SYS(sys_setsockopt , 5)
2150 MIPS_SYS(sys_shutdown , 2)
2151 MIPS_SYS(sys_socket , 3)
2152 MIPS_SYS(sys_socketpair , 4)
2153 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2154 MIPS_SYS(sys_getresuid , 3)
2155 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2156 MIPS_SYS(sys_poll , 3)
2157 MIPS_SYS(sys_nfsservctl , 3)
2158 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2159 MIPS_SYS(sys_getresgid , 3)
2160 MIPS_SYS(sys_prctl , 5)
2161 MIPS_SYS(sys_rt_sigreturn, 0)
2162 MIPS_SYS(sys_rt_sigaction, 4)
2163 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2164 MIPS_SYS(sys_rt_sigpending, 2)
2165 MIPS_SYS(sys_rt_sigtimedwait, 4)
2166 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2167 MIPS_SYS(sys_rt_sigsuspend, 0)
2168 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2169 MIPS_SYS(sys_pwrite64 , 6)
2170 MIPS_SYS(sys_chown , 3)
2171 MIPS_SYS(sys_getcwd , 2)
2172 MIPS_SYS(sys_capget , 2)
2173 MIPS_SYS(sys_capset , 2) /* 4205 */
053ebb27 2174 MIPS_SYS(sys_sigaltstack , 2)
048f6b4d
FB		 2175 MIPS_SYS(sys_sendfile , 4)
2176 MIPS_SYS(sys_ni_syscall , 0)
2177 MIPS_SYS(sys_ni_syscall , 0)
2178 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2179 MIPS_SYS(sys_truncate64 , 4)
2180 MIPS_SYS(sys_ftruncate64 , 4)
2181 MIPS_SYS(sys_stat64 , 2)
2182 MIPS_SYS(sys_lstat64 , 2)
2183 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2184 MIPS_SYS(sys_pivot_root , 2)
2185 MIPS_SYS(sys_mincore , 3)
2186 MIPS_SYS(sys_madvise , 3)
2187 MIPS_SYS(sys_getdents64 , 3)
2188 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2189 MIPS_SYS(sys_ni_syscall , 0)
2190 MIPS_SYS(sys_gettid , 0)
2191 MIPS_SYS(sys_readahead , 5)
2192 MIPS_SYS(sys_setxattr , 5)
2193 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2194 MIPS_SYS(sys_fsetxattr , 5)
2195 MIPS_SYS(sys_getxattr , 4)
2196 MIPS_SYS(sys_lgetxattr , 4)
2197 MIPS_SYS(sys_fgetxattr , 4)
2198 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2199 MIPS_SYS(sys_llistxattr , 3)
2200 MIPS_SYS(sys_flistxattr , 3)
2201 MIPS_SYS(sys_removexattr , 2)
2202 MIPS_SYS(sys_lremovexattr, 2)
2203 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2204 MIPS_SYS(sys_tkill , 2)
2205 MIPS_SYS(sys_sendfile64 , 5)
43be1343 2206 MIPS_SYS(sys_futex , 6)
048f6b4d
FB		 2207 MIPS_SYS(sys_sched_setaffinity, 3)
2208 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2209 MIPS_SYS(sys_io_setup , 2)
2210 MIPS_SYS(sys_io_destroy , 1)
2211 MIPS_SYS(sys_io_getevents, 5)
2212 MIPS_SYS(sys_io_submit , 3)
2213 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2214 MIPS_SYS(sys_exit_group , 1)
2215 MIPS_SYS(sys_lookup_dcookie, 3)
2216 MIPS_SYS(sys_epoll_create, 1)
2217 MIPS_SYS(sys_epoll_ctl , 4)
2218 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2219 MIPS_SYS(sys_remap_file_pages, 5)
2220 MIPS_SYS(sys_set_tid_address, 1)
2221 MIPS_SYS(sys_restart_syscall, 0)
2222 MIPS_SYS(sys_fadvise64_64, 7)
2223 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2224 MIPS_SYS(sys_fstatfs64 , 2)
2225 MIPS_SYS(sys_timer_create, 3)
2226 MIPS_SYS(sys_timer_settime, 4)
2227 MIPS_SYS(sys_timer_gettime, 2)
2228 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2229 MIPS_SYS(sys_timer_delete, 1)
2230 MIPS_SYS(sys_clock_settime, 2)
2231 MIPS_SYS(sys_clock_gettime, 2)
2232 MIPS_SYS(sys_clock_getres, 2)
2233 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2234 MIPS_SYS(sys_tgkill , 3)
2235 MIPS_SYS(sys_utimes , 2)
2236 MIPS_SYS(sys_mbind , 4)
2237 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2238 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2239 MIPS_SYS(sys_mq_open , 4)
2240 MIPS_SYS(sys_mq_unlink , 1)
2241 MIPS_SYS(sys_mq_timedsend, 5)
2242 MIPS_SYS(sys_mq_timedreceive, 5)
2243 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2244 MIPS_SYS(sys_mq_getsetattr, 3)
2245 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2246 MIPS_SYS(sys_waitid , 4)
2247 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2248 MIPS_SYS(sys_add_key , 5)
388bb21a 2249 MIPS_SYS(sys_request_key, 4)
048f6b4d 2250 MIPS_SYS(sys_keyctl , 5)
6f5b89a0 2251 MIPS_SYS(sys_set_thread_area, 1)
388bb21a
TS		 2252 MIPS_SYS(sys_inotify_init, 0)
2253 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2254 MIPS_SYS(sys_inotify_rm_watch, 2)
2255 MIPS_SYS(sys_migrate_pages, 4)
2256 MIPS_SYS(sys_openat, 4)
2257 MIPS_SYS(sys_mkdirat, 3)
2258 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2259 MIPS_SYS(sys_fchownat, 5)
2260 MIPS_SYS(sys_futimesat, 3)
2261 MIPS_SYS(sys_fstatat64, 4)
2262 MIPS_SYS(sys_unlinkat, 3)
2263 MIPS_SYS(sys_renameat, 4) /* 4295 */
2264 MIPS_SYS(sys_linkat, 5)
2265 MIPS_SYS(sys_symlinkat, 3)
2266 MIPS_SYS(sys_readlinkat, 4)
2267 MIPS_SYS(sys_fchmodat, 3)
2268 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2269 MIPS_SYS(sys_pselect6, 6)
2270 MIPS_SYS(sys_ppoll, 5)
2271 MIPS_SYS(sys_unshare, 1)
b0932e06 2272 MIPS_SYS(sys_splice, 6)
388bb21a
TS		 2273 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2274 MIPS_SYS(sys_tee, 4)
2275 MIPS_SYS(sys_vmsplice, 4)
2276 MIPS_SYS(sys_move_pages, 6)
2277 MIPS_SYS(sys_set_robust_list, 2)
2278 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2279 MIPS_SYS(sys_kexec_load, 4)
2280 MIPS_SYS(sys_getcpu, 3)
2281 MIPS_SYS(sys_epoll_pwait, 6)
2282 MIPS_SYS(sys_ioprio_set, 3)
2283 MIPS_SYS(sys_ioprio_get, 2)
d979e8eb
PM		 2284 MIPS_SYS(sys_utimensat, 4)
2285 MIPS_SYS(sys_signalfd, 3)
2286 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2287 MIPS_SYS(sys_eventfd, 1)
2288 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2289 MIPS_SYS(sys_timerfd_create, 2)
2290 MIPS_SYS(sys_timerfd_gettime, 2)
2291 MIPS_SYS(sys_timerfd_settime, 4)
2292 MIPS_SYS(sys_signalfd4, 4)
2293 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2294 MIPS_SYS(sys_epoll_create1, 1)
2295 MIPS_SYS(sys_dup3, 3)
2296 MIPS_SYS(sys_pipe2, 2)
2297 MIPS_SYS(sys_inotify_init1, 1)
2298 MIPS_SYS(sys_preadv, 6) /* 4330 */
2299 MIPS_SYS(sys_pwritev, 6)
2300 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2301 MIPS_SYS(sys_perf_event_open, 5)
2302 MIPS_SYS(sys_accept4, 4)
2303 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2304 MIPS_SYS(sys_fanotify_init, 2)
2305 MIPS_SYS(sys_fanotify_mark, 6)
2306 MIPS_SYS(sys_prlimit64, 4)
2307 MIPS_SYS(sys_name_to_handle_at, 5)
2308 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2309 MIPS_SYS(sys_clock_adjtime, 2)
2310 MIPS_SYS(sys_syncfs, 1)
048f6b4d 2311};
ff4f7382
RH		 2312# undef MIPS_SYS
2313# endif /* O32 */
048f6b4d 2314
590bc601
PB		 2315static int do_store_exclusive(CPUMIPSState *env)
2316{
2317 target_ulong addr;
2318 target_ulong page_addr;
2319 target_ulong val;
2320 int flags;
2321 int segv = 0;
2322 int reg;
2323 int d;
2324
5499b6ff 2325 addr = env->lladdr;
590bc601
PB		 2326 page_addr = addr & TARGET_PAGE_MASK;
2327 start_exclusive();
2328 mmap_lock();
2329 flags = page_get_flags(page_addr);
2330 if ((flags & PAGE_READ) == 0) {
2331 segv = 1;
2332 } else {
2333 reg = env->llreg & 0x1f;
2334 d = (env->llreg & 0x20) != 0;
2335 if (d) {
2336 segv = get_user_s64(val, addr);
2337 } else {
2338 segv = get_user_s32(val, addr);
2339 }
2340 if (!segv) {
2341 if (val != env->llval) {
2342 env->active_tc.gpr[reg] = 0;
2343 } else {
2344 if (d) {
2345 segv = put_user_u64(env->llnewval, addr);
2346 } else {
2347 segv = put_user_u32(env->llnewval, addr);
2348 }
2349 if (!segv) {
2350 env->active_tc.gpr[reg] = 1;
2351 }
2352 }
2353 }
2354 }
5499b6ff 2355 env->lladdr = -1;
590bc601
PB		 2356 if (!segv) {
2357 env->active_tc.PC += 4;
2358 }
2359 mmap_unlock();
2360 end_exclusive();
2361 return segv;
2362}
2363
54b2f42c
MI		 2364/* Break codes */
2365enum {
2366 BRK_OVERFLOW = 6,
2367 BRK_DIVZERO = 7
2368};
2369
2370static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2371 unsigned int code)
2372{
2373 int ret = -1;
2374
2375 switch (code) {
2376 case BRK_OVERFLOW:
2377 case BRK_DIVZERO:
2378 info->si_signo = TARGET_SIGFPE;
2379 info->si_errno = 0;
2380 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2381 queue_signal(env, info->si_signo, &*info);
2382 ret = 0;
2383 break;
2384 default:
2385 break;
2386 }
2387
2388 return ret;
2389}
2390
048f6b4d
FB		 2391void cpu_loop(CPUMIPSState *env)
2392{
0315c31c 2393 CPUState *cs = CPU(mips_env_get_cpu(env));
c227f099 2394 target_siginfo_t info;
ff4f7382
RH		 2395 int trapnr;
2396 abi_long ret;
2397# ifdef TARGET_ABI_MIPSO32
048f6b4d 2398 unsigned int syscall_num;
ff4f7382 2399# endif
048f6b4d
FB		 2400
2401 for(;;) {
0315c31c 2402 cpu_exec_start(cs);
048f6b4d 2403 trapnr = cpu_mips_exec(env);
0315c31c 2404 cpu_exec_end(cs);
048f6b4d
FB		 2405 switch(trapnr) {
2406 case EXCP_SYSCALL:
b5dc7732 2407 env->active_tc.PC += 4;
ff4f7382
RH		 2408# ifdef TARGET_ABI_MIPSO32
2409 syscall_num = env->active_tc.gpr[2] - 4000;
388bb21a 2410 if (syscall_num >= sizeof(mips_syscall_args)) {
7c2f6157 2411 ret = -TARGET_ENOSYS;
388bb21a
TS		 2412 } else {
2413 int nb_args;
992f48a0
BS		 2414 abi_ulong sp_reg;
2415 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
388bb21a
TS		 2416
2417 nb_args = mips_syscall_args[syscall_num];
b5dc7732 2418 sp_reg = env->active_tc.gpr[29];
388bb21a
TS		 2419 switch (nb_args) {
2420 /* these arguments are taken from the stack */
94c19610
ACH		 2421 case 8:
2422 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2423 goto done_syscall;
2424 }
2425 case 7:
2426 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2427 goto done_syscall;
2428 }
2429 case 6:
2430 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2431 goto done_syscall;
2432 }
2433 case 5:
2434 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2435 goto done_syscall;
2436 }
388bb21a
TS		 2437 default:
2438 break;
048f6b4d 2439 }
b5dc7732
TS		 2440 ret = do_syscall(env, env->active_tc.gpr[2],
2441 env->active_tc.gpr[4],
2442 env->active_tc.gpr[5],
2443 env->active_tc.gpr[6],
2444 env->active_tc.gpr[7],
5945cfcb 2445 arg5, arg6, arg7, arg8);
388bb21a 2446 }
94c19610 2447done_syscall:
ff4f7382
RH		 2448# else
2449 ret = do_syscall(env, env->active_tc.gpr[2],
2450 env->active_tc.gpr[4], env->active_tc.gpr[5],
2451 env->active_tc.gpr[6], env->active_tc.gpr[7],
2452 env->active_tc.gpr[8], env->active_tc.gpr[9],
2453 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2454# endif /* O32 */
0b1bcb00
PB		 2455 if (ret == -TARGET_QEMU_ESIGRETURN) {
2456 /* Returning from a successful sigreturn syscall.
2457 Avoid clobbering register state. */
2458 break;
2459 }
ff4f7382 2460 if ((abi_ulong)ret >= (abi_ulong)-1133) {
b5dc7732 2461 env->active_tc.gpr[7] = 1; /* error flag */
388bb21a
TS		 2462 ret = -ret;
2463 } else {
b5dc7732 2464 env->active_tc.gpr[7] = 0; /* error flag */
048f6b4d 2465 }
b5dc7732 2466 env->active_tc.gpr[2] = ret;
048f6b4d 2467 break;
ca7c2b1b
TS		 2468 case EXCP_TLBL:
2469 case EXCP_TLBS:
e6e5bd2d
WT		 2470 case EXCP_AdEL:
2471 case EXCP_AdES:
e4474235
PB		 2472 info.si_signo = TARGET_SIGSEGV;
2473 info.si_errno = 0;
2474 /* XXX: check env->error_code */
2475 info.si_code = TARGET_SEGV_MAPERR;
2476 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2477 queue_signal(env, info.si_signo, &info);
2478 break;
6900e84b 2479 case EXCP_CpU:
048f6b4d 2480 case EXCP_RI:
bc1ad2de
FB		 2481 info.si_signo = TARGET_SIGILL;
2482 info.si_errno = 0;
2483 info.si_code = 0;
624f7979 2484 queue_signal(env, info.si_signo, &info);
048f6b4d 2485 break;
106ec879
FB		 2486 case EXCP_INTERRUPT:
2487 /* just indicate that signals should be handled asap */
2488 break;
d08b2a28
PB		 2489 case EXCP_DEBUG:
2490 {
2491 int sig;
2492
db6b81d4 2493 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d08b2a28
PB		 2494 if (sig)
2495 {
2496 info.si_signo = sig;
2497 info.si_errno = 0;
2498 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2499 queue_signal(env, info.si_signo, &info);
d08b2a28
PB		 2500 }
2501 }
2502 break;
590bc601
PB		 2503 case EXCP_SC:
2504 if (do_store_exclusive(env)) {
2505 info.si_signo = TARGET_SIGSEGV;
2506 info.si_errno = 0;
2507 info.si_code = TARGET_SEGV_MAPERR;
2508 info._sifields._sigfault._addr = env->active_tc.PC;
2509 queue_signal(env, info.si_signo, &info);
2510 }
2511 break;
853c3240
JL		 2512 case EXCP_DSPDIS:
2513 info.si_signo = TARGET_SIGILL;
2514 info.si_errno = 0;
2515 info.si_code = TARGET_ILL_ILLOPC;
2516 queue_signal(env, info.si_signo, &info);
2517 break;
54b2f42c
MI		 2518 /* The code below was inspired by the MIPS Linux kernel trap
2519 * handling code in arch/mips/kernel/traps.c.
2520 */
2521 case EXCP_BREAK:
2522 {
2523 abi_ulong trap_instr;
2524 unsigned int code;
2525
a0333817
KCY		 2526 if (env->hflags & MIPS_HFLAG_M16) {
2527 if (env->insn_flags & ASE_MICROMIPS) {
2528 /* microMIPS mode */
1308c464
KCY		 2529 ret = get_user_u16(trap_instr, env->active_tc.PC);
2530 if (ret != 0) {
2531 goto error;
2532 }
a0333817 2533
1308c464
KCY		 2534 if ((trap_instr >> 10) == 0x11) {
2535 /* 16-bit instruction */
2536 code = trap_instr & 0xf;
2537 } else {
2538 /* 32-bit instruction */
2539 abi_ulong instr_lo;
2540
2541 ret = get_user_u16(instr_lo,
2542 env->active_tc.PC + 2);
2543 if (ret != 0) {
2544 goto error;
2545 }
2546 trap_instr = (trap_instr << 16) | instr_lo;
2547 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2548 /* Unfortunately, microMIPS also suffers from
2549 the old assembler bug... */
2550 if (code >= (1 << 10)) {
2551 code >>= 10;
2552 }
2553 }
a0333817
KCY		 2554 } else {
2555 /* MIPS16e mode */
2556 ret = get_user_u16(trap_instr, env->active_tc.PC);
2557 if (ret != 0) {
2558 goto error;
2559 }
2560 code = (trap_instr >> 6) & 0x3f;
a0333817
KCY		 2561 }
2562 } else {
2563 ret = get_user_ual(trap_instr, env->active_tc.PC);
1308c464
KCY		 2564 if (ret != 0) {
2565 goto error;
2566 }
54b2f42c 2567
1308c464
KCY		 2568 /* As described in the original Linux kernel code, the
2569 * below checks on 'code' are to work around an old
2570 * assembly bug.
2571 */
2572 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2573 if (code >= (1 << 10)) {
2574 code >>= 10;
2575 }
54b2f42c
MI		 2576 }
2577
2578 if (do_break(env, &info, code) != 0) {
2579 goto error;
2580 }
2581 }
2582 break;
2583 case EXCP_TRAP:
2584 {
2585 abi_ulong trap_instr;
2586 unsigned int code = 0;
2587
a0333817
KCY		 2588 if (env->hflags & MIPS_HFLAG_M16) {
2589 /* microMIPS mode */
2590 abi_ulong instr[2];
2591
2592 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2593 get_user_u16(instr[1], env->active_tc.PC + 2);
2594
2595 trap_instr = (instr[0] << 16) | instr[1];
2596 } else {
2597 ret = get_user_ual(trap_instr, env->active_tc.PC);
2598 }
2599
54b2f42c
MI		 2600 if (ret != 0) {
2601 goto error;
2602 }
2603
2604 /* The immediate versions don't provide a code. */
2605 if (!(trap_instr & 0xFC000000)) {
a0333817
KCY		 2606 if (env->hflags & MIPS_HFLAG_M16) {
2607 /* microMIPS mode */
2608 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2609 } else {
2610 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2611 }
54b2f42c
MI		 2612 }
2613
2614 if (do_break(env, &info, code) != 0) {
2615 goto error;
2616 }
2617 }
2618 break;
048f6b4d 2619 default:
54b2f42c 2620error:
5fafdf24 2621 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
048f6b4d 2622 trapnr);
878096ee 2623 cpu_dump_state(cs, stderr, fprintf, 0);
048f6b4d
FB		 2624 abort();
2625 }
2626 process_pending_signals(env);
2627 }
2628}
2629#endif
2630
d962783e
JL		 2631#ifdef TARGET_OPENRISC
2632
2633void cpu_loop(CPUOpenRISCState *env)
2634{
878096ee 2635 CPUState *cs = CPU(openrisc_env_get_cpu(env));
d962783e
JL		 2636 int trapnr, gdbsig;
2637
2638 for (;;) {
2639 trapnr = cpu_exec(env);
2640 gdbsig = 0;
2641
2642 switch (trapnr) {
2643 case EXCP_RESET:
2644 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2645 exit(1);
2646 break;
2647 case EXCP_BUSERR:
2648 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
2649 gdbsig = SIGBUS;
2650 break;
2651 case EXCP_DPF:
2652 case EXCP_IPF:
878096ee 2653 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2654 gdbsig = TARGET_SIGSEGV;
2655 break;
2656 case EXCP_TICK:
2657 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2658 break;
2659 case EXCP_ALIGN:
2660 qemu_log("\nAlignment pc is %#x\n", env->pc);
2661 gdbsig = SIGBUS;
2662 break;
2663 case EXCP_ILLEGAL:
2664 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
2665 gdbsig = SIGILL;
2666 break;
2667 case EXCP_INT:
2668 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2669 break;
2670 case EXCP_DTLBMISS:
2671 case EXCP_ITLBMISS:
2672 qemu_log("\nTLB miss\n");
2673 break;
2674 case EXCP_RANGE:
2675 qemu_log("\nRange\n");
2676 gdbsig = SIGSEGV;
2677 break;
2678 case EXCP_SYSCALL:
2679 env->pc += 4; /* 0xc00; */
2680 env->gpr[11] = do_syscall(env,
2681 env->gpr[11], /* return value */
2682 env->gpr[3], /* r3 - r7 are params */
2683 env->gpr[4],
2684 env->gpr[5],
2685 env->gpr[6],
2686 env->gpr[7],
2687 env->gpr[8], 0, 0);
2688 break;
2689 case EXCP_FPE:
2690 qemu_log("\nFloating point error\n");
2691 break;
2692 case EXCP_TRAP:
2693 qemu_log("\nTrap\n");
2694 gdbsig = SIGTRAP;
2695 break;
2696 case EXCP_NR:
2697 qemu_log("\nNR\n");
2698 break;
2699 default:
2700 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2701 trapnr);
878096ee 2702 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2703 gdbsig = TARGET_SIGILL;
2704 break;
2705 }
2706 if (gdbsig) {
db6b81d4 2707 gdb_handlesig(cs, gdbsig);
d962783e
JL		 2708 if (gdbsig != TARGET_SIGTRAP) {
2709 exit(1);
2710 }
2711 }
2712
2713 process_pending_signals(env);
2714 }
2715}
2716
2717#endif /* TARGET_OPENRISC */
2718
fdf9b3e8 2719#ifdef TARGET_SH4
05390248 2720void cpu_loop(CPUSH4State *env)
fdf9b3e8 2721{
878096ee 2722 CPUState *cs = CPU(sh_env_get_cpu(env));
fdf9b3e8 2723 int trapnr, ret;
c227f099 2724 target_siginfo_t info;
3b46e624 2725
fdf9b3e8
FB		 2726 while (1) {
2727 trapnr = cpu_sh4_exec (env);
3b46e624 2728
fdf9b3e8
FB		 2729 switch (trapnr) {
2730 case 0x160:
0b6d3ae0 2731 env->pc += 2;
5fafdf24
TS		 2732 ret = do_syscall(env,
2733 env->gregs[3],
2734 env->gregs[4],
2735 env->gregs[5],
2736 env->gregs[6],
2737 env->gregs[7],
2738 env->gregs[0],
5945cfcb
PM		 2739 env->gregs[1],
2740 0, 0);
9c2a9ea1 2741 env->gregs[0] = ret;
fdf9b3e8 2742 break;
c3b5bc8a
TS		 2743 case EXCP_INTERRUPT:
2744 /* just indicate that signals should be handled asap */
2745 break;
355fb23d
PB		 2746 case EXCP_DEBUG:
2747 {
2748 int sig;
2749
db6b81d4 2750 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
355fb23d
PB		 2751 if (sig)
2752 {
2753 info.si_signo = sig;
2754 info.si_errno = 0;
2755 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2756 queue_signal(env, info.si_signo, &info);
355fb23d
PB		 2757 }
2758 }
2759 break;
c3b5bc8a
TS		 2760 case 0xa0:
2761 case 0xc0:
2762 info.si_signo = SIGSEGV;
2763 info.si_errno = 0;
2764 info.si_code = TARGET_SEGV_MAPERR;
2765 info._sifields._sigfault._addr = env->tea;
624f7979 2766 queue_signal(env, info.si_signo, &info);
c3b5bc8a
TS		 2767 break;
2768
fdf9b3e8
FB		 2769 default:
2770 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2771 cpu_dump_state(cs, stderr, fprintf, 0);
fdf9b3e8
FB		 2772 exit (1);
2773 }
2774 process_pending_signals (env);
2775 }
2776}
2777#endif
2778
48733d19 2779#ifdef TARGET_CRIS
05390248 2780void cpu_loop(CPUCRISState *env)
48733d19 2781{
878096ee 2782 CPUState *cs = CPU(cris_env_get_cpu(env));
48733d19 2783 int trapnr, ret;
c227f099 2784 target_siginfo_t info;
48733d19
TS		 2785
2786 while (1) {
2787 trapnr = cpu_cris_exec (env);
2788 switch (trapnr) {
2789 case 0xaa:
2790 {
2791 info.si_signo = SIGSEGV;
2792 info.si_errno = 0;
2793 /* XXX: check env->error_code */
2794 info.si_code = TARGET_SEGV_MAPERR;
e00c1e71 2795 info._sifields._sigfault._addr = env->pregs[PR_EDA];
624f7979 2796 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2797 }
2798 break;
b6d3abda
EI		 2799 case EXCP_INTERRUPT:
2800 /* just indicate that signals should be handled asap */
2801 break;
48733d19
TS		 2802 case EXCP_BREAK:
2803 ret = do_syscall(env,
2804 env->regs[9],
2805 env->regs[10],
2806 env->regs[11],
2807 env->regs[12],
2808 env->regs[13],
2809 env->pregs[7],
5945cfcb
PM		 2810 env->pregs[11],
2811 0, 0);
48733d19 2812 env->regs[10] = ret;
48733d19
TS		 2813 break;
2814 case EXCP_DEBUG:
2815 {
2816 int sig;
2817
db6b81d4 2818 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
48733d19
TS		 2819 if (sig)
2820 {
2821 info.si_signo = sig;
2822 info.si_errno = 0;
2823 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2824 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2825 }
2826 }
2827 break;
2828 default:
2829 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2830 cpu_dump_state(cs, stderr, fprintf, 0);
48733d19
TS		 2831 exit (1);
2832 }
2833 process_pending_signals (env);
2834 }
2835}
2836#endif
2837
b779e29e 2838#ifdef TARGET_MICROBLAZE
05390248 2839void cpu_loop(CPUMBState *env)
b779e29e 2840{
878096ee 2841 CPUState *cs = CPU(mb_env_get_cpu(env));
b779e29e 2842 int trapnr, ret;
c227f099 2843 target_siginfo_t info;
b779e29e
EI		 2844
2845 while (1) {
2846 trapnr = cpu_mb_exec (env);
2847 switch (trapnr) {
2848 case 0xaa:
2849 {
2850 info.si_signo = SIGSEGV;
2851 info.si_errno = 0;
2852 /* XXX: check env->error_code */
2853 info.si_code = TARGET_SEGV_MAPERR;
2854 info._sifields._sigfault._addr = 0;
2855 queue_signal(env, info.si_signo, &info);
2856 }
2857 break;
2858 case EXCP_INTERRUPT:
2859 /* just indicate that signals should be handled asap */
2860 break;
2861 case EXCP_BREAK:
2862 /* Return address is 4 bytes after the call. */
2863 env->regs[14] += 4;
d7dce494 2864 env->sregs[SR_PC] = env->regs[14];
b779e29e
EI		 2865 ret = do_syscall(env,
2866 env->regs[12],
2867 env->regs[5],
2868 env->regs[6],
2869 env->regs[7],
2870 env->regs[8],
2871 env->regs[9],
5945cfcb
PM		 2872 env->regs[10],
2873 0, 0);
b779e29e 2874 env->regs[3] = ret;
b779e29e 2875 break;
b76da7e3
EI		 2876 case EXCP_HW_EXCP:
2877 env->regs[17] = env->sregs[SR_PC] + 4;
2878 if (env->iflags & D_FLAG) {
2879 env->sregs[SR_ESR] |= 1 << 12;
2880 env->sregs[SR_PC] -= 4;
b4916d7b 2881 /* FIXME: if branch was immed, replay the imm as well. */
b76da7e3
EI		 2882 }
2883
2884 env->iflags &= ~(IMM_FLAG | D_FLAG);
2885
2886 switch (env->sregs[SR_ESR] & 31) {
22a78d64
EI		 2887 case ESR_EC_DIVZERO:
2888 info.si_signo = SIGFPE;
2889 info.si_errno = 0;
2890 info.si_code = TARGET_FPE_FLTDIV;
2891 info._sifields._sigfault._addr = 0;
2892 queue_signal(env, info.si_signo, &info);
2893 break;
b76da7e3
EI		 2894 case ESR_EC_FPU:
2895 info.si_signo = SIGFPE;
2896 info.si_errno = 0;
2897 if (env->sregs[SR_FSR] & FSR_IO) {
2898 info.si_code = TARGET_FPE_FLTINV;
2899 }
2900 if (env->sregs[SR_FSR] & FSR_DZ) {
2901 info.si_code = TARGET_FPE_FLTDIV;
2902 }
2903 info._sifields._sigfault._addr = 0;
2904 queue_signal(env, info.si_signo, &info);
2905 break;
2906 default:
2907 printf ("Unhandled hw-exception: 0x%x\n",
2e42d52d 2908 env->sregs[SR_ESR] & ESR_EC_MASK);
878096ee 2909 cpu_dump_state(cs, stderr, fprintf, 0);
b76da7e3
EI		 2910 exit (1);
2911 break;
2912 }
2913 break;
b779e29e
EI		 2914 case EXCP_DEBUG:
2915 {
2916 int sig;
2917
db6b81d4 2918 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
b779e29e
EI		 2919 if (sig)
2920 {
2921 info.si_signo = sig;
2922 info.si_errno = 0;
2923 info.si_code = TARGET_TRAP_BRKPT;
2924 queue_signal(env, info.si_signo, &info);
2925 }
2926 }
2927 break;
2928 default:
2929 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2930 cpu_dump_state(cs, stderr, fprintf, 0);
b779e29e
EI		 2931 exit (1);
2932 }
2933 process_pending_signals (env);
2934 }
2935}
2936#endif
2937
e6e5906b
PB		 2938#ifdef TARGET_M68K
2939
2940void cpu_loop(CPUM68KState *env)
2941{
878096ee 2942 CPUState *cs = CPU(m68k_env_get_cpu(env));
e6e5906b
PB		 2943 int trapnr;
2944 unsigned int n;
c227f099 2945 target_siginfo_t info;
e6e5906b 2946 TaskState *ts = env->opaque;
3b46e624 2947
e6e5906b
PB		 2948 for(;;) {
2949 trapnr = cpu_m68k_exec(env);
2950 switch(trapnr) {
2951 case EXCP_ILLEGAL:
2952 {
2953 if (ts->sim_syscalls) {
2954 uint16_t nr;
2955 nr = lduw(env->pc + 2);
2956 env->pc += 4;
2957 do_m68k_simcall(env, nr);
2958 } else {
2959 goto do_sigill;
2960 }
2961 }
2962 break;
a87295e8 2963 case EXCP_HALT_INSN:
e6e5906b 2964 /* Semihosing syscall. */
a87295e8 2965 env->pc += 4;
e6e5906b
PB		 2966 do_m68k_semihosting(env, env->dregs[0]);
2967 break;
2968 case EXCP_LINEA:
2969 case EXCP_LINEF:
2970 case EXCP_UNSUPPORTED:
2971 do_sigill:
2972 info.si_signo = SIGILL;
2973 info.si_errno = 0;
2974 info.si_code = TARGET_ILL_ILLOPN;
2975 info._sifields._sigfault._addr = env->pc;
624f7979 2976 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2977 break;
2978 case EXCP_TRAP0:
2979 {
2980 ts->sim_syscalls = 0;
2981 n = env->dregs[0];
2982 env->pc += 2;
5fafdf24
TS		 2983 env->dregs[0] = do_syscall(env,
2984 n,
e6e5906b
PB		 2985 env->dregs[1],
2986 env->dregs[2],
2987 env->dregs[3],
2988 env->dregs[4],
2989 env->dregs[5],
5945cfcb
PM		 2990 env->aregs[0],
2991 0, 0);
e6e5906b
PB		 2992 }
2993 break;
2994 case EXCP_INTERRUPT:
2995 /* just indicate that signals should be handled asap */
2996 break;
2997 case EXCP_ACCESS:
2998 {
2999 info.si_signo = SIGSEGV;
3000 info.si_errno = 0;
3001 /* XXX: check env->error_code */
3002 info.si_code = TARGET_SEGV_MAPERR;
3003 info._sifields._sigfault._addr = env->mmu.ar;
624f7979 3004 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3005 }
3006 break;
3007 case EXCP_DEBUG:
3008 {
3009 int sig;
3010
db6b81d4 3011 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
e6e5906b
PB		 3012 if (sig)
3013 {
3014 info.si_signo = sig;
3015 info.si_errno = 0;
3016 info.si_code = TARGET_TRAP_BRKPT;
624f7979 3017 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3018 }
3019 }
3020 break;
3021 default:
5fafdf24 3022 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
e6e5906b 3023 trapnr);
878096ee 3024 cpu_dump_state(cs, stderr, fprintf, 0);
e6e5906b
PB		 3025 abort();
3026 }
3027 process_pending_signals(env);
3028 }
3029}
3030#endif /* TARGET_M68K */
3031
7a3148a9 3032#ifdef TARGET_ALPHA
6910b8f6
RH		 3033static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3034{
3035 target_ulong addr, val, tmp;
3036 target_siginfo_t info;
3037 int ret = 0;
3038
3039 addr = env->lock_addr;
3040 tmp = env->lock_st_addr;
3041 env->lock_addr = -1;
3042 env->lock_st_addr = 0;
3043
3044 start_exclusive();
3045 mmap_lock();
3046
3047 if (addr == tmp) {
3048 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3049 goto do_sigsegv;
3050 }
3051
3052 if (val == env->lock_value) {
3053 tmp = env->ir[reg];
3054 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3055 goto do_sigsegv;
3056 }
3057 ret = 1;
3058 }
3059 }
3060 env->ir[reg] = ret;
3061 env->pc += 4;
3062
3063 mmap_unlock();
3064 end_exclusive();
3065 return;
3066
3067 do_sigsegv:
3068 mmap_unlock();
3069 end_exclusive();
3070
3071 info.si_signo = TARGET_SIGSEGV;
3072 info.si_errno = 0;
3073 info.si_code = TARGET_SEGV_MAPERR;
3074 info._sifields._sigfault._addr = addr;
3075 queue_signal(env, TARGET_SIGSEGV, &info);
3076}
3077
05390248 3078void cpu_loop(CPUAlphaState *env)
7a3148a9 3079{
878096ee 3080 CPUState *cs = CPU(alpha_env_get_cpu(env));
e96efcfc 3081 int trapnr;
c227f099 3082 target_siginfo_t info;
6049f4f8 3083 abi_long sysret;
3b46e624 3084
7a3148a9
JM		 3085 while (1) {
3086 trapnr = cpu_alpha_exec (env);
3b46e624 3087
ac316ca4
RH		 3088 /* All of the traps imply a transition through PALcode, which
3089 implies an REI instruction has been executed. Which means
3090 that the intr_flag should be cleared. */
3091 env->intr_flag = 0;
3092
7a3148a9
JM		 3093 switch (trapnr) {
3094 case EXCP_RESET:
3095 fprintf(stderr, "Reset requested. Exit\n");
3096 exit(1);
3097 break;
3098 case EXCP_MCHK:
3099 fprintf(stderr, "Machine check exception. Exit\n");
3100 exit(1);
3101 break;
07b6c13b
RH		 3102 case EXCP_SMP_INTERRUPT:
3103 case EXCP_CLK_INTERRUPT:
3104 case EXCP_DEV_INTERRUPT:
5fafdf24 3105 fprintf(stderr, "External interrupt. Exit\n");
7a3148a9
JM		 3106 exit(1);
3107 break;
07b6c13b 3108 case EXCP_MMFAULT:
6910b8f6 3109 env->lock_addr = -1;
6049f4f8
RH		 3110 info.si_signo = TARGET_SIGSEGV;
3111 info.si_errno = 0;
129d8aa5 3112 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
0be1d07c 3113 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
129d8aa5 3114 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3115 queue_signal(env, info.si_signo, &info);
7a3148a9 3116 break;
7a3148a9 3117 case EXCP_UNALIGN:
6910b8f6 3118 env->lock_addr = -1;
6049f4f8
RH		 3119 info.si_signo = TARGET_SIGBUS;
3120 info.si_errno = 0;
3121 info.si_code = TARGET_BUS_ADRALN;
129d8aa5 3122 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3123 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3124 break;
3125 case EXCP_OPCDEC:
6049f4f8 3126 do_sigill:
6910b8f6 3127 env->lock_addr = -1;
6049f4f8
RH		 3128 info.si_signo = TARGET_SIGILL;
3129 info.si_errno = 0;
3130 info.si_code = TARGET_ILL_ILLOPC;
3131 info._sifields._sigfault._addr = env->pc;
3132 queue_signal(env, info.si_signo, &info);
7a3148a9 3133 break;
07b6c13b
RH		 3134 case EXCP_ARITH:
3135 env->lock_addr = -1;
3136 info.si_signo = TARGET_SIGFPE;
3137 info.si_errno = 0;
3138 info.si_code = TARGET_FPE_FLTINV;
3139 info._sifields._sigfault._addr = env->pc;
3140 queue_signal(env, info.si_signo, &info);
3141 break;
7a3148a9 3142 case EXCP_FEN:
6049f4f8 3143 /* No-op. Linux simply re-enables the FPU. */
7a3148a9 3144 break;
07b6c13b 3145 case EXCP_CALL_PAL:
6910b8f6 3146 env->lock_addr = -1;
07b6c13b 3147 switch (env->error_code) {
6049f4f8
RH		 3148 case 0x80:
3149 /* BPT */
3150 info.si_signo = TARGET_SIGTRAP;
3151 info.si_errno = 0;
3152 info.si_code = TARGET_TRAP_BRKPT;
3153 info._sifields._sigfault._addr = env->pc;
3154 queue_signal(env, info.si_signo, &info);
3155 break;
3156 case 0x81:
3157 /* BUGCHK */
3158 info.si_signo = TARGET_SIGTRAP;
3159 info.si_errno = 0;
3160 info.si_code = 0;
3161 info._sifields._sigfault._addr = env->pc;
3162 queue_signal(env, info.si_signo, &info);
3163 break;
3164 case 0x83:
3165 /* CALLSYS */
3166 trapnr = env->ir[IR_V0];
3167 sysret = do_syscall(env, trapnr,
3168 env->ir[IR_A0], env->ir[IR_A1],
3169 env->ir[IR_A2], env->ir[IR_A3],
5945cfcb
PM		 3170 env->ir[IR_A4], env->ir[IR_A5],
3171 0, 0);
a5b3b13b
RH		 3172 if (trapnr == TARGET_NR_sigreturn
3173 || trapnr == TARGET_NR_rt_sigreturn) {
3174 break;
3175 }
3176 /* Syscall writes 0 to V0 to bypass error check, similar
0e141977
RH		 3177 to how this is handled internal to Linux kernel.
3178 (Ab)use trapnr temporarily as boolean indicating error. */
3179 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3180 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3181 env->ir[IR_A3] = trapnr;
6049f4f8
RH		 3182 break;
3183 case 0x86:
3184 /* IMB */
3185 /* ??? We can probably elide the code using page_unprotect
3186 that is checking for self-modifying code. Instead we
3187 could simply call tb_flush here. Until we work out the
3188 changes required to turn off the extra write protection,
3189 this can be a no-op. */
3190 break;
3191 case 0x9E:
3192 /* RDUNIQUE */
3193 /* Handled in the translator for usermode. */
3194 abort();
3195 case 0x9F:
3196 /* WRUNIQUE */
3197 /* Handled in the translator for usermode. */
3198 abort();
3199 case 0xAA:
3200 /* GENTRAP */
3201 info.si_signo = TARGET_SIGFPE;
3202 switch (env->ir[IR_A0]) {
3203 case TARGET_GEN_INTOVF:
3204 info.si_code = TARGET_FPE_INTOVF;
3205 break;
3206 case TARGET_GEN_INTDIV:
3207 info.si_code = TARGET_FPE_INTDIV;
3208 break;
3209 case TARGET_GEN_FLTOVF:
3210 info.si_code = TARGET_FPE_FLTOVF;
3211 break;
3212 case TARGET_GEN_FLTUND:
3213 info.si_code = TARGET_FPE_FLTUND;
3214 break;
3215 case TARGET_GEN_FLTINV:
3216 info.si_code = TARGET_FPE_FLTINV;
3217 break;
3218 case TARGET_GEN_FLTINE:
3219 info.si_code = TARGET_FPE_FLTRES;
3220 break;
3221 case TARGET_GEN_ROPRAND:
3222 info.si_code = 0;
3223 break;
3224 default:
3225 info.si_signo = TARGET_SIGTRAP;
3226 info.si_code = 0;
3227 break;
3228 }
3229 info.si_errno = 0;
3230 info._sifields._sigfault._addr = env->pc;
3231 queue_signal(env, info.si_signo, &info);
3232 break;
3233 default:
3234 goto do_sigill;
3235 }
7a3148a9 3236 break;
7a3148a9 3237 case EXCP_DEBUG:
db6b81d4 3238 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
6049f4f8 3239 if (info.si_signo) {
6910b8f6 3240 env->lock_addr = -1;
6049f4f8
RH		 3241 info.si_errno = 0;
3242 info.si_code = TARGET_TRAP_BRKPT;
3243 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3244 }
3245 break;
6910b8f6
RH		 3246 case EXCP_STL_C:
3247 case EXCP_STQ_C:
3248 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3249 break;
d0f20495
RH		 3250 case EXCP_INTERRUPT:
3251 /* Just indicate that signals should be handled asap. */
3252 break;
7a3148a9
JM		 3253 default:
3254 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3255 cpu_dump_state(cs, stderr, fprintf, 0);
7a3148a9
JM		 3256 exit (1);
3257 }
3258 process_pending_signals (env);
3259 }
3260}
3261#endif /* TARGET_ALPHA */
3262
a4c075f1
UH		 3263#ifdef TARGET_S390X
3264void cpu_loop(CPUS390XState *env)
3265{
878096ee 3266 CPUState *cs = CPU(s390_env_get_cpu(env));
d5a103cd 3267 int trapnr, n, sig;
a4c075f1 3268 target_siginfo_t info;
d5a103cd 3269 target_ulong addr;
a4c075f1
UH		 3270
3271 while (1) {
d5a103cd 3272 trapnr = cpu_s390x_exec(env);
a4c075f1
UH		 3273 switch (trapnr) {
3274 case EXCP_INTERRUPT:
d5a103cd 3275 /* Just indicate that signals should be handled asap. */
a4c075f1 3276 break;
a4c075f1 3277
d5a103cd
RH		 3278 case EXCP_SVC:
3279 n = env->int_svc_code;
3280 if (!n) {
3281 /* syscalls > 255 */
3282 n = env->regs[1];
a4c075f1 3283 }
d5a103cd
RH		 3284 env->psw.addr += env->int_svc_ilen;
3285 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3286 env->regs[4], env->regs[5],
3287 env->regs[6], env->regs[7], 0, 0);
a4c075f1 3288 break;
d5a103cd
RH		 3289
3290 case EXCP_DEBUG:
db6b81d4 3291 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d5a103cd
RH		 3292 if (sig) {
3293 n = TARGET_TRAP_BRKPT;
3294 goto do_signal_pc;
a4c075f1
UH		 3295 }
3296 break;
d5a103cd
RH		 3297 case EXCP_PGM:
3298 n = env->int_pgm_code;
3299 switch (n) {
3300 case PGM_OPERATION:
3301 case PGM_PRIVILEGED:
3302 sig = SIGILL;
3303 n = TARGET_ILL_ILLOPC;
3304 goto do_signal_pc;
3305 case PGM_PROTECTION:
3306 case PGM_ADDRESSING:
3307 sig = SIGSEGV;
a4c075f1 3308 /* XXX: check env->error_code */
d5a103cd
RH		 3309 n = TARGET_SEGV_MAPERR;
3310 addr = env->__excp_addr;
3311 goto do_signal;
3312 case PGM_EXECUTE:
3313 case PGM_SPECIFICATION:
3314 case PGM_SPECIAL_OP:
3315 case PGM_OPERAND:
3316 do_sigill_opn:
3317 sig = SIGILL;
3318 n = TARGET_ILL_ILLOPN;
3319 goto do_signal_pc;
3320
3321 case PGM_FIXPT_OVERFLOW:
3322 sig = SIGFPE;
3323 n = TARGET_FPE_INTOVF;
3324 goto do_signal_pc;
3325 case PGM_FIXPT_DIVIDE:
3326 sig = SIGFPE;
3327 n = TARGET_FPE_INTDIV;
3328 goto do_signal_pc;
3329
3330 case PGM_DATA:
3331 n = (env->fpc >> 8) & 0xff;
3332 if (n == 0xff) {
3333 /* compare-and-trap */
3334 goto do_sigill_opn;
3335 } else {
3336 /* An IEEE exception, simulated or otherwise. */
3337 if (n & 0x80) {
3338 n = TARGET_FPE_FLTINV;
3339 } else if (n & 0x40) {
3340 n = TARGET_FPE_FLTDIV;
3341 } else if (n & 0x20) {
3342 n = TARGET_FPE_FLTOVF;
3343 } else if (n & 0x10) {
3344 n = TARGET_FPE_FLTUND;
3345 } else if (n & 0x08) {
3346 n = TARGET_FPE_FLTRES;
3347 } else {
3348 /* ??? Quantum exception; BFP, DFP error. */
3349 goto do_sigill_opn;
3350 }
3351 sig = SIGFPE;
3352 goto do_signal_pc;
3353 }
3354
3355 default:
3356 fprintf(stderr, "Unhandled program exception: %#x\n", n);
878096ee 3357 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3358 exit(1);
a4c075f1
UH		 3359 }
3360 break;
d5a103cd
RH		 3361
3362 do_signal_pc:
3363 addr = env->psw.addr;
3364 do_signal:
3365 info.si_signo = sig;
3366 info.si_errno = 0;
3367 info.si_code = n;
3368 info._sifields._sigfault._addr = addr;
3369 queue_signal(env, info.si_signo, &info);
a4c075f1 3370 break;
d5a103cd 3371
a4c075f1 3372 default:
d5a103cd 3373 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
878096ee 3374 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3375 exit(1);
a4c075f1
UH		 3376 }
3377 process_pending_signals (env);
3378 }
3379}
3380
3381#endif /* TARGET_S390X */
3382
a2247f8e 3383THREAD CPUState *thread_cpu;
59faf6d6 3384
edf8e2af
MW		 3385void task_settid(TaskState *ts)
3386{
3387 if (ts->ts_tid == 0) {
edf8e2af 3388 ts->ts_tid = (pid_t)syscall(SYS_gettid);
edf8e2af
MW		 3389 }
3390}
3391
3392void stop_all_tasks(void)
3393{
3394 /*
3395 * We trust that when using NPTL, start_exclusive()
3396 * handles thread stopping correctly.
3397 */
3398 start_exclusive();
3399}
3400
c3a92833 3401/* Assumes contents are already zeroed. */
624f7979
PB		 3402void init_task_state(TaskState *ts)
3403{
3404 int i;
3405
624f7979
PB		 3406 ts->used = 1;
3407 ts->first_free = ts->sigqueue_table;
3408 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3409 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3410 }
3411 ts->sigqueue_table[i].next = NULL;
3412}
fc9c5412 3413
30ba0ee5
AF		 3414CPUArchState *cpu_copy(CPUArchState *env)
3415{
51fb256a 3416 CPUArchState *new_env = cpu_init(cpu_model);
30ba0ee5
AF		 3417#if defined(TARGET_HAS_ICE)
3418 CPUBreakpoint *bp;
3419 CPUWatchpoint *wp;
3420#endif
3421
3422 /* Reset non arch specific state */
3423 cpu_reset(ENV_GET_CPU(new_env));
3424
3425 memcpy(new_env, env, sizeof(CPUArchState));
3426
3427 /* Clone all break/watchpoints.
3428 Note: Once we support ptrace with hw-debug register access, make sure
3429 BP_CPU break/watchpoints are handled correctly on clone. */
3430 QTAILQ_INIT(&env->breakpoints);
3431 QTAILQ_INIT(&env->watchpoints);
3432#if defined(TARGET_HAS_ICE)
3433 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
3434 cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL);
3435 }
3436 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
3437 cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1,
3438 wp->flags, NULL);
3439 }
3440#endif
3441
3442 return new_env;
3443}
3444
fc9c5412
JS		 3445static void handle_arg_help(const char *arg)
3446{
3447 usage();
3448}
3449
3450static void handle_arg_log(const char *arg)
3451{
3452 int mask;
fc9c5412 3453
4fde1eba 3454 mask = qemu_str_to_log_mask(arg);
fc9c5412 3455 if (!mask) {
59a6fa6e 3456 qemu_print_log_usage(stdout);
fc9c5412
JS		 3457 exit(1);
3458 }
24537a01 3459 qemu_set_log(mask);
fc9c5412
JS		 3460}
3461
50171d42
CWR		 3462static void handle_arg_log_filename(const char *arg)
3463{
9a7e5424 3464 qemu_set_log_filename(arg);
50171d42
CWR		 3465}
3466
fc9c5412
JS		 3467static void handle_arg_set_env(const char *arg)
3468{
3469 char *r, *p, *token;
3470 r = p = strdup(arg);
3471 while ((token = strsep(&p, ",")) != NULL) {
3472 if (envlist_setenv(envlist, token) != 0) {
3473 usage();
3474 }
3475 }
3476 free(r);
3477}
3478
3479static void handle_arg_unset_env(const char *arg)
3480{
3481 char *r, *p, *token;
3482 r = p = strdup(arg);
3483 while ((token = strsep(&p, ",")) != NULL) {
3484 if (envlist_unsetenv(envlist, token) != 0) {
3485 usage();
3486 }
3487 }
3488 free(r);
3489}
3490
3491static void handle_arg_argv0(const char *arg)
3492{
3493 argv0 = strdup(arg);
3494}
3495
3496static void handle_arg_stack_size(const char *arg)
3497{
3498 char *p;
3499 guest_stack_size = strtoul(arg, &p, 0);
3500 if (guest_stack_size == 0) {
3501 usage();
3502 }
3503
3504 if (*p == 'M') {
3505 guest_stack_size *= 1024 * 1024;
3506 } else if (*p == 'k' || *p == 'K') {
3507 guest_stack_size *= 1024;
3508 }
3509}
3510
3511static void handle_arg_ld_prefix(const char *arg)
3512{
3513 interp_prefix = strdup(arg);
3514}
3515
3516static void handle_arg_pagesize(const char *arg)
3517{
3518 qemu_host_page_size = atoi(arg);
3519 if (qemu_host_page_size == 0 ||
3520 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3521 fprintf(stderr, "page size must be a power of two\n");
3522 exit(1);
3523 }
3524}
3525
3526static void handle_arg_gdb(const char *arg)
3527{
3528 gdbstub_port = atoi(arg);
3529}
3530
3531static void handle_arg_uname(const char *arg)
3532{
3533 qemu_uname_release = strdup(arg);
3534}
3535
3536static void handle_arg_cpu(const char *arg)
3537{
3538 cpu_model = strdup(arg);
c8057f95 3539 if (cpu_model == NULL || is_help_option(cpu_model)) {
fc9c5412 3540 /* XXX: implement xxx_cpu_list for targets that still miss it */
e916cbf8
PM		 3541#if defined(cpu_list)
3542 cpu_list(stdout, &fprintf);
fc9c5412
JS		 3543#endif
3544 exit(1);
3545 }
3546}
3547
3548#if defined(CONFIG_USE_GUEST_BASE)
3549static void handle_arg_guest_base(const char *arg)
3550{
3551 guest_base = strtol(arg, NULL, 0);
3552 have_guest_base = 1;
3553}
3554
3555static void handle_arg_reserved_va(const char *arg)
3556{
3557 char *p;
3558 int shift = 0;
3559 reserved_va = strtoul(arg, &p, 0);
3560 switch (*p) {
3561 case 'k':
3562 case 'K':
3563 shift = 10;
3564 break;
3565 case 'M':
3566 shift = 20;
3567 break;
3568 case 'G':
3569 shift = 30;
3570 break;
3571 }
3572 if (shift) {
3573 unsigned long unshifted = reserved_va;
3574 p++;
3575 reserved_va <<= shift;
3576 if (((reserved_va >> shift) != unshifted)
3577#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3578 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3579#endif
3580 ) {
3581 fprintf(stderr, "Reserved virtual address too big\n");
3582 exit(1);
3583 }
3584 }
3585 if (*p) {
3586 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3587 exit(1);
3588 }
3589}
3590#endif
3591
3592static void handle_arg_singlestep(const char *arg)
3593{
3594 singlestep = 1;
3595}
3596
3597static void handle_arg_strace(const char *arg)
3598{
3599 do_strace = 1;
3600}
3601
3602static void handle_arg_version(const char *arg)
3603{
2e59915d 3604 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
fc9c5412 3605 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
1386d4c0 3606 exit(0);
fc9c5412
JS		 3607}
3608
3609struct qemu_argument {
3610 const char *argv;
3611 const char *env;
3612 bool has_arg;
3613 void (*handle_opt)(const char *arg);
3614 const char *example;
3615 const char *help;
3616};
3617
42644cee 3618static const struct qemu_argument arg_table[] = {
fc9c5412
JS		 3619 {"h", "", false, handle_arg_help,
3620 "", "print this help"},
3621 {"g", "QEMU_GDB", true, handle_arg_gdb,
3622 "port", "wait gdb connection to 'port'"},
3623 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3624 "path", "set the elf interpreter prefix to 'path'"},
3625 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3626 "size", "set the stack size to 'size' bytes"},
3627 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
c8057f95 3628 "model", "select CPU (-cpu help for list)"},
fc9c5412
JS		 3629 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3630 "var=value", "sets targets environment variable (see below)"},
3631 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3632 "var", "unsets targets environment variable (see below)"},
3633 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3634 "argv0", "forces target process argv[0] to be 'argv0'"},
3635 {"r", "QEMU_UNAME", true, handle_arg_uname,
3636 "uname", "set qemu uname release string to 'uname'"},
3637#if defined(CONFIG_USE_GUEST_BASE)
3638 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3639 "address", "set guest_base address to 'address'"},
3640 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3641 "size", "reserve 'size' bytes for guest virtual address space"},
3642#endif
3643 {"d", "QEMU_LOG", true, handle_arg_log,
989b697d
PM		 3644 "item[,...]", "enable logging of specified items "
3645 "(use '-d help' for a list of items)"},
50171d42 3646 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
989b697d 3647 "logfile", "write logs to 'logfile' (default stderr)"},
fc9c5412
JS		 3648 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3649 "pagesize", "set the host page size to 'pagesize'"},
3650 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3651 "", "run in singlestep mode"},
3652 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3653 "", "log system calls"},
3654 {"version", "QEMU_VERSION", false, handle_arg_version,
1386d4c0 3655 "", "display version information and exit"},
fc9c5412
JS		 3656 {NULL, NULL, false, NULL, NULL, NULL}
3657};
3658
3659static void usage(void)
3660{
42644cee 3661 const struct qemu_argument *arginfo;
fc9c5412
JS		 3662 int maxarglen;
3663 int maxenvlen;
3664
2e59915d
PB		 3665 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3666 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
fc9c5412
JS		 3667 "\n"
3668 "Options and associated environment variables:\n"
3669 "\n");
3670
63ec54d7
PM		 3671 /* Calculate column widths. We must always have at least enough space
3672 * for the column header.
3673 */
3674 maxarglen = strlen("Argument");
3675 maxenvlen = strlen("Env-variable");
fc9c5412
JS		 3676
3677 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
63ec54d7
PM		 3678 int arglen = strlen(arginfo->argv);
3679 if (arginfo->has_arg) {
3680 arglen += strlen(arginfo->example) + 1;
3681 }
fc9c5412
JS		 3682 if (strlen(arginfo->env) > maxenvlen) {
3683 maxenvlen = strlen(arginfo->env);
3684 }
63ec54d7
PM		 3685 if (arglen > maxarglen) {
3686 maxarglen = arglen;
fc9c5412
JS		 3687 }
3688 }
3689
63ec54d7
PM		 3690 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3691 maxenvlen, "Env-variable");
fc9c5412
JS		 3692
3693 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3694 if (arginfo->has_arg) {
3695 printf("-%s %-*s %-*s %s\n", arginfo->argv,
63ec54d7
PM		 3696 (int)(maxarglen - strlen(arginfo->argv) - 1),
3697 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
fc9c5412 3698 } else {
63ec54d7 3699 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
fc9c5412
JS		 3700 maxenvlen, arginfo->env,
3701 arginfo->help);
3702 }
3703 }
3704
3705 printf("\n"
3706 "Defaults:\n"
3707 "QEMU_LD_PREFIX = %s\n"
989b697d 3708 "QEMU_STACK_SIZE = %ld byte\n",
fc9c5412 3709 interp_prefix,
989b697d 3710 guest_stack_size);
fc9c5412
JS		 3711
3712 printf("\n"
3713 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3714 "QEMU_UNSET_ENV environment variables to set and unset\n"
3715 "environment variables for the target process.\n"
3716 "It is possible to provide several variables by separating them\n"
3717 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3718 "provide the -E and -U options multiple times.\n"
3719 "The following lines are equivalent:\n"
3720 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3721 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3722 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3723 "Note that if you provide several changes to a single variable\n"
3724 "the last change will stay in effect.\n");
3725
3726 exit(1);
3727}
3728
3729static int parse_args(int argc, char **argv)
3730{
3731 const char *r;
3732 int optind;
42644cee 3733 const struct qemu_argument *arginfo;
fc9c5412
JS		 3734
3735 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3736 if (arginfo->env == NULL) {
3737 continue;
3738 }
3739
3740 r = getenv(arginfo->env);
3741 if (r != NULL) {
3742 arginfo->handle_opt(r);
3743 }
3744 }
3745
3746 optind = 1;
3747 for (;;) {
3748 if (optind >= argc) {
3749 break;
3750 }
3751 r = argv[optind];
3752 if (r[0] != '-') {
3753 break;
3754 }
3755 optind++;
3756 r++;
3757 if (!strcmp(r, "-")) {
3758 break;
3759 }
3760
3761 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3762 if (!strcmp(r, arginfo->argv)) {
fc9c5412 3763 if (arginfo->has_arg) {
1386d4c0
PM		 3764 if (optind >= argc) {
3765 usage();
3766 }
3767 arginfo->handle_opt(argv[optind]);
fc9c5412 3768 optind++;
1386d4c0
PM		 3769 } else {
3770 arginfo->handle_opt(NULL);
fc9c5412 3771 }
fc9c5412
JS		 3772 break;
3773 }
3774 }
3775
3776 /* no option matched the current argv */
3777 if (arginfo->handle_opt == NULL) {
3778 usage();
3779 }
3780 }
3781
3782 if (optind >= argc) {
3783 usage();
3784 }
3785
3786 filename = argv[optind];
3787 exec_path = argv[optind];
3788
3789 return optind;
3790}
3791
902b3d5c 3792int main(int argc, char **argv, char **envp)
31e31b8a 3793{
01ffc75b 3794 struct target_pt_regs regs1, *regs = &regs1;
31e31b8a 3795 struct image_info info1, *info = &info1;
edf8e2af 3796 struct linux_binprm bprm;
48e15fc2 3797 TaskState *ts;
9349b4f9 3798 CPUArchState *env;
db6b81d4 3799 CPUState *cpu;
586314f2 3800 int optind;
04a6dfeb 3801 char **target_environ, **wrk;
7d8cec95
AJ		 3802 char **target_argv;
3803 int target_argc;
7d8cec95 3804 int i;
fd4d81dd 3805 int ret;
03cfd8fa 3806 int execfd;
b12b6a18 3807
ce008c1f
AF		 3808 module_call_init(MODULE_INIT_QOM);
3809
b6a3e690 3810 qemu_init_auxval(envp);
664d2c44 3811 qemu_cache_utils_init();
902b3d5c 3812
04a6dfeb
AJ		 3813 if ((envlist = envlist_create()) == NULL) {
3814 (void) fprintf(stderr, "Unable to allocate envlist\n");
3815 exit(1);
3816 }
3817
3818 /* add current environment into the list */
3819 for (wrk = environ; *wrk != NULL; wrk++) {
3820 (void) envlist_setenv(envlist, *wrk);
3821 }
3822
703e0e89
RH		 3823 /* Read the stack limit from the kernel. If it's "unlimited",
3824 then we can do little else besides use the default. */
3825 {
3826 struct rlimit lim;
3827 if (getrlimit(RLIMIT_STACK, &lim) == 0
81bbe906
TY		 3828 && lim.rlim_cur != RLIM_INFINITY
3829 && lim.rlim_cur == (target_long)lim.rlim_cur) {
703e0e89
RH		 3830 guest_stack_size = lim.rlim_cur;
3831 }
3832 }
3833
b1f9be31 3834 cpu_model = NULL;
b5ec5ce0 3835#if defined(cpudef_setup)
3836 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3837#endif
3838
fc9c5412 3839 optind = parse_args(argc, argv);
586314f2 3840
31e31b8a 3841 /* Zero out regs */
01ffc75b 3842 memset(regs, 0, sizeof(struct target_pt_regs));
31e31b8a
FB		 3843
3844 /* Zero out image_info */
3845 memset(info, 0, sizeof(struct image_info));
3846
edf8e2af
MW		 3847 memset(&bprm, 0, sizeof (bprm));
3848
74cd30b8
FB		 3849 /* Scan interp_prefix dir for replacement files. */
3850 init_paths(interp_prefix);
3851
4a24a758
PM		 3852 init_qemu_uname_release();
3853
46027c07 3854 if (cpu_model == NULL) {
aaed909a 3855#if defined(TARGET_I386)
46027c07
FB		 3856#ifdef TARGET_X86_64
3857 cpu_model = "qemu64";
3858#else
3859 cpu_model = "qemu32";
3860#endif
aaed909a 3861#elif defined(TARGET_ARM)
088ab16c 3862 cpu_model = "any";
d2fbca94
GX		 3863#elif defined(TARGET_UNICORE32)
3864 cpu_model = "any";
aaed909a
FB		 3865#elif defined(TARGET_M68K)
3866 cpu_model = "any";
3867#elif defined(TARGET_SPARC)
3868#ifdef TARGET_SPARC64
3869 cpu_model = "TI UltraSparc II";
3870#else
3871 cpu_model = "Fujitsu MB86904";
46027c07 3872#endif
aaed909a
FB		 3873#elif defined(TARGET_MIPS)
3874#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
3875 cpu_model = "20Kc";
3876#else
3877 cpu_model = "24Kf";
3878#endif
d962783e
JL		 3879#elif defined TARGET_OPENRISC
3880 cpu_model = "or1200";
aaed909a 3881#elif defined(TARGET_PPC)
7ded4f52 3882#ifdef TARGET_PPC64
f7177937 3883 cpu_model = "970fx";
7ded4f52 3884#else
aaed909a 3885 cpu_model = "750";
7ded4f52 3886#endif
aaed909a
FB		 3887#else
3888 cpu_model = "any";
3889#endif
3890 }
d5ab9713
JK		 3891 tcg_exec_init(0);
3892 cpu_exec_init_all();
83fb7adf
FB		 3893 /* NOTE: we need to init the CPU at this stage to get
3894 qemu_host_page_size */
aaed909a
FB		 3895 env = cpu_init(cpu_model);
3896 if (!env) {
3897 fprintf(stderr, "Unable to find CPU definition\n");
3898 exit(1);
3899 }
db6b81d4 3900 cpu = ENV_GET_CPU(env);
0ac46af3 3901 cpu_reset(cpu);
b55a37c9 3902
db6b81d4 3903 thread_cpu = cpu;
3b46e624 3904
b6741956
FB		 3905 if (getenv("QEMU_STRACE")) {
3906 do_strace = 1;
b92c47c1
TS		 3907 }
3908
04a6dfeb
AJ		 3909 target_environ = envlist_to_environ(envlist, NULL);
3910 envlist_free(envlist);
b12b6a18 3911
379f6698
PB		 3912#if defined(CONFIG_USE_GUEST_BASE)
3913 /*
3914 * Now that page sizes are configured in cpu_init() we can do
3915 * proper page alignment for guest_base.
3916 */
3917 guest_base = HOST_PAGE_ALIGN(guest_base);
68a1c816 3918
806d1021
MI		 3919 if (reserved_va || have_guest_base) {
3920 guest_base = init_guest_space(guest_base, reserved_va, 0,
3921 have_guest_base);
3922 if (guest_base == (unsigned long)-1) {
097b8cb8
PM		 3923 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
3924 "space for use as guest address space (check your virtual "
3925 "memory ulimit setting or reserve less using -R option)\n",
3926 reserved_va);
68a1c816
PB		 3927 exit(1);
3928 }
97cc7560 3929
806d1021
MI		 3930 if (reserved_va) {
3931 mmap_next_start = reserved_va;
97cc7560
DDAG		 3932 }
3933 }
14f24e14 3934#endif /* CONFIG_USE_GUEST_BASE */
379f6698
PB		 3935
3936 /*
3937 * Read in mmap_min_addr kernel parameter. This value is used
3938 * When loading the ELF image to determine whether guest_base
14f24e14 3939 * is needed. It is also used in mmap_find_vma.
379f6698 3940 */
14f24e14 3941 {
379f6698
PB		 3942 FILE *fp;
3943
3944 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
3945 unsigned long tmp;
3946 if (fscanf(fp, "%lu", &tmp) == 1) {
3947 mmap_min_addr = tmp;
3948 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
3949 }
3950 fclose(fp);
3951 }
3952 }
379f6698 3953
7d8cec95
AJ		 3954 /*
3955 * Prepare copy of argv vector for target.
3956 */
3957 target_argc = argc - optind;
3958 target_argv = calloc(target_argc + 1, sizeof (char *));
3959 if (target_argv == NULL) {
3960 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
3961 exit(1);
3962 }
3963
3964 /*
3965 * If argv0 is specified (using '-0' switch) we replace
3966 * argv[0] pointer with the given one.
3967 */
3968 i = 0;
3969 if (argv0 != NULL) {
3970 target_argv[i++] = strdup(argv0);
3971 }
3972 for (; i < target_argc; i++) {
3973 target_argv[i] = strdup(argv[optind + i]);
3974 }
3975 target_argv[target_argc] = NULL;
3976
7267c094 3977 ts = g_malloc0 (sizeof(TaskState));
edf8e2af
MW		 3978 init_task_state(ts);
3979 /* build Task State */
3980 ts->info = info;
3981 ts->bprm = &bprm;
3982 env->opaque = ts;
3983 task_settid(ts);
3984
0b959cf5
RH		 3985 execfd = qemu_getauxval(AT_EXECFD);
3986 if (execfd == 0) {
03cfd8fa 3987 execfd = open(filename, O_RDONLY);
0b959cf5
RH		 3988 if (execfd < 0) {
3989 printf("Error while loading %s: %s\n", filename, strerror(errno));
3990 _exit(1);
3991 }
03cfd8fa
LV		 3992 }
3993
3994 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
fd4d81dd
AP		 3995 info, &bprm);
3996 if (ret != 0) {
885c1d10 3997 printf("Error while loading %s: %s\n", filename, strerror(-ret));
b12b6a18
TS		 3998 _exit(1);
3999 }
4000
4001 for (wrk = target_environ; *wrk; wrk++) {
4002 free(*wrk);
31e31b8a 4003 }
3b46e624 4004
b12b6a18
TS		 4005 free(target_environ);
4006
2e77eac6 4007 if (qemu_log_enabled()) {
379f6698
PB		 4008#if defined(CONFIG_USE_GUEST_BASE)
4009 qemu_log("guest_base 0x%lx\n", guest_base);
4010#endif
2e77eac6
BS		 4011 log_page_dump();
4012
4013 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4014 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4015 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4016 info->start_code);
4017 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4018 info->start_data);
4019 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4020 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4021 info->start_stack);
4022 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4023 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4024 }
31e31b8a 4025
53a5960a 4026 target_set_brk(info->brk);
31e31b8a 4027 syscall_init();
66fb9763 4028 signal_init();
31e31b8a 4029
9002ec79
RH		 4030#if defined(CONFIG_USE_GUEST_BASE)
4031 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4032 generating the prologue until now so that the prologue can take
4033 the real value of GUEST_BASE into account. */
4034 tcg_prologue_init(&tcg_ctx);
4035#endif
4036
b346ff46 4037#if defined(TARGET_I386)
2e255c6b
FB		 4038 cpu_x86_set_cpl(env, 3);
4039
3802ce26 4040 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
1bde465e 4041 env->hflags |= HF_PE_MASK;
0514ef2f 4042 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
1bde465e
FB		 4043 env->cr[4] |= CR4_OSFXSR_MASK;
4044 env->hflags |= HF_OSFXSR_MASK;
4045 }
d2fd1af7 4046#ifndef TARGET_ABI32
4dbc422b 4047 /* enable 64 bit mode if possible */
0514ef2f 4048 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4dbc422b
FB		 4049 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4050 exit(1);
4051 }
d2fd1af7 4052 env->cr[4] |= CR4_PAE_MASK;
4dbc422b 4053 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
d2fd1af7
FB		 4054 env->hflags |= HF_LMA_MASK;
4055#endif
1bde465e 4056
415e561f
FB		 4057 /* flags setup : we activate the IRQs by default as in user mode */
4058 env->eflags |= IF_MASK;
3b46e624 4059
6dbad63e 4060 /* linux register setup */
d2fd1af7 4061#ifndef TARGET_ABI32
84409ddb
JM		 4062 env->regs[R_EAX] = regs->rax;
4063 env->regs[R_EBX] = regs->rbx;
4064 env->regs[R_ECX] = regs->rcx;
4065 env->regs[R_EDX] = regs->rdx;
4066 env->regs[R_ESI] = regs->rsi;
4067 env->regs[R_EDI] = regs->rdi;
4068 env->regs[R_EBP] = regs->rbp;
4069 env->regs[R_ESP] = regs->rsp;
4070 env->eip = regs->rip;
4071#else
0ecfa993
FB		 4072 env->regs[R_EAX] = regs->eax;
4073 env->regs[R_EBX] = regs->ebx;
4074 env->regs[R_ECX] = regs->ecx;
4075 env->regs[R_EDX] = regs->edx;
4076 env->regs[R_ESI] = regs->esi;
4077 env->regs[R_EDI] = regs->edi;
4078 env->regs[R_EBP] = regs->ebp;
4079 env->regs[R_ESP] = regs->esp;
dab2ed99 4080 env->eip = regs->eip;
84409ddb 4081#endif
31e31b8a 4082
f4beb510 4083 /* linux interrupt setup */
e441570f
AZ		 4084#ifndef TARGET_ABI32
4085 env->idt.limit = 511;
4086#else
4087 env->idt.limit = 255;
4088#endif
4089 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4090 PROT_READ|PROT_WRITE,
4091 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4092 idt_table = g2h(env->idt.base);
f4beb510
FB		 4093 set_idt(0, 0);
4094 set_idt(1, 0);
4095 set_idt(2, 0);
4096 set_idt(3, 3);
4097 set_idt(4, 3);
ec95da6c 4098 set_idt(5, 0);
f4beb510
FB		 4099 set_idt(6, 0);
4100 set_idt(7, 0);
4101 set_idt(8, 0);
4102 set_idt(9, 0);
4103 set_idt(10, 0);
4104 set_idt(11, 0);
4105 set_idt(12, 0);
4106 set_idt(13, 0);
4107 set_idt(14, 0);
4108 set_idt(15, 0);
4109 set_idt(16, 0);
4110 set_idt(17, 0);
4111 set_idt(18, 0);
4112 set_idt(19, 0);
4113 set_idt(0x80, 3);
4114
6dbad63e 4115 /* linux segment setup */
8d18e893
FB		 4116 {
4117 uint64_t *gdt_table;
e441570f
AZ		 4118 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4119 PROT_READ|PROT_WRITE,
4120 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
8d18e893 4121 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
e441570f 4122 gdt_table = g2h(env->gdt.base);
d2fd1af7 4123#ifdef TARGET_ABI32
8d18e893
FB		 4124 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4125 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4126 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
d2fd1af7
FB		 4127#else
4128 /* 64 bit code segment */
4129 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4130 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4131 DESC_L_MASK |
4132 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4133#endif
8d18e893
FB		 4134 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4135 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4136 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4137 }
6dbad63e 4138 cpu_x86_load_seg(env, R_CS, __USER_CS);
d2fd1af7
FB		 4139 cpu_x86_load_seg(env, R_SS, __USER_DS);
4140#ifdef TARGET_ABI32
6dbad63e
FB		 4141 cpu_x86_load_seg(env, R_DS, __USER_DS);
4142 cpu_x86_load_seg(env, R_ES, __USER_DS);
6dbad63e
FB		 4143 cpu_x86_load_seg(env, R_FS, __USER_DS);
4144 cpu_x86_load_seg(env, R_GS, __USER_DS);
d6eb40f6
TS		 4145 /* This hack makes Wine work... */
4146 env->segs[R_FS].selector = 0;
d2fd1af7
FB		 4147#else
4148 cpu_x86_load_seg(env, R_DS, 0);
4149 cpu_x86_load_seg(env, R_ES, 0);
4150 cpu_x86_load_seg(env, R_FS, 0);
4151 cpu_x86_load_seg(env, R_GS, 0);
4152#endif
99033cae
AG		 4153#elif defined(TARGET_AARCH64)
4154 {
4155 int i;
4156
4157 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4158 fprintf(stderr,
4159 "The selected ARM CPU does not support 64 bit mode\n");
4160 exit(1);
4161 }
4162
4163 for (i = 0; i < 31; i++) {
4164 env->xregs[i] = regs->regs[i];
4165 }
4166 env->pc = regs->pc;
4167 env->xregs[31] = regs->sp;
4168 }
b346ff46
FB		 4169#elif defined(TARGET_ARM)
4170 {
4171 int i;
b5ff1b31 4172 cpsr_write(env, regs->uregs[16], 0xffffffff);
b346ff46
FB		 4173 for(i = 0; i < 16; i++) {
4174 env->regs[i] = regs->uregs[i];
4175 }
d8fd2954
PB		 4176 /* Enable BE8. */
4177 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4178 && (info->elf_flags & EF_ARM_BE8)) {
4179 env->bswap_code = 1;
4180 }
b346ff46 4181 }
d2fbca94
GX		 4182#elif defined(TARGET_UNICORE32)
4183 {
4184 int i;
4185 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4186 for (i = 0; i < 32; i++) {
4187 env->regs[i] = regs->uregs[i];
4188 }
4189 }
93ac68bc 4190#elif defined(TARGET_SPARC)
060366c5
FB		 4191 {
4192 int i;
4193 env->pc = regs->pc;
4194 env->npc = regs->npc;
4195 env->y = regs->y;
4196 for(i = 0; i < 8; i++)
4197 env->gregs[i] = regs->u_regs[i];
4198 for(i = 0; i < 8; i++)
4199 env->regwptr[i] = regs->u_regs[i + 8];
4200 }
67867308
FB		 4201#elif defined(TARGET_PPC)
4202 {
4203 int i;
3fc6c082 4204
0411a972
JM		 4205#if defined(TARGET_PPC64)
4206#if defined(TARGET_ABI32)
4207 env->msr &= ~((target_ulong)1 << MSR_SF);
e85e7c6e 4208#else
0411a972
JM		 4209 env->msr |= (target_ulong)1 << MSR_SF;
4210#endif
84409ddb 4211#endif
67867308
FB		 4212 env->nip = regs->nip;
4213 for(i = 0; i < 32; i++) {
4214 env->gpr[i] = regs->gpr[i];
4215 }
4216 }
e6e5906b
PB		 4217#elif defined(TARGET_M68K)
4218 {
e6e5906b
PB		 4219 env->pc = regs->pc;
4220 env->dregs[0] = regs->d0;
4221 env->dregs[1] = regs->d1;
4222 env->dregs[2] = regs->d2;
4223 env->dregs[3] = regs->d3;
4224 env->dregs[4] = regs->d4;
4225 env->dregs[5] = regs->d5;
4226 env->dregs[6] = regs->d6;
4227 env->dregs[7] = regs->d7;
4228 env->aregs[0] = regs->a0;
4229 env->aregs[1] = regs->a1;
4230 env->aregs[2] = regs->a2;
4231 env->aregs[3] = regs->a3;
4232 env->aregs[4] = regs->a4;
4233 env->aregs[5] = regs->a5;
4234 env->aregs[6] = regs->a6;
4235 env->aregs[7] = regs->usp;
4236 env->sr = regs->sr;
4237 ts->sim_syscalls = 1;
4238 }
b779e29e
EI		 4239#elif defined(TARGET_MICROBLAZE)
4240 {
4241 env->regs[0] = regs->r0;
4242 env->regs[1] = regs->r1;
4243 env->regs[2] = regs->r2;
4244 env->regs[3] = regs->r3;
4245 env->regs[4] = regs->r4;
4246 env->regs[5] = regs->r5;
4247 env->regs[6] = regs->r6;
4248 env->regs[7] = regs->r7;
4249 env->regs[8] = regs->r8;
4250 env->regs[9] = regs->r9;
4251 env->regs[10] = regs->r10;
4252 env->regs[11] = regs->r11;
4253 env->regs[12] = regs->r12;
4254 env->regs[13] = regs->r13;
4255 env->regs[14] = regs->r14;
4256 env->regs[15] = regs->r15;
4257 env->regs[16] = regs->r16;
4258 env->regs[17] = regs->r17;
4259 env->regs[18] = regs->r18;
4260 env->regs[19] = regs->r19;
4261 env->regs[20] = regs->r20;
4262 env->regs[21] = regs->r21;
4263 env->regs[22] = regs->r22;
4264 env->regs[23] = regs->r23;
4265 env->regs[24] = regs->r24;
4266 env->regs[25] = regs->r25;
4267 env->regs[26] = regs->r26;
4268 env->regs[27] = regs->r27;
4269 env->regs[28] = regs->r28;
4270 env->regs[29] = regs->r29;
4271 env->regs[30] = regs->r30;
4272 env->regs[31] = regs->r31;
4273 env->sregs[SR_PC] = regs->pc;
4274 }
048f6b4d
FB		 4275#elif defined(TARGET_MIPS)
4276 {
4277 int i;
4278
4279 for(i = 0; i < 32; i++) {
b5dc7732 4280 env->active_tc.gpr[i] = regs->regs[i];
048f6b4d 4281 }
0fddbbf2
NF		 4282 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4283 if (regs->cp0_epc & 1) {
4284 env->hflags |= MIPS_HFLAG_M16;
4285 }
048f6b4d 4286 }
d962783e
JL		 4287#elif defined(TARGET_OPENRISC)
4288 {
4289 int i;
4290
4291 for (i = 0; i < 32; i++) {
4292 env->gpr[i] = regs->gpr[i];
4293 }
4294
4295 env->sr = regs->sr;
4296 env->pc = regs->pc;
4297 }
fdf9b3e8
FB		 4298#elif defined(TARGET_SH4)
4299 {
4300 int i;
4301
4302 for(i = 0; i < 16; i++) {
4303 env->gregs[i] = regs->regs[i];
4304 }
4305 env->pc = regs->pc;
4306 }
7a3148a9
JM		 4307#elif defined(TARGET_ALPHA)
4308 {
4309 int i;
4310
4311 for(i = 0; i < 28; i++) {
992f48a0 4312 env->ir[i] = ((abi_ulong *)regs)[i];
7a3148a9 4313 }
dad081ee 4314 env->ir[IR_SP] = regs->usp;
7a3148a9 4315 env->pc = regs->pc;
7a3148a9 4316 }
48733d19
TS		 4317#elif defined(TARGET_CRIS)
4318 {
4319 env->regs[0] = regs->r0;
4320 env->regs[1] = regs->r1;
4321 env->regs[2] = regs->r2;
4322 env->regs[3] = regs->r3;
4323 env->regs[4] = regs->r4;
4324 env->regs[5] = regs->r5;
4325 env->regs[6] = regs->r6;
4326 env->regs[7] = regs->r7;
4327 env->regs[8] = regs->r8;
4328 env->regs[9] = regs->r9;
4329 env->regs[10] = regs->r10;
4330 env->regs[11] = regs->r11;
4331 env->regs[12] = regs->r12;
4332 env->regs[13] = regs->r13;
4333 env->regs[14] = info->start_stack;
4334 env->regs[15] = regs->acr;
4335 env->pc = regs->erp;
4336 }
a4c075f1
UH		 4337#elif defined(TARGET_S390X)
4338 {
4339 int i;
4340 for (i = 0; i < 16; i++) {
4341 env->regs[i] = regs->gprs[i];
4342 }
4343 env->psw.mask = regs->psw.mask;
4344 env->psw.addr = regs->psw.addr;
4345 }
b346ff46
FB		 4346#else
4347#error unsupported target CPU
4348#endif
31e31b8a 4349
d2fbca94 4350#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
a87295e8
PB		 4351 ts->stack_base = info->start_stack;
4352 ts->heap_base = info->brk;
4353 /* This will be filled in on the first SYS_HEAPINFO call. */
4354 ts->heap_limit = 0;
4355#endif
4356
74c33bed 4357 if (gdbstub_port) {
ff7a981a
PM		 4358 if (gdbserver_start(gdbstub_port) < 0) {
4359 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4360 gdbstub_port);
4361 exit(1);
4362 }
db6b81d4 4363 gdb_handlesig(cpu, 0);
1fddef4b 4364 }
1b6b029e
FB		 4365 cpu_loop(env);
4366 /* never exits */
31e31b8a
FB		 4367 return 0;
4368}
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