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linux-user: Use QemuMutex and QemuCond
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31e31b8a 1/*
93ac68bc 2 * qemu user main
5fafdf24 3 *
68d0f70e 4 * Copyright (c) 2003-2008 Fabrice Bellard
31e31b8a
FB		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
8167ee88 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31e31b8a 18 */
d39594e9 19#include "qemu/osdep.h"
67a1de0d 20#include "qemu-version.h"
edf8e2af 21#include <sys/syscall.h>
703e0e89 22#include <sys/resource.h>
31e31b8a 23
daa76aa4 24#include "qapi/error.h"
3ef693a0 25#include "qemu.h"
f348b6d1 26#include "qemu/path.h"
6533dd6e 27#include "qemu/config-file.h"
f348b6d1
VB		 28#include "qemu/cutils.h"
29#include "qemu/help_option.h"
2b41f10e 30#include "cpu.h"
63c91552 31#include "exec/exec-all.h"
9002ec79 32#include "tcg.h"
1de7afc9
PB		 33#include "qemu/timer.h"
34#include "qemu/envlist.h"
d8fd2954 35#include "elf.h"
508127e2 36#include "exec/log.h"
6533dd6e
LV		 37#include "trace/control.h"
38#include "glib-compat.h"
04a6dfeb 39
d088d664
AJ		 40char *exec_path;
41
1b530a6d 42int singlestep;
8cb76755
SW		 43static const char *filename;
44static const char *argv0;
45static int gdbstub_port;
46static envlist_t *envlist;
51fb256a 47static const char *cpu_model;
379f6698
PB		 48unsigned long mmap_min_addr;
49unsigned long guest_base;
50int have_guest_base;
120a9848
PB		 51
52#define EXCP_DUMP(env, fmt, ...) \
53do { \
54 CPUState *cs = ENV_GET_CPU(env); \
55 fprintf(stderr, fmt , ## __VA_ARGS__); \
56 cpu_dump_state(cs, stderr, fprintf, 0); \
57 if (qemu_log_separate()) { \
58 qemu_log(fmt, ## __VA_ARGS__); \
59 log_cpu_state(cs, 0); \
60 } \
61} while (0)
62
288e65b9
AG		 63#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
64/*
65 * When running 32-on-64 we should make sure we can fit all of the possible
66 * guest address space into a contiguous chunk of virtual host memory.
67 *
68 * This way we will never overlap with our own libraries or binaries or stack
69 * or anything else that QEMU maps.
70 */
314992b1
AG		 71# ifdef TARGET_MIPS
72/* MIPS only supports 31 bits of virtual address space for user space */
73unsigned long reserved_va = 0x77000000;
74# else
288e65b9 75unsigned long reserved_va = 0xf7000000;
314992b1 76# endif
288e65b9 77#else
68a1c816 78unsigned long reserved_va;
379f6698 79#endif
1b530a6d 80
d03f9c32 81static void usage(int exitcode);
fc9c5412 82
7ee2822c 83static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
e586822a 84const char *qemu_uname_release;
586314f2 85
9de5e440
FB		 86/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
87 we allocate a bigger stack. Need a better solution, for example
88 by remapping the process stack directly at the right place */
703e0e89 89unsigned long guest_stack_size = 8 * 1024 * 1024UL;
31e31b8a
FB		 90
91void gemu_log(const char *fmt, ...)
92{
93 va_list ap;
94
95 va_start(ap, fmt);
96 vfprintf(stderr, fmt, ap);
97 va_end(ap);
98}
99
8fcd3692 100#if defined(TARGET_I386)
05390248 101int cpu_get_pic_interrupt(CPUX86State *env)
92ccca6a
FB		 102{
103 return -1;
104}
8fcd3692 105#endif
92ccca6a 106
d5975363
PB		 107/***********************************************************/
108/* Helper routines for implementing atomic operations. */
109
110/* To implement exclusive operations we force all cpus to syncronise.
111 We don't require a full sync, only that no cpus are executing guest code.
112 The alternative is to map target atomic ops onto host equivalents,
113 which requires quite a lot of per host/target work. */
959f593c
SF		 114static QemuMutex cpu_list_lock;
115static QemuMutex exclusive_lock;
116static QemuCond exclusive_cond;
117static QemuCond exclusive_resume;
d5975363
PB		 118static int pending_cpus;
119
959f593c
SF		 120void qemu_init_cpu_loop(void)
121{
122 qemu_mutex_init(&cpu_list_lock);
123 qemu_mutex_init(&exclusive_lock);
124 qemu_cond_init(&exclusive_cond);
125 qemu_cond_init(&exclusive_resume);
126}
127
d5975363
PB		 128/* Make sure everything is in a consistent state for calling fork(). */
129void fork_start(void)
130{
677ef623 131 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
959f593c 132 qemu_mutex_lock(&exclusive_lock);
d032d1b4 133 mmap_fork_start();
d5975363
PB		 134}
135
136void fork_end(int child)
137{
d032d1b4 138 mmap_fork_end(child);
d5975363 139 if (child) {
bdc44640 140 CPUState *cpu, *next_cpu;
d5975363
PB		 141 /* Child processes created by fork() only have a single thread.
142 Discard information about the parent threads. */
bdc44640
AF		 143 CPU_FOREACH_SAFE(cpu, next_cpu) {
144 if (cpu != thread_cpu) {
014628a7 145 QTAILQ_REMOVE(&cpus, cpu, node);
bdc44640
AF		 146 }
147 }
d5975363 148 pending_cpus = 0;
959f593c
SF		 149 qemu_mutex_init(&exclusive_lock);
150 qemu_mutex_init(&cpu_list_lock);
151 qemu_cond_init(&exclusive_cond);
152 qemu_cond_init(&exclusive_resume);
677ef623 153 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
f7ec7f7b 154 gdbserver_fork(thread_cpu);
d5975363 155 } else {
959f593c 156 qemu_mutex_unlock(&exclusive_lock);
677ef623 157 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 158 }
d5975363
PB		 159}
160
161/* Wait for pending exclusive operations to complete. The exclusive lock
162 must be held. */
163static inline void exclusive_idle(void)
164{
165 while (pending_cpus) {
959f593c 166 qemu_cond_wait(&exclusive_resume, &exclusive_lock);
d5975363
PB		 167 }
168}
169
170/* Start an exclusive operation.
8642c1b8 171 Must only be called from outside cpu_exec. */
d5975363
PB		 172static inline void start_exclusive(void)
173{
0315c31c
AF		 174 CPUState *other_cpu;
175
959f593c 176 qemu_mutex_lock(&exclusive_lock);
d5975363
PB		 177 exclusive_idle();
178
179 pending_cpus = 1;
180 /* Make all other cpus stop executing. */
bdc44640 181 CPU_FOREACH(other_cpu) {
0315c31c 182 if (other_cpu->running) {
d5975363 183 pending_cpus++;
60a3e17a 184 cpu_exit(other_cpu);
d5975363
PB		 185 }
186 }
959f593c
SF		 187 while (pending_cpus > 1) {
188 qemu_cond_wait(&exclusive_cond, &exclusive_lock);
d5975363
PB		 189 }
190}
191
192/* Finish an exclusive operation. */
f7e61b22 193static inline void __attribute__((unused)) end_exclusive(void)
d5975363
PB		 194{
195 pending_cpus = 0;
959f593c
SF		 196 qemu_cond_broadcast(&exclusive_resume);
197 qemu_mutex_unlock(&exclusive_lock);
d5975363
PB		 198}
199
200/* Wait for exclusive ops to finish, and begin cpu execution. */
0315c31c 201static inline void cpu_exec_start(CPUState *cpu)
d5975363 202{
959f593c 203 qemu_mutex_lock(&exclusive_lock);
d5975363 204 exclusive_idle();
0315c31c 205 cpu->running = true;
959f593c 206 qemu_mutex_unlock(&exclusive_lock);
d5975363
PB		 207}
208
209/* Mark cpu as not executing, and release pending exclusive ops. */
0315c31c 210static inline void cpu_exec_end(CPUState *cpu)
d5975363 211{
959f593c 212 qemu_mutex_lock(&exclusive_lock);
0315c31c 213 cpu->running = false;
d5975363
PB		 214 if (pending_cpus > 1) {
215 pending_cpus--;
216 if (pending_cpus == 1) {
959f593c 217 qemu_cond_signal(&exclusive_cond);
d5975363
PB		 218 }
219 }
220 exclusive_idle();
959f593c 221 qemu_mutex_unlock(&exclusive_lock);
d5975363 222}
c2764719
PB		 223
224void cpu_list_lock(void)
225{
959f593c 226 qemu_mutex_lock(&cpu_list_lock);
c2764719
PB		 227}
228
229void cpu_list_unlock(void)
230{
959f593c 231 qemu_mutex_unlock(&cpu_list_lock);
c2764719 232}
d5975363
PB		 233
234
a541f297
FB		 235#ifdef TARGET_I386
236/***********************************************************/
237/* CPUX86 core interface */
238
28ab0e2e
FB		 239uint64_t cpu_get_tsc(CPUX86State *env)
240{
4a7428c5 241 return cpu_get_host_ticks();
28ab0e2e
FB		 242}
243
5fafdf24 244static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
f4beb510 245 int flags)
6dbad63e 246{
f4beb510 247 unsigned int e1, e2;
53a5960a 248 uint32_t *p;
6dbad63e
FB		 249 e1 = (addr << 16) | (limit & 0xffff);
250 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
f4beb510 251 e2 |= flags;
53a5960a 252 p = ptr;
d538e8f5 253 p[0] = tswap32(e1);
254 p[1] = tswap32(e2);
f4beb510
FB		 255}
256
e441570f 257static uint64_t *idt_table;
eb38c52c 258#ifdef TARGET_X86_64
d2fd1af7
FB		 259static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
260 uint64_t addr, unsigned int sel)
f4beb510 261{
4dbc422b 262 uint32_t *p, e1, e2;
f4beb510
FB		 263 e1 = (addr & 0xffff) | (sel << 16);
264 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
53a5960a 265 p = ptr;
4dbc422b
FB		 266 p[0] = tswap32(e1);
267 p[1] = tswap32(e2);
268 p[2] = tswap32(addr >> 32);
269 p[3] = 0;
6dbad63e 270}
d2fd1af7
FB		 271/* only dpl matters as we do only user space emulation */
272static void set_idt(int n, unsigned int dpl)
273{
274 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
275}
276#else
d2fd1af7
FB		 277static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
278 uint32_t addr, unsigned int sel)
279{
4dbc422b 280 uint32_t *p, e1, e2;
d2fd1af7
FB		 281 e1 = (addr & 0xffff) | (sel << 16);
282 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
283 p = ptr;
4dbc422b
FB		 284 p[0] = tswap32(e1);
285 p[1] = tswap32(e2);
d2fd1af7
FB		 286}
287
f4beb510
FB		 288/* only dpl matters as we do only user space emulation */
289static void set_idt(int n, unsigned int dpl)
290{
291 set_gate(idt_table + n, 0, dpl, 0, 0);
292}
d2fd1af7 293#endif
31e31b8a 294
89e957e7 295void cpu_loop(CPUX86State *env)
1b6b029e 296{
db6b81d4 297 CPUState *cs = CPU(x86_env_get_cpu(env));
bc8a22cc 298 int trapnr;
992f48a0 299 abi_ulong pc;
0284b03b 300 abi_ulong ret;
c227f099 301 target_siginfo_t info;
851e67a1 302
1b6b029e 303 for(;;) {
b040bc9c 304 cpu_exec_start(cs);
8642c1b8 305 trapnr = cpu_exec(cs);
b040bc9c 306 cpu_exec_end(cs);
bc8a22cc 307 switch(trapnr) {
f4beb510 308 case 0x80:
d2fd1af7 309 /* linux syscall from int $0x80 */
0284b03b
TB		 310 ret = do_syscall(env,
311 env->regs[R_EAX],
312 env->regs[R_EBX],
313 env->regs[R_ECX],
314 env->regs[R_EDX],
315 env->regs[R_ESI],
316 env->regs[R_EDI],
317 env->regs[R_EBP],
318 0, 0);
319 if (ret == -TARGET_ERESTARTSYS) {
320 env->eip -= 2;
321 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
322 env->regs[R_EAX] = ret;
323 }
f4beb510 324 break;
d2fd1af7
FB		 325#ifndef TARGET_ABI32
326 case EXCP_SYSCALL:
5ba18547 327 /* linux syscall from syscall instruction */
0284b03b
TB		 328 ret = do_syscall(env,
329 env->regs[R_EAX],
330 env->regs[R_EDI],
331 env->regs[R_ESI],
332 env->regs[R_EDX],
333 env->regs[10],
334 env->regs[8],
335 env->regs[9],
336 0, 0);
337 if (ret == -TARGET_ERESTARTSYS) {
338 env->eip -= 2;
339 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
340 env->regs[R_EAX] = ret;
341 }
d2fd1af7
FB		 342 break;
343#endif
f4beb510
FB		 344 case EXCP0B_NOSEG:
345 case EXCP0C_STACK:
a86b3c64 346 info.si_signo = TARGET_SIGBUS;
f4beb510
FB		 347 info.si_errno = 0;
348 info.si_code = TARGET_SI_KERNEL;
349 info._sifields._sigfault._addr = 0;
9d2803f7 350 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
f4beb510 351 break;
1b6b029e 352 case EXCP0D_GPF:
d2fd1af7 353 /* XXX: potential problem if ABI32 */
84409ddb 354#ifndef TARGET_X86_64
851e67a1 355 if (env->eflags & VM_MASK) {
89e957e7 356 handle_vm86_fault(env);
84409ddb
JM		 357 } else
358#endif
359 {
a86b3c64 360 info.si_signo = TARGET_SIGSEGV;
f4beb510
FB		 361 info.si_errno = 0;
362 info.si_code = TARGET_SI_KERNEL;
363 info._sifields._sigfault._addr = 0;
9d2803f7 364 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1b6b029e
FB		 365 }
366 break;
b689bc57 367 case EXCP0E_PAGE:
a86b3c64 368 info.si_signo = TARGET_SIGSEGV;
b689bc57
FB		 369 info.si_errno = 0;
370 if (!(env->error_code & 1))
371 info.si_code = TARGET_SEGV_MAPERR;
372 else
373 info.si_code = TARGET_SEGV_ACCERR;
970a87a6 374 info._sifields._sigfault._addr = env->cr[2];
9d2803f7 375 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
b689bc57 376 break;
9de5e440 377 case EXCP00_DIVZ:
84409ddb 378#ifndef TARGET_X86_64
bc8a22cc 379 if (env->eflags & VM_MASK) {
447db213 380 handle_vm86_trap(env, trapnr);
84409ddb
JM		 381 } else
382#endif
383 {
bc8a22cc 384 /* division by zero */
a86b3c64 385 info.si_signo = TARGET_SIGFPE;
bc8a22cc
FB		 386 info.si_errno = 0;
387 info.si_code = TARGET_FPE_INTDIV;
388 info._sifields._sigfault._addr = env->eip;
9d2803f7 389 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
bc8a22cc 390 }
9de5e440 391 break;
01df040b 392 case EXCP01_DB:
447db213 393 case EXCP03_INT3:
84409ddb 394#ifndef TARGET_X86_64
447db213
FB		 395 if (env->eflags & VM_MASK) {
396 handle_vm86_trap(env, trapnr);
84409ddb
JM		 397 } else
398#endif
399 {
a86b3c64 400 info.si_signo = TARGET_SIGTRAP;
447db213 401 info.si_errno = 0;
01df040b 402 if (trapnr == EXCP01_DB) {
447db213
FB		 403 info.si_code = TARGET_TRAP_BRKPT;
404 info._sifields._sigfault._addr = env->eip;
405 } else {
406 info.si_code = TARGET_SI_KERNEL;
407 info._sifields._sigfault._addr = 0;
408 }
9d2803f7 409 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
447db213
FB		 410 }
411 break;
9de5e440
FB		 412 case EXCP04_INTO:
413 case EXCP05_BOUND:
84409ddb 414#ifndef TARGET_X86_64
bc8a22cc 415 if (env->eflags & VM_MASK) {
447db213 416 handle_vm86_trap(env, trapnr);
84409ddb
JM		 417 } else
418#endif
419 {
a86b3c64 420 info.si_signo = TARGET_SIGSEGV;
bc8a22cc 421 info.si_errno = 0;
b689bc57 422 info.si_code = TARGET_SI_KERNEL;
bc8a22cc 423 info._sifields._sigfault._addr = 0;
9d2803f7 424 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
bc8a22cc 425 }
9de5e440
FB		 426 break;
427 case EXCP06_ILLOP:
a86b3c64 428 info.si_signo = TARGET_SIGILL;
9de5e440
FB		 429 info.si_errno = 0;
430 info.si_code = TARGET_ILL_ILLOPN;
431 info._sifields._sigfault._addr = env->eip;
9d2803f7 432 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
9de5e440
FB		 433 break;
434 case EXCP_INTERRUPT:
435 /* just indicate that signals should be handled asap */
436 break;
1fddef4b
FB		 437 case EXCP_DEBUG:
438 {
439 int sig;
440
db6b81d4 441 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 442 if (sig)
443 {
444 info.si_signo = sig;
445 info.si_errno = 0;
446 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 447 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1fddef4b
FB		 448 }
449 }
450 break;
1b6b029e 451 default:
970a87a6 452 pc = env->segs[R_CS].base + env->eip;
120a9848
PB		 453 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
454 (long)pc, trapnr);
1b6b029e
FB		 455 abort();
456 }
66fb9763 457 process_pending_signals(env);
1b6b029e
FB		 458 }
459}
b346ff46
FB		 460#endif
461
462#ifdef TARGET_ARM
463
49017bd8 464#define get_user_code_u32(x, gaddr, env) \
d8fd2954 465 ({ abi_long __r = get_user_u32((x), (gaddr)); \
f9fd40eb 466 if (!__r && bswap_code(arm_sctlr_b(env))) { \
d8fd2954
PB		 467 (x) = bswap32(x); \
468 } \
469 __r; \
470 })
471
49017bd8 472#define get_user_code_u16(x, gaddr, env) \
d8fd2954 473 ({ abi_long __r = get_user_u16((x), (gaddr)); \
f9fd40eb 474 if (!__r && bswap_code(arm_sctlr_b(env))) { \
d8fd2954
PB		 475 (x) = bswap16(x); \
476 } \
477 __r; \
478 })
479
c3ae85fc
PB		 480#define get_user_data_u32(x, gaddr, env) \
481 ({ abi_long __r = get_user_u32((x), (gaddr)); \
482 if (!__r && arm_cpu_bswap_data(env)) { \
483 (x) = bswap32(x); \
484 } \
485 __r; \
486 })
487
488#define get_user_data_u16(x, gaddr, env) \
489 ({ abi_long __r = get_user_u16((x), (gaddr)); \
490 if (!__r && arm_cpu_bswap_data(env)) { \
491 (x) = bswap16(x); \
492 } \
493 __r; \
494 })
495
496#define put_user_data_u32(x, gaddr, env) \
497 ({ typeof(x) __x = (x); \
498 if (arm_cpu_bswap_data(env)) { \
499 __x = bswap32(__x); \
500 } \
501 put_user_u32(__x, (gaddr)); \
502 })
503
504#define put_user_data_u16(x, gaddr, env) \
505 ({ typeof(x) __x = (x); \
506 if (arm_cpu_bswap_data(env)) { \
507 __x = bswap16(__x); \
508 } \
509 put_user_u16(__x, (gaddr)); \
510 })
511
1861c454
PM		 512#ifdef TARGET_ABI32
513/* Commpage handling -- there is no commpage for AArch64 */
514
97cc7560
DDAG		 515/*
516 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
517 * Input:
518 * r0 = pointer to oldval
519 * r1 = pointer to newval
520 * r2 = pointer to target value
521 *
522 * Output:
523 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
524 * C set if *ptr was changed, clear if no exchange happened
525 *
526 * Note segv's in kernel helpers are a bit tricky, we can set the
527 * data address sensibly but the PC address is just the entry point.
528 */
529static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
530{
531 uint64_t oldval, newval, val;
532 uint32_t addr, cpsr;
533 target_siginfo_t info;
534
535 /* Based on the 32 bit code in do_kernel_trap */
536
537 /* XXX: This only works between threads, not between processes.
538 It's probably possible to implement this with native host
539 operations. However things like ldrex/strex are much harder so
540 there's not much point trying. */
541 start_exclusive();
542 cpsr = cpsr_read(env);
543 addr = env->regs[2];
544
545 if (get_user_u64(oldval, env->regs[0])) {
abf1172f 546 env->exception.vaddress = env->regs[0];
97cc7560
DDAG		 547 goto segv;
548 };
549
550 if (get_user_u64(newval, env->regs[1])) {
abf1172f 551 env->exception.vaddress = env->regs[1];
97cc7560
DDAG		 552 goto segv;
553 };
554
555 if (get_user_u64(val, addr)) {
abf1172f 556 env->exception.vaddress = addr;
97cc7560
DDAG		 557 goto segv;
558 }
559
560 if (val == oldval) {
561 val = newval;
562
563 if (put_user_u64(val, addr)) {
abf1172f 564 env->exception.vaddress = addr;
97cc7560
DDAG		 565 goto segv;
566 };
567
568 env->regs[0] = 0;
569 cpsr |= CPSR_C;
570 } else {
571 env->regs[0] = -1;
572 cpsr &= ~CPSR_C;
573 }
50866ba5 574 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
97cc7560
DDAG		 575 end_exclusive();
576 return;
577
578segv:
579 end_exclusive();
580 /* We get the PC of the entry address - which is as good as anything,
581 on a real kernel what you get depends on which mode it uses. */
a86b3c64 582 info.si_signo = TARGET_SIGSEGV;
97cc7560
DDAG		 583 info.si_errno = 0;
584 /* XXX: check env->error_code */
585 info.si_code = TARGET_SEGV_MAPERR;
abf1172f 586 info._sifields._sigfault._addr = env->exception.vaddress;
9d2803f7 587 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
97cc7560
DDAG		 588}
589
fbb4a2e3
PB		 590/* Handle a jump to the kernel code page. */
591static int
592do_kernel_trap(CPUARMState *env)
593{
594 uint32_t addr;
595 uint32_t cpsr;
596 uint32_t val;
597
598 switch (env->regs[15]) {
599 case 0xffff0fa0: /* __kernel_memory_barrier */
600 /* ??? No-op. Will need to do better for SMP. */
601 break;
602 case 0xffff0fc0: /* __kernel_cmpxchg */
d5975363
PB		 603 /* XXX: This only works between threads, not between processes.
604 It's probably possible to implement this with native host
605 operations. However things like ldrex/strex are much harder so
606 there's not much point trying. */
607 start_exclusive();
fbb4a2e3
PB		 608 cpsr = cpsr_read(env);
609 addr = env->regs[2];
610 /* FIXME: This should SEGV if the access fails. */
611 if (get_user_u32(val, addr))
612 val = ~env->regs[0];
613 if (val == env->regs[0]) {
614 val = env->regs[1];
615 /* FIXME: Check for segfaults. */
616 put_user_u32(val, addr);
617 env->regs[0] = 0;
618 cpsr |= CPSR_C;
619 } else {
620 env->regs[0] = -1;
621 cpsr &= ~CPSR_C;
622 }
50866ba5 623 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
d5975363 624 end_exclusive();
fbb4a2e3
PB		 625 break;
626 case 0xffff0fe0: /* __kernel_get_tls */
b8d43285 627 env->regs[0] = cpu_get_tls(env);
fbb4a2e3 628 break;
97cc7560
DDAG		 629 case 0xffff0f60: /* __kernel_cmpxchg64 */
630 arm_kernel_cmpxchg64_helper(env);
631 break;
632
fbb4a2e3
PB		 633 default:
634 return 1;
635 }
636 /* Jump back to the caller. */
637 addr = env->regs[14];
638 if (addr & 1) {
639 env->thumb = 1;
640 addr &= ~1;
641 }
642 env->regs[15] = addr;
643
644 return 0;
645}
646
fa2ef212 647/* Store exclusive handling for AArch32 */
426f5abc
PB		 648static int do_strex(CPUARMState *env)
649{
03d05e2d 650 uint64_t val;
426f5abc
PB		 651 int size;
652 int rc = 1;
653 int segv = 0;
654 uint32_t addr;
655 start_exclusive();
03d05e2d 656 if (env->exclusive_addr != env->exclusive_test) {
426f5abc
PB		 657 goto fail;
658 }
03d05e2d
PM		 659 /* We know we're always AArch32 so the address is in uint32_t range
660 * unless it was the -1 exclusive-monitor-lost value (which won't
661 * match exclusive_test above).
662 */
663 assert(extract64(env->exclusive_addr, 32, 32) == 0);
664 addr = env->exclusive_addr;
426f5abc
PB		 665 size = env->exclusive_info & 0xf;
666 switch (size) {
667 case 0:
668 segv = get_user_u8(val, addr);
669 break;
670 case 1:
c3ae85fc 671 segv = get_user_data_u16(val, addr, env);
426f5abc
PB		 672 break;
673 case 2:
674 case 3:
c3ae85fc 675 segv = get_user_data_u32(val, addr, env);
426f5abc 676 break;
f7001a3b
AJ		 677 default:
678 abort();
426f5abc
PB		 679 }
680 if (segv) {
abf1172f 681 env->exception.vaddress = addr;
426f5abc
PB		 682 goto done;
683 }
426f5abc 684 if (size == 3) {
03d05e2d 685 uint32_t valhi;
c3ae85fc 686 segv = get_user_data_u32(valhi, addr + 4, env);
426f5abc 687 if (segv) {
abf1172f 688 env->exception.vaddress = addr + 4;
426f5abc
PB		 689 goto done;
690 }
c3ae85fc
PB		 691 if (arm_cpu_bswap_data(env)) {
692 val = deposit64((uint64_t)valhi, 32, 32, val);
693 } else {
694 val = deposit64(val, 32, 32, valhi);
695 }
426f5abc 696 }
03d05e2d
PM		 697 if (val != env->exclusive_val) {
698 goto fail;
699 }
700
426f5abc
PB		 701 val = env->regs[(env->exclusive_info >> 8) & 0xf];
702 switch (size) {
703 case 0:
704 segv = put_user_u8(val, addr);
705 break;
706 case 1:
c3ae85fc 707 segv = put_user_data_u16(val, addr, env);
426f5abc
PB		 708 break;
709 case 2:
710 case 3:
c3ae85fc 711 segv = put_user_data_u32(val, addr, env);
426f5abc
PB		 712 break;
713 }
714 if (segv) {
abf1172f 715 env->exception.vaddress = addr;
426f5abc
PB		 716 goto done;
717 }
718 if (size == 3) {
719 val = env->regs[(env->exclusive_info >> 12) & 0xf];
c3ae85fc 720 segv = put_user_data_u32(val, addr + 4, env);
426f5abc 721 if (segv) {
abf1172f 722 env->exception.vaddress = addr + 4;
426f5abc
PB		 723 goto done;
724 }
725 }
726 rc = 0;
727fail:
725b8a69 728 env->regs[15] += 4;
426f5abc
PB		 729 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
730done:
731 end_exclusive();
732 return segv;
733}
734
b346ff46
FB		 735void cpu_loop(CPUARMState *env)
736{
0315c31c 737 CPUState *cs = CPU(arm_env_get_cpu(env));
b346ff46
FB		 738 int trapnr;
739 unsigned int n, insn;
c227f099 740 target_siginfo_t info;
b5ff1b31 741 uint32_t addr;
f0267ef7 742 abi_ulong ret;
3b46e624 743
b346ff46 744 for(;;) {
0315c31c 745 cpu_exec_start(cs);
8642c1b8 746 trapnr = cpu_exec(cs);
0315c31c 747 cpu_exec_end(cs);
b346ff46
FB		 748 switch(trapnr) {
749 case EXCP_UDEF:
c6981055 750 {
0429a971 751 TaskState *ts = cs->opaque;
c6981055 752 uint32_t opcode;
6d9a42be 753 int rc;
c6981055
FB		 754
755 /* we handle the FPU emulation here, as Linux */
756 /* we get the opcode */
2f619698 757 /* FIXME - what to do if get_user() fails? */
49017bd8 758 get_user_code_u32(opcode, env->regs[15], env);
3b46e624 759
6d9a42be
AJ		 760 rc = EmulateAll(opcode, &ts->fpa, env);
761 if (rc == 0) { /* illegal instruction */
a86b3c64 762 info.si_signo = TARGET_SIGILL;
c6981055
FB		 763 info.si_errno = 0;
764 info.si_code = TARGET_ILL_ILLOPN;
765 info._sifields._sigfault._addr = env->regs[15];
9d2803f7 766 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
6d9a42be
AJ		 767 } else if (rc < 0) { /* FP exception */
768 int arm_fpe=0;
769
770 /* translate softfloat flags to FPSR flags */
771 if (-rc & float_flag_invalid)
772 arm_fpe |= BIT_IOC;
773 if (-rc & float_flag_divbyzero)
774 arm_fpe |= BIT_DZC;
775 if (-rc & float_flag_overflow)
776 arm_fpe |= BIT_OFC;
777 if (-rc & float_flag_underflow)
778 arm_fpe |= BIT_UFC;
779 if (-rc & float_flag_inexact)
780 arm_fpe |= BIT_IXC;
781
782 FPSR fpsr = ts->fpa.fpsr;
783 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
784
785 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
a86b3c64 786 info.si_signo = TARGET_SIGFPE;
6d9a42be
AJ		 787 info.si_errno = 0;
788
789 /* ordered by priority, least first */
790 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
791 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
792 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
793 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
794 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
795
796 info._sifields._sigfault._addr = env->regs[15];
9d2803f7 797 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
6d9a42be
AJ		 798 } else {
799 env->regs[15] += 4;
800 }
801
802 /* accumulate unenabled exceptions */
803 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
804 fpsr |= BIT_IXC;
805 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
806 fpsr |= BIT_UFC;
807 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
808 fpsr |= BIT_OFC;
809 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
810 fpsr |= BIT_DZC;
811 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
812 fpsr |= BIT_IOC;
813 ts->fpa.fpsr=fpsr;
814 } else { /* everything OK */
c6981055
FB		 815 /* increment PC */
816 env->regs[15] += 4;
817 }
818 }
b346ff46
FB		 819 break;
820 case EXCP_SWI:
06c949e6 821 case EXCP_BKPT:
b346ff46 822 {
ce4defa0 823 env->eabi = 1;
b346ff46 824 /* system call */
06c949e6
PB		 825 if (trapnr == EXCP_BKPT) {
826 if (env->thumb) {
2f619698 827 /* FIXME - what to do if get_user() fails? */
49017bd8 828 get_user_code_u16(insn, env->regs[15], env);
06c949e6
PB		 829 n = insn & 0xff;
830 env->regs[15] += 2;
831 } else {
2f619698 832 /* FIXME - what to do if get_user() fails? */
49017bd8 833 get_user_code_u32(insn, env->regs[15], env);
06c949e6
PB		 834 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
835 env->regs[15] += 4;
836 }
192c7bd9 837 } else {
06c949e6 838 if (env->thumb) {
2f619698 839 /* FIXME - what to do if get_user() fails? */
49017bd8 840 get_user_code_u16(insn, env->regs[15] - 2, env);
06c949e6
PB		 841 n = insn & 0xff;
842 } else {
2f619698 843 /* FIXME - what to do if get_user() fails? */
49017bd8 844 get_user_code_u32(insn, env->regs[15] - 4, env);
06c949e6
PB		 845 n = insn & 0xffffff;
846 }
192c7bd9
FB		 847 }
848
6f1f31c0 849 if (n == ARM_NR_cacheflush) {
dcfd14b3 850 /* nop */
a4f81979
FB		 851 } else if (n == ARM_NR_semihosting
852 || n == ARM_NR_thumb_semihosting) {
853 env->regs[0] = do_arm_semihosting (env);
3a1363ac 854 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
b346ff46 855 /* linux syscall */
ce4defa0 856 if (env->thumb || n == 0) {
192c7bd9
FB		 857 n = env->regs[7];
858 } else {
859 n -= ARM_SYSCALL_BASE;
ce4defa0 860 env->eabi = 0;
192c7bd9 861 }
fbb4a2e3
PB		 862 if ( n > ARM_NR_BASE) {
863 switch (n) {
864 case ARM_NR_cacheflush:
dcfd14b3 865 /* nop */
fbb4a2e3
PB		 866 break;
867 case ARM_NR_set_tls:
868 cpu_set_tls(env, env->regs[0]);
869 env->regs[0] = 0;
870 break;
d5355087
HL		 871 case ARM_NR_breakpoint:
872 env->regs[15] -= env->thumb ? 2 : 4;
873 goto excp_debug;
fbb4a2e3
PB		 874 default:
875 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
876 n);
877 env->regs[0] = -TARGET_ENOSYS;
878 break;
879 }
880 } else {
f0267ef7
TB		 881 ret = do_syscall(env,
882 n,
883 env->regs[0],
884 env->regs[1],
885 env->regs[2],
886 env->regs[3],
887 env->regs[4],
888 env->regs[5],
889 0, 0);
890 if (ret == -TARGET_ERESTARTSYS) {
891 env->regs[15] -= env->thumb ? 2 : 4;
892 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
893 env->regs[0] = ret;
894 }
fbb4a2e3 895 }
b346ff46
FB		 896 } else {
897 goto error;
898 }
899 }
900 break;
43fff238
FB		 901 case EXCP_INTERRUPT:
902 /* just indicate that signals should be handled asap */
903 break;
abf1172f
PM		 904 case EXCP_STREX:
905 if (!do_strex(env)) {
906 break;
907 }
908 /* fall through for segv */
68016c62
FB		 909 case EXCP_PREFETCH_ABORT:
910 case EXCP_DATA_ABORT:
abf1172f 911 addr = env->exception.vaddress;
68016c62 912 {
a86b3c64 913 info.si_signo = TARGET_SIGSEGV;
68016c62
FB		 914 info.si_errno = 0;
915 /* XXX: check env->error_code */
916 info.si_code = TARGET_SEGV_MAPERR;
b5ff1b31 917 info._sifields._sigfault._addr = addr;
9d2803f7 918 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
68016c62
FB		 919 }
920 break;
1fddef4b 921 case EXCP_DEBUG:
d5355087 922 excp_debug:
1fddef4b
FB		 923 {
924 int sig;
925
db6b81d4 926 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 927 if (sig)
928 {
929 info.si_signo = sig;
930 info.si_errno = 0;
931 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 932 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1fddef4b
FB		 933 }
934 }
935 break;
fbb4a2e3
PB		 936 case EXCP_KERNEL_TRAP:
937 if (do_kernel_trap(env))
938 goto error;
939 break;
f911e0a3
PM		 940 case EXCP_YIELD:
941 /* nothing to do here for user-mode, just resume guest code */
942 break;
b346ff46
FB		 943 default:
944 error:
120a9848 945 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
b346ff46
FB		 946 abort();
947 }
948 process_pending_signals(env);
949 }
950}
951
1861c454
PM		 952#else
953
fa2ef212
MM		 954/*
955 * Handle AArch64 store-release exclusive
956 *
957 * rs = gets the status result of store exclusive
958 * rt = is the register that is stored
959 * rt2 = is the second register store (in STP)
960 *
961 */
962static int do_strex_a64(CPUARMState *env)
963{
964 uint64_t val;
965 int size;
966 bool is_pair;
967 int rc = 1;
968 int segv = 0;
969 uint64_t addr;
970 int rs, rt, rt2;
971
972 start_exclusive();
973 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
974 size = extract32(env->exclusive_info, 0, 2);
975 is_pair = extract32(env->exclusive_info, 2, 1);
976 rs = extract32(env->exclusive_info, 4, 5);
977 rt = extract32(env->exclusive_info, 9, 5);
978 rt2 = extract32(env->exclusive_info, 14, 5);
979
980 addr = env->exclusive_addr;
981
982 if (addr != env->exclusive_test) {
983 goto finish;
984 }
985
986 switch (size) {
987 case 0:
988 segv = get_user_u8(val, addr);
989 break;
990 case 1:
991 segv = get_user_u16(val, addr);
992 break;
993 case 2:
994 segv = get_user_u32(val, addr);
995 break;
996 case 3:
997 segv = get_user_u64(val, addr);
998 break;
999 default:
1000 abort();
1001 }
1002 if (segv) {
abf1172f 1003 env->exception.vaddress = addr;
fa2ef212
MM		 1004 goto error;
1005 }
1006 if (val != env->exclusive_val) {
1007 goto finish;
1008 }
1009 if (is_pair) {
1010 if (size == 2) {
1011 segv = get_user_u32(val, addr + 4);
1012 } else {
1013 segv = get_user_u64(val, addr + 8);
1014 }
1015 if (segv) {
abf1172f 1016 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 1017 goto error;
1018 }
1019 if (val != env->exclusive_high) {
1020 goto finish;
1021 }
1022 }
2ea5a2ca
JG		 1023 /* handle the zero register */
1024 val = rt == 31 ? 0 : env->xregs[rt];
fa2ef212
MM		 1025 switch (size) {
1026 case 0:
1027 segv = put_user_u8(val, addr);
1028 break;
1029 case 1:
1030 segv = put_user_u16(val, addr);
1031 break;
1032 case 2:
1033 segv = put_user_u32(val, addr);
1034 break;
1035 case 3:
1036 segv = put_user_u64(val, addr);
1037 break;
1038 }
1039 if (segv) {
1040 goto error;
1041 }
1042 if (is_pair) {
2ea5a2ca
JG		 1043 /* handle the zero register */
1044 val = rt2 == 31 ? 0 : env->xregs[rt2];
fa2ef212
MM		 1045 if (size == 2) {
1046 segv = put_user_u32(val, addr + 4);
1047 } else {
1048 segv = put_user_u64(val, addr + 8);
1049 }
1050 if (segv) {
abf1172f 1051 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 1052 goto error;
1053 }
1054 }
1055 rc = 0;
1056finish:
1057 env->pc += 4;
1058 /* rs == 31 encodes a write to the ZR, thus throwing away
1059 * the status return. This is rather silly but valid.
1060 */
1061 if (rs < 31) {
1062 env->xregs[rs] = rc;
1063 }
1064error:
1065 /* instruction faulted, PC does not advance */
1066 /* either way a strex releases any exclusive lock we have */
1067 env->exclusive_addr = -1;
1068 end_exclusive();
1069 return segv;
1070}
1071
1861c454
PM		 1072/* AArch64 main loop */
1073void cpu_loop(CPUARMState *env)
1074{
1075 CPUState *cs = CPU(arm_env_get_cpu(env));
1076 int trapnr, sig;
f0267ef7 1077 abi_long ret;
1861c454 1078 target_siginfo_t info;
1861c454
PM		 1079
1080 for (;;) {
1081 cpu_exec_start(cs);
8642c1b8 1082 trapnr = cpu_exec(cs);
1861c454
PM		 1083 cpu_exec_end(cs);
1084
1085 switch (trapnr) {
1086 case EXCP_SWI:
f0267ef7
TB		 1087 ret = do_syscall(env,
1088 env->xregs[8],
1089 env->xregs[0],
1090 env->xregs[1],
1091 env->xregs[2],
1092 env->xregs[3],
1093 env->xregs[4],
1094 env->xregs[5],
1095 0, 0);
1096 if (ret == -TARGET_ERESTARTSYS) {
1097 env->pc -= 4;
1098 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
1099 env->xregs[0] = ret;
1100 }
1861c454
PM		 1101 break;
1102 case EXCP_INTERRUPT:
1103 /* just indicate that signals should be handled asap */
1104 break;
1105 case EXCP_UDEF:
a86b3c64 1106 info.si_signo = TARGET_SIGILL;
1861c454
PM		 1107 info.si_errno = 0;
1108 info.si_code = TARGET_ILL_ILLOPN;
1109 info._sifields._sigfault._addr = env->pc;
9d2803f7 1110 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1861c454 1111 break;
abf1172f
PM		 1112 case EXCP_STREX:
1113 if (!do_strex_a64(env)) {
1114 break;
1115 }
1116 /* fall through for segv */
1861c454 1117 case EXCP_PREFETCH_ABORT:
1861c454 1118 case EXCP_DATA_ABORT:
a86b3c64 1119 info.si_signo = TARGET_SIGSEGV;
1861c454
PM		 1120 info.si_errno = 0;
1121 /* XXX: check env->error_code */
1122 info.si_code = TARGET_SEGV_MAPERR;
686581ad 1123 info._sifields._sigfault._addr = env->exception.vaddress;
9d2803f7 1124 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1861c454
PM		 1125 break;
1126 case EXCP_DEBUG:
1127 case EXCP_BKPT:
1128 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1129 if (sig) {
1130 info.si_signo = sig;
1131 info.si_errno = 0;
1132 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 1133 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1861c454
PM		 1134 }
1135 break;
8012c84f
PM		 1136 case EXCP_SEMIHOST:
1137 env->xregs[0] = do_arm_semihosting(env);
1138 break;
f911e0a3
PM		 1139 case EXCP_YIELD:
1140 /* nothing to do here for user-mode, just resume guest code */
1141 break;
1861c454 1142 default:
120a9848 1143 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1861c454
PM		 1144 abort();
1145 }
1146 process_pending_signals(env);
fa2ef212
MM		 1147 /* Exception return on AArch64 always clears the exclusive monitor,
1148 * so any return to running guest code implies this.
1149 * A strex (successful or otherwise) also clears the monitor, so
1150 * we don't need to specialcase EXCP_STREX.
1151 */
1152 env->exclusive_addr = -1;
1861c454
PM		 1153 }
1154}
1155#endif /* ndef TARGET_ABI32 */
1156
b346ff46 1157#endif
1b6b029e 1158
d2fbca94
GX		 1159#ifdef TARGET_UNICORE32
1160
05390248 1161void cpu_loop(CPUUniCore32State *env)
d2fbca94 1162{
0315c31c 1163 CPUState *cs = CPU(uc32_env_get_cpu(env));
d2fbca94
GX		 1164 int trapnr;
1165 unsigned int n, insn;
1166 target_siginfo_t info;
1167
1168 for (;;) {
0315c31c 1169 cpu_exec_start(cs);
8642c1b8 1170 trapnr = cpu_exec(cs);
0315c31c 1171 cpu_exec_end(cs);
d2fbca94
GX		 1172 switch (trapnr) {
1173 case UC32_EXCP_PRIV:
1174 {
1175 /* system call */
1176 get_user_u32(insn, env->regs[31] - 4);
1177 n = insn & 0xffffff;
1178
1179 if (n >= UC32_SYSCALL_BASE) {
1180 /* linux syscall */
1181 n -= UC32_SYSCALL_BASE;
1182 if (n == UC32_SYSCALL_NR_set_tls) {
1183 cpu_set_tls(env, env->regs[0]);
1184 env->regs[0] = 0;
1185 } else {
256cb6af 1186 abi_long ret = do_syscall(env,
d2fbca94
GX		 1187 n,
1188 env->regs[0],
1189 env->regs[1],
1190 env->regs[2],
1191 env->regs[3],
1192 env->regs[4],
5945cfcb
PM		 1193 env->regs[5],
1194 0, 0);
256cb6af
TB		 1195 if (ret == -TARGET_ERESTARTSYS) {
1196 env->regs[31] -= 4;
1197 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
1198 env->regs[0] = ret;
1199 }
d2fbca94
GX		 1200 }
1201 } else {
1202 goto error;
1203 }
1204 }
1205 break;
d48813dd
GX		 1206 case UC32_EXCP_DTRAP:
1207 case UC32_EXCP_ITRAP:
a86b3c64 1208 info.si_signo = TARGET_SIGSEGV;
d2fbca94
GX		 1209 info.si_errno = 0;
1210 /* XXX: check env->error_code */
1211 info.si_code = TARGET_SEGV_MAPERR;
1212 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
9d2803f7 1213 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
d2fbca94
GX		 1214 break;
1215 case EXCP_INTERRUPT:
1216 /* just indicate that signals should be handled asap */
1217 break;
1218 case EXCP_DEBUG:
1219 {
1220 int sig;
1221
db6b81d4 1222 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d2fbca94
GX		 1223 if (sig) {
1224 info.si_signo = sig;
1225 info.si_errno = 0;
1226 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 1227 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
d2fbca94
GX		 1228 }
1229 }
1230 break;
1231 default:
1232 goto error;
1233 }
1234 process_pending_signals(env);
1235 }
1236
1237error:
120a9848 1238 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
d2fbca94
GX		 1239 abort();
1240}
1241#endif
1242
93ac68bc 1243#ifdef TARGET_SPARC
ed23fbd9 1244#define SPARC64_STACK_BIAS 2047
93ac68bc 1245
060366c5
FB		 1246//#define DEBUG_WIN
1247
2623cbaf
FB		 1248/* WARNING: dealing with register windows _is_ complicated. More info
1249 can be found at http://www.sics.se/~psm/sparcstack.html */
060366c5
FB		 1250static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1251{
1a14026e 1252 index = (index + cwp * 16) % (16 * env->nwindows);
060366c5
FB		 1253 /* wrap handling : if cwp is on the last window, then we use the
1254 registers 'after' the end */
1a14026e
BS		 1255 if (index < 8 && env->cwp == env->nwindows - 1)
1256 index += 16 * env->nwindows;
060366c5
FB		 1257 return index;
1258}
1259
2623cbaf
FB		 1260/* save the register window 'cwp1' */
1261static inline void save_window_offset(CPUSPARCState *env, int cwp1)
060366c5 1262{
2623cbaf 1263 unsigned int i;
992f48a0 1264 abi_ulong sp_ptr;
3b46e624 1265
53a5960a 1266 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1267#ifdef TARGET_SPARC64
1268 if (sp_ptr & 3)
1269 sp_ptr += SPARC64_STACK_BIAS;
1270#endif
060366c5 1271#if defined(DEBUG_WIN)
2daf0284
BS		 1272 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1273 sp_ptr, cwp1);
060366c5 1274#endif
2623cbaf 1275 for(i = 0; i < 16; i++) {
2f619698
FB		 1276 /* FIXME - what to do if put_user() fails? */
1277 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1278 sp_ptr += sizeof(abi_ulong);
2623cbaf 1279 }
060366c5
FB		 1280}
1281
1282static void save_window(CPUSPARCState *env)
1283{
5ef54116 1284#ifndef TARGET_SPARC64
2623cbaf 1285 unsigned int new_wim;
1a14026e
BS		 1286 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1287 ((1LL << env->nwindows) - 1);
1288 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
2623cbaf 1289 env->wim = new_wim;
5ef54116 1290#else
1a14026e 1291 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
5ef54116
FB		 1292 env->cansave++;
1293 env->canrestore--;
1294#endif
060366c5
FB		 1295}
1296
1297static void restore_window(CPUSPARCState *env)
1298{
eda52953
BS		 1299#ifndef TARGET_SPARC64
1300 unsigned int new_wim;
1301#endif
1302 unsigned int i, cwp1;
992f48a0 1303 abi_ulong sp_ptr;
3b46e624 1304
eda52953 1305#ifndef TARGET_SPARC64
1a14026e
BS		 1306 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1307 ((1LL << env->nwindows) - 1);
eda52953 1308#endif
3b46e624 1309
060366c5 1310 /* restore the invalid window */
1a14026e 1311 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
53a5960a 1312 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1313#ifdef TARGET_SPARC64
1314 if (sp_ptr & 3)
1315 sp_ptr += SPARC64_STACK_BIAS;
1316#endif
060366c5 1317#if defined(DEBUG_WIN)
2daf0284
BS		 1318 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1319 sp_ptr, cwp1);
060366c5 1320#endif
2623cbaf 1321 for(i = 0; i < 16; i++) {
2f619698
FB		 1322 /* FIXME - what to do if get_user() fails? */
1323 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1324 sp_ptr += sizeof(abi_ulong);
2623cbaf 1325 }
5ef54116
FB		 1326#ifdef TARGET_SPARC64
1327 env->canrestore++;
1a14026e
BS		 1328 if (env->cleanwin < env->nwindows - 1)
1329 env->cleanwin++;
5ef54116 1330 env->cansave--;
eda52953
BS		 1331#else
1332 env->wim = new_wim;
5ef54116 1333#endif
060366c5
FB		 1334}
1335
1336static void flush_windows(CPUSPARCState *env)
1337{
1338 int offset, cwp1;
2623cbaf
FB		 1339
1340 offset = 1;
060366c5
FB		 1341 for(;;) {
1342 /* if restore would invoke restore_window(), then we can stop */
1a14026e 1343 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
eda52953 1344#ifndef TARGET_SPARC64
060366c5
FB		 1345 if (env->wim & (1 << cwp1))
1346 break;
eda52953
BS		 1347#else
1348 if (env->canrestore == 0)
1349 break;
1350 env->cansave++;
1351 env->canrestore--;
1352#endif
2623cbaf 1353 save_window_offset(env, cwp1);
060366c5
FB		 1354 offset++;
1355 }
1a14026e 1356 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
eda52953
BS		 1357#ifndef TARGET_SPARC64
1358 /* set wim so that restore will reload the registers */
2623cbaf 1359 env->wim = 1 << cwp1;
eda52953 1360#endif
2623cbaf
FB		 1361#if defined(DEBUG_WIN)
1362 printf("flush_windows: nb=%d\n", offset - 1);
80a9d035 1363#endif
2623cbaf 1364}
060366c5 1365
93ac68bc
FB		 1366void cpu_loop (CPUSPARCState *env)
1367{
878096ee 1368 CPUState *cs = CPU(sparc_env_get_cpu(env));
2cc20260
RH		 1369 int trapnr;
1370 abi_long ret;
c227f099 1371 target_siginfo_t info;
3b46e624 1372
060366c5 1373 while (1) {
b040bc9c 1374 cpu_exec_start(cs);
8642c1b8 1375 trapnr = cpu_exec(cs);
b040bc9c 1376 cpu_exec_end(cs);
3b46e624 1377
20132b96
RH		 1378 /* Compute PSR before exposing state. */
1379 if (env->cc_op != CC_OP_FLAGS) {
1380 cpu_get_psr(env);
1381 }
1382
060366c5 1383 switch (trapnr) {
5ef54116 1384#ifndef TARGET_SPARC64
5fafdf24 1385 case 0x88:
060366c5 1386 case 0x90:
5ef54116 1387#else
cb33da57 1388 case 0x110:
5ef54116
FB		 1389 case 0x16d:
1390#endif
060366c5 1391 ret = do_syscall (env, env->gregs[1],
5fafdf24
TS		 1392 env->regwptr[0], env->regwptr[1],
1393 env->regwptr[2], env->regwptr[3],
5945cfcb
PM		 1394 env->regwptr[4], env->regwptr[5],
1395 0, 0);
c0bea68f
TB		 1396 if (ret == -TARGET_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) {
1397 break;
1398 }
2cc20260 1399 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
992f48a0 1400#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1401 env->xcc |= PSR_CARRY;
1402#else
060366c5 1403 env->psr |= PSR_CARRY;
27908725 1404#endif
060366c5
FB		 1405 ret = -ret;
1406 } else {
992f48a0 1407#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1408 env->xcc &= ~PSR_CARRY;
1409#else
060366c5 1410 env->psr &= ~PSR_CARRY;
27908725 1411#endif
060366c5
FB		 1412 }
1413 env->regwptr[0] = ret;
1414 /* next instruction */
1415 env->pc = env->npc;
1416 env->npc = env->npc + 4;
1417 break;
1418 case 0x83: /* flush windows */
992f48a0
BS		 1419#ifdef TARGET_ABI32
1420 case 0x103:
1421#endif
2623cbaf 1422 flush_windows(env);
060366c5
FB		 1423 /* next instruction */
1424 env->pc = env->npc;
1425 env->npc = env->npc + 4;
1426 break;
3475187d 1427#ifndef TARGET_SPARC64
060366c5
FB		 1428 case TT_WIN_OVF: /* window overflow */
1429 save_window(env);
1430 break;
1431 case TT_WIN_UNF: /* window underflow */
1432 restore_window(env);
1433 break;
61ff6f58
FB		 1434 case TT_TFAULT:
1435 case TT_DFAULT:
1436 {
59f7182f 1437 info.si_signo = TARGET_SIGSEGV;
61ff6f58
FB		 1438 info.si_errno = 0;
1439 /* XXX: check env->error_code */
1440 info.si_code = TARGET_SEGV_MAPERR;
1441 info._sifields._sigfault._addr = env->mmuregs[4];
9d2803f7 1442 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
61ff6f58
FB		 1443 }
1444 break;
3475187d 1445#else
5ef54116
FB		 1446 case TT_SPILL: /* window overflow */
1447 save_window(env);
1448 break;
1449 case TT_FILL: /* window underflow */
1450 restore_window(env);
1451 break;
7f84a729
BS		 1452 case TT_TFAULT:
1453 case TT_DFAULT:
1454 {
59f7182f 1455 info.si_signo = TARGET_SIGSEGV;
7f84a729
BS		 1456 info.si_errno = 0;
1457 /* XXX: check env->error_code */
1458 info.si_code = TARGET_SEGV_MAPERR;
1459 if (trapnr == TT_DFAULT)
1460 info._sifields._sigfault._addr = env->dmmuregs[4];
1461 else
8194f35a 1462 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
9d2803f7 1463 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
7f84a729
BS		 1464 }
1465 break;
27524dc3 1466#ifndef TARGET_ABI32
5bfb56b2
BS		 1467 case 0x16e:
1468 flush_windows(env);
1469 sparc64_get_context(env);
1470 break;
1471 case 0x16f:
1472 flush_windows(env);
1473 sparc64_set_context(env);
1474 break;
27524dc3 1475#endif
3475187d 1476#endif
48dc41eb
FB		 1477 case EXCP_INTERRUPT:
1478 /* just indicate that signals should be handled asap */
1479 break;
75f22e4e
RH		 1480 case TT_ILL_INSN:
1481 {
1482 info.si_signo = TARGET_SIGILL;
1483 info.si_errno = 0;
1484 info.si_code = TARGET_ILL_ILLOPC;
1485 info._sifields._sigfault._addr = env->pc;
9d2803f7 1486 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
75f22e4e
RH		 1487 }
1488 break;
1fddef4b
FB		 1489 case EXCP_DEBUG:
1490 {
1491 int sig;
1492
db6b81d4 1493 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 1494 if (sig)
1495 {
1496 info.si_signo = sig;
1497 info.si_errno = 0;
1498 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 1499 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1fddef4b
FB		 1500 }
1501 }
1502 break;
060366c5
FB		 1503 default:
1504 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 1505 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 1506 exit(EXIT_FAILURE);
060366c5
FB		 1507 }
1508 process_pending_signals (env);
1509 }
93ac68bc
FB		 1510}
1511
1512#endif
1513
67867308 1514#ifdef TARGET_PPC
05390248 1515static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
9fddaa0c 1516{
4a7428c5 1517 return cpu_get_host_ticks();
9fddaa0c 1518}
3b46e624 1519
05390248 1520uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
9fddaa0c 1521{
e3ea6529 1522 return cpu_ppc_get_tb(env);
9fddaa0c 1523}
3b46e624 1524
05390248 1525uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
9fddaa0c
FB		 1526{
1527 return cpu_ppc_get_tb(env) >> 32;
1528}
3b46e624 1529
05390248 1530uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
9fddaa0c 1531{
b711de95 1532 return cpu_ppc_get_tb(env);
9fddaa0c 1533}
5fafdf24 1534
05390248 1535uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
9fddaa0c 1536{
a062e36c 1537 return cpu_ppc_get_tb(env) >> 32;
9fddaa0c 1538}
76a66253 1539
05390248 1540uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
76a66253
JM		 1541__attribute__ (( alias ("cpu_ppc_load_tbu") ));
1542
05390248 1543uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
9fddaa0c 1544{
76a66253 1545 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
9fddaa0c 1546}
76a66253 1547
a750fc0b 1548/* XXX: to be fixed */
73b01960 1549int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
a750fc0b
JM		 1550{
1551 return -1;
1552}
1553
73b01960 1554int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
a750fc0b
JM		 1555{
1556 return -1;
1557}
1558
56f066bb
NF		 1559static int do_store_exclusive(CPUPPCState *env)
1560{
1561 target_ulong addr;
1562 target_ulong page_addr;
e22c357b 1563 target_ulong val, val2 __attribute__((unused)) = 0;
56f066bb
NF		 1564 int flags;
1565 int segv = 0;
1566
1567 addr = env->reserve_ea;
1568 page_addr = addr & TARGET_PAGE_MASK;
1569 start_exclusive();
1570 mmap_lock();
1571 flags = page_get_flags(page_addr);
1572 if ((flags & PAGE_READ) == 0) {
1573 segv = 1;
1574 } else {
1575 int reg = env->reserve_info & 0x1f;
4b1daa72 1576 int size = env->reserve_info >> 5;
56f066bb
NF		 1577 int stored = 0;
1578
1579 if (addr == env->reserve_addr) {
1580 switch (size) {
1581 case 1: segv = get_user_u8(val, addr); break;
1582 case 2: segv = get_user_u16(val, addr); break;
1583 case 4: segv = get_user_u32(val, addr); break;
1584#if defined(TARGET_PPC64)
1585 case 8: segv = get_user_u64(val, addr); break;
27b95bfe
TM		 1586 case 16: {
1587 segv = get_user_u64(val, addr);
1588 if (!segv) {
1589 segv = get_user_u64(val2, addr + 8);
1590 }
1591 break;
1592 }
56f066bb
NF		 1593#endif
1594 default: abort();
1595 }
1596 if (!segv && val == env->reserve_val) {
1597 val = env->gpr[reg];
1598 switch (size) {
1599 case 1: segv = put_user_u8(val, addr); break;
1600 case 2: segv = put_user_u16(val, addr); break;
1601 case 4: segv = put_user_u32(val, addr); break;
1602#if defined(TARGET_PPC64)
1603 case 8: segv = put_user_u64(val, addr); break;
27b95bfe
TM		 1604 case 16: {
1605 if (val2 == env->reserve_val2) {
e22c357b
DK		 1606 if (msr_le) {
1607 val2 = val;
1608 val = env->gpr[reg+1];
1609 } else {
1610 val2 = env->gpr[reg+1];
1611 }
27b95bfe
TM		 1612 segv = put_user_u64(val, addr);
1613 if (!segv) {
1614 segv = put_user_u64(val2, addr + 8);
1615 }
1616 }
1617 break;
1618 }
56f066bb
NF		 1619#endif
1620 default: abort();
1621 }
1622 if (!segv) {
1623 stored = 1;
1624 }
1625 }
1626 }
1627 env->crf[0] = (stored << 1) | xer_so;
1628 env->reserve_addr = (target_ulong)-1;
1629 }
1630 if (!segv) {
1631 env->nip += 4;
1632 }
1633 mmap_unlock();
1634 end_exclusive();
1635 return segv;
1636}
1637
67867308
FB		 1638void cpu_loop(CPUPPCState *env)
1639{
0315c31c 1640 CPUState *cs = CPU(ppc_env_get_cpu(env));
c227f099 1641 target_siginfo_t info;
61190b14 1642 int trapnr;
9e0e2f96 1643 target_ulong ret;
3b46e624 1644
67867308 1645 for(;;) {
0315c31c 1646 cpu_exec_start(cs);
8642c1b8 1647 trapnr = cpu_exec(cs);
0315c31c 1648 cpu_exec_end(cs);
67867308 1649 switch(trapnr) {
e1833e1f
JM		 1650 case POWERPC_EXCP_NONE:
1651 /* Just go on */
67867308 1652 break;
e1833e1f 1653 case POWERPC_EXCP_CRITICAL: /* Critical input */
a47dddd7 1654 cpu_abort(cs, "Critical interrupt while in user mode. "
e1833e1f 1655 "Aborting\n");
61190b14 1656 break;
e1833e1f 1657 case POWERPC_EXCP_MCHECK: /* Machine check exception */
a47dddd7 1658 cpu_abort(cs, "Machine check exception while in user mode. "
e1833e1f
JM		 1659 "Aborting\n");
1660 break;
1661 case POWERPC_EXCP_DSI: /* Data storage exception */
e1833e1f 1662 /* XXX: check this. Seems bugged */
2be0071f
FB		 1663 switch (env->error_code & 0xFF000000) {
1664 case 0x40000000:
ba4a8df8 1665 case 0x42000000:
61190b14
FB		 1666 info.si_signo = TARGET_SIGSEGV;
1667 info.si_errno = 0;
1668 info.si_code = TARGET_SEGV_MAPERR;
1669 break;
2be0071f 1670 case 0x04000000:
61190b14
FB		 1671 info.si_signo = TARGET_SIGILL;
1672 info.si_errno = 0;
1673 info.si_code = TARGET_ILL_ILLADR;
1674 break;
2be0071f 1675 case 0x08000000:
61190b14
FB		 1676 info.si_signo = TARGET_SIGSEGV;
1677 info.si_errno = 0;
1678 info.si_code = TARGET_SEGV_ACCERR;
1679 break;
61190b14
FB		 1680 default:
1681 /* Let's send a regular segfault... */
e1833e1f
JM		 1682 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1683 env->error_code);
61190b14
FB		 1684 info.si_signo = TARGET_SIGSEGV;
1685 info.si_errno = 0;
1686 info.si_code = TARGET_SEGV_MAPERR;
1687 break;
1688 }
67867308 1689 info._sifields._sigfault._addr = env->nip;
9d2803f7 1690 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
67867308 1691 break;
e1833e1f 1692 case POWERPC_EXCP_ISI: /* Instruction storage exception */
e1833e1f 1693 /* XXX: check this */
2be0071f
FB		 1694 switch (env->error_code & 0xFF000000) {
1695 case 0x40000000:
61190b14 1696 info.si_signo = TARGET_SIGSEGV;
67867308 1697 info.si_errno = 0;
61190b14
FB		 1698 info.si_code = TARGET_SEGV_MAPERR;
1699 break;
2be0071f
FB		 1700 case 0x10000000:
1701 case 0x08000000:
61190b14
FB		 1702 info.si_signo = TARGET_SIGSEGV;
1703 info.si_errno = 0;
1704 info.si_code = TARGET_SEGV_ACCERR;
1705 break;
1706 default:
1707 /* Let's send a regular segfault... */
e1833e1f
JM		 1708 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1709 env->error_code);
61190b14
FB		 1710 info.si_signo = TARGET_SIGSEGV;
1711 info.si_errno = 0;
1712 info.si_code = TARGET_SEGV_MAPERR;
1713 break;
1714 }
1715 info._sifields._sigfault._addr = env->nip - 4;
9d2803f7 1716 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
67867308 1717 break;
e1833e1f 1718 case POWERPC_EXCP_EXTERNAL: /* External input */
a47dddd7 1719 cpu_abort(cs, "External interrupt while in user mode. "
e1833e1f
JM		 1720 "Aborting\n");
1721 break;
1722 case POWERPC_EXCP_ALIGN: /* Alignment exception */
e1833e1f 1723 /* XXX: check this */
61190b14 1724 info.si_signo = TARGET_SIGBUS;
67867308 1725 info.si_errno = 0;
61190b14 1726 info.si_code = TARGET_BUS_ADRALN;
6bb9a0a9 1727 info._sifields._sigfault._addr = env->nip;
9d2803f7 1728 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
67867308 1729 break;
e1833e1f 1730 case POWERPC_EXCP_PROGRAM: /* Program exception */
9b2fadda 1731 case POWERPC_EXCP_HV_EMU: /* HV emulation */
e1833e1f 1732 /* XXX: check this */
61190b14 1733 switch (env->error_code & ~0xF) {
e1833e1f 1734 case POWERPC_EXCP_FP:
61190b14
FB		 1735 info.si_signo = TARGET_SIGFPE;
1736 info.si_errno = 0;
1737 switch (env->error_code & 0xF) {
e1833e1f 1738 case POWERPC_EXCP_FP_OX:
61190b14
FB		 1739 info.si_code = TARGET_FPE_FLTOVF;
1740 break;
e1833e1f 1741 case POWERPC_EXCP_FP_UX:
61190b14
FB		 1742 info.si_code = TARGET_FPE_FLTUND;
1743 break;
e1833e1f
JM		 1744 case POWERPC_EXCP_FP_ZX:
1745 case POWERPC_EXCP_FP_VXZDZ:
61190b14
FB		 1746 info.si_code = TARGET_FPE_FLTDIV;
1747 break;
e1833e1f 1748 case POWERPC_EXCP_FP_XX:
61190b14
FB		 1749 info.si_code = TARGET_FPE_FLTRES;
1750 break;
e1833e1f 1751 case POWERPC_EXCP_FP_VXSOFT:
61190b14
FB		 1752 info.si_code = TARGET_FPE_FLTINV;
1753 break;
7c58044c 1754 case POWERPC_EXCP_FP_VXSNAN:
e1833e1f
JM		 1755 case POWERPC_EXCP_FP_VXISI:
1756 case POWERPC_EXCP_FP_VXIDI:
1757 case POWERPC_EXCP_FP_VXIMZ:
1758 case POWERPC_EXCP_FP_VXVC:
1759 case POWERPC_EXCP_FP_VXSQRT:
1760 case POWERPC_EXCP_FP_VXCVI:
61190b14
FB		 1761 info.si_code = TARGET_FPE_FLTSUB;
1762 break;
1763 default:
e1833e1f
JM		 1764 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1765 env->error_code);
1766 break;
61190b14 1767 }
e1833e1f
JM		 1768 break;
1769 case POWERPC_EXCP_INVAL:
61190b14
FB		 1770 info.si_signo = TARGET_SIGILL;
1771 info.si_errno = 0;
1772 switch (env->error_code & 0xF) {
e1833e1f 1773 case POWERPC_EXCP_INVAL_INVAL:
61190b14
FB		 1774 info.si_code = TARGET_ILL_ILLOPC;
1775 break;
e1833e1f 1776 case POWERPC_EXCP_INVAL_LSWX:
a750fc0b 1777 info.si_code = TARGET_ILL_ILLOPN;
61190b14 1778 break;
e1833e1f 1779 case POWERPC_EXCP_INVAL_SPR:
61190b14
FB		 1780 info.si_code = TARGET_ILL_PRVREG;
1781 break;
e1833e1f 1782 case POWERPC_EXCP_INVAL_FP:
61190b14
FB		 1783 info.si_code = TARGET_ILL_COPROC;
1784 break;
1785 default:
e1833e1f
JM		 1786 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1787 env->error_code & 0xF);
61190b14
FB		 1788 info.si_code = TARGET_ILL_ILLADR;
1789 break;
1790 }
1791 break;
e1833e1f 1792 case POWERPC_EXCP_PRIV:
61190b14
FB		 1793 info.si_signo = TARGET_SIGILL;
1794 info.si_errno = 0;
1795 switch (env->error_code & 0xF) {
e1833e1f 1796 case POWERPC_EXCP_PRIV_OPC:
61190b14
FB		 1797 info.si_code = TARGET_ILL_PRVOPC;
1798 break;
e1833e1f 1799 case POWERPC_EXCP_PRIV_REG:
61190b14 1800 info.si_code = TARGET_ILL_PRVREG;
e1833e1f 1801 break;
61190b14 1802 default:
e1833e1f
JM		 1803 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1804 env->error_code & 0xF);
61190b14
FB		 1805 info.si_code = TARGET_ILL_PRVOPC;
1806 break;
1807 }
1808 break;
e1833e1f 1809 case POWERPC_EXCP_TRAP:
a47dddd7 1810 cpu_abort(cs, "Tried to call a TRAP\n");
e1833e1f 1811 break;
61190b14
FB		 1812 default:
1813 /* Should not happen ! */
a47dddd7 1814 cpu_abort(cs, "Unknown program exception (%02x)\n",
e1833e1f
JM		 1815 env->error_code);
1816 break;
61190b14 1817 }
bd6fefe7 1818 info._sifields._sigfault._addr = env->nip;
9d2803f7 1819 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
67867308 1820 break;
e1833e1f 1821 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
61190b14 1822 info.si_signo = TARGET_SIGILL;
67867308 1823 info.si_errno = 0;
61190b14 1824 info.si_code = TARGET_ILL_COPROC;
bd6fefe7 1825 info._sifields._sigfault._addr = env->nip;
9d2803f7 1826 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
67867308 1827 break;
e1833e1f 1828 case POWERPC_EXCP_SYSCALL: /* System call exception */
a47dddd7 1829 cpu_abort(cs, "Syscall exception while in user mode. "
e1833e1f 1830 "Aborting\n");
61190b14 1831 break;
e1833e1f 1832 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
e1833e1f
JM		 1833 info.si_signo = TARGET_SIGILL;
1834 info.si_errno = 0;
1835 info.si_code = TARGET_ILL_COPROC;
bd6fefe7 1836 info._sifields._sigfault._addr = env->nip;
9d2803f7 1837 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
61190b14 1838 break;
e1833e1f 1839 case POWERPC_EXCP_DECR: /* Decrementer exception */
a47dddd7 1840 cpu_abort(cs, "Decrementer interrupt while in user mode. "
e1833e1f 1841 "Aborting\n");
61190b14 1842 break;
e1833e1f 1843 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
a47dddd7 1844 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
e1833e1f
JM		 1845 "Aborting\n");
1846 break;
1847 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
a47dddd7 1848 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
e1833e1f
JM		 1849 "Aborting\n");
1850 break;
1851 case POWERPC_EXCP_DTLB: /* Data TLB error */
a47dddd7 1852 cpu_abort(cs, "Data TLB exception while in user mode. "
e1833e1f
JM		 1853 "Aborting\n");
1854 break;
1855 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
a47dddd7 1856 cpu_abort(cs, "Instruction TLB exception while in user mode. "
e1833e1f
JM		 1857 "Aborting\n");
1858 break;
e1833e1f 1859 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
e1833e1f
JM		 1860 info.si_signo = TARGET_SIGILL;
1861 info.si_errno = 0;
1862 info.si_code = TARGET_ILL_COPROC;
bd6fefe7 1863 info._sifields._sigfault._addr = env->nip;
9d2803f7 1864 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
e1833e1f
JM		 1865 break;
1866 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
a47dddd7 1867 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
e1833e1f
JM		 1868 break;
1869 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
a47dddd7 1870 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
e1833e1f
JM		 1871 break;
1872 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
a47dddd7 1873 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1874 break;
1875 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
a47dddd7 1876 cpu_abort(cs, "Doorbell interrupt while in user mode. "
e1833e1f
JM		 1877 "Aborting\n");
1878 break;
1879 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
a47dddd7 1880 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
e1833e1f
JM		 1881 "Aborting\n");
1882 break;
1883 case POWERPC_EXCP_RESET: /* System reset exception */
a47dddd7 1884 cpu_abort(cs, "Reset interrupt while in user mode. "
e1833e1f
JM		 1885 "Aborting\n");
1886 break;
e1833e1f 1887 case POWERPC_EXCP_DSEG: /* Data segment exception */
a47dddd7 1888 cpu_abort(cs, "Data segment exception while in user mode. "
e1833e1f
JM		 1889 "Aborting\n");
1890 break;
1891 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
a47dddd7 1892 cpu_abort(cs, "Instruction segment exception "
e1833e1f
JM		 1893 "while in user mode. Aborting\n");
1894 break;
e85e7c6e 1895 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1896 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
a47dddd7 1897 cpu_abort(cs, "Hypervisor decrementer interrupt "
e1833e1f
JM		 1898 "while in user mode. Aborting\n");
1899 break;
e1833e1f
JM		 1900 case POWERPC_EXCP_TRACE: /* Trace exception */
1901 /* Nothing to do:
1902 * we use this exception to emulate step-by-step execution mode.
1903 */
1904 break;
e85e7c6e 1905 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1906 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
a47dddd7 1907 cpu_abort(cs, "Hypervisor data storage exception "
e1833e1f
JM		 1908 "while in user mode. Aborting\n");
1909 break;
1910 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
a47dddd7 1911 cpu_abort(cs, "Hypervisor instruction storage exception "
e1833e1f
JM		 1912 "while in user mode. Aborting\n");
1913 break;
1914 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
a47dddd7 1915 cpu_abort(cs, "Hypervisor data segment exception "
e1833e1f
JM		 1916 "while in user mode. Aborting\n");
1917 break;
1918 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
a47dddd7 1919 cpu_abort(cs, "Hypervisor instruction segment exception "
e1833e1f
JM		 1920 "while in user mode. Aborting\n");
1921 break;
e1833e1f 1922 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
e1833e1f
JM		 1923 info.si_signo = TARGET_SIGILL;
1924 info.si_errno = 0;
1925 info.si_code = TARGET_ILL_COPROC;
bd6fefe7 1926 info._sifields._sigfault._addr = env->nip;
9d2803f7 1927 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
e1833e1f
JM		 1928 break;
1929 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
a47dddd7 1930 cpu_abort(cs, "Programmable interval timer interrupt "
e1833e1f
JM		 1931 "while in user mode. Aborting\n");
1932 break;
1933 case POWERPC_EXCP_IO: /* IO error exception */
a47dddd7 1934 cpu_abort(cs, "IO error exception while in user mode. "
e1833e1f
JM		 1935 "Aborting\n");
1936 break;
1937 case POWERPC_EXCP_RUNM: /* Run mode exception */
a47dddd7 1938 cpu_abort(cs, "Run mode exception while in user mode. "
e1833e1f
JM		 1939 "Aborting\n");
1940 break;
1941 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
a47dddd7 1942 cpu_abort(cs, "Emulation trap exception not handled\n");
e1833e1f
JM		 1943 break;
1944 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
a47dddd7 1945 cpu_abort(cs, "Instruction fetch TLB exception "
e1833e1f
JM		 1946 "while in user-mode. Aborting");
1947 break;
1948 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
a47dddd7 1949 cpu_abort(cs, "Data load TLB exception while in user-mode. "
e1833e1f
JM		 1950 "Aborting");
1951 break;
1952 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
a47dddd7 1953 cpu_abort(cs, "Data store TLB exception while in user-mode. "
e1833e1f
JM		 1954 "Aborting");
1955 break;
1956 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
a47dddd7 1957 cpu_abort(cs, "Floating-point assist exception not handled\n");
e1833e1f
JM		 1958 break;
1959 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
a47dddd7 1960 cpu_abort(cs, "Instruction address breakpoint exception "
e1833e1f
JM		 1961 "not handled\n");
1962 break;
1963 case POWERPC_EXCP_SMI: /* System management interrupt */
a47dddd7 1964 cpu_abort(cs, "System management interrupt while in user mode. "
e1833e1f
JM		 1965 "Aborting\n");
1966 break;
1967 case POWERPC_EXCP_THERM: /* Thermal interrupt */
a47dddd7 1968 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
e1833e1f
JM		 1969 "Aborting\n");
1970 break;
1971 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
a47dddd7 1972 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1973 break;
1974 case POWERPC_EXCP_VPUA: /* Vector assist exception */
a47dddd7 1975 cpu_abort(cs, "Vector assist exception not handled\n");
e1833e1f
JM		 1976 break;
1977 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
a47dddd7 1978 cpu_abort(cs, "Soft patch exception not handled\n");
e1833e1f
JM		 1979 break;
1980 case POWERPC_EXCP_MAINT: /* Maintenance exception */
a47dddd7 1981 cpu_abort(cs, "Maintenance exception while in user mode. "
e1833e1f
JM		 1982 "Aborting\n");
1983 break;
1984 case POWERPC_EXCP_STOP: /* stop translation */
1985 /* We did invalidate the instruction cache. Go on */
1986 break;
1987 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1988 /* We just stopped because of a branch. Go on */
1989 break;
1990 case POWERPC_EXCP_SYSCALL_USER:
1991 /* system call in user-mode emulation */
1992 /* WARNING:
1993 * PPC ABI uses overflow flag in cr0 to signal an error
1994 * in syscalls.
1995 */
e1833e1f
JM		 1996 env->crf[0] &= ~0x1;
1997 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1998 env->gpr[5], env->gpr[6], env->gpr[7],
5945cfcb 1999 env->gpr[8], 0, 0);
6db9d00e 2000 if (ret == -TARGET_ERESTARTSYS) {
6db9d00e
TB		 2001 break;
2002 }
9e0e2f96 2003 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
bcd4933a
NF		 2004 /* Returning from a successful sigreturn syscall.
2005 Avoid corrupting register state. */
2006 break;
2007 }
95cda4c4 2008 env->nip += 4;
9e0e2f96 2009 if (ret > (target_ulong)(-515)) {
e1833e1f
JM		 2010 env->crf[0] |= 0x1;
2011 ret = -ret;
61190b14 2012 }
e1833e1f 2013 env->gpr[3] = ret;
e1833e1f 2014 break;
56f066bb
NF		 2015 case POWERPC_EXCP_STCX:
2016 if (do_store_exclusive(env)) {
2017 info.si_signo = TARGET_SIGSEGV;
2018 info.si_errno = 0;
2019 info.si_code = TARGET_SEGV_MAPERR;
2020 info._sifields._sigfault._addr = env->nip;
9d2803f7 2021 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
56f066bb
NF		 2022 }
2023 break;
71f75756
AJ		 2024 case EXCP_DEBUG:
2025 {
2026 int sig;
2027
db6b81d4 2028 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
71f75756
AJ		 2029 if (sig) {
2030 info.si_signo = sig;
2031 info.si_errno = 0;
2032 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 2033 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
71f75756
AJ		 2034 }
2035 }
2036 break;
56ba31ff
JM		 2037 case EXCP_INTERRUPT:
2038 /* just indicate that signals should be handled asap */
2039 break;
e1833e1f 2040 default:
8223f345 2041 cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr);
e1833e1f 2042 break;
67867308
FB		 2043 }
2044 process_pending_signals(env);
2045 }
2046}
2047#endif
2048
048f6b4d
FB		 2049#ifdef TARGET_MIPS
2050
ff4f7382
RH		 2051# ifdef TARGET_ABI_MIPSO32
2052# define MIPS_SYS(name, args) args,
048f6b4d 2053static const uint8_t mips_syscall_args[] = {
29fb0f25 2054 MIPS_SYS(sys_syscall , 8) /* 4000 */
048f6b4d
FB		 2055 MIPS_SYS(sys_exit , 1)
2056 MIPS_SYS(sys_fork , 0)
2057 MIPS_SYS(sys_read , 3)
2058 MIPS_SYS(sys_write , 3)
2059 MIPS_SYS(sys_open , 3) /* 4005 */
2060 MIPS_SYS(sys_close , 1)
2061 MIPS_SYS(sys_waitpid , 3)
2062 MIPS_SYS(sys_creat , 2)
2063 MIPS_SYS(sys_link , 2)
2064 MIPS_SYS(sys_unlink , 1) /* 4010 */
2065 MIPS_SYS(sys_execve , 0)
2066 MIPS_SYS(sys_chdir , 1)
2067 MIPS_SYS(sys_time , 1)
2068 MIPS_SYS(sys_mknod , 3)
2069 MIPS_SYS(sys_chmod , 2) /* 4015 */
2070 MIPS_SYS(sys_lchown , 3)
2071 MIPS_SYS(sys_ni_syscall , 0)
2072 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2073 MIPS_SYS(sys_lseek , 3)
2074 MIPS_SYS(sys_getpid , 0) /* 4020 */
2075 MIPS_SYS(sys_mount , 5)
868e34d7 2076 MIPS_SYS(sys_umount , 1)
048f6b4d
FB		 2077 MIPS_SYS(sys_setuid , 1)
2078 MIPS_SYS(sys_getuid , 0)
2079 MIPS_SYS(sys_stime , 1) /* 4025 */
2080 MIPS_SYS(sys_ptrace , 4)
2081 MIPS_SYS(sys_alarm , 1)
2082 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2083 MIPS_SYS(sys_pause , 0)
2084 MIPS_SYS(sys_utime , 2) /* 4030 */
2085 MIPS_SYS(sys_ni_syscall , 0)
2086 MIPS_SYS(sys_ni_syscall , 0)
2087 MIPS_SYS(sys_access , 2)
2088 MIPS_SYS(sys_nice , 1)
2089 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2090 MIPS_SYS(sys_sync , 0)
2091 MIPS_SYS(sys_kill , 2)
2092 MIPS_SYS(sys_rename , 2)
2093 MIPS_SYS(sys_mkdir , 2)
2094 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2095 MIPS_SYS(sys_dup , 1)
2096 MIPS_SYS(sys_pipe , 0)
2097 MIPS_SYS(sys_times , 1)
2098 MIPS_SYS(sys_ni_syscall , 0)
2099 MIPS_SYS(sys_brk , 1) /* 4045 */
2100 MIPS_SYS(sys_setgid , 1)
2101 MIPS_SYS(sys_getgid , 0)
2102 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2103 MIPS_SYS(sys_geteuid , 0)
2104 MIPS_SYS(sys_getegid , 0) /* 4050 */
2105 MIPS_SYS(sys_acct , 0)
868e34d7 2106 MIPS_SYS(sys_umount2 , 2)
048f6b4d
FB		 2107 MIPS_SYS(sys_ni_syscall , 0)
2108 MIPS_SYS(sys_ioctl , 3)
2109 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2110 MIPS_SYS(sys_ni_syscall , 2)
2111 MIPS_SYS(sys_setpgid , 2)
2112 MIPS_SYS(sys_ni_syscall , 0)
2113 MIPS_SYS(sys_olduname , 1)
2114 MIPS_SYS(sys_umask , 1) /* 4060 */
2115 MIPS_SYS(sys_chroot , 1)
2116 MIPS_SYS(sys_ustat , 2)
2117 MIPS_SYS(sys_dup2 , 2)
2118 MIPS_SYS(sys_getppid , 0)
2119 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2120 MIPS_SYS(sys_setsid , 0)
2121 MIPS_SYS(sys_sigaction , 3)
2122 MIPS_SYS(sys_sgetmask , 0)
2123 MIPS_SYS(sys_ssetmask , 1)
2124 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2125 MIPS_SYS(sys_setregid , 2)
2126 MIPS_SYS(sys_sigsuspend , 0)
2127 MIPS_SYS(sys_sigpending , 1)
2128 MIPS_SYS(sys_sethostname , 2)
2129 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2130 MIPS_SYS(sys_getrlimit , 2)
2131 MIPS_SYS(sys_getrusage , 2)
2132 MIPS_SYS(sys_gettimeofday, 2)
2133 MIPS_SYS(sys_settimeofday, 2)
2134 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2135 MIPS_SYS(sys_setgroups , 2)
2136 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2137 MIPS_SYS(sys_symlink , 2)
2138 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2139 MIPS_SYS(sys_readlink , 3) /* 4085 */
2140 MIPS_SYS(sys_uselib , 1)
2141 MIPS_SYS(sys_swapon , 2)
2142 MIPS_SYS(sys_reboot , 3)
2143 MIPS_SYS(old_readdir , 3)
2144 MIPS_SYS(old_mmap , 6) /* 4090 */
2145 MIPS_SYS(sys_munmap , 2)
2146 MIPS_SYS(sys_truncate , 2)
2147 MIPS_SYS(sys_ftruncate , 2)
2148 MIPS_SYS(sys_fchmod , 2)
2149 MIPS_SYS(sys_fchown , 3) /* 4095 */
2150 MIPS_SYS(sys_getpriority , 2)
2151 MIPS_SYS(sys_setpriority , 3)
2152 MIPS_SYS(sys_ni_syscall , 0)
2153 MIPS_SYS(sys_statfs , 2)
2154 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2155 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2156 MIPS_SYS(sys_socketcall , 2)
2157 MIPS_SYS(sys_syslog , 3)
2158 MIPS_SYS(sys_setitimer , 3)
2159 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2160 MIPS_SYS(sys_newstat , 2)
2161 MIPS_SYS(sys_newlstat , 2)
2162 MIPS_SYS(sys_newfstat , 2)
2163 MIPS_SYS(sys_uname , 1)
2164 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2165 MIPS_SYS(sys_vhangup , 0)
2166 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2167 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2168 MIPS_SYS(sys_wait4 , 4)
2169 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2170 MIPS_SYS(sys_sysinfo , 1)
2171 MIPS_SYS(sys_ipc , 6)
2172 MIPS_SYS(sys_fsync , 1)
2173 MIPS_SYS(sys_sigreturn , 0)
18113962 2174 MIPS_SYS(sys_clone , 6) /* 4120 */
048f6b4d
FB		 2175 MIPS_SYS(sys_setdomainname, 2)
2176 MIPS_SYS(sys_newuname , 1)
2177 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2178 MIPS_SYS(sys_adjtimex , 1)
2179 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2180 MIPS_SYS(sys_sigprocmask , 3)
2181 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2182 MIPS_SYS(sys_init_module , 5)
2183 MIPS_SYS(sys_delete_module, 1)
2184 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2185 MIPS_SYS(sys_quotactl , 0)
2186 MIPS_SYS(sys_getpgid , 1)
2187 MIPS_SYS(sys_fchdir , 1)
2188 MIPS_SYS(sys_bdflush , 2)
2189 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2190 MIPS_SYS(sys_personality , 1)
2191 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2192 MIPS_SYS(sys_setfsuid , 1)
2193 MIPS_SYS(sys_setfsgid , 1)
2194 MIPS_SYS(sys_llseek , 5) /* 4140 */
2195 MIPS_SYS(sys_getdents , 3)
2196 MIPS_SYS(sys_select , 5)
2197 MIPS_SYS(sys_flock , 2)
2198 MIPS_SYS(sys_msync , 3)
2199 MIPS_SYS(sys_readv , 3) /* 4145 */
2200 MIPS_SYS(sys_writev , 3)
2201 MIPS_SYS(sys_cacheflush , 3)
2202 MIPS_SYS(sys_cachectl , 3)
2203 MIPS_SYS(sys_sysmips , 4)
2204 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2205 MIPS_SYS(sys_getsid , 1)
2206 MIPS_SYS(sys_fdatasync , 0)
2207 MIPS_SYS(sys_sysctl , 1)
2208 MIPS_SYS(sys_mlock , 2)
2209 MIPS_SYS(sys_munlock , 2) /* 4155 */
2210 MIPS_SYS(sys_mlockall , 1)
2211 MIPS_SYS(sys_munlockall , 0)
2212 MIPS_SYS(sys_sched_setparam, 2)
2213 MIPS_SYS(sys_sched_getparam, 2)
2214 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2215 MIPS_SYS(sys_sched_getscheduler, 1)
2216 MIPS_SYS(sys_sched_yield , 0)
2217 MIPS_SYS(sys_sched_get_priority_max, 1)
2218 MIPS_SYS(sys_sched_get_priority_min, 1)
2219 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2220 MIPS_SYS(sys_nanosleep, 2)
b0932e06 2221 MIPS_SYS(sys_mremap , 5)
048f6b4d
FB		 2222 MIPS_SYS(sys_accept , 3)
2223 MIPS_SYS(sys_bind , 3)
2224 MIPS_SYS(sys_connect , 3) /* 4170 */
2225 MIPS_SYS(sys_getpeername , 3)
2226 MIPS_SYS(sys_getsockname , 3)
2227 MIPS_SYS(sys_getsockopt , 5)
2228 MIPS_SYS(sys_listen , 2)
2229 MIPS_SYS(sys_recv , 4) /* 4175 */
2230 MIPS_SYS(sys_recvfrom , 6)
2231 MIPS_SYS(sys_recvmsg , 3)
2232 MIPS_SYS(sys_send , 4)
2233 MIPS_SYS(sys_sendmsg , 3)
2234 MIPS_SYS(sys_sendto , 6) /* 4180 */
2235 MIPS_SYS(sys_setsockopt , 5)
2236 MIPS_SYS(sys_shutdown , 2)
2237 MIPS_SYS(sys_socket , 3)
2238 MIPS_SYS(sys_socketpair , 4)
2239 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2240 MIPS_SYS(sys_getresuid , 3)
2241 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2242 MIPS_SYS(sys_poll , 3)
2243 MIPS_SYS(sys_nfsservctl , 3)
2244 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2245 MIPS_SYS(sys_getresgid , 3)
2246 MIPS_SYS(sys_prctl , 5)
2247 MIPS_SYS(sys_rt_sigreturn, 0)
2248 MIPS_SYS(sys_rt_sigaction, 4)
2249 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2250 MIPS_SYS(sys_rt_sigpending, 2)
2251 MIPS_SYS(sys_rt_sigtimedwait, 4)
2252 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2253 MIPS_SYS(sys_rt_sigsuspend, 0)
2254 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2255 MIPS_SYS(sys_pwrite64 , 6)
2256 MIPS_SYS(sys_chown , 3)
2257 MIPS_SYS(sys_getcwd , 2)
2258 MIPS_SYS(sys_capget , 2)
2259 MIPS_SYS(sys_capset , 2) /* 4205 */
053ebb27 2260 MIPS_SYS(sys_sigaltstack , 2)
048f6b4d
FB		 2261 MIPS_SYS(sys_sendfile , 4)
2262 MIPS_SYS(sys_ni_syscall , 0)
2263 MIPS_SYS(sys_ni_syscall , 0)
2264 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2265 MIPS_SYS(sys_truncate64 , 4)
2266 MIPS_SYS(sys_ftruncate64 , 4)
2267 MIPS_SYS(sys_stat64 , 2)
2268 MIPS_SYS(sys_lstat64 , 2)
2269 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2270 MIPS_SYS(sys_pivot_root , 2)
2271 MIPS_SYS(sys_mincore , 3)
2272 MIPS_SYS(sys_madvise , 3)
2273 MIPS_SYS(sys_getdents64 , 3)
2274 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2275 MIPS_SYS(sys_ni_syscall , 0)
2276 MIPS_SYS(sys_gettid , 0)
2277 MIPS_SYS(sys_readahead , 5)
2278 MIPS_SYS(sys_setxattr , 5)
2279 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2280 MIPS_SYS(sys_fsetxattr , 5)
2281 MIPS_SYS(sys_getxattr , 4)
2282 MIPS_SYS(sys_lgetxattr , 4)
2283 MIPS_SYS(sys_fgetxattr , 4)
2284 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2285 MIPS_SYS(sys_llistxattr , 3)
2286 MIPS_SYS(sys_flistxattr , 3)
2287 MIPS_SYS(sys_removexattr , 2)
2288 MIPS_SYS(sys_lremovexattr, 2)
2289 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2290 MIPS_SYS(sys_tkill , 2)
2291 MIPS_SYS(sys_sendfile64 , 5)
43be1343 2292 MIPS_SYS(sys_futex , 6)
048f6b4d
FB		 2293 MIPS_SYS(sys_sched_setaffinity, 3)
2294 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2295 MIPS_SYS(sys_io_setup , 2)
2296 MIPS_SYS(sys_io_destroy , 1)
2297 MIPS_SYS(sys_io_getevents, 5)
2298 MIPS_SYS(sys_io_submit , 3)
2299 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2300 MIPS_SYS(sys_exit_group , 1)
2301 MIPS_SYS(sys_lookup_dcookie, 3)
2302 MIPS_SYS(sys_epoll_create, 1)
2303 MIPS_SYS(sys_epoll_ctl , 4)
2304 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2305 MIPS_SYS(sys_remap_file_pages, 5)
2306 MIPS_SYS(sys_set_tid_address, 1)
2307 MIPS_SYS(sys_restart_syscall, 0)
2308 MIPS_SYS(sys_fadvise64_64, 7)
2309 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2310 MIPS_SYS(sys_fstatfs64 , 2)
2311 MIPS_SYS(sys_timer_create, 3)
2312 MIPS_SYS(sys_timer_settime, 4)
2313 MIPS_SYS(sys_timer_gettime, 2)
2314 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2315 MIPS_SYS(sys_timer_delete, 1)
2316 MIPS_SYS(sys_clock_settime, 2)
2317 MIPS_SYS(sys_clock_gettime, 2)
2318 MIPS_SYS(sys_clock_getres, 2)
2319 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2320 MIPS_SYS(sys_tgkill , 3)
2321 MIPS_SYS(sys_utimes , 2)
2322 MIPS_SYS(sys_mbind , 4)
2323 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2324 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2325 MIPS_SYS(sys_mq_open , 4)
2326 MIPS_SYS(sys_mq_unlink , 1)
2327 MIPS_SYS(sys_mq_timedsend, 5)
2328 MIPS_SYS(sys_mq_timedreceive, 5)
2329 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2330 MIPS_SYS(sys_mq_getsetattr, 3)
2331 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2332 MIPS_SYS(sys_waitid , 4)
2333 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2334 MIPS_SYS(sys_add_key , 5)
388bb21a 2335 MIPS_SYS(sys_request_key, 4)
048f6b4d 2336 MIPS_SYS(sys_keyctl , 5)
6f5b89a0 2337 MIPS_SYS(sys_set_thread_area, 1)
388bb21a
TS		 2338 MIPS_SYS(sys_inotify_init, 0)
2339 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2340 MIPS_SYS(sys_inotify_rm_watch, 2)
2341 MIPS_SYS(sys_migrate_pages, 4)
2342 MIPS_SYS(sys_openat, 4)
2343 MIPS_SYS(sys_mkdirat, 3)
2344 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2345 MIPS_SYS(sys_fchownat, 5)
2346 MIPS_SYS(sys_futimesat, 3)
2347 MIPS_SYS(sys_fstatat64, 4)
2348 MIPS_SYS(sys_unlinkat, 3)
2349 MIPS_SYS(sys_renameat, 4) /* 4295 */
2350 MIPS_SYS(sys_linkat, 5)
2351 MIPS_SYS(sys_symlinkat, 3)
2352 MIPS_SYS(sys_readlinkat, 4)
2353 MIPS_SYS(sys_fchmodat, 3)
2354 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2355 MIPS_SYS(sys_pselect6, 6)
2356 MIPS_SYS(sys_ppoll, 5)
2357 MIPS_SYS(sys_unshare, 1)
b0932e06 2358 MIPS_SYS(sys_splice, 6)
388bb21a
TS		 2359 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2360 MIPS_SYS(sys_tee, 4)
2361 MIPS_SYS(sys_vmsplice, 4)
2362 MIPS_SYS(sys_move_pages, 6)
2363 MIPS_SYS(sys_set_robust_list, 2)
2364 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2365 MIPS_SYS(sys_kexec_load, 4)
2366 MIPS_SYS(sys_getcpu, 3)
2367 MIPS_SYS(sys_epoll_pwait, 6)
2368 MIPS_SYS(sys_ioprio_set, 3)
2369 MIPS_SYS(sys_ioprio_get, 2)
d979e8eb
PM		 2370 MIPS_SYS(sys_utimensat, 4)
2371 MIPS_SYS(sys_signalfd, 3)
2372 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2373 MIPS_SYS(sys_eventfd, 1)
2374 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2375 MIPS_SYS(sys_timerfd_create, 2)
2376 MIPS_SYS(sys_timerfd_gettime, 2)
2377 MIPS_SYS(sys_timerfd_settime, 4)
2378 MIPS_SYS(sys_signalfd4, 4)
2379 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2380 MIPS_SYS(sys_epoll_create1, 1)
2381 MIPS_SYS(sys_dup3, 3)
2382 MIPS_SYS(sys_pipe2, 2)
2383 MIPS_SYS(sys_inotify_init1, 1)
2384 MIPS_SYS(sys_preadv, 6) /* 4330 */
2385 MIPS_SYS(sys_pwritev, 6)
2386 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2387 MIPS_SYS(sys_perf_event_open, 5)
2388 MIPS_SYS(sys_accept4, 4)
2389 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2390 MIPS_SYS(sys_fanotify_init, 2)
2391 MIPS_SYS(sys_fanotify_mark, 6)
2392 MIPS_SYS(sys_prlimit64, 4)
2393 MIPS_SYS(sys_name_to_handle_at, 5)
2394 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2395 MIPS_SYS(sys_clock_adjtime, 2)
2396 MIPS_SYS(sys_syncfs, 1)
048f6b4d 2397};
ff4f7382
RH		 2398# undef MIPS_SYS
2399# endif /* O32 */
048f6b4d 2400
590bc601
PB		 2401static int do_store_exclusive(CPUMIPSState *env)
2402{
2403 target_ulong addr;
2404 target_ulong page_addr;
2405 target_ulong val;
2406 int flags;
2407 int segv = 0;
2408 int reg;
2409 int d;
2410
5499b6ff 2411 addr = env->lladdr;
590bc601
PB		 2412 page_addr = addr & TARGET_PAGE_MASK;
2413 start_exclusive();
2414 mmap_lock();
2415 flags = page_get_flags(page_addr);
2416 if ((flags & PAGE_READ) == 0) {
2417 segv = 1;
2418 } else {
2419 reg = env->llreg & 0x1f;
2420 d = (env->llreg & 0x20) != 0;
2421 if (d) {
2422 segv = get_user_s64(val, addr);
2423 } else {
2424 segv = get_user_s32(val, addr);
2425 }
2426 if (!segv) {
2427 if (val != env->llval) {
2428 env->active_tc.gpr[reg] = 0;
2429 } else {
2430 if (d) {
2431 segv = put_user_u64(env->llnewval, addr);
2432 } else {
2433 segv = put_user_u32(env->llnewval, addr);
2434 }
2435 if (!segv) {
2436 env->active_tc.gpr[reg] = 1;
2437 }
2438 }
2439 }
2440 }
5499b6ff 2441 env->lladdr = -1;
590bc601
PB		 2442 if (!segv) {
2443 env->active_tc.PC += 4;
2444 }
2445 mmap_unlock();
2446 end_exclusive();
2447 return segv;
2448}
2449
54b2f42c
MI		 2450/* Break codes */
2451enum {
2452 BRK_OVERFLOW = 6,
2453 BRK_DIVZERO = 7
2454};
2455
2456static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2457 unsigned int code)
2458{
2459 int ret = -1;
2460
2461 switch (code) {
2462 case BRK_OVERFLOW:
2463 case BRK_DIVZERO:
2464 info->si_signo = TARGET_SIGFPE;
2465 info->si_errno = 0;
2466 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
9d2803f7 2467 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info);
54b2f42c
MI		 2468 ret = 0;
2469 break;
2470 default:
b51910ba
PJ		 2471 info->si_signo = TARGET_SIGTRAP;
2472 info->si_errno = 0;
9d2803f7 2473 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info);
b51910ba 2474 ret = 0;
54b2f42c
MI		 2475 break;
2476 }
2477
2478 return ret;
2479}
2480
048f6b4d
FB		 2481void cpu_loop(CPUMIPSState *env)
2482{
0315c31c 2483 CPUState *cs = CPU(mips_env_get_cpu(env));
c227f099 2484 target_siginfo_t info;
ff4f7382
RH		 2485 int trapnr;
2486 abi_long ret;
2487# ifdef TARGET_ABI_MIPSO32
048f6b4d 2488 unsigned int syscall_num;
ff4f7382 2489# endif
048f6b4d
FB		 2490
2491 for(;;) {
0315c31c 2492 cpu_exec_start(cs);
8642c1b8 2493 trapnr = cpu_exec(cs);
0315c31c 2494 cpu_exec_end(cs);
048f6b4d
FB		 2495 switch(trapnr) {
2496 case EXCP_SYSCALL:
b5dc7732 2497 env->active_tc.PC += 4;
ff4f7382
RH		 2498# ifdef TARGET_ABI_MIPSO32
2499 syscall_num = env->active_tc.gpr[2] - 4000;
388bb21a 2500 if (syscall_num >= sizeof(mips_syscall_args)) {
7c2f6157 2501 ret = -TARGET_ENOSYS;
388bb21a
TS		 2502 } else {
2503 int nb_args;
992f48a0
BS		 2504 abi_ulong sp_reg;
2505 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
388bb21a
TS		 2506
2507 nb_args = mips_syscall_args[syscall_num];
b5dc7732 2508 sp_reg = env->active_tc.gpr[29];
388bb21a
TS		 2509 switch (nb_args) {
2510 /* these arguments are taken from the stack */
94c19610
ACH		 2511 case 8:
2512 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2513 goto done_syscall;
2514 }
2515 case 7:
2516 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2517 goto done_syscall;
2518 }
2519 case 6:
2520 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2521 goto done_syscall;
2522 }
2523 case 5:
2524 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2525 goto done_syscall;
2526 }
388bb21a
TS		 2527 default:
2528 break;
048f6b4d 2529 }
b5dc7732
TS		 2530 ret = do_syscall(env, env->active_tc.gpr[2],
2531 env->active_tc.gpr[4],
2532 env->active_tc.gpr[5],
2533 env->active_tc.gpr[6],
2534 env->active_tc.gpr[7],
5945cfcb 2535 arg5, arg6, arg7, arg8);
388bb21a 2536 }
94c19610 2537done_syscall:
ff4f7382
RH		 2538# else
2539 ret = do_syscall(env, env->active_tc.gpr[2],
2540 env->active_tc.gpr[4], env->active_tc.gpr[5],
2541 env->active_tc.gpr[6], env->active_tc.gpr[7],
2542 env->active_tc.gpr[8], env->active_tc.gpr[9],
2543 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2544# endif /* O32 */
2eb3ae27
TB		 2545 if (ret == -TARGET_ERESTARTSYS) {
2546 env->active_tc.PC -= 4;
2547 break;
2548 }
0b1bcb00
PB		 2549 if (ret == -TARGET_QEMU_ESIGRETURN) {
2550 /* Returning from a successful sigreturn syscall.
2551 Avoid clobbering register state. */
2552 break;
2553 }
ff4f7382 2554 if ((abi_ulong)ret >= (abi_ulong)-1133) {
b5dc7732 2555 env->active_tc.gpr[7] = 1; /* error flag */
388bb21a
TS		 2556 ret = -ret;
2557 } else {
b5dc7732 2558 env->active_tc.gpr[7] = 0; /* error flag */
048f6b4d 2559 }
b5dc7732 2560 env->active_tc.gpr[2] = ret;
048f6b4d 2561 break;
ca7c2b1b
TS		 2562 case EXCP_TLBL:
2563 case EXCP_TLBS:
e6e5bd2d
WT		 2564 case EXCP_AdEL:
2565 case EXCP_AdES:
e4474235
PB		 2566 info.si_signo = TARGET_SIGSEGV;
2567 info.si_errno = 0;
2568 /* XXX: check env->error_code */
2569 info.si_code = TARGET_SEGV_MAPERR;
2570 info._sifields._sigfault._addr = env->CP0_BadVAddr;
9d2803f7 2571 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
e4474235 2572 break;
6900e84b 2573 case EXCP_CpU:
048f6b4d 2574 case EXCP_RI:
bc1ad2de
FB		 2575 info.si_signo = TARGET_SIGILL;
2576 info.si_errno = 0;
2577 info.si_code = 0;
9d2803f7 2578 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
048f6b4d 2579 break;
106ec879
FB		 2580 case EXCP_INTERRUPT:
2581 /* just indicate that signals should be handled asap */
2582 break;
d08b2a28
PB		 2583 case EXCP_DEBUG:
2584 {
2585 int sig;
2586
db6b81d4 2587 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d08b2a28
PB		 2588 if (sig)
2589 {
2590 info.si_signo = sig;
2591 info.si_errno = 0;
2592 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 2593 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
d08b2a28
PB		 2594 }
2595 }
2596 break;
590bc601
PB		 2597 case EXCP_SC:
2598 if (do_store_exclusive(env)) {
2599 info.si_signo = TARGET_SIGSEGV;
2600 info.si_errno = 0;
2601 info.si_code = TARGET_SEGV_MAPERR;
2602 info._sifields._sigfault._addr = env->active_tc.PC;
9d2803f7 2603 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
590bc601
PB		 2604 }
2605 break;
853c3240
JL		 2606 case EXCP_DSPDIS:
2607 info.si_signo = TARGET_SIGILL;
2608 info.si_errno = 0;
2609 info.si_code = TARGET_ILL_ILLOPC;
9d2803f7 2610 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
853c3240 2611 break;
54b2f42c
MI		 2612 /* The code below was inspired by the MIPS Linux kernel trap
2613 * handling code in arch/mips/kernel/traps.c.
2614 */
2615 case EXCP_BREAK:
2616 {
2617 abi_ulong trap_instr;
2618 unsigned int code;
2619
a0333817
KCY		 2620 if (env->hflags & MIPS_HFLAG_M16) {
2621 if (env->insn_flags & ASE_MICROMIPS) {
2622 /* microMIPS mode */
1308c464
KCY		 2623 ret = get_user_u16(trap_instr, env->active_tc.PC);
2624 if (ret != 0) {
2625 goto error;
2626 }
a0333817 2627
1308c464
KCY		 2628 if ((trap_instr >> 10) == 0x11) {
2629 /* 16-bit instruction */
2630 code = trap_instr & 0xf;
2631 } else {
2632 /* 32-bit instruction */
2633 abi_ulong instr_lo;
2634
2635 ret = get_user_u16(instr_lo,
2636 env->active_tc.PC + 2);
2637 if (ret != 0) {
2638 goto error;
2639 }
2640 trap_instr = (trap_instr << 16) | instr_lo;
2641 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2642 /* Unfortunately, microMIPS also suffers from
2643 the old assembler bug... */
2644 if (code >= (1 << 10)) {
2645 code >>= 10;
2646 }
2647 }
a0333817
KCY		 2648 } else {
2649 /* MIPS16e mode */
2650 ret = get_user_u16(trap_instr, env->active_tc.PC);
2651 if (ret != 0) {
2652 goto error;
2653 }
2654 code = (trap_instr >> 6) & 0x3f;
a0333817
KCY		 2655 }
2656 } else {
f01a361b 2657 ret = get_user_u32(trap_instr, env->active_tc.PC);
1308c464
KCY		 2658 if (ret != 0) {
2659 goto error;
2660 }
54b2f42c 2661
1308c464
KCY		 2662 /* As described in the original Linux kernel code, the
2663 * below checks on 'code' are to work around an old
2664 * assembly bug.
2665 */
2666 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2667 if (code >= (1 << 10)) {
2668 code >>= 10;
2669 }
54b2f42c
MI		 2670 }
2671
2672 if (do_break(env, &info, code) != 0) {
2673 goto error;
2674 }
2675 }
2676 break;
2677 case EXCP_TRAP:
2678 {
2679 abi_ulong trap_instr;
2680 unsigned int code = 0;
2681
a0333817
KCY		 2682 if (env->hflags & MIPS_HFLAG_M16) {
2683 /* microMIPS mode */
2684 abi_ulong instr[2];
2685
2686 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2687 get_user_u16(instr[1], env->active_tc.PC + 2);
2688
2689 trap_instr = (instr[0] << 16) | instr[1];
2690 } else {
f01a361b 2691 ret = get_user_u32(trap_instr, env->active_tc.PC);
a0333817
KCY		 2692 }
2693
54b2f42c
MI		 2694 if (ret != 0) {
2695 goto error;
2696 }
2697
2698 /* The immediate versions don't provide a code. */
2699 if (!(trap_instr & 0xFC000000)) {
a0333817
KCY		 2700 if (env->hflags & MIPS_HFLAG_M16) {
2701 /* microMIPS mode */
2702 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2703 } else {
2704 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2705 }
54b2f42c
MI		 2706 }
2707
2708 if (do_break(env, &info, code) != 0) {
2709 goto error;
2710 }
2711 }
2712 break;
048f6b4d 2713 default:
54b2f42c 2714error:
120a9848 2715 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
048f6b4d
FB		 2716 abort();
2717 }
2718 process_pending_signals(env);
2719 }
2720}
2721#endif
2722
d962783e
JL		 2723#ifdef TARGET_OPENRISC
2724
2725void cpu_loop(CPUOpenRISCState *env)
2726{
878096ee 2727 CPUState *cs = CPU(openrisc_env_get_cpu(env));
d962783e 2728 int trapnr, gdbsig;
7fe7231a 2729 abi_long ret;
d962783e
JL		 2730
2731 for (;;) {
b040bc9c 2732 cpu_exec_start(cs);
8642c1b8 2733 trapnr = cpu_exec(cs);
b040bc9c 2734 cpu_exec_end(cs);
d962783e
JL		 2735 gdbsig = 0;
2736
2737 switch (trapnr) {
2738 case EXCP_RESET:
120a9848 2739 qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc);
4d1275c2 2740 exit(EXIT_FAILURE);
d962783e
JL		 2741 break;
2742 case EXCP_BUSERR:
120a9848 2743 qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc);
a86b3c64 2744 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2745 break;
2746 case EXCP_DPF:
2747 case EXCP_IPF:
878096ee 2748 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2749 gdbsig = TARGET_SIGSEGV;
2750 break;
2751 case EXCP_TICK:
120a9848 2752 qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc);
d962783e
JL		 2753 break;
2754 case EXCP_ALIGN:
120a9848 2755 qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc);
a86b3c64 2756 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2757 break;
2758 case EXCP_ILLEGAL:
120a9848 2759 qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc);
a86b3c64 2760 gdbsig = TARGET_SIGILL;
d962783e
JL		 2761 break;
2762 case EXCP_INT:
120a9848 2763 qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc);
d962783e
JL		 2764 break;
2765 case EXCP_DTLBMISS:
2766 case EXCP_ITLBMISS:
120a9848 2767 qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n");
d962783e
JL		 2768 break;
2769 case EXCP_RANGE:
120a9848 2770 qemu_log_mask(CPU_LOG_INT, "\nRange\n");
a86b3c64 2771 gdbsig = TARGET_SIGSEGV;
d962783e
JL		 2772 break;
2773 case EXCP_SYSCALL:
2774 env->pc += 4; /* 0xc00; */
7fe7231a
TB		 2775 ret = do_syscall(env,
2776 env->gpr[11], /* return value */
2777 env->gpr[3], /* r3 - r7 are params */
2778 env->gpr[4],
2779 env->gpr[5],
2780 env->gpr[6],
2781 env->gpr[7],
2782 env->gpr[8], 0, 0);
2783 if (ret == -TARGET_ERESTARTSYS) {
2784 env->pc -= 4;
2785 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2786 env->gpr[11] = ret;
2787 }
d962783e
JL		 2788 break;
2789 case EXCP_FPE:
120a9848 2790 qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n");
d962783e
JL		 2791 break;
2792 case EXCP_TRAP:
120a9848 2793 qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
a86b3c64 2794 gdbsig = TARGET_SIGTRAP;
d962783e
JL		 2795 break;
2796 case EXCP_NR:
120a9848 2797 qemu_log_mask(CPU_LOG_INT, "\nNR\n");
d962783e
JL		 2798 break;
2799 default:
120a9848 2800 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
d962783e 2801 trapnr);
d962783e
JL		 2802 gdbsig = TARGET_SIGILL;
2803 break;
2804 }
2805 if (gdbsig) {
db6b81d4 2806 gdb_handlesig(cs, gdbsig);
d962783e 2807 if (gdbsig != TARGET_SIGTRAP) {
4d1275c2 2808 exit(EXIT_FAILURE);
d962783e
JL		 2809 }
2810 }
2811
2812 process_pending_signals(env);
2813 }
2814}
2815
2816#endif /* TARGET_OPENRISC */
2817
fdf9b3e8 2818#ifdef TARGET_SH4
05390248 2819void cpu_loop(CPUSH4State *env)
fdf9b3e8 2820{
878096ee 2821 CPUState *cs = CPU(sh_env_get_cpu(env));
fdf9b3e8 2822 int trapnr, ret;
c227f099 2823 target_siginfo_t info;
3b46e624 2824
fdf9b3e8 2825 while (1) {
b040bc9c 2826 cpu_exec_start(cs);
8642c1b8 2827 trapnr = cpu_exec(cs);
b040bc9c 2828 cpu_exec_end(cs);
3b46e624 2829
fdf9b3e8
FB		 2830 switch (trapnr) {
2831 case 0x160:
0b6d3ae0 2832 env->pc += 2;
5fafdf24
TS		 2833 ret = do_syscall(env,
2834 env->gregs[3],
2835 env->gregs[4],
2836 env->gregs[5],
2837 env->gregs[6],
2838 env->gregs[7],
2839 env->gregs[0],
5945cfcb
PM		 2840 env->gregs[1],
2841 0, 0);
ba412496
TB		 2842 if (ret == -TARGET_ERESTARTSYS) {
2843 env->pc -= 2;
2844 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2845 env->gregs[0] = ret;
2846 }
fdf9b3e8 2847 break;
c3b5bc8a
TS		 2848 case EXCP_INTERRUPT:
2849 /* just indicate that signals should be handled asap */
2850 break;
355fb23d
PB		 2851 case EXCP_DEBUG:
2852 {
2853 int sig;
2854
db6b81d4 2855 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
355fb23d
PB		 2856 if (sig)
2857 {
2858 info.si_signo = sig;
2859 info.si_errno = 0;
2860 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 2861 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
355fb23d
PB		 2862 }
2863 }
2864 break;
c3b5bc8a
TS		 2865 case 0xa0:
2866 case 0xc0:
a86b3c64 2867 info.si_signo = TARGET_SIGSEGV;
c3b5bc8a
TS		 2868 info.si_errno = 0;
2869 info.si_code = TARGET_SEGV_MAPERR;
2870 info._sifields._sigfault._addr = env->tea;
9d2803f7 2871 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
c3b5bc8a
TS		 2872 break;
2873
fdf9b3e8
FB		 2874 default:
2875 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2876 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 2877 exit(EXIT_FAILURE);
fdf9b3e8
FB		 2878 }
2879 process_pending_signals (env);
2880 }
2881}
2882#endif
2883
48733d19 2884#ifdef TARGET_CRIS
05390248 2885void cpu_loop(CPUCRISState *env)
48733d19 2886{
878096ee 2887 CPUState *cs = CPU(cris_env_get_cpu(env));
48733d19 2888 int trapnr, ret;
c227f099 2889 target_siginfo_t info;
48733d19
TS		 2890
2891 while (1) {
b040bc9c 2892 cpu_exec_start(cs);
8642c1b8 2893 trapnr = cpu_exec(cs);
b040bc9c 2894 cpu_exec_end(cs);
48733d19
TS		 2895 switch (trapnr) {
2896 case 0xaa:
2897 {
a86b3c64 2898 info.si_signo = TARGET_SIGSEGV;
48733d19
TS		 2899 info.si_errno = 0;
2900 /* XXX: check env->error_code */
2901 info.si_code = TARGET_SEGV_MAPERR;
e00c1e71 2902 info._sifields._sigfault._addr = env->pregs[PR_EDA];
9d2803f7 2903 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
48733d19
TS		 2904 }
2905 break;
b6d3abda
EI		 2906 case EXCP_INTERRUPT:
2907 /* just indicate that signals should be handled asap */
2908 break;
48733d19
TS		 2909 case EXCP_BREAK:
2910 ret = do_syscall(env,
2911 env->regs[9],
2912 env->regs[10],
2913 env->regs[11],
2914 env->regs[12],
2915 env->regs[13],
2916 env->pregs[7],
5945cfcb
PM		 2917 env->pregs[11],
2918 0, 0);
62050865
TB		 2919 if (ret == -TARGET_ERESTARTSYS) {
2920 env->pc -= 2;
2921 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2922 env->regs[10] = ret;
2923 }
48733d19
TS		 2924 break;
2925 case EXCP_DEBUG:
2926 {
2927 int sig;
2928
db6b81d4 2929 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
48733d19
TS		 2930 if (sig)
2931 {
2932 info.si_signo = sig;
2933 info.si_errno = 0;
2934 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 2935 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
48733d19
TS		 2936 }
2937 }
2938 break;
2939 default:
2940 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2941 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 2942 exit(EXIT_FAILURE);
48733d19
TS		 2943 }
2944 process_pending_signals (env);
2945 }
2946}
2947#endif
2948
b779e29e 2949#ifdef TARGET_MICROBLAZE
05390248 2950void cpu_loop(CPUMBState *env)
b779e29e 2951{
878096ee 2952 CPUState *cs = CPU(mb_env_get_cpu(env));
b779e29e 2953 int trapnr, ret;
c227f099 2954 target_siginfo_t info;
b779e29e
EI		 2955
2956 while (1) {
b040bc9c 2957 cpu_exec_start(cs);
8642c1b8 2958 trapnr = cpu_exec(cs);
b040bc9c 2959 cpu_exec_end(cs);
b779e29e
EI		 2960 switch (trapnr) {
2961 case 0xaa:
2962 {
a86b3c64 2963 info.si_signo = TARGET_SIGSEGV;
b779e29e
EI		 2964 info.si_errno = 0;
2965 /* XXX: check env->error_code */
2966 info.si_code = TARGET_SEGV_MAPERR;
2967 info._sifields._sigfault._addr = 0;
9d2803f7 2968 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
b779e29e
EI		 2969 }
2970 break;
2971 case EXCP_INTERRUPT:
2972 /* just indicate that signals should be handled asap */
2973 break;
2974 case EXCP_BREAK:
2975 /* Return address is 4 bytes after the call. */
2976 env->regs[14] += 4;
d7dce494 2977 env->sregs[SR_PC] = env->regs[14];
b779e29e
EI		 2978 ret = do_syscall(env,
2979 env->regs[12],
2980 env->regs[5],
2981 env->regs[6],
2982 env->regs[7],
2983 env->regs[8],
2984 env->regs[9],
5945cfcb
PM		 2985 env->regs[10],
2986 0, 0);
4134ecfe
TB		 2987 if (ret == -TARGET_ERESTARTSYS) {
2988 /* Wind back to before the syscall. */
2989 env->sregs[SR_PC] -= 4;
2990 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2991 env->regs[3] = ret;
2992 }
d7749ab7
PM		 2993 /* All syscall exits result in guest r14 being equal to the
2994 * PC we return to, because the kernel syscall exit "rtbd" does
2995 * this. (This is true even for sigreturn(); note that r14 is
2996 * not a userspace-usable register, as the kernel may clobber it
2997 * at any point.)
2998 */
2999 env->regs[14] = env->sregs[SR_PC];
b779e29e 3000 break;
b76da7e3
EI		 3001 case EXCP_HW_EXCP:
3002 env->regs[17] = env->sregs[SR_PC] + 4;
3003 if (env->iflags & D_FLAG) {
3004 env->sregs[SR_ESR] |= 1 << 12;
3005 env->sregs[SR_PC] -= 4;
b4916d7b 3006 /* FIXME: if branch was immed, replay the imm as well. */
b76da7e3
EI		 3007 }
3008
3009 env->iflags &= ~(IMM_FLAG | D_FLAG);
3010
3011 switch (env->sregs[SR_ESR] & 31) {
22a78d64 3012 case ESR_EC_DIVZERO:
a86b3c64 3013 info.si_signo = TARGET_SIGFPE;
22a78d64
EI		 3014 info.si_errno = 0;
3015 info.si_code = TARGET_FPE_FLTDIV;
3016 info._sifields._sigfault._addr = 0;
9d2803f7 3017 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
22a78d64 3018 break;
b76da7e3 3019 case ESR_EC_FPU:
a86b3c64 3020 info.si_signo = TARGET_SIGFPE;
b76da7e3
EI		 3021 info.si_errno = 0;
3022 if (env->sregs[SR_FSR] & FSR_IO) {
3023 info.si_code = TARGET_FPE_FLTINV;
3024 }
3025 if (env->sregs[SR_FSR] & FSR_DZ) {
3026 info.si_code = TARGET_FPE_FLTDIV;
3027 }
3028 info._sifields._sigfault._addr = 0;
9d2803f7 3029 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
b76da7e3
EI		 3030 break;
3031 default:
3032 printf ("Unhandled hw-exception: 0x%x\n",
2e42d52d 3033 env->sregs[SR_ESR] & ESR_EC_MASK);
878096ee 3034 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3035 exit(EXIT_FAILURE);
b76da7e3
EI		 3036 break;
3037 }
3038 break;
b779e29e
EI		 3039 case EXCP_DEBUG:
3040 {
3041 int sig;
3042
db6b81d4 3043 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
b779e29e
EI		 3044 if (sig)
3045 {
3046 info.si_signo = sig;
3047 info.si_errno = 0;
3048 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 3049 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
b779e29e
EI		 3050 }
3051 }
3052 break;
3053 default:
3054 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3055 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3056 exit(EXIT_FAILURE);
b779e29e
EI		 3057 }
3058 process_pending_signals (env);
3059 }
3060}
3061#endif
3062
e6e5906b
PB		 3063#ifdef TARGET_M68K
3064
3065void cpu_loop(CPUM68KState *env)
3066{
878096ee 3067 CPUState *cs = CPU(m68k_env_get_cpu(env));
e6e5906b
PB		 3068 int trapnr;
3069 unsigned int n;
c227f099 3070 target_siginfo_t info;
0429a971 3071 TaskState *ts = cs->opaque;
3b46e624 3072
e6e5906b 3073 for(;;) {
b040bc9c 3074 cpu_exec_start(cs);
8642c1b8 3075 trapnr = cpu_exec(cs);
b040bc9c 3076 cpu_exec_end(cs);
e6e5906b
PB		 3077 switch(trapnr) {
3078 case EXCP_ILLEGAL:
3079 {
3080 if (ts->sim_syscalls) {
3081 uint16_t nr;
d8d5119c 3082 get_user_u16(nr, env->pc + 2);
e6e5906b
PB		 3083 env->pc += 4;
3084 do_m68k_simcall(env, nr);
3085 } else {
3086 goto do_sigill;
3087 }
3088 }
3089 break;
a87295e8 3090 case EXCP_HALT_INSN:
e6e5906b 3091 /* Semihosing syscall. */
a87295e8 3092 env->pc += 4;
e6e5906b
PB		 3093 do_m68k_semihosting(env, env->dregs[0]);
3094 break;
3095 case EXCP_LINEA:
3096 case EXCP_LINEF:
3097 case EXCP_UNSUPPORTED:
3098 do_sigill:
a86b3c64 3099 info.si_signo = TARGET_SIGILL;
e6e5906b
PB		 3100 info.si_errno = 0;
3101 info.si_code = TARGET_ILL_ILLOPN;
3102 info._sifields._sigfault._addr = env->pc;
9d2803f7 3103 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
e6e5906b
PB		 3104 break;
3105 case EXCP_TRAP0:
3106 {
7ccb84a9 3107 abi_long ret;
e6e5906b
PB		 3108 ts->sim_syscalls = 0;
3109 n = env->dregs[0];
3110 env->pc += 2;
7ccb84a9
TB		 3111 ret = do_syscall(env,
3112 n,
3113 env->dregs[1],
3114 env->dregs[2],
3115 env->dregs[3],
3116 env->dregs[4],
3117 env->dregs[5],
3118 env->aregs[0],
3119 0, 0);
3120 if (ret == -TARGET_ERESTARTSYS) {
3121 env->pc -= 2;
3122 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3123 env->dregs[0] = ret;
3124 }
e6e5906b
PB		 3125 }
3126 break;
3127 case EXCP_INTERRUPT:
3128 /* just indicate that signals should be handled asap */
3129 break;
3130 case EXCP_ACCESS:
3131 {
a86b3c64 3132 info.si_signo = TARGET_SIGSEGV;
e6e5906b
PB		 3133 info.si_errno = 0;
3134 /* XXX: check env->error_code */
3135 info.si_code = TARGET_SEGV_MAPERR;
3136 info._sifields._sigfault._addr = env->mmu.ar;
9d2803f7 3137 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
e6e5906b
PB		 3138 }
3139 break;
3140 case EXCP_DEBUG:
3141 {
3142 int sig;
3143
db6b81d4 3144 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
e6e5906b
PB		 3145 if (sig)
3146 {
3147 info.si_signo = sig;
3148 info.si_errno = 0;
3149 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 3150 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
e6e5906b
PB		 3151 }
3152 }
3153 break;
3154 default:
120a9848 3155 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
e6e5906b
PB		 3156 abort();
3157 }
3158 process_pending_signals(env);
3159 }
3160}
3161#endif /* TARGET_M68K */
3162
7a3148a9 3163#ifdef TARGET_ALPHA
6910b8f6
RH		 3164static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3165{
3166 target_ulong addr, val, tmp;
3167 target_siginfo_t info;
3168 int ret = 0;
3169
3170 addr = env->lock_addr;
3171 tmp = env->lock_st_addr;
3172 env->lock_addr = -1;
3173 env->lock_st_addr = 0;
3174
3175 start_exclusive();
3176 mmap_lock();
3177
3178 if (addr == tmp) {
3179 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3180 goto do_sigsegv;
3181 }
3182
3183 if (val == env->lock_value) {
3184 tmp = env->ir[reg];
3185 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3186 goto do_sigsegv;
3187 }
3188 ret = 1;
3189 }
3190 }
3191 env->ir[reg] = ret;
3192 env->pc += 4;
3193
3194 mmap_unlock();
3195 end_exclusive();
3196 return;
3197
3198 do_sigsegv:
3199 mmap_unlock();
3200 end_exclusive();
3201
3202 info.si_signo = TARGET_SIGSEGV;
3203 info.si_errno = 0;
3204 info.si_code = TARGET_SEGV_MAPERR;
3205 info._sifields._sigfault._addr = addr;
9d2803f7 3206 queue_signal(env, TARGET_SIGSEGV, QEMU_SI_FAULT, &info);
6910b8f6
RH		 3207}
3208
05390248 3209void cpu_loop(CPUAlphaState *env)
7a3148a9 3210{
878096ee 3211 CPUState *cs = CPU(alpha_env_get_cpu(env));
e96efcfc 3212 int trapnr;
c227f099 3213 target_siginfo_t info;
6049f4f8 3214 abi_long sysret;
3b46e624 3215
7a3148a9 3216 while (1) {
b040bc9c 3217 cpu_exec_start(cs);
8642c1b8 3218 trapnr = cpu_exec(cs);
b040bc9c 3219 cpu_exec_end(cs);
3b46e624 3220
ac316ca4
RH		 3221 /* All of the traps imply a transition through PALcode, which
3222 implies an REI instruction has been executed. Which means
3223 that the intr_flag should be cleared. */
3224 env->intr_flag = 0;
3225
7a3148a9
JM		 3226 switch (trapnr) {
3227 case EXCP_RESET:
3228 fprintf(stderr, "Reset requested. Exit\n");
4d1275c2 3229 exit(EXIT_FAILURE);
7a3148a9
JM		 3230 break;
3231 case EXCP_MCHK:
3232 fprintf(stderr, "Machine check exception. Exit\n");
4d1275c2 3233 exit(EXIT_FAILURE);
7a3148a9 3234 break;
07b6c13b
RH		 3235 case EXCP_SMP_INTERRUPT:
3236 case EXCP_CLK_INTERRUPT:
3237 case EXCP_DEV_INTERRUPT:
5fafdf24 3238 fprintf(stderr, "External interrupt. Exit\n");
4d1275c2 3239 exit(EXIT_FAILURE);
7a3148a9 3240 break;
07b6c13b 3241 case EXCP_MMFAULT:
6910b8f6 3242 env->lock_addr = -1;
6049f4f8
RH		 3243 info.si_signo = TARGET_SIGSEGV;
3244 info.si_errno = 0;
129d8aa5 3245 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
0be1d07c 3246 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
129d8aa5 3247 info._sifields._sigfault._addr = env->trap_arg0;
9d2803f7 3248 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
7a3148a9 3249 break;
7a3148a9 3250 case EXCP_UNALIGN:
6910b8f6 3251 env->lock_addr = -1;
6049f4f8
RH		 3252 info.si_signo = TARGET_SIGBUS;
3253 info.si_errno = 0;
3254 info.si_code = TARGET_BUS_ADRALN;
129d8aa5 3255 info._sifields._sigfault._addr = env->trap_arg0;
9d2803f7 3256 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
7a3148a9
JM		 3257 break;
3258 case EXCP_OPCDEC:
6049f4f8 3259 do_sigill:
6910b8f6 3260 env->lock_addr = -1;
6049f4f8
RH		 3261 info.si_signo = TARGET_SIGILL;
3262 info.si_errno = 0;
3263 info.si_code = TARGET_ILL_ILLOPC;
3264 info._sifields._sigfault._addr = env->pc;
9d2803f7 3265 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
7a3148a9 3266 break;
07b6c13b
RH		 3267 case EXCP_ARITH:
3268 env->lock_addr = -1;
3269 info.si_signo = TARGET_SIGFPE;
3270 info.si_errno = 0;
3271 info.si_code = TARGET_FPE_FLTINV;
3272 info._sifields._sigfault._addr = env->pc;
9d2803f7 3273 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
07b6c13b 3274 break;
7a3148a9 3275 case EXCP_FEN:
6049f4f8 3276 /* No-op. Linux simply re-enables the FPU. */
7a3148a9 3277 break;
07b6c13b 3278 case EXCP_CALL_PAL:
6910b8f6 3279 env->lock_addr = -1;
07b6c13b 3280 switch (env->error_code) {
6049f4f8
RH		 3281 case 0x80:
3282 /* BPT */
3283 info.si_signo = TARGET_SIGTRAP;
3284 info.si_errno = 0;
3285 info.si_code = TARGET_TRAP_BRKPT;
3286 info._sifields._sigfault._addr = env->pc;
9d2803f7 3287 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
6049f4f8
RH		 3288 break;
3289 case 0x81:
3290 /* BUGCHK */
3291 info.si_signo = TARGET_SIGTRAP;
3292 info.si_errno = 0;
3293 info.si_code = 0;
3294 info._sifields._sigfault._addr = env->pc;
9d2803f7 3295 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
6049f4f8
RH		 3296 break;
3297 case 0x83:
3298 /* CALLSYS */
3299 trapnr = env->ir[IR_V0];
3300 sysret = do_syscall(env, trapnr,
3301 env->ir[IR_A0], env->ir[IR_A1],
3302 env->ir[IR_A2], env->ir[IR_A3],
5945cfcb
PM		 3303 env->ir[IR_A4], env->ir[IR_A5],
3304 0, 0);
338c858c
TB		 3305 if (sysret == -TARGET_ERESTARTSYS) {
3306 env->pc -= 4;
3307 break;
3308 }
3309 if (sysret == -TARGET_QEMU_ESIGRETURN) {
a5b3b13b
RH		 3310 break;
3311 }
3312 /* Syscall writes 0 to V0 to bypass error check, similar
0e141977
RH		 3313 to how this is handled internal to Linux kernel.
3314 (Ab)use trapnr temporarily as boolean indicating error. */
3315 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3316 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3317 env->ir[IR_A3] = trapnr;
6049f4f8
RH		 3318 break;
3319 case 0x86:
3320 /* IMB */
3321 /* ??? We can probably elide the code using page_unprotect
3322 that is checking for self-modifying code. Instead we
3323 could simply call tb_flush here. Until we work out the
3324 changes required to turn off the extra write protection,
3325 this can be a no-op. */
3326 break;
3327 case 0x9E:
3328 /* RDUNIQUE */
3329 /* Handled in the translator for usermode. */
3330 abort();
3331 case 0x9F:
3332 /* WRUNIQUE */
3333 /* Handled in the translator for usermode. */
3334 abort();
3335 case 0xAA:
3336 /* GENTRAP */
3337 info.si_signo = TARGET_SIGFPE;
3338 switch (env->ir[IR_A0]) {
3339 case TARGET_GEN_INTOVF:
3340 info.si_code = TARGET_FPE_INTOVF;
3341 break;
3342 case TARGET_GEN_INTDIV:
3343 info.si_code = TARGET_FPE_INTDIV;
3344 break;
3345 case TARGET_GEN_FLTOVF:
3346 info.si_code = TARGET_FPE_FLTOVF;
3347 break;
3348 case TARGET_GEN_FLTUND:
3349 info.si_code = TARGET_FPE_FLTUND;
3350 break;
3351 case TARGET_GEN_FLTINV:
3352 info.si_code = TARGET_FPE_FLTINV;
3353 break;
3354 case TARGET_GEN_FLTINE:
3355 info.si_code = TARGET_FPE_FLTRES;
3356 break;
3357 case TARGET_GEN_ROPRAND:
3358 info.si_code = 0;
3359 break;
3360 default:
3361 info.si_signo = TARGET_SIGTRAP;
3362 info.si_code = 0;
3363 break;
3364 }
3365 info.si_errno = 0;
3366 info._sifields._sigfault._addr = env->pc;
9d2803f7 3367 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
6049f4f8
RH		 3368 break;
3369 default:
3370 goto do_sigill;
3371 }
7a3148a9 3372 break;
7a3148a9 3373 case EXCP_DEBUG:
db6b81d4 3374 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
6049f4f8 3375 if (info.si_signo) {
6910b8f6 3376 env->lock_addr = -1;
6049f4f8
RH		 3377 info.si_errno = 0;
3378 info.si_code = TARGET_TRAP_BRKPT;
9d2803f7 3379 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
7a3148a9
JM		 3380 }
3381 break;
6910b8f6
RH		 3382 case EXCP_STL_C:
3383 case EXCP_STQ_C:
3384 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3385 break;
d0f20495
RH		 3386 case EXCP_INTERRUPT:
3387 /* Just indicate that signals should be handled asap. */
3388 break;
7a3148a9
JM		 3389 default:
3390 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3391 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3392 exit(EXIT_FAILURE);
7a3148a9
JM		 3393 }
3394 process_pending_signals (env);
3395 }
3396}
3397#endif /* TARGET_ALPHA */
3398
a4c075f1
UH		 3399#ifdef TARGET_S390X
3400void cpu_loop(CPUS390XState *env)
3401{
878096ee 3402 CPUState *cs = CPU(s390_env_get_cpu(env));
d5a103cd 3403 int trapnr, n, sig;
a4c075f1 3404 target_siginfo_t info;
d5a103cd 3405 target_ulong addr;
47405ab6 3406 abi_long ret;
a4c075f1
UH		 3407
3408 while (1) {
b040bc9c 3409 cpu_exec_start(cs);
8642c1b8 3410 trapnr = cpu_exec(cs);
b040bc9c 3411 cpu_exec_end(cs);
a4c075f1
UH		 3412 switch (trapnr) {
3413 case EXCP_INTERRUPT:
d5a103cd 3414 /* Just indicate that signals should be handled asap. */
a4c075f1 3415 break;
a4c075f1 3416
d5a103cd
RH		 3417 case EXCP_SVC:
3418 n = env->int_svc_code;
3419 if (!n) {
3420 /* syscalls > 255 */
3421 n = env->regs[1];
a4c075f1 3422 }
d5a103cd 3423 env->psw.addr += env->int_svc_ilen;
47405ab6
TB		 3424 ret = do_syscall(env, n, env->regs[2], env->regs[3],
3425 env->regs[4], env->regs[5],
3426 env->regs[6], env->regs[7], 0, 0);
3427 if (ret == -TARGET_ERESTARTSYS) {
3428 env->psw.addr -= env->int_svc_ilen;
3429 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3430 env->regs[2] = ret;
3431 }
a4c075f1 3432 break;
d5a103cd
RH		 3433
3434 case EXCP_DEBUG:
db6b81d4 3435 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d5a103cd
RH		 3436 if (sig) {
3437 n = TARGET_TRAP_BRKPT;
3438 goto do_signal_pc;
a4c075f1
UH		 3439 }
3440 break;
d5a103cd
RH		 3441 case EXCP_PGM:
3442 n = env->int_pgm_code;
3443 switch (n) {
3444 case PGM_OPERATION:
3445 case PGM_PRIVILEGED:
a86b3c64 3446 sig = TARGET_SIGILL;
d5a103cd
RH		 3447 n = TARGET_ILL_ILLOPC;
3448 goto do_signal_pc;
3449 case PGM_PROTECTION:
3450 case PGM_ADDRESSING:
a86b3c64 3451 sig = TARGET_SIGSEGV;
a4c075f1 3452 /* XXX: check env->error_code */
d5a103cd
RH		 3453 n = TARGET_SEGV_MAPERR;
3454 addr = env->__excp_addr;
3455 goto do_signal;
3456 case PGM_EXECUTE:
3457 case PGM_SPECIFICATION:
3458 case PGM_SPECIAL_OP:
3459 case PGM_OPERAND:
3460 do_sigill_opn:
a86b3c64 3461 sig = TARGET_SIGILL;
d5a103cd
RH		 3462 n = TARGET_ILL_ILLOPN;
3463 goto do_signal_pc;
3464
3465 case PGM_FIXPT_OVERFLOW:
a86b3c64 3466 sig = TARGET_SIGFPE;
d5a103cd
RH		 3467 n = TARGET_FPE_INTOVF;
3468 goto do_signal_pc;
3469 case PGM_FIXPT_DIVIDE:
a86b3c64 3470 sig = TARGET_SIGFPE;
d5a103cd
RH		 3471 n = TARGET_FPE_INTDIV;
3472 goto do_signal_pc;
3473
3474 case PGM_DATA:
3475 n = (env->fpc >> 8) & 0xff;
3476 if (n == 0xff) {
3477 /* compare-and-trap */
3478 goto do_sigill_opn;
3479 } else {
3480 /* An IEEE exception, simulated or otherwise. */
3481 if (n & 0x80) {
3482 n = TARGET_FPE_FLTINV;
3483 } else if (n & 0x40) {
3484 n = TARGET_FPE_FLTDIV;
3485 } else if (n & 0x20) {
3486 n = TARGET_FPE_FLTOVF;
3487 } else if (n & 0x10) {
3488 n = TARGET_FPE_FLTUND;
3489 } else if (n & 0x08) {
3490 n = TARGET_FPE_FLTRES;
3491 } else {
3492 /* ??? Quantum exception; BFP, DFP error. */
3493 goto do_sigill_opn;
3494 }
a86b3c64 3495 sig = TARGET_SIGFPE;
d5a103cd
RH		 3496 goto do_signal_pc;
3497 }
3498
3499 default:
3500 fprintf(stderr, "Unhandled program exception: %#x\n", n);
878096ee 3501 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3502 exit(EXIT_FAILURE);
a4c075f1
UH		 3503 }
3504 break;
d5a103cd
RH		 3505
3506 do_signal_pc:
3507 addr = env->psw.addr;
3508 do_signal:
3509 info.si_signo = sig;
3510 info.si_errno = 0;
3511 info.si_code = n;
3512 info._sifields._sigfault._addr = addr;
9d2803f7 3513 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
a4c075f1 3514 break;
d5a103cd 3515
a4c075f1 3516 default:
d5a103cd 3517 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
878096ee 3518 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3519 exit(EXIT_FAILURE);
a4c075f1
UH		 3520 }
3521 process_pending_signals (env);
3522 }
3523}
3524
3525#endif /* TARGET_S390X */
3526
b16189b2
CG		 3527#ifdef TARGET_TILEGX
3528
b16189b2
CG		 3529static void gen_sigill_reg(CPUTLGState *env)
3530{
3531 target_siginfo_t info;
3532
3533 info.si_signo = TARGET_SIGILL;
3534 info.si_errno = 0;
3535 info.si_code = TARGET_ILL_PRVREG;
3536 info._sifields._sigfault._addr = env->pc;
9d2803f7 3537 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
b16189b2
CG		 3538}
3539
a0577d2a 3540static void do_signal(CPUTLGState *env, int signo, int sigcode)
dd8070d8
CG		 3541{
3542 target_siginfo_t info;
3543
a0577d2a 3544 info.si_signo = signo;
dd8070d8 3545 info.si_errno = 0;
dd8070d8 3546 info._sifields._sigfault._addr = env->pc;
a0577d2a
RH		 3547
3548 if (signo == TARGET_SIGSEGV) {
3549 /* The passed in sigcode is a dummy; check for a page mapping
3550 and pass either MAPERR or ACCERR. */
3551 target_ulong addr = env->excaddr;
3552 info._sifields._sigfault._addr = addr;
3553 if (page_check_range(addr, 1, PAGE_VALID) < 0) {
3554 sigcode = TARGET_SEGV_MAPERR;
3555 } else {
3556 sigcode = TARGET_SEGV_ACCERR;
3557 }
3558 }
3559 info.si_code = sigcode;
3560
9d2803f7 3561 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
dd8070d8
CG		 3562}
3563
a0577d2a
RH		 3564static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
3565{
3566 env->excaddr = addr;
3567 do_signal(env, TARGET_SIGSEGV, 0);
3568}
3569
0583b233
RH		 3570static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
3571{
3572 if (unlikely(reg >= TILEGX_R_COUNT)) {
3573 switch (reg) {
3574 case TILEGX_R_SN:
3575 case TILEGX_R_ZERO:
3576 return;
3577 case TILEGX_R_IDN0:
3578 case TILEGX_R_IDN1:
3579 case TILEGX_R_UDN0:
3580 case TILEGX_R_UDN1:
3581 case TILEGX_R_UDN2:
3582 case TILEGX_R_UDN3:
3583 gen_sigill_reg(env);
3584 return;
3585 default:
3586 g_assert_not_reached();
3587 }
3588 }
3589 env->regs[reg] = val;
3590}
3591
3592/*
3593 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
3594 * memory at the address held in the first source register. If the values are
3595 * not equal, then no memory operation is performed. If the values are equal,
3596 * the 8-byte quantity from the second source register is written into memory
3597 * at the address held in the first source register. In either case, the result
3598 * of the instruction is the value read from memory. The compare and write to
3599 * memory are atomic and thus can be used for synchronization purposes. This
3600 * instruction only operates for addresses aligned to a 8-byte boundary.
3601 * Unaligned memory access causes an Unaligned Data Reference interrupt.
3602 *
3603 * Functional Description (64-bit)
3604 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
3605 * rf[Dest] = memVal;
3606 * if (memVal == SPR[CmpValueSPR])
3607 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
3608 *
3609 * Functional Description (32-bit)
3610 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
3611 * rf[Dest] = memVal;
3612 * if (memVal == signExtend32 (SPR[CmpValueSPR]))
3613 * memoryWriteWord (rf[SrcA], rf[SrcB]);
3614 *
3615 *
3616 * This function also processes exch and exch4 which need not process SPR.
3617 */
3618static void do_exch(CPUTLGState *env, bool quad, bool cmp)
3619{
3620 target_ulong addr;
3621 target_long val, sprval;
3622
3623 start_exclusive();
3624
3625 addr = env->atomic_srca;
3626 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3627 goto sigsegv_maperr;
3628 }
3629
3630 if (cmp) {
3631 if (quad) {
3632 sprval = env->spregs[TILEGX_SPR_CMPEXCH];
3633 } else {
3634 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
3635 }
3636 }
3637
3638 if (!cmp || val == sprval) {
3639 target_long valb = env->atomic_srcb;
3640 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3641 goto sigsegv_maperr;
3642 }
3643 }
3644
3645 set_regval(env, env->atomic_dstr, val);
3646 end_exclusive();
3647 return;
3648
3649 sigsegv_maperr:
3650 end_exclusive();
3651 gen_sigsegv_maperr(env, addr);
3652}
3653
3654static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
3655{
3656 int8_t write = 1;
3657 target_ulong addr;
3658 target_long val, valb;
3659
3660 start_exclusive();
3661
3662 addr = env->atomic_srca;
3663 valb = env->atomic_srcb;
3664 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3665 goto sigsegv_maperr;
3666 }
3667
3668 switch (trapnr) {
3669 case TILEGX_EXCP_OPCODE_FETCHADD:
3670 case TILEGX_EXCP_OPCODE_FETCHADD4:
3671 valb += val;
3672 break;
3673 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3674 valb += val;
3675 if (valb < 0) {
3676 write = 0;
3677 }
3678 break;
3679 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3680 valb += val;
3681 if ((int32_t)valb < 0) {
3682 write = 0;
3683 }
3684 break;
3685 case TILEGX_EXCP_OPCODE_FETCHAND:
3686 case TILEGX_EXCP_OPCODE_FETCHAND4:
3687 valb &= val;
3688 break;
3689 case TILEGX_EXCP_OPCODE_FETCHOR:
3690 case TILEGX_EXCP_OPCODE_FETCHOR4:
3691 valb |= val;
3692 break;
3693 default:
3694 g_assert_not_reached();
3695 }
3696
3697 if (write) {
3698 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3699 goto sigsegv_maperr;
3700 }
3701 }
3702
3703 set_regval(env, env->atomic_dstr, val);
3704 end_exclusive();
3705 return;
3706
3707 sigsegv_maperr:
3708 end_exclusive();
3709 gen_sigsegv_maperr(env, addr);
3710}
3711
b16189b2
CG		 3712void cpu_loop(CPUTLGState *env)
3713{
3714 CPUState *cs = CPU(tilegx_env_get_cpu(env));
3715 int trapnr;
3716
3717 while (1) {
3718 cpu_exec_start(cs);
8642c1b8 3719 trapnr = cpu_exec(cs);
b16189b2
CG		 3720 cpu_exec_end(cs);
3721 switch (trapnr) {
3722 case TILEGX_EXCP_SYSCALL:
a9175169
PM		 3723 {
3724 abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR],
3725 env->regs[0], env->regs[1],
3726 env->regs[2], env->regs[3],
3727 env->regs[4], env->regs[5],
3728 env->regs[6], env->regs[7]);
3729 if (ret == -TARGET_ERESTARTSYS) {
3730 env->pc -= 8;
3731 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3732 env->regs[TILEGX_R_RE] = ret;
3733 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0;
3734 }
b16189b2 3735 break;
a9175169 3736 }
0583b233
RH		 3737 case TILEGX_EXCP_OPCODE_EXCH:
3738 do_exch(env, true, false);
3739 break;
3740 case TILEGX_EXCP_OPCODE_EXCH4:
3741 do_exch(env, false, false);
3742 break;
3743 case TILEGX_EXCP_OPCODE_CMPEXCH:
3744 do_exch(env, true, true);
3745 break;
3746 case TILEGX_EXCP_OPCODE_CMPEXCH4:
3747 do_exch(env, false, true);
3748 break;
3749 case TILEGX_EXCP_OPCODE_FETCHADD:
3750 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3751 case TILEGX_EXCP_OPCODE_FETCHAND:
3752 case TILEGX_EXCP_OPCODE_FETCHOR:
3753 do_fetch(env, trapnr, true);
3754 break;
3755 case TILEGX_EXCP_OPCODE_FETCHADD4:
3756 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3757 case TILEGX_EXCP_OPCODE_FETCHAND4:
3758 case TILEGX_EXCP_OPCODE_FETCHOR4:
3759 do_fetch(env, trapnr, false);
3760 break;
dd8070d8 3761 case TILEGX_EXCP_SIGNAL:
a0577d2a 3762 do_signal(env, env->signo, env->sigcode);
dd8070d8 3763 break;
b16189b2
CG		 3764 case TILEGX_EXCP_REG_IDN_ACCESS:
3765 case TILEGX_EXCP_REG_UDN_ACCESS:
3766 gen_sigill_reg(env);
3767 break;
3768 default:
3769 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
3770 g_assert_not_reached();
3771 }
3772 process_pending_signals(env);
3773 }
3774}
3775
3776#endif
3777
a2247f8e 3778THREAD CPUState *thread_cpu;
59faf6d6 3779
edf8e2af
MW		 3780void task_settid(TaskState *ts)
3781{
3782 if (ts->ts_tid == 0) {
edf8e2af 3783 ts->ts_tid = (pid_t)syscall(SYS_gettid);
edf8e2af
MW		 3784 }
3785}
3786
3787void stop_all_tasks(void)
3788{
3789 /*
3790 * We trust that when using NPTL, start_exclusive()
3791 * handles thread stopping correctly.
3792 */
3793 start_exclusive();
3794}
3795
c3a92833 3796/* Assumes contents are already zeroed. */
624f7979
PB		 3797void init_task_state(TaskState *ts)
3798{
624f7979 3799 ts->used = 1;
624f7979 3800}
fc9c5412 3801
30ba0ee5
AF		 3802CPUArchState *cpu_copy(CPUArchState *env)
3803{
ff4700b0 3804 CPUState *cpu = ENV_GET_CPU(env);
2994fd96 3805 CPUState *new_cpu = cpu_init(cpu_model);
61c7480f 3806 CPUArchState *new_env = new_cpu->env_ptr;
30ba0ee5
AF		 3807 CPUBreakpoint *bp;
3808 CPUWatchpoint *wp;
30ba0ee5
AF		 3809
3810 /* Reset non arch specific state */
75a34036 3811 cpu_reset(new_cpu);
30ba0ee5
AF		 3812
3813 memcpy(new_env, env, sizeof(CPUArchState));
3814
3815 /* Clone all break/watchpoints.
3816 Note: Once we support ptrace with hw-debug register access, make sure
3817 BP_CPU break/watchpoints are handled correctly on clone. */
1d085f6c
TB		 3818 QTAILQ_INIT(&new_cpu->breakpoints);
3819 QTAILQ_INIT(&new_cpu->watchpoints);
f0c3c505 3820 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
b3310ab3 3821 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
30ba0ee5 3822 }
ff4700b0 3823 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
05068c0d 3824 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
30ba0ee5 3825 }
30ba0ee5
AF		 3826
3827 return new_env;
3828}
3829
fc9c5412
JS		 3830static void handle_arg_help(const char *arg)
3831{
4d1275c2 3832 usage(EXIT_SUCCESS);
fc9c5412
JS		 3833}
3834
3835static void handle_arg_log(const char *arg)
3836{
3837 int mask;
fc9c5412 3838
4fde1eba 3839 mask = qemu_str_to_log_mask(arg);
fc9c5412 3840 if (!mask) {
59a6fa6e 3841 qemu_print_log_usage(stdout);
4d1275c2 3842 exit(EXIT_FAILURE);
fc9c5412 3843 }
f2937a33 3844 qemu_log_needs_buffers();
24537a01 3845 qemu_set_log(mask);
fc9c5412
JS		 3846}
3847
50171d42
CWR		 3848static void handle_arg_log_filename(const char *arg)
3849{
daa76aa4 3850 qemu_set_log_filename(arg, &error_fatal);
50171d42
CWR		 3851}
3852
fc9c5412
JS		 3853static void handle_arg_set_env(const char *arg)
3854{
3855 char *r, *p, *token;
3856 r = p = strdup(arg);
3857 while ((token = strsep(&p, ",")) != NULL) {
3858 if (envlist_setenv(envlist, token) != 0) {
4d1275c2 3859 usage(EXIT_FAILURE);
fc9c5412
JS		 3860 }
3861 }
3862 free(r);
3863}
3864
3865static void handle_arg_unset_env(const char *arg)
3866{
3867 char *r, *p, *token;
3868 r = p = strdup(arg);
3869 while ((token = strsep(&p, ",")) != NULL) {
3870 if (envlist_unsetenv(envlist, token) != 0) {
4d1275c2 3871 usage(EXIT_FAILURE);
fc9c5412
JS		 3872 }
3873 }
3874 free(r);
3875}
3876
3877static void handle_arg_argv0(const char *arg)
3878{
3879 argv0 = strdup(arg);
3880}
3881
3882static void handle_arg_stack_size(const char *arg)
3883{
3884 char *p;
3885 guest_stack_size = strtoul(arg, &p, 0);
3886 if (guest_stack_size == 0) {
4d1275c2 3887 usage(EXIT_FAILURE);
fc9c5412
JS		 3888 }
3889
3890 if (*p == 'M') {
3891 guest_stack_size *= 1024 * 1024;
3892 } else if (*p == 'k' || *p == 'K') {
3893 guest_stack_size *= 1024;
3894 }
3895}
3896
3897static void handle_arg_ld_prefix(const char *arg)
3898{
3899 interp_prefix = strdup(arg);
3900}
3901
3902static void handle_arg_pagesize(const char *arg)
3903{
3904 qemu_host_page_size = atoi(arg);
3905 if (qemu_host_page_size == 0 ||
3906 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3907 fprintf(stderr, "page size must be a power of two\n");
4d1275c2 3908 exit(EXIT_FAILURE);
fc9c5412
JS		 3909 }
3910}
3911
c5e4a5a9
MR		 3912static void handle_arg_randseed(const char *arg)
3913{
3914 unsigned long long seed;
3915
3916 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3917 fprintf(stderr, "Invalid seed number: %s\n", arg);
4d1275c2 3918 exit(EXIT_FAILURE);
c5e4a5a9
MR		 3919 }
3920 srand(seed);
3921}
3922
fc9c5412
JS		 3923static void handle_arg_gdb(const char *arg)
3924{
3925 gdbstub_port = atoi(arg);
3926}
3927
3928static void handle_arg_uname(const char *arg)
3929{
3930 qemu_uname_release = strdup(arg);
3931}
3932
3933static void handle_arg_cpu(const char *arg)
3934{
3935 cpu_model = strdup(arg);
c8057f95 3936 if (cpu_model == NULL || is_help_option(cpu_model)) {
fc9c5412 3937 /* XXX: implement xxx_cpu_list for targets that still miss it */
e916cbf8
PM		 3938#if defined(cpu_list)
3939 cpu_list(stdout, &fprintf);
fc9c5412 3940#endif
4d1275c2 3941 exit(EXIT_FAILURE);
fc9c5412
JS		 3942 }
3943}
3944
fc9c5412
JS		 3945static void handle_arg_guest_base(const char *arg)
3946{
3947 guest_base = strtol(arg, NULL, 0);
3948 have_guest_base = 1;
3949}
3950
3951static void handle_arg_reserved_va(const char *arg)
3952{
3953 char *p;
3954 int shift = 0;
3955 reserved_va = strtoul(arg, &p, 0);
3956 switch (*p) {
3957 case 'k':
3958 case 'K':
3959 shift = 10;
3960 break;
3961 case 'M':
3962 shift = 20;
3963 break;
3964 case 'G':
3965 shift = 30;
3966 break;
3967 }
3968 if (shift) {
3969 unsigned long unshifted = reserved_va;
3970 p++;
3971 reserved_va <<= shift;
3972 if (((reserved_va >> shift) != unshifted)
3973#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3974 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3975#endif
3976 ) {
3977 fprintf(stderr, "Reserved virtual address too big\n");
4d1275c2 3978 exit(EXIT_FAILURE);
fc9c5412
JS		 3979 }
3980 }
3981 if (*p) {
3982 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
4d1275c2 3983 exit(EXIT_FAILURE);
fc9c5412
JS		 3984 }
3985}
fc9c5412
JS		 3986
3987static void handle_arg_singlestep(const char *arg)
3988{
3989 singlestep = 1;
3990}
3991
3992static void handle_arg_strace(const char *arg)
3993{
3994 do_strace = 1;
3995}
3996
3997static void handle_arg_version(const char *arg)
3998{
2e59915d 3999 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
d915b7bb 4000 ", " QEMU_COPYRIGHT "\n");
4d1275c2 4001 exit(EXIT_SUCCESS);
fc9c5412
JS		 4002}
4003
6533dd6e
LV		 4004static char *trace_file;
4005static void handle_arg_trace(const char *arg)
4006{
4007 g_free(trace_file);
4008 trace_file = trace_opt_parse(arg);
4009}
4010
fc9c5412
JS		 4011struct qemu_argument {
4012 const char *argv;
4013 const char *env;
4014 bool has_arg;
4015 void (*handle_opt)(const char *arg);
4016 const char *example;
4017 const char *help;
4018};
4019
42644cee 4020static const struct qemu_argument arg_table[] = {
fc9c5412
JS		 4021 {"h", "", false, handle_arg_help,
4022 "", "print this help"},
daaf8c8e
MI		 4023 {"help", "", false, handle_arg_help,
4024 "", ""},
fc9c5412
JS		 4025 {"g", "QEMU_GDB", true, handle_arg_gdb,
4026 "port", "wait gdb connection to 'port'"},
4027 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
4028 "path", "set the elf interpreter prefix to 'path'"},
4029 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
4030 "size", "set the stack size to 'size' bytes"},
4031 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
c8057f95 4032 "model", "select CPU (-cpu help for list)"},
fc9c5412
JS		 4033 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
4034 "var=value", "sets targets environment variable (see below)"},
4035 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
4036 "var", "unsets targets environment variable (see below)"},
4037 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
4038 "argv0", "forces target process argv[0] to be 'argv0'"},
4039 {"r", "QEMU_UNAME", true, handle_arg_uname,
4040 "uname", "set qemu uname release string to 'uname'"},
fc9c5412
JS		 4041 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
4042 "address", "set guest_base address to 'address'"},
4043 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
4044 "size", "reserve 'size' bytes for guest virtual address space"},
fc9c5412 4045 {"d", "QEMU_LOG", true, handle_arg_log,
989b697d
PM		 4046 "item[,...]", "enable logging of specified items "
4047 "(use '-d help' for a list of items)"},
50171d42 4048 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
989b697d 4049 "logfile", "write logs to 'logfile' (default stderr)"},
fc9c5412
JS		 4050 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
4051 "pagesize", "set the host page size to 'pagesize'"},
4052 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
4053 "", "run in singlestep mode"},
4054 {"strace", "QEMU_STRACE", false, handle_arg_strace,
4055 "", "log system calls"},
c5e4a5a9
MR		 4056 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
4057 "", "Seed for pseudo-random number generator"},
6533dd6e
LV		 4058 {"trace", "QEMU_TRACE", true, handle_arg_trace,
4059 "", "[[enable=]<pattern>][,events=<file>][,file=<file>]"},
fc9c5412 4060 {"version", "QEMU_VERSION", false, handle_arg_version,
1386d4c0 4061 "", "display version information and exit"},
fc9c5412
JS		 4062 {NULL, NULL, false, NULL, NULL, NULL}
4063};
4064
d03f9c32 4065static void usage(int exitcode)
fc9c5412 4066{
42644cee 4067 const struct qemu_argument *arginfo;
fc9c5412
JS		 4068 int maxarglen;
4069 int maxenvlen;
4070
2e59915d
PB		 4071 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
4072 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
fc9c5412
JS		 4073 "\n"
4074 "Options and associated environment variables:\n"
4075 "\n");
4076
63ec54d7
PM		 4077 /* Calculate column widths. We must always have at least enough space
4078 * for the column header.
4079 */
4080 maxarglen = strlen("Argument");
4081 maxenvlen = strlen("Env-variable");
fc9c5412
JS		 4082
4083 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
63ec54d7
PM		 4084 int arglen = strlen(arginfo->argv);
4085 if (arginfo->has_arg) {
4086 arglen += strlen(arginfo->example) + 1;
4087 }
fc9c5412
JS		 4088 if (strlen(arginfo->env) > maxenvlen) {
4089 maxenvlen = strlen(arginfo->env);
4090 }
63ec54d7
PM		 4091 if (arglen > maxarglen) {
4092 maxarglen = arglen;
fc9c5412
JS		 4093 }
4094 }
4095
63ec54d7
PM		 4096 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
4097 maxenvlen, "Env-variable");
fc9c5412
JS		 4098
4099 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4100 if (arginfo->has_arg) {
4101 printf("-%s %-*s %-*s %s\n", arginfo->argv,
63ec54d7
PM		 4102 (int)(maxarglen - strlen(arginfo->argv) - 1),
4103 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
fc9c5412 4104 } else {
63ec54d7 4105 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
fc9c5412
JS		 4106 maxenvlen, arginfo->env,
4107 arginfo->help);
4108 }
4109 }
4110
4111 printf("\n"
4112 "Defaults:\n"
4113 "QEMU_LD_PREFIX = %s\n"
989b697d 4114 "QEMU_STACK_SIZE = %ld byte\n",
fc9c5412 4115 interp_prefix,
989b697d 4116 guest_stack_size);
fc9c5412
JS		 4117
4118 printf("\n"
4119 "You can use -E and -U options or the QEMU_SET_ENV and\n"
4120 "QEMU_UNSET_ENV environment variables to set and unset\n"
4121 "environment variables for the target process.\n"
4122 "It is possible to provide several variables by separating them\n"
4123 "by commas in getsubopt(3) style. Additionally it is possible to\n"
4124 "provide the -E and -U options multiple times.\n"
4125 "The following lines are equivalent:\n"
4126 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
4127 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
4128 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
4129 "Note that if you provide several changes to a single variable\n"
4130 "the last change will stay in effect.\n");
4131
d03f9c32 4132 exit(exitcode);
fc9c5412
JS		 4133}
4134
4135static int parse_args(int argc, char **argv)
4136{
4137 const char *r;
4138 int optind;
42644cee 4139 const struct qemu_argument *arginfo;
fc9c5412
JS		 4140
4141 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4142 if (arginfo->env == NULL) {
4143 continue;
4144 }
4145
4146 r = getenv(arginfo->env);
4147 if (r != NULL) {
4148 arginfo->handle_opt(r);
4149 }
4150 }
4151
4152 optind = 1;
4153 for (;;) {
4154 if (optind >= argc) {
4155 break;
4156 }
4157 r = argv[optind];
4158 if (r[0] != '-') {
4159 break;
4160 }
4161 optind++;
4162 r++;
4163 if (!strcmp(r, "-")) {
4164 break;
4165 }
ba02577c
MI		 4166 /* Treat --foo the same as -foo. */
4167 if (r[0] == '-') {
4168 r++;
4169 }
fc9c5412
JS		 4170
4171 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4172 if (!strcmp(r, arginfo->argv)) {
fc9c5412 4173 if (arginfo->has_arg) {
1386d4c0 4174 if (optind >= argc) {
138940bf
MI		 4175 (void) fprintf(stderr,
4176 "qemu: missing argument for option '%s'\n", r);
4d1275c2 4177 exit(EXIT_FAILURE);
1386d4c0
PM		 4178 }
4179 arginfo->handle_opt(argv[optind]);
fc9c5412 4180 optind++;
1386d4c0
PM		 4181 } else {
4182 arginfo->handle_opt(NULL);
fc9c5412 4183 }
fc9c5412
JS		 4184 break;
4185 }
4186 }
4187
4188 /* no option matched the current argv */
4189 if (arginfo->handle_opt == NULL) {
138940bf 4190 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r);
4d1275c2 4191 exit(EXIT_FAILURE);
fc9c5412
JS		 4192 }
4193 }
4194
4195 if (optind >= argc) {
138940bf 4196 (void) fprintf(stderr, "qemu: no user program specified\n");
4d1275c2 4197 exit(EXIT_FAILURE);
fc9c5412
JS		 4198 }
4199
4200 filename = argv[optind];
4201 exec_path = argv[optind];
4202
4203 return optind;
4204}
4205
902b3d5c 4206int main(int argc, char **argv, char **envp)
31e31b8a 4207{
01ffc75b 4208 struct target_pt_regs regs1, *regs = &regs1;
31e31b8a 4209 struct image_info info1, *info = &info1;
edf8e2af 4210 struct linux_binprm bprm;
48e15fc2 4211 TaskState *ts;
9349b4f9 4212 CPUArchState *env;
db6b81d4 4213 CPUState *cpu;
586314f2 4214 int optind;
04a6dfeb 4215 char **target_environ, **wrk;
7d8cec95
AJ		 4216 char **target_argv;
4217 int target_argc;
7d8cec95 4218 int i;
fd4d81dd 4219 int ret;
03cfd8fa 4220 int execfd;
b12b6a18 4221
959f593c 4222 qemu_init_cpu_loop();
ce008c1f
AF		 4223 module_call_init(MODULE_INIT_QOM);
4224
04a6dfeb
AJ		 4225 if ((envlist = envlist_create()) == NULL) {
4226 (void) fprintf(stderr, "Unable to allocate envlist\n");
4d1275c2 4227 exit(EXIT_FAILURE);
04a6dfeb
AJ		 4228 }
4229
4230 /* add current environment into the list */
4231 for (wrk = environ; *wrk != NULL; wrk++) {
4232 (void) envlist_setenv(envlist, *wrk);
4233 }
4234
703e0e89
RH		 4235 /* Read the stack limit from the kernel. If it's "unlimited",
4236 then we can do little else besides use the default. */
4237 {
4238 struct rlimit lim;
4239 if (getrlimit(RLIMIT_STACK, &lim) == 0
81bbe906
TY		 4240 && lim.rlim_cur != RLIM_INFINITY
4241 && lim.rlim_cur == (target_long)lim.rlim_cur) {
703e0e89
RH		 4242 guest_stack_size = lim.rlim_cur;
4243 }
4244 }
4245
b1f9be31 4246 cpu_model = NULL;
b5ec5ce0 4247
c5e4a5a9
MR		 4248 srand(time(NULL));
4249
6533dd6e
LV		 4250 qemu_add_opts(&qemu_trace_opts);
4251
fc9c5412 4252 optind = parse_args(argc, argv);
586314f2 4253
6533dd6e
LV		 4254 if (!trace_init_backends()) {
4255 exit(1);
4256 }
4257 trace_init_file(trace_file);
4258
31e31b8a 4259 /* Zero out regs */
01ffc75b 4260 memset(regs, 0, sizeof(struct target_pt_regs));
31e31b8a
FB		 4261
4262 /* Zero out image_info */
4263 memset(info, 0, sizeof(struct image_info));
4264
edf8e2af
MW		 4265 memset(&bprm, 0, sizeof (bprm));
4266
74cd30b8
FB		 4267 /* Scan interp_prefix dir for replacement files. */
4268 init_paths(interp_prefix);
4269
4a24a758
PM		 4270 init_qemu_uname_release();
4271
46027c07 4272 if (cpu_model == NULL) {
aaed909a 4273#if defined(TARGET_I386)
46027c07
FB		 4274#ifdef TARGET_X86_64
4275 cpu_model = "qemu64";
4276#else
4277 cpu_model = "qemu32";
4278#endif
aaed909a 4279#elif defined(TARGET_ARM)
088ab16c 4280 cpu_model = "any";
d2fbca94
GX		 4281#elif defined(TARGET_UNICORE32)
4282 cpu_model = "any";
aaed909a
FB		 4283#elif defined(TARGET_M68K)
4284 cpu_model = "any";
4285#elif defined(TARGET_SPARC)
4286#ifdef TARGET_SPARC64
4287 cpu_model = "TI UltraSparc II";
4288#else
4289 cpu_model = "Fujitsu MB86904";
46027c07 4290#endif
aaed909a
FB		 4291#elif defined(TARGET_MIPS)
4292#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
74797f40 4293 cpu_model = "5KEf";
aaed909a
FB		 4294#else
4295 cpu_model = "24Kf";
4296#endif
d962783e
JL		 4297#elif defined TARGET_OPENRISC
4298 cpu_model = "or1200";
aaed909a 4299#elif defined(TARGET_PPC)
a74029f6 4300# ifdef TARGET_PPC64
de3f1b98 4301 cpu_model = "POWER8";
a74029f6 4302# else
aaed909a 4303 cpu_model = "750";
a74029f6 4304# endif
91c45a38
RH		 4305#elif defined TARGET_SH4
4306 cpu_model = TYPE_SH7785_CPU;
aaed909a
FB		 4307#else
4308 cpu_model = "any";
4309#endif
4310 }
d5ab9713 4311 tcg_exec_init(0);
83fb7adf
FB		 4312 /* NOTE: we need to init the CPU at this stage to get
4313 qemu_host_page_size */
2994fd96
EH		 4314 cpu = cpu_init(cpu_model);
4315 if (!cpu) {
aaed909a 4316 fprintf(stderr, "Unable to find CPU definition\n");
4d1275c2 4317 exit(EXIT_FAILURE);
aaed909a 4318 }
2994fd96 4319 env = cpu->env_ptr;
0ac46af3 4320 cpu_reset(cpu);
b55a37c9 4321
db6b81d4 4322 thread_cpu = cpu;
3b46e624 4323
b6741956
FB		 4324 if (getenv("QEMU_STRACE")) {
4325 do_strace = 1;
b92c47c1
TS		 4326 }
4327
c5e4a5a9
MR		 4328 if (getenv("QEMU_RAND_SEED")) {
4329 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4330 }
4331
04a6dfeb
AJ		 4332 target_environ = envlist_to_environ(envlist, NULL);
4333 envlist_free(envlist);
b12b6a18 4334
379f6698
PB		 4335 /*
4336 * Now that page sizes are configured in cpu_init() we can do
4337 * proper page alignment for guest_base.
4338 */
4339 guest_base = HOST_PAGE_ALIGN(guest_base);
68a1c816 4340
806d1021
MI		 4341 if (reserved_va || have_guest_base) {
4342 guest_base = init_guest_space(guest_base, reserved_va, 0,
4343 have_guest_base);
4344 if (guest_base == (unsigned long)-1) {
097b8cb8
PM		 4345 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
4346 "space for use as guest address space (check your virtual "
4347 "memory ulimit setting or reserve less using -R option)\n",
4348 reserved_va);
4d1275c2 4349 exit(EXIT_FAILURE);
68a1c816 4350 }
97cc7560 4351
806d1021
MI		 4352 if (reserved_va) {
4353 mmap_next_start = reserved_va;
97cc7560
DDAG		 4354 }
4355 }
379f6698
PB		 4356
4357 /*
4358 * Read in mmap_min_addr kernel parameter. This value is used
4359 * When loading the ELF image to determine whether guest_base
14f24e14 4360 * is needed. It is also used in mmap_find_vma.
379f6698 4361 */
14f24e14 4362 {
379f6698
PB		 4363 FILE *fp;
4364
4365 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
4366 unsigned long tmp;
4367 if (fscanf(fp, "%lu", &tmp) == 1) {
4368 mmap_min_addr = tmp;
13829020 4369 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr);
379f6698
PB		 4370 }
4371 fclose(fp);
4372 }
4373 }
379f6698 4374
7d8cec95
AJ		 4375 /*
4376 * Prepare copy of argv vector for target.
4377 */
4378 target_argc = argc - optind;
4379 target_argv = calloc(target_argc + 1, sizeof (char *));
4380 if (target_argv == NULL) {
4381 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4d1275c2 4382 exit(EXIT_FAILURE);
7d8cec95
AJ		 4383 }
4384
4385 /*
4386 * If argv0 is specified (using '-0' switch) we replace
4387 * argv[0] pointer with the given one.
4388 */
4389 i = 0;
4390 if (argv0 != NULL) {
4391 target_argv[i++] = strdup(argv0);
4392 }
4393 for (; i < target_argc; i++) {
4394 target_argv[i] = strdup(argv[optind + i]);
4395 }
4396 target_argv[target_argc] = NULL;
4397
c78d65e8 4398 ts = g_new0(TaskState, 1);
edf8e2af
MW		 4399 init_task_state(ts);
4400 /* build Task State */
4401 ts->info = info;
4402 ts->bprm = &bprm;
0429a971 4403 cpu->opaque = ts;
edf8e2af
MW		 4404 task_settid(ts);
4405
0b959cf5
RH		 4406 execfd = qemu_getauxval(AT_EXECFD);
4407 if (execfd == 0) {
03cfd8fa 4408 execfd = open(filename, O_RDONLY);
0b959cf5
RH		 4409 if (execfd < 0) {
4410 printf("Error while loading %s: %s\n", filename, strerror(errno));
4d1275c2 4411 _exit(EXIT_FAILURE);
0b959cf5 4412 }
03cfd8fa
LV		 4413 }
4414
4415 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
fd4d81dd
AP		 4416 info, &bprm);
4417 if (ret != 0) {
885c1d10 4418 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4d1275c2 4419 _exit(EXIT_FAILURE);
b12b6a18
TS		 4420 }
4421
4422 for (wrk = target_environ; *wrk; wrk++) {
4423 free(*wrk);
31e31b8a 4424 }
3b46e624 4425
b12b6a18
TS		 4426 free(target_environ);
4427
13829020 4428 if (qemu_loglevel_mask(CPU_LOG_PAGE)) {
379f6698 4429 qemu_log("guest_base 0x%lx\n", guest_base);
2e77eac6
BS		 4430 log_page_dump();
4431
4432 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4433 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4434 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4435 info->start_code);
4436 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4437 info->start_data);
4438 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4439 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4440 info->start_stack);
4441 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4442 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4443 }
31e31b8a 4444
53a5960a 4445 target_set_brk(info->brk);
31e31b8a 4446 syscall_init();
66fb9763 4447 signal_init();
31e31b8a 4448
9002ec79
RH		 4449 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4450 generating the prologue until now so that the prologue can take
4451 the real value of GUEST_BASE into account. */
4452 tcg_prologue_init(&tcg_ctx);
9002ec79 4453
b346ff46 4454#if defined(TARGET_I386)
3802ce26 4455 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
b98dbc90 4456 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
0514ef2f 4457 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
1bde465e
FB		 4458 env->cr[4] |= CR4_OSFXSR_MASK;
4459 env->hflags |= HF_OSFXSR_MASK;
4460 }
d2fd1af7 4461#ifndef TARGET_ABI32
4dbc422b 4462 /* enable 64 bit mode if possible */
0514ef2f 4463 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4dbc422b 4464 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4d1275c2 4465 exit(EXIT_FAILURE);
4dbc422b 4466 }
d2fd1af7 4467 env->cr[4] |= CR4_PAE_MASK;
4dbc422b 4468 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
d2fd1af7
FB		 4469 env->hflags |= HF_LMA_MASK;
4470#endif
1bde465e 4471
415e561f
FB		 4472 /* flags setup : we activate the IRQs by default as in user mode */
4473 env->eflags |= IF_MASK;
3b46e624 4474
6dbad63e 4475 /* linux register setup */
d2fd1af7 4476#ifndef TARGET_ABI32
84409ddb
JM		 4477 env->regs[R_EAX] = regs->rax;
4478 env->regs[R_EBX] = regs->rbx;
4479 env->regs[R_ECX] = regs->rcx;
4480 env->regs[R_EDX] = regs->rdx;
4481 env->regs[R_ESI] = regs->rsi;
4482 env->regs[R_EDI] = regs->rdi;
4483 env->regs[R_EBP] = regs->rbp;
4484 env->regs[R_ESP] = regs->rsp;
4485 env->eip = regs->rip;
4486#else
0ecfa993
FB		 4487 env->regs[R_EAX] = regs->eax;
4488 env->regs[R_EBX] = regs->ebx;
4489 env->regs[R_ECX] = regs->ecx;
4490 env->regs[R_EDX] = regs->edx;
4491 env->regs[R_ESI] = regs->esi;
4492 env->regs[R_EDI] = regs->edi;
4493 env->regs[R_EBP] = regs->ebp;
4494 env->regs[R_ESP] = regs->esp;
dab2ed99 4495 env->eip = regs->eip;
84409ddb 4496#endif
31e31b8a 4497
f4beb510 4498 /* linux interrupt setup */
e441570f
AZ		 4499#ifndef TARGET_ABI32
4500 env->idt.limit = 511;
4501#else
4502 env->idt.limit = 255;
4503#endif
4504 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4505 PROT_READ|PROT_WRITE,
4506 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4507 idt_table = g2h(env->idt.base);
f4beb510
FB		 4508 set_idt(0, 0);
4509 set_idt(1, 0);
4510 set_idt(2, 0);
4511 set_idt(3, 3);
4512 set_idt(4, 3);
ec95da6c 4513 set_idt(5, 0);
f4beb510
FB		 4514 set_idt(6, 0);
4515 set_idt(7, 0);
4516 set_idt(8, 0);
4517 set_idt(9, 0);
4518 set_idt(10, 0);
4519 set_idt(11, 0);
4520 set_idt(12, 0);
4521 set_idt(13, 0);
4522 set_idt(14, 0);
4523 set_idt(15, 0);
4524 set_idt(16, 0);
4525 set_idt(17, 0);
4526 set_idt(18, 0);
4527 set_idt(19, 0);
4528 set_idt(0x80, 3);
4529
6dbad63e 4530 /* linux segment setup */
8d18e893
FB		 4531 {
4532 uint64_t *gdt_table;
e441570f
AZ		 4533 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4534 PROT_READ|PROT_WRITE,
4535 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
8d18e893 4536 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
e441570f 4537 gdt_table = g2h(env->gdt.base);
d2fd1af7 4538#ifdef TARGET_ABI32
8d18e893
FB		 4539 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4540 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4541 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
d2fd1af7
FB		 4542#else
4543 /* 64 bit code segment */
4544 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4545 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4546 DESC_L_MASK |
4547 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4548#endif
8d18e893
FB		 4549 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4550 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4551 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4552 }
6dbad63e 4553 cpu_x86_load_seg(env, R_CS, __USER_CS);
d2fd1af7
FB		 4554 cpu_x86_load_seg(env, R_SS, __USER_DS);
4555#ifdef TARGET_ABI32
6dbad63e
FB		 4556 cpu_x86_load_seg(env, R_DS, __USER_DS);
4557 cpu_x86_load_seg(env, R_ES, __USER_DS);
6dbad63e
FB		 4558 cpu_x86_load_seg(env, R_FS, __USER_DS);
4559 cpu_x86_load_seg(env, R_GS, __USER_DS);
d6eb40f6
TS		 4560 /* This hack makes Wine work... */
4561 env->segs[R_FS].selector = 0;
d2fd1af7
FB		 4562#else
4563 cpu_x86_load_seg(env, R_DS, 0);
4564 cpu_x86_load_seg(env, R_ES, 0);
4565 cpu_x86_load_seg(env, R_FS, 0);
4566 cpu_x86_load_seg(env, R_GS, 0);
4567#endif
99033cae
AG		 4568#elif defined(TARGET_AARCH64)
4569 {
4570 int i;
4571
4572 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4573 fprintf(stderr,
4574 "The selected ARM CPU does not support 64 bit mode\n");
4d1275c2 4575 exit(EXIT_FAILURE);
99033cae
AG		 4576 }
4577
4578 for (i = 0; i < 31; i++) {
4579 env->xregs[i] = regs->regs[i];
4580 }
4581 env->pc = regs->pc;
4582 env->xregs[31] = regs->sp;
4583 }
b346ff46
FB		 4584#elif defined(TARGET_ARM)
4585 {
4586 int i;
ae087923
PM		 4587 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
4588 CPSRWriteByInstr);
b346ff46
FB		 4589 for(i = 0; i < 16; i++) {
4590 env->regs[i] = regs->uregs[i];
4591 }
f9fd40eb 4592#ifdef TARGET_WORDS_BIGENDIAN
d8fd2954
PB		 4593 /* Enable BE8. */
4594 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4595 && (info->elf_flags & EF_ARM_BE8)) {
9c5a7460
PC		 4596 env->uncached_cpsr |= CPSR_E;
4597 env->cp15.sctlr_el[1] |= SCTLR_E0E;
f9fd40eb
PB		 4598 } else {
4599 env->cp15.sctlr_el[1] |= SCTLR_B;
d8fd2954 4600 }
f9fd40eb 4601#endif
b346ff46 4602 }
d2fbca94
GX		 4603#elif defined(TARGET_UNICORE32)
4604 {
4605 int i;
4606 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4607 for (i = 0; i < 32; i++) {
4608 env->regs[i] = regs->uregs[i];
4609 }
4610 }
93ac68bc 4611#elif defined(TARGET_SPARC)
060366c5
FB		 4612 {
4613 int i;
4614 env->pc = regs->pc;
4615 env->npc = regs->npc;
4616 env->y = regs->y;
4617 for(i = 0; i < 8; i++)
4618 env->gregs[i] = regs->u_regs[i];
4619 for(i = 0; i < 8; i++)
4620 env->regwptr[i] = regs->u_regs[i + 8];
4621 }
67867308
FB		 4622#elif defined(TARGET_PPC)
4623 {
4624 int i;
3fc6c082 4625
0411a972 4626#if defined(TARGET_PPC64)
c8361129 4627 int flag = (env->insns_flags2 & PPC2_BOOKE206) ? MSR_CM : MSR_SF;
0411a972 4628#if defined(TARGET_ABI32)
c8361129 4629 env->msr &= ~((target_ulong)1 << flag);
e85e7c6e 4630#else
c8361129 4631 env->msr |= (target_ulong)1 << flag;
0411a972 4632#endif
84409ddb 4633#endif
67867308
FB		 4634 env->nip = regs->nip;
4635 for(i = 0; i < 32; i++) {
4636 env->gpr[i] = regs->gpr[i];
4637 }
4638 }
e6e5906b
PB		 4639#elif defined(TARGET_M68K)
4640 {
e6e5906b
PB		 4641 env->pc = regs->pc;
4642 env->dregs[0] = regs->d0;
4643 env->dregs[1] = regs->d1;
4644 env->dregs[2] = regs->d2;
4645 env->dregs[3] = regs->d3;
4646 env->dregs[4] = regs->d4;
4647 env->dregs[5] = regs->d5;
4648 env->dregs[6] = regs->d6;
4649 env->dregs[7] = regs->d7;
4650 env->aregs[0] = regs->a0;
4651 env->aregs[1] = regs->a1;
4652 env->aregs[2] = regs->a2;
4653 env->aregs[3] = regs->a3;
4654 env->aregs[4] = regs->a4;
4655 env->aregs[5] = regs->a5;
4656 env->aregs[6] = regs->a6;
4657 env->aregs[7] = regs->usp;
4658 env->sr = regs->sr;
4659 ts->sim_syscalls = 1;
4660 }
b779e29e
EI		 4661#elif defined(TARGET_MICROBLAZE)
4662 {
4663 env->regs[0] = regs->r0;
4664 env->regs[1] = regs->r1;
4665 env->regs[2] = regs->r2;
4666 env->regs[3] = regs->r3;
4667 env->regs[4] = regs->r4;
4668 env->regs[5] = regs->r5;
4669 env->regs[6] = regs->r6;
4670 env->regs[7] = regs->r7;
4671 env->regs[8] = regs->r8;
4672 env->regs[9] = regs->r9;
4673 env->regs[10] = regs->r10;
4674 env->regs[11] = regs->r11;
4675 env->regs[12] = regs->r12;
4676 env->regs[13] = regs->r13;
4677 env->regs[14] = regs->r14;
4678 env->regs[15] = regs->r15;
4679 env->regs[16] = regs->r16;
4680 env->regs[17] = regs->r17;
4681 env->regs[18] = regs->r18;
4682 env->regs[19] = regs->r19;
4683 env->regs[20] = regs->r20;
4684 env->regs[21] = regs->r21;
4685 env->regs[22] = regs->r22;
4686 env->regs[23] = regs->r23;
4687 env->regs[24] = regs->r24;
4688 env->regs[25] = regs->r25;
4689 env->regs[26] = regs->r26;
4690 env->regs[27] = regs->r27;
4691 env->regs[28] = regs->r28;
4692 env->regs[29] = regs->r29;
4693 env->regs[30] = regs->r30;
4694 env->regs[31] = regs->r31;
4695 env->sregs[SR_PC] = regs->pc;
4696 }
048f6b4d
FB		 4697#elif defined(TARGET_MIPS)
4698 {
4699 int i;
4700
4701 for(i = 0; i < 32; i++) {
b5dc7732 4702 env->active_tc.gpr[i] = regs->regs[i];
048f6b4d 4703 }
0fddbbf2
NF		 4704 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4705 if (regs->cp0_epc & 1) {
4706 env->hflags |= MIPS_HFLAG_M16;
4707 }
599bc5e8
AM		 4708 if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
4709 ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
4710 if ((env->active_fpu.fcr31_rw_bitmask &
4711 (1 << FCR31_NAN2008)) == 0) {
4712 fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n");
4713 exit(1);
4714 }
4715 if ((info->elf_flags & EF_MIPS_NAN2008) != 0) {
4716 env->active_fpu.fcr31 |= (1 << FCR31_NAN2008);
4717 } else {
4718 env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008);
4719 }
4720 restore_snan_bit_mode(env);
4721 }
048f6b4d 4722 }
d962783e
JL		 4723#elif defined(TARGET_OPENRISC)
4724 {
4725 int i;
4726
4727 for (i = 0; i < 32; i++) {
4728 env->gpr[i] = regs->gpr[i];
4729 }
4730
4731 env->sr = regs->sr;
4732 env->pc = regs->pc;
4733 }
fdf9b3e8
FB		 4734#elif defined(TARGET_SH4)
4735 {
4736 int i;
4737
4738 for(i = 0; i < 16; i++) {
4739 env->gregs[i] = regs->regs[i];
4740 }
4741 env->pc = regs->pc;
4742 }
7a3148a9
JM		 4743#elif defined(TARGET_ALPHA)
4744 {
4745 int i;
4746
4747 for(i = 0; i < 28; i++) {
992f48a0 4748 env->ir[i] = ((abi_ulong *)regs)[i];
7a3148a9 4749 }
dad081ee 4750 env->ir[IR_SP] = regs->usp;
7a3148a9 4751 env->pc = regs->pc;
7a3148a9 4752 }
48733d19
TS		 4753#elif defined(TARGET_CRIS)
4754 {
4755 env->regs[0] = regs->r0;
4756 env->regs[1] = regs->r1;
4757 env->regs[2] = regs->r2;
4758 env->regs[3] = regs->r3;
4759 env->regs[4] = regs->r4;
4760 env->regs[5] = regs->r5;
4761 env->regs[6] = regs->r6;
4762 env->regs[7] = regs->r7;
4763 env->regs[8] = regs->r8;
4764 env->regs[9] = regs->r9;
4765 env->regs[10] = regs->r10;
4766 env->regs[11] = regs->r11;
4767 env->regs[12] = regs->r12;
4768 env->regs[13] = regs->r13;
4769 env->regs[14] = info->start_stack;
4770 env->regs[15] = regs->acr;
4771 env->pc = regs->erp;
4772 }
a4c075f1
UH		 4773#elif defined(TARGET_S390X)
4774 {
4775 int i;
4776 for (i = 0; i < 16; i++) {
4777 env->regs[i] = regs->gprs[i];
4778 }
4779 env->psw.mask = regs->psw.mask;
4780 env->psw.addr = regs->psw.addr;
4781 }
b16189b2
CG		 4782#elif defined(TARGET_TILEGX)
4783 {
4784 int i;
4785 for (i = 0; i < TILEGX_R_COUNT; i++) {
4786 env->regs[i] = regs->regs[i];
4787 }
4788 for (i = 0; i < TILEGX_SPR_COUNT; i++) {
4789 env->spregs[i] = 0;
4790 }
4791 env->pc = regs->pc;
4792 }
b346ff46
FB		 4793#else
4794#error unsupported target CPU
4795#endif
31e31b8a 4796
d2fbca94 4797#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
a87295e8
PB		 4798 ts->stack_base = info->start_stack;
4799 ts->heap_base = info->brk;
4800 /* This will be filled in on the first SYS_HEAPINFO call. */
4801 ts->heap_limit = 0;
4802#endif
4803
74c33bed 4804 if (gdbstub_port) {
ff7a981a
PM		 4805 if (gdbserver_start(gdbstub_port) < 0) {
4806 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4807 gdbstub_port);
4d1275c2 4808 exit(EXIT_FAILURE);
ff7a981a 4809 }
db6b81d4 4810 gdb_handlesig(cpu, 0);
1fddef4b 4811 }
48151859 4812 trace_init_vcpu_events();
1b6b029e
FB		 4813 cpu_loop(env);
4814 /* never exits */
31e31b8a
FB		 4815 return 0;
4816}
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