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Commit | Line | Data |
---|---|---|
31e31b8a | 1 | /* |
93ac68bc | 2 | * qemu user main |
5fafdf24 | 3 | * |
68d0f70e | 4 | * Copyright (c) 2003-2008 Fabrice Bellard |
31e31b8a FB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
8167ee88 | 17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
31e31b8a FB |
18 | */ |
19 | #include <stdlib.h> | |
20 | #include <stdio.h> | |
21 | #include <stdarg.h> | |
04369ff2 | 22 | #include <string.h> |
31e31b8a | 23 | #include <errno.h> |
0ecfa993 | 24 | #include <unistd.h> |
e441570f | 25 | #include <sys/mman.h> |
edf8e2af | 26 | #include <sys/syscall.h> |
31e31b8a | 27 | |
3ef693a0 | 28 | #include "qemu.h" |
ca10f867 | 29 | #include "qemu-common.h" |
902b3d5c | 30 | #include "cache-utils.h" |
d5975363 PB |
31 | /* For tb_lock */ |
32 | #include "exec-all.h" | |
31e31b8a | 33 | |
04a6dfeb AJ |
34 | |
35 | #include "envlist.h" | |
36 | ||
3ef693a0 | 37 | #define DEBUG_LOGFILE "/tmp/qemu.log" |
586314f2 | 38 | |
d088d664 AJ |
39 | char *exec_path; |
40 | ||
1b530a6d | 41 | int singlestep; |
379f6698 PB |
42 | #if defined(CONFIG_USE_GUEST_BASE) |
43 | unsigned long mmap_min_addr; | |
44 | unsigned long guest_base; | |
45 | int have_guest_base; | |
46 | #endif | |
1b530a6d | 47 | |
74cd30b8 | 48 | static const char *interp_prefix = CONFIG_QEMU_PREFIX; |
c5937220 | 49 | const char *qemu_uname_release = CONFIG_UNAME_RELEASE; |
586314f2 | 50 | |
3a4739d6 | 51 | #if defined(__i386__) && !defined(CONFIG_STATIC) |
f801f97e FB |
52 | /* Force usage of an ELF interpreter even if it is an ELF shared |
53 | object ! */ | |
54 | const char interp[] __attribute__((section(".interp"))) = "/lib/ld-linux.so.2"; | |
4304763b | 55 | #endif |
74cd30b8 | 56 | |
93ac68bc | 57 | /* for recent libc, we add these dummy symbols which are not declared |
74cd30b8 | 58 | when generating a linked object (bug in ld ?) */ |
fbf59244 | 59 | #if (__GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3)) && !defined(CONFIG_STATIC) |
46027c07 FB |
60 | asm(".globl __preinit_array_start\n" |
61 | ".globl __preinit_array_end\n" | |
62 | ".globl __init_array_start\n" | |
63 | ".globl __init_array_end\n" | |
64 | ".globl __fini_array_start\n" | |
65 | ".globl __fini_array_end\n" | |
66 | ".section \".rodata\"\n" | |
67 | "__preinit_array_start:\n" | |
68 | "__preinit_array_end:\n" | |
69 | "__init_array_start:\n" | |
70 | "__init_array_end:\n" | |
71 | "__fini_array_start:\n" | |
72 | "__fini_array_end:\n" | |
7bba1ee8 TS |
73 | ".long 0\n" |
74 | ".previous\n"); | |
74cd30b8 FB |
75 | #endif |
76 | ||
9de5e440 FB |
77 | /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so |
78 | we allocate a bigger stack. Need a better solution, for example | |
79 | by remapping the process stack directly at the right place */ | |
80 | unsigned long x86_stack_size = 512 * 1024; | |
31e31b8a FB |
81 | |
82 | void gemu_log(const char *fmt, ...) | |
83 | { | |
84 | va_list ap; | |
85 | ||
86 | va_start(ap, fmt); | |
87 | vfprintf(stderr, fmt, ap); | |
88 | va_end(ap); | |
89 | } | |
90 | ||
8fcd3692 | 91 | #if defined(TARGET_I386) |
a541f297 | 92 | int cpu_get_pic_interrupt(CPUState *env) |
92ccca6a FB |
93 | { |
94 | return -1; | |
95 | } | |
8fcd3692 | 96 | #endif |
92ccca6a | 97 | |
28ab0e2e FB |
98 | /* timers for rdtsc */ |
99 | ||
1dce7c3c | 100 | #if 0 |
28ab0e2e FB |
101 | |
102 | static uint64_t emu_time; | |
103 | ||
104 | int64_t cpu_get_real_ticks(void) | |
105 | { | |
106 | return emu_time++; | |
107 | } | |
108 | ||
109 | #endif | |
110 | ||
2f7bb878 | 111 | #if defined(CONFIG_USE_NPTL) |
d5975363 PB |
112 | /***********************************************************/ |
113 | /* Helper routines for implementing atomic operations. */ | |
114 | ||
115 | /* To implement exclusive operations we force all cpus to syncronise. | |
116 | We don't require a full sync, only that no cpus are executing guest code. | |
117 | The alternative is to map target atomic ops onto host equivalents, | |
118 | which requires quite a lot of per host/target work. */ | |
c2764719 | 119 | static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER; |
d5975363 PB |
120 | static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER; |
121 | static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER; | |
122 | static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER; | |
123 | static int pending_cpus; | |
124 | ||
125 | /* Make sure everything is in a consistent state for calling fork(). */ | |
126 | void fork_start(void) | |
127 | { | |
128 | mmap_fork_start(); | |
129 | pthread_mutex_lock(&tb_lock); | |
130 | pthread_mutex_lock(&exclusive_lock); | |
131 | } | |
132 | ||
133 | void fork_end(int child) | |
134 | { | |
135 | if (child) { | |
136 | /* Child processes created by fork() only have a single thread. | |
137 | Discard information about the parent threads. */ | |
138 | first_cpu = thread_env; | |
139 | thread_env->next_cpu = NULL; | |
140 | pending_cpus = 0; | |
141 | pthread_mutex_init(&exclusive_lock, NULL); | |
c2764719 | 142 | pthread_mutex_init(&cpu_list_mutex, NULL); |
d5975363 PB |
143 | pthread_cond_init(&exclusive_cond, NULL); |
144 | pthread_cond_init(&exclusive_resume, NULL); | |
145 | pthread_mutex_init(&tb_lock, NULL); | |
2b1319c8 | 146 | gdbserver_fork(thread_env); |
d5975363 PB |
147 | } else { |
148 | pthread_mutex_unlock(&exclusive_lock); | |
149 | pthread_mutex_unlock(&tb_lock); | |
150 | } | |
151 | mmap_fork_end(child); | |
152 | } | |
153 | ||
154 | /* Wait for pending exclusive operations to complete. The exclusive lock | |
155 | must be held. */ | |
156 | static inline void exclusive_idle(void) | |
157 | { | |
158 | while (pending_cpus) { | |
159 | pthread_cond_wait(&exclusive_resume, &exclusive_lock); | |
160 | } | |
161 | } | |
162 | ||
163 | /* Start an exclusive operation. | |
164 | Must only be called from outside cpu_arm_exec. */ | |
165 | static inline void start_exclusive(void) | |
166 | { | |
167 | CPUState *other; | |
168 | pthread_mutex_lock(&exclusive_lock); | |
169 | exclusive_idle(); | |
170 | ||
171 | pending_cpus = 1; | |
172 | /* Make all other cpus stop executing. */ | |
173 | for (other = first_cpu; other; other = other->next_cpu) { | |
174 | if (other->running) { | |
175 | pending_cpus++; | |
3098dba0 | 176 | cpu_exit(other); |
d5975363 PB |
177 | } |
178 | } | |
179 | if (pending_cpus > 1) { | |
180 | pthread_cond_wait(&exclusive_cond, &exclusive_lock); | |
181 | } | |
182 | } | |
183 | ||
184 | /* Finish an exclusive operation. */ | |
185 | static inline void end_exclusive(void) | |
186 | { | |
187 | pending_cpus = 0; | |
188 | pthread_cond_broadcast(&exclusive_resume); | |
189 | pthread_mutex_unlock(&exclusive_lock); | |
190 | } | |
191 | ||
192 | /* Wait for exclusive ops to finish, and begin cpu execution. */ | |
193 | static inline void cpu_exec_start(CPUState *env) | |
194 | { | |
195 | pthread_mutex_lock(&exclusive_lock); | |
196 | exclusive_idle(); | |
197 | env->running = 1; | |
198 | pthread_mutex_unlock(&exclusive_lock); | |
199 | } | |
200 | ||
201 | /* Mark cpu as not executing, and release pending exclusive ops. */ | |
202 | static inline void cpu_exec_end(CPUState *env) | |
203 | { | |
204 | pthread_mutex_lock(&exclusive_lock); | |
205 | env->running = 0; | |
206 | if (pending_cpus > 1) { | |
207 | pending_cpus--; | |
208 | if (pending_cpus == 1) { | |
209 | pthread_cond_signal(&exclusive_cond); | |
210 | } | |
211 | } | |
212 | exclusive_idle(); | |
213 | pthread_mutex_unlock(&exclusive_lock); | |
214 | } | |
c2764719 PB |
215 | |
216 | void cpu_list_lock(void) | |
217 | { | |
218 | pthread_mutex_lock(&cpu_list_mutex); | |
219 | } | |
220 | ||
221 | void cpu_list_unlock(void) | |
222 | { | |
223 | pthread_mutex_unlock(&cpu_list_mutex); | |
224 | } | |
2f7bb878 | 225 | #else /* if !CONFIG_USE_NPTL */ |
d5975363 PB |
226 | /* These are no-ops because we are not threadsafe. */ |
227 | static inline void cpu_exec_start(CPUState *env) | |
228 | { | |
229 | } | |
230 | ||
231 | static inline void cpu_exec_end(CPUState *env) | |
232 | { | |
233 | } | |
234 | ||
235 | static inline void start_exclusive(void) | |
236 | { | |
237 | } | |
238 | ||
239 | static inline void end_exclusive(void) | |
240 | { | |
241 | } | |
242 | ||
243 | void fork_start(void) | |
244 | { | |
245 | } | |
246 | ||
247 | void fork_end(int child) | |
248 | { | |
2b1319c8 AJ |
249 | if (child) { |
250 | gdbserver_fork(thread_env); | |
251 | } | |
d5975363 | 252 | } |
c2764719 PB |
253 | |
254 | void cpu_list_lock(void) | |
255 | { | |
256 | } | |
257 | ||
258 | void cpu_list_unlock(void) | |
259 | { | |
260 | } | |
d5975363 PB |
261 | #endif |
262 | ||
263 | ||
a541f297 FB |
264 | #ifdef TARGET_I386 |
265 | /***********************************************************/ | |
266 | /* CPUX86 core interface */ | |
267 | ||
02a1602e FB |
268 | void cpu_smm_update(CPUState *env) |
269 | { | |
270 | } | |
271 | ||
28ab0e2e FB |
272 | uint64_t cpu_get_tsc(CPUX86State *env) |
273 | { | |
274 | return cpu_get_real_ticks(); | |
275 | } | |
276 | ||
5fafdf24 | 277 | static void write_dt(void *ptr, unsigned long addr, unsigned long limit, |
f4beb510 | 278 | int flags) |
6dbad63e | 279 | { |
f4beb510 | 280 | unsigned int e1, e2; |
53a5960a | 281 | uint32_t *p; |
6dbad63e FB |
282 | e1 = (addr << 16) | (limit & 0xffff); |
283 | e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000); | |
f4beb510 | 284 | e2 |= flags; |
53a5960a | 285 | p = ptr; |
d538e8f5 | 286 | p[0] = tswap32(e1); |
287 | p[1] = tswap32(e2); | |
f4beb510 FB |
288 | } |
289 | ||
e441570f | 290 | static uint64_t *idt_table; |
eb38c52c | 291 | #ifdef TARGET_X86_64 |
d2fd1af7 FB |
292 | static void set_gate64(void *ptr, unsigned int type, unsigned int dpl, |
293 | uint64_t addr, unsigned int sel) | |
f4beb510 | 294 | { |
4dbc422b | 295 | uint32_t *p, e1, e2; |
f4beb510 FB |
296 | e1 = (addr & 0xffff) | (sel << 16); |
297 | e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); | |
53a5960a | 298 | p = ptr; |
4dbc422b FB |
299 | p[0] = tswap32(e1); |
300 | p[1] = tswap32(e2); | |
301 | p[2] = tswap32(addr >> 32); | |
302 | p[3] = 0; | |
6dbad63e | 303 | } |
d2fd1af7 FB |
304 | /* only dpl matters as we do only user space emulation */ |
305 | static void set_idt(int n, unsigned int dpl) | |
306 | { | |
307 | set_gate64(idt_table + n * 2, 0, dpl, 0, 0); | |
308 | } | |
309 | #else | |
d2fd1af7 FB |
310 | static void set_gate(void *ptr, unsigned int type, unsigned int dpl, |
311 | uint32_t addr, unsigned int sel) | |
312 | { | |
4dbc422b | 313 | uint32_t *p, e1, e2; |
d2fd1af7 FB |
314 | e1 = (addr & 0xffff) | (sel << 16); |
315 | e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); | |
316 | p = ptr; | |
4dbc422b FB |
317 | p[0] = tswap32(e1); |
318 | p[1] = tswap32(e2); | |
d2fd1af7 FB |
319 | } |
320 | ||
f4beb510 FB |
321 | /* only dpl matters as we do only user space emulation */ |
322 | static void set_idt(int n, unsigned int dpl) | |
323 | { | |
324 | set_gate(idt_table + n, 0, dpl, 0, 0); | |
325 | } | |
d2fd1af7 | 326 | #endif |
31e31b8a | 327 | |
89e957e7 | 328 | void cpu_loop(CPUX86State *env) |
1b6b029e | 329 | { |
bc8a22cc | 330 | int trapnr; |
992f48a0 | 331 | abi_ulong pc; |
9de5e440 | 332 | target_siginfo_t info; |
851e67a1 | 333 | |
1b6b029e | 334 | for(;;) { |
bc8a22cc | 335 | trapnr = cpu_x86_exec(env); |
bc8a22cc | 336 | switch(trapnr) { |
f4beb510 | 337 | case 0x80: |
d2fd1af7 | 338 | /* linux syscall from int $0x80 */ |
5fafdf24 TS |
339 | env->regs[R_EAX] = do_syscall(env, |
340 | env->regs[R_EAX], | |
f4beb510 FB |
341 | env->regs[R_EBX], |
342 | env->regs[R_ECX], | |
343 | env->regs[R_EDX], | |
344 | env->regs[R_ESI], | |
345 | env->regs[R_EDI], | |
346 | env->regs[R_EBP]); | |
347 | break; | |
d2fd1af7 FB |
348 | #ifndef TARGET_ABI32 |
349 | case EXCP_SYSCALL: | |
350 | /* linux syscall from syscall intruction */ | |
351 | env->regs[R_EAX] = do_syscall(env, | |
352 | env->regs[R_EAX], | |
353 | env->regs[R_EDI], | |
354 | env->regs[R_ESI], | |
355 | env->regs[R_EDX], | |
356 | env->regs[10], | |
357 | env->regs[8], | |
358 | env->regs[9]); | |
359 | env->eip = env->exception_next_eip; | |
360 | break; | |
361 | #endif | |
f4beb510 FB |
362 | case EXCP0B_NOSEG: |
363 | case EXCP0C_STACK: | |
364 | info.si_signo = SIGBUS; | |
365 | info.si_errno = 0; | |
366 | info.si_code = TARGET_SI_KERNEL; | |
367 | info._sifields._sigfault._addr = 0; | |
624f7979 | 368 | queue_signal(env, info.si_signo, &info); |
f4beb510 | 369 | break; |
1b6b029e | 370 | case EXCP0D_GPF: |
d2fd1af7 | 371 | /* XXX: potential problem if ABI32 */ |
84409ddb | 372 | #ifndef TARGET_X86_64 |
851e67a1 | 373 | if (env->eflags & VM_MASK) { |
89e957e7 | 374 | handle_vm86_fault(env); |
84409ddb JM |
375 | } else |
376 | #endif | |
377 | { | |
f4beb510 FB |
378 | info.si_signo = SIGSEGV; |
379 | info.si_errno = 0; | |
380 | info.si_code = TARGET_SI_KERNEL; | |
381 | info._sifields._sigfault._addr = 0; | |
624f7979 | 382 | queue_signal(env, info.si_signo, &info); |
1b6b029e FB |
383 | } |
384 | break; | |
b689bc57 FB |
385 | case EXCP0E_PAGE: |
386 | info.si_signo = SIGSEGV; | |
387 | info.si_errno = 0; | |
388 | if (!(env->error_code & 1)) | |
389 | info.si_code = TARGET_SEGV_MAPERR; | |
390 | else | |
391 | info.si_code = TARGET_SEGV_ACCERR; | |
970a87a6 | 392 | info._sifields._sigfault._addr = env->cr[2]; |
624f7979 | 393 | queue_signal(env, info.si_signo, &info); |
b689bc57 | 394 | break; |
9de5e440 | 395 | case EXCP00_DIVZ: |
84409ddb | 396 | #ifndef TARGET_X86_64 |
bc8a22cc | 397 | if (env->eflags & VM_MASK) { |
447db213 | 398 | handle_vm86_trap(env, trapnr); |
84409ddb JM |
399 | } else |
400 | #endif | |
401 | { | |
bc8a22cc FB |
402 | /* division by zero */ |
403 | info.si_signo = SIGFPE; | |
404 | info.si_errno = 0; | |
405 | info.si_code = TARGET_FPE_INTDIV; | |
406 | info._sifields._sigfault._addr = env->eip; | |
624f7979 | 407 | queue_signal(env, info.si_signo, &info); |
bc8a22cc | 408 | } |
9de5e440 | 409 | break; |
01df040b | 410 | case EXCP01_DB: |
447db213 | 411 | case EXCP03_INT3: |
84409ddb | 412 | #ifndef TARGET_X86_64 |
447db213 FB |
413 | if (env->eflags & VM_MASK) { |
414 | handle_vm86_trap(env, trapnr); | |
84409ddb JM |
415 | } else |
416 | #endif | |
417 | { | |
447db213 FB |
418 | info.si_signo = SIGTRAP; |
419 | info.si_errno = 0; | |
01df040b | 420 | if (trapnr == EXCP01_DB) { |
447db213 FB |
421 | info.si_code = TARGET_TRAP_BRKPT; |
422 | info._sifields._sigfault._addr = env->eip; | |
423 | } else { | |
424 | info.si_code = TARGET_SI_KERNEL; | |
425 | info._sifields._sigfault._addr = 0; | |
426 | } | |
624f7979 | 427 | queue_signal(env, info.si_signo, &info); |
447db213 FB |
428 | } |
429 | break; | |
9de5e440 FB |
430 | case EXCP04_INTO: |
431 | case EXCP05_BOUND: | |
84409ddb | 432 | #ifndef TARGET_X86_64 |
bc8a22cc | 433 | if (env->eflags & VM_MASK) { |
447db213 | 434 | handle_vm86_trap(env, trapnr); |
84409ddb JM |
435 | } else |
436 | #endif | |
437 | { | |
bc8a22cc FB |
438 | info.si_signo = SIGSEGV; |
439 | info.si_errno = 0; | |
b689bc57 | 440 | info.si_code = TARGET_SI_KERNEL; |
bc8a22cc | 441 | info._sifields._sigfault._addr = 0; |
624f7979 | 442 | queue_signal(env, info.si_signo, &info); |
bc8a22cc | 443 | } |
9de5e440 FB |
444 | break; |
445 | case EXCP06_ILLOP: | |
446 | info.si_signo = SIGILL; | |
447 | info.si_errno = 0; | |
448 | info.si_code = TARGET_ILL_ILLOPN; | |
449 | info._sifields._sigfault._addr = env->eip; | |
624f7979 | 450 | queue_signal(env, info.si_signo, &info); |
9de5e440 FB |
451 | break; |
452 | case EXCP_INTERRUPT: | |
453 | /* just indicate that signals should be handled asap */ | |
454 | break; | |
1fddef4b FB |
455 | case EXCP_DEBUG: |
456 | { | |
457 | int sig; | |
458 | ||
459 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
460 | if (sig) | |
461 | { | |
462 | info.si_signo = sig; | |
463 | info.si_errno = 0; | |
464 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 465 | queue_signal(env, info.si_signo, &info); |
1fddef4b FB |
466 | } |
467 | } | |
468 | break; | |
1b6b029e | 469 | default: |
970a87a6 | 470 | pc = env->segs[R_CS].base + env->eip; |
5fafdf24 | 471 | fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n", |
bc8a22cc | 472 | (long)pc, trapnr); |
1b6b029e FB |
473 | abort(); |
474 | } | |
66fb9763 | 475 | process_pending_signals(env); |
1b6b029e FB |
476 | } |
477 | } | |
b346ff46 FB |
478 | #endif |
479 | ||
480 | #ifdef TARGET_ARM | |
481 | ||
992f48a0 | 482 | static void arm_cache_flush(abi_ulong start, abi_ulong last) |
6f1f31c0 | 483 | { |
992f48a0 | 484 | abi_ulong addr, last1; |
6f1f31c0 FB |
485 | |
486 | if (last < start) | |
487 | return; | |
488 | addr = start; | |
489 | for(;;) { | |
490 | last1 = ((addr + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK) - 1; | |
491 | if (last1 > last) | |
492 | last1 = last; | |
493 | tb_invalidate_page_range(addr, last1 + 1); | |
494 | if (last1 == last) | |
495 | break; | |
496 | addr = last1 + 1; | |
497 | } | |
498 | } | |
499 | ||
fbb4a2e3 PB |
500 | /* Handle a jump to the kernel code page. */ |
501 | static int | |
502 | do_kernel_trap(CPUARMState *env) | |
503 | { | |
504 | uint32_t addr; | |
505 | uint32_t cpsr; | |
506 | uint32_t val; | |
507 | ||
508 | switch (env->regs[15]) { | |
509 | case 0xffff0fa0: /* __kernel_memory_barrier */ | |
510 | /* ??? No-op. Will need to do better for SMP. */ | |
511 | break; | |
512 | case 0xffff0fc0: /* __kernel_cmpxchg */ | |
d5975363 PB |
513 | /* XXX: This only works between threads, not between processes. |
514 | It's probably possible to implement this with native host | |
515 | operations. However things like ldrex/strex are much harder so | |
516 | there's not much point trying. */ | |
517 | start_exclusive(); | |
fbb4a2e3 PB |
518 | cpsr = cpsr_read(env); |
519 | addr = env->regs[2]; | |
520 | /* FIXME: This should SEGV if the access fails. */ | |
521 | if (get_user_u32(val, addr)) | |
522 | val = ~env->regs[0]; | |
523 | if (val == env->regs[0]) { | |
524 | val = env->regs[1]; | |
525 | /* FIXME: Check for segfaults. */ | |
526 | put_user_u32(val, addr); | |
527 | env->regs[0] = 0; | |
528 | cpsr |= CPSR_C; | |
529 | } else { | |
530 | env->regs[0] = -1; | |
531 | cpsr &= ~CPSR_C; | |
532 | } | |
533 | cpsr_write(env, cpsr, CPSR_C); | |
d5975363 | 534 | end_exclusive(); |
fbb4a2e3 PB |
535 | break; |
536 | case 0xffff0fe0: /* __kernel_get_tls */ | |
537 | env->regs[0] = env->cp15.c13_tls2; | |
538 | break; | |
539 | default: | |
540 | return 1; | |
541 | } | |
542 | /* Jump back to the caller. */ | |
543 | addr = env->regs[14]; | |
544 | if (addr & 1) { | |
545 | env->thumb = 1; | |
546 | addr &= ~1; | |
547 | } | |
548 | env->regs[15] = addr; | |
549 | ||
550 | return 0; | |
551 | } | |
552 | ||
b346ff46 FB |
553 | void cpu_loop(CPUARMState *env) |
554 | { | |
555 | int trapnr; | |
556 | unsigned int n, insn; | |
557 | target_siginfo_t info; | |
b5ff1b31 | 558 | uint32_t addr; |
3b46e624 | 559 | |
b346ff46 | 560 | for(;;) { |
d5975363 | 561 | cpu_exec_start(env); |
b346ff46 | 562 | trapnr = cpu_arm_exec(env); |
d5975363 | 563 | cpu_exec_end(env); |
b346ff46 FB |
564 | switch(trapnr) { |
565 | case EXCP_UDEF: | |
c6981055 FB |
566 | { |
567 | TaskState *ts = env->opaque; | |
568 | uint32_t opcode; | |
6d9a42be | 569 | int rc; |
c6981055 FB |
570 | |
571 | /* we handle the FPU emulation here, as Linux */ | |
572 | /* we get the opcode */ | |
2f619698 FB |
573 | /* FIXME - what to do if get_user() fails? */ |
574 | get_user_u32(opcode, env->regs[15]); | |
3b46e624 | 575 | |
6d9a42be AJ |
576 | rc = EmulateAll(opcode, &ts->fpa, env); |
577 | if (rc == 0) { /* illegal instruction */ | |
c6981055 FB |
578 | info.si_signo = SIGILL; |
579 | info.si_errno = 0; | |
580 | info.si_code = TARGET_ILL_ILLOPN; | |
581 | info._sifields._sigfault._addr = env->regs[15]; | |
624f7979 | 582 | queue_signal(env, info.si_signo, &info); |
6d9a42be AJ |
583 | } else if (rc < 0) { /* FP exception */ |
584 | int arm_fpe=0; | |
585 | ||
586 | /* translate softfloat flags to FPSR flags */ | |
587 | if (-rc & float_flag_invalid) | |
588 | arm_fpe |= BIT_IOC; | |
589 | if (-rc & float_flag_divbyzero) | |
590 | arm_fpe |= BIT_DZC; | |
591 | if (-rc & float_flag_overflow) | |
592 | arm_fpe |= BIT_OFC; | |
593 | if (-rc & float_flag_underflow) | |
594 | arm_fpe |= BIT_UFC; | |
595 | if (-rc & float_flag_inexact) | |
596 | arm_fpe |= BIT_IXC; | |
597 | ||
598 | FPSR fpsr = ts->fpa.fpsr; | |
599 | //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe); | |
600 | ||
601 | if (fpsr & (arm_fpe << 16)) { /* exception enabled? */ | |
602 | info.si_signo = SIGFPE; | |
603 | info.si_errno = 0; | |
604 | ||
605 | /* ordered by priority, least first */ | |
606 | if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES; | |
607 | if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND; | |
608 | if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF; | |
609 | if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV; | |
610 | if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV; | |
611 | ||
612 | info._sifields._sigfault._addr = env->regs[15]; | |
624f7979 | 613 | queue_signal(env, info.si_signo, &info); |
6d9a42be AJ |
614 | } else { |
615 | env->regs[15] += 4; | |
616 | } | |
617 | ||
618 | /* accumulate unenabled exceptions */ | |
619 | if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC)) | |
620 | fpsr |= BIT_IXC; | |
621 | if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC)) | |
622 | fpsr |= BIT_UFC; | |
623 | if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC)) | |
624 | fpsr |= BIT_OFC; | |
625 | if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC)) | |
626 | fpsr |= BIT_DZC; | |
627 | if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC)) | |
628 | fpsr |= BIT_IOC; | |
629 | ts->fpa.fpsr=fpsr; | |
630 | } else { /* everything OK */ | |
c6981055 FB |
631 | /* increment PC */ |
632 | env->regs[15] += 4; | |
633 | } | |
634 | } | |
b346ff46 FB |
635 | break; |
636 | case EXCP_SWI: | |
06c949e6 | 637 | case EXCP_BKPT: |
b346ff46 | 638 | { |
ce4defa0 | 639 | env->eabi = 1; |
b346ff46 | 640 | /* system call */ |
06c949e6 PB |
641 | if (trapnr == EXCP_BKPT) { |
642 | if (env->thumb) { | |
2f619698 FB |
643 | /* FIXME - what to do if get_user() fails? */ |
644 | get_user_u16(insn, env->regs[15]); | |
06c949e6 PB |
645 | n = insn & 0xff; |
646 | env->regs[15] += 2; | |
647 | } else { | |
2f619698 FB |
648 | /* FIXME - what to do if get_user() fails? */ |
649 | get_user_u32(insn, env->regs[15]); | |
06c949e6 PB |
650 | n = (insn & 0xf) | ((insn >> 4) & 0xff0); |
651 | env->regs[15] += 4; | |
652 | } | |
192c7bd9 | 653 | } else { |
06c949e6 | 654 | if (env->thumb) { |
2f619698 FB |
655 | /* FIXME - what to do if get_user() fails? */ |
656 | get_user_u16(insn, env->regs[15] - 2); | |
06c949e6 PB |
657 | n = insn & 0xff; |
658 | } else { | |
2f619698 FB |
659 | /* FIXME - what to do if get_user() fails? */ |
660 | get_user_u32(insn, env->regs[15] - 4); | |
06c949e6 PB |
661 | n = insn & 0xffffff; |
662 | } | |
192c7bd9 FB |
663 | } |
664 | ||
6f1f31c0 FB |
665 | if (n == ARM_NR_cacheflush) { |
666 | arm_cache_flush(env->regs[0], env->regs[1]); | |
a4f81979 FB |
667 | } else if (n == ARM_NR_semihosting |
668 | || n == ARM_NR_thumb_semihosting) { | |
669 | env->regs[0] = do_arm_semihosting (env); | |
ce4defa0 | 670 | } else if (n == 0 || n >= ARM_SYSCALL_BASE |
192c7bd9 | 671 | || (env->thumb && n == ARM_THUMB_SYSCALL)) { |
b346ff46 | 672 | /* linux syscall */ |
ce4defa0 | 673 | if (env->thumb || n == 0) { |
192c7bd9 FB |
674 | n = env->regs[7]; |
675 | } else { | |
676 | n -= ARM_SYSCALL_BASE; | |
ce4defa0 | 677 | env->eabi = 0; |
192c7bd9 | 678 | } |
fbb4a2e3 PB |
679 | if ( n > ARM_NR_BASE) { |
680 | switch (n) { | |
681 | case ARM_NR_cacheflush: | |
682 | arm_cache_flush(env->regs[0], env->regs[1]); | |
683 | break; | |
684 | case ARM_NR_set_tls: | |
685 | cpu_set_tls(env, env->regs[0]); | |
686 | env->regs[0] = 0; | |
687 | break; | |
688 | default: | |
689 | gemu_log("qemu: Unsupported ARM syscall: 0x%x\n", | |
690 | n); | |
691 | env->regs[0] = -TARGET_ENOSYS; | |
692 | break; | |
693 | } | |
694 | } else { | |
695 | env->regs[0] = do_syscall(env, | |
696 | n, | |
697 | env->regs[0], | |
698 | env->regs[1], | |
699 | env->regs[2], | |
700 | env->regs[3], | |
701 | env->regs[4], | |
702 | env->regs[5]); | |
703 | } | |
b346ff46 FB |
704 | } else { |
705 | goto error; | |
706 | } | |
707 | } | |
708 | break; | |
43fff238 FB |
709 | case EXCP_INTERRUPT: |
710 | /* just indicate that signals should be handled asap */ | |
711 | break; | |
68016c62 | 712 | case EXCP_PREFETCH_ABORT: |
eae473c1 | 713 | addr = env->cp15.c6_insn; |
b5ff1b31 | 714 | goto do_segv; |
68016c62 | 715 | case EXCP_DATA_ABORT: |
eae473c1 | 716 | addr = env->cp15.c6_data; |
b5ff1b31 FB |
717 | goto do_segv; |
718 | do_segv: | |
68016c62 FB |
719 | { |
720 | info.si_signo = SIGSEGV; | |
721 | info.si_errno = 0; | |
722 | /* XXX: check env->error_code */ | |
723 | info.si_code = TARGET_SEGV_MAPERR; | |
b5ff1b31 | 724 | info._sifields._sigfault._addr = addr; |
624f7979 | 725 | queue_signal(env, info.si_signo, &info); |
68016c62 FB |
726 | } |
727 | break; | |
1fddef4b FB |
728 | case EXCP_DEBUG: |
729 | { | |
730 | int sig; | |
731 | ||
732 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
733 | if (sig) | |
734 | { | |
735 | info.si_signo = sig; | |
736 | info.si_errno = 0; | |
737 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 738 | queue_signal(env, info.si_signo, &info); |
1fddef4b FB |
739 | } |
740 | } | |
741 | break; | |
fbb4a2e3 PB |
742 | case EXCP_KERNEL_TRAP: |
743 | if (do_kernel_trap(env)) | |
744 | goto error; | |
745 | break; | |
b346ff46 FB |
746 | default: |
747 | error: | |
5fafdf24 | 748 | fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", |
b346ff46 | 749 | trapnr); |
7fe48483 | 750 | cpu_dump_state(env, stderr, fprintf, 0); |
b346ff46 FB |
751 | abort(); |
752 | } | |
753 | process_pending_signals(env); | |
754 | } | |
755 | } | |
756 | ||
757 | #endif | |
1b6b029e | 758 | |
93ac68bc | 759 | #ifdef TARGET_SPARC |
ed23fbd9 | 760 | #define SPARC64_STACK_BIAS 2047 |
93ac68bc | 761 | |
060366c5 FB |
762 | //#define DEBUG_WIN |
763 | ||
2623cbaf FB |
764 | /* WARNING: dealing with register windows _is_ complicated. More info |
765 | can be found at http://www.sics.se/~psm/sparcstack.html */ | |
060366c5 FB |
766 | static inline int get_reg_index(CPUSPARCState *env, int cwp, int index) |
767 | { | |
1a14026e | 768 | index = (index + cwp * 16) % (16 * env->nwindows); |
060366c5 FB |
769 | /* wrap handling : if cwp is on the last window, then we use the |
770 | registers 'after' the end */ | |
1a14026e BS |
771 | if (index < 8 && env->cwp == env->nwindows - 1) |
772 | index += 16 * env->nwindows; | |
060366c5 FB |
773 | return index; |
774 | } | |
775 | ||
2623cbaf FB |
776 | /* save the register window 'cwp1' */ |
777 | static inline void save_window_offset(CPUSPARCState *env, int cwp1) | |
060366c5 | 778 | { |
2623cbaf | 779 | unsigned int i; |
992f48a0 | 780 | abi_ulong sp_ptr; |
3b46e624 | 781 | |
53a5960a | 782 | sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; |
ed23fbd9 BS |
783 | #ifdef TARGET_SPARC64 |
784 | if (sp_ptr & 3) | |
785 | sp_ptr += SPARC64_STACK_BIAS; | |
786 | #endif | |
060366c5 | 787 | #if defined(DEBUG_WIN) |
2daf0284 BS |
788 | printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n", |
789 | sp_ptr, cwp1); | |
060366c5 | 790 | #endif |
2623cbaf | 791 | for(i = 0; i < 16; i++) { |
2f619698 FB |
792 | /* FIXME - what to do if put_user() fails? */ |
793 | put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); | |
992f48a0 | 794 | sp_ptr += sizeof(abi_ulong); |
2623cbaf | 795 | } |
060366c5 FB |
796 | } |
797 | ||
798 | static void save_window(CPUSPARCState *env) | |
799 | { | |
5ef54116 | 800 | #ifndef TARGET_SPARC64 |
2623cbaf | 801 | unsigned int new_wim; |
1a14026e BS |
802 | new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & |
803 | ((1LL << env->nwindows) - 1); | |
804 | save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); | |
2623cbaf | 805 | env->wim = new_wim; |
5ef54116 | 806 | #else |
1a14026e | 807 | save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); |
5ef54116 FB |
808 | env->cansave++; |
809 | env->canrestore--; | |
810 | #endif | |
060366c5 FB |
811 | } |
812 | ||
813 | static void restore_window(CPUSPARCState *env) | |
814 | { | |
eda52953 BS |
815 | #ifndef TARGET_SPARC64 |
816 | unsigned int new_wim; | |
817 | #endif | |
818 | unsigned int i, cwp1; | |
992f48a0 | 819 | abi_ulong sp_ptr; |
3b46e624 | 820 | |
eda52953 | 821 | #ifndef TARGET_SPARC64 |
1a14026e BS |
822 | new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) & |
823 | ((1LL << env->nwindows) - 1); | |
eda52953 | 824 | #endif |
3b46e624 | 825 | |
060366c5 | 826 | /* restore the invalid window */ |
1a14026e | 827 | cwp1 = cpu_cwp_inc(env, env->cwp + 1); |
53a5960a | 828 | sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; |
ed23fbd9 BS |
829 | #ifdef TARGET_SPARC64 |
830 | if (sp_ptr & 3) | |
831 | sp_ptr += SPARC64_STACK_BIAS; | |
832 | #endif | |
060366c5 | 833 | #if defined(DEBUG_WIN) |
2daf0284 BS |
834 | printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n", |
835 | sp_ptr, cwp1); | |
060366c5 | 836 | #endif |
2623cbaf | 837 | for(i = 0; i < 16; i++) { |
2f619698 FB |
838 | /* FIXME - what to do if get_user() fails? */ |
839 | get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); | |
992f48a0 | 840 | sp_ptr += sizeof(abi_ulong); |
2623cbaf | 841 | } |
5ef54116 FB |
842 | #ifdef TARGET_SPARC64 |
843 | env->canrestore++; | |
1a14026e BS |
844 | if (env->cleanwin < env->nwindows - 1) |
845 | env->cleanwin++; | |
5ef54116 | 846 | env->cansave--; |
eda52953 BS |
847 | #else |
848 | env->wim = new_wim; | |
5ef54116 | 849 | #endif |
060366c5 FB |
850 | } |
851 | ||
852 | static void flush_windows(CPUSPARCState *env) | |
853 | { | |
854 | int offset, cwp1; | |
2623cbaf FB |
855 | |
856 | offset = 1; | |
060366c5 FB |
857 | for(;;) { |
858 | /* if restore would invoke restore_window(), then we can stop */ | |
1a14026e | 859 | cwp1 = cpu_cwp_inc(env, env->cwp + offset); |
eda52953 | 860 | #ifndef TARGET_SPARC64 |
060366c5 FB |
861 | if (env->wim & (1 << cwp1)) |
862 | break; | |
eda52953 BS |
863 | #else |
864 | if (env->canrestore == 0) | |
865 | break; | |
866 | env->cansave++; | |
867 | env->canrestore--; | |
868 | #endif | |
2623cbaf | 869 | save_window_offset(env, cwp1); |
060366c5 FB |
870 | offset++; |
871 | } | |
1a14026e | 872 | cwp1 = cpu_cwp_inc(env, env->cwp + 1); |
eda52953 BS |
873 | #ifndef TARGET_SPARC64 |
874 | /* set wim so that restore will reload the registers */ | |
2623cbaf | 875 | env->wim = 1 << cwp1; |
eda52953 | 876 | #endif |
2623cbaf FB |
877 | #if defined(DEBUG_WIN) |
878 | printf("flush_windows: nb=%d\n", offset - 1); | |
80a9d035 | 879 | #endif |
2623cbaf | 880 | } |
060366c5 | 881 | |
93ac68bc FB |
882 | void cpu_loop (CPUSPARCState *env) |
883 | { | |
060366c5 | 884 | int trapnr, ret; |
61ff6f58 | 885 | target_siginfo_t info; |
3b46e624 | 886 | |
060366c5 FB |
887 | while (1) { |
888 | trapnr = cpu_sparc_exec (env); | |
3b46e624 | 889 | |
060366c5 | 890 | switch (trapnr) { |
5ef54116 | 891 | #ifndef TARGET_SPARC64 |
5fafdf24 | 892 | case 0x88: |
060366c5 | 893 | case 0x90: |
5ef54116 | 894 | #else |
cb33da57 | 895 | case 0x110: |
5ef54116 FB |
896 | case 0x16d: |
897 | #endif | |
060366c5 | 898 | ret = do_syscall (env, env->gregs[1], |
5fafdf24 TS |
899 | env->regwptr[0], env->regwptr[1], |
900 | env->regwptr[2], env->regwptr[3], | |
060366c5 FB |
901 | env->regwptr[4], env->regwptr[5]); |
902 | if ((unsigned int)ret >= (unsigned int)(-515)) { | |
992f48a0 | 903 | #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) |
27908725 FB |
904 | env->xcc |= PSR_CARRY; |
905 | #else | |
060366c5 | 906 | env->psr |= PSR_CARRY; |
27908725 | 907 | #endif |
060366c5 FB |
908 | ret = -ret; |
909 | } else { | |
992f48a0 | 910 | #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) |
27908725 FB |
911 | env->xcc &= ~PSR_CARRY; |
912 | #else | |
060366c5 | 913 | env->psr &= ~PSR_CARRY; |
27908725 | 914 | #endif |
060366c5 FB |
915 | } |
916 | env->regwptr[0] = ret; | |
917 | /* next instruction */ | |
918 | env->pc = env->npc; | |
919 | env->npc = env->npc + 4; | |
920 | break; | |
921 | case 0x83: /* flush windows */ | |
992f48a0 BS |
922 | #ifdef TARGET_ABI32 |
923 | case 0x103: | |
924 | #endif | |
2623cbaf | 925 | flush_windows(env); |
060366c5 FB |
926 | /* next instruction */ |
927 | env->pc = env->npc; | |
928 | env->npc = env->npc + 4; | |
929 | break; | |
3475187d | 930 | #ifndef TARGET_SPARC64 |
060366c5 FB |
931 | case TT_WIN_OVF: /* window overflow */ |
932 | save_window(env); | |
933 | break; | |
934 | case TT_WIN_UNF: /* window underflow */ | |
935 | restore_window(env); | |
936 | break; | |
61ff6f58 FB |
937 | case TT_TFAULT: |
938 | case TT_DFAULT: | |
939 | { | |
940 | info.si_signo = SIGSEGV; | |
941 | info.si_errno = 0; | |
942 | /* XXX: check env->error_code */ | |
943 | info.si_code = TARGET_SEGV_MAPERR; | |
944 | info._sifields._sigfault._addr = env->mmuregs[4]; | |
624f7979 | 945 | queue_signal(env, info.si_signo, &info); |
61ff6f58 FB |
946 | } |
947 | break; | |
3475187d | 948 | #else |
5ef54116 FB |
949 | case TT_SPILL: /* window overflow */ |
950 | save_window(env); | |
951 | break; | |
952 | case TT_FILL: /* window underflow */ | |
953 | restore_window(env); | |
954 | break; | |
7f84a729 BS |
955 | case TT_TFAULT: |
956 | case TT_DFAULT: | |
957 | { | |
958 | info.si_signo = SIGSEGV; | |
959 | info.si_errno = 0; | |
960 | /* XXX: check env->error_code */ | |
961 | info.si_code = TARGET_SEGV_MAPERR; | |
962 | if (trapnr == TT_DFAULT) | |
963 | info._sifields._sigfault._addr = env->dmmuregs[4]; | |
964 | else | |
375ee38b | 965 | info._sifields._sigfault._addr = env->tsptr->tpc; |
624f7979 | 966 | queue_signal(env, info.si_signo, &info); |
7f84a729 BS |
967 | } |
968 | break; | |
27524dc3 | 969 | #ifndef TARGET_ABI32 |
5bfb56b2 BS |
970 | case 0x16e: |
971 | flush_windows(env); | |
972 | sparc64_get_context(env); | |
973 | break; | |
974 | case 0x16f: | |
975 | flush_windows(env); | |
976 | sparc64_set_context(env); | |
977 | break; | |
27524dc3 | 978 | #endif |
3475187d | 979 | #endif |
48dc41eb FB |
980 | case EXCP_INTERRUPT: |
981 | /* just indicate that signals should be handled asap */ | |
982 | break; | |
1fddef4b FB |
983 | case EXCP_DEBUG: |
984 | { | |
985 | int sig; | |
986 | ||
987 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
988 | if (sig) | |
989 | { | |
990 | info.si_signo = sig; | |
991 | info.si_errno = 0; | |
992 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 993 | queue_signal(env, info.si_signo, &info); |
1fddef4b FB |
994 | } |
995 | } | |
996 | break; | |
060366c5 FB |
997 | default: |
998 | printf ("Unhandled trap: 0x%x\n", trapnr); | |
7fe48483 | 999 | cpu_dump_state(env, stderr, fprintf, 0); |
060366c5 FB |
1000 | exit (1); |
1001 | } | |
1002 | process_pending_signals (env); | |
1003 | } | |
93ac68bc FB |
1004 | } |
1005 | ||
1006 | #endif | |
1007 | ||
67867308 | 1008 | #ifdef TARGET_PPC |
9fddaa0c FB |
1009 | static inline uint64_t cpu_ppc_get_tb (CPUState *env) |
1010 | { | |
1011 | /* TO FIX */ | |
1012 | return 0; | |
1013 | } | |
3b46e624 | 1014 | |
9fddaa0c FB |
1015 | uint32_t cpu_ppc_load_tbl (CPUState *env) |
1016 | { | |
1017 | return cpu_ppc_get_tb(env) & 0xFFFFFFFF; | |
1018 | } | |
3b46e624 | 1019 | |
9fddaa0c FB |
1020 | uint32_t cpu_ppc_load_tbu (CPUState *env) |
1021 | { | |
1022 | return cpu_ppc_get_tb(env) >> 32; | |
1023 | } | |
3b46e624 | 1024 | |
a062e36c | 1025 | uint32_t cpu_ppc_load_atbl (CPUState *env) |
9fddaa0c | 1026 | { |
a062e36c | 1027 | return cpu_ppc_get_tb(env) & 0xFFFFFFFF; |
9fddaa0c | 1028 | } |
5fafdf24 | 1029 | |
a062e36c | 1030 | uint32_t cpu_ppc_load_atbu (CPUState *env) |
9fddaa0c | 1031 | { |
a062e36c | 1032 | return cpu_ppc_get_tb(env) >> 32; |
9fddaa0c | 1033 | } |
76a66253 | 1034 | |
76a66253 JM |
1035 | uint32_t cpu_ppc601_load_rtcu (CPUState *env) |
1036 | __attribute__ (( alias ("cpu_ppc_load_tbu") )); | |
1037 | ||
76a66253 | 1038 | uint32_t cpu_ppc601_load_rtcl (CPUState *env) |
9fddaa0c | 1039 | { |
76a66253 | 1040 | return cpu_ppc_load_tbl(env) & 0x3FFFFF80; |
9fddaa0c | 1041 | } |
76a66253 | 1042 | |
a750fc0b JM |
1043 | /* XXX: to be fixed */ |
1044 | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp) | |
1045 | { | |
1046 | return -1; | |
1047 | } | |
1048 | ||
1049 | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val) | |
1050 | { | |
1051 | return -1; | |
1052 | } | |
1053 | ||
001faf32 BS |
1054 | #define EXCP_DUMP(env, fmt, ...) \ |
1055 | do { \ | |
1056 | fprintf(stderr, fmt , ## __VA_ARGS__); \ | |
1057 | cpu_dump_state(env, stderr, fprintf, 0); \ | |
1058 | qemu_log(fmt, ## __VA_ARGS__); \ | |
430c7ec7 | 1059 | if (logfile) \ |
1060 | log_cpu_state(env, 0); \ | |
e1833e1f JM |
1061 | } while (0) |
1062 | ||
56f066bb NF |
1063 | static int do_store_exclusive(CPUPPCState *env) |
1064 | { | |
1065 | target_ulong addr; | |
1066 | target_ulong page_addr; | |
1067 | target_ulong val; | |
1068 | int flags; | |
1069 | int segv = 0; | |
1070 | ||
1071 | addr = env->reserve_ea; | |
1072 | page_addr = addr & TARGET_PAGE_MASK; | |
1073 | start_exclusive(); | |
1074 | mmap_lock(); | |
1075 | flags = page_get_flags(page_addr); | |
1076 | if ((flags & PAGE_READ) == 0) { | |
1077 | segv = 1; | |
1078 | } else { | |
1079 | int reg = env->reserve_info & 0x1f; | |
1080 | int size = (env->reserve_info >> 5) & 0xf; | |
1081 | int stored = 0; | |
1082 | ||
1083 | if (addr == env->reserve_addr) { | |
1084 | switch (size) { | |
1085 | case 1: segv = get_user_u8(val, addr); break; | |
1086 | case 2: segv = get_user_u16(val, addr); break; | |
1087 | case 4: segv = get_user_u32(val, addr); break; | |
1088 | #if defined(TARGET_PPC64) | |
1089 | case 8: segv = get_user_u64(val, addr); break; | |
1090 | #endif | |
1091 | default: abort(); | |
1092 | } | |
1093 | if (!segv && val == env->reserve_val) { | |
1094 | val = env->gpr[reg]; | |
1095 | switch (size) { | |
1096 | case 1: segv = put_user_u8(val, addr); break; | |
1097 | case 2: segv = put_user_u16(val, addr); break; | |
1098 | case 4: segv = put_user_u32(val, addr); break; | |
1099 | #if defined(TARGET_PPC64) | |
1100 | case 8: segv = put_user_u64(val, addr); break; | |
1101 | #endif | |
1102 | default: abort(); | |
1103 | } | |
1104 | if (!segv) { | |
1105 | stored = 1; | |
1106 | } | |
1107 | } | |
1108 | } | |
1109 | env->crf[0] = (stored << 1) | xer_so; | |
1110 | env->reserve_addr = (target_ulong)-1; | |
1111 | } | |
1112 | if (!segv) { | |
1113 | env->nip += 4; | |
1114 | } | |
1115 | mmap_unlock(); | |
1116 | end_exclusive(); | |
1117 | return segv; | |
1118 | } | |
1119 | ||
67867308 FB |
1120 | void cpu_loop(CPUPPCState *env) |
1121 | { | |
67867308 | 1122 | target_siginfo_t info; |
61190b14 FB |
1123 | int trapnr; |
1124 | uint32_t ret; | |
3b46e624 | 1125 | |
67867308 | 1126 | for(;;) { |
56f066bb | 1127 | cpu_exec_start(env); |
67867308 | 1128 | trapnr = cpu_ppc_exec(env); |
56f066bb | 1129 | cpu_exec_end(env); |
67867308 | 1130 | switch(trapnr) { |
e1833e1f JM |
1131 | case POWERPC_EXCP_NONE: |
1132 | /* Just go on */ | |
67867308 | 1133 | break; |
e1833e1f JM |
1134 | case POWERPC_EXCP_CRITICAL: /* Critical input */ |
1135 | cpu_abort(env, "Critical interrupt while in user mode. " | |
1136 | "Aborting\n"); | |
61190b14 | 1137 | break; |
e1833e1f JM |
1138 | case POWERPC_EXCP_MCHECK: /* Machine check exception */ |
1139 | cpu_abort(env, "Machine check exception while in user mode. " | |
1140 | "Aborting\n"); | |
1141 | break; | |
1142 | case POWERPC_EXCP_DSI: /* Data storage exception */ | |
1143 | EXCP_DUMP(env, "Invalid data memory access: 0x" ADDRX "\n", | |
1144 | env->spr[SPR_DAR]); | |
1145 | /* XXX: check this. Seems bugged */ | |
2be0071f FB |
1146 | switch (env->error_code & 0xFF000000) { |
1147 | case 0x40000000: | |
61190b14 FB |
1148 | info.si_signo = TARGET_SIGSEGV; |
1149 | info.si_errno = 0; | |
1150 | info.si_code = TARGET_SEGV_MAPERR; | |
1151 | break; | |
2be0071f | 1152 | case 0x04000000: |
61190b14 FB |
1153 | info.si_signo = TARGET_SIGILL; |
1154 | info.si_errno = 0; | |
1155 | info.si_code = TARGET_ILL_ILLADR; | |
1156 | break; | |
2be0071f | 1157 | case 0x08000000: |
61190b14 FB |
1158 | info.si_signo = TARGET_SIGSEGV; |
1159 | info.si_errno = 0; | |
1160 | info.si_code = TARGET_SEGV_ACCERR; | |
1161 | break; | |
61190b14 FB |
1162 | default: |
1163 | /* Let's send a regular segfault... */ | |
e1833e1f JM |
1164 | EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", |
1165 | env->error_code); | |
61190b14 FB |
1166 | info.si_signo = TARGET_SIGSEGV; |
1167 | info.si_errno = 0; | |
1168 | info.si_code = TARGET_SEGV_MAPERR; | |
1169 | break; | |
1170 | } | |
67867308 | 1171 | info._sifields._sigfault._addr = env->nip; |
624f7979 | 1172 | queue_signal(env, info.si_signo, &info); |
67867308 | 1173 | break; |
e1833e1f JM |
1174 | case POWERPC_EXCP_ISI: /* Instruction storage exception */ |
1175 | EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" ADDRX "\n", | |
f10c315f | 1176 | env->spr[SPR_SRR0]); |
e1833e1f | 1177 | /* XXX: check this */ |
2be0071f FB |
1178 | switch (env->error_code & 0xFF000000) { |
1179 | case 0x40000000: | |
61190b14 | 1180 | info.si_signo = TARGET_SIGSEGV; |
67867308 | 1181 | info.si_errno = 0; |
61190b14 FB |
1182 | info.si_code = TARGET_SEGV_MAPERR; |
1183 | break; | |
2be0071f FB |
1184 | case 0x10000000: |
1185 | case 0x08000000: | |
61190b14 FB |
1186 | info.si_signo = TARGET_SIGSEGV; |
1187 | info.si_errno = 0; | |
1188 | info.si_code = TARGET_SEGV_ACCERR; | |
1189 | break; | |
1190 | default: | |
1191 | /* Let's send a regular segfault... */ | |
e1833e1f JM |
1192 | EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", |
1193 | env->error_code); | |
61190b14 FB |
1194 | info.si_signo = TARGET_SIGSEGV; |
1195 | info.si_errno = 0; | |
1196 | info.si_code = TARGET_SEGV_MAPERR; | |
1197 | break; | |
1198 | } | |
1199 | info._sifields._sigfault._addr = env->nip - 4; | |
624f7979 | 1200 | queue_signal(env, info.si_signo, &info); |
67867308 | 1201 | break; |
e1833e1f JM |
1202 | case POWERPC_EXCP_EXTERNAL: /* External input */ |
1203 | cpu_abort(env, "External interrupt while in user mode. " | |
1204 | "Aborting\n"); | |
1205 | break; | |
1206 | case POWERPC_EXCP_ALIGN: /* Alignment exception */ | |
1207 | EXCP_DUMP(env, "Unaligned memory access\n"); | |
1208 | /* XXX: check this */ | |
61190b14 | 1209 | info.si_signo = TARGET_SIGBUS; |
67867308 | 1210 | info.si_errno = 0; |
61190b14 FB |
1211 | info.si_code = TARGET_BUS_ADRALN; |
1212 | info._sifields._sigfault._addr = env->nip - 4; | |
624f7979 | 1213 | queue_signal(env, info.si_signo, &info); |
67867308 | 1214 | break; |
e1833e1f JM |
1215 | case POWERPC_EXCP_PROGRAM: /* Program exception */ |
1216 | /* XXX: check this */ | |
61190b14 | 1217 | switch (env->error_code & ~0xF) { |
e1833e1f JM |
1218 | case POWERPC_EXCP_FP: |
1219 | EXCP_DUMP(env, "Floating point program exception\n"); | |
61190b14 FB |
1220 | info.si_signo = TARGET_SIGFPE; |
1221 | info.si_errno = 0; | |
1222 | switch (env->error_code & 0xF) { | |
e1833e1f | 1223 | case POWERPC_EXCP_FP_OX: |
61190b14 FB |
1224 | info.si_code = TARGET_FPE_FLTOVF; |
1225 | break; | |
e1833e1f | 1226 | case POWERPC_EXCP_FP_UX: |
61190b14 FB |
1227 | info.si_code = TARGET_FPE_FLTUND; |
1228 | break; | |
e1833e1f JM |
1229 | case POWERPC_EXCP_FP_ZX: |
1230 | case POWERPC_EXCP_FP_VXZDZ: | |
61190b14 FB |
1231 | info.si_code = TARGET_FPE_FLTDIV; |
1232 | break; | |
e1833e1f | 1233 | case POWERPC_EXCP_FP_XX: |
61190b14 FB |
1234 | info.si_code = TARGET_FPE_FLTRES; |
1235 | break; | |
e1833e1f | 1236 | case POWERPC_EXCP_FP_VXSOFT: |
61190b14 FB |
1237 | info.si_code = TARGET_FPE_FLTINV; |
1238 | break; | |
7c58044c | 1239 | case POWERPC_EXCP_FP_VXSNAN: |
e1833e1f JM |
1240 | case POWERPC_EXCP_FP_VXISI: |
1241 | case POWERPC_EXCP_FP_VXIDI: | |
1242 | case POWERPC_EXCP_FP_VXIMZ: | |
1243 | case POWERPC_EXCP_FP_VXVC: | |
1244 | case POWERPC_EXCP_FP_VXSQRT: | |
1245 | case POWERPC_EXCP_FP_VXCVI: | |
61190b14 FB |
1246 | info.si_code = TARGET_FPE_FLTSUB; |
1247 | break; | |
1248 | default: | |
e1833e1f JM |
1249 | EXCP_DUMP(env, "Unknown floating point exception (%02x)\n", |
1250 | env->error_code); | |
1251 | break; | |
61190b14 | 1252 | } |
e1833e1f JM |
1253 | break; |
1254 | case POWERPC_EXCP_INVAL: | |
1255 | EXCP_DUMP(env, "Invalid instruction\n"); | |
61190b14 FB |
1256 | info.si_signo = TARGET_SIGILL; |
1257 | info.si_errno = 0; | |
1258 | switch (env->error_code & 0xF) { | |
e1833e1f | 1259 | case POWERPC_EXCP_INVAL_INVAL: |
61190b14 FB |
1260 | info.si_code = TARGET_ILL_ILLOPC; |
1261 | break; | |
e1833e1f | 1262 | case POWERPC_EXCP_INVAL_LSWX: |
a750fc0b | 1263 | info.si_code = TARGET_ILL_ILLOPN; |
61190b14 | 1264 | break; |
e1833e1f | 1265 | case POWERPC_EXCP_INVAL_SPR: |
61190b14 FB |
1266 | info.si_code = TARGET_ILL_PRVREG; |
1267 | break; | |
e1833e1f | 1268 | case POWERPC_EXCP_INVAL_FP: |
61190b14 FB |
1269 | info.si_code = TARGET_ILL_COPROC; |
1270 | break; | |
1271 | default: | |
e1833e1f JM |
1272 | EXCP_DUMP(env, "Unknown invalid operation (%02x)\n", |
1273 | env->error_code & 0xF); | |
61190b14 FB |
1274 | info.si_code = TARGET_ILL_ILLADR; |
1275 | break; | |
1276 | } | |
1277 | break; | |
e1833e1f JM |
1278 | case POWERPC_EXCP_PRIV: |
1279 | EXCP_DUMP(env, "Privilege violation\n"); | |
61190b14 FB |
1280 | info.si_signo = TARGET_SIGILL; |
1281 | info.si_errno = 0; | |
1282 | switch (env->error_code & 0xF) { | |
e1833e1f | 1283 | case POWERPC_EXCP_PRIV_OPC: |
61190b14 FB |
1284 | info.si_code = TARGET_ILL_PRVOPC; |
1285 | break; | |
e1833e1f | 1286 | case POWERPC_EXCP_PRIV_REG: |
61190b14 | 1287 | info.si_code = TARGET_ILL_PRVREG; |
e1833e1f | 1288 | break; |
61190b14 | 1289 | default: |
e1833e1f JM |
1290 | EXCP_DUMP(env, "Unknown privilege violation (%02x)\n", |
1291 | env->error_code & 0xF); | |
61190b14 FB |
1292 | info.si_code = TARGET_ILL_PRVOPC; |
1293 | break; | |
1294 | } | |
1295 | break; | |
e1833e1f JM |
1296 | case POWERPC_EXCP_TRAP: |
1297 | cpu_abort(env, "Tried to call a TRAP\n"); | |
1298 | break; | |
61190b14 FB |
1299 | default: |
1300 | /* Should not happen ! */ | |
e1833e1f JM |
1301 | cpu_abort(env, "Unknown program exception (%02x)\n", |
1302 | env->error_code); | |
1303 | break; | |
61190b14 FB |
1304 | } |
1305 | info._sifields._sigfault._addr = env->nip - 4; | |
624f7979 | 1306 | queue_signal(env, info.si_signo, &info); |
67867308 | 1307 | break; |
e1833e1f JM |
1308 | case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ |
1309 | EXCP_DUMP(env, "No floating point allowed\n"); | |
61190b14 | 1310 | info.si_signo = TARGET_SIGILL; |
67867308 | 1311 | info.si_errno = 0; |
61190b14 FB |
1312 | info.si_code = TARGET_ILL_COPROC; |
1313 | info._sifields._sigfault._addr = env->nip - 4; | |
624f7979 | 1314 | queue_signal(env, info.si_signo, &info); |
67867308 | 1315 | break; |
e1833e1f JM |
1316 | case POWERPC_EXCP_SYSCALL: /* System call exception */ |
1317 | cpu_abort(env, "Syscall exception while in user mode. " | |
1318 | "Aborting\n"); | |
61190b14 | 1319 | break; |
e1833e1f JM |
1320 | case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ |
1321 | EXCP_DUMP(env, "No APU instruction allowed\n"); | |
1322 | info.si_signo = TARGET_SIGILL; | |
1323 | info.si_errno = 0; | |
1324 | info.si_code = TARGET_ILL_COPROC; | |
1325 | info._sifields._sigfault._addr = env->nip - 4; | |
624f7979 | 1326 | queue_signal(env, info.si_signo, &info); |
61190b14 | 1327 | break; |
e1833e1f JM |
1328 | case POWERPC_EXCP_DECR: /* Decrementer exception */ |
1329 | cpu_abort(env, "Decrementer interrupt while in user mode. " | |
1330 | "Aborting\n"); | |
61190b14 | 1331 | break; |
e1833e1f JM |
1332 | case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ |
1333 | cpu_abort(env, "Fix interval timer interrupt while in user mode. " | |
1334 | "Aborting\n"); | |
1335 | break; | |
1336 | case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ | |
1337 | cpu_abort(env, "Watchdog timer interrupt while in user mode. " | |
1338 | "Aborting\n"); | |
1339 | break; | |
1340 | case POWERPC_EXCP_DTLB: /* Data TLB error */ | |
1341 | cpu_abort(env, "Data TLB exception while in user mode. " | |
1342 | "Aborting\n"); | |
1343 | break; | |
1344 | case POWERPC_EXCP_ITLB: /* Instruction TLB error */ | |
1345 | cpu_abort(env, "Instruction TLB exception while in user mode. " | |
1346 | "Aborting\n"); | |
1347 | break; | |
e1833e1f JM |
1348 | case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */ |
1349 | EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n"); | |
1350 | info.si_signo = TARGET_SIGILL; | |
1351 | info.si_errno = 0; | |
1352 | info.si_code = TARGET_ILL_COPROC; | |
1353 | info._sifields._sigfault._addr = env->nip - 4; | |
624f7979 | 1354 | queue_signal(env, info.si_signo, &info); |
e1833e1f JM |
1355 | break; |
1356 | case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */ | |
1357 | cpu_abort(env, "Embedded floating-point data IRQ not handled\n"); | |
1358 | break; | |
1359 | case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */ | |
1360 | cpu_abort(env, "Embedded floating-point round IRQ not handled\n"); | |
1361 | break; | |
1362 | case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */ | |
1363 | cpu_abort(env, "Performance monitor exception not handled\n"); | |
1364 | break; | |
1365 | case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ | |
1366 | cpu_abort(env, "Doorbell interrupt while in user mode. " | |
1367 | "Aborting\n"); | |
1368 | break; | |
1369 | case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ | |
1370 | cpu_abort(env, "Doorbell critical interrupt while in user mode. " | |
1371 | "Aborting\n"); | |
1372 | break; | |
1373 | case POWERPC_EXCP_RESET: /* System reset exception */ | |
1374 | cpu_abort(env, "Reset interrupt while in user mode. " | |
1375 | "Aborting\n"); | |
1376 | break; | |
e1833e1f JM |
1377 | case POWERPC_EXCP_DSEG: /* Data segment exception */ |
1378 | cpu_abort(env, "Data segment exception while in user mode. " | |
1379 | "Aborting\n"); | |
1380 | break; | |
1381 | case POWERPC_EXCP_ISEG: /* Instruction segment exception */ | |
1382 | cpu_abort(env, "Instruction segment exception " | |
1383 | "while in user mode. Aborting\n"); | |
1384 | break; | |
e85e7c6e | 1385 | /* PowerPC 64 with hypervisor mode support */ |
e1833e1f JM |
1386 | case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ |
1387 | cpu_abort(env, "Hypervisor decrementer interrupt " | |
1388 | "while in user mode. Aborting\n"); | |
1389 | break; | |
e1833e1f JM |
1390 | case POWERPC_EXCP_TRACE: /* Trace exception */ |
1391 | /* Nothing to do: | |
1392 | * we use this exception to emulate step-by-step execution mode. | |
1393 | */ | |
1394 | break; | |
e85e7c6e | 1395 | /* PowerPC 64 with hypervisor mode support */ |
e1833e1f JM |
1396 | case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ |
1397 | cpu_abort(env, "Hypervisor data storage exception " | |
1398 | "while in user mode. Aborting\n"); | |
1399 | break; | |
1400 | case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */ | |
1401 | cpu_abort(env, "Hypervisor instruction storage exception " | |
1402 | "while in user mode. Aborting\n"); | |
1403 | break; | |
1404 | case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ | |
1405 | cpu_abort(env, "Hypervisor data segment exception " | |
1406 | "while in user mode. Aborting\n"); | |
1407 | break; | |
1408 | case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */ | |
1409 | cpu_abort(env, "Hypervisor instruction segment exception " | |
1410 | "while in user mode. Aborting\n"); | |
1411 | break; | |
e1833e1f JM |
1412 | case POWERPC_EXCP_VPU: /* Vector unavailable exception */ |
1413 | EXCP_DUMP(env, "No Altivec instructions allowed\n"); | |
1414 | info.si_signo = TARGET_SIGILL; | |
1415 | info.si_errno = 0; | |
1416 | info.si_code = TARGET_ILL_COPROC; | |
1417 | info._sifields._sigfault._addr = env->nip - 4; | |
624f7979 | 1418 | queue_signal(env, info.si_signo, &info); |
e1833e1f JM |
1419 | break; |
1420 | case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */ | |
1421 | cpu_abort(env, "Programable interval timer interrupt " | |
1422 | "while in user mode. Aborting\n"); | |
1423 | break; | |
1424 | case POWERPC_EXCP_IO: /* IO error exception */ | |
1425 | cpu_abort(env, "IO error exception while in user mode. " | |
1426 | "Aborting\n"); | |
1427 | break; | |
1428 | case POWERPC_EXCP_RUNM: /* Run mode exception */ | |
1429 | cpu_abort(env, "Run mode exception while in user mode. " | |
1430 | "Aborting\n"); | |
1431 | break; | |
1432 | case POWERPC_EXCP_EMUL: /* Emulation trap exception */ | |
1433 | cpu_abort(env, "Emulation trap exception not handled\n"); | |
1434 | break; | |
1435 | case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ | |
1436 | cpu_abort(env, "Instruction fetch TLB exception " | |
1437 | "while in user-mode. Aborting"); | |
1438 | break; | |
1439 | case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ | |
1440 | cpu_abort(env, "Data load TLB exception while in user-mode. " | |
1441 | "Aborting"); | |
1442 | break; | |
1443 | case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ | |
1444 | cpu_abort(env, "Data store TLB exception while in user-mode. " | |
1445 | "Aborting"); | |
1446 | break; | |
1447 | case POWERPC_EXCP_FPA: /* Floating-point assist exception */ | |
1448 | cpu_abort(env, "Floating-point assist exception not handled\n"); | |
1449 | break; | |
1450 | case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ | |
1451 | cpu_abort(env, "Instruction address breakpoint exception " | |
1452 | "not handled\n"); | |
1453 | break; | |
1454 | case POWERPC_EXCP_SMI: /* System management interrupt */ | |
1455 | cpu_abort(env, "System management interrupt while in user mode. " | |
1456 | "Aborting\n"); | |
1457 | break; | |
1458 | case POWERPC_EXCP_THERM: /* Thermal interrupt */ | |
1459 | cpu_abort(env, "Thermal interrupt interrupt while in user mode. " | |
1460 | "Aborting\n"); | |
1461 | break; | |
1462 | case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */ | |
1463 | cpu_abort(env, "Performance monitor exception not handled\n"); | |
1464 | break; | |
1465 | case POWERPC_EXCP_VPUA: /* Vector assist exception */ | |
1466 | cpu_abort(env, "Vector assist exception not handled\n"); | |
1467 | break; | |
1468 | case POWERPC_EXCP_SOFTP: /* Soft patch exception */ | |
1469 | cpu_abort(env, "Soft patch exception not handled\n"); | |
1470 | break; | |
1471 | case POWERPC_EXCP_MAINT: /* Maintenance exception */ | |
1472 | cpu_abort(env, "Maintenance exception while in user mode. " | |
1473 | "Aborting\n"); | |
1474 | break; | |
1475 | case POWERPC_EXCP_STOP: /* stop translation */ | |
1476 | /* We did invalidate the instruction cache. Go on */ | |
1477 | break; | |
1478 | case POWERPC_EXCP_BRANCH: /* branch instruction: */ | |
1479 | /* We just stopped because of a branch. Go on */ | |
1480 | break; | |
1481 | case POWERPC_EXCP_SYSCALL_USER: | |
1482 | /* system call in user-mode emulation */ | |
1483 | /* WARNING: | |
1484 | * PPC ABI uses overflow flag in cr0 to signal an error | |
1485 | * in syscalls. | |
1486 | */ | |
1487 | #if 0 | |
1488 | printf("syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n", env->gpr[0], | |
1489 | env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6]); | |
1490 | #endif | |
1491 | env->crf[0] &= ~0x1; | |
1492 | ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4], | |
1493 | env->gpr[5], env->gpr[6], env->gpr[7], | |
1494 | env->gpr[8]); | |
bcd4933a NF |
1495 | if (ret == (uint32_t)(-TARGET_QEMU_ESIGRETURN)) { |
1496 | /* Returning from a successful sigreturn syscall. | |
1497 | Avoid corrupting register state. */ | |
1498 | break; | |
1499 | } | |
e1833e1f JM |
1500 | if (ret > (uint32_t)(-515)) { |
1501 | env->crf[0] |= 0x1; | |
1502 | ret = -ret; | |
61190b14 | 1503 | } |
e1833e1f JM |
1504 | env->gpr[3] = ret; |
1505 | #if 0 | |
1506 | printf("syscall returned 0x%08x (%d)\n", ret, ret); | |
1507 | #endif | |
1508 | break; | |
56f066bb NF |
1509 | case POWERPC_EXCP_STCX: |
1510 | if (do_store_exclusive(env)) { | |
1511 | info.si_signo = TARGET_SIGSEGV; | |
1512 | info.si_errno = 0; | |
1513 | info.si_code = TARGET_SEGV_MAPERR; | |
1514 | info._sifields._sigfault._addr = env->nip; | |
1515 | queue_signal(env, info.si_signo, &info); | |
1516 | } | |
1517 | break; | |
71f75756 AJ |
1518 | case EXCP_DEBUG: |
1519 | { | |
1520 | int sig; | |
1521 | ||
1522 | sig = gdb_handlesig(env, TARGET_SIGTRAP); | |
1523 | if (sig) { | |
1524 | info.si_signo = sig; | |
1525 | info.si_errno = 0; | |
1526 | info.si_code = TARGET_TRAP_BRKPT; | |
1527 | queue_signal(env, info.si_signo, &info); | |
1528 | } | |
1529 | } | |
1530 | break; | |
56ba31ff JM |
1531 | case EXCP_INTERRUPT: |
1532 | /* just indicate that signals should be handled asap */ | |
1533 | break; | |
e1833e1f JM |
1534 | default: |
1535 | cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr); | |
1536 | break; | |
67867308 FB |
1537 | } |
1538 | process_pending_signals(env); | |
1539 | } | |
1540 | } | |
1541 | #endif | |
1542 | ||
048f6b4d FB |
1543 | #ifdef TARGET_MIPS |
1544 | ||
1545 | #define MIPS_SYS(name, args) args, | |
1546 | ||
1547 | static const uint8_t mips_syscall_args[] = { | |
1548 | MIPS_SYS(sys_syscall , 0) /* 4000 */ | |
1549 | MIPS_SYS(sys_exit , 1) | |
1550 | MIPS_SYS(sys_fork , 0) | |
1551 | MIPS_SYS(sys_read , 3) | |
1552 | MIPS_SYS(sys_write , 3) | |
1553 | MIPS_SYS(sys_open , 3) /* 4005 */ | |
1554 | MIPS_SYS(sys_close , 1) | |
1555 | MIPS_SYS(sys_waitpid , 3) | |
1556 | MIPS_SYS(sys_creat , 2) | |
1557 | MIPS_SYS(sys_link , 2) | |
1558 | MIPS_SYS(sys_unlink , 1) /* 4010 */ | |
1559 | MIPS_SYS(sys_execve , 0) | |
1560 | MIPS_SYS(sys_chdir , 1) | |
1561 | MIPS_SYS(sys_time , 1) | |
1562 | MIPS_SYS(sys_mknod , 3) | |
1563 | MIPS_SYS(sys_chmod , 2) /* 4015 */ | |
1564 | MIPS_SYS(sys_lchown , 3) | |
1565 | MIPS_SYS(sys_ni_syscall , 0) | |
1566 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */ | |
1567 | MIPS_SYS(sys_lseek , 3) | |
1568 | MIPS_SYS(sys_getpid , 0) /* 4020 */ | |
1569 | MIPS_SYS(sys_mount , 5) | |
1570 | MIPS_SYS(sys_oldumount , 1) | |
1571 | MIPS_SYS(sys_setuid , 1) | |
1572 | MIPS_SYS(sys_getuid , 0) | |
1573 | MIPS_SYS(sys_stime , 1) /* 4025 */ | |
1574 | MIPS_SYS(sys_ptrace , 4) | |
1575 | MIPS_SYS(sys_alarm , 1) | |
1576 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */ | |
1577 | MIPS_SYS(sys_pause , 0) | |
1578 | MIPS_SYS(sys_utime , 2) /* 4030 */ | |
1579 | MIPS_SYS(sys_ni_syscall , 0) | |
1580 | MIPS_SYS(sys_ni_syscall , 0) | |
1581 | MIPS_SYS(sys_access , 2) | |
1582 | MIPS_SYS(sys_nice , 1) | |
1583 | MIPS_SYS(sys_ni_syscall , 0) /* 4035 */ | |
1584 | MIPS_SYS(sys_sync , 0) | |
1585 | MIPS_SYS(sys_kill , 2) | |
1586 | MIPS_SYS(sys_rename , 2) | |
1587 | MIPS_SYS(sys_mkdir , 2) | |
1588 | MIPS_SYS(sys_rmdir , 1) /* 4040 */ | |
1589 | MIPS_SYS(sys_dup , 1) | |
1590 | MIPS_SYS(sys_pipe , 0) | |
1591 | MIPS_SYS(sys_times , 1) | |
1592 | MIPS_SYS(sys_ni_syscall , 0) | |
1593 | MIPS_SYS(sys_brk , 1) /* 4045 */ | |
1594 | MIPS_SYS(sys_setgid , 1) | |
1595 | MIPS_SYS(sys_getgid , 0) | |
1596 | MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */ | |
1597 | MIPS_SYS(sys_geteuid , 0) | |
1598 | MIPS_SYS(sys_getegid , 0) /* 4050 */ | |
1599 | MIPS_SYS(sys_acct , 0) | |
1600 | MIPS_SYS(sys_umount , 2) | |
1601 | MIPS_SYS(sys_ni_syscall , 0) | |
1602 | MIPS_SYS(sys_ioctl , 3) | |
1603 | MIPS_SYS(sys_fcntl , 3) /* 4055 */ | |
1604 | MIPS_SYS(sys_ni_syscall , 2) | |
1605 | MIPS_SYS(sys_setpgid , 2) | |
1606 | MIPS_SYS(sys_ni_syscall , 0) | |
1607 | MIPS_SYS(sys_olduname , 1) | |
1608 | MIPS_SYS(sys_umask , 1) /* 4060 */ | |
1609 | MIPS_SYS(sys_chroot , 1) | |
1610 | MIPS_SYS(sys_ustat , 2) | |
1611 | MIPS_SYS(sys_dup2 , 2) | |
1612 | MIPS_SYS(sys_getppid , 0) | |
1613 | MIPS_SYS(sys_getpgrp , 0) /* 4065 */ | |
1614 | MIPS_SYS(sys_setsid , 0) | |
1615 | MIPS_SYS(sys_sigaction , 3) | |
1616 | MIPS_SYS(sys_sgetmask , 0) | |
1617 | MIPS_SYS(sys_ssetmask , 1) | |
1618 | MIPS_SYS(sys_setreuid , 2) /* 4070 */ | |
1619 | MIPS_SYS(sys_setregid , 2) | |
1620 | MIPS_SYS(sys_sigsuspend , 0) | |
1621 | MIPS_SYS(sys_sigpending , 1) | |
1622 | MIPS_SYS(sys_sethostname , 2) | |
1623 | MIPS_SYS(sys_setrlimit , 2) /* 4075 */ | |
1624 | MIPS_SYS(sys_getrlimit , 2) | |
1625 | MIPS_SYS(sys_getrusage , 2) | |
1626 | MIPS_SYS(sys_gettimeofday, 2) | |
1627 | MIPS_SYS(sys_settimeofday, 2) | |
1628 | MIPS_SYS(sys_getgroups , 2) /* 4080 */ | |
1629 | MIPS_SYS(sys_setgroups , 2) | |
1630 | MIPS_SYS(sys_ni_syscall , 0) /* old_select */ | |
1631 | MIPS_SYS(sys_symlink , 2) | |
1632 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */ | |
1633 | MIPS_SYS(sys_readlink , 3) /* 4085 */ | |
1634 | MIPS_SYS(sys_uselib , 1) | |
1635 | MIPS_SYS(sys_swapon , 2) | |
1636 | MIPS_SYS(sys_reboot , 3) | |
1637 | MIPS_SYS(old_readdir , 3) | |
1638 | MIPS_SYS(old_mmap , 6) /* 4090 */ | |
1639 | MIPS_SYS(sys_munmap , 2) | |
1640 | MIPS_SYS(sys_truncate , 2) | |
1641 | MIPS_SYS(sys_ftruncate , 2) | |
1642 | MIPS_SYS(sys_fchmod , 2) | |
1643 | MIPS_SYS(sys_fchown , 3) /* 4095 */ | |
1644 | MIPS_SYS(sys_getpriority , 2) | |
1645 | MIPS_SYS(sys_setpriority , 3) | |
1646 | MIPS_SYS(sys_ni_syscall , 0) | |
1647 | MIPS_SYS(sys_statfs , 2) | |
1648 | MIPS_SYS(sys_fstatfs , 2) /* 4100 */ | |
1649 | MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */ | |
1650 | MIPS_SYS(sys_socketcall , 2) | |
1651 | MIPS_SYS(sys_syslog , 3) | |
1652 | MIPS_SYS(sys_setitimer , 3) | |
1653 | MIPS_SYS(sys_getitimer , 2) /* 4105 */ | |
1654 | MIPS_SYS(sys_newstat , 2) | |
1655 | MIPS_SYS(sys_newlstat , 2) | |
1656 | MIPS_SYS(sys_newfstat , 2) | |
1657 | MIPS_SYS(sys_uname , 1) | |
1658 | MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */ | |
1659 | MIPS_SYS(sys_vhangup , 0) | |
1660 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */ | |
1661 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */ | |
1662 | MIPS_SYS(sys_wait4 , 4) | |
1663 | MIPS_SYS(sys_swapoff , 1) /* 4115 */ | |
1664 | MIPS_SYS(sys_sysinfo , 1) | |
1665 | MIPS_SYS(sys_ipc , 6) | |
1666 | MIPS_SYS(sys_fsync , 1) | |
1667 | MIPS_SYS(sys_sigreturn , 0) | |
18113962 | 1668 | MIPS_SYS(sys_clone , 6) /* 4120 */ |
048f6b4d FB |
1669 | MIPS_SYS(sys_setdomainname, 2) |
1670 | MIPS_SYS(sys_newuname , 1) | |
1671 | MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */ | |
1672 | MIPS_SYS(sys_adjtimex , 1) | |
1673 | MIPS_SYS(sys_mprotect , 3) /* 4125 */ | |
1674 | MIPS_SYS(sys_sigprocmask , 3) | |
1675 | MIPS_SYS(sys_ni_syscall , 0) /* was create_module */ | |
1676 | MIPS_SYS(sys_init_module , 5) | |
1677 | MIPS_SYS(sys_delete_module, 1) | |
1678 | MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */ | |
1679 | MIPS_SYS(sys_quotactl , 0) | |
1680 | MIPS_SYS(sys_getpgid , 1) | |
1681 | MIPS_SYS(sys_fchdir , 1) | |
1682 | MIPS_SYS(sys_bdflush , 2) | |
1683 | MIPS_SYS(sys_sysfs , 3) /* 4135 */ | |
1684 | MIPS_SYS(sys_personality , 1) | |
1685 | MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */ | |
1686 | MIPS_SYS(sys_setfsuid , 1) | |
1687 | MIPS_SYS(sys_setfsgid , 1) | |
1688 | MIPS_SYS(sys_llseek , 5) /* 4140 */ | |
1689 | MIPS_SYS(sys_getdents , 3) | |
1690 | MIPS_SYS(sys_select , 5) | |
1691 | MIPS_SYS(sys_flock , 2) | |
1692 | MIPS_SYS(sys_msync , 3) | |
1693 | MIPS_SYS(sys_readv , 3) /* 4145 */ | |
1694 | MIPS_SYS(sys_writev , 3) | |
1695 | MIPS_SYS(sys_cacheflush , 3) | |
1696 | MIPS_SYS(sys_cachectl , 3) | |
1697 | MIPS_SYS(sys_sysmips , 4) | |
1698 | MIPS_SYS(sys_ni_syscall , 0) /* 4150 */ | |
1699 | MIPS_SYS(sys_getsid , 1) | |
1700 | MIPS_SYS(sys_fdatasync , 0) | |
1701 | MIPS_SYS(sys_sysctl , 1) | |
1702 | MIPS_SYS(sys_mlock , 2) | |
1703 | MIPS_SYS(sys_munlock , 2) /* 4155 */ | |
1704 | MIPS_SYS(sys_mlockall , 1) | |
1705 | MIPS_SYS(sys_munlockall , 0) | |
1706 | MIPS_SYS(sys_sched_setparam, 2) | |
1707 | MIPS_SYS(sys_sched_getparam, 2) | |
1708 | MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */ | |
1709 | MIPS_SYS(sys_sched_getscheduler, 1) | |
1710 | MIPS_SYS(sys_sched_yield , 0) | |
1711 | MIPS_SYS(sys_sched_get_priority_max, 1) | |
1712 | MIPS_SYS(sys_sched_get_priority_min, 1) | |
1713 | MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */ | |
1714 | MIPS_SYS(sys_nanosleep, 2) | |
1715 | MIPS_SYS(sys_mremap , 4) | |
1716 | MIPS_SYS(sys_accept , 3) | |
1717 | MIPS_SYS(sys_bind , 3) | |
1718 | MIPS_SYS(sys_connect , 3) /* 4170 */ | |
1719 | MIPS_SYS(sys_getpeername , 3) | |
1720 | MIPS_SYS(sys_getsockname , 3) | |
1721 | MIPS_SYS(sys_getsockopt , 5) | |
1722 | MIPS_SYS(sys_listen , 2) | |
1723 | MIPS_SYS(sys_recv , 4) /* 4175 */ | |
1724 | MIPS_SYS(sys_recvfrom , 6) | |
1725 | MIPS_SYS(sys_recvmsg , 3) | |
1726 | MIPS_SYS(sys_send , 4) | |
1727 | MIPS_SYS(sys_sendmsg , 3) | |
1728 | MIPS_SYS(sys_sendto , 6) /* 4180 */ | |
1729 | MIPS_SYS(sys_setsockopt , 5) | |
1730 | MIPS_SYS(sys_shutdown , 2) | |
1731 | MIPS_SYS(sys_socket , 3) | |
1732 | MIPS_SYS(sys_socketpair , 4) | |
1733 | MIPS_SYS(sys_setresuid , 3) /* 4185 */ | |
1734 | MIPS_SYS(sys_getresuid , 3) | |
1735 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */ | |
1736 | MIPS_SYS(sys_poll , 3) | |
1737 | MIPS_SYS(sys_nfsservctl , 3) | |
1738 | MIPS_SYS(sys_setresgid , 3) /* 4190 */ | |
1739 | MIPS_SYS(sys_getresgid , 3) | |
1740 | MIPS_SYS(sys_prctl , 5) | |
1741 | MIPS_SYS(sys_rt_sigreturn, 0) | |
1742 | MIPS_SYS(sys_rt_sigaction, 4) | |
1743 | MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */ | |
1744 | MIPS_SYS(sys_rt_sigpending, 2) | |
1745 | MIPS_SYS(sys_rt_sigtimedwait, 4) | |
1746 | MIPS_SYS(sys_rt_sigqueueinfo, 3) | |
1747 | MIPS_SYS(sys_rt_sigsuspend, 0) | |
1748 | MIPS_SYS(sys_pread64 , 6) /* 4200 */ | |
1749 | MIPS_SYS(sys_pwrite64 , 6) | |
1750 | MIPS_SYS(sys_chown , 3) | |
1751 | MIPS_SYS(sys_getcwd , 2) | |
1752 | MIPS_SYS(sys_capget , 2) | |
1753 | MIPS_SYS(sys_capset , 2) /* 4205 */ | |
1754 | MIPS_SYS(sys_sigaltstack , 0) | |
1755 | MIPS_SYS(sys_sendfile , 4) | |
1756 | MIPS_SYS(sys_ni_syscall , 0) | |
1757 | MIPS_SYS(sys_ni_syscall , 0) | |
1758 | MIPS_SYS(sys_mmap2 , 6) /* 4210 */ | |
1759 | MIPS_SYS(sys_truncate64 , 4) | |
1760 | MIPS_SYS(sys_ftruncate64 , 4) | |
1761 | MIPS_SYS(sys_stat64 , 2) | |
1762 | MIPS_SYS(sys_lstat64 , 2) | |
1763 | MIPS_SYS(sys_fstat64 , 2) /* 4215 */ | |
1764 | MIPS_SYS(sys_pivot_root , 2) | |
1765 | MIPS_SYS(sys_mincore , 3) | |
1766 | MIPS_SYS(sys_madvise , 3) | |
1767 | MIPS_SYS(sys_getdents64 , 3) | |
1768 | MIPS_SYS(sys_fcntl64 , 3) /* 4220 */ | |
1769 | MIPS_SYS(sys_ni_syscall , 0) | |
1770 | MIPS_SYS(sys_gettid , 0) | |
1771 | MIPS_SYS(sys_readahead , 5) | |
1772 | MIPS_SYS(sys_setxattr , 5) | |
1773 | MIPS_SYS(sys_lsetxattr , 5) /* 4225 */ | |
1774 | MIPS_SYS(sys_fsetxattr , 5) | |
1775 | MIPS_SYS(sys_getxattr , 4) | |
1776 | MIPS_SYS(sys_lgetxattr , 4) | |
1777 | MIPS_SYS(sys_fgetxattr , 4) | |
1778 | MIPS_SYS(sys_listxattr , 3) /* 4230 */ | |
1779 | MIPS_SYS(sys_llistxattr , 3) | |
1780 | MIPS_SYS(sys_flistxattr , 3) | |
1781 | MIPS_SYS(sys_removexattr , 2) | |
1782 | MIPS_SYS(sys_lremovexattr, 2) | |
1783 | MIPS_SYS(sys_fremovexattr, 2) /* 4235 */ | |
1784 | MIPS_SYS(sys_tkill , 2) | |
1785 | MIPS_SYS(sys_sendfile64 , 5) | |
1786 | MIPS_SYS(sys_futex , 2) | |
1787 | MIPS_SYS(sys_sched_setaffinity, 3) | |
1788 | MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */ | |
1789 | MIPS_SYS(sys_io_setup , 2) | |
1790 | MIPS_SYS(sys_io_destroy , 1) | |
1791 | MIPS_SYS(sys_io_getevents, 5) | |
1792 | MIPS_SYS(sys_io_submit , 3) | |
1793 | MIPS_SYS(sys_io_cancel , 3) /* 4245 */ | |
1794 | MIPS_SYS(sys_exit_group , 1) | |
1795 | MIPS_SYS(sys_lookup_dcookie, 3) | |
1796 | MIPS_SYS(sys_epoll_create, 1) | |
1797 | MIPS_SYS(sys_epoll_ctl , 4) | |
1798 | MIPS_SYS(sys_epoll_wait , 3) /* 4250 */ | |
1799 | MIPS_SYS(sys_remap_file_pages, 5) | |
1800 | MIPS_SYS(sys_set_tid_address, 1) | |
1801 | MIPS_SYS(sys_restart_syscall, 0) | |
1802 | MIPS_SYS(sys_fadvise64_64, 7) | |
1803 | MIPS_SYS(sys_statfs64 , 3) /* 4255 */ | |
1804 | MIPS_SYS(sys_fstatfs64 , 2) | |
1805 | MIPS_SYS(sys_timer_create, 3) | |
1806 | MIPS_SYS(sys_timer_settime, 4) | |
1807 | MIPS_SYS(sys_timer_gettime, 2) | |
1808 | MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */ | |
1809 | MIPS_SYS(sys_timer_delete, 1) | |
1810 | MIPS_SYS(sys_clock_settime, 2) | |
1811 | MIPS_SYS(sys_clock_gettime, 2) | |
1812 | MIPS_SYS(sys_clock_getres, 2) | |
1813 | MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */ | |
1814 | MIPS_SYS(sys_tgkill , 3) | |
1815 | MIPS_SYS(sys_utimes , 2) | |
1816 | MIPS_SYS(sys_mbind , 4) | |
1817 | MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */ | |
1818 | MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */ | |
1819 | MIPS_SYS(sys_mq_open , 4) | |
1820 | MIPS_SYS(sys_mq_unlink , 1) | |
1821 | MIPS_SYS(sys_mq_timedsend, 5) | |
1822 | MIPS_SYS(sys_mq_timedreceive, 5) | |
1823 | MIPS_SYS(sys_mq_notify , 2) /* 4275 */ | |
1824 | MIPS_SYS(sys_mq_getsetattr, 3) | |
1825 | MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */ | |
1826 | MIPS_SYS(sys_waitid , 4) | |
1827 | MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */ | |
1828 | MIPS_SYS(sys_add_key , 5) | |
388bb21a | 1829 | MIPS_SYS(sys_request_key, 4) |
048f6b4d | 1830 | MIPS_SYS(sys_keyctl , 5) |
6f5b89a0 | 1831 | MIPS_SYS(sys_set_thread_area, 1) |
388bb21a TS |
1832 | MIPS_SYS(sys_inotify_init, 0) |
1833 | MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */ | |
1834 | MIPS_SYS(sys_inotify_rm_watch, 2) | |
1835 | MIPS_SYS(sys_migrate_pages, 4) | |
1836 | MIPS_SYS(sys_openat, 4) | |
1837 | MIPS_SYS(sys_mkdirat, 3) | |
1838 | MIPS_SYS(sys_mknodat, 4) /* 4290 */ | |
1839 | MIPS_SYS(sys_fchownat, 5) | |
1840 | MIPS_SYS(sys_futimesat, 3) | |
1841 | MIPS_SYS(sys_fstatat64, 4) | |
1842 | MIPS_SYS(sys_unlinkat, 3) | |
1843 | MIPS_SYS(sys_renameat, 4) /* 4295 */ | |
1844 | MIPS_SYS(sys_linkat, 5) | |
1845 | MIPS_SYS(sys_symlinkat, 3) | |
1846 | MIPS_SYS(sys_readlinkat, 4) | |
1847 | MIPS_SYS(sys_fchmodat, 3) | |
1848 | MIPS_SYS(sys_faccessat, 3) /* 4300 */ | |
1849 | MIPS_SYS(sys_pselect6, 6) | |
1850 | MIPS_SYS(sys_ppoll, 5) | |
1851 | MIPS_SYS(sys_unshare, 1) | |
1852 | MIPS_SYS(sys_splice, 4) | |
1853 | MIPS_SYS(sys_sync_file_range, 7) /* 4305 */ | |
1854 | MIPS_SYS(sys_tee, 4) | |
1855 | MIPS_SYS(sys_vmsplice, 4) | |
1856 | MIPS_SYS(sys_move_pages, 6) | |
1857 | MIPS_SYS(sys_set_robust_list, 2) | |
1858 | MIPS_SYS(sys_get_robust_list, 3) /* 4310 */ | |
1859 | MIPS_SYS(sys_kexec_load, 4) | |
1860 | MIPS_SYS(sys_getcpu, 3) | |
1861 | MIPS_SYS(sys_epoll_pwait, 6) | |
1862 | MIPS_SYS(sys_ioprio_set, 3) | |
1863 | MIPS_SYS(sys_ioprio_get, 2) | |
048f6b4d FB |
1864 | }; |
1865 | ||
1866 | #undef MIPS_SYS | |
1867 | ||
590bc601 PB |
1868 | static int do_store_exclusive(CPUMIPSState *env) |
1869 | { | |
1870 | target_ulong addr; | |
1871 | target_ulong page_addr; | |
1872 | target_ulong val; | |
1873 | int flags; | |
1874 | int segv = 0; | |
1875 | int reg; | |
1876 | int d; | |
1877 | ||
1878 | addr = env->CP0_LLAddr; | |
1879 | page_addr = addr & TARGET_PAGE_MASK; | |
1880 | start_exclusive(); | |
1881 | mmap_lock(); | |
1882 | flags = page_get_flags(page_addr); | |
1883 | if ((flags & PAGE_READ) == 0) { | |
1884 | segv = 1; | |
1885 | } else { | |
1886 | reg = env->llreg & 0x1f; | |
1887 | d = (env->llreg & 0x20) != 0; | |
1888 | if (d) { | |
1889 | segv = get_user_s64(val, addr); | |
1890 | } else { | |
1891 | segv = get_user_s32(val, addr); | |
1892 | } | |
1893 | if (!segv) { | |
1894 | if (val != env->llval) { | |
1895 | env->active_tc.gpr[reg] = 0; | |
1896 | } else { | |
1897 | if (d) { | |
1898 | segv = put_user_u64(env->llnewval, addr); | |
1899 | } else { | |
1900 | segv = put_user_u32(env->llnewval, addr); | |
1901 | } | |
1902 | if (!segv) { | |
1903 | env->active_tc.gpr[reg] = 1; | |
1904 | } | |
1905 | } | |
1906 | } | |
1907 | } | |
1908 | env->CP0_LLAddr = -1; | |
1909 | if (!segv) { | |
1910 | env->active_tc.PC += 4; | |
1911 | } | |
1912 | mmap_unlock(); | |
1913 | end_exclusive(); | |
1914 | return segv; | |
1915 | } | |
1916 | ||
048f6b4d FB |
1917 | void cpu_loop(CPUMIPSState *env) |
1918 | { | |
1919 | target_siginfo_t info; | |
388bb21a | 1920 | int trapnr, ret; |
048f6b4d | 1921 | unsigned int syscall_num; |
048f6b4d FB |
1922 | |
1923 | for(;;) { | |
590bc601 | 1924 | cpu_exec_start(env); |
048f6b4d | 1925 | trapnr = cpu_mips_exec(env); |
590bc601 | 1926 | cpu_exec_end(env); |
048f6b4d FB |
1927 | switch(trapnr) { |
1928 | case EXCP_SYSCALL: | |
b5dc7732 TS |
1929 | syscall_num = env->active_tc.gpr[2] - 4000; |
1930 | env->active_tc.PC += 4; | |
388bb21a TS |
1931 | if (syscall_num >= sizeof(mips_syscall_args)) { |
1932 | ret = -ENOSYS; | |
1933 | } else { | |
1934 | int nb_args; | |
992f48a0 BS |
1935 | abi_ulong sp_reg; |
1936 | abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0; | |
388bb21a TS |
1937 | |
1938 | nb_args = mips_syscall_args[syscall_num]; | |
b5dc7732 | 1939 | sp_reg = env->active_tc.gpr[29]; |
388bb21a TS |
1940 | switch (nb_args) { |
1941 | /* these arguments are taken from the stack */ | |
2f619698 FB |
1942 | /* FIXME - what to do if get_user() fails? */ |
1943 | case 8: get_user_ual(arg8, sp_reg + 28); | |
1944 | case 7: get_user_ual(arg7, sp_reg + 24); | |
1945 | case 6: get_user_ual(arg6, sp_reg + 20); | |
1946 | case 5: get_user_ual(arg5, sp_reg + 16); | |
388bb21a TS |
1947 | default: |
1948 | break; | |
048f6b4d | 1949 | } |
b5dc7732 TS |
1950 | ret = do_syscall(env, env->active_tc.gpr[2], |
1951 | env->active_tc.gpr[4], | |
1952 | env->active_tc.gpr[5], | |
1953 | env->active_tc.gpr[6], | |
1954 | env->active_tc.gpr[7], | |
388bb21a TS |
1955 | arg5, arg6/*, arg7, arg8*/); |
1956 | } | |
0b1bcb00 PB |
1957 | if (ret == -TARGET_QEMU_ESIGRETURN) { |
1958 | /* Returning from a successful sigreturn syscall. | |
1959 | Avoid clobbering register state. */ | |
1960 | break; | |
1961 | } | |
388bb21a | 1962 | if ((unsigned int)ret >= (unsigned int)(-1133)) { |
b5dc7732 | 1963 | env->active_tc.gpr[7] = 1; /* error flag */ |
388bb21a TS |
1964 | ret = -ret; |
1965 | } else { | |
b5dc7732 | 1966 | env->active_tc.gpr[7] = 0; /* error flag */ |
048f6b4d | 1967 | } |
b5dc7732 | 1968 | env->active_tc.gpr[2] = ret; |
048f6b4d | 1969 | break; |
ca7c2b1b TS |
1970 | case EXCP_TLBL: |
1971 | case EXCP_TLBS: | |
e4474235 PB |
1972 | info.si_signo = TARGET_SIGSEGV; |
1973 | info.si_errno = 0; | |
1974 | /* XXX: check env->error_code */ | |
1975 | info.si_code = TARGET_SEGV_MAPERR; | |
1976 | info._sifields._sigfault._addr = env->CP0_BadVAddr; | |
1977 | queue_signal(env, info.si_signo, &info); | |
1978 | break; | |
6900e84b | 1979 | case EXCP_CpU: |
048f6b4d | 1980 | case EXCP_RI: |
bc1ad2de FB |
1981 | info.si_signo = TARGET_SIGILL; |
1982 | info.si_errno = 0; | |
1983 | info.si_code = 0; | |
624f7979 | 1984 | queue_signal(env, info.si_signo, &info); |
048f6b4d | 1985 | break; |
106ec879 FB |
1986 | case EXCP_INTERRUPT: |
1987 | /* just indicate that signals should be handled asap */ | |
1988 | break; | |
d08b2a28 PB |
1989 | case EXCP_DEBUG: |
1990 | { | |
1991 | int sig; | |
1992 | ||
1993 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
1994 | if (sig) | |
1995 | { | |
1996 | info.si_signo = sig; | |
1997 | info.si_errno = 0; | |
1998 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 1999 | queue_signal(env, info.si_signo, &info); |
d08b2a28 PB |
2000 | } |
2001 | } | |
2002 | break; | |
590bc601 PB |
2003 | case EXCP_SC: |
2004 | if (do_store_exclusive(env)) { | |
2005 | info.si_signo = TARGET_SIGSEGV; | |
2006 | info.si_errno = 0; | |
2007 | info.si_code = TARGET_SEGV_MAPERR; | |
2008 | info._sifields._sigfault._addr = env->active_tc.PC; | |
2009 | queue_signal(env, info.si_signo, &info); | |
2010 | } | |
2011 | break; | |
048f6b4d FB |
2012 | default: |
2013 | // error: | |
5fafdf24 | 2014 | fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", |
048f6b4d FB |
2015 | trapnr); |
2016 | cpu_dump_state(env, stderr, fprintf, 0); | |
2017 | abort(); | |
2018 | } | |
2019 | process_pending_signals(env); | |
2020 | } | |
2021 | } | |
2022 | #endif | |
2023 | ||
fdf9b3e8 FB |
2024 | #ifdef TARGET_SH4 |
2025 | void cpu_loop (CPUState *env) | |
2026 | { | |
2027 | int trapnr, ret; | |
355fb23d | 2028 | target_siginfo_t info; |
3b46e624 | 2029 | |
fdf9b3e8 FB |
2030 | while (1) { |
2031 | trapnr = cpu_sh4_exec (env); | |
3b46e624 | 2032 | |
fdf9b3e8 FB |
2033 | switch (trapnr) { |
2034 | case 0x160: | |
0b6d3ae0 | 2035 | env->pc += 2; |
5fafdf24 TS |
2036 | ret = do_syscall(env, |
2037 | env->gregs[3], | |
2038 | env->gregs[4], | |
2039 | env->gregs[5], | |
2040 | env->gregs[6], | |
2041 | env->gregs[7], | |
2042 | env->gregs[0], | |
fca743f3 | 2043 | env->gregs[1]); |
9c2a9ea1 | 2044 | env->gregs[0] = ret; |
fdf9b3e8 | 2045 | break; |
c3b5bc8a TS |
2046 | case EXCP_INTERRUPT: |
2047 | /* just indicate that signals should be handled asap */ | |
2048 | break; | |
355fb23d PB |
2049 | case EXCP_DEBUG: |
2050 | { | |
2051 | int sig; | |
2052 | ||
2053 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
2054 | if (sig) | |
2055 | { | |
2056 | info.si_signo = sig; | |
2057 | info.si_errno = 0; | |
2058 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 2059 | queue_signal(env, info.si_signo, &info); |
355fb23d PB |
2060 | } |
2061 | } | |
2062 | break; | |
c3b5bc8a TS |
2063 | case 0xa0: |
2064 | case 0xc0: | |
2065 | info.si_signo = SIGSEGV; | |
2066 | info.si_errno = 0; | |
2067 | info.si_code = TARGET_SEGV_MAPERR; | |
2068 | info._sifields._sigfault._addr = env->tea; | |
624f7979 | 2069 | queue_signal(env, info.si_signo, &info); |
c3b5bc8a TS |
2070 | break; |
2071 | ||
fdf9b3e8 FB |
2072 | default: |
2073 | printf ("Unhandled trap: 0x%x\n", trapnr); | |
2074 | cpu_dump_state(env, stderr, fprintf, 0); | |
2075 | exit (1); | |
2076 | } | |
2077 | process_pending_signals (env); | |
2078 | } | |
2079 | } | |
2080 | #endif | |
2081 | ||
48733d19 TS |
2082 | #ifdef TARGET_CRIS |
2083 | void cpu_loop (CPUState *env) | |
2084 | { | |
2085 | int trapnr, ret; | |
2086 | target_siginfo_t info; | |
2087 | ||
2088 | while (1) { | |
2089 | trapnr = cpu_cris_exec (env); | |
2090 | switch (trapnr) { | |
2091 | case 0xaa: | |
2092 | { | |
2093 | info.si_signo = SIGSEGV; | |
2094 | info.si_errno = 0; | |
2095 | /* XXX: check env->error_code */ | |
2096 | info.si_code = TARGET_SEGV_MAPERR; | |
e00c1e71 | 2097 | info._sifields._sigfault._addr = env->pregs[PR_EDA]; |
624f7979 | 2098 | queue_signal(env, info.si_signo, &info); |
48733d19 TS |
2099 | } |
2100 | break; | |
b6d3abda EI |
2101 | case EXCP_INTERRUPT: |
2102 | /* just indicate that signals should be handled asap */ | |
2103 | break; | |
48733d19 TS |
2104 | case EXCP_BREAK: |
2105 | ret = do_syscall(env, | |
2106 | env->regs[9], | |
2107 | env->regs[10], | |
2108 | env->regs[11], | |
2109 | env->regs[12], | |
2110 | env->regs[13], | |
2111 | env->pregs[7], | |
2112 | env->pregs[11]); | |
2113 | env->regs[10] = ret; | |
48733d19 TS |
2114 | break; |
2115 | case EXCP_DEBUG: | |
2116 | { | |
2117 | int sig; | |
2118 | ||
2119 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
2120 | if (sig) | |
2121 | { | |
2122 | info.si_signo = sig; | |
2123 | info.si_errno = 0; | |
2124 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 2125 | queue_signal(env, info.si_signo, &info); |
48733d19 TS |
2126 | } |
2127 | } | |
2128 | break; | |
2129 | default: | |
2130 | printf ("Unhandled trap: 0x%x\n", trapnr); | |
2131 | cpu_dump_state(env, stderr, fprintf, 0); | |
2132 | exit (1); | |
2133 | } | |
2134 | process_pending_signals (env); | |
2135 | } | |
2136 | } | |
2137 | #endif | |
2138 | ||
b779e29e EI |
2139 | #ifdef TARGET_MICROBLAZE |
2140 | void cpu_loop (CPUState *env) | |
2141 | { | |
2142 | int trapnr, ret; | |
2143 | target_siginfo_t info; | |
2144 | ||
2145 | while (1) { | |
2146 | trapnr = cpu_mb_exec (env); | |
2147 | switch (trapnr) { | |
2148 | case 0xaa: | |
2149 | { | |
2150 | info.si_signo = SIGSEGV; | |
2151 | info.si_errno = 0; | |
2152 | /* XXX: check env->error_code */ | |
2153 | info.si_code = TARGET_SEGV_MAPERR; | |
2154 | info._sifields._sigfault._addr = 0; | |
2155 | queue_signal(env, info.si_signo, &info); | |
2156 | } | |
2157 | break; | |
2158 | case EXCP_INTERRUPT: | |
2159 | /* just indicate that signals should be handled asap */ | |
2160 | break; | |
2161 | case EXCP_BREAK: | |
2162 | /* Return address is 4 bytes after the call. */ | |
2163 | env->regs[14] += 4; | |
2164 | ret = do_syscall(env, | |
2165 | env->regs[12], | |
2166 | env->regs[5], | |
2167 | env->regs[6], | |
2168 | env->regs[7], | |
2169 | env->regs[8], | |
2170 | env->regs[9], | |
2171 | env->regs[10]); | |
2172 | env->regs[3] = ret; | |
2173 | env->sregs[SR_PC] = env->regs[14]; | |
2174 | break; | |
2175 | case EXCP_DEBUG: | |
2176 | { | |
2177 | int sig; | |
2178 | ||
2179 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
2180 | if (sig) | |
2181 | { | |
2182 | info.si_signo = sig; | |
2183 | info.si_errno = 0; | |
2184 | info.si_code = TARGET_TRAP_BRKPT; | |
2185 | queue_signal(env, info.si_signo, &info); | |
2186 | } | |
2187 | } | |
2188 | break; | |
2189 | default: | |
2190 | printf ("Unhandled trap: 0x%x\n", trapnr); | |
2191 | cpu_dump_state(env, stderr, fprintf, 0); | |
2192 | exit (1); | |
2193 | } | |
2194 | process_pending_signals (env); | |
2195 | } | |
2196 | } | |
2197 | #endif | |
2198 | ||
e6e5906b PB |
2199 | #ifdef TARGET_M68K |
2200 | ||
2201 | void cpu_loop(CPUM68KState *env) | |
2202 | { | |
2203 | int trapnr; | |
2204 | unsigned int n; | |
2205 | target_siginfo_t info; | |
2206 | TaskState *ts = env->opaque; | |
3b46e624 | 2207 | |
e6e5906b PB |
2208 | for(;;) { |
2209 | trapnr = cpu_m68k_exec(env); | |
2210 | switch(trapnr) { | |
2211 | case EXCP_ILLEGAL: | |
2212 | { | |
2213 | if (ts->sim_syscalls) { | |
2214 | uint16_t nr; | |
2215 | nr = lduw(env->pc + 2); | |
2216 | env->pc += 4; | |
2217 | do_m68k_simcall(env, nr); | |
2218 | } else { | |
2219 | goto do_sigill; | |
2220 | } | |
2221 | } | |
2222 | break; | |
a87295e8 | 2223 | case EXCP_HALT_INSN: |
e6e5906b | 2224 | /* Semihosing syscall. */ |
a87295e8 | 2225 | env->pc += 4; |
e6e5906b PB |
2226 | do_m68k_semihosting(env, env->dregs[0]); |
2227 | break; | |
2228 | case EXCP_LINEA: | |
2229 | case EXCP_LINEF: | |
2230 | case EXCP_UNSUPPORTED: | |
2231 | do_sigill: | |
2232 | info.si_signo = SIGILL; | |
2233 | info.si_errno = 0; | |
2234 | info.si_code = TARGET_ILL_ILLOPN; | |
2235 | info._sifields._sigfault._addr = env->pc; | |
624f7979 | 2236 | queue_signal(env, info.si_signo, &info); |
e6e5906b PB |
2237 | break; |
2238 | case EXCP_TRAP0: | |
2239 | { | |
2240 | ts->sim_syscalls = 0; | |
2241 | n = env->dregs[0]; | |
2242 | env->pc += 2; | |
5fafdf24 TS |
2243 | env->dregs[0] = do_syscall(env, |
2244 | n, | |
e6e5906b PB |
2245 | env->dregs[1], |
2246 | env->dregs[2], | |
2247 | env->dregs[3], | |
2248 | env->dregs[4], | |
2249 | env->dregs[5], | |
bb7ec043 | 2250 | env->aregs[0]); |
e6e5906b PB |
2251 | } |
2252 | break; | |
2253 | case EXCP_INTERRUPT: | |
2254 | /* just indicate that signals should be handled asap */ | |
2255 | break; | |
2256 | case EXCP_ACCESS: | |
2257 | { | |
2258 | info.si_signo = SIGSEGV; | |
2259 | info.si_errno = 0; | |
2260 | /* XXX: check env->error_code */ | |
2261 | info.si_code = TARGET_SEGV_MAPERR; | |
2262 | info._sifields._sigfault._addr = env->mmu.ar; | |
624f7979 | 2263 | queue_signal(env, info.si_signo, &info); |
e6e5906b PB |
2264 | } |
2265 | break; | |
2266 | case EXCP_DEBUG: | |
2267 | { | |
2268 | int sig; | |
2269 | ||
2270 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
2271 | if (sig) | |
2272 | { | |
2273 | info.si_signo = sig; | |
2274 | info.si_errno = 0; | |
2275 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 2276 | queue_signal(env, info.si_signo, &info); |
e6e5906b PB |
2277 | } |
2278 | } | |
2279 | break; | |
2280 | default: | |
5fafdf24 | 2281 | fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", |
e6e5906b PB |
2282 | trapnr); |
2283 | cpu_dump_state(env, stderr, fprintf, 0); | |
2284 | abort(); | |
2285 | } | |
2286 | process_pending_signals(env); | |
2287 | } | |
2288 | } | |
2289 | #endif /* TARGET_M68K */ | |
2290 | ||
7a3148a9 JM |
2291 | #ifdef TARGET_ALPHA |
2292 | void cpu_loop (CPUState *env) | |
2293 | { | |
e96efcfc | 2294 | int trapnr; |
7a3148a9 | 2295 | target_siginfo_t info; |
3b46e624 | 2296 | |
7a3148a9 JM |
2297 | while (1) { |
2298 | trapnr = cpu_alpha_exec (env); | |
3b46e624 | 2299 | |
7a3148a9 JM |
2300 | switch (trapnr) { |
2301 | case EXCP_RESET: | |
2302 | fprintf(stderr, "Reset requested. Exit\n"); | |
2303 | exit(1); | |
2304 | break; | |
2305 | case EXCP_MCHK: | |
2306 | fprintf(stderr, "Machine check exception. Exit\n"); | |
2307 | exit(1); | |
2308 | break; | |
2309 | case EXCP_ARITH: | |
2310 | fprintf(stderr, "Arithmetic trap.\n"); | |
2311 | exit(1); | |
2312 | break; | |
2313 | case EXCP_HW_INTERRUPT: | |
5fafdf24 | 2314 | fprintf(stderr, "External interrupt. Exit\n"); |
7a3148a9 JM |
2315 | exit(1); |
2316 | break; | |
2317 | case EXCP_DFAULT: | |
2318 | fprintf(stderr, "MMU data fault\n"); | |
2319 | exit(1); | |
2320 | break; | |
2321 | case EXCP_DTB_MISS_PAL: | |
2322 | fprintf(stderr, "MMU data TLB miss in PALcode\n"); | |
2323 | exit(1); | |
2324 | break; | |
2325 | case EXCP_ITB_MISS: | |
2326 | fprintf(stderr, "MMU instruction TLB miss\n"); | |
2327 | exit(1); | |
2328 | break; | |
2329 | case EXCP_ITB_ACV: | |
2330 | fprintf(stderr, "MMU instruction access violation\n"); | |
2331 | exit(1); | |
2332 | break; | |
2333 | case EXCP_DTB_MISS_NATIVE: | |
2334 | fprintf(stderr, "MMU data TLB miss\n"); | |
2335 | exit(1); | |
2336 | break; | |
2337 | case EXCP_UNALIGN: | |
2338 | fprintf(stderr, "Unaligned access\n"); | |
2339 | exit(1); | |
2340 | break; | |
2341 | case EXCP_OPCDEC: | |
2342 | fprintf(stderr, "Invalid instruction\n"); | |
2343 | exit(1); | |
2344 | break; | |
2345 | case EXCP_FEN: | |
2346 | fprintf(stderr, "Floating-point not allowed\n"); | |
2347 | exit(1); | |
2348 | break; | |
2349 | case EXCP_CALL_PAL ... (EXCP_CALL_PALP - 1): | |
7a3148a9 JM |
2350 | call_pal(env, (trapnr >> 6) | 0x80); |
2351 | break; | |
2352 | case EXCP_CALL_PALP ... (EXCP_CALL_PALE - 1): | |
7f75ffd3 | 2353 | fprintf(stderr, "Privileged call to PALcode\n"); |
7a3148a9 JM |
2354 | exit(1); |
2355 | break; | |
2356 | case EXCP_DEBUG: | |
2357 | { | |
2358 | int sig; | |
2359 | ||
2360 | sig = gdb_handlesig (env, TARGET_SIGTRAP); | |
2361 | if (sig) | |
2362 | { | |
2363 | info.si_signo = sig; | |
2364 | info.si_errno = 0; | |
2365 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 2366 | queue_signal(env, info.si_signo, &info); |
7a3148a9 JM |
2367 | } |
2368 | } | |
2369 | break; | |
2370 | default: | |
2371 | printf ("Unhandled trap: 0x%x\n", trapnr); | |
2372 | cpu_dump_state(env, stderr, fprintf, 0); | |
2373 | exit (1); | |
2374 | } | |
2375 | process_pending_signals (env); | |
2376 | } | |
2377 | } | |
2378 | #endif /* TARGET_ALPHA */ | |
2379 | ||
8fcd3692 | 2380 | static void usage(void) |
31e31b8a | 2381 | { |
4a19f1ec | 2382 | printf("qemu-" TARGET_ARCH " version " QEMU_VERSION QEMU_PKGVERSION ", Copyright (c) 2003-2008 Fabrice Bellard\n" |
68d0f70e | 2383 | "usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n" |
b346ff46 | 2384 | "Linux CPU emulator (compiled for %s emulation)\n" |
d691f669 | 2385 | "\n" |
68d0f70e | 2386 | "Standard options:\n" |
b12b6a18 TS |
2387 | "-h print this help\n" |
2388 | "-g port wait gdb connection to port\n" | |
2389 | "-L path set the elf interpreter prefix (default=%s)\n" | |
2390 | "-s size set the stack size in bytes (default=%ld)\n" | |
2391 | "-cpu model select CPU (-cpu ? for list)\n" | |
2392 | "-drop-ld-preload drop LD_PRELOAD for target process\n" | |
04a6dfeb AJ |
2393 | "-E var=value sets/modifies targets environment variable(s)\n" |
2394 | "-U var unsets targets environment variable(s)\n" | |
7d8cec95 | 2395 | "-0 argv0 forces target process argv[0] to be argv0\n" |
379f6698 PB |
2396 | #if defined(CONFIG_USE_GUEST_BASE) |
2397 | "-B address set guest_base address to address\n" | |
2398 | #endif | |
54936004 | 2399 | "\n" |
68d0f70e | 2400 | "Debug options:\n" |
6f1f31c0 | 2401 | "-d options activate log (logfile=%s)\n" |
b6741956 | 2402 | "-p pagesize set the host page size to 'pagesize'\n" |
1b530a6d | 2403 | "-singlestep always run in singlestep mode\n" |
b01bcae6 AZ |
2404 | "-strace log system calls\n" |
2405 | "\n" | |
68d0f70e | 2406 | "Environment variables:\n" |
b01bcae6 AZ |
2407 | "QEMU_STRACE Print system calls and arguments similar to the\n" |
2408 | " 'strace' program. Enable by setting to any value.\n" | |
04a6dfeb AJ |
2409 | "You can use -E and -U options to set/unset environment variables\n" |
2410 | "for target process. It is possible to provide several variables\n" | |
2411 | "by repeating the option. For example:\n" | |
2412 | " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n" | |
2413 | "Note that if you provide several changes to single variable\n" | |
2414 | "last change will stay in effect.\n" | |
b01bcae6 | 2415 | , |
b346ff46 | 2416 | TARGET_ARCH, |
5fafdf24 | 2417 | interp_prefix, |
54936004 FB |
2418 | x86_stack_size, |
2419 | DEBUG_LOGFILE); | |
2d18e637 | 2420 | exit(1); |
31e31b8a FB |
2421 | } |
2422 | ||
d5975363 | 2423 | THREAD CPUState *thread_env; |
59faf6d6 | 2424 | |
edf8e2af MW |
2425 | void task_settid(TaskState *ts) |
2426 | { | |
2427 | if (ts->ts_tid == 0) { | |
2f7bb878 | 2428 | #ifdef CONFIG_USE_NPTL |
edf8e2af MW |
2429 | ts->ts_tid = (pid_t)syscall(SYS_gettid); |
2430 | #else | |
2431 | /* when no threads are used, tid becomes pid */ | |
2432 | ts->ts_tid = getpid(); | |
2433 | #endif | |
2434 | } | |
2435 | } | |
2436 | ||
2437 | void stop_all_tasks(void) | |
2438 | { | |
2439 | /* | |
2440 | * We trust that when using NPTL, start_exclusive() | |
2441 | * handles thread stopping correctly. | |
2442 | */ | |
2443 | start_exclusive(); | |
2444 | } | |
2445 | ||
c3a92833 | 2446 | /* Assumes contents are already zeroed. */ |
624f7979 PB |
2447 | void init_task_state(TaskState *ts) |
2448 | { | |
2449 | int i; | |
2450 | ||
624f7979 PB |
2451 | ts->used = 1; |
2452 | ts->first_free = ts->sigqueue_table; | |
2453 | for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) { | |
2454 | ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1]; | |
2455 | } | |
2456 | ts->sigqueue_table[i].next = NULL; | |
2457 | } | |
2458 | ||
902b3d5c | 2459 | int main(int argc, char **argv, char **envp) |
31e31b8a FB |
2460 | { |
2461 | const char *filename; | |
b1f9be31 | 2462 | const char *cpu_model; |
01ffc75b | 2463 | struct target_pt_regs regs1, *regs = ®s1; |
31e31b8a | 2464 | struct image_info info1, *info = &info1; |
edf8e2af | 2465 | struct linux_binprm bprm; |
851e67a1 | 2466 | TaskState ts1, *ts = &ts1; |
b346ff46 | 2467 | CPUState *env; |
586314f2 | 2468 | int optind; |
d691f669 | 2469 | const char *r; |
74c33bed | 2470 | int gdbstub_port = 0; |
04a6dfeb | 2471 | char **target_environ, **wrk; |
7d8cec95 AJ |
2472 | char **target_argv; |
2473 | int target_argc; | |
04a6dfeb | 2474 | envlist_t *envlist = NULL; |
7d8cec95 AJ |
2475 | const char *argv0 = NULL; |
2476 | int i; | |
fd4d81dd | 2477 | int ret; |
b12b6a18 | 2478 | |
31e31b8a | 2479 | if (argc <= 1) |
44de1b33 | 2480 | usage(); |
f801f97e | 2481 | |
902b3d5c | 2482 | qemu_cache_utils_init(envp); |
2483 | ||
cc38b844 FB |
2484 | /* init debug */ |
2485 | cpu_set_log_filename(DEBUG_LOGFILE); | |
2486 | ||
04a6dfeb AJ |
2487 | if ((envlist = envlist_create()) == NULL) { |
2488 | (void) fprintf(stderr, "Unable to allocate envlist\n"); | |
2489 | exit(1); | |
2490 | } | |
2491 | ||
2492 | /* add current environment into the list */ | |
2493 | for (wrk = environ; *wrk != NULL; wrk++) { | |
2494 | (void) envlist_setenv(envlist, *wrk); | |
2495 | } | |
2496 | ||
b1f9be31 | 2497 | cpu_model = NULL; |
586314f2 | 2498 | optind = 1; |
d691f669 FB |
2499 | for(;;) { |
2500 | if (optind >= argc) | |
2501 | break; | |
2502 | r = argv[optind]; | |
2503 | if (r[0] != '-') | |
2504 | break; | |
586314f2 | 2505 | optind++; |
d691f669 FB |
2506 | r++; |
2507 | if (!strcmp(r, "-")) { | |
2508 | break; | |
2509 | } else if (!strcmp(r, "d")) { | |
e19e89a5 | 2510 | int mask; |
c7cd6a37 | 2511 | const CPULogItem *item; |
6f1f31c0 FB |
2512 | |
2513 | if (optind >= argc) | |
2514 | break; | |
3b46e624 | 2515 | |
6f1f31c0 FB |
2516 | r = argv[optind++]; |
2517 | mask = cpu_str_to_log_mask(r); | |
e19e89a5 FB |
2518 | if (!mask) { |
2519 | printf("Log items (comma separated):\n"); | |
2520 | for(item = cpu_log_items; item->mask != 0; item++) { | |
2521 | printf("%-10s %s\n", item->name, item->help); | |
2522 | } | |
2523 | exit(1); | |
2524 | } | |
2525 | cpu_set_log(mask); | |
04a6dfeb AJ |
2526 | } else if (!strcmp(r, "E")) { |
2527 | r = argv[optind++]; | |
2528 | if (envlist_setenv(envlist, r) != 0) | |
2529 | usage(); | |
2530 | } else if (!strcmp(r, "U")) { | |
2531 | r = argv[optind++]; | |
2532 | if (envlist_unsetenv(envlist, r) != 0) | |
2533 | usage(); | |
7d8cec95 AJ |
2534 | } else if (!strcmp(r, "0")) { |
2535 | r = argv[optind++]; | |
2536 | argv0 = r; | |
d691f669 | 2537 | } else if (!strcmp(r, "s")) { |
491150db AJ |
2538 | if (optind >= argc) |
2539 | break; | |
d691f669 FB |
2540 | r = argv[optind++]; |
2541 | x86_stack_size = strtol(r, (char **)&r, 0); | |
2542 | if (x86_stack_size <= 0) | |
44de1b33 | 2543 | usage(); |
d691f669 FB |
2544 | if (*r == 'M') |
2545 | x86_stack_size *= 1024 * 1024; | |
2546 | else if (*r == 'k' || *r == 'K') | |
2547 | x86_stack_size *= 1024; | |
2548 | } else if (!strcmp(r, "L")) { | |
2549 | interp_prefix = argv[optind++]; | |
54936004 | 2550 | } else if (!strcmp(r, "p")) { |
491150db AJ |
2551 | if (optind >= argc) |
2552 | break; | |
83fb7adf FB |
2553 | qemu_host_page_size = atoi(argv[optind++]); |
2554 | if (qemu_host_page_size == 0 || | |
2555 | (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) { | |
54936004 FB |
2556 | fprintf(stderr, "page size must be a power of two\n"); |
2557 | exit(1); | |
2558 | } | |
1fddef4b | 2559 | } else if (!strcmp(r, "g")) { |
491150db AJ |
2560 | if (optind >= argc) |
2561 | break; | |
74c33bed | 2562 | gdbstub_port = atoi(argv[optind++]); |
c5937220 PB |
2563 | } else if (!strcmp(r, "r")) { |
2564 | qemu_uname_release = argv[optind++]; | |
b1f9be31 JM |
2565 | } else if (!strcmp(r, "cpu")) { |
2566 | cpu_model = argv[optind++]; | |
491150db | 2567 | if (cpu_model == NULL || strcmp(cpu_model, "?") == 0) { |
c732abe2 JM |
2568 | /* XXX: implement xxx_cpu_list for targets that still miss it */ |
2569 | #if defined(cpu_list) | |
2570 | cpu_list(stdout, &fprintf); | |
b1f9be31 | 2571 | #endif |
2d18e637 | 2572 | exit(1); |
b1f9be31 | 2573 | } |
379f6698 PB |
2574 | #if defined(CONFIG_USE_GUEST_BASE) |
2575 | } else if (!strcmp(r, "B")) { | |
2576 | guest_base = strtol(argv[optind++], NULL, 0); | |
2577 | have_guest_base = 1; | |
2578 | #endif | |
b12b6a18 | 2579 | } else if (!strcmp(r, "drop-ld-preload")) { |
04a6dfeb | 2580 | (void) envlist_unsetenv(envlist, "LD_PRELOAD"); |
1b530a6d AJ |
2581 | } else if (!strcmp(r, "singlestep")) { |
2582 | singlestep = 1; | |
b6741956 FB |
2583 | } else if (!strcmp(r, "strace")) { |
2584 | do_strace = 1; | |
5fafdf24 | 2585 | } else |
c6981055 | 2586 | { |
d691f669 FB |
2587 | usage(); |
2588 | } | |
586314f2 | 2589 | } |
d691f669 FB |
2590 | if (optind >= argc) |
2591 | usage(); | |
586314f2 | 2592 | filename = argv[optind]; |
d088d664 | 2593 | exec_path = argv[optind]; |
586314f2 | 2594 | |
31e31b8a | 2595 | /* Zero out regs */ |
01ffc75b | 2596 | memset(regs, 0, sizeof(struct target_pt_regs)); |
31e31b8a FB |
2597 | |
2598 | /* Zero out image_info */ | |
2599 | memset(info, 0, sizeof(struct image_info)); | |
2600 | ||
edf8e2af MW |
2601 | memset(&bprm, 0, sizeof (bprm)); |
2602 | ||
74cd30b8 FB |
2603 | /* Scan interp_prefix dir for replacement files. */ |
2604 | init_paths(interp_prefix); | |
2605 | ||
46027c07 | 2606 | if (cpu_model == NULL) { |
aaed909a | 2607 | #if defined(TARGET_I386) |
46027c07 FB |
2608 | #ifdef TARGET_X86_64 |
2609 | cpu_model = "qemu64"; | |
2610 | #else | |
2611 | cpu_model = "qemu32"; | |
2612 | #endif | |
aaed909a | 2613 | #elif defined(TARGET_ARM) |
088ab16c | 2614 | cpu_model = "any"; |
aaed909a FB |
2615 | #elif defined(TARGET_M68K) |
2616 | cpu_model = "any"; | |
2617 | #elif defined(TARGET_SPARC) | |
2618 | #ifdef TARGET_SPARC64 | |
2619 | cpu_model = "TI UltraSparc II"; | |
2620 | #else | |
2621 | cpu_model = "Fujitsu MB86904"; | |
46027c07 | 2622 | #endif |
aaed909a FB |
2623 | #elif defined(TARGET_MIPS) |
2624 | #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) | |
2625 | cpu_model = "20Kc"; | |
2626 | #else | |
2627 | cpu_model = "24Kf"; | |
2628 | #endif | |
2629 | #elif defined(TARGET_PPC) | |
7ded4f52 FB |
2630 | #ifdef TARGET_PPC64 |
2631 | cpu_model = "970"; | |
2632 | #else | |
aaed909a | 2633 | cpu_model = "750"; |
7ded4f52 | 2634 | #endif |
aaed909a FB |
2635 | #else |
2636 | cpu_model = "any"; | |
2637 | #endif | |
2638 | } | |
26a5f13b | 2639 | cpu_exec_init_all(0); |
83fb7adf FB |
2640 | /* NOTE: we need to init the CPU at this stage to get |
2641 | qemu_host_page_size */ | |
aaed909a FB |
2642 | env = cpu_init(cpu_model); |
2643 | if (!env) { | |
2644 | fprintf(stderr, "Unable to find CPU definition\n"); | |
2645 | exit(1); | |
2646 | } | |
d5975363 | 2647 | thread_env = env; |
3b46e624 | 2648 | |
b6741956 FB |
2649 | if (getenv("QEMU_STRACE")) { |
2650 | do_strace = 1; | |
b92c47c1 TS |
2651 | } |
2652 | ||
04a6dfeb AJ |
2653 | target_environ = envlist_to_environ(envlist, NULL); |
2654 | envlist_free(envlist); | |
b12b6a18 | 2655 | |
379f6698 PB |
2656 | #if defined(CONFIG_USE_GUEST_BASE) |
2657 | /* | |
2658 | * Now that page sizes are configured in cpu_init() we can do | |
2659 | * proper page alignment for guest_base. | |
2660 | */ | |
2661 | guest_base = HOST_PAGE_ALIGN(guest_base); | |
2662 | ||
2663 | /* | |
2664 | * Read in mmap_min_addr kernel parameter. This value is used | |
2665 | * When loading the ELF image to determine whether guest_base | |
2666 | * is needed. | |
2667 | * | |
2668 | * When user has explicitly set the quest base, we skip this | |
2669 | * test. | |
2670 | */ | |
2671 | if (!have_guest_base) { | |
2672 | FILE *fp; | |
2673 | ||
2674 | if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) { | |
2675 | unsigned long tmp; | |
2676 | if (fscanf(fp, "%lu", &tmp) == 1) { | |
2677 | mmap_min_addr = tmp; | |
2678 | qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr); | |
2679 | } | |
2680 | fclose(fp); | |
2681 | } | |
2682 | } | |
2683 | #endif /* CONFIG_USE_GUEST_BASE */ | |
2684 | ||
7d8cec95 AJ |
2685 | /* |
2686 | * Prepare copy of argv vector for target. | |
2687 | */ | |
2688 | target_argc = argc - optind; | |
2689 | target_argv = calloc(target_argc + 1, sizeof (char *)); | |
2690 | if (target_argv == NULL) { | |
2691 | (void) fprintf(stderr, "Unable to allocate memory for target_argv\n"); | |
2692 | exit(1); | |
2693 | } | |
2694 | ||
2695 | /* | |
2696 | * If argv0 is specified (using '-0' switch) we replace | |
2697 | * argv[0] pointer with the given one. | |
2698 | */ | |
2699 | i = 0; | |
2700 | if (argv0 != NULL) { | |
2701 | target_argv[i++] = strdup(argv0); | |
2702 | } | |
2703 | for (; i < target_argc; i++) { | |
2704 | target_argv[i] = strdup(argv[optind + i]); | |
2705 | } | |
2706 | target_argv[target_argc] = NULL; | |
2707 | ||
edf8e2af MW |
2708 | memset(ts, 0, sizeof(TaskState)); |
2709 | init_task_state(ts); | |
2710 | /* build Task State */ | |
2711 | ts->info = info; | |
2712 | ts->bprm = &bprm; | |
2713 | env->opaque = ts; | |
2714 | task_settid(ts); | |
2715 | ||
fd4d81dd AP |
2716 | ret = loader_exec(filename, target_argv, target_environ, regs, |
2717 | info, &bprm); | |
2718 | if (ret != 0) { | |
2719 | printf("Error %d while loading %s\n", ret, filename); | |
b12b6a18 TS |
2720 | _exit(1); |
2721 | } | |
2722 | ||
7d8cec95 AJ |
2723 | for (i = 0; i < target_argc; i++) { |
2724 | free(target_argv[i]); | |
2725 | } | |
2726 | free(target_argv); | |
2727 | ||
b12b6a18 TS |
2728 | for (wrk = target_environ; *wrk; wrk++) { |
2729 | free(*wrk); | |
31e31b8a | 2730 | } |
3b46e624 | 2731 | |
b12b6a18 TS |
2732 | free(target_environ); |
2733 | ||
2e77eac6 | 2734 | if (qemu_log_enabled()) { |
379f6698 PB |
2735 | #if defined(CONFIG_USE_GUEST_BASE) |
2736 | qemu_log("guest_base 0x%lx\n", guest_base); | |
2737 | #endif | |
2e77eac6 BS |
2738 | log_page_dump(); |
2739 | ||
2740 | qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk); | |
2741 | qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code); | |
2742 | qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n", | |
2743 | info->start_code); | |
2744 | qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n", | |
2745 | info->start_data); | |
2746 | qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data); | |
2747 | qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n", | |
2748 | info->start_stack); | |
2749 | qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk); | |
2750 | qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry); | |
2751 | } | |
31e31b8a | 2752 | |
53a5960a | 2753 | target_set_brk(info->brk); |
31e31b8a | 2754 | syscall_init(); |
66fb9763 | 2755 | signal_init(); |
31e31b8a | 2756 | |
b346ff46 | 2757 | #if defined(TARGET_I386) |
2e255c6b FB |
2758 | cpu_x86_set_cpl(env, 3); |
2759 | ||
3802ce26 | 2760 | env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; |
1bde465e FB |
2761 | env->hflags |= HF_PE_MASK; |
2762 | if (env->cpuid_features & CPUID_SSE) { | |
2763 | env->cr[4] |= CR4_OSFXSR_MASK; | |
2764 | env->hflags |= HF_OSFXSR_MASK; | |
2765 | } | |
d2fd1af7 | 2766 | #ifndef TARGET_ABI32 |
4dbc422b FB |
2767 | /* enable 64 bit mode if possible */ |
2768 | if (!(env->cpuid_ext2_features & CPUID_EXT2_LM)) { | |
2769 | fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n"); | |
2770 | exit(1); | |
2771 | } | |
d2fd1af7 | 2772 | env->cr[4] |= CR4_PAE_MASK; |
4dbc422b | 2773 | env->efer |= MSR_EFER_LMA | MSR_EFER_LME; |
d2fd1af7 FB |
2774 | env->hflags |= HF_LMA_MASK; |
2775 | #endif | |
1bde465e | 2776 | |
415e561f FB |
2777 | /* flags setup : we activate the IRQs by default as in user mode */ |
2778 | env->eflags |= IF_MASK; | |
3b46e624 | 2779 | |
6dbad63e | 2780 | /* linux register setup */ |
d2fd1af7 | 2781 | #ifndef TARGET_ABI32 |
84409ddb JM |
2782 | env->regs[R_EAX] = regs->rax; |
2783 | env->regs[R_EBX] = regs->rbx; | |
2784 | env->regs[R_ECX] = regs->rcx; | |
2785 | env->regs[R_EDX] = regs->rdx; | |
2786 | env->regs[R_ESI] = regs->rsi; | |
2787 | env->regs[R_EDI] = regs->rdi; | |
2788 | env->regs[R_EBP] = regs->rbp; | |
2789 | env->regs[R_ESP] = regs->rsp; | |
2790 | env->eip = regs->rip; | |
2791 | #else | |
0ecfa993 FB |
2792 | env->regs[R_EAX] = regs->eax; |
2793 | env->regs[R_EBX] = regs->ebx; | |
2794 | env->regs[R_ECX] = regs->ecx; | |
2795 | env->regs[R_EDX] = regs->edx; | |
2796 | env->regs[R_ESI] = regs->esi; | |
2797 | env->regs[R_EDI] = regs->edi; | |
2798 | env->regs[R_EBP] = regs->ebp; | |
2799 | env->regs[R_ESP] = regs->esp; | |
dab2ed99 | 2800 | env->eip = regs->eip; |
84409ddb | 2801 | #endif |
31e31b8a | 2802 | |
f4beb510 | 2803 | /* linux interrupt setup */ |
e441570f AZ |
2804 | #ifndef TARGET_ABI32 |
2805 | env->idt.limit = 511; | |
2806 | #else | |
2807 | env->idt.limit = 255; | |
2808 | #endif | |
2809 | env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1), | |
2810 | PROT_READ|PROT_WRITE, | |
2811 | MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); | |
2812 | idt_table = g2h(env->idt.base); | |
f4beb510 FB |
2813 | set_idt(0, 0); |
2814 | set_idt(1, 0); | |
2815 | set_idt(2, 0); | |
2816 | set_idt(3, 3); | |
2817 | set_idt(4, 3); | |
ec95da6c | 2818 | set_idt(5, 0); |
f4beb510 FB |
2819 | set_idt(6, 0); |
2820 | set_idt(7, 0); | |
2821 | set_idt(8, 0); | |
2822 | set_idt(9, 0); | |
2823 | set_idt(10, 0); | |
2824 | set_idt(11, 0); | |
2825 | set_idt(12, 0); | |
2826 | set_idt(13, 0); | |
2827 | set_idt(14, 0); | |
2828 | set_idt(15, 0); | |
2829 | set_idt(16, 0); | |
2830 | set_idt(17, 0); | |
2831 | set_idt(18, 0); | |
2832 | set_idt(19, 0); | |
2833 | set_idt(0x80, 3); | |
2834 | ||
6dbad63e | 2835 | /* linux segment setup */ |
8d18e893 FB |
2836 | { |
2837 | uint64_t *gdt_table; | |
e441570f AZ |
2838 | env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES, |
2839 | PROT_READ|PROT_WRITE, | |
2840 | MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); | |
8d18e893 | 2841 | env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; |
e441570f | 2842 | gdt_table = g2h(env->gdt.base); |
d2fd1af7 | 2843 | #ifdef TARGET_ABI32 |
8d18e893 FB |
2844 | write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, |
2845 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | | |
2846 | (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); | |
d2fd1af7 FB |
2847 | #else |
2848 | /* 64 bit code segment */ | |
2849 | write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, | |
2850 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | | |
2851 | DESC_L_MASK | | |
2852 | (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); | |
2853 | #endif | |
8d18e893 FB |
2854 | write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff, |
2855 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | | |
2856 | (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT)); | |
2857 | } | |
6dbad63e | 2858 | cpu_x86_load_seg(env, R_CS, __USER_CS); |
d2fd1af7 FB |
2859 | cpu_x86_load_seg(env, R_SS, __USER_DS); |
2860 | #ifdef TARGET_ABI32 | |
6dbad63e FB |
2861 | cpu_x86_load_seg(env, R_DS, __USER_DS); |
2862 | cpu_x86_load_seg(env, R_ES, __USER_DS); | |
6dbad63e FB |
2863 | cpu_x86_load_seg(env, R_FS, __USER_DS); |
2864 | cpu_x86_load_seg(env, R_GS, __USER_DS); | |
d6eb40f6 TS |
2865 | /* This hack makes Wine work... */ |
2866 | env->segs[R_FS].selector = 0; | |
d2fd1af7 FB |
2867 | #else |
2868 | cpu_x86_load_seg(env, R_DS, 0); | |
2869 | cpu_x86_load_seg(env, R_ES, 0); | |
2870 | cpu_x86_load_seg(env, R_FS, 0); | |
2871 | cpu_x86_load_seg(env, R_GS, 0); | |
2872 | #endif | |
b346ff46 FB |
2873 | #elif defined(TARGET_ARM) |
2874 | { | |
2875 | int i; | |
b5ff1b31 | 2876 | cpsr_write(env, regs->uregs[16], 0xffffffff); |
b346ff46 FB |
2877 | for(i = 0; i < 16; i++) { |
2878 | env->regs[i] = regs->uregs[i]; | |
2879 | } | |
b346ff46 | 2880 | } |
93ac68bc | 2881 | #elif defined(TARGET_SPARC) |
060366c5 FB |
2882 | { |
2883 | int i; | |
2884 | env->pc = regs->pc; | |
2885 | env->npc = regs->npc; | |
2886 | env->y = regs->y; | |
2887 | for(i = 0; i < 8; i++) | |
2888 | env->gregs[i] = regs->u_regs[i]; | |
2889 | for(i = 0; i < 8; i++) | |
2890 | env->regwptr[i] = regs->u_regs[i + 8]; | |
2891 | } | |
67867308 FB |
2892 | #elif defined(TARGET_PPC) |
2893 | { | |
2894 | int i; | |
3fc6c082 | 2895 | |
0411a972 JM |
2896 | #if defined(TARGET_PPC64) |
2897 | #if defined(TARGET_ABI32) | |
2898 | env->msr &= ~((target_ulong)1 << MSR_SF); | |
e85e7c6e | 2899 | #else |
0411a972 JM |
2900 | env->msr |= (target_ulong)1 << MSR_SF; |
2901 | #endif | |
84409ddb | 2902 | #endif |
67867308 FB |
2903 | env->nip = regs->nip; |
2904 | for(i = 0; i < 32; i++) { | |
2905 | env->gpr[i] = regs->gpr[i]; | |
2906 | } | |
2907 | } | |
e6e5906b PB |
2908 | #elif defined(TARGET_M68K) |
2909 | { | |
e6e5906b PB |
2910 | env->pc = regs->pc; |
2911 | env->dregs[0] = regs->d0; | |
2912 | env->dregs[1] = regs->d1; | |
2913 | env->dregs[2] = regs->d2; | |
2914 | env->dregs[3] = regs->d3; | |
2915 | env->dregs[4] = regs->d4; | |
2916 | env->dregs[5] = regs->d5; | |
2917 | env->dregs[6] = regs->d6; | |
2918 | env->dregs[7] = regs->d7; | |
2919 | env->aregs[0] = regs->a0; | |
2920 | env->aregs[1] = regs->a1; | |
2921 | env->aregs[2] = regs->a2; | |
2922 | env->aregs[3] = regs->a3; | |
2923 | env->aregs[4] = regs->a4; | |
2924 | env->aregs[5] = regs->a5; | |
2925 | env->aregs[6] = regs->a6; | |
2926 | env->aregs[7] = regs->usp; | |
2927 | env->sr = regs->sr; | |
2928 | ts->sim_syscalls = 1; | |
2929 | } | |
b779e29e EI |
2930 | #elif defined(TARGET_MICROBLAZE) |
2931 | { | |
2932 | env->regs[0] = regs->r0; | |
2933 | env->regs[1] = regs->r1; | |
2934 | env->regs[2] = regs->r2; | |
2935 | env->regs[3] = regs->r3; | |
2936 | env->regs[4] = regs->r4; | |
2937 | env->regs[5] = regs->r5; | |
2938 | env->regs[6] = regs->r6; | |
2939 | env->regs[7] = regs->r7; | |
2940 | env->regs[8] = regs->r8; | |
2941 | env->regs[9] = regs->r9; | |
2942 | env->regs[10] = regs->r10; | |
2943 | env->regs[11] = regs->r11; | |
2944 | env->regs[12] = regs->r12; | |
2945 | env->regs[13] = regs->r13; | |
2946 | env->regs[14] = regs->r14; | |
2947 | env->regs[15] = regs->r15; | |
2948 | env->regs[16] = regs->r16; | |
2949 | env->regs[17] = regs->r17; | |
2950 | env->regs[18] = regs->r18; | |
2951 | env->regs[19] = regs->r19; | |
2952 | env->regs[20] = regs->r20; | |
2953 | env->regs[21] = regs->r21; | |
2954 | env->regs[22] = regs->r22; | |
2955 | env->regs[23] = regs->r23; | |
2956 | env->regs[24] = regs->r24; | |
2957 | env->regs[25] = regs->r25; | |
2958 | env->regs[26] = regs->r26; | |
2959 | env->regs[27] = regs->r27; | |
2960 | env->regs[28] = regs->r28; | |
2961 | env->regs[29] = regs->r29; | |
2962 | env->regs[30] = regs->r30; | |
2963 | env->regs[31] = regs->r31; | |
2964 | env->sregs[SR_PC] = regs->pc; | |
2965 | } | |
048f6b4d FB |
2966 | #elif defined(TARGET_MIPS) |
2967 | { | |
2968 | int i; | |
2969 | ||
2970 | for(i = 0; i < 32; i++) { | |
b5dc7732 | 2971 | env->active_tc.gpr[i] = regs->regs[i]; |
048f6b4d | 2972 | } |
b5dc7732 | 2973 | env->active_tc.PC = regs->cp0_epc; |
048f6b4d | 2974 | } |
fdf9b3e8 FB |
2975 | #elif defined(TARGET_SH4) |
2976 | { | |
2977 | int i; | |
2978 | ||
2979 | for(i = 0; i < 16; i++) { | |
2980 | env->gregs[i] = regs->regs[i]; | |
2981 | } | |
2982 | env->pc = regs->pc; | |
2983 | } | |
7a3148a9 JM |
2984 | #elif defined(TARGET_ALPHA) |
2985 | { | |
2986 | int i; | |
2987 | ||
2988 | for(i = 0; i < 28; i++) { | |
992f48a0 | 2989 | env->ir[i] = ((abi_ulong *)regs)[i]; |
7a3148a9 JM |
2990 | } |
2991 | env->ipr[IPR_USP] = regs->usp; | |
2992 | env->ir[30] = regs->usp; | |
2993 | env->pc = regs->pc; | |
2994 | env->unique = regs->unique; | |
2995 | } | |
48733d19 TS |
2996 | #elif defined(TARGET_CRIS) |
2997 | { | |
2998 | env->regs[0] = regs->r0; | |
2999 | env->regs[1] = regs->r1; | |
3000 | env->regs[2] = regs->r2; | |
3001 | env->regs[3] = regs->r3; | |
3002 | env->regs[4] = regs->r4; | |
3003 | env->regs[5] = regs->r5; | |
3004 | env->regs[6] = regs->r6; | |
3005 | env->regs[7] = regs->r7; | |
3006 | env->regs[8] = regs->r8; | |
3007 | env->regs[9] = regs->r9; | |
3008 | env->regs[10] = regs->r10; | |
3009 | env->regs[11] = regs->r11; | |
3010 | env->regs[12] = regs->r12; | |
3011 | env->regs[13] = regs->r13; | |
3012 | env->regs[14] = info->start_stack; | |
3013 | env->regs[15] = regs->acr; | |
3014 | env->pc = regs->erp; | |
3015 | } | |
b346ff46 FB |
3016 | #else |
3017 | #error unsupported target CPU | |
3018 | #endif | |
31e31b8a | 3019 | |
a87295e8 PB |
3020 | #if defined(TARGET_ARM) || defined(TARGET_M68K) |
3021 | ts->stack_base = info->start_stack; | |
3022 | ts->heap_base = info->brk; | |
3023 | /* This will be filled in on the first SYS_HEAPINFO call. */ | |
3024 | ts->heap_limit = 0; | |
3025 | #endif | |
3026 | ||
74c33bed FB |
3027 | if (gdbstub_port) { |
3028 | gdbserver_start (gdbstub_port); | |
1fddef4b FB |
3029 | gdb_handlesig(env, 0); |
3030 | } | |
1b6b029e FB |
3031 | cpu_loop(env); |
3032 | /* never exits */ | |
31e31b8a FB |
3033 | return 0; |
3034 | } |