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linux-user: Support for restarting system calls for SH4 targets
[mirror_qemu.git] / linux-user / main.c
CommitLineData
31e31b8a 1/*
93ac68bc 2 * qemu user main
5fafdf24 3 *
68d0f70e 4 * Copyright (c) 2003-2008 Fabrice Bellard
31e31b8a
FB		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
8167ee88 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31e31b8a 18 */
d39594e9 19#include "qemu/osdep.h"
e441570f 20#include <sys/mman.h>
edf8e2af 21#include <sys/syscall.h>
703e0e89 22#include <sys/resource.h>
31e31b8a 23
3ef693a0 24#include "qemu.h"
f348b6d1
VB		 25#include "qemu/path.h"
26#include "qemu/cutils.h"
27#include "qemu/help_option.h"
2b41f10e 28#include "cpu.h"
63c91552 29#include "exec/exec-all.h"
9002ec79 30#include "tcg.h"
1de7afc9
PB		 31#include "qemu/timer.h"
32#include "qemu/envlist.h"
d8fd2954 33#include "elf.h"
508127e2 34#include "exec/log.h"
04a6dfeb 35
d088d664
AJ		 36char *exec_path;
37
1b530a6d 38int singlestep;
8cb76755
SW		 39static const char *filename;
40static const char *argv0;
41static int gdbstub_port;
42static envlist_t *envlist;
51fb256a 43static const char *cpu_model;
379f6698
PB		 44unsigned long mmap_min_addr;
45unsigned long guest_base;
46int have_guest_base;
120a9848
PB		 47
48#define EXCP_DUMP(env, fmt, ...) \
49do { \
50 CPUState *cs = ENV_GET_CPU(env); \
51 fprintf(stderr, fmt , ## __VA_ARGS__); \
52 cpu_dump_state(cs, stderr, fprintf, 0); \
53 if (qemu_log_separate()) { \
54 qemu_log(fmt, ## __VA_ARGS__); \
55 log_cpu_state(cs, 0); \
56 } \
57} while (0)
58
288e65b9
AG		 59#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
60/*
61 * When running 32-on-64 we should make sure we can fit all of the possible
62 * guest address space into a contiguous chunk of virtual host memory.
63 *
64 * This way we will never overlap with our own libraries or binaries or stack
65 * or anything else that QEMU maps.
66 */
314992b1
AG		 67# ifdef TARGET_MIPS
68/* MIPS only supports 31 bits of virtual address space for user space */
69unsigned long reserved_va = 0x77000000;
70# else
288e65b9 71unsigned long reserved_va = 0xf7000000;
314992b1 72# endif
288e65b9 73#else
68a1c816 74unsigned long reserved_va;
379f6698 75#endif
1b530a6d 76
d03f9c32 77static void usage(int exitcode);
fc9c5412 78
7ee2822c 79static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
e586822a 80const char *qemu_uname_release;
586314f2 81
9de5e440
FB		 82/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
83 we allocate a bigger stack. Need a better solution, for example
84 by remapping the process stack directly at the right place */
703e0e89 85unsigned long guest_stack_size = 8 * 1024 * 1024UL;
31e31b8a
FB		 86
87void gemu_log(const char *fmt, ...)
88{
89 va_list ap;
90
91 va_start(ap, fmt);
92 vfprintf(stderr, fmt, ap);
93 va_end(ap);
94}
95
8fcd3692 96#if defined(TARGET_I386)
05390248 97int cpu_get_pic_interrupt(CPUX86State *env)
92ccca6a
FB		 98{
99 return -1;
100}
8fcd3692 101#endif
92ccca6a 102
d5975363
PB		 103/***********************************************************/
104/* Helper routines for implementing atomic operations. */
105
106/* To implement exclusive operations we force all cpus to syncronise.
107 We don't require a full sync, only that no cpus are executing guest code.
108 The alternative is to map target atomic ops onto host equivalents,
109 which requires quite a lot of per host/target work. */
c2764719 110static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
d5975363
PB		 111static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
112static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
113static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
114static int pending_cpus;
115
116/* Make sure everything is in a consistent state for calling fork(). */
117void fork_start(void)
118{
677ef623 119 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 120 pthread_mutex_lock(&exclusive_lock);
d032d1b4 121 mmap_fork_start();
d5975363
PB		 122}
123
124void fork_end(int child)
125{
d032d1b4 126 mmap_fork_end(child);
d5975363 127 if (child) {
bdc44640 128 CPUState *cpu, *next_cpu;
d5975363
PB		 129 /* Child processes created by fork() only have a single thread.
130 Discard information about the parent threads. */
bdc44640
AF		 131 CPU_FOREACH_SAFE(cpu, next_cpu) {
132 if (cpu != thread_cpu) {
133 QTAILQ_REMOVE(&cpus, thread_cpu, node);
134 }
135 }
d5975363
PB		 136 pending_cpus = 0;
137 pthread_mutex_init(&exclusive_lock, NULL);
c2764719 138 pthread_mutex_init(&cpu_list_mutex, NULL);
d5975363
PB		 139 pthread_cond_init(&exclusive_cond, NULL);
140 pthread_cond_init(&exclusive_resume, NULL);
677ef623 141 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
f7ec7f7b 142 gdbserver_fork(thread_cpu);
d5975363
PB		 143 } else {
144 pthread_mutex_unlock(&exclusive_lock);
677ef623 145 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 146 }
d5975363
PB		 147}
148
149/* Wait for pending exclusive operations to complete. The exclusive lock
150 must be held. */
151static inline void exclusive_idle(void)
152{
153 while (pending_cpus) {
154 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
155 }
156}
157
158/* Start an exclusive operation.
159 Must only be called from outside cpu_arm_exec. */
160static inline void start_exclusive(void)
161{
0315c31c
AF		 162 CPUState *other_cpu;
163
d5975363
PB		 164 pthread_mutex_lock(&exclusive_lock);
165 exclusive_idle();
166
167 pending_cpus = 1;
168 /* Make all other cpus stop executing. */
bdc44640 169 CPU_FOREACH(other_cpu) {
0315c31c 170 if (other_cpu->running) {
d5975363 171 pending_cpus++;
60a3e17a 172 cpu_exit(other_cpu);
d5975363
PB		 173 }
174 }
175 if (pending_cpus > 1) {
176 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
177 }
178}
179
180/* Finish an exclusive operation. */
f7e61b22 181static inline void __attribute__((unused)) end_exclusive(void)
d5975363
PB		 182{
183 pending_cpus = 0;
184 pthread_cond_broadcast(&exclusive_resume);
185 pthread_mutex_unlock(&exclusive_lock);
186}
187
188/* Wait for exclusive ops to finish, and begin cpu execution. */
0315c31c 189static inline void cpu_exec_start(CPUState *cpu)
d5975363
PB		 190{
191 pthread_mutex_lock(&exclusive_lock);
192 exclusive_idle();
0315c31c 193 cpu->running = true;
d5975363
PB		 194 pthread_mutex_unlock(&exclusive_lock);
195}
196
197/* Mark cpu as not executing, and release pending exclusive ops. */
0315c31c 198static inline void cpu_exec_end(CPUState *cpu)
d5975363
PB		 199{
200 pthread_mutex_lock(&exclusive_lock);
0315c31c 201 cpu->running = false;
d5975363
PB		 202 if (pending_cpus > 1) {
203 pending_cpus--;
204 if (pending_cpus == 1) {
205 pthread_cond_signal(&exclusive_cond);
206 }
207 }
208 exclusive_idle();
209 pthread_mutex_unlock(&exclusive_lock);
210}
c2764719
PB		 211
212void cpu_list_lock(void)
213{
214 pthread_mutex_lock(&cpu_list_mutex);
215}
216
217void cpu_list_unlock(void)
218{
219 pthread_mutex_unlock(&cpu_list_mutex);
220}
d5975363
PB		 221
222
a541f297
FB		 223#ifdef TARGET_I386
224/***********************************************************/
225/* CPUX86 core interface */
226
28ab0e2e
FB		 227uint64_t cpu_get_tsc(CPUX86State *env)
228{
4a7428c5 229 return cpu_get_host_ticks();
28ab0e2e
FB		 230}
231
5fafdf24 232static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
f4beb510 233 int flags)
6dbad63e 234{
f4beb510 235 unsigned int e1, e2;
53a5960a 236 uint32_t *p;
6dbad63e
FB		 237 e1 = (addr << 16) | (limit & 0xffff);
238 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
f4beb510 239 e2 |= flags;
53a5960a 240 p = ptr;
d538e8f5 241 p[0] = tswap32(e1);
242 p[1] = tswap32(e2);
f4beb510
FB		 243}
244
e441570f 245static uint64_t *idt_table;
eb38c52c 246#ifdef TARGET_X86_64
d2fd1af7
FB		 247static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
248 uint64_t addr, unsigned int sel)
f4beb510 249{
4dbc422b 250 uint32_t *p, e1, e2;
f4beb510
FB		 251 e1 = (addr & 0xffff) | (sel << 16);
252 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
53a5960a 253 p = ptr;
4dbc422b
FB		 254 p[0] = tswap32(e1);
255 p[1] = tswap32(e2);
256 p[2] = tswap32(addr >> 32);
257 p[3] = 0;
6dbad63e 258}
d2fd1af7
FB		 259/* only dpl matters as we do only user space emulation */
260static void set_idt(int n, unsigned int dpl)
261{
262 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
263}
264#else
d2fd1af7
FB		 265static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
266 uint32_t addr, unsigned int sel)
267{
4dbc422b 268 uint32_t *p, e1, e2;
d2fd1af7
FB		 269 e1 = (addr & 0xffff) | (sel << 16);
270 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
271 p = ptr;
4dbc422b
FB		 272 p[0] = tswap32(e1);
273 p[1] = tswap32(e2);
d2fd1af7
FB		 274}
275
f4beb510
FB		 276/* only dpl matters as we do only user space emulation */
277static void set_idt(int n, unsigned int dpl)
278{
279 set_gate(idt_table + n, 0, dpl, 0, 0);
280}
d2fd1af7 281#endif
31e31b8a 282
89e957e7 283void cpu_loop(CPUX86State *env)
1b6b029e 284{
db6b81d4 285 CPUState *cs = CPU(x86_env_get_cpu(env));
bc8a22cc 286 int trapnr;
992f48a0 287 abi_ulong pc;
0284b03b 288 abi_ulong ret;
c227f099 289 target_siginfo_t info;
851e67a1 290
1b6b029e 291 for(;;) {
b040bc9c 292 cpu_exec_start(cs);
ea3e9847 293 trapnr = cpu_x86_exec(cs);
b040bc9c 294 cpu_exec_end(cs);
bc8a22cc 295 switch(trapnr) {
f4beb510 296 case 0x80:
d2fd1af7 297 /* linux syscall from int $0x80 */
0284b03b
TB		 298 ret = do_syscall(env,
299 env->regs[R_EAX],
300 env->regs[R_EBX],
301 env->regs[R_ECX],
302 env->regs[R_EDX],
303 env->regs[R_ESI],
304 env->regs[R_EDI],
305 env->regs[R_EBP],
306 0, 0);
307 if (ret == -TARGET_ERESTARTSYS) {
308 env->eip -= 2;
309 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
310 env->regs[R_EAX] = ret;
311 }
f4beb510 312 break;
d2fd1af7
FB		 313#ifndef TARGET_ABI32
314 case EXCP_SYSCALL:
5ba18547 315 /* linux syscall from syscall instruction */
0284b03b
TB		 316 ret = do_syscall(env,
317 env->regs[R_EAX],
318 env->regs[R_EDI],
319 env->regs[R_ESI],
320 env->regs[R_EDX],
321 env->regs[10],
322 env->regs[8],
323 env->regs[9],
324 0, 0);
325 if (ret == -TARGET_ERESTARTSYS) {
326 env->eip -= 2;
327 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
328 env->regs[R_EAX] = ret;
329 }
d2fd1af7
FB		 330 break;
331#endif
f4beb510
FB		 332 case EXCP0B_NOSEG:
333 case EXCP0C_STACK:
a86b3c64 334 info.si_signo = TARGET_SIGBUS;
f4beb510
FB		 335 info.si_errno = 0;
336 info.si_code = TARGET_SI_KERNEL;
337 info._sifields._sigfault._addr = 0;
624f7979 338 queue_signal(env, info.si_signo, &info);
f4beb510 339 break;
1b6b029e 340 case EXCP0D_GPF:
d2fd1af7 341 /* XXX: potential problem if ABI32 */
84409ddb 342#ifndef TARGET_X86_64
851e67a1 343 if (env->eflags & VM_MASK) {
89e957e7 344 handle_vm86_fault(env);
84409ddb
JM		 345 } else
346#endif
347 {
a86b3c64 348 info.si_signo = TARGET_SIGSEGV;
f4beb510
FB		 349 info.si_errno = 0;
350 info.si_code = TARGET_SI_KERNEL;
351 info._sifields._sigfault._addr = 0;
624f7979 352 queue_signal(env, info.si_signo, &info);
1b6b029e
FB		 353 }
354 break;
b689bc57 355 case EXCP0E_PAGE:
a86b3c64 356 info.si_signo = TARGET_SIGSEGV;
b689bc57
FB		 357 info.si_errno = 0;
358 if (!(env->error_code & 1))
359 info.si_code = TARGET_SEGV_MAPERR;
360 else
361 info.si_code = TARGET_SEGV_ACCERR;
970a87a6 362 info._sifields._sigfault._addr = env->cr[2];
624f7979 363 queue_signal(env, info.si_signo, &info);
b689bc57 364 break;
9de5e440 365 case EXCP00_DIVZ:
84409ddb 366#ifndef TARGET_X86_64
bc8a22cc 367 if (env->eflags & VM_MASK) {
447db213 368 handle_vm86_trap(env, trapnr);
84409ddb
JM		 369 } else
370#endif
371 {
bc8a22cc 372 /* division by zero */
a86b3c64 373 info.si_signo = TARGET_SIGFPE;
bc8a22cc
FB		 374 info.si_errno = 0;
375 info.si_code = TARGET_FPE_INTDIV;
376 info._sifields._sigfault._addr = env->eip;
624f7979 377 queue_signal(env, info.si_signo, &info);
bc8a22cc 378 }
9de5e440 379 break;
01df040b 380 case EXCP01_DB:
447db213 381 case EXCP03_INT3:
84409ddb 382#ifndef TARGET_X86_64
447db213
FB		 383 if (env->eflags & VM_MASK) {
384 handle_vm86_trap(env, trapnr);
84409ddb
JM		 385 } else
386#endif
387 {
a86b3c64 388 info.si_signo = TARGET_SIGTRAP;
447db213 389 info.si_errno = 0;
01df040b 390 if (trapnr == EXCP01_DB) {
447db213
FB		 391 info.si_code = TARGET_TRAP_BRKPT;
392 info._sifields._sigfault._addr = env->eip;
393 } else {
394 info.si_code = TARGET_SI_KERNEL;
395 info._sifields._sigfault._addr = 0;
396 }
624f7979 397 queue_signal(env, info.si_signo, &info);
447db213
FB		 398 }
399 break;
9de5e440
FB		 400 case EXCP04_INTO:
401 case EXCP05_BOUND:
84409ddb 402#ifndef TARGET_X86_64
bc8a22cc 403 if (env->eflags & VM_MASK) {
447db213 404 handle_vm86_trap(env, trapnr);
84409ddb
JM		 405 } else
406#endif
407 {
a86b3c64 408 info.si_signo = TARGET_SIGSEGV;
bc8a22cc 409 info.si_errno = 0;
b689bc57 410 info.si_code = TARGET_SI_KERNEL;
bc8a22cc 411 info._sifields._sigfault._addr = 0;
624f7979 412 queue_signal(env, info.si_signo, &info);
bc8a22cc 413 }
9de5e440
FB		 414 break;
415 case EXCP06_ILLOP:
a86b3c64 416 info.si_signo = TARGET_SIGILL;
9de5e440
FB		 417 info.si_errno = 0;
418 info.si_code = TARGET_ILL_ILLOPN;
419 info._sifields._sigfault._addr = env->eip;
624f7979 420 queue_signal(env, info.si_signo, &info);
9de5e440
FB		 421 break;
422 case EXCP_INTERRUPT:
423 /* just indicate that signals should be handled asap */
424 break;
1fddef4b
FB		 425 case EXCP_DEBUG:
426 {
427 int sig;
428
db6b81d4 429 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 430 if (sig)
431 {
432 info.si_signo = sig;
433 info.si_errno = 0;
434 info.si_code = TARGET_TRAP_BRKPT;
624f7979 435 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 436 }
437 }
438 break;
1b6b029e 439 default:
970a87a6 440 pc = env->segs[R_CS].base + env->eip;
120a9848
PB		 441 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
442 (long)pc, trapnr);
1b6b029e
FB		 443 abort();
444 }
66fb9763 445 process_pending_signals(env);
1b6b029e
FB		 446 }
447}
b346ff46
FB		 448#endif
449
450#ifdef TARGET_ARM
451
49017bd8 452#define get_user_code_u32(x, gaddr, env) \
d8fd2954 453 ({ abi_long __r = get_user_u32((x), (gaddr)); \
f9fd40eb 454 if (!__r && bswap_code(arm_sctlr_b(env))) { \
d8fd2954
PB		 455 (x) = bswap32(x); \
456 } \
457 __r; \
458 })
459
49017bd8 460#define get_user_code_u16(x, gaddr, env) \
d8fd2954 461 ({ abi_long __r = get_user_u16((x), (gaddr)); \
f9fd40eb 462 if (!__r && bswap_code(arm_sctlr_b(env))) { \
d8fd2954
PB		 463 (x) = bswap16(x); \
464 } \
465 __r; \
466 })
467
c3ae85fc
PB		 468#define get_user_data_u32(x, gaddr, env) \
469 ({ abi_long __r = get_user_u32((x), (gaddr)); \
470 if (!__r && arm_cpu_bswap_data(env)) { \
471 (x) = bswap32(x); \
472 } \
473 __r; \
474 })
475
476#define get_user_data_u16(x, gaddr, env) \
477 ({ abi_long __r = get_user_u16((x), (gaddr)); \
478 if (!__r && arm_cpu_bswap_data(env)) { \
479 (x) = bswap16(x); \
480 } \
481 __r; \
482 })
483
484#define put_user_data_u32(x, gaddr, env) \
485 ({ typeof(x) __x = (x); \
486 if (arm_cpu_bswap_data(env)) { \
487 __x = bswap32(__x); \
488 } \
489 put_user_u32(__x, (gaddr)); \
490 })
491
492#define put_user_data_u16(x, gaddr, env) \
493 ({ typeof(x) __x = (x); \
494 if (arm_cpu_bswap_data(env)) { \
495 __x = bswap16(__x); \
496 } \
497 put_user_u16(__x, (gaddr)); \
498 })
499
1861c454
PM		 500#ifdef TARGET_ABI32
501/* Commpage handling -- there is no commpage for AArch64 */
502
97cc7560
DDAG		 503/*
504 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
505 * Input:
506 * r0 = pointer to oldval
507 * r1 = pointer to newval
508 * r2 = pointer to target value
509 *
510 * Output:
511 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
512 * C set if *ptr was changed, clear if no exchange happened
513 *
514 * Note segv's in kernel helpers are a bit tricky, we can set the
515 * data address sensibly but the PC address is just the entry point.
516 */
517static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
518{
519 uint64_t oldval, newval, val;
520 uint32_t addr, cpsr;
521 target_siginfo_t info;
522
523 /* Based on the 32 bit code in do_kernel_trap */
524
525 /* XXX: This only works between threads, not between processes.
526 It's probably possible to implement this with native host
527 operations. However things like ldrex/strex are much harder so
528 there's not much point trying. */
529 start_exclusive();
530 cpsr = cpsr_read(env);
531 addr = env->regs[2];
532
533 if (get_user_u64(oldval, env->regs[0])) {
abf1172f 534 env->exception.vaddress = env->regs[0];
97cc7560
DDAG		 535 goto segv;
536 };
537
538 if (get_user_u64(newval, env->regs[1])) {
abf1172f 539 env->exception.vaddress = env->regs[1];
97cc7560
DDAG		 540 goto segv;
541 };
542
543 if (get_user_u64(val, addr)) {
abf1172f 544 env->exception.vaddress = addr;
97cc7560
DDAG		 545 goto segv;
546 }
547
548 if (val == oldval) {
549 val = newval;
550
551 if (put_user_u64(val, addr)) {
abf1172f 552 env->exception.vaddress = addr;
97cc7560
DDAG		 553 goto segv;
554 };
555
556 env->regs[0] = 0;
557 cpsr |= CPSR_C;
558 } else {
559 env->regs[0] = -1;
560 cpsr &= ~CPSR_C;
561 }
50866ba5 562 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
97cc7560
DDAG		 563 end_exclusive();
564 return;
565
566segv:
567 end_exclusive();
568 /* We get the PC of the entry address - which is as good as anything,
569 on a real kernel what you get depends on which mode it uses. */
a86b3c64 570 info.si_signo = TARGET_SIGSEGV;
97cc7560
DDAG		 571 info.si_errno = 0;
572 /* XXX: check env->error_code */
573 info.si_code = TARGET_SEGV_MAPERR;
abf1172f 574 info._sifields._sigfault._addr = env->exception.vaddress;
97cc7560 575 queue_signal(env, info.si_signo, &info);
97cc7560
DDAG		 576}
577
fbb4a2e3
PB		 578/* Handle a jump to the kernel code page. */
579static int
580do_kernel_trap(CPUARMState *env)
581{
582 uint32_t addr;
583 uint32_t cpsr;
584 uint32_t val;
585
586 switch (env->regs[15]) {
587 case 0xffff0fa0: /* __kernel_memory_barrier */
588 /* ??? No-op. Will need to do better for SMP. */
589 break;
590 case 0xffff0fc0: /* __kernel_cmpxchg */
d5975363
PB		 591 /* XXX: This only works between threads, not between processes.
592 It's probably possible to implement this with native host
593 operations. However things like ldrex/strex are much harder so
594 there's not much point trying. */
595 start_exclusive();
fbb4a2e3
PB		 596 cpsr = cpsr_read(env);
597 addr = env->regs[2];
598 /* FIXME: This should SEGV if the access fails. */
599 if (get_user_u32(val, addr))
600 val = ~env->regs[0];
601 if (val == env->regs[0]) {
602 val = env->regs[1];
603 /* FIXME: Check for segfaults. */
604 put_user_u32(val, addr);
605 env->regs[0] = 0;
606 cpsr |= CPSR_C;
607 } else {
608 env->regs[0] = -1;
609 cpsr &= ~CPSR_C;
610 }
50866ba5 611 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
d5975363 612 end_exclusive();
fbb4a2e3
PB		 613 break;
614 case 0xffff0fe0: /* __kernel_get_tls */
b8d43285 615 env->regs[0] = cpu_get_tls(env);
fbb4a2e3 616 break;
97cc7560
DDAG		 617 case 0xffff0f60: /* __kernel_cmpxchg64 */
618 arm_kernel_cmpxchg64_helper(env);
619 break;
620
fbb4a2e3
PB		 621 default:
622 return 1;
623 }
624 /* Jump back to the caller. */
625 addr = env->regs[14];
626 if (addr & 1) {
627 env->thumb = 1;
628 addr &= ~1;
629 }
630 env->regs[15] = addr;
631
632 return 0;
633}
634
fa2ef212 635/* Store exclusive handling for AArch32 */
426f5abc
PB		 636static int do_strex(CPUARMState *env)
637{
03d05e2d 638 uint64_t val;
426f5abc
PB		 639 int size;
640 int rc = 1;
641 int segv = 0;
642 uint32_t addr;
643 start_exclusive();
03d05e2d 644 if (env->exclusive_addr != env->exclusive_test) {
426f5abc
PB		 645 goto fail;
646 }
03d05e2d
PM		 647 /* We know we're always AArch32 so the address is in uint32_t range
648 * unless it was the -1 exclusive-monitor-lost value (which won't
649 * match exclusive_test above).
650 */
651 assert(extract64(env->exclusive_addr, 32, 32) == 0);
652 addr = env->exclusive_addr;
426f5abc
PB		 653 size = env->exclusive_info & 0xf;
654 switch (size) {
655 case 0:
656 segv = get_user_u8(val, addr);
657 break;
658 case 1:
c3ae85fc 659 segv = get_user_data_u16(val, addr, env);
426f5abc
PB		 660 break;
661 case 2:
662 case 3:
c3ae85fc 663 segv = get_user_data_u32(val, addr, env);
426f5abc 664 break;
f7001a3b
AJ		 665 default:
666 abort();
426f5abc
PB		 667 }
668 if (segv) {
abf1172f 669 env->exception.vaddress = addr;
426f5abc
PB		 670 goto done;
671 }
426f5abc 672 if (size == 3) {
03d05e2d 673 uint32_t valhi;
c3ae85fc 674 segv = get_user_data_u32(valhi, addr + 4, env);
426f5abc 675 if (segv) {
abf1172f 676 env->exception.vaddress = addr + 4;
426f5abc
PB		 677 goto done;
678 }
c3ae85fc
PB		 679 if (arm_cpu_bswap_data(env)) {
680 val = deposit64((uint64_t)valhi, 32, 32, val);
681 } else {
682 val = deposit64(val, 32, 32, valhi);
683 }
426f5abc 684 }
03d05e2d
PM		 685 if (val != env->exclusive_val) {
686 goto fail;
687 }
688
426f5abc
PB		 689 val = env->regs[(env->exclusive_info >> 8) & 0xf];
690 switch (size) {
691 case 0:
692 segv = put_user_u8(val, addr);
693 break;
694 case 1:
c3ae85fc 695 segv = put_user_data_u16(val, addr, env);
426f5abc
PB		 696 break;
697 case 2:
698 case 3:
c3ae85fc 699 segv = put_user_data_u32(val, addr, env);
426f5abc
PB		 700 break;
701 }
702 if (segv) {
abf1172f 703 env->exception.vaddress = addr;
426f5abc
PB		 704 goto done;
705 }
706 if (size == 3) {
707 val = env->regs[(env->exclusive_info >> 12) & 0xf];
c3ae85fc 708 segv = put_user_data_u32(val, addr + 4, env);
426f5abc 709 if (segv) {
abf1172f 710 env->exception.vaddress = addr + 4;
426f5abc
PB		 711 goto done;
712 }
713 }
714 rc = 0;
715fail:
725b8a69 716 env->regs[15] += 4;
426f5abc
PB		 717 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
718done:
719 end_exclusive();
720 return segv;
721}
722
b346ff46
FB		 723void cpu_loop(CPUARMState *env)
724{
0315c31c 725 CPUState *cs = CPU(arm_env_get_cpu(env));
b346ff46
FB		 726 int trapnr;
727 unsigned int n, insn;
c227f099 728 target_siginfo_t info;
b5ff1b31 729 uint32_t addr;
f0267ef7 730 abi_ulong ret;
3b46e624 731
b346ff46 732 for(;;) {
0315c31c 733 cpu_exec_start(cs);
ea3e9847 734 trapnr = cpu_arm_exec(cs);
0315c31c 735 cpu_exec_end(cs);
b346ff46
FB		 736 switch(trapnr) {
737 case EXCP_UDEF:
c6981055 738 {
0429a971 739 TaskState *ts = cs->opaque;
c6981055 740 uint32_t opcode;
6d9a42be 741 int rc;
c6981055
FB		 742
743 /* we handle the FPU emulation here, as Linux */
744 /* we get the opcode */
2f619698 745 /* FIXME - what to do if get_user() fails? */
49017bd8 746 get_user_code_u32(opcode, env->regs[15], env);
3b46e624 747
6d9a42be
AJ		 748 rc = EmulateAll(opcode, &ts->fpa, env);
749 if (rc == 0) { /* illegal instruction */
a86b3c64 750 info.si_signo = TARGET_SIGILL;
c6981055
FB		 751 info.si_errno = 0;
752 info.si_code = TARGET_ILL_ILLOPN;
753 info._sifields._sigfault._addr = env->regs[15];
624f7979 754 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 755 } else if (rc < 0) { /* FP exception */
756 int arm_fpe=0;
757
758 /* translate softfloat flags to FPSR flags */
759 if (-rc & float_flag_invalid)
760 arm_fpe |= BIT_IOC;
761 if (-rc & float_flag_divbyzero)
762 arm_fpe |= BIT_DZC;
763 if (-rc & float_flag_overflow)
764 arm_fpe |= BIT_OFC;
765 if (-rc & float_flag_underflow)
766 arm_fpe |= BIT_UFC;
767 if (-rc & float_flag_inexact)
768 arm_fpe |= BIT_IXC;
769
770 FPSR fpsr = ts->fpa.fpsr;
771 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
772
773 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
a86b3c64 774 info.si_signo = TARGET_SIGFPE;
6d9a42be
AJ		 775 info.si_errno = 0;
776
777 /* ordered by priority, least first */
778 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
779 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
780 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
781 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
782 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
783
784 info._sifields._sigfault._addr = env->regs[15];
624f7979 785 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 786 } else {
787 env->regs[15] += 4;
788 }
789
790 /* accumulate unenabled exceptions */
791 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
792 fpsr |= BIT_IXC;
793 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
794 fpsr |= BIT_UFC;
795 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
796 fpsr |= BIT_OFC;
797 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
798 fpsr |= BIT_DZC;
799 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
800 fpsr |= BIT_IOC;
801 ts->fpa.fpsr=fpsr;
802 } else { /* everything OK */
c6981055
FB		 803 /* increment PC */
804 env->regs[15] += 4;
805 }
806 }
b346ff46
FB		 807 break;
808 case EXCP_SWI:
06c949e6 809 case EXCP_BKPT:
b346ff46 810 {
ce4defa0 811 env->eabi = 1;
b346ff46 812 /* system call */
06c949e6
PB		 813 if (trapnr == EXCP_BKPT) {
814 if (env->thumb) {
2f619698 815 /* FIXME - what to do if get_user() fails? */
49017bd8 816 get_user_code_u16(insn, env->regs[15], env);
06c949e6
PB		 817 n = insn & 0xff;
818 env->regs[15] += 2;
819 } else {
2f619698 820 /* FIXME - what to do if get_user() fails? */
49017bd8 821 get_user_code_u32(insn, env->regs[15], env);
06c949e6
PB		 822 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
823 env->regs[15] += 4;
824 }
192c7bd9 825 } else {
06c949e6 826 if (env->thumb) {
2f619698 827 /* FIXME - what to do if get_user() fails? */
49017bd8 828 get_user_code_u16(insn, env->regs[15] - 2, env);
06c949e6
PB		 829 n = insn & 0xff;
830 } else {
2f619698 831 /* FIXME - what to do if get_user() fails? */
49017bd8 832 get_user_code_u32(insn, env->regs[15] - 4, env);
06c949e6
PB		 833 n = insn & 0xffffff;
834 }
192c7bd9
FB		 835 }
836
6f1f31c0 837 if (n == ARM_NR_cacheflush) {
dcfd14b3 838 /* nop */
a4f81979
FB		 839 } else if (n == ARM_NR_semihosting
840 || n == ARM_NR_thumb_semihosting) {
841 env->regs[0] = do_arm_semihosting (env);
3a1363ac 842 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
b346ff46 843 /* linux syscall */
ce4defa0 844 if (env->thumb || n == 0) {
192c7bd9
FB		 845 n = env->regs[7];
846 } else {
847 n -= ARM_SYSCALL_BASE;
ce4defa0 848 env->eabi = 0;
192c7bd9 849 }
fbb4a2e3
PB		 850 if ( n > ARM_NR_BASE) {
851 switch (n) {
852 case ARM_NR_cacheflush:
dcfd14b3 853 /* nop */
fbb4a2e3
PB		 854 break;
855 case ARM_NR_set_tls:
856 cpu_set_tls(env, env->regs[0]);
857 env->regs[0] = 0;
858 break;
d5355087
HL		 859 case ARM_NR_breakpoint:
860 env->regs[15] -= env->thumb ? 2 : 4;
861 goto excp_debug;
fbb4a2e3
PB		 862 default:
863 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
864 n);
865 env->regs[0] = -TARGET_ENOSYS;
866 break;
867 }
868 } else {
f0267ef7
TB		 869 ret = do_syscall(env,
870 n,
871 env->regs[0],
872 env->regs[1],
873 env->regs[2],
874 env->regs[3],
875 env->regs[4],
876 env->regs[5],
877 0, 0);
878 if (ret == -TARGET_ERESTARTSYS) {
879 env->regs[15] -= env->thumb ? 2 : 4;
880 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
881 env->regs[0] = ret;
882 }
fbb4a2e3 883 }
b346ff46
FB		 884 } else {
885 goto error;
886 }
887 }
888 break;
43fff238
FB		 889 case EXCP_INTERRUPT:
890 /* just indicate that signals should be handled asap */
891 break;
abf1172f
PM		 892 case EXCP_STREX:
893 if (!do_strex(env)) {
894 break;
895 }
896 /* fall through for segv */
68016c62
FB		 897 case EXCP_PREFETCH_ABORT:
898 case EXCP_DATA_ABORT:
abf1172f 899 addr = env->exception.vaddress;
68016c62 900 {
a86b3c64 901 info.si_signo = TARGET_SIGSEGV;
68016c62
FB		 902 info.si_errno = 0;
903 /* XXX: check env->error_code */
904 info.si_code = TARGET_SEGV_MAPERR;
b5ff1b31 905 info._sifields._sigfault._addr = addr;
624f7979 906 queue_signal(env, info.si_signo, &info);
68016c62
FB		 907 }
908 break;
1fddef4b 909 case EXCP_DEBUG:
d5355087 910 excp_debug:
1fddef4b
FB		 911 {
912 int sig;
913
db6b81d4 914 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 915 if (sig)
916 {
917 info.si_signo = sig;
918 info.si_errno = 0;
919 info.si_code = TARGET_TRAP_BRKPT;
624f7979 920 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 921 }
922 }
923 break;
fbb4a2e3
PB		 924 case EXCP_KERNEL_TRAP:
925 if (do_kernel_trap(env))
926 goto error;
927 break;
f911e0a3
PM		 928 case EXCP_YIELD:
929 /* nothing to do here for user-mode, just resume guest code */
930 break;
b346ff46
FB		 931 default:
932 error:
120a9848 933 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
b346ff46
FB		 934 abort();
935 }
936 process_pending_signals(env);
937 }
938}
939
1861c454
PM		 940#else
941
fa2ef212
MM		 942/*
943 * Handle AArch64 store-release exclusive
944 *
945 * rs = gets the status result of store exclusive
946 * rt = is the register that is stored
947 * rt2 = is the second register store (in STP)
948 *
949 */
950static int do_strex_a64(CPUARMState *env)
951{
952 uint64_t val;
953 int size;
954 bool is_pair;
955 int rc = 1;
956 int segv = 0;
957 uint64_t addr;
958 int rs, rt, rt2;
959
960 start_exclusive();
961 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
962 size = extract32(env->exclusive_info, 0, 2);
963 is_pair = extract32(env->exclusive_info, 2, 1);
964 rs = extract32(env->exclusive_info, 4, 5);
965 rt = extract32(env->exclusive_info, 9, 5);
966 rt2 = extract32(env->exclusive_info, 14, 5);
967
968 addr = env->exclusive_addr;
969
970 if (addr != env->exclusive_test) {
971 goto finish;
972 }
973
974 switch (size) {
975 case 0:
976 segv = get_user_u8(val, addr);
977 break;
978 case 1:
979 segv = get_user_u16(val, addr);
980 break;
981 case 2:
982 segv = get_user_u32(val, addr);
983 break;
984 case 3:
985 segv = get_user_u64(val, addr);
986 break;
987 default:
988 abort();
989 }
990 if (segv) {
abf1172f 991 env->exception.vaddress = addr;
fa2ef212
MM		 992 goto error;
993 }
994 if (val != env->exclusive_val) {
995 goto finish;
996 }
997 if (is_pair) {
998 if (size == 2) {
999 segv = get_user_u32(val, addr + 4);
1000 } else {
1001 segv = get_user_u64(val, addr + 8);
1002 }
1003 if (segv) {
abf1172f 1004 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 1005 goto error;
1006 }
1007 if (val != env->exclusive_high) {
1008 goto finish;
1009 }
1010 }
2ea5a2ca
JG		 1011 /* handle the zero register */
1012 val = rt == 31 ? 0 : env->xregs[rt];
fa2ef212
MM		 1013 switch (size) {
1014 case 0:
1015 segv = put_user_u8(val, addr);
1016 break;
1017 case 1:
1018 segv = put_user_u16(val, addr);
1019 break;
1020 case 2:
1021 segv = put_user_u32(val, addr);
1022 break;
1023 case 3:
1024 segv = put_user_u64(val, addr);
1025 break;
1026 }
1027 if (segv) {
1028 goto error;
1029 }
1030 if (is_pair) {
2ea5a2ca
JG		 1031 /* handle the zero register */
1032 val = rt2 == 31 ? 0 : env->xregs[rt2];
fa2ef212
MM		 1033 if (size == 2) {
1034 segv = put_user_u32(val, addr + 4);
1035 } else {
1036 segv = put_user_u64(val, addr + 8);
1037 }
1038 if (segv) {
abf1172f 1039 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 1040 goto error;
1041 }
1042 }
1043 rc = 0;
1044finish:
1045 env->pc += 4;
1046 /* rs == 31 encodes a write to the ZR, thus throwing away
1047 * the status return. This is rather silly but valid.
1048 */
1049 if (rs < 31) {
1050 env->xregs[rs] = rc;
1051 }
1052error:
1053 /* instruction faulted, PC does not advance */
1054 /* either way a strex releases any exclusive lock we have */
1055 env->exclusive_addr = -1;
1056 end_exclusive();
1057 return segv;
1058}
1059
1861c454
PM		 1060/* AArch64 main loop */
1061void cpu_loop(CPUARMState *env)
1062{
1063 CPUState *cs = CPU(arm_env_get_cpu(env));
1064 int trapnr, sig;
f0267ef7 1065 abi_long ret;
1861c454 1066 target_siginfo_t info;
1861c454
PM		 1067
1068 for (;;) {
1069 cpu_exec_start(cs);
ea3e9847 1070 trapnr = cpu_arm_exec(cs);
1861c454
PM		 1071 cpu_exec_end(cs);
1072
1073 switch (trapnr) {
1074 case EXCP_SWI:
f0267ef7
TB		 1075 ret = do_syscall(env,
1076 env->xregs[8],
1077 env->xregs[0],
1078 env->xregs[1],
1079 env->xregs[2],
1080 env->xregs[3],
1081 env->xregs[4],
1082 env->xregs[5],
1083 0, 0);
1084 if (ret == -TARGET_ERESTARTSYS) {
1085 env->pc -= 4;
1086 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
1087 env->xregs[0] = ret;
1088 }
1861c454
PM		 1089 break;
1090 case EXCP_INTERRUPT:
1091 /* just indicate that signals should be handled asap */
1092 break;
1093 case EXCP_UDEF:
a86b3c64 1094 info.si_signo = TARGET_SIGILL;
1861c454
PM		 1095 info.si_errno = 0;
1096 info.si_code = TARGET_ILL_ILLOPN;
1097 info._sifields._sigfault._addr = env->pc;
1098 queue_signal(env, info.si_signo, &info);
1099 break;
abf1172f
PM		 1100 case EXCP_STREX:
1101 if (!do_strex_a64(env)) {
1102 break;
1103 }
1104 /* fall through for segv */
1861c454 1105 case EXCP_PREFETCH_ABORT:
1861c454 1106 case EXCP_DATA_ABORT:
a86b3c64 1107 info.si_signo = TARGET_SIGSEGV;
1861c454
PM		 1108 info.si_errno = 0;
1109 /* XXX: check env->error_code */
1110 info.si_code = TARGET_SEGV_MAPERR;
686581ad 1111 info._sifields._sigfault._addr = env->exception.vaddress;
1861c454
PM		 1112 queue_signal(env, info.si_signo, &info);
1113 break;
1114 case EXCP_DEBUG:
1115 case EXCP_BKPT:
1116 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1117 if (sig) {
1118 info.si_signo = sig;
1119 info.si_errno = 0;
1120 info.si_code = TARGET_TRAP_BRKPT;
1121 queue_signal(env, info.si_signo, &info);
1122 }
1123 break;
8012c84f
PM		 1124 case EXCP_SEMIHOST:
1125 env->xregs[0] = do_arm_semihosting(env);
1126 break;
f911e0a3
PM		 1127 case EXCP_YIELD:
1128 /* nothing to do here for user-mode, just resume guest code */
1129 break;
1861c454 1130 default:
120a9848 1131 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1861c454
PM		 1132 abort();
1133 }
1134 process_pending_signals(env);
fa2ef212
MM		 1135 /* Exception return on AArch64 always clears the exclusive monitor,
1136 * so any return to running guest code implies this.
1137 * A strex (successful or otherwise) also clears the monitor, so
1138 * we don't need to specialcase EXCP_STREX.
1139 */
1140 env->exclusive_addr = -1;
1861c454
PM		 1141 }
1142}
1143#endif /* ndef TARGET_ABI32 */
1144
b346ff46 1145#endif
1b6b029e 1146
d2fbca94
GX		 1147#ifdef TARGET_UNICORE32
1148
05390248 1149void cpu_loop(CPUUniCore32State *env)
d2fbca94 1150{
0315c31c 1151 CPUState *cs = CPU(uc32_env_get_cpu(env));
d2fbca94
GX		 1152 int trapnr;
1153 unsigned int n, insn;
1154 target_siginfo_t info;
1155
1156 for (;;) {
0315c31c 1157 cpu_exec_start(cs);
ea3e9847 1158 trapnr = uc32_cpu_exec(cs);
0315c31c 1159 cpu_exec_end(cs);
d2fbca94
GX		 1160 switch (trapnr) {
1161 case UC32_EXCP_PRIV:
1162 {
1163 /* system call */
1164 get_user_u32(insn, env->regs[31] - 4);
1165 n = insn & 0xffffff;
1166
1167 if (n >= UC32_SYSCALL_BASE) {
1168 /* linux syscall */
1169 n -= UC32_SYSCALL_BASE;
1170 if (n == UC32_SYSCALL_NR_set_tls) {
1171 cpu_set_tls(env, env->regs[0]);
1172 env->regs[0] = 0;
1173 } else {
1174 env->regs[0] = do_syscall(env,
1175 n,
1176 env->regs[0],
1177 env->regs[1],
1178 env->regs[2],
1179 env->regs[3],
1180 env->regs[4],
5945cfcb
PM		 1181 env->regs[5],
1182 0, 0);
d2fbca94
GX		 1183 }
1184 } else {
1185 goto error;
1186 }
1187 }
1188 break;
d48813dd
GX		 1189 case UC32_EXCP_DTRAP:
1190 case UC32_EXCP_ITRAP:
a86b3c64 1191 info.si_signo = TARGET_SIGSEGV;
d2fbca94
GX		 1192 info.si_errno = 0;
1193 /* XXX: check env->error_code */
1194 info.si_code = TARGET_SEGV_MAPERR;
1195 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1196 queue_signal(env, info.si_signo, &info);
1197 break;
1198 case EXCP_INTERRUPT:
1199 /* just indicate that signals should be handled asap */
1200 break;
1201 case EXCP_DEBUG:
1202 {
1203 int sig;
1204
db6b81d4 1205 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d2fbca94
GX		 1206 if (sig) {
1207 info.si_signo = sig;
1208 info.si_errno = 0;
1209 info.si_code = TARGET_TRAP_BRKPT;
1210 queue_signal(env, info.si_signo, &info);
1211 }
1212 }
1213 break;
1214 default:
1215 goto error;
1216 }
1217 process_pending_signals(env);
1218 }
1219
1220error:
120a9848 1221 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
d2fbca94
GX		 1222 abort();
1223}
1224#endif
1225
93ac68bc 1226#ifdef TARGET_SPARC
ed23fbd9 1227#define SPARC64_STACK_BIAS 2047
93ac68bc 1228
060366c5
FB		 1229//#define DEBUG_WIN
1230
2623cbaf
FB		 1231/* WARNING: dealing with register windows _is_ complicated. More info
1232 can be found at http://www.sics.se/~psm/sparcstack.html */
060366c5
FB		 1233static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1234{
1a14026e 1235 index = (index + cwp * 16) % (16 * env->nwindows);
060366c5
FB		 1236 /* wrap handling : if cwp is on the last window, then we use the
1237 registers 'after' the end */
1a14026e
BS		 1238 if (index < 8 && env->cwp == env->nwindows - 1)
1239 index += 16 * env->nwindows;
060366c5
FB		 1240 return index;
1241}
1242
2623cbaf
FB		 1243/* save the register window 'cwp1' */
1244static inline void save_window_offset(CPUSPARCState *env, int cwp1)
060366c5 1245{
2623cbaf 1246 unsigned int i;
992f48a0 1247 abi_ulong sp_ptr;
3b46e624 1248
53a5960a 1249 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1250#ifdef TARGET_SPARC64
1251 if (sp_ptr & 3)
1252 sp_ptr += SPARC64_STACK_BIAS;
1253#endif
060366c5 1254#if defined(DEBUG_WIN)
2daf0284
BS		 1255 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1256 sp_ptr, cwp1);
060366c5 1257#endif
2623cbaf 1258 for(i = 0; i < 16; i++) {
2f619698
FB		 1259 /* FIXME - what to do if put_user() fails? */
1260 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1261 sp_ptr += sizeof(abi_ulong);
2623cbaf 1262 }
060366c5
FB		 1263}
1264
1265static void save_window(CPUSPARCState *env)
1266{
5ef54116 1267#ifndef TARGET_SPARC64
2623cbaf 1268 unsigned int new_wim;
1a14026e
BS		 1269 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1270 ((1LL << env->nwindows) - 1);
1271 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
2623cbaf 1272 env->wim = new_wim;
5ef54116 1273#else
1a14026e 1274 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
5ef54116
FB		 1275 env->cansave++;
1276 env->canrestore--;
1277#endif
060366c5
FB		 1278}
1279
1280static void restore_window(CPUSPARCState *env)
1281{
eda52953
BS		 1282#ifndef TARGET_SPARC64
1283 unsigned int new_wim;
1284#endif
1285 unsigned int i, cwp1;
992f48a0 1286 abi_ulong sp_ptr;
3b46e624 1287
eda52953 1288#ifndef TARGET_SPARC64
1a14026e
BS		 1289 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1290 ((1LL << env->nwindows) - 1);
eda52953 1291#endif
3b46e624 1292
060366c5 1293 /* restore the invalid window */
1a14026e 1294 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
53a5960a 1295 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1296#ifdef TARGET_SPARC64
1297 if (sp_ptr & 3)
1298 sp_ptr += SPARC64_STACK_BIAS;
1299#endif
060366c5 1300#if defined(DEBUG_WIN)
2daf0284
BS		 1301 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1302 sp_ptr, cwp1);
060366c5 1303#endif
2623cbaf 1304 for(i = 0; i < 16; i++) {
2f619698
FB		 1305 /* FIXME - what to do if get_user() fails? */
1306 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1307 sp_ptr += sizeof(abi_ulong);
2623cbaf 1308 }
5ef54116
FB		 1309#ifdef TARGET_SPARC64
1310 env->canrestore++;
1a14026e
BS		 1311 if (env->cleanwin < env->nwindows - 1)
1312 env->cleanwin++;
5ef54116 1313 env->cansave--;
eda52953
BS		 1314#else
1315 env->wim = new_wim;
5ef54116 1316#endif
060366c5
FB		 1317}
1318
1319static void flush_windows(CPUSPARCState *env)
1320{
1321 int offset, cwp1;
2623cbaf
FB		 1322
1323 offset = 1;
060366c5
FB		 1324 for(;;) {
1325 /* if restore would invoke restore_window(), then we can stop */
1a14026e 1326 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
eda52953 1327#ifndef TARGET_SPARC64
060366c5
FB		 1328 if (env->wim & (1 << cwp1))
1329 break;
eda52953
BS		 1330#else
1331 if (env->canrestore == 0)
1332 break;
1333 env->cansave++;
1334 env->canrestore--;
1335#endif
2623cbaf 1336 save_window_offset(env, cwp1);
060366c5
FB		 1337 offset++;
1338 }
1a14026e 1339 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
eda52953
BS		 1340#ifndef TARGET_SPARC64
1341 /* set wim so that restore will reload the registers */
2623cbaf 1342 env->wim = 1 << cwp1;
eda52953 1343#endif
2623cbaf
FB		 1344#if defined(DEBUG_WIN)
1345 printf("flush_windows: nb=%d\n", offset - 1);
80a9d035 1346#endif
2623cbaf 1347}
060366c5 1348
93ac68bc
FB		 1349void cpu_loop (CPUSPARCState *env)
1350{
878096ee 1351 CPUState *cs = CPU(sparc_env_get_cpu(env));
2cc20260
RH		 1352 int trapnr;
1353 abi_long ret;
c227f099 1354 target_siginfo_t info;
3b46e624 1355
060366c5 1356 while (1) {
b040bc9c 1357 cpu_exec_start(cs);
ea3e9847 1358 trapnr = cpu_sparc_exec(cs);
b040bc9c 1359 cpu_exec_end(cs);
3b46e624 1360
20132b96
RH		 1361 /* Compute PSR before exposing state. */
1362 if (env->cc_op != CC_OP_FLAGS) {
1363 cpu_get_psr(env);
1364 }
1365
060366c5 1366 switch (trapnr) {
5ef54116 1367#ifndef TARGET_SPARC64
5fafdf24 1368 case 0x88:
060366c5 1369 case 0x90:
5ef54116 1370#else
cb33da57 1371 case 0x110:
5ef54116
FB		 1372 case 0x16d:
1373#endif
060366c5 1374 ret = do_syscall (env, env->gregs[1],
5fafdf24
TS		 1375 env->regwptr[0], env->regwptr[1],
1376 env->regwptr[2], env->regwptr[3],
5945cfcb
PM		 1377 env->regwptr[4], env->regwptr[5],
1378 0, 0);
c0bea68f
TB		 1379 if (ret == -TARGET_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) {
1380 break;
1381 }
2cc20260 1382 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
992f48a0 1383#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1384 env->xcc |= PSR_CARRY;
1385#else
060366c5 1386 env->psr |= PSR_CARRY;
27908725 1387#endif
060366c5
FB		 1388 ret = -ret;
1389 } else {
992f48a0 1390#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1391 env->xcc &= ~PSR_CARRY;
1392#else
060366c5 1393 env->psr &= ~PSR_CARRY;
27908725 1394#endif
060366c5
FB		 1395 }
1396 env->regwptr[0] = ret;
1397 /* next instruction */
1398 env->pc = env->npc;
1399 env->npc = env->npc + 4;
1400 break;
1401 case 0x83: /* flush windows */
992f48a0
BS		 1402#ifdef TARGET_ABI32
1403 case 0x103:
1404#endif
2623cbaf 1405 flush_windows(env);
060366c5
FB		 1406 /* next instruction */
1407 env->pc = env->npc;
1408 env->npc = env->npc + 4;
1409 break;
3475187d 1410#ifndef TARGET_SPARC64
060366c5
FB		 1411 case TT_WIN_OVF: /* window overflow */
1412 save_window(env);
1413 break;
1414 case TT_WIN_UNF: /* window underflow */
1415 restore_window(env);
1416 break;
61ff6f58
FB		 1417 case TT_TFAULT:
1418 case TT_DFAULT:
1419 {
59f7182f 1420 info.si_signo = TARGET_SIGSEGV;
61ff6f58
FB		 1421 info.si_errno = 0;
1422 /* XXX: check env->error_code */
1423 info.si_code = TARGET_SEGV_MAPERR;
1424 info._sifields._sigfault._addr = env->mmuregs[4];
624f7979 1425 queue_signal(env, info.si_signo, &info);
61ff6f58
FB		 1426 }
1427 break;
3475187d 1428#else
5ef54116
FB		 1429 case TT_SPILL: /* window overflow */
1430 save_window(env);
1431 break;
1432 case TT_FILL: /* window underflow */
1433 restore_window(env);
1434 break;
7f84a729
BS		 1435 case TT_TFAULT:
1436 case TT_DFAULT:
1437 {
59f7182f 1438 info.si_signo = TARGET_SIGSEGV;
7f84a729
BS		 1439 info.si_errno = 0;
1440 /* XXX: check env->error_code */
1441 info.si_code = TARGET_SEGV_MAPERR;
1442 if (trapnr == TT_DFAULT)
1443 info._sifields._sigfault._addr = env->dmmuregs[4];
1444 else
8194f35a 1445 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
624f7979 1446 queue_signal(env, info.si_signo, &info);
7f84a729
BS		 1447 }
1448 break;
27524dc3 1449#ifndef TARGET_ABI32
5bfb56b2
BS		 1450 case 0x16e:
1451 flush_windows(env);
1452 sparc64_get_context(env);
1453 break;
1454 case 0x16f:
1455 flush_windows(env);
1456 sparc64_set_context(env);
1457 break;
27524dc3 1458#endif
3475187d 1459#endif
48dc41eb
FB		 1460 case EXCP_INTERRUPT:
1461 /* just indicate that signals should be handled asap */
1462 break;
75f22e4e
RH		 1463 case TT_ILL_INSN:
1464 {
1465 info.si_signo = TARGET_SIGILL;
1466 info.si_errno = 0;
1467 info.si_code = TARGET_ILL_ILLOPC;
1468 info._sifields._sigfault._addr = env->pc;
1469 queue_signal(env, info.si_signo, &info);
1470 }
1471 break;
1fddef4b
FB		 1472 case EXCP_DEBUG:
1473 {
1474 int sig;
1475
db6b81d4 1476 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 1477 if (sig)
1478 {
1479 info.si_signo = sig;
1480 info.si_errno = 0;
1481 info.si_code = TARGET_TRAP_BRKPT;
624f7979 1482 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 1483 }
1484 }
1485 break;
060366c5
FB		 1486 default:
1487 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 1488 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 1489 exit(EXIT_FAILURE);
060366c5
FB		 1490 }
1491 process_pending_signals (env);
1492 }
93ac68bc
FB		 1493}
1494
1495#endif
1496
67867308 1497#ifdef TARGET_PPC
05390248 1498static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
9fddaa0c 1499{
4a7428c5 1500 return cpu_get_host_ticks();
9fddaa0c 1501}
3b46e624 1502
05390248 1503uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
9fddaa0c 1504{
e3ea6529 1505 return cpu_ppc_get_tb(env);
9fddaa0c 1506}
3b46e624 1507
05390248 1508uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
9fddaa0c
FB		 1509{
1510 return cpu_ppc_get_tb(env) >> 32;
1511}
3b46e624 1512
05390248 1513uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
9fddaa0c 1514{
b711de95 1515 return cpu_ppc_get_tb(env);
9fddaa0c 1516}
5fafdf24 1517
05390248 1518uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
9fddaa0c 1519{
a062e36c 1520 return cpu_ppc_get_tb(env) >> 32;
9fddaa0c 1521}
76a66253 1522
05390248 1523uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
76a66253
JM		 1524__attribute__ (( alias ("cpu_ppc_load_tbu") ));
1525
05390248 1526uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
9fddaa0c 1527{
76a66253 1528 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
9fddaa0c 1529}
76a66253 1530
a750fc0b 1531/* XXX: to be fixed */
73b01960 1532int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
a750fc0b
JM		 1533{
1534 return -1;
1535}
1536
73b01960 1537int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
a750fc0b
JM		 1538{
1539 return -1;
1540}
1541
56f066bb
NF		 1542static int do_store_exclusive(CPUPPCState *env)
1543{
1544 target_ulong addr;
1545 target_ulong page_addr;
e22c357b 1546 target_ulong val, val2 __attribute__((unused)) = 0;
56f066bb
NF		 1547 int flags;
1548 int segv = 0;
1549
1550 addr = env->reserve_ea;
1551 page_addr = addr & TARGET_PAGE_MASK;
1552 start_exclusive();
1553 mmap_lock();
1554 flags = page_get_flags(page_addr);
1555 if ((flags & PAGE_READ) == 0) {
1556 segv = 1;
1557 } else {
1558 int reg = env->reserve_info & 0x1f;
4b1daa72 1559 int size = env->reserve_info >> 5;
56f066bb
NF		 1560 int stored = 0;
1561
1562 if (addr == env->reserve_addr) {
1563 switch (size) {
1564 case 1: segv = get_user_u8(val, addr); break;
1565 case 2: segv = get_user_u16(val, addr); break;
1566 case 4: segv = get_user_u32(val, addr); break;
1567#if defined(TARGET_PPC64)
1568 case 8: segv = get_user_u64(val, addr); break;
27b95bfe
TM		 1569 case 16: {
1570 segv = get_user_u64(val, addr);
1571 if (!segv) {
1572 segv = get_user_u64(val2, addr + 8);
1573 }
1574 break;
1575 }
56f066bb
NF		 1576#endif
1577 default: abort();
1578 }
1579 if (!segv && val == env->reserve_val) {
1580 val = env->gpr[reg];
1581 switch (size) {
1582 case 1: segv = put_user_u8(val, addr); break;
1583 case 2: segv = put_user_u16(val, addr); break;
1584 case 4: segv = put_user_u32(val, addr); break;
1585#if defined(TARGET_PPC64)
1586 case 8: segv = put_user_u64(val, addr); break;
27b95bfe
TM		 1587 case 16: {
1588 if (val2 == env->reserve_val2) {
e22c357b
DK		 1589 if (msr_le) {
1590 val2 = val;
1591 val = env->gpr[reg+1];
1592 } else {
1593 val2 = env->gpr[reg+1];
1594 }
27b95bfe
TM		 1595 segv = put_user_u64(val, addr);
1596 if (!segv) {
1597 segv = put_user_u64(val2, addr + 8);
1598 }
1599 }
1600 break;
1601 }
56f066bb
NF		 1602#endif
1603 default: abort();
1604 }
1605 if (!segv) {
1606 stored = 1;
1607 }
1608 }
1609 }
1610 env->crf[0] = (stored << 1) | xer_so;
1611 env->reserve_addr = (target_ulong)-1;
1612 }
1613 if (!segv) {
1614 env->nip += 4;
1615 }
1616 mmap_unlock();
1617 end_exclusive();
1618 return segv;
1619}
1620
67867308
FB		 1621void cpu_loop(CPUPPCState *env)
1622{
0315c31c 1623 CPUState *cs = CPU(ppc_env_get_cpu(env));
c227f099 1624 target_siginfo_t info;
61190b14 1625 int trapnr;
9e0e2f96 1626 target_ulong ret;
3b46e624 1627
67867308 1628 for(;;) {
0315c31c 1629 cpu_exec_start(cs);
ea3e9847 1630 trapnr = cpu_ppc_exec(cs);
0315c31c 1631 cpu_exec_end(cs);
67867308 1632 switch(trapnr) {
e1833e1f
JM		 1633 case POWERPC_EXCP_NONE:
1634 /* Just go on */
67867308 1635 break;
e1833e1f 1636 case POWERPC_EXCP_CRITICAL: /* Critical input */
a47dddd7 1637 cpu_abort(cs, "Critical interrupt while in user mode. "
e1833e1f 1638 "Aborting\n");
61190b14 1639 break;
e1833e1f 1640 case POWERPC_EXCP_MCHECK: /* Machine check exception */
a47dddd7 1641 cpu_abort(cs, "Machine check exception while in user mode. "
e1833e1f
JM		 1642 "Aborting\n");
1643 break;
1644 case POWERPC_EXCP_DSI: /* Data storage exception */
90e189ec 1645 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
e1833e1f
JM		 1646 env->spr[SPR_DAR]);
1647 /* XXX: check this. Seems bugged */
2be0071f
FB		 1648 switch (env->error_code & 0xFF000000) {
1649 case 0x40000000:
61190b14
FB		 1650 info.si_signo = TARGET_SIGSEGV;
1651 info.si_errno = 0;
1652 info.si_code = TARGET_SEGV_MAPERR;
1653 break;
2be0071f 1654 case 0x04000000:
61190b14
FB		 1655 info.si_signo = TARGET_SIGILL;
1656 info.si_errno = 0;
1657 info.si_code = TARGET_ILL_ILLADR;
1658 break;
2be0071f 1659 case 0x08000000:
61190b14
FB		 1660 info.si_signo = TARGET_SIGSEGV;
1661 info.si_errno = 0;
1662 info.si_code = TARGET_SEGV_ACCERR;
1663 break;
61190b14
FB		 1664 default:
1665 /* Let's send a regular segfault... */
e1833e1f
JM		 1666 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1667 env->error_code);
61190b14
FB		 1668 info.si_signo = TARGET_SIGSEGV;
1669 info.si_errno = 0;
1670 info.si_code = TARGET_SEGV_MAPERR;
1671 break;
1672 }
67867308 1673 info._sifields._sigfault._addr = env->nip;
624f7979 1674 queue_signal(env, info.si_signo, &info);
67867308 1675 break;
e1833e1f 1676 case POWERPC_EXCP_ISI: /* Instruction storage exception */
90e189ec
BS		 1677 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1678 "\n", env->spr[SPR_SRR0]);
e1833e1f 1679 /* XXX: check this */
2be0071f
FB		 1680 switch (env->error_code & 0xFF000000) {
1681 case 0x40000000:
61190b14 1682 info.si_signo = TARGET_SIGSEGV;
67867308 1683 info.si_errno = 0;
61190b14
FB		 1684 info.si_code = TARGET_SEGV_MAPERR;
1685 break;
2be0071f
FB		 1686 case 0x10000000:
1687 case 0x08000000:
61190b14
FB		 1688 info.si_signo = TARGET_SIGSEGV;
1689 info.si_errno = 0;
1690 info.si_code = TARGET_SEGV_ACCERR;
1691 break;
1692 default:
1693 /* Let's send a regular segfault... */
e1833e1f
JM		 1694 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1695 env->error_code);
61190b14
FB		 1696 info.si_signo = TARGET_SIGSEGV;
1697 info.si_errno = 0;
1698 info.si_code = TARGET_SEGV_MAPERR;
1699 break;
1700 }
1701 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1702 queue_signal(env, info.si_signo, &info);
67867308 1703 break;
e1833e1f 1704 case POWERPC_EXCP_EXTERNAL: /* External input */
a47dddd7 1705 cpu_abort(cs, "External interrupt while in user mode. "
e1833e1f
JM		 1706 "Aborting\n");
1707 break;
1708 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1709 EXCP_DUMP(env, "Unaligned memory access\n");
1710 /* XXX: check this */
61190b14 1711 info.si_signo = TARGET_SIGBUS;
67867308 1712 info.si_errno = 0;
61190b14 1713 info.si_code = TARGET_BUS_ADRALN;
6bb9a0a9 1714 info._sifields._sigfault._addr = env->nip;
624f7979 1715 queue_signal(env, info.si_signo, &info);
67867308 1716 break;
e1833e1f
JM		 1717 case POWERPC_EXCP_PROGRAM: /* Program exception */
1718 /* XXX: check this */
61190b14 1719 switch (env->error_code & ~0xF) {
e1833e1f
JM		 1720 case POWERPC_EXCP_FP:
1721 EXCP_DUMP(env, "Floating point program exception\n");
61190b14
FB		 1722 info.si_signo = TARGET_SIGFPE;
1723 info.si_errno = 0;
1724 switch (env->error_code & 0xF) {
e1833e1f 1725 case POWERPC_EXCP_FP_OX:
61190b14
FB		 1726 info.si_code = TARGET_FPE_FLTOVF;
1727 break;
e1833e1f 1728 case POWERPC_EXCP_FP_UX:
61190b14
FB		 1729 info.si_code = TARGET_FPE_FLTUND;
1730 break;
e1833e1f
JM		 1731 case POWERPC_EXCP_FP_ZX:
1732 case POWERPC_EXCP_FP_VXZDZ:
61190b14
FB		 1733 info.si_code = TARGET_FPE_FLTDIV;
1734 break;
e1833e1f 1735 case POWERPC_EXCP_FP_XX:
61190b14
FB		 1736 info.si_code = TARGET_FPE_FLTRES;
1737 break;
e1833e1f 1738 case POWERPC_EXCP_FP_VXSOFT:
61190b14
FB		 1739 info.si_code = TARGET_FPE_FLTINV;
1740 break;
7c58044c 1741 case POWERPC_EXCP_FP_VXSNAN:
e1833e1f
JM		 1742 case POWERPC_EXCP_FP_VXISI:
1743 case POWERPC_EXCP_FP_VXIDI:
1744 case POWERPC_EXCP_FP_VXIMZ:
1745 case POWERPC_EXCP_FP_VXVC:
1746 case POWERPC_EXCP_FP_VXSQRT:
1747 case POWERPC_EXCP_FP_VXCVI:
61190b14
FB		 1748 info.si_code = TARGET_FPE_FLTSUB;
1749 break;
1750 default:
e1833e1f
JM		 1751 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1752 env->error_code);
1753 break;
61190b14 1754 }
e1833e1f
JM		 1755 break;
1756 case POWERPC_EXCP_INVAL:
1757 EXCP_DUMP(env, "Invalid instruction\n");
61190b14
FB		 1758 info.si_signo = TARGET_SIGILL;
1759 info.si_errno = 0;
1760 switch (env->error_code & 0xF) {
e1833e1f 1761 case POWERPC_EXCP_INVAL_INVAL:
61190b14
FB		 1762 info.si_code = TARGET_ILL_ILLOPC;
1763 break;
e1833e1f 1764 case POWERPC_EXCP_INVAL_LSWX:
a750fc0b 1765 info.si_code = TARGET_ILL_ILLOPN;
61190b14 1766 break;
e1833e1f 1767 case POWERPC_EXCP_INVAL_SPR:
61190b14
FB		 1768 info.si_code = TARGET_ILL_PRVREG;
1769 break;
e1833e1f 1770 case POWERPC_EXCP_INVAL_FP:
61190b14
FB		 1771 info.si_code = TARGET_ILL_COPROC;
1772 break;
1773 default:
e1833e1f
JM		 1774 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1775 env->error_code & 0xF);
61190b14
FB		 1776 info.si_code = TARGET_ILL_ILLADR;
1777 break;
1778 }
1779 break;
e1833e1f
JM		 1780 case POWERPC_EXCP_PRIV:
1781 EXCP_DUMP(env, "Privilege violation\n");
61190b14
FB		 1782 info.si_signo = TARGET_SIGILL;
1783 info.si_errno = 0;
1784 switch (env->error_code & 0xF) {
e1833e1f 1785 case POWERPC_EXCP_PRIV_OPC:
61190b14
FB		 1786 info.si_code = TARGET_ILL_PRVOPC;
1787 break;
e1833e1f 1788 case POWERPC_EXCP_PRIV_REG:
61190b14 1789 info.si_code = TARGET_ILL_PRVREG;
e1833e1f 1790 break;
61190b14 1791 default:
e1833e1f
JM		 1792 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1793 env->error_code & 0xF);
61190b14
FB		 1794 info.si_code = TARGET_ILL_PRVOPC;
1795 break;
1796 }
1797 break;
e1833e1f 1798 case POWERPC_EXCP_TRAP:
a47dddd7 1799 cpu_abort(cs, "Tried to call a TRAP\n");
e1833e1f 1800 break;
61190b14
FB		 1801 default:
1802 /* Should not happen ! */
a47dddd7 1803 cpu_abort(cs, "Unknown program exception (%02x)\n",
e1833e1f
JM		 1804 env->error_code);
1805 break;
61190b14
FB		 1806 }
1807 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1808 queue_signal(env, info.si_signo, &info);
67867308 1809 break;
e1833e1f
JM		 1810 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1811 EXCP_DUMP(env, "No floating point allowed\n");
61190b14 1812 info.si_signo = TARGET_SIGILL;
67867308 1813 info.si_errno = 0;
61190b14
FB		 1814 info.si_code = TARGET_ILL_COPROC;
1815 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1816 queue_signal(env, info.si_signo, &info);
67867308 1817 break;
e1833e1f 1818 case POWERPC_EXCP_SYSCALL: /* System call exception */
a47dddd7 1819 cpu_abort(cs, "Syscall exception while in user mode. "
e1833e1f 1820 "Aborting\n");
61190b14 1821 break;
e1833e1f
JM		 1822 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1823 EXCP_DUMP(env, "No APU instruction allowed\n");
1824 info.si_signo = TARGET_SIGILL;
1825 info.si_errno = 0;
1826 info.si_code = TARGET_ILL_COPROC;
1827 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1828 queue_signal(env, info.si_signo, &info);
61190b14 1829 break;
e1833e1f 1830 case POWERPC_EXCP_DECR: /* Decrementer exception */
a47dddd7 1831 cpu_abort(cs, "Decrementer interrupt while in user mode. "
e1833e1f 1832 "Aborting\n");
61190b14 1833 break;
e1833e1f 1834 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
a47dddd7 1835 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
e1833e1f
JM		 1836 "Aborting\n");
1837 break;
1838 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
a47dddd7 1839 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
e1833e1f
JM		 1840 "Aborting\n");
1841 break;
1842 case POWERPC_EXCP_DTLB: /* Data TLB error */
a47dddd7 1843 cpu_abort(cs, "Data TLB exception while in user mode. "
e1833e1f
JM		 1844 "Aborting\n");
1845 break;
1846 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
a47dddd7 1847 cpu_abort(cs, "Instruction TLB exception while in user mode. "
e1833e1f
JM		 1848 "Aborting\n");
1849 break;
e1833e1f
JM		 1850 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1851 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1852 info.si_signo = TARGET_SIGILL;
1853 info.si_errno = 0;
1854 info.si_code = TARGET_ILL_COPROC;
1855 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1856 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1857 break;
1858 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
a47dddd7 1859 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
e1833e1f
JM		 1860 break;
1861 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
a47dddd7 1862 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
e1833e1f
JM		 1863 break;
1864 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
a47dddd7 1865 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1866 break;
1867 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
a47dddd7 1868 cpu_abort(cs, "Doorbell interrupt while in user mode. "
e1833e1f
JM		 1869 "Aborting\n");
1870 break;
1871 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
a47dddd7 1872 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
e1833e1f
JM		 1873 "Aborting\n");
1874 break;
1875 case POWERPC_EXCP_RESET: /* System reset exception */
a47dddd7 1876 cpu_abort(cs, "Reset interrupt while in user mode. "
e1833e1f
JM		 1877 "Aborting\n");
1878 break;
e1833e1f 1879 case POWERPC_EXCP_DSEG: /* Data segment exception */
a47dddd7 1880 cpu_abort(cs, "Data segment exception while in user mode. "
e1833e1f
JM		 1881 "Aborting\n");
1882 break;
1883 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
a47dddd7 1884 cpu_abort(cs, "Instruction segment exception "
e1833e1f
JM		 1885 "while in user mode. Aborting\n");
1886 break;
e85e7c6e 1887 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1888 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
a47dddd7 1889 cpu_abort(cs, "Hypervisor decrementer interrupt "
e1833e1f
JM		 1890 "while in user mode. Aborting\n");
1891 break;
e1833e1f
JM		 1892 case POWERPC_EXCP_TRACE: /* Trace exception */
1893 /* Nothing to do:
1894 * we use this exception to emulate step-by-step execution mode.
1895 */
1896 break;
e85e7c6e 1897 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1898 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
a47dddd7 1899 cpu_abort(cs, "Hypervisor data storage exception "
e1833e1f
JM		 1900 "while in user mode. Aborting\n");
1901 break;
1902 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
a47dddd7 1903 cpu_abort(cs, "Hypervisor instruction storage exception "
e1833e1f
JM		 1904 "while in user mode. Aborting\n");
1905 break;
1906 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
a47dddd7 1907 cpu_abort(cs, "Hypervisor data segment exception "
e1833e1f
JM		 1908 "while in user mode. Aborting\n");
1909 break;
1910 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
a47dddd7 1911 cpu_abort(cs, "Hypervisor instruction segment exception "
e1833e1f
JM		 1912 "while in user mode. Aborting\n");
1913 break;
e1833e1f
JM		 1914 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1915 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1916 info.si_signo = TARGET_SIGILL;
1917 info.si_errno = 0;
1918 info.si_code = TARGET_ILL_COPROC;
1919 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1920 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1921 break;
1922 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
a47dddd7 1923 cpu_abort(cs, "Programmable interval timer interrupt "
e1833e1f
JM		 1924 "while in user mode. Aborting\n");
1925 break;
1926 case POWERPC_EXCP_IO: /* IO error exception */
a47dddd7 1927 cpu_abort(cs, "IO error exception while in user mode. "
e1833e1f
JM		 1928 "Aborting\n");
1929 break;
1930 case POWERPC_EXCP_RUNM: /* Run mode exception */
a47dddd7 1931 cpu_abort(cs, "Run mode exception while in user mode. "
e1833e1f
JM		 1932 "Aborting\n");
1933 break;
1934 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
a47dddd7 1935 cpu_abort(cs, "Emulation trap exception not handled\n");
e1833e1f
JM		 1936 break;
1937 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
a47dddd7 1938 cpu_abort(cs, "Instruction fetch TLB exception "
e1833e1f
JM		 1939 "while in user-mode. Aborting");
1940 break;
1941 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
a47dddd7 1942 cpu_abort(cs, "Data load TLB exception while in user-mode. "
e1833e1f
JM		 1943 "Aborting");
1944 break;
1945 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
a47dddd7 1946 cpu_abort(cs, "Data store TLB exception while in user-mode. "
e1833e1f
JM		 1947 "Aborting");
1948 break;
1949 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
a47dddd7 1950 cpu_abort(cs, "Floating-point assist exception not handled\n");
e1833e1f
JM		 1951 break;
1952 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
a47dddd7 1953 cpu_abort(cs, "Instruction address breakpoint exception "
e1833e1f
JM		 1954 "not handled\n");
1955 break;
1956 case POWERPC_EXCP_SMI: /* System management interrupt */
a47dddd7 1957 cpu_abort(cs, "System management interrupt while in user mode. "
e1833e1f
JM		 1958 "Aborting\n");
1959 break;
1960 case POWERPC_EXCP_THERM: /* Thermal interrupt */
a47dddd7 1961 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
e1833e1f
JM		 1962 "Aborting\n");
1963 break;
1964 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
a47dddd7 1965 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1966 break;
1967 case POWERPC_EXCP_VPUA: /* Vector assist exception */
a47dddd7 1968 cpu_abort(cs, "Vector assist exception not handled\n");
e1833e1f
JM		 1969 break;
1970 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
a47dddd7 1971 cpu_abort(cs, "Soft patch exception not handled\n");
e1833e1f
JM		 1972 break;
1973 case POWERPC_EXCP_MAINT: /* Maintenance exception */
a47dddd7 1974 cpu_abort(cs, "Maintenance exception while in user mode. "
e1833e1f
JM		 1975 "Aborting\n");
1976 break;
1977 case POWERPC_EXCP_STOP: /* stop translation */
1978 /* We did invalidate the instruction cache. Go on */
1979 break;
1980 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1981 /* We just stopped because of a branch. Go on */
1982 break;
1983 case POWERPC_EXCP_SYSCALL_USER:
1984 /* system call in user-mode emulation */
1985 /* WARNING:
1986 * PPC ABI uses overflow flag in cr0 to signal an error
1987 * in syscalls.
1988 */
e1833e1f
JM		 1989 env->crf[0] &= ~0x1;
1990 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1991 env->gpr[5], env->gpr[6], env->gpr[7],
5945cfcb 1992 env->gpr[8], 0, 0);
6db9d00e
TB		 1993 if (ret == -TARGET_ERESTARTSYS) {
1994 env->nip -= 4;
1995 break;
1996 }
9e0e2f96 1997 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
bcd4933a
NF		 1998 /* Returning from a successful sigreturn syscall.
1999 Avoid corrupting register state. */
2000 break;
2001 }
9e0e2f96 2002 if (ret > (target_ulong)(-515)) {
e1833e1f
JM		 2003 env->crf[0] |= 0x1;
2004 ret = -ret;
61190b14 2005 }
e1833e1f 2006 env->gpr[3] = ret;
e1833e1f 2007 break;
56f066bb
NF		 2008 case POWERPC_EXCP_STCX:
2009 if (do_store_exclusive(env)) {
2010 info.si_signo = TARGET_SIGSEGV;
2011 info.si_errno = 0;
2012 info.si_code = TARGET_SEGV_MAPERR;
2013 info._sifields._sigfault._addr = env->nip;
2014 queue_signal(env, info.si_signo, &info);
2015 }
2016 break;
71f75756
AJ		 2017 case EXCP_DEBUG:
2018 {
2019 int sig;
2020
db6b81d4 2021 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
71f75756
AJ		 2022 if (sig) {
2023 info.si_signo = sig;
2024 info.si_errno = 0;
2025 info.si_code = TARGET_TRAP_BRKPT;
2026 queue_signal(env, info.si_signo, &info);
2027 }
2028 }
2029 break;
56ba31ff
JM		 2030 case EXCP_INTERRUPT:
2031 /* just indicate that signals should be handled asap */
2032 break;
e1833e1f 2033 default:
a47dddd7 2034 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
e1833e1f 2035 break;
67867308
FB		 2036 }
2037 process_pending_signals(env);
2038 }
2039}
2040#endif
2041
048f6b4d
FB		 2042#ifdef TARGET_MIPS
2043
ff4f7382
RH		 2044# ifdef TARGET_ABI_MIPSO32
2045# define MIPS_SYS(name, args) args,
048f6b4d 2046static const uint8_t mips_syscall_args[] = {
29fb0f25 2047 MIPS_SYS(sys_syscall , 8) /* 4000 */
048f6b4d
FB		 2048 MIPS_SYS(sys_exit , 1)
2049 MIPS_SYS(sys_fork , 0)
2050 MIPS_SYS(sys_read , 3)
2051 MIPS_SYS(sys_write , 3)
2052 MIPS_SYS(sys_open , 3) /* 4005 */
2053 MIPS_SYS(sys_close , 1)
2054 MIPS_SYS(sys_waitpid , 3)
2055 MIPS_SYS(sys_creat , 2)
2056 MIPS_SYS(sys_link , 2)
2057 MIPS_SYS(sys_unlink , 1) /* 4010 */
2058 MIPS_SYS(sys_execve , 0)
2059 MIPS_SYS(sys_chdir , 1)
2060 MIPS_SYS(sys_time , 1)
2061 MIPS_SYS(sys_mknod , 3)
2062 MIPS_SYS(sys_chmod , 2) /* 4015 */
2063 MIPS_SYS(sys_lchown , 3)
2064 MIPS_SYS(sys_ni_syscall , 0)
2065 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2066 MIPS_SYS(sys_lseek , 3)
2067 MIPS_SYS(sys_getpid , 0) /* 4020 */
2068 MIPS_SYS(sys_mount , 5)
868e34d7 2069 MIPS_SYS(sys_umount , 1)
048f6b4d
FB		 2070 MIPS_SYS(sys_setuid , 1)
2071 MIPS_SYS(sys_getuid , 0)
2072 MIPS_SYS(sys_stime , 1) /* 4025 */
2073 MIPS_SYS(sys_ptrace , 4)
2074 MIPS_SYS(sys_alarm , 1)
2075 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2076 MIPS_SYS(sys_pause , 0)
2077 MIPS_SYS(sys_utime , 2) /* 4030 */
2078 MIPS_SYS(sys_ni_syscall , 0)
2079 MIPS_SYS(sys_ni_syscall , 0)
2080 MIPS_SYS(sys_access , 2)
2081 MIPS_SYS(sys_nice , 1)
2082 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2083 MIPS_SYS(sys_sync , 0)
2084 MIPS_SYS(sys_kill , 2)
2085 MIPS_SYS(sys_rename , 2)
2086 MIPS_SYS(sys_mkdir , 2)
2087 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2088 MIPS_SYS(sys_dup , 1)
2089 MIPS_SYS(sys_pipe , 0)
2090 MIPS_SYS(sys_times , 1)
2091 MIPS_SYS(sys_ni_syscall , 0)
2092 MIPS_SYS(sys_brk , 1) /* 4045 */
2093 MIPS_SYS(sys_setgid , 1)
2094 MIPS_SYS(sys_getgid , 0)
2095 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2096 MIPS_SYS(sys_geteuid , 0)
2097 MIPS_SYS(sys_getegid , 0) /* 4050 */
2098 MIPS_SYS(sys_acct , 0)
868e34d7 2099 MIPS_SYS(sys_umount2 , 2)
048f6b4d
FB		 2100 MIPS_SYS(sys_ni_syscall , 0)
2101 MIPS_SYS(sys_ioctl , 3)
2102 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2103 MIPS_SYS(sys_ni_syscall , 2)
2104 MIPS_SYS(sys_setpgid , 2)
2105 MIPS_SYS(sys_ni_syscall , 0)
2106 MIPS_SYS(sys_olduname , 1)
2107 MIPS_SYS(sys_umask , 1) /* 4060 */
2108 MIPS_SYS(sys_chroot , 1)
2109 MIPS_SYS(sys_ustat , 2)
2110 MIPS_SYS(sys_dup2 , 2)
2111 MIPS_SYS(sys_getppid , 0)
2112 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2113 MIPS_SYS(sys_setsid , 0)
2114 MIPS_SYS(sys_sigaction , 3)
2115 MIPS_SYS(sys_sgetmask , 0)
2116 MIPS_SYS(sys_ssetmask , 1)
2117 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2118 MIPS_SYS(sys_setregid , 2)
2119 MIPS_SYS(sys_sigsuspend , 0)
2120 MIPS_SYS(sys_sigpending , 1)
2121 MIPS_SYS(sys_sethostname , 2)
2122 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2123 MIPS_SYS(sys_getrlimit , 2)
2124 MIPS_SYS(sys_getrusage , 2)
2125 MIPS_SYS(sys_gettimeofday, 2)
2126 MIPS_SYS(sys_settimeofday, 2)
2127 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2128 MIPS_SYS(sys_setgroups , 2)
2129 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2130 MIPS_SYS(sys_symlink , 2)
2131 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2132 MIPS_SYS(sys_readlink , 3) /* 4085 */
2133 MIPS_SYS(sys_uselib , 1)
2134 MIPS_SYS(sys_swapon , 2)
2135 MIPS_SYS(sys_reboot , 3)
2136 MIPS_SYS(old_readdir , 3)
2137 MIPS_SYS(old_mmap , 6) /* 4090 */
2138 MIPS_SYS(sys_munmap , 2)
2139 MIPS_SYS(sys_truncate , 2)
2140 MIPS_SYS(sys_ftruncate , 2)
2141 MIPS_SYS(sys_fchmod , 2)
2142 MIPS_SYS(sys_fchown , 3) /* 4095 */
2143 MIPS_SYS(sys_getpriority , 2)
2144 MIPS_SYS(sys_setpriority , 3)
2145 MIPS_SYS(sys_ni_syscall , 0)
2146 MIPS_SYS(sys_statfs , 2)
2147 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2148 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2149 MIPS_SYS(sys_socketcall , 2)
2150 MIPS_SYS(sys_syslog , 3)
2151 MIPS_SYS(sys_setitimer , 3)
2152 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2153 MIPS_SYS(sys_newstat , 2)
2154 MIPS_SYS(sys_newlstat , 2)
2155 MIPS_SYS(sys_newfstat , 2)
2156 MIPS_SYS(sys_uname , 1)
2157 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2158 MIPS_SYS(sys_vhangup , 0)
2159 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2160 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2161 MIPS_SYS(sys_wait4 , 4)
2162 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2163 MIPS_SYS(sys_sysinfo , 1)
2164 MIPS_SYS(sys_ipc , 6)
2165 MIPS_SYS(sys_fsync , 1)
2166 MIPS_SYS(sys_sigreturn , 0)
18113962 2167 MIPS_SYS(sys_clone , 6) /* 4120 */
048f6b4d
FB		 2168 MIPS_SYS(sys_setdomainname, 2)
2169 MIPS_SYS(sys_newuname , 1)
2170 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2171 MIPS_SYS(sys_adjtimex , 1)
2172 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2173 MIPS_SYS(sys_sigprocmask , 3)
2174 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2175 MIPS_SYS(sys_init_module , 5)
2176 MIPS_SYS(sys_delete_module, 1)
2177 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2178 MIPS_SYS(sys_quotactl , 0)
2179 MIPS_SYS(sys_getpgid , 1)
2180 MIPS_SYS(sys_fchdir , 1)
2181 MIPS_SYS(sys_bdflush , 2)
2182 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2183 MIPS_SYS(sys_personality , 1)
2184 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2185 MIPS_SYS(sys_setfsuid , 1)
2186 MIPS_SYS(sys_setfsgid , 1)
2187 MIPS_SYS(sys_llseek , 5) /* 4140 */
2188 MIPS_SYS(sys_getdents , 3)
2189 MIPS_SYS(sys_select , 5)
2190 MIPS_SYS(sys_flock , 2)
2191 MIPS_SYS(sys_msync , 3)
2192 MIPS_SYS(sys_readv , 3) /* 4145 */
2193 MIPS_SYS(sys_writev , 3)
2194 MIPS_SYS(sys_cacheflush , 3)
2195 MIPS_SYS(sys_cachectl , 3)
2196 MIPS_SYS(sys_sysmips , 4)
2197 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2198 MIPS_SYS(sys_getsid , 1)
2199 MIPS_SYS(sys_fdatasync , 0)
2200 MIPS_SYS(sys_sysctl , 1)
2201 MIPS_SYS(sys_mlock , 2)
2202 MIPS_SYS(sys_munlock , 2) /* 4155 */
2203 MIPS_SYS(sys_mlockall , 1)
2204 MIPS_SYS(sys_munlockall , 0)
2205 MIPS_SYS(sys_sched_setparam, 2)
2206 MIPS_SYS(sys_sched_getparam, 2)
2207 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2208 MIPS_SYS(sys_sched_getscheduler, 1)
2209 MIPS_SYS(sys_sched_yield , 0)
2210 MIPS_SYS(sys_sched_get_priority_max, 1)
2211 MIPS_SYS(sys_sched_get_priority_min, 1)
2212 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2213 MIPS_SYS(sys_nanosleep, 2)
b0932e06 2214 MIPS_SYS(sys_mremap , 5)
048f6b4d
FB		 2215 MIPS_SYS(sys_accept , 3)
2216 MIPS_SYS(sys_bind , 3)
2217 MIPS_SYS(sys_connect , 3) /* 4170 */
2218 MIPS_SYS(sys_getpeername , 3)
2219 MIPS_SYS(sys_getsockname , 3)
2220 MIPS_SYS(sys_getsockopt , 5)
2221 MIPS_SYS(sys_listen , 2)
2222 MIPS_SYS(sys_recv , 4) /* 4175 */
2223 MIPS_SYS(sys_recvfrom , 6)
2224 MIPS_SYS(sys_recvmsg , 3)
2225 MIPS_SYS(sys_send , 4)
2226 MIPS_SYS(sys_sendmsg , 3)
2227 MIPS_SYS(sys_sendto , 6) /* 4180 */
2228 MIPS_SYS(sys_setsockopt , 5)
2229 MIPS_SYS(sys_shutdown , 2)
2230 MIPS_SYS(sys_socket , 3)
2231 MIPS_SYS(sys_socketpair , 4)
2232 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2233 MIPS_SYS(sys_getresuid , 3)
2234 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2235 MIPS_SYS(sys_poll , 3)
2236 MIPS_SYS(sys_nfsservctl , 3)
2237 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2238 MIPS_SYS(sys_getresgid , 3)
2239 MIPS_SYS(sys_prctl , 5)
2240 MIPS_SYS(sys_rt_sigreturn, 0)
2241 MIPS_SYS(sys_rt_sigaction, 4)
2242 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2243 MIPS_SYS(sys_rt_sigpending, 2)
2244 MIPS_SYS(sys_rt_sigtimedwait, 4)
2245 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2246 MIPS_SYS(sys_rt_sigsuspend, 0)
2247 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2248 MIPS_SYS(sys_pwrite64 , 6)
2249 MIPS_SYS(sys_chown , 3)
2250 MIPS_SYS(sys_getcwd , 2)
2251 MIPS_SYS(sys_capget , 2)
2252 MIPS_SYS(sys_capset , 2) /* 4205 */
053ebb27 2253 MIPS_SYS(sys_sigaltstack , 2)
048f6b4d
FB		 2254 MIPS_SYS(sys_sendfile , 4)
2255 MIPS_SYS(sys_ni_syscall , 0)
2256 MIPS_SYS(sys_ni_syscall , 0)
2257 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2258 MIPS_SYS(sys_truncate64 , 4)
2259 MIPS_SYS(sys_ftruncate64 , 4)
2260 MIPS_SYS(sys_stat64 , 2)
2261 MIPS_SYS(sys_lstat64 , 2)
2262 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2263 MIPS_SYS(sys_pivot_root , 2)
2264 MIPS_SYS(sys_mincore , 3)
2265 MIPS_SYS(sys_madvise , 3)
2266 MIPS_SYS(sys_getdents64 , 3)
2267 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2268 MIPS_SYS(sys_ni_syscall , 0)
2269 MIPS_SYS(sys_gettid , 0)
2270 MIPS_SYS(sys_readahead , 5)
2271 MIPS_SYS(sys_setxattr , 5)
2272 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2273 MIPS_SYS(sys_fsetxattr , 5)
2274 MIPS_SYS(sys_getxattr , 4)
2275 MIPS_SYS(sys_lgetxattr , 4)
2276 MIPS_SYS(sys_fgetxattr , 4)
2277 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2278 MIPS_SYS(sys_llistxattr , 3)
2279 MIPS_SYS(sys_flistxattr , 3)
2280 MIPS_SYS(sys_removexattr , 2)
2281 MIPS_SYS(sys_lremovexattr, 2)
2282 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2283 MIPS_SYS(sys_tkill , 2)
2284 MIPS_SYS(sys_sendfile64 , 5)
43be1343 2285 MIPS_SYS(sys_futex , 6)
048f6b4d
FB		 2286 MIPS_SYS(sys_sched_setaffinity, 3)
2287 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2288 MIPS_SYS(sys_io_setup , 2)
2289 MIPS_SYS(sys_io_destroy , 1)
2290 MIPS_SYS(sys_io_getevents, 5)
2291 MIPS_SYS(sys_io_submit , 3)
2292 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2293 MIPS_SYS(sys_exit_group , 1)
2294 MIPS_SYS(sys_lookup_dcookie, 3)
2295 MIPS_SYS(sys_epoll_create, 1)
2296 MIPS_SYS(sys_epoll_ctl , 4)
2297 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2298 MIPS_SYS(sys_remap_file_pages, 5)
2299 MIPS_SYS(sys_set_tid_address, 1)
2300 MIPS_SYS(sys_restart_syscall, 0)
2301 MIPS_SYS(sys_fadvise64_64, 7)
2302 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2303 MIPS_SYS(sys_fstatfs64 , 2)
2304 MIPS_SYS(sys_timer_create, 3)
2305 MIPS_SYS(sys_timer_settime, 4)
2306 MIPS_SYS(sys_timer_gettime, 2)
2307 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2308 MIPS_SYS(sys_timer_delete, 1)
2309 MIPS_SYS(sys_clock_settime, 2)
2310 MIPS_SYS(sys_clock_gettime, 2)
2311 MIPS_SYS(sys_clock_getres, 2)
2312 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2313 MIPS_SYS(sys_tgkill , 3)
2314 MIPS_SYS(sys_utimes , 2)
2315 MIPS_SYS(sys_mbind , 4)
2316 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2317 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2318 MIPS_SYS(sys_mq_open , 4)
2319 MIPS_SYS(sys_mq_unlink , 1)
2320 MIPS_SYS(sys_mq_timedsend, 5)
2321 MIPS_SYS(sys_mq_timedreceive, 5)
2322 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2323 MIPS_SYS(sys_mq_getsetattr, 3)
2324 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2325 MIPS_SYS(sys_waitid , 4)
2326 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2327 MIPS_SYS(sys_add_key , 5)
388bb21a 2328 MIPS_SYS(sys_request_key, 4)
048f6b4d 2329 MIPS_SYS(sys_keyctl , 5)
6f5b89a0 2330 MIPS_SYS(sys_set_thread_area, 1)
388bb21a
TS		 2331 MIPS_SYS(sys_inotify_init, 0)
2332 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2333 MIPS_SYS(sys_inotify_rm_watch, 2)
2334 MIPS_SYS(sys_migrate_pages, 4)
2335 MIPS_SYS(sys_openat, 4)
2336 MIPS_SYS(sys_mkdirat, 3)
2337 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2338 MIPS_SYS(sys_fchownat, 5)
2339 MIPS_SYS(sys_futimesat, 3)
2340 MIPS_SYS(sys_fstatat64, 4)
2341 MIPS_SYS(sys_unlinkat, 3)
2342 MIPS_SYS(sys_renameat, 4) /* 4295 */
2343 MIPS_SYS(sys_linkat, 5)
2344 MIPS_SYS(sys_symlinkat, 3)
2345 MIPS_SYS(sys_readlinkat, 4)
2346 MIPS_SYS(sys_fchmodat, 3)
2347 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2348 MIPS_SYS(sys_pselect6, 6)
2349 MIPS_SYS(sys_ppoll, 5)
2350 MIPS_SYS(sys_unshare, 1)
b0932e06 2351 MIPS_SYS(sys_splice, 6)
388bb21a
TS		 2352 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2353 MIPS_SYS(sys_tee, 4)
2354 MIPS_SYS(sys_vmsplice, 4)
2355 MIPS_SYS(sys_move_pages, 6)
2356 MIPS_SYS(sys_set_robust_list, 2)
2357 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2358 MIPS_SYS(sys_kexec_load, 4)
2359 MIPS_SYS(sys_getcpu, 3)
2360 MIPS_SYS(sys_epoll_pwait, 6)
2361 MIPS_SYS(sys_ioprio_set, 3)
2362 MIPS_SYS(sys_ioprio_get, 2)
d979e8eb
PM		 2363 MIPS_SYS(sys_utimensat, 4)
2364 MIPS_SYS(sys_signalfd, 3)
2365 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2366 MIPS_SYS(sys_eventfd, 1)
2367 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2368 MIPS_SYS(sys_timerfd_create, 2)
2369 MIPS_SYS(sys_timerfd_gettime, 2)
2370 MIPS_SYS(sys_timerfd_settime, 4)
2371 MIPS_SYS(sys_signalfd4, 4)
2372 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2373 MIPS_SYS(sys_epoll_create1, 1)
2374 MIPS_SYS(sys_dup3, 3)
2375 MIPS_SYS(sys_pipe2, 2)
2376 MIPS_SYS(sys_inotify_init1, 1)
2377 MIPS_SYS(sys_preadv, 6) /* 4330 */
2378 MIPS_SYS(sys_pwritev, 6)
2379 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2380 MIPS_SYS(sys_perf_event_open, 5)
2381 MIPS_SYS(sys_accept4, 4)
2382 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2383 MIPS_SYS(sys_fanotify_init, 2)
2384 MIPS_SYS(sys_fanotify_mark, 6)
2385 MIPS_SYS(sys_prlimit64, 4)
2386 MIPS_SYS(sys_name_to_handle_at, 5)
2387 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2388 MIPS_SYS(sys_clock_adjtime, 2)
2389 MIPS_SYS(sys_syncfs, 1)
048f6b4d 2390};
ff4f7382
RH		 2391# undef MIPS_SYS
2392# endif /* O32 */
048f6b4d 2393
590bc601
PB		 2394static int do_store_exclusive(CPUMIPSState *env)
2395{
2396 target_ulong addr;
2397 target_ulong page_addr;
2398 target_ulong val;
2399 int flags;
2400 int segv = 0;
2401 int reg;
2402 int d;
2403
5499b6ff 2404 addr = env->lladdr;
590bc601
PB		 2405 page_addr = addr & TARGET_PAGE_MASK;
2406 start_exclusive();
2407 mmap_lock();
2408 flags = page_get_flags(page_addr);
2409 if ((flags & PAGE_READ) == 0) {
2410 segv = 1;
2411 } else {
2412 reg = env->llreg & 0x1f;
2413 d = (env->llreg & 0x20) != 0;
2414 if (d) {
2415 segv = get_user_s64(val, addr);
2416 } else {
2417 segv = get_user_s32(val, addr);
2418 }
2419 if (!segv) {
2420 if (val != env->llval) {
2421 env->active_tc.gpr[reg] = 0;
2422 } else {
2423 if (d) {
2424 segv = put_user_u64(env->llnewval, addr);
2425 } else {
2426 segv = put_user_u32(env->llnewval, addr);
2427 }
2428 if (!segv) {
2429 env->active_tc.gpr[reg] = 1;
2430 }
2431 }
2432 }
2433 }
5499b6ff 2434 env->lladdr = -1;
590bc601
PB		 2435 if (!segv) {
2436 env->active_tc.PC += 4;
2437 }
2438 mmap_unlock();
2439 end_exclusive();
2440 return segv;
2441}
2442
54b2f42c
MI		 2443/* Break codes */
2444enum {
2445 BRK_OVERFLOW = 6,
2446 BRK_DIVZERO = 7
2447};
2448
2449static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2450 unsigned int code)
2451{
2452 int ret = -1;
2453
2454 switch (code) {
2455 case BRK_OVERFLOW:
2456 case BRK_DIVZERO:
2457 info->si_signo = TARGET_SIGFPE;
2458 info->si_errno = 0;
2459 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2460 queue_signal(env, info->si_signo, &*info);
2461 ret = 0;
2462 break;
2463 default:
b51910ba
PJ		 2464 info->si_signo = TARGET_SIGTRAP;
2465 info->si_errno = 0;
2466 queue_signal(env, info->si_signo, &*info);
2467 ret = 0;
54b2f42c
MI		 2468 break;
2469 }
2470
2471 return ret;
2472}
2473
048f6b4d
FB		 2474void cpu_loop(CPUMIPSState *env)
2475{
0315c31c 2476 CPUState *cs = CPU(mips_env_get_cpu(env));
c227f099 2477 target_siginfo_t info;
ff4f7382
RH		 2478 int trapnr;
2479 abi_long ret;
2480# ifdef TARGET_ABI_MIPSO32
048f6b4d 2481 unsigned int syscall_num;
ff4f7382 2482# endif
048f6b4d
FB		 2483
2484 for(;;) {
0315c31c 2485 cpu_exec_start(cs);
ea3e9847 2486 trapnr = cpu_mips_exec(cs);
0315c31c 2487 cpu_exec_end(cs);
048f6b4d
FB		 2488 switch(trapnr) {
2489 case EXCP_SYSCALL:
b5dc7732 2490 env->active_tc.PC += 4;
ff4f7382
RH		 2491# ifdef TARGET_ABI_MIPSO32
2492 syscall_num = env->active_tc.gpr[2] - 4000;
388bb21a 2493 if (syscall_num >= sizeof(mips_syscall_args)) {
7c2f6157 2494 ret = -TARGET_ENOSYS;
388bb21a
TS		 2495 } else {
2496 int nb_args;
992f48a0
BS		 2497 abi_ulong sp_reg;
2498 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
388bb21a
TS		 2499
2500 nb_args = mips_syscall_args[syscall_num];
b5dc7732 2501 sp_reg = env->active_tc.gpr[29];
388bb21a
TS		 2502 switch (nb_args) {
2503 /* these arguments are taken from the stack */
94c19610
ACH		 2504 case 8:
2505 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2506 goto done_syscall;
2507 }
2508 case 7:
2509 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2510 goto done_syscall;
2511 }
2512 case 6:
2513 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2514 goto done_syscall;
2515 }
2516 case 5:
2517 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2518 goto done_syscall;
2519 }
388bb21a
TS		 2520 default:
2521 break;
048f6b4d 2522 }
b5dc7732
TS		 2523 ret = do_syscall(env, env->active_tc.gpr[2],
2524 env->active_tc.gpr[4],
2525 env->active_tc.gpr[5],
2526 env->active_tc.gpr[6],
2527 env->active_tc.gpr[7],
5945cfcb 2528 arg5, arg6, arg7, arg8);
388bb21a 2529 }
94c19610 2530done_syscall:
ff4f7382
RH		 2531# else
2532 ret = do_syscall(env, env->active_tc.gpr[2],
2533 env->active_tc.gpr[4], env->active_tc.gpr[5],
2534 env->active_tc.gpr[6], env->active_tc.gpr[7],
2535 env->active_tc.gpr[8], env->active_tc.gpr[9],
2536 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2537# endif /* O32 */
2eb3ae27
TB		 2538 if (ret == -TARGET_ERESTARTSYS) {
2539 env->active_tc.PC -= 4;
2540 break;
2541 }
0b1bcb00
PB		 2542 if (ret == -TARGET_QEMU_ESIGRETURN) {
2543 /* Returning from a successful sigreturn syscall.
2544 Avoid clobbering register state. */
2545 break;
2546 }
ff4f7382 2547 if ((abi_ulong)ret >= (abi_ulong)-1133) {
b5dc7732 2548 env->active_tc.gpr[7] = 1; /* error flag */
388bb21a
TS		 2549 ret = -ret;
2550 } else {
b5dc7732 2551 env->active_tc.gpr[7] = 0; /* error flag */
048f6b4d 2552 }
b5dc7732 2553 env->active_tc.gpr[2] = ret;
048f6b4d 2554 break;
ca7c2b1b
TS		 2555 case EXCP_TLBL:
2556 case EXCP_TLBS:
e6e5bd2d
WT		 2557 case EXCP_AdEL:
2558 case EXCP_AdES:
e4474235
PB		 2559 info.si_signo = TARGET_SIGSEGV;
2560 info.si_errno = 0;
2561 /* XXX: check env->error_code */
2562 info.si_code = TARGET_SEGV_MAPERR;
2563 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2564 queue_signal(env, info.si_signo, &info);
2565 break;
6900e84b 2566 case EXCP_CpU:
048f6b4d 2567 case EXCP_RI:
bc1ad2de
FB		 2568 info.si_signo = TARGET_SIGILL;
2569 info.si_errno = 0;
2570 info.si_code = 0;
624f7979 2571 queue_signal(env, info.si_signo, &info);
048f6b4d 2572 break;
106ec879
FB		 2573 case EXCP_INTERRUPT:
2574 /* just indicate that signals should be handled asap */
2575 break;
d08b2a28
PB		 2576 case EXCP_DEBUG:
2577 {
2578 int sig;
2579
db6b81d4 2580 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d08b2a28
PB		 2581 if (sig)
2582 {
2583 info.si_signo = sig;
2584 info.si_errno = 0;
2585 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2586 queue_signal(env, info.si_signo, &info);
d08b2a28
PB		 2587 }
2588 }
2589 break;
590bc601
PB		 2590 case EXCP_SC:
2591 if (do_store_exclusive(env)) {
2592 info.si_signo = TARGET_SIGSEGV;
2593 info.si_errno = 0;
2594 info.si_code = TARGET_SEGV_MAPERR;
2595 info._sifields._sigfault._addr = env->active_tc.PC;
2596 queue_signal(env, info.si_signo, &info);
2597 }
2598 break;
853c3240
JL		 2599 case EXCP_DSPDIS:
2600 info.si_signo = TARGET_SIGILL;
2601 info.si_errno = 0;
2602 info.si_code = TARGET_ILL_ILLOPC;
2603 queue_signal(env, info.si_signo, &info);
2604 break;
54b2f42c
MI		 2605 /* The code below was inspired by the MIPS Linux kernel trap
2606 * handling code in arch/mips/kernel/traps.c.
2607 */
2608 case EXCP_BREAK:
2609 {
2610 abi_ulong trap_instr;
2611 unsigned int code;
2612
a0333817
KCY		 2613 if (env->hflags & MIPS_HFLAG_M16) {
2614 if (env->insn_flags & ASE_MICROMIPS) {
2615 /* microMIPS mode */
1308c464
KCY		 2616 ret = get_user_u16(trap_instr, env->active_tc.PC);
2617 if (ret != 0) {
2618 goto error;
2619 }
a0333817 2620
1308c464
KCY		 2621 if ((trap_instr >> 10) == 0x11) {
2622 /* 16-bit instruction */
2623 code = trap_instr & 0xf;
2624 } else {
2625 /* 32-bit instruction */
2626 abi_ulong instr_lo;
2627
2628 ret = get_user_u16(instr_lo,
2629 env->active_tc.PC + 2);
2630 if (ret != 0) {
2631 goto error;
2632 }
2633 trap_instr = (trap_instr << 16) | instr_lo;
2634 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2635 /* Unfortunately, microMIPS also suffers from
2636 the old assembler bug... */
2637 if (code >= (1 << 10)) {
2638 code >>= 10;
2639 }
2640 }
a0333817
KCY		 2641 } else {
2642 /* MIPS16e mode */
2643 ret = get_user_u16(trap_instr, env->active_tc.PC);
2644 if (ret != 0) {
2645 goto error;
2646 }
2647 code = (trap_instr >> 6) & 0x3f;
a0333817
KCY		 2648 }
2649 } else {
f01a361b 2650 ret = get_user_u32(trap_instr, env->active_tc.PC);
1308c464
KCY		 2651 if (ret != 0) {
2652 goto error;
2653 }
54b2f42c 2654
1308c464
KCY		 2655 /* As described in the original Linux kernel code, the
2656 * below checks on 'code' are to work around an old
2657 * assembly bug.
2658 */
2659 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2660 if (code >= (1 << 10)) {
2661 code >>= 10;
2662 }
54b2f42c
MI		 2663 }
2664
2665 if (do_break(env, &info, code) != 0) {
2666 goto error;
2667 }
2668 }
2669 break;
2670 case EXCP_TRAP:
2671 {
2672 abi_ulong trap_instr;
2673 unsigned int code = 0;
2674
a0333817
KCY		 2675 if (env->hflags & MIPS_HFLAG_M16) {
2676 /* microMIPS mode */
2677 abi_ulong instr[2];
2678
2679 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2680 get_user_u16(instr[1], env->active_tc.PC + 2);
2681
2682 trap_instr = (instr[0] << 16) | instr[1];
2683 } else {
f01a361b 2684 ret = get_user_u32(trap_instr, env->active_tc.PC);
a0333817
KCY		 2685 }
2686
54b2f42c
MI		 2687 if (ret != 0) {
2688 goto error;
2689 }
2690
2691 /* The immediate versions don't provide a code. */
2692 if (!(trap_instr & 0xFC000000)) {
a0333817
KCY		 2693 if (env->hflags & MIPS_HFLAG_M16) {
2694 /* microMIPS mode */
2695 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2696 } else {
2697 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2698 }
54b2f42c
MI		 2699 }
2700
2701 if (do_break(env, &info, code) != 0) {
2702 goto error;
2703 }
2704 }
2705 break;
048f6b4d 2706 default:
54b2f42c 2707error:
120a9848 2708 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
048f6b4d
FB		 2709 abort();
2710 }
2711 process_pending_signals(env);
2712 }
2713}
2714#endif
2715
d962783e
JL		 2716#ifdef TARGET_OPENRISC
2717
2718void cpu_loop(CPUOpenRISCState *env)
2719{
878096ee 2720 CPUState *cs = CPU(openrisc_env_get_cpu(env));
d962783e
JL		 2721 int trapnr, gdbsig;
2722
2723 for (;;) {
b040bc9c 2724 cpu_exec_start(cs);
ea3e9847 2725 trapnr = cpu_openrisc_exec(cs);
b040bc9c 2726 cpu_exec_end(cs);
d962783e
JL		 2727 gdbsig = 0;
2728
2729 switch (trapnr) {
2730 case EXCP_RESET:
120a9848 2731 qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc);
4d1275c2 2732 exit(EXIT_FAILURE);
d962783e
JL		 2733 break;
2734 case EXCP_BUSERR:
120a9848 2735 qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc);
a86b3c64 2736 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2737 break;
2738 case EXCP_DPF:
2739 case EXCP_IPF:
878096ee 2740 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2741 gdbsig = TARGET_SIGSEGV;
2742 break;
2743 case EXCP_TICK:
120a9848 2744 qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc);
d962783e
JL		 2745 break;
2746 case EXCP_ALIGN:
120a9848 2747 qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc);
a86b3c64 2748 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2749 break;
2750 case EXCP_ILLEGAL:
120a9848 2751 qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc);
a86b3c64 2752 gdbsig = TARGET_SIGILL;
d962783e
JL		 2753 break;
2754 case EXCP_INT:
120a9848 2755 qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc);
d962783e
JL		 2756 break;
2757 case EXCP_DTLBMISS:
2758 case EXCP_ITLBMISS:
120a9848 2759 qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n");
d962783e
JL		 2760 break;
2761 case EXCP_RANGE:
120a9848 2762 qemu_log_mask(CPU_LOG_INT, "\nRange\n");
a86b3c64 2763 gdbsig = TARGET_SIGSEGV;
d962783e
JL		 2764 break;
2765 case EXCP_SYSCALL:
2766 env->pc += 4; /* 0xc00; */
2767 env->gpr[11] = do_syscall(env,
2768 env->gpr[11], /* return value */
2769 env->gpr[3], /* r3 - r7 are params */
2770 env->gpr[4],
2771 env->gpr[5],
2772 env->gpr[6],
2773 env->gpr[7],
2774 env->gpr[8], 0, 0);
2775 break;
2776 case EXCP_FPE:
120a9848 2777 qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n");
d962783e
JL		 2778 break;
2779 case EXCP_TRAP:
120a9848 2780 qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
a86b3c64 2781 gdbsig = TARGET_SIGTRAP;
d962783e
JL		 2782 break;
2783 case EXCP_NR:
120a9848 2784 qemu_log_mask(CPU_LOG_INT, "\nNR\n");
d962783e
JL		 2785 break;
2786 default:
120a9848 2787 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
d962783e 2788 trapnr);
d962783e
JL		 2789 gdbsig = TARGET_SIGILL;
2790 break;
2791 }
2792 if (gdbsig) {
db6b81d4 2793 gdb_handlesig(cs, gdbsig);
d962783e 2794 if (gdbsig != TARGET_SIGTRAP) {
4d1275c2 2795 exit(EXIT_FAILURE);
d962783e
JL		 2796 }
2797 }
2798
2799 process_pending_signals(env);
2800 }
2801}
2802
2803#endif /* TARGET_OPENRISC */
2804
fdf9b3e8 2805#ifdef TARGET_SH4
05390248 2806void cpu_loop(CPUSH4State *env)
fdf9b3e8 2807{
878096ee 2808 CPUState *cs = CPU(sh_env_get_cpu(env));
fdf9b3e8 2809 int trapnr, ret;
c227f099 2810 target_siginfo_t info;
3b46e624 2811
fdf9b3e8 2812 while (1) {
b040bc9c 2813 cpu_exec_start(cs);
ea3e9847 2814 trapnr = cpu_sh4_exec(cs);
b040bc9c 2815 cpu_exec_end(cs);
3b46e624 2816
fdf9b3e8
FB		 2817 switch (trapnr) {
2818 case 0x160:
0b6d3ae0 2819 env->pc += 2;
5fafdf24
TS		 2820 ret = do_syscall(env,
2821 env->gregs[3],
2822 env->gregs[4],
2823 env->gregs[5],
2824 env->gregs[6],
2825 env->gregs[7],
2826 env->gregs[0],
5945cfcb
PM		 2827 env->gregs[1],
2828 0, 0);
ba412496
TB		 2829 if (ret == -TARGET_ERESTARTSYS) {
2830 env->pc -= 2;
2831 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2832 env->gregs[0] = ret;
2833 }
fdf9b3e8 2834 break;
c3b5bc8a
TS		 2835 case EXCP_INTERRUPT:
2836 /* just indicate that signals should be handled asap */
2837 break;
355fb23d
PB		 2838 case EXCP_DEBUG:
2839 {
2840 int sig;
2841
db6b81d4 2842 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
355fb23d
PB		 2843 if (sig)
2844 {
2845 info.si_signo = sig;
2846 info.si_errno = 0;
2847 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2848 queue_signal(env, info.si_signo, &info);
355fb23d
PB		 2849 }
2850 }
2851 break;
c3b5bc8a
TS		 2852 case 0xa0:
2853 case 0xc0:
a86b3c64 2854 info.si_signo = TARGET_SIGSEGV;
c3b5bc8a
TS		 2855 info.si_errno = 0;
2856 info.si_code = TARGET_SEGV_MAPERR;
2857 info._sifields._sigfault._addr = env->tea;
624f7979 2858 queue_signal(env, info.si_signo, &info);
c3b5bc8a
TS		 2859 break;
2860
fdf9b3e8
FB		 2861 default:
2862 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2863 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 2864 exit(EXIT_FAILURE);
fdf9b3e8
FB		 2865 }
2866 process_pending_signals (env);
2867 }
2868}
2869#endif
2870
48733d19 2871#ifdef TARGET_CRIS
05390248 2872void cpu_loop(CPUCRISState *env)
48733d19 2873{
878096ee 2874 CPUState *cs = CPU(cris_env_get_cpu(env));
48733d19 2875 int trapnr, ret;
c227f099 2876 target_siginfo_t info;
48733d19
TS		 2877
2878 while (1) {
b040bc9c 2879 cpu_exec_start(cs);
ea3e9847 2880 trapnr = cpu_cris_exec(cs);
b040bc9c 2881 cpu_exec_end(cs);
48733d19
TS		 2882 switch (trapnr) {
2883 case 0xaa:
2884 {
a86b3c64 2885 info.si_signo = TARGET_SIGSEGV;
48733d19
TS		 2886 info.si_errno = 0;
2887 /* XXX: check env->error_code */
2888 info.si_code = TARGET_SEGV_MAPERR;
e00c1e71 2889 info._sifields._sigfault._addr = env->pregs[PR_EDA];
624f7979 2890 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2891 }
2892 break;
b6d3abda
EI		 2893 case EXCP_INTERRUPT:
2894 /* just indicate that signals should be handled asap */
2895 break;
48733d19
TS		 2896 case EXCP_BREAK:
2897 ret = do_syscall(env,
2898 env->regs[9],
2899 env->regs[10],
2900 env->regs[11],
2901 env->regs[12],
2902 env->regs[13],
2903 env->pregs[7],
5945cfcb
PM		 2904 env->pregs[11],
2905 0, 0);
48733d19 2906 env->regs[10] = ret;
48733d19
TS		 2907 break;
2908 case EXCP_DEBUG:
2909 {
2910 int sig;
2911
db6b81d4 2912 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
48733d19
TS		 2913 if (sig)
2914 {
2915 info.si_signo = sig;
2916 info.si_errno = 0;
2917 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2918 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2919 }
2920 }
2921 break;
2922 default:
2923 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2924 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 2925 exit(EXIT_FAILURE);
48733d19
TS		 2926 }
2927 process_pending_signals (env);
2928 }
2929}
2930#endif
2931
b779e29e 2932#ifdef TARGET_MICROBLAZE
05390248 2933void cpu_loop(CPUMBState *env)
b779e29e 2934{
878096ee 2935 CPUState *cs = CPU(mb_env_get_cpu(env));
b779e29e 2936 int trapnr, ret;
c227f099 2937 target_siginfo_t info;
b779e29e
EI		 2938
2939 while (1) {
b040bc9c 2940 cpu_exec_start(cs);
ea3e9847 2941 trapnr = cpu_mb_exec(cs);
b040bc9c 2942 cpu_exec_end(cs);
b779e29e
EI		 2943 switch (trapnr) {
2944 case 0xaa:
2945 {
a86b3c64 2946 info.si_signo = TARGET_SIGSEGV;
b779e29e
EI		 2947 info.si_errno = 0;
2948 /* XXX: check env->error_code */
2949 info.si_code = TARGET_SEGV_MAPERR;
2950 info._sifields._sigfault._addr = 0;
2951 queue_signal(env, info.si_signo, &info);
2952 }
2953 break;
2954 case EXCP_INTERRUPT:
2955 /* just indicate that signals should be handled asap */
2956 break;
2957 case EXCP_BREAK:
2958 /* Return address is 4 bytes after the call. */
2959 env->regs[14] += 4;
d7dce494 2960 env->sregs[SR_PC] = env->regs[14];
b779e29e
EI		 2961 ret = do_syscall(env,
2962 env->regs[12],
2963 env->regs[5],
2964 env->regs[6],
2965 env->regs[7],
2966 env->regs[8],
2967 env->regs[9],
5945cfcb
PM		 2968 env->regs[10],
2969 0, 0);
b779e29e 2970 env->regs[3] = ret;
b779e29e 2971 break;
b76da7e3
EI		 2972 case EXCP_HW_EXCP:
2973 env->regs[17] = env->sregs[SR_PC] + 4;
2974 if (env->iflags & D_FLAG) {
2975 env->sregs[SR_ESR] |= 1 << 12;
2976 env->sregs[SR_PC] -= 4;
b4916d7b 2977 /* FIXME: if branch was immed, replay the imm as well. */
b76da7e3
EI		 2978 }
2979
2980 env->iflags &= ~(IMM_FLAG | D_FLAG);
2981
2982 switch (env->sregs[SR_ESR] & 31) {
22a78d64 2983 case ESR_EC_DIVZERO:
a86b3c64 2984 info.si_signo = TARGET_SIGFPE;
22a78d64
EI		 2985 info.si_errno = 0;
2986 info.si_code = TARGET_FPE_FLTDIV;
2987 info._sifields._sigfault._addr = 0;
2988 queue_signal(env, info.si_signo, &info);
2989 break;
b76da7e3 2990 case ESR_EC_FPU:
a86b3c64 2991 info.si_signo = TARGET_SIGFPE;
b76da7e3
EI		 2992 info.si_errno = 0;
2993 if (env->sregs[SR_FSR] & FSR_IO) {
2994 info.si_code = TARGET_FPE_FLTINV;
2995 }
2996 if (env->sregs[SR_FSR] & FSR_DZ) {
2997 info.si_code = TARGET_FPE_FLTDIV;
2998 }
2999 info._sifields._sigfault._addr = 0;
3000 queue_signal(env, info.si_signo, &info);
3001 break;
3002 default:
3003 printf ("Unhandled hw-exception: 0x%x\n",
2e42d52d 3004 env->sregs[SR_ESR] & ESR_EC_MASK);
878096ee 3005 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3006 exit(EXIT_FAILURE);
b76da7e3
EI		 3007 break;
3008 }
3009 break;
b779e29e
EI		 3010 case EXCP_DEBUG:
3011 {
3012 int sig;
3013
db6b81d4 3014 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
b779e29e
EI		 3015 if (sig)
3016 {
3017 info.si_signo = sig;
3018 info.si_errno = 0;
3019 info.si_code = TARGET_TRAP_BRKPT;
3020 queue_signal(env, info.si_signo, &info);
3021 }
3022 }
3023 break;
3024 default:
3025 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3026 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3027 exit(EXIT_FAILURE);
b779e29e
EI		 3028 }
3029 process_pending_signals (env);
3030 }
3031}
3032#endif
3033
e6e5906b
PB		 3034#ifdef TARGET_M68K
3035
3036void cpu_loop(CPUM68KState *env)
3037{
878096ee 3038 CPUState *cs = CPU(m68k_env_get_cpu(env));
e6e5906b
PB		 3039 int trapnr;
3040 unsigned int n;
c227f099 3041 target_siginfo_t info;
0429a971 3042 TaskState *ts = cs->opaque;
3b46e624 3043
e6e5906b 3044 for(;;) {
b040bc9c 3045 cpu_exec_start(cs);
ea3e9847 3046 trapnr = cpu_m68k_exec(cs);
b040bc9c 3047 cpu_exec_end(cs);
e6e5906b
PB		 3048 switch(trapnr) {
3049 case EXCP_ILLEGAL:
3050 {
3051 if (ts->sim_syscalls) {
3052 uint16_t nr;
d8d5119c 3053 get_user_u16(nr, env->pc + 2);
e6e5906b
PB		 3054 env->pc += 4;
3055 do_m68k_simcall(env, nr);
3056 } else {
3057 goto do_sigill;
3058 }
3059 }
3060 break;
a87295e8 3061 case EXCP_HALT_INSN:
e6e5906b 3062 /* Semihosing syscall. */
a87295e8 3063 env->pc += 4;
e6e5906b
PB		 3064 do_m68k_semihosting(env, env->dregs[0]);
3065 break;
3066 case EXCP_LINEA:
3067 case EXCP_LINEF:
3068 case EXCP_UNSUPPORTED:
3069 do_sigill:
a86b3c64 3070 info.si_signo = TARGET_SIGILL;
e6e5906b
PB		 3071 info.si_errno = 0;
3072 info.si_code = TARGET_ILL_ILLOPN;
3073 info._sifields._sigfault._addr = env->pc;
624f7979 3074 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3075 break;
3076 case EXCP_TRAP0:
3077 {
3078 ts->sim_syscalls = 0;
3079 n = env->dregs[0];
3080 env->pc += 2;
5fafdf24
TS		 3081 env->dregs[0] = do_syscall(env,
3082 n,
e6e5906b
PB		 3083 env->dregs[1],
3084 env->dregs[2],
3085 env->dregs[3],
3086 env->dregs[4],
3087 env->dregs[5],
5945cfcb
PM		 3088 env->aregs[0],
3089 0, 0);
e6e5906b
PB		 3090 }
3091 break;
3092 case EXCP_INTERRUPT:
3093 /* just indicate that signals should be handled asap */
3094 break;
3095 case EXCP_ACCESS:
3096 {
a86b3c64 3097 info.si_signo = TARGET_SIGSEGV;
e6e5906b
PB		 3098 info.si_errno = 0;
3099 /* XXX: check env->error_code */
3100 info.si_code = TARGET_SEGV_MAPERR;
3101 info._sifields._sigfault._addr = env->mmu.ar;
624f7979 3102 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3103 }
3104 break;
3105 case EXCP_DEBUG:
3106 {
3107 int sig;
3108
db6b81d4 3109 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
e6e5906b
PB		 3110 if (sig)
3111 {
3112 info.si_signo = sig;
3113 info.si_errno = 0;
3114 info.si_code = TARGET_TRAP_BRKPT;
624f7979 3115 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3116 }
3117 }
3118 break;
3119 default:
120a9848 3120 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
e6e5906b
PB		 3121 abort();
3122 }
3123 process_pending_signals(env);
3124 }
3125}
3126#endif /* TARGET_M68K */
3127
7a3148a9 3128#ifdef TARGET_ALPHA
6910b8f6
RH		 3129static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3130{
3131 target_ulong addr, val, tmp;
3132 target_siginfo_t info;
3133 int ret = 0;
3134
3135 addr = env->lock_addr;
3136 tmp = env->lock_st_addr;
3137 env->lock_addr = -1;
3138 env->lock_st_addr = 0;
3139
3140 start_exclusive();
3141 mmap_lock();
3142
3143 if (addr == tmp) {
3144 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3145 goto do_sigsegv;
3146 }
3147
3148 if (val == env->lock_value) {
3149 tmp = env->ir[reg];
3150 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3151 goto do_sigsegv;
3152 }
3153 ret = 1;
3154 }
3155 }
3156 env->ir[reg] = ret;
3157 env->pc += 4;
3158
3159 mmap_unlock();
3160 end_exclusive();
3161 return;
3162
3163 do_sigsegv:
3164 mmap_unlock();
3165 end_exclusive();
3166
3167 info.si_signo = TARGET_SIGSEGV;
3168 info.si_errno = 0;
3169 info.si_code = TARGET_SEGV_MAPERR;
3170 info._sifields._sigfault._addr = addr;
3171 queue_signal(env, TARGET_SIGSEGV, &info);
3172}
3173
05390248 3174void cpu_loop(CPUAlphaState *env)
7a3148a9 3175{
878096ee 3176 CPUState *cs = CPU(alpha_env_get_cpu(env));
e96efcfc 3177 int trapnr;
c227f099 3178 target_siginfo_t info;
6049f4f8 3179 abi_long sysret;
3b46e624 3180
7a3148a9 3181 while (1) {
b040bc9c 3182 cpu_exec_start(cs);
ea3e9847 3183 trapnr = cpu_alpha_exec(cs);
b040bc9c 3184 cpu_exec_end(cs);
3b46e624 3185
ac316ca4
RH		 3186 /* All of the traps imply a transition through PALcode, which
3187 implies an REI instruction has been executed. Which means
3188 that the intr_flag should be cleared. */
3189 env->intr_flag = 0;
3190
7a3148a9
JM		 3191 switch (trapnr) {
3192 case EXCP_RESET:
3193 fprintf(stderr, "Reset requested. Exit\n");
4d1275c2 3194 exit(EXIT_FAILURE);
7a3148a9
JM		 3195 break;
3196 case EXCP_MCHK:
3197 fprintf(stderr, "Machine check exception. Exit\n");
4d1275c2 3198 exit(EXIT_FAILURE);
7a3148a9 3199 break;
07b6c13b
RH		 3200 case EXCP_SMP_INTERRUPT:
3201 case EXCP_CLK_INTERRUPT:
3202 case EXCP_DEV_INTERRUPT:
5fafdf24 3203 fprintf(stderr, "External interrupt. Exit\n");
4d1275c2 3204 exit(EXIT_FAILURE);
7a3148a9 3205 break;
07b6c13b 3206 case EXCP_MMFAULT:
6910b8f6 3207 env->lock_addr = -1;
6049f4f8
RH		 3208 info.si_signo = TARGET_SIGSEGV;
3209 info.si_errno = 0;
129d8aa5 3210 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
0be1d07c 3211 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
129d8aa5 3212 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3213 queue_signal(env, info.si_signo, &info);
7a3148a9 3214 break;
7a3148a9 3215 case EXCP_UNALIGN:
6910b8f6 3216 env->lock_addr = -1;
6049f4f8
RH		 3217 info.si_signo = TARGET_SIGBUS;
3218 info.si_errno = 0;
3219 info.si_code = TARGET_BUS_ADRALN;
129d8aa5 3220 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3221 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3222 break;
3223 case EXCP_OPCDEC:
6049f4f8 3224 do_sigill:
6910b8f6 3225 env->lock_addr = -1;
6049f4f8
RH		 3226 info.si_signo = TARGET_SIGILL;
3227 info.si_errno = 0;
3228 info.si_code = TARGET_ILL_ILLOPC;
3229 info._sifields._sigfault._addr = env->pc;
3230 queue_signal(env, info.si_signo, &info);
7a3148a9 3231 break;
07b6c13b
RH		 3232 case EXCP_ARITH:
3233 env->lock_addr = -1;
3234 info.si_signo = TARGET_SIGFPE;
3235 info.si_errno = 0;
3236 info.si_code = TARGET_FPE_FLTINV;
3237 info._sifields._sigfault._addr = env->pc;
3238 queue_signal(env, info.si_signo, &info);
3239 break;
7a3148a9 3240 case EXCP_FEN:
6049f4f8 3241 /* No-op. Linux simply re-enables the FPU. */
7a3148a9 3242 break;
07b6c13b 3243 case EXCP_CALL_PAL:
6910b8f6 3244 env->lock_addr = -1;
07b6c13b 3245 switch (env->error_code) {
6049f4f8
RH		 3246 case 0x80:
3247 /* BPT */
3248 info.si_signo = TARGET_SIGTRAP;
3249 info.si_errno = 0;
3250 info.si_code = TARGET_TRAP_BRKPT;
3251 info._sifields._sigfault._addr = env->pc;
3252 queue_signal(env, info.si_signo, &info);
3253 break;
3254 case 0x81:
3255 /* BUGCHK */
3256 info.si_signo = TARGET_SIGTRAP;
3257 info.si_errno = 0;
3258 info.si_code = 0;
3259 info._sifields._sigfault._addr = env->pc;
3260 queue_signal(env, info.si_signo, &info);
3261 break;
3262 case 0x83:
3263 /* CALLSYS */
3264 trapnr = env->ir[IR_V0];
3265 sysret = do_syscall(env, trapnr,
3266 env->ir[IR_A0], env->ir[IR_A1],
3267 env->ir[IR_A2], env->ir[IR_A3],
5945cfcb
PM		 3268 env->ir[IR_A4], env->ir[IR_A5],
3269 0, 0);
a5b3b13b
RH		 3270 if (trapnr == TARGET_NR_sigreturn
3271 || trapnr == TARGET_NR_rt_sigreturn) {
3272 break;
3273 }
3274 /* Syscall writes 0 to V0 to bypass error check, similar
0e141977
RH		 3275 to how this is handled internal to Linux kernel.
3276 (Ab)use trapnr temporarily as boolean indicating error. */
3277 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3278 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3279 env->ir[IR_A3] = trapnr;
6049f4f8
RH		 3280 break;
3281 case 0x86:
3282 /* IMB */
3283 /* ??? We can probably elide the code using page_unprotect
3284 that is checking for self-modifying code. Instead we
3285 could simply call tb_flush here. Until we work out the
3286 changes required to turn off the extra write protection,
3287 this can be a no-op. */
3288 break;
3289 case 0x9E:
3290 /* RDUNIQUE */
3291 /* Handled in the translator for usermode. */
3292 abort();
3293 case 0x9F:
3294 /* WRUNIQUE */
3295 /* Handled in the translator for usermode. */
3296 abort();
3297 case 0xAA:
3298 /* GENTRAP */
3299 info.si_signo = TARGET_SIGFPE;
3300 switch (env->ir[IR_A0]) {
3301 case TARGET_GEN_INTOVF:
3302 info.si_code = TARGET_FPE_INTOVF;
3303 break;
3304 case TARGET_GEN_INTDIV:
3305 info.si_code = TARGET_FPE_INTDIV;
3306 break;
3307 case TARGET_GEN_FLTOVF:
3308 info.si_code = TARGET_FPE_FLTOVF;
3309 break;
3310 case TARGET_GEN_FLTUND:
3311 info.si_code = TARGET_FPE_FLTUND;
3312 break;
3313 case TARGET_GEN_FLTINV:
3314 info.si_code = TARGET_FPE_FLTINV;
3315 break;
3316 case TARGET_GEN_FLTINE:
3317 info.si_code = TARGET_FPE_FLTRES;
3318 break;
3319 case TARGET_GEN_ROPRAND:
3320 info.si_code = 0;
3321 break;
3322 default:
3323 info.si_signo = TARGET_SIGTRAP;
3324 info.si_code = 0;
3325 break;
3326 }
3327 info.si_errno = 0;
3328 info._sifields._sigfault._addr = env->pc;
3329 queue_signal(env, info.si_signo, &info);
3330 break;
3331 default:
3332 goto do_sigill;
3333 }
7a3148a9 3334 break;
7a3148a9 3335 case EXCP_DEBUG:
db6b81d4 3336 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
6049f4f8 3337 if (info.si_signo) {
6910b8f6 3338 env->lock_addr = -1;
6049f4f8
RH		 3339 info.si_errno = 0;
3340 info.si_code = TARGET_TRAP_BRKPT;
3341 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3342 }
3343 break;
6910b8f6
RH		 3344 case EXCP_STL_C:
3345 case EXCP_STQ_C:
3346 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3347 break;
d0f20495
RH		 3348 case EXCP_INTERRUPT:
3349 /* Just indicate that signals should be handled asap. */
3350 break;
7a3148a9
JM		 3351 default:
3352 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3353 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3354 exit(EXIT_FAILURE);
7a3148a9
JM		 3355 }
3356 process_pending_signals (env);
3357 }
3358}
3359#endif /* TARGET_ALPHA */
3360
a4c075f1
UH		 3361#ifdef TARGET_S390X
3362void cpu_loop(CPUS390XState *env)
3363{
878096ee 3364 CPUState *cs = CPU(s390_env_get_cpu(env));
d5a103cd 3365 int trapnr, n, sig;
a4c075f1 3366 target_siginfo_t info;
d5a103cd 3367 target_ulong addr;
a4c075f1
UH		 3368
3369 while (1) {
b040bc9c 3370 cpu_exec_start(cs);
ea3e9847 3371 trapnr = cpu_s390x_exec(cs);
b040bc9c 3372 cpu_exec_end(cs);
a4c075f1
UH		 3373 switch (trapnr) {
3374 case EXCP_INTERRUPT:
d5a103cd 3375 /* Just indicate that signals should be handled asap. */
a4c075f1 3376 break;
a4c075f1 3377
d5a103cd
RH		 3378 case EXCP_SVC:
3379 n = env->int_svc_code;
3380 if (!n) {
3381 /* syscalls > 255 */
3382 n = env->regs[1];
a4c075f1 3383 }
d5a103cd
RH		 3384 env->psw.addr += env->int_svc_ilen;
3385 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3386 env->regs[4], env->regs[5],
3387 env->regs[6], env->regs[7], 0, 0);
a4c075f1 3388 break;
d5a103cd
RH		 3389
3390 case EXCP_DEBUG:
db6b81d4 3391 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d5a103cd
RH		 3392 if (sig) {
3393 n = TARGET_TRAP_BRKPT;
3394 goto do_signal_pc;
a4c075f1
UH		 3395 }
3396 break;
d5a103cd
RH		 3397 case EXCP_PGM:
3398 n = env->int_pgm_code;
3399 switch (n) {
3400 case PGM_OPERATION:
3401 case PGM_PRIVILEGED:
a86b3c64 3402 sig = TARGET_SIGILL;
d5a103cd
RH		 3403 n = TARGET_ILL_ILLOPC;
3404 goto do_signal_pc;
3405 case PGM_PROTECTION:
3406 case PGM_ADDRESSING:
a86b3c64 3407 sig = TARGET_SIGSEGV;
a4c075f1 3408 /* XXX: check env->error_code */
d5a103cd
RH		 3409 n = TARGET_SEGV_MAPERR;
3410 addr = env->__excp_addr;
3411 goto do_signal;
3412 case PGM_EXECUTE:
3413 case PGM_SPECIFICATION:
3414 case PGM_SPECIAL_OP:
3415 case PGM_OPERAND:
3416 do_sigill_opn:
a86b3c64 3417 sig = TARGET_SIGILL;
d5a103cd
RH		 3418 n = TARGET_ILL_ILLOPN;
3419 goto do_signal_pc;
3420
3421 case PGM_FIXPT_OVERFLOW:
a86b3c64 3422 sig = TARGET_SIGFPE;
d5a103cd
RH		 3423 n = TARGET_FPE_INTOVF;
3424 goto do_signal_pc;
3425 case PGM_FIXPT_DIVIDE:
a86b3c64 3426 sig = TARGET_SIGFPE;
d5a103cd
RH		 3427 n = TARGET_FPE_INTDIV;
3428 goto do_signal_pc;
3429
3430 case PGM_DATA:
3431 n = (env->fpc >> 8) & 0xff;
3432 if (n == 0xff) {
3433 /* compare-and-trap */
3434 goto do_sigill_opn;
3435 } else {
3436 /* An IEEE exception, simulated or otherwise. */
3437 if (n & 0x80) {
3438 n = TARGET_FPE_FLTINV;
3439 } else if (n & 0x40) {
3440 n = TARGET_FPE_FLTDIV;
3441 } else if (n & 0x20) {
3442 n = TARGET_FPE_FLTOVF;
3443 } else if (n & 0x10) {
3444 n = TARGET_FPE_FLTUND;
3445 } else if (n & 0x08) {
3446 n = TARGET_FPE_FLTRES;
3447 } else {
3448 /* ??? Quantum exception; BFP, DFP error. */
3449 goto do_sigill_opn;
3450 }
a86b3c64 3451 sig = TARGET_SIGFPE;
d5a103cd
RH		 3452 goto do_signal_pc;
3453 }
3454
3455 default:
3456 fprintf(stderr, "Unhandled program exception: %#x\n", n);
878096ee 3457 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3458 exit(EXIT_FAILURE);
a4c075f1
UH		 3459 }
3460 break;
d5a103cd
RH		 3461
3462 do_signal_pc:
3463 addr = env->psw.addr;
3464 do_signal:
3465 info.si_signo = sig;
3466 info.si_errno = 0;
3467 info.si_code = n;
3468 info._sifields._sigfault._addr = addr;
3469 queue_signal(env, info.si_signo, &info);
a4c075f1 3470 break;
d5a103cd 3471
a4c075f1 3472 default:
d5a103cd 3473 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
878096ee 3474 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3475 exit(EXIT_FAILURE);
a4c075f1
UH		 3476 }
3477 process_pending_signals (env);
3478 }
3479}
3480
3481#endif /* TARGET_S390X */
3482
b16189b2
CG		 3483#ifdef TARGET_TILEGX
3484
b16189b2
CG		 3485static void gen_sigill_reg(CPUTLGState *env)
3486{
3487 target_siginfo_t info;
3488
3489 info.si_signo = TARGET_SIGILL;
3490 info.si_errno = 0;
3491 info.si_code = TARGET_ILL_PRVREG;
3492 info._sifields._sigfault._addr = env->pc;
3493 queue_signal(env, info.si_signo, &info);
3494}
3495
a0577d2a 3496static void do_signal(CPUTLGState *env, int signo, int sigcode)
dd8070d8
CG		 3497{
3498 target_siginfo_t info;
3499
a0577d2a 3500 info.si_signo = signo;
dd8070d8 3501 info.si_errno = 0;
dd8070d8 3502 info._sifields._sigfault._addr = env->pc;
a0577d2a
RH		 3503
3504 if (signo == TARGET_SIGSEGV) {
3505 /* The passed in sigcode is a dummy; check for a page mapping
3506 and pass either MAPERR or ACCERR. */
3507 target_ulong addr = env->excaddr;
3508 info._sifields._sigfault._addr = addr;
3509 if (page_check_range(addr, 1, PAGE_VALID) < 0) {
3510 sigcode = TARGET_SEGV_MAPERR;
3511 } else {
3512 sigcode = TARGET_SEGV_ACCERR;
3513 }
3514 }
3515 info.si_code = sigcode;
3516
dd8070d8
CG		 3517 queue_signal(env, info.si_signo, &info);
3518}
3519
a0577d2a
RH		 3520static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
3521{
3522 env->excaddr = addr;
3523 do_signal(env, TARGET_SIGSEGV, 0);
3524}
3525
0583b233
RH		 3526static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
3527{
3528 if (unlikely(reg >= TILEGX_R_COUNT)) {
3529 switch (reg) {
3530 case TILEGX_R_SN:
3531 case TILEGX_R_ZERO:
3532 return;
3533 case TILEGX_R_IDN0:
3534 case TILEGX_R_IDN1:
3535 case TILEGX_R_UDN0:
3536 case TILEGX_R_UDN1:
3537 case TILEGX_R_UDN2:
3538 case TILEGX_R_UDN3:
3539 gen_sigill_reg(env);
3540 return;
3541 default:
3542 g_assert_not_reached();
3543 }
3544 }
3545 env->regs[reg] = val;
3546}
3547
3548/*
3549 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
3550 * memory at the address held in the first source register. If the values are
3551 * not equal, then no memory operation is performed. If the values are equal,
3552 * the 8-byte quantity from the second source register is written into memory
3553 * at the address held in the first source register. In either case, the result
3554 * of the instruction is the value read from memory. The compare and write to
3555 * memory are atomic and thus can be used for synchronization purposes. This
3556 * instruction only operates for addresses aligned to a 8-byte boundary.
3557 * Unaligned memory access causes an Unaligned Data Reference interrupt.
3558 *
3559 * Functional Description (64-bit)
3560 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
3561 * rf[Dest] = memVal;
3562 * if (memVal == SPR[CmpValueSPR])
3563 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
3564 *
3565 * Functional Description (32-bit)
3566 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
3567 * rf[Dest] = memVal;
3568 * if (memVal == signExtend32 (SPR[CmpValueSPR]))
3569 * memoryWriteWord (rf[SrcA], rf[SrcB]);
3570 *
3571 *
3572 * This function also processes exch and exch4 which need not process SPR.
3573 */
3574static void do_exch(CPUTLGState *env, bool quad, bool cmp)
3575{
3576 target_ulong addr;
3577 target_long val, sprval;
3578
3579 start_exclusive();
3580
3581 addr = env->atomic_srca;
3582 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3583 goto sigsegv_maperr;
3584 }
3585
3586 if (cmp) {
3587 if (quad) {
3588 sprval = env->spregs[TILEGX_SPR_CMPEXCH];
3589 } else {
3590 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
3591 }
3592 }
3593
3594 if (!cmp || val == sprval) {
3595 target_long valb = env->atomic_srcb;
3596 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3597 goto sigsegv_maperr;
3598 }
3599 }
3600
3601 set_regval(env, env->atomic_dstr, val);
3602 end_exclusive();
3603 return;
3604
3605 sigsegv_maperr:
3606 end_exclusive();
3607 gen_sigsegv_maperr(env, addr);
3608}
3609
3610static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
3611{
3612 int8_t write = 1;
3613 target_ulong addr;
3614 target_long val, valb;
3615
3616 start_exclusive();
3617
3618 addr = env->atomic_srca;
3619 valb = env->atomic_srcb;
3620 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3621 goto sigsegv_maperr;
3622 }
3623
3624 switch (trapnr) {
3625 case TILEGX_EXCP_OPCODE_FETCHADD:
3626 case TILEGX_EXCP_OPCODE_FETCHADD4:
3627 valb += val;
3628 break;
3629 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3630 valb += val;
3631 if (valb < 0) {
3632 write = 0;
3633 }
3634 break;
3635 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3636 valb += val;
3637 if ((int32_t)valb < 0) {
3638 write = 0;
3639 }
3640 break;
3641 case TILEGX_EXCP_OPCODE_FETCHAND:
3642 case TILEGX_EXCP_OPCODE_FETCHAND4:
3643 valb &= val;
3644 break;
3645 case TILEGX_EXCP_OPCODE_FETCHOR:
3646 case TILEGX_EXCP_OPCODE_FETCHOR4:
3647 valb |= val;
3648 break;
3649 default:
3650 g_assert_not_reached();
3651 }
3652
3653 if (write) {
3654 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3655 goto sigsegv_maperr;
3656 }
3657 }
3658
3659 set_regval(env, env->atomic_dstr, val);
3660 end_exclusive();
3661 return;
3662
3663 sigsegv_maperr:
3664 end_exclusive();
3665 gen_sigsegv_maperr(env, addr);
3666}
3667
b16189b2
CG		 3668void cpu_loop(CPUTLGState *env)
3669{
3670 CPUState *cs = CPU(tilegx_env_get_cpu(env));
3671 int trapnr;
3672
3673 while (1) {
3674 cpu_exec_start(cs);
3675 trapnr = cpu_tilegx_exec(cs);
3676 cpu_exec_end(cs);
3677 switch (trapnr) {
3678 case TILEGX_EXCP_SYSCALL:
3679 env->regs[TILEGX_R_RE] = do_syscall(env, env->regs[TILEGX_R_NR],
3680 env->regs[0], env->regs[1],
3681 env->regs[2], env->regs[3],
3682 env->regs[4], env->regs[5],
3683 env->regs[6], env->regs[7]);
3684 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(env->regs[TILEGX_R_RE])
3685 ? - env->regs[TILEGX_R_RE]
3686 : 0;
3687 break;
0583b233
RH		 3688 case TILEGX_EXCP_OPCODE_EXCH:
3689 do_exch(env, true, false);
3690 break;
3691 case TILEGX_EXCP_OPCODE_EXCH4:
3692 do_exch(env, false, false);
3693 break;
3694 case TILEGX_EXCP_OPCODE_CMPEXCH:
3695 do_exch(env, true, true);
3696 break;
3697 case TILEGX_EXCP_OPCODE_CMPEXCH4:
3698 do_exch(env, false, true);
3699 break;
3700 case TILEGX_EXCP_OPCODE_FETCHADD:
3701 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3702 case TILEGX_EXCP_OPCODE_FETCHAND:
3703 case TILEGX_EXCP_OPCODE_FETCHOR:
3704 do_fetch(env, trapnr, true);
3705 break;
3706 case TILEGX_EXCP_OPCODE_FETCHADD4:
3707 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3708 case TILEGX_EXCP_OPCODE_FETCHAND4:
3709 case TILEGX_EXCP_OPCODE_FETCHOR4:
3710 do_fetch(env, trapnr, false);
3711 break;
dd8070d8 3712 case TILEGX_EXCP_SIGNAL:
a0577d2a 3713 do_signal(env, env->signo, env->sigcode);
dd8070d8 3714 break;
b16189b2
CG		 3715 case TILEGX_EXCP_REG_IDN_ACCESS:
3716 case TILEGX_EXCP_REG_UDN_ACCESS:
3717 gen_sigill_reg(env);
3718 break;
3719 default:
3720 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
3721 g_assert_not_reached();
3722 }
3723 process_pending_signals(env);
3724 }
3725}
3726
3727#endif
3728
a2247f8e 3729THREAD CPUState *thread_cpu;
59faf6d6 3730
edf8e2af
MW		 3731void task_settid(TaskState *ts)
3732{
3733 if (ts->ts_tid == 0) {
edf8e2af 3734 ts->ts_tid = (pid_t)syscall(SYS_gettid);
edf8e2af
MW		 3735 }
3736}
3737
3738void stop_all_tasks(void)
3739{
3740 /*
3741 * We trust that when using NPTL, start_exclusive()
3742 * handles thread stopping correctly.
3743 */
3744 start_exclusive();
3745}
3746
c3a92833 3747/* Assumes contents are already zeroed. */
624f7979
PB		 3748void init_task_state(TaskState *ts)
3749{
3750 int i;
3751
624f7979
PB		 3752 ts->used = 1;
3753 ts->first_free = ts->sigqueue_table;
3754 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3755 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3756 }
3757 ts->sigqueue_table[i].next = NULL;
3758}
fc9c5412 3759
30ba0ee5
AF		 3760CPUArchState *cpu_copy(CPUArchState *env)
3761{
ff4700b0 3762 CPUState *cpu = ENV_GET_CPU(env);
2994fd96 3763 CPUState *new_cpu = cpu_init(cpu_model);
61c7480f 3764 CPUArchState *new_env = new_cpu->env_ptr;
30ba0ee5
AF		 3765 CPUBreakpoint *bp;
3766 CPUWatchpoint *wp;
30ba0ee5
AF		 3767
3768 /* Reset non arch specific state */
75a34036 3769 cpu_reset(new_cpu);
30ba0ee5
AF		 3770
3771 memcpy(new_env, env, sizeof(CPUArchState));
3772
3773 /* Clone all break/watchpoints.
3774 Note: Once we support ptrace with hw-debug register access, make sure
3775 BP_CPU break/watchpoints are handled correctly on clone. */
1d085f6c
TB		 3776 QTAILQ_INIT(&new_cpu->breakpoints);
3777 QTAILQ_INIT(&new_cpu->watchpoints);
f0c3c505 3778 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
b3310ab3 3779 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
30ba0ee5 3780 }
ff4700b0 3781 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
05068c0d 3782 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
30ba0ee5 3783 }
30ba0ee5
AF		 3784
3785 return new_env;
3786}
3787
fc9c5412
JS		 3788static void handle_arg_help(const char *arg)
3789{
4d1275c2 3790 usage(EXIT_SUCCESS);
fc9c5412
JS		 3791}
3792
3793static void handle_arg_log(const char *arg)
3794{
3795 int mask;
fc9c5412 3796
4fde1eba 3797 mask = qemu_str_to_log_mask(arg);
fc9c5412 3798 if (!mask) {
59a6fa6e 3799 qemu_print_log_usage(stdout);
4d1275c2 3800 exit(EXIT_FAILURE);
fc9c5412 3801 }
f2937a33 3802 qemu_log_needs_buffers();
24537a01 3803 qemu_set_log(mask);
fc9c5412
JS		 3804}
3805
50171d42
CWR		 3806static void handle_arg_log_filename(const char *arg)
3807{
9a7e5424 3808 qemu_set_log_filename(arg);
50171d42
CWR		 3809}
3810
fc9c5412
JS		 3811static void handle_arg_set_env(const char *arg)
3812{
3813 char *r, *p, *token;
3814 r = p = strdup(arg);
3815 while ((token = strsep(&p, ",")) != NULL) {
3816 if (envlist_setenv(envlist, token) != 0) {
4d1275c2 3817 usage(EXIT_FAILURE);
fc9c5412
JS		 3818 }
3819 }
3820 free(r);
3821}
3822
3823static void handle_arg_unset_env(const char *arg)
3824{
3825 char *r, *p, *token;
3826 r = p = strdup(arg);
3827 while ((token = strsep(&p, ",")) != NULL) {
3828 if (envlist_unsetenv(envlist, token) != 0) {
4d1275c2 3829 usage(EXIT_FAILURE);
fc9c5412
JS		 3830 }
3831 }
3832 free(r);
3833}
3834
3835static void handle_arg_argv0(const char *arg)
3836{
3837 argv0 = strdup(arg);
3838}
3839
3840static void handle_arg_stack_size(const char *arg)
3841{
3842 char *p;
3843 guest_stack_size = strtoul(arg, &p, 0);
3844 if (guest_stack_size == 0) {
4d1275c2 3845 usage(EXIT_FAILURE);
fc9c5412
JS		 3846 }
3847
3848 if (*p == 'M') {
3849 guest_stack_size *= 1024 * 1024;
3850 } else if (*p == 'k' || *p == 'K') {
3851 guest_stack_size *= 1024;
3852 }
3853}
3854
3855static void handle_arg_ld_prefix(const char *arg)
3856{
3857 interp_prefix = strdup(arg);
3858}
3859
3860static void handle_arg_pagesize(const char *arg)
3861{
3862 qemu_host_page_size = atoi(arg);
3863 if (qemu_host_page_size == 0 ||
3864 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3865 fprintf(stderr, "page size must be a power of two\n");
4d1275c2 3866 exit(EXIT_FAILURE);
fc9c5412
JS		 3867 }
3868}
3869
c5e4a5a9
MR		 3870static void handle_arg_randseed(const char *arg)
3871{
3872 unsigned long long seed;
3873
3874 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3875 fprintf(stderr, "Invalid seed number: %s\n", arg);
4d1275c2 3876 exit(EXIT_FAILURE);
c5e4a5a9
MR		 3877 }
3878 srand(seed);
3879}
3880
fc9c5412
JS		 3881static void handle_arg_gdb(const char *arg)
3882{
3883 gdbstub_port = atoi(arg);
3884}
3885
3886static void handle_arg_uname(const char *arg)
3887{
3888 qemu_uname_release = strdup(arg);
3889}
3890
3891static void handle_arg_cpu(const char *arg)
3892{
3893 cpu_model = strdup(arg);
c8057f95 3894 if (cpu_model == NULL || is_help_option(cpu_model)) {
fc9c5412 3895 /* XXX: implement xxx_cpu_list for targets that still miss it */
e916cbf8
PM		 3896#if defined(cpu_list)
3897 cpu_list(stdout, &fprintf);
fc9c5412 3898#endif
4d1275c2 3899 exit(EXIT_FAILURE);
fc9c5412
JS		 3900 }
3901}
3902
fc9c5412
JS		 3903static void handle_arg_guest_base(const char *arg)
3904{
3905 guest_base = strtol(arg, NULL, 0);
3906 have_guest_base = 1;
3907}
3908
3909static void handle_arg_reserved_va(const char *arg)
3910{
3911 char *p;
3912 int shift = 0;
3913 reserved_va = strtoul(arg, &p, 0);
3914 switch (*p) {
3915 case 'k':
3916 case 'K':
3917 shift = 10;
3918 break;
3919 case 'M':
3920 shift = 20;
3921 break;
3922 case 'G':
3923 shift = 30;
3924 break;
3925 }
3926 if (shift) {
3927 unsigned long unshifted = reserved_va;
3928 p++;
3929 reserved_va <<= shift;
3930 if (((reserved_va >> shift) != unshifted)
3931#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3932 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3933#endif
3934 ) {
3935 fprintf(stderr, "Reserved virtual address too big\n");
4d1275c2 3936 exit(EXIT_FAILURE);
fc9c5412
JS		 3937 }
3938 }
3939 if (*p) {
3940 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
4d1275c2 3941 exit(EXIT_FAILURE);
fc9c5412
JS		 3942 }
3943}
fc9c5412
JS		 3944
3945static void handle_arg_singlestep(const char *arg)
3946{
3947 singlestep = 1;
3948}
3949
3950static void handle_arg_strace(const char *arg)
3951{
3952 do_strace = 1;
3953}
3954
3955static void handle_arg_version(const char *arg)
3956{
2e59915d 3957 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
fc9c5412 3958 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
4d1275c2 3959 exit(EXIT_SUCCESS);
fc9c5412
JS		 3960}
3961
3962struct qemu_argument {
3963 const char *argv;
3964 const char *env;
3965 bool has_arg;
3966 void (*handle_opt)(const char *arg);
3967 const char *example;
3968 const char *help;
3969};
3970
42644cee 3971static const struct qemu_argument arg_table[] = {
fc9c5412
JS		 3972 {"h", "", false, handle_arg_help,
3973 "", "print this help"},
daaf8c8e
MI		 3974 {"help", "", false, handle_arg_help,
3975 "", ""},
fc9c5412
JS		 3976 {"g", "QEMU_GDB", true, handle_arg_gdb,
3977 "port", "wait gdb connection to 'port'"},
3978 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3979 "path", "set the elf interpreter prefix to 'path'"},
3980 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3981 "size", "set the stack size to 'size' bytes"},
3982 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
c8057f95 3983 "model", "select CPU (-cpu help for list)"},
fc9c5412
JS		 3984 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3985 "var=value", "sets targets environment variable (see below)"},
3986 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3987 "var", "unsets targets environment variable (see below)"},
3988 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3989 "argv0", "forces target process argv[0] to be 'argv0'"},
3990 {"r", "QEMU_UNAME", true, handle_arg_uname,
3991 "uname", "set qemu uname release string to 'uname'"},
fc9c5412
JS		 3992 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3993 "address", "set guest_base address to 'address'"},
3994 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3995 "size", "reserve 'size' bytes for guest virtual address space"},
fc9c5412 3996 {"d", "QEMU_LOG", true, handle_arg_log,
989b697d
PM		 3997 "item[,...]", "enable logging of specified items "
3998 "(use '-d help' for a list of items)"},
50171d42 3999 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
989b697d 4000 "logfile", "write logs to 'logfile' (default stderr)"},
fc9c5412
JS		 4001 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
4002 "pagesize", "set the host page size to 'pagesize'"},
4003 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
4004 "", "run in singlestep mode"},
4005 {"strace", "QEMU_STRACE", false, handle_arg_strace,
4006 "", "log system calls"},
c5e4a5a9
MR		 4007 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
4008 "", "Seed for pseudo-random number generator"},
fc9c5412 4009 {"version", "QEMU_VERSION", false, handle_arg_version,
1386d4c0 4010 "", "display version information and exit"},
fc9c5412
JS		 4011 {NULL, NULL, false, NULL, NULL, NULL}
4012};
4013
d03f9c32 4014static void usage(int exitcode)
fc9c5412 4015{
42644cee 4016 const struct qemu_argument *arginfo;
fc9c5412
JS		 4017 int maxarglen;
4018 int maxenvlen;
4019
2e59915d
PB		 4020 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
4021 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
fc9c5412
JS		 4022 "\n"
4023 "Options and associated environment variables:\n"
4024 "\n");
4025
63ec54d7
PM		 4026 /* Calculate column widths. We must always have at least enough space
4027 * for the column header.
4028 */
4029 maxarglen = strlen("Argument");
4030 maxenvlen = strlen("Env-variable");
fc9c5412
JS		 4031
4032 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
63ec54d7
PM		 4033 int arglen = strlen(arginfo->argv);
4034 if (arginfo->has_arg) {
4035 arglen += strlen(arginfo->example) + 1;
4036 }
fc9c5412
JS		 4037 if (strlen(arginfo->env) > maxenvlen) {
4038 maxenvlen = strlen(arginfo->env);
4039 }
63ec54d7
PM		 4040 if (arglen > maxarglen) {
4041 maxarglen = arglen;
fc9c5412
JS		 4042 }
4043 }
4044
63ec54d7
PM		 4045 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
4046 maxenvlen, "Env-variable");
fc9c5412
JS		 4047
4048 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4049 if (arginfo->has_arg) {
4050 printf("-%s %-*s %-*s %s\n", arginfo->argv,
63ec54d7
PM		 4051 (int)(maxarglen - strlen(arginfo->argv) - 1),
4052 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
fc9c5412 4053 } else {
63ec54d7 4054 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
fc9c5412
JS		 4055 maxenvlen, arginfo->env,
4056 arginfo->help);
4057 }
4058 }
4059
4060 printf("\n"
4061 "Defaults:\n"
4062 "QEMU_LD_PREFIX = %s\n"
989b697d 4063 "QEMU_STACK_SIZE = %ld byte\n",
fc9c5412 4064 interp_prefix,
989b697d 4065 guest_stack_size);
fc9c5412
JS		 4066
4067 printf("\n"
4068 "You can use -E and -U options or the QEMU_SET_ENV and\n"
4069 "QEMU_UNSET_ENV environment variables to set and unset\n"
4070 "environment variables for the target process.\n"
4071 "It is possible to provide several variables by separating them\n"
4072 "by commas in getsubopt(3) style. Additionally it is possible to\n"
4073 "provide the -E and -U options multiple times.\n"
4074 "The following lines are equivalent:\n"
4075 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
4076 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
4077 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
4078 "Note that if you provide several changes to a single variable\n"
4079 "the last change will stay in effect.\n");
4080
d03f9c32 4081 exit(exitcode);
fc9c5412
JS		 4082}
4083
4084static int parse_args(int argc, char **argv)
4085{
4086 const char *r;
4087 int optind;
42644cee 4088 const struct qemu_argument *arginfo;
fc9c5412
JS		 4089
4090 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4091 if (arginfo->env == NULL) {
4092 continue;
4093 }
4094
4095 r = getenv(arginfo->env);
4096 if (r != NULL) {
4097 arginfo->handle_opt(r);
4098 }
4099 }
4100
4101 optind = 1;
4102 for (;;) {
4103 if (optind >= argc) {
4104 break;
4105 }
4106 r = argv[optind];
4107 if (r[0] != '-') {
4108 break;
4109 }
4110 optind++;
4111 r++;
4112 if (!strcmp(r, "-")) {
4113 break;
4114 }
ba02577c
MI		 4115 /* Treat --foo the same as -foo. */
4116 if (r[0] == '-') {
4117 r++;
4118 }
fc9c5412
JS		 4119
4120 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4121 if (!strcmp(r, arginfo->argv)) {
fc9c5412 4122 if (arginfo->has_arg) {
1386d4c0 4123 if (optind >= argc) {
138940bf
MI		 4124 (void) fprintf(stderr,
4125 "qemu: missing argument for option '%s'\n", r);
4d1275c2 4126 exit(EXIT_FAILURE);
1386d4c0
PM		 4127 }
4128 arginfo->handle_opt(argv[optind]);
fc9c5412 4129 optind++;
1386d4c0
PM		 4130 } else {
4131 arginfo->handle_opt(NULL);
fc9c5412 4132 }
fc9c5412
JS		 4133 break;
4134 }
4135 }
4136
4137 /* no option matched the current argv */
4138 if (arginfo->handle_opt == NULL) {
138940bf 4139 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r);
4d1275c2 4140 exit(EXIT_FAILURE);
fc9c5412
JS		 4141 }
4142 }
4143
4144 if (optind >= argc) {
138940bf 4145 (void) fprintf(stderr, "qemu: no user program specified\n");
4d1275c2 4146 exit(EXIT_FAILURE);
fc9c5412
JS		 4147 }
4148
4149 filename = argv[optind];
4150 exec_path = argv[optind];
4151
4152 return optind;
4153}
4154
902b3d5c 4155int main(int argc, char **argv, char **envp)
31e31b8a 4156{
01ffc75b 4157 struct target_pt_regs regs1, *regs = &regs1;
31e31b8a 4158 struct image_info info1, *info = &info1;
edf8e2af 4159 struct linux_binprm bprm;
48e15fc2 4160 TaskState *ts;
9349b4f9 4161 CPUArchState *env;
db6b81d4 4162 CPUState *cpu;
586314f2 4163 int optind;
04a6dfeb 4164 char **target_environ, **wrk;
7d8cec95
AJ		 4165 char **target_argv;
4166 int target_argc;
7d8cec95 4167 int i;
fd4d81dd 4168 int ret;
03cfd8fa 4169 int execfd;
b12b6a18 4170
ce008c1f
AF		 4171 module_call_init(MODULE_INIT_QOM);
4172
04a6dfeb
AJ		 4173 if ((envlist = envlist_create()) == NULL) {
4174 (void) fprintf(stderr, "Unable to allocate envlist\n");
4d1275c2 4175 exit(EXIT_FAILURE);
04a6dfeb
AJ		 4176 }
4177
4178 /* add current environment into the list */
4179 for (wrk = environ; *wrk != NULL; wrk++) {
4180 (void) envlist_setenv(envlist, *wrk);
4181 }
4182
703e0e89
RH		 4183 /* Read the stack limit from the kernel. If it's "unlimited",
4184 then we can do little else besides use the default. */
4185 {
4186 struct rlimit lim;
4187 if (getrlimit(RLIMIT_STACK, &lim) == 0
81bbe906
TY		 4188 && lim.rlim_cur != RLIM_INFINITY
4189 && lim.rlim_cur == (target_long)lim.rlim_cur) {
703e0e89
RH		 4190 guest_stack_size = lim.rlim_cur;
4191 }
4192 }
4193
b1f9be31 4194 cpu_model = NULL;
b5ec5ce0 4195
c5e4a5a9
MR		 4196 srand(time(NULL));
4197
fc9c5412 4198 optind = parse_args(argc, argv);
586314f2 4199
31e31b8a 4200 /* Zero out regs */
01ffc75b 4201 memset(regs, 0, sizeof(struct target_pt_regs));
31e31b8a
FB		 4202
4203 /* Zero out image_info */
4204 memset(info, 0, sizeof(struct image_info));
4205
edf8e2af
MW		 4206 memset(&bprm, 0, sizeof (bprm));
4207
74cd30b8
FB		 4208 /* Scan interp_prefix dir for replacement files. */
4209 init_paths(interp_prefix);
4210
4a24a758
PM		 4211 init_qemu_uname_release();
4212
46027c07 4213 if (cpu_model == NULL) {
aaed909a 4214#if defined(TARGET_I386)
46027c07
FB		 4215#ifdef TARGET_X86_64
4216 cpu_model = "qemu64";
4217#else
4218 cpu_model = "qemu32";
4219#endif
aaed909a 4220#elif defined(TARGET_ARM)
088ab16c 4221 cpu_model = "any";
d2fbca94
GX		 4222#elif defined(TARGET_UNICORE32)
4223 cpu_model = "any";
aaed909a
FB		 4224#elif defined(TARGET_M68K)
4225 cpu_model = "any";
4226#elif defined(TARGET_SPARC)
4227#ifdef TARGET_SPARC64
4228 cpu_model = "TI UltraSparc II";
4229#else
4230 cpu_model = "Fujitsu MB86904";
46027c07 4231#endif
aaed909a
FB		 4232#elif defined(TARGET_MIPS)
4233#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
74797f40 4234 cpu_model = "5KEf";
aaed909a
FB		 4235#else
4236 cpu_model = "24Kf";
4237#endif
d962783e
JL		 4238#elif defined TARGET_OPENRISC
4239 cpu_model = "or1200";
aaed909a 4240#elif defined(TARGET_PPC)
a74029f6 4241# ifdef TARGET_PPC64
de3f1b98 4242 cpu_model = "POWER8";
a74029f6 4243# else
aaed909a 4244 cpu_model = "750";
a74029f6 4245# endif
91c45a38
RH		 4246#elif defined TARGET_SH4
4247 cpu_model = TYPE_SH7785_CPU;
aaed909a
FB		 4248#else
4249 cpu_model = "any";
4250#endif
4251 }
d5ab9713 4252 tcg_exec_init(0);
83fb7adf
FB		 4253 /* NOTE: we need to init the CPU at this stage to get
4254 qemu_host_page_size */
2994fd96
EH		 4255 cpu = cpu_init(cpu_model);
4256 if (!cpu) {
aaed909a 4257 fprintf(stderr, "Unable to find CPU definition\n");
4d1275c2 4258 exit(EXIT_FAILURE);
aaed909a 4259 }
2994fd96 4260 env = cpu->env_ptr;
0ac46af3 4261 cpu_reset(cpu);
b55a37c9 4262
db6b81d4 4263 thread_cpu = cpu;
3b46e624 4264
b6741956
FB		 4265 if (getenv("QEMU_STRACE")) {
4266 do_strace = 1;
b92c47c1
TS		 4267 }
4268
c5e4a5a9
MR		 4269 if (getenv("QEMU_RAND_SEED")) {
4270 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4271 }
4272
04a6dfeb
AJ		 4273 target_environ = envlist_to_environ(envlist, NULL);
4274 envlist_free(envlist);
b12b6a18 4275
379f6698
PB		 4276 /*
4277 * Now that page sizes are configured in cpu_init() we can do
4278 * proper page alignment for guest_base.
4279 */
4280 guest_base = HOST_PAGE_ALIGN(guest_base);
68a1c816 4281
806d1021
MI		 4282 if (reserved_va || have_guest_base) {
4283 guest_base = init_guest_space(guest_base, reserved_va, 0,
4284 have_guest_base);
4285 if (guest_base == (unsigned long)-1) {
097b8cb8
PM		 4286 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
4287 "space for use as guest address space (check your virtual "
4288 "memory ulimit setting or reserve less using -R option)\n",
4289 reserved_va);
4d1275c2 4290 exit(EXIT_FAILURE);
68a1c816 4291 }
97cc7560 4292
806d1021
MI		 4293 if (reserved_va) {
4294 mmap_next_start = reserved_va;
97cc7560
DDAG		 4295 }
4296 }
379f6698
PB		 4297
4298 /*
4299 * Read in mmap_min_addr kernel parameter. This value is used
4300 * When loading the ELF image to determine whether guest_base
14f24e14 4301 * is needed. It is also used in mmap_find_vma.
379f6698 4302 */
14f24e14 4303 {
379f6698
PB		 4304 FILE *fp;
4305
4306 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
4307 unsigned long tmp;
4308 if (fscanf(fp, "%lu", &tmp) == 1) {
4309 mmap_min_addr = tmp;
13829020 4310 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr);
379f6698
PB		 4311 }
4312 fclose(fp);
4313 }
4314 }
379f6698 4315
7d8cec95
AJ		 4316 /*
4317 * Prepare copy of argv vector for target.
4318 */
4319 target_argc = argc - optind;
4320 target_argv = calloc(target_argc + 1, sizeof (char *));
4321 if (target_argv == NULL) {
4322 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4d1275c2 4323 exit(EXIT_FAILURE);
7d8cec95
AJ		 4324 }
4325
4326 /*
4327 * If argv0 is specified (using '-0' switch) we replace
4328 * argv[0] pointer with the given one.
4329 */
4330 i = 0;
4331 if (argv0 != NULL) {
4332 target_argv[i++] = strdup(argv0);
4333 }
4334 for (; i < target_argc; i++) {
4335 target_argv[i] = strdup(argv[optind + i]);
4336 }
4337 target_argv[target_argc] = NULL;
4338
c78d65e8 4339 ts = g_new0(TaskState, 1);
edf8e2af
MW		 4340 init_task_state(ts);
4341 /* build Task State */
4342 ts->info = info;
4343 ts->bprm = &bprm;
0429a971 4344 cpu->opaque = ts;
edf8e2af
MW		 4345 task_settid(ts);
4346
0b959cf5
RH		 4347 execfd = qemu_getauxval(AT_EXECFD);
4348 if (execfd == 0) {
03cfd8fa 4349 execfd = open(filename, O_RDONLY);
0b959cf5
RH		 4350 if (execfd < 0) {
4351 printf("Error while loading %s: %s\n", filename, strerror(errno));
4d1275c2 4352 _exit(EXIT_FAILURE);
0b959cf5 4353 }
03cfd8fa
LV		 4354 }
4355
4356 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
fd4d81dd
AP		 4357 info, &bprm);
4358 if (ret != 0) {
885c1d10 4359 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4d1275c2 4360 _exit(EXIT_FAILURE);
b12b6a18
TS		 4361 }
4362
4363 for (wrk = target_environ; *wrk; wrk++) {
4364 free(*wrk);
31e31b8a 4365 }
3b46e624 4366
b12b6a18
TS		 4367 free(target_environ);
4368
13829020 4369 if (qemu_loglevel_mask(CPU_LOG_PAGE)) {
379f6698 4370 qemu_log("guest_base 0x%lx\n", guest_base);
2e77eac6
BS		 4371 log_page_dump();
4372
4373 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4374 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4375 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4376 info->start_code);
4377 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4378 info->start_data);
4379 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4380 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4381 info->start_stack);
4382 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4383 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4384 }
31e31b8a 4385
53a5960a 4386 target_set_brk(info->brk);
31e31b8a 4387 syscall_init();
66fb9763 4388 signal_init();
31e31b8a 4389
9002ec79
RH		 4390 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4391 generating the prologue until now so that the prologue can take
4392 the real value of GUEST_BASE into account. */
4393 tcg_prologue_init(&tcg_ctx);
9002ec79 4394
b346ff46 4395#if defined(TARGET_I386)
3802ce26 4396 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
b98dbc90 4397 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
0514ef2f 4398 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
1bde465e
FB		 4399 env->cr[4] |= CR4_OSFXSR_MASK;
4400 env->hflags |= HF_OSFXSR_MASK;
4401 }
d2fd1af7 4402#ifndef TARGET_ABI32
4dbc422b 4403 /* enable 64 bit mode if possible */
0514ef2f 4404 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4dbc422b 4405 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4d1275c2 4406 exit(EXIT_FAILURE);
4dbc422b 4407 }
d2fd1af7 4408 env->cr[4] |= CR4_PAE_MASK;
4dbc422b 4409 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
d2fd1af7
FB		 4410 env->hflags |= HF_LMA_MASK;
4411#endif
1bde465e 4412
415e561f
FB		 4413 /* flags setup : we activate the IRQs by default as in user mode */
4414 env->eflags |= IF_MASK;
3b46e624 4415
6dbad63e 4416 /* linux register setup */
d2fd1af7 4417#ifndef TARGET_ABI32
84409ddb
JM		 4418 env->regs[R_EAX] = regs->rax;
4419 env->regs[R_EBX] = regs->rbx;
4420 env->regs[R_ECX] = regs->rcx;
4421 env->regs[R_EDX] = regs->rdx;
4422 env->regs[R_ESI] = regs->rsi;
4423 env->regs[R_EDI] = regs->rdi;
4424 env->regs[R_EBP] = regs->rbp;
4425 env->regs[R_ESP] = regs->rsp;
4426 env->eip = regs->rip;
4427#else
0ecfa993
FB		 4428 env->regs[R_EAX] = regs->eax;
4429 env->regs[R_EBX] = regs->ebx;
4430 env->regs[R_ECX] = regs->ecx;
4431 env->regs[R_EDX] = regs->edx;
4432 env->regs[R_ESI] = regs->esi;
4433 env->regs[R_EDI] = regs->edi;
4434 env->regs[R_EBP] = regs->ebp;
4435 env->regs[R_ESP] = regs->esp;
dab2ed99 4436 env->eip = regs->eip;
84409ddb 4437#endif
31e31b8a 4438
f4beb510 4439 /* linux interrupt setup */
e441570f
AZ		 4440#ifndef TARGET_ABI32
4441 env->idt.limit = 511;
4442#else
4443 env->idt.limit = 255;
4444#endif
4445 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4446 PROT_READ|PROT_WRITE,
4447 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4448 idt_table = g2h(env->idt.base);
f4beb510
FB		 4449 set_idt(0, 0);
4450 set_idt(1, 0);
4451 set_idt(2, 0);
4452 set_idt(3, 3);
4453 set_idt(4, 3);
ec95da6c 4454 set_idt(5, 0);
f4beb510
FB		 4455 set_idt(6, 0);
4456 set_idt(7, 0);
4457 set_idt(8, 0);
4458 set_idt(9, 0);
4459 set_idt(10, 0);
4460 set_idt(11, 0);
4461 set_idt(12, 0);
4462 set_idt(13, 0);
4463 set_idt(14, 0);
4464 set_idt(15, 0);
4465 set_idt(16, 0);
4466 set_idt(17, 0);
4467 set_idt(18, 0);
4468 set_idt(19, 0);
4469 set_idt(0x80, 3);
4470
6dbad63e 4471 /* linux segment setup */
8d18e893
FB		 4472 {
4473 uint64_t *gdt_table;
e441570f
AZ		 4474 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4475 PROT_READ|PROT_WRITE,
4476 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
8d18e893 4477 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
e441570f 4478 gdt_table = g2h(env->gdt.base);
d2fd1af7 4479#ifdef TARGET_ABI32
8d18e893
FB		 4480 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4481 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4482 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
d2fd1af7
FB		 4483#else
4484 /* 64 bit code segment */
4485 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4486 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4487 DESC_L_MASK |
4488 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4489#endif
8d18e893
FB		 4490 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4491 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4492 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4493 }
6dbad63e 4494 cpu_x86_load_seg(env, R_CS, __USER_CS);
d2fd1af7
FB		 4495 cpu_x86_load_seg(env, R_SS, __USER_DS);
4496#ifdef TARGET_ABI32
6dbad63e
FB		 4497 cpu_x86_load_seg(env, R_DS, __USER_DS);
4498 cpu_x86_load_seg(env, R_ES, __USER_DS);
6dbad63e
FB		 4499 cpu_x86_load_seg(env, R_FS, __USER_DS);
4500 cpu_x86_load_seg(env, R_GS, __USER_DS);
d6eb40f6
TS		 4501 /* This hack makes Wine work... */
4502 env->segs[R_FS].selector = 0;
d2fd1af7
FB		 4503#else
4504 cpu_x86_load_seg(env, R_DS, 0);
4505 cpu_x86_load_seg(env, R_ES, 0);
4506 cpu_x86_load_seg(env, R_FS, 0);
4507 cpu_x86_load_seg(env, R_GS, 0);
4508#endif
99033cae
AG		 4509#elif defined(TARGET_AARCH64)
4510 {
4511 int i;
4512
4513 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4514 fprintf(stderr,
4515 "The selected ARM CPU does not support 64 bit mode\n");
4d1275c2 4516 exit(EXIT_FAILURE);
99033cae
AG		 4517 }
4518
4519 for (i = 0; i < 31; i++) {
4520 env->xregs[i] = regs->regs[i];
4521 }
4522 env->pc = regs->pc;
4523 env->xregs[31] = regs->sp;
4524 }
b346ff46
FB		 4525#elif defined(TARGET_ARM)
4526 {
4527 int i;
ae087923
PM		 4528 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
4529 CPSRWriteByInstr);
b346ff46
FB		 4530 for(i = 0; i < 16; i++) {
4531 env->regs[i] = regs->uregs[i];
4532 }
f9fd40eb 4533#ifdef TARGET_WORDS_BIGENDIAN
d8fd2954
PB		 4534 /* Enable BE8. */
4535 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4536 && (info->elf_flags & EF_ARM_BE8)) {
9c5a7460
PC		 4537 env->uncached_cpsr |= CPSR_E;
4538 env->cp15.sctlr_el[1] |= SCTLR_E0E;
f9fd40eb
PB		 4539 } else {
4540 env->cp15.sctlr_el[1] |= SCTLR_B;
d8fd2954 4541 }
f9fd40eb 4542#endif
b346ff46 4543 }
d2fbca94
GX		 4544#elif defined(TARGET_UNICORE32)
4545 {
4546 int i;
4547 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4548 for (i = 0; i < 32; i++) {
4549 env->regs[i] = regs->uregs[i];
4550 }
4551 }
93ac68bc 4552#elif defined(TARGET_SPARC)
060366c5
FB		 4553 {
4554 int i;
4555 env->pc = regs->pc;
4556 env->npc = regs->npc;
4557 env->y = regs->y;
4558 for(i = 0; i < 8; i++)
4559 env->gregs[i] = regs->u_regs[i];
4560 for(i = 0; i < 8; i++)
4561 env->regwptr[i] = regs->u_regs[i + 8];
4562 }
67867308
FB		 4563#elif defined(TARGET_PPC)
4564 {
4565 int i;
3fc6c082 4566
0411a972
JM		 4567#if defined(TARGET_PPC64)
4568#if defined(TARGET_ABI32)
4569 env->msr &= ~((target_ulong)1 << MSR_SF);
e85e7c6e 4570#else
0411a972
JM		 4571 env->msr |= (target_ulong)1 << MSR_SF;
4572#endif
84409ddb 4573#endif
67867308
FB		 4574 env->nip = regs->nip;
4575 for(i = 0; i < 32; i++) {
4576 env->gpr[i] = regs->gpr[i];
4577 }
4578 }
e6e5906b
PB		 4579#elif defined(TARGET_M68K)
4580 {
e6e5906b
PB		 4581 env->pc = regs->pc;
4582 env->dregs[0] = regs->d0;
4583 env->dregs[1] = regs->d1;
4584 env->dregs[2] = regs->d2;
4585 env->dregs[3] = regs->d3;
4586 env->dregs[4] = regs->d4;
4587 env->dregs[5] = regs->d5;
4588 env->dregs[6] = regs->d6;
4589 env->dregs[7] = regs->d7;
4590 env->aregs[0] = regs->a0;
4591 env->aregs[1] = regs->a1;
4592 env->aregs[2] = regs->a2;
4593 env->aregs[3] = regs->a3;
4594 env->aregs[4] = regs->a4;
4595 env->aregs[5] = regs->a5;
4596 env->aregs[6] = regs->a6;
4597 env->aregs[7] = regs->usp;
4598 env->sr = regs->sr;
4599 ts->sim_syscalls = 1;
4600 }
b779e29e
EI		 4601#elif defined(TARGET_MICROBLAZE)
4602 {
4603 env->regs[0] = regs->r0;
4604 env->regs[1] = regs->r1;
4605 env->regs[2] = regs->r2;
4606 env->regs[3] = regs->r3;
4607 env->regs[4] = regs->r4;
4608 env->regs[5] = regs->r5;
4609 env->regs[6] = regs->r6;
4610 env->regs[7] = regs->r7;
4611 env->regs[8] = regs->r8;
4612 env->regs[9] = regs->r9;
4613 env->regs[10] = regs->r10;
4614 env->regs[11] = regs->r11;
4615 env->regs[12] = regs->r12;
4616 env->regs[13] = regs->r13;
4617 env->regs[14] = regs->r14;
4618 env->regs[15] = regs->r15;
4619 env->regs[16] = regs->r16;
4620 env->regs[17] = regs->r17;
4621 env->regs[18] = regs->r18;
4622 env->regs[19] = regs->r19;
4623 env->regs[20] = regs->r20;
4624 env->regs[21] = regs->r21;
4625 env->regs[22] = regs->r22;
4626 env->regs[23] = regs->r23;
4627 env->regs[24] = regs->r24;
4628 env->regs[25] = regs->r25;
4629 env->regs[26] = regs->r26;
4630 env->regs[27] = regs->r27;
4631 env->regs[28] = regs->r28;
4632 env->regs[29] = regs->r29;
4633 env->regs[30] = regs->r30;
4634 env->regs[31] = regs->r31;
4635 env->sregs[SR_PC] = regs->pc;
4636 }
048f6b4d
FB		 4637#elif defined(TARGET_MIPS)
4638 {
4639 int i;
4640
4641 for(i = 0; i < 32; i++) {
b5dc7732 4642 env->active_tc.gpr[i] = regs->regs[i];
048f6b4d 4643 }
0fddbbf2
NF		 4644 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4645 if (regs->cp0_epc & 1) {
4646 env->hflags |= MIPS_HFLAG_M16;
4647 }
048f6b4d 4648 }
d962783e
JL		 4649#elif defined(TARGET_OPENRISC)
4650 {
4651 int i;
4652
4653 for (i = 0; i < 32; i++) {
4654 env->gpr[i] = regs->gpr[i];
4655 }
4656
4657 env->sr = regs->sr;
4658 env->pc = regs->pc;
4659 }
fdf9b3e8
FB		 4660#elif defined(TARGET_SH4)
4661 {
4662 int i;
4663
4664 for(i = 0; i < 16; i++) {
4665 env->gregs[i] = regs->regs[i];
4666 }
4667 env->pc = regs->pc;
4668 }
7a3148a9
JM		 4669#elif defined(TARGET_ALPHA)
4670 {
4671 int i;
4672
4673 for(i = 0; i < 28; i++) {
992f48a0 4674 env->ir[i] = ((abi_ulong *)regs)[i];
7a3148a9 4675 }
dad081ee 4676 env->ir[IR_SP] = regs->usp;
7a3148a9 4677 env->pc = regs->pc;
7a3148a9 4678 }
48733d19
TS		 4679#elif defined(TARGET_CRIS)
4680 {
4681 env->regs[0] = regs->r0;
4682 env->regs[1] = regs->r1;
4683 env->regs[2] = regs->r2;
4684 env->regs[3] = regs->r3;
4685 env->regs[4] = regs->r4;
4686 env->regs[5] = regs->r5;
4687 env->regs[6] = regs->r6;
4688 env->regs[7] = regs->r7;
4689 env->regs[8] = regs->r8;
4690 env->regs[9] = regs->r9;
4691 env->regs[10] = regs->r10;
4692 env->regs[11] = regs->r11;
4693 env->regs[12] = regs->r12;
4694 env->regs[13] = regs->r13;
4695 env->regs[14] = info->start_stack;
4696 env->regs[15] = regs->acr;
4697 env->pc = regs->erp;
4698 }
a4c075f1
UH		 4699#elif defined(TARGET_S390X)
4700 {
4701 int i;
4702 for (i = 0; i < 16; i++) {
4703 env->regs[i] = regs->gprs[i];
4704 }
4705 env->psw.mask = regs->psw.mask;
4706 env->psw.addr = regs->psw.addr;
4707 }
b16189b2
CG		 4708#elif defined(TARGET_TILEGX)
4709 {
4710 int i;
4711 for (i = 0; i < TILEGX_R_COUNT; i++) {
4712 env->regs[i] = regs->regs[i];
4713 }
4714 for (i = 0; i < TILEGX_SPR_COUNT; i++) {
4715 env->spregs[i] = 0;
4716 }
4717 env->pc = regs->pc;
4718 }
b346ff46
FB		 4719#else
4720#error unsupported target CPU
4721#endif
31e31b8a 4722
d2fbca94 4723#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
a87295e8
PB		 4724 ts->stack_base = info->start_stack;
4725 ts->heap_base = info->brk;
4726 /* This will be filled in on the first SYS_HEAPINFO call. */
4727 ts->heap_limit = 0;
4728#endif
4729
74c33bed 4730 if (gdbstub_port) {
ff7a981a
PM		 4731 if (gdbserver_start(gdbstub_port) < 0) {
4732 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4733 gdbstub_port);
4d1275c2 4734 exit(EXIT_FAILURE);
ff7a981a 4735 }
db6b81d4 4736 gdb_handlesig(cpu, 0);
1fddef4b 4737 }
1b6b029e
FB		 4738 cpu_loop(env);
4739 /* never exits */
31e31b8a
FB		 4740 return 0;
4741}
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