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target-arm: Implement AArch64 DAIF system register
[mirror_qemu.git] / linux-user / main.c
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31e31b8a 1/*
93ac68bc 2 * qemu user main
5fafdf24 3 *
68d0f70e 4 * Copyright (c) 2003-2008 Fabrice Bellard
31e31b8a
FB		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
8167ee88 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31e31b8a
FB		 18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <stdarg.h>
04369ff2 22#include <string.h>
31e31b8a 23#include <errno.h>
0ecfa993 24#include <unistd.h>
e441570f 25#include <sys/mman.h>
edf8e2af 26#include <sys/syscall.h>
703e0e89 27#include <sys/resource.h>
31e31b8a 28
3ef693a0 29#include "qemu.h"
ca10f867 30#include "qemu-common.h"
1de7afc9 31#include "qemu/cache-utils.h"
2b41f10e 32#include "cpu.h"
9002ec79 33#include "tcg.h"
1de7afc9
PB		 34#include "qemu/timer.h"
35#include "qemu/envlist.h"
d8fd2954 36#include "elf.h"
04a6dfeb 37
d088d664
AJ		 38char *exec_path;
39
1b530a6d 40int singlestep;
fc9c5412
JS		 41const char *filename;
42const char *argv0;
43int gdbstub_port;
44envlist_t *envlist;
51fb256a 45static const char *cpu_model;
379f6698 46unsigned long mmap_min_addr;
14f24e14 47#if defined(CONFIG_USE_GUEST_BASE)
379f6698
PB		 48unsigned long guest_base;
49int have_guest_base;
288e65b9
AG		 50#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
51/*
52 * When running 32-on-64 we should make sure we can fit all of the possible
53 * guest address space into a contiguous chunk of virtual host memory.
54 *
55 * This way we will never overlap with our own libraries or binaries or stack
56 * or anything else that QEMU maps.
57 */
314992b1
AG		 58# ifdef TARGET_MIPS
59/* MIPS only supports 31 bits of virtual address space for user space */
60unsigned long reserved_va = 0x77000000;
61# else
288e65b9 62unsigned long reserved_va = 0xf7000000;
314992b1 63# endif
288e65b9 64#else
68a1c816 65unsigned long reserved_va;
379f6698 66#endif
288e65b9 67#endif
1b530a6d 68
fc9c5412
JS		 69static void usage(void);
70
7ee2822c 71static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
c5937220 72const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
586314f2 73
9de5e440
FB		 74/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
75 we allocate a bigger stack. Need a better solution, for example
76 by remapping the process stack directly at the right place */
703e0e89 77unsigned long guest_stack_size = 8 * 1024 * 1024UL;
31e31b8a
FB		 78
79void gemu_log(const char *fmt, ...)
80{
81 va_list ap;
82
83 va_start(ap, fmt);
84 vfprintf(stderr, fmt, ap);
85 va_end(ap);
86}
87
8fcd3692 88#if defined(TARGET_I386)
05390248 89int cpu_get_pic_interrupt(CPUX86State *env)
92ccca6a
FB		 90{
91 return -1;
92}
8fcd3692 93#endif
92ccca6a 94
d5975363
PB		 95/***********************************************************/
96/* Helper routines for implementing atomic operations. */
97
98/* To implement exclusive operations we force all cpus to syncronise.
99 We don't require a full sync, only that no cpus are executing guest code.
100 The alternative is to map target atomic ops onto host equivalents,
101 which requires quite a lot of per host/target work. */
c2764719 102static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
d5975363
PB		 103static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
104static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
105static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
106static int pending_cpus;
107
108/* Make sure everything is in a consistent state for calling fork(). */
109void fork_start(void)
110{
5e5f07e0 111 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 112 pthread_mutex_lock(&exclusive_lock);
d032d1b4 113 mmap_fork_start();
d5975363
PB		 114}
115
116void fork_end(int child)
117{
d032d1b4 118 mmap_fork_end(child);
d5975363 119 if (child) {
bdc44640 120 CPUState *cpu, *next_cpu;
d5975363
PB		 121 /* Child processes created by fork() only have a single thread.
122 Discard information about the parent threads. */
bdc44640
AF		 123 CPU_FOREACH_SAFE(cpu, next_cpu) {
124 if (cpu != thread_cpu) {
125 QTAILQ_REMOVE(&cpus, thread_cpu, node);
126 }
127 }
d5975363
PB		 128 pending_cpus = 0;
129 pthread_mutex_init(&exclusive_lock, NULL);
c2764719 130 pthread_mutex_init(&cpu_list_mutex, NULL);
d5975363
PB		 131 pthread_cond_init(&exclusive_cond, NULL);
132 pthread_cond_init(&exclusive_resume, NULL);
5e5f07e0 133 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
a2247f8e 134 gdbserver_fork((CPUArchState *)thread_cpu->env_ptr);
d5975363
PB		 135 } else {
136 pthread_mutex_unlock(&exclusive_lock);
5e5f07e0 137 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 138 }
d5975363
PB		 139}
140
141/* Wait for pending exclusive operations to complete. The exclusive lock
142 must be held. */
143static inline void exclusive_idle(void)
144{
145 while (pending_cpus) {
146 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
147 }
148}
149
150/* Start an exclusive operation.
151 Must only be called from outside cpu_arm_exec. */
152static inline void start_exclusive(void)
153{
0315c31c
AF		 154 CPUState *other_cpu;
155
d5975363
PB		 156 pthread_mutex_lock(&exclusive_lock);
157 exclusive_idle();
158
159 pending_cpus = 1;
160 /* Make all other cpus stop executing. */
bdc44640 161 CPU_FOREACH(other_cpu) {
0315c31c 162 if (other_cpu->running) {
d5975363 163 pending_cpus++;
60a3e17a 164 cpu_exit(other_cpu);
d5975363
PB		 165 }
166 }
167 if (pending_cpus > 1) {
168 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
169 }
170}
171
172/* Finish an exclusive operation. */
173static inline void end_exclusive(void)
174{
175 pending_cpus = 0;
176 pthread_cond_broadcast(&exclusive_resume);
177 pthread_mutex_unlock(&exclusive_lock);
178}
179
180/* Wait for exclusive ops to finish, and begin cpu execution. */
0315c31c 181static inline void cpu_exec_start(CPUState *cpu)
d5975363
PB		 182{
183 pthread_mutex_lock(&exclusive_lock);
184 exclusive_idle();
0315c31c 185 cpu->running = true;
d5975363
PB		 186 pthread_mutex_unlock(&exclusive_lock);
187}
188
189/* Mark cpu as not executing, and release pending exclusive ops. */
0315c31c 190static inline void cpu_exec_end(CPUState *cpu)
d5975363
PB		 191{
192 pthread_mutex_lock(&exclusive_lock);
0315c31c 193 cpu->running = false;
d5975363
PB		 194 if (pending_cpus > 1) {
195 pending_cpus--;
196 if (pending_cpus == 1) {
197 pthread_cond_signal(&exclusive_cond);
198 }
199 }
200 exclusive_idle();
201 pthread_mutex_unlock(&exclusive_lock);
202}
c2764719
PB		 203
204void cpu_list_lock(void)
205{
206 pthread_mutex_lock(&cpu_list_mutex);
207}
208
209void cpu_list_unlock(void)
210{
211 pthread_mutex_unlock(&cpu_list_mutex);
212}
d5975363
PB		 213
214
a541f297
FB		 215#ifdef TARGET_I386
216/***********************************************************/
217/* CPUX86 core interface */
218
05390248 219void cpu_smm_update(CPUX86State *env)
02a1602e
FB		 220{
221}
222
28ab0e2e
FB		 223uint64_t cpu_get_tsc(CPUX86State *env)
224{
225 return cpu_get_real_ticks();
226}
227
5fafdf24 228static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
f4beb510 229 int flags)
6dbad63e 230{
f4beb510 231 unsigned int e1, e2;
53a5960a 232 uint32_t *p;
6dbad63e
FB		 233 e1 = (addr << 16) | (limit & 0xffff);
234 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
f4beb510 235 e2 |= flags;
53a5960a 236 p = ptr;
d538e8f5 237 p[0] = tswap32(e1);
238 p[1] = tswap32(e2);
f4beb510
FB		 239}
240
e441570f 241static uint64_t *idt_table;
eb38c52c 242#ifdef TARGET_X86_64
d2fd1af7
FB		 243static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
244 uint64_t addr, unsigned int sel)
f4beb510 245{
4dbc422b 246 uint32_t *p, e1, e2;
f4beb510
FB		 247 e1 = (addr & 0xffff) | (sel << 16);
248 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
53a5960a 249 p = ptr;
4dbc422b
FB		 250 p[0] = tswap32(e1);
251 p[1] = tswap32(e2);
252 p[2] = tswap32(addr >> 32);
253 p[3] = 0;
6dbad63e 254}
d2fd1af7
FB		 255/* only dpl matters as we do only user space emulation */
256static void set_idt(int n, unsigned int dpl)
257{
258 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
259}
260#else
d2fd1af7
FB		 261static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
262 uint32_t addr, unsigned int sel)
263{
4dbc422b 264 uint32_t *p, e1, e2;
d2fd1af7
FB		 265 e1 = (addr & 0xffff) | (sel << 16);
266 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
267 p = ptr;
4dbc422b
FB		 268 p[0] = tswap32(e1);
269 p[1] = tswap32(e2);
d2fd1af7
FB		 270}
271
f4beb510
FB		 272/* only dpl matters as we do only user space emulation */
273static void set_idt(int n, unsigned int dpl)
274{
275 set_gate(idt_table + n, 0, dpl, 0, 0);
276}
d2fd1af7 277#endif
31e31b8a 278
89e957e7 279void cpu_loop(CPUX86State *env)
1b6b029e 280{
db6b81d4 281 CPUState *cs = CPU(x86_env_get_cpu(env));
bc8a22cc 282 int trapnr;
992f48a0 283 abi_ulong pc;
c227f099 284 target_siginfo_t info;
851e67a1 285
1b6b029e 286 for(;;) {
bc8a22cc 287 trapnr = cpu_x86_exec(env);
bc8a22cc 288 switch(trapnr) {
f4beb510 289 case 0x80:
d2fd1af7 290 /* linux syscall from int $0x80 */
5fafdf24
TS		 291 env->regs[R_EAX] = do_syscall(env,
292 env->regs[R_EAX],
f4beb510
FB		 293 env->regs[R_EBX],
294 env->regs[R_ECX],
295 env->regs[R_EDX],
296 env->regs[R_ESI],
297 env->regs[R_EDI],
5945cfcb
PM		 298 env->regs[R_EBP],
299 0, 0);
f4beb510 300 break;
d2fd1af7
FB		 301#ifndef TARGET_ABI32
302 case EXCP_SYSCALL:
5ba18547 303 /* linux syscall from syscall instruction */
d2fd1af7
FB		 304 env->regs[R_EAX] = do_syscall(env,
305 env->regs[R_EAX],
306 env->regs[R_EDI],
307 env->regs[R_ESI],
308 env->regs[R_EDX],
309 env->regs[10],
310 env->regs[8],
5945cfcb
PM		 311 env->regs[9],
312 0, 0);
d2fd1af7
FB		 313 env->eip = env->exception_next_eip;
314 break;
315#endif
f4beb510
FB		 316 case EXCP0B_NOSEG:
317 case EXCP0C_STACK:
318 info.si_signo = SIGBUS;
319 info.si_errno = 0;
320 info.si_code = TARGET_SI_KERNEL;
321 info._sifields._sigfault._addr = 0;
624f7979 322 queue_signal(env, info.si_signo, &info);
f4beb510 323 break;
1b6b029e 324 case EXCP0D_GPF:
d2fd1af7 325 /* XXX: potential problem if ABI32 */
84409ddb 326#ifndef TARGET_X86_64
851e67a1 327 if (env->eflags & VM_MASK) {
89e957e7 328 handle_vm86_fault(env);
84409ddb
JM		 329 } else
330#endif
331 {
f4beb510
FB		 332 info.si_signo = SIGSEGV;
333 info.si_errno = 0;
334 info.si_code = TARGET_SI_KERNEL;
335 info._sifields._sigfault._addr = 0;
624f7979 336 queue_signal(env, info.si_signo, &info);
1b6b029e
FB		 337 }
338 break;
b689bc57
FB		 339 case EXCP0E_PAGE:
340 info.si_signo = SIGSEGV;
341 info.si_errno = 0;
342 if (!(env->error_code & 1))
343 info.si_code = TARGET_SEGV_MAPERR;
344 else
345 info.si_code = TARGET_SEGV_ACCERR;
970a87a6 346 info._sifields._sigfault._addr = env->cr[2];
624f7979 347 queue_signal(env, info.si_signo, &info);
b689bc57 348 break;
9de5e440 349 case EXCP00_DIVZ:
84409ddb 350#ifndef TARGET_X86_64
bc8a22cc 351 if (env->eflags & VM_MASK) {
447db213 352 handle_vm86_trap(env, trapnr);
84409ddb
JM		 353 } else
354#endif
355 {
bc8a22cc
FB		 356 /* division by zero */
357 info.si_signo = SIGFPE;
358 info.si_errno = 0;
359 info.si_code = TARGET_FPE_INTDIV;
360 info._sifields._sigfault._addr = env->eip;
624f7979 361 queue_signal(env, info.si_signo, &info);
bc8a22cc 362 }
9de5e440 363 break;
01df040b 364 case EXCP01_DB:
447db213 365 case EXCP03_INT3:
84409ddb 366#ifndef TARGET_X86_64
447db213
FB		 367 if (env->eflags & VM_MASK) {
368 handle_vm86_trap(env, trapnr);
84409ddb
JM		 369 } else
370#endif
371 {
447db213
FB		 372 info.si_signo = SIGTRAP;
373 info.si_errno = 0;
01df040b 374 if (trapnr == EXCP01_DB) {
447db213
FB		 375 info.si_code = TARGET_TRAP_BRKPT;
376 info._sifields._sigfault._addr = env->eip;
377 } else {
378 info.si_code = TARGET_SI_KERNEL;
379 info._sifields._sigfault._addr = 0;
380 }
624f7979 381 queue_signal(env, info.si_signo, &info);
447db213
FB		 382 }
383 break;
9de5e440
FB		 384 case EXCP04_INTO:
385 case EXCP05_BOUND:
84409ddb 386#ifndef TARGET_X86_64
bc8a22cc 387 if (env->eflags & VM_MASK) {
447db213 388 handle_vm86_trap(env, trapnr);
84409ddb
JM		 389 } else
390#endif
391 {
bc8a22cc
FB		 392 info.si_signo = SIGSEGV;
393 info.si_errno = 0;
b689bc57 394 info.si_code = TARGET_SI_KERNEL;
bc8a22cc 395 info._sifields._sigfault._addr = 0;
624f7979 396 queue_signal(env, info.si_signo, &info);
bc8a22cc 397 }
9de5e440
FB		 398 break;
399 case EXCP06_ILLOP:
400 info.si_signo = SIGILL;
401 info.si_errno = 0;
402 info.si_code = TARGET_ILL_ILLOPN;
403 info._sifields._sigfault._addr = env->eip;
624f7979 404 queue_signal(env, info.si_signo, &info);
9de5e440
FB		 405 break;
406 case EXCP_INTERRUPT:
407 /* just indicate that signals should be handled asap */
408 break;
1fddef4b
FB		 409 case EXCP_DEBUG:
410 {
411 int sig;
412
db6b81d4 413 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 414 if (sig)
415 {
416 info.si_signo = sig;
417 info.si_errno = 0;
418 info.si_code = TARGET_TRAP_BRKPT;
624f7979 419 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 420 }
421 }
422 break;
1b6b029e 423 default:
970a87a6 424 pc = env->segs[R_CS].base + env->eip;
5fafdf24 425 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
bc8a22cc 426 (long)pc, trapnr);
1b6b029e
FB		 427 abort();
428 }
66fb9763 429 process_pending_signals(env);
1b6b029e
FB		 430 }
431}
b346ff46
FB		 432#endif
433
434#ifdef TARGET_ARM
435
d8fd2954
PB		 436#define get_user_code_u32(x, gaddr, doswap) \
437 ({ abi_long __r = get_user_u32((x), (gaddr)); \
438 if (!__r && (doswap)) { \
439 (x) = bswap32(x); \
440 } \
441 __r; \
442 })
443
444#define get_user_code_u16(x, gaddr, doswap) \
445 ({ abi_long __r = get_user_u16((x), (gaddr)); \
446 if (!__r && (doswap)) { \
447 (x) = bswap16(x); \
448 } \
449 __r; \
450 })
451
1861c454
PM		 452#ifdef TARGET_ABI32
453/* Commpage handling -- there is no commpage for AArch64 */
454
97cc7560
DDAG		 455/*
456 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
457 * Input:
458 * r0 = pointer to oldval
459 * r1 = pointer to newval
460 * r2 = pointer to target value
461 *
462 * Output:
463 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
464 * C set if *ptr was changed, clear if no exchange happened
465 *
466 * Note segv's in kernel helpers are a bit tricky, we can set the
467 * data address sensibly but the PC address is just the entry point.
468 */
469static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
470{
471 uint64_t oldval, newval, val;
472 uint32_t addr, cpsr;
473 target_siginfo_t info;
474
475 /* Based on the 32 bit code in do_kernel_trap */
476
477 /* XXX: This only works between threads, not between processes.
478 It's probably possible to implement this with native host
479 operations. However things like ldrex/strex are much harder so
480 there's not much point trying. */
481 start_exclusive();
482 cpsr = cpsr_read(env);
483 addr = env->regs[2];
484
485 if (get_user_u64(oldval, env->regs[0])) {
486 env->cp15.c6_data = env->regs[0];
487 goto segv;
488 };
489
490 if (get_user_u64(newval, env->regs[1])) {
491 env->cp15.c6_data = env->regs[1];
492 goto segv;
493 };
494
495 if (get_user_u64(val, addr)) {
496 env->cp15.c6_data = addr;
497 goto segv;
498 }
499
500 if (val == oldval) {
501 val = newval;
502
503 if (put_user_u64(val, addr)) {
504 env->cp15.c6_data = addr;
505 goto segv;
506 };
507
508 env->regs[0] = 0;
509 cpsr |= CPSR_C;
510 } else {
511 env->regs[0] = -1;
512 cpsr &= ~CPSR_C;
513 }
514 cpsr_write(env, cpsr, CPSR_C);
515 end_exclusive();
516 return;
517
518segv:
519 end_exclusive();
520 /* We get the PC of the entry address - which is as good as anything,
521 on a real kernel what you get depends on which mode it uses. */
522 info.si_signo = SIGSEGV;
523 info.si_errno = 0;
524 /* XXX: check env->error_code */
525 info.si_code = TARGET_SEGV_MAPERR;
526 info._sifields._sigfault._addr = env->cp15.c6_data;
527 queue_signal(env, info.si_signo, &info);
528
529 end_exclusive();
530}
531
fbb4a2e3
PB		 532/* Handle a jump to the kernel code page. */
533static int
534do_kernel_trap(CPUARMState *env)
535{
536 uint32_t addr;
537 uint32_t cpsr;
538 uint32_t val;
539
540 switch (env->regs[15]) {
541 case 0xffff0fa0: /* __kernel_memory_barrier */
542 /* ??? No-op. Will need to do better for SMP. */
543 break;
544 case 0xffff0fc0: /* __kernel_cmpxchg */
d5975363
PB		 545 /* XXX: This only works between threads, not between processes.
546 It's probably possible to implement this with native host
547 operations. However things like ldrex/strex are much harder so
548 there's not much point trying. */
549 start_exclusive();
fbb4a2e3
PB		 550 cpsr = cpsr_read(env);
551 addr = env->regs[2];
552 /* FIXME: This should SEGV if the access fails. */
553 if (get_user_u32(val, addr))
554 val = ~env->regs[0];
555 if (val == env->regs[0]) {
556 val = env->regs[1];
557 /* FIXME: Check for segfaults. */
558 put_user_u32(val, addr);
559 env->regs[0] = 0;
560 cpsr |= CPSR_C;
561 } else {
562 env->regs[0] = -1;
563 cpsr &= ~CPSR_C;
564 }
565 cpsr_write(env, cpsr, CPSR_C);
d5975363 566 end_exclusive();
fbb4a2e3
PB		 567 break;
568 case 0xffff0fe0: /* __kernel_get_tls */
e4fe830b 569 env->regs[0] = env->cp15.tpidrro_el0;
fbb4a2e3 570 break;
97cc7560
DDAG		 571 case 0xffff0f60: /* __kernel_cmpxchg64 */
572 arm_kernel_cmpxchg64_helper(env);
573 break;
574
fbb4a2e3
PB		 575 default:
576 return 1;
577 }
578 /* Jump back to the caller. */
579 addr = env->regs[14];
580 if (addr & 1) {
581 env->thumb = 1;
582 addr &= ~1;
583 }
584 env->regs[15] = addr;
585
586 return 0;
587}
588
fa2ef212 589/* Store exclusive handling for AArch32 */
426f5abc
PB		 590static int do_strex(CPUARMState *env)
591{
03d05e2d 592 uint64_t val;
426f5abc
PB		 593 int size;
594 int rc = 1;
595 int segv = 0;
596 uint32_t addr;
597 start_exclusive();
03d05e2d 598 if (env->exclusive_addr != env->exclusive_test) {
426f5abc
PB		 599 goto fail;
600 }
03d05e2d
PM		 601 /* We know we're always AArch32 so the address is in uint32_t range
602 * unless it was the -1 exclusive-monitor-lost value (which won't
603 * match exclusive_test above).
604 */
605 assert(extract64(env->exclusive_addr, 32, 32) == 0);
606 addr = env->exclusive_addr;
426f5abc
PB		 607 size = env->exclusive_info & 0xf;
608 switch (size) {
609 case 0:
610 segv = get_user_u8(val, addr);
611 break;
612 case 1:
613 segv = get_user_u16(val, addr);
614 break;
615 case 2:
616 case 3:
617 segv = get_user_u32(val, addr);
618 break;
f7001a3b
AJ		 619 default:
620 abort();
426f5abc
PB		 621 }
622 if (segv) {
623 env->cp15.c6_data = addr;
624 goto done;
625 }
426f5abc 626 if (size == 3) {
03d05e2d
PM		 627 uint32_t valhi;
628 segv = get_user_u32(valhi, addr + 4);
426f5abc
PB		 629 if (segv) {
630 env->cp15.c6_data = addr + 4;
631 goto done;
632 }
03d05e2d 633 val = deposit64(val, 32, 32, valhi);
426f5abc 634 }
03d05e2d
PM		 635 if (val != env->exclusive_val) {
636 goto fail;
637 }
638
426f5abc
PB		 639 val = env->regs[(env->exclusive_info >> 8) & 0xf];
640 switch (size) {
641 case 0:
642 segv = put_user_u8(val, addr);
643 break;
644 case 1:
645 segv = put_user_u16(val, addr);
646 break;
647 case 2:
648 case 3:
649 segv = put_user_u32(val, addr);
650 break;
651 }
652 if (segv) {
653 env->cp15.c6_data = addr;
654 goto done;
655 }
656 if (size == 3) {
657 val = env->regs[(env->exclusive_info >> 12) & 0xf];
2c9adbda 658 segv = put_user_u32(val, addr + 4);
426f5abc
PB		 659 if (segv) {
660 env->cp15.c6_data = addr + 4;
661 goto done;
662 }
663 }
664 rc = 0;
665fail:
725b8a69 666 env->regs[15] += 4;
426f5abc
PB		 667 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
668done:
669 end_exclusive();
670 return segv;
671}
672
b346ff46
FB		 673void cpu_loop(CPUARMState *env)
674{
0315c31c 675 CPUState *cs = CPU(arm_env_get_cpu(env));
b346ff46
FB		 676 int trapnr;
677 unsigned int n, insn;
c227f099 678 target_siginfo_t info;
b5ff1b31 679 uint32_t addr;
3b46e624 680
b346ff46 681 for(;;) {
0315c31c 682 cpu_exec_start(cs);
b346ff46 683 trapnr = cpu_arm_exec(env);
0315c31c 684 cpu_exec_end(cs);
b346ff46
FB		 685 switch(trapnr) {
686 case EXCP_UDEF:
c6981055 687 {
0429a971 688 TaskState *ts = cs->opaque;
c6981055 689 uint32_t opcode;
6d9a42be 690 int rc;
c6981055
FB		 691
692 /* we handle the FPU emulation here, as Linux */
693 /* we get the opcode */
2f619698 694 /* FIXME - what to do if get_user() fails? */
d8fd2954 695 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
3b46e624 696
6d9a42be
AJ		 697 rc = EmulateAll(opcode, &ts->fpa, env);
698 if (rc == 0) { /* illegal instruction */
c6981055
FB		 699 info.si_signo = SIGILL;
700 info.si_errno = 0;
701 info.si_code = TARGET_ILL_ILLOPN;
702 info._sifields._sigfault._addr = env->regs[15];
624f7979 703 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 704 } else if (rc < 0) { /* FP exception */
705 int arm_fpe=0;
706
707 /* translate softfloat flags to FPSR flags */
708 if (-rc & float_flag_invalid)
709 arm_fpe |= BIT_IOC;
710 if (-rc & float_flag_divbyzero)
711 arm_fpe |= BIT_DZC;
712 if (-rc & float_flag_overflow)
713 arm_fpe |= BIT_OFC;
714 if (-rc & float_flag_underflow)
715 arm_fpe |= BIT_UFC;
716 if (-rc & float_flag_inexact)
717 arm_fpe |= BIT_IXC;
718
719 FPSR fpsr = ts->fpa.fpsr;
720 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
721
722 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
723 info.si_signo = SIGFPE;
724 info.si_errno = 0;
725
726 /* ordered by priority, least first */
727 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
728 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
729 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
730 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
731 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
732
733 info._sifields._sigfault._addr = env->regs[15];
624f7979 734 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 735 } else {
736 env->regs[15] += 4;
737 }
738
739 /* accumulate unenabled exceptions */
740 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
741 fpsr |= BIT_IXC;
742 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
743 fpsr |= BIT_UFC;
744 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
745 fpsr |= BIT_OFC;
746 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
747 fpsr |= BIT_DZC;
748 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
749 fpsr |= BIT_IOC;
750 ts->fpa.fpsr=fpsr;
751 } else { /* everything OK */
c6981055
FB		 752 /* increment PC */
753 env->regs[15] += 4;
754 }
755 }
b346ff46
FB		 756 break;
757 case EXCP_SWI:
06c949e6 758 case EXCP_BKPT:
b346ff46 759 {
ce4defa0 760 env->eabi = 1;
b346ff46 761 /* system call */
06c949e6
PB		 762 if (trapnr == EXCP_BKPT) {
763 if (env->thumb) {
2f619698 764 /* FIXME - what to do if get_user() fails? */
d8fd2954 765 get_user_code_u16(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 766 n = insn & 0xff;
767 env->regs[15] += 2;
768 } else {
2f619698 769 /* FIXME - what to do if get_user() fails? */
d8fd2954 770 get_user_code_u32(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 771 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
772 env->regs[15] += 4;
773 }
192c7bd9 774 } else {
06c949e6 775 if (env->thumb) {
2f619698 776 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 777 get_user_code_u16(insn, env->regs[15] - 2,
778 env->bswap_code);
06c949e6
PB		 779 n = insn & 0xff;
780 } else {
2f619698 781 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 782 get_user_code_u32(insn, env->regs[15] - 4,
783 env->bswap_code);
06c949e6
PB		 784 n = insn & 0xffffff;
785 }
192c7bd9
FB		 786 }
787
6f1f31c0 788 if (n == ARM_NR_cacheflush) {
dcfd14b3 789 /* nop */
a4f81979
FB		 790 } else if (n == ARM_NR_semihosting
791 || n == ARM_NR_thumb_semihosting) {
792 env->regs[0] = do_arm_semihosting (env);
3a1363ac 793 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
b346ff46 794 /* linux syscall */
ce4defa0 795 if (env->thumb || n == 0) {
192c7bd9
FB		 796 n = env->regs[7];
797 } else {
798 n -= ARM_SYSCALL_BASE;
ce4defa0 799 env->eabi = 0;
192c7bd9 800 }
fbb4a2e3
PB		 801 if ( n > ARM_NR_BASE) {
802 switch (n) {
803 case ARM_NR_cacheflush:
dcfd14b3 804 /* nop */
fbb4a2e3
PB		 805 break;
806 case ARM_NR_set_tls:
807 cpu_set_tls(env, env->regs[0]);
808 env->regs[0] = 0;
809 break;
810 default:
811 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
812 n);
813 env->regs[0] = -TARGET_ENOSYS;
814 break;
815 }
816 } else {
817 env->regs[0] = do_syscall(env,
818 n,
819 env->regs[0],
820 env->regs[1],
821 env->regs[2],
822 env->regs[3],
823 env->regs[4],
5945cfcb
PM		 824 env->regs[5],
825 0, 0);
fbb4a2e3 826 }
b346ff46
FB		 827 } else {
828 goto error;
829 }
830 }
831 break;
43fff238
FB		 832 case EXCP_INTERRUPT:
833 /* just indicate that signals should be handled asap */
834 break;
68016c62 835 case EXCP_PREFETCH_ABORT:
eae473c1 836 addr = env->cp15.c6_insn;
b5ff1b31 837 goto do_segv;
68016c62 838 case EXCP_DATA_ABORT:
eae473c1 839 addr = env->cp15.c6_data;
b5ff1b31 840 do_segv:
68016c62
FB		 841 {
842 info.si_signo = SIGSEGV;
843 info.si_errno = 0;
844 /* XXX: check env->error_code */
845 info.si_code = TARGET_SEGV_MAPERR;
b5ff1b31 846 info._sifields._sigfault._addr = addr;
624f7979 847 queue_signal(env, info.si_signo, &info);
68016c62
FB		 848 }
849 break;
1fddef4b
FB		 850 case EXCP_DEBUG:
851 {
852 int sig;
853
db6b81d4 854 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 855 if (sig)
856 {
857 info.si_signo = sig;
858 info.si_errno = 0;
859 info.si_code = TARGET_TRAP_BRKPT;
624f7979 860 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 861 }
862 }
863 break;
fbb4a2e3
PB		 864 case EXCP_KERNEL_TRAP:
865 if (do_kernel_trap(env))
866 goto error;
867 break;
426f5abc
PB		 868 case EXCP_STREX:
869 if (do_strex(env)) {
870 addr = env->cp15.c6_data;
871 goto do_segv;
872 }
e9273455 873 break;
b346ff46
FB		 874 default:
875 error:
5fafdf24 876 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
b346ff46 877 trapnr);
878096ee 878 cpu_dump_state(cs, stderr, fprintf, 0);
b346ff46
FB		 879 abort();
880 }
881 process_pending_signals(env);
882 }
883}
884
1861c454
PM		 885#else
886
fa2ef212
MM		 887/*
888 * Handle AArch64 store-release exclusive
889 *
890 * rs = gets the status result of store exclusive
891 * rt = is the register that is stored
892 * rt2 = is the second register store (in STP)
893 *
894 */
895static int do_strex_a64(CPUARMState *env)
896{
897 uint64_t val;
898 int size;
899 bool is_pair;
900 int rc = 1;
901 int segv = 0;
902 uint64_t addr;
903 int rs, rt, rt2;
904
905 start_exclusive();
906 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
907 size = extract32(env->exclusive_info, 0, 2);
908 is_pair = extract32(env->exclusive_info, 2, 1);
909 rs = extract32(env->exclusive_info, 4, 5);
910 rt = extract32(env->exclusive_info, 9, 5);
911 rt2 = extract32(env->exclusive_info, 14, 5);
912
913 addr = env->exclusive_addr;
914
915 if (addr != env->exclusive_test) {
916 goto finish;
917 }
918
919 switch (size) {
920 case 0:
921 segv = get_user_u8(val, addr);
922 break;
923 case 1:
924 segv = get_user_u16(val, addr);
925 break;
926 case 2:
927 segv = get_user_u32(val, addr);
928 break;
929 case 3:
930 segv = get_user_u64(val, addr);
931 break;
932 default:
933 abort();
934 }
935 if (segv) {
936 env->cp15.c6_data = addr;
937 goto error;
938 }
939 if (val != env->exclusive_val) {
940 goto finish;
941 }
942 if (is_pair) {
943 if (size == 2) {
944 segv = get_user_u32(val, addr + 4);
945 } else {
946 segv = get_user_u64(val, addr + 8);
947 }
948 if (segv) {
949 env->cp15.c6_data = addr + (size == 2 ? 4 : 8);
950 goto error;
951 }
952 if (val != env->exclusive_high) {
953 goto finish;
954 }
955 }
2ea5a2ca
JG		 956 /* handle the zero register */
957 val = rt == 31 ? 0 : env->xregs[rt];
fa2ef212
MM		 958 switch (size) {
959 case 0:
960 segv = put_user_u8(val, addr);
961 break;
962 case 1:
963 segv = put_user_u16(val, addr);
964 break;
965 case 2:
966 segv = put_user_u32(val, addr);
967 break;
968 case 3:
969 segv = put_user_u64(val, addr);
970 break;
971 }
972 if (segv) {
973 goto error;
974 }
975 if (is_pair) {
2ea5a2ca
JG		 976 /* handle the zero register */
977 val = rt2 == 31 ? 0 : env->xregs[rt2];
fa2ef212
MM		 978 if (size == 2) {
979 segv = put_user_u32(val, addr + 4);
980 } else {
981 segv = put_user_u64(val, addr + 8);
982 }
983 if (segv) {
984 env->cp15.c6_data = addr + (size == 2 ? 4 : 8);
985 goto error;
986 }
987 }
988 rc = 0;
989finish:
990 env->pc += 4;
991 /* rs == 31 encodes a write to the ZR, thus throwing away
992 * the status return. This is rather silly but valid.
993 */
994 if (rs < 31) {
995 env->xregs[rs] = rc;
996 }
997error:
998 /* instruction faulted, PC does not advance */
999 /* either way a strex releases any exclusive lock we have */
1000 env->exclusive_addr = -1;
1001 end_exclusive();
1002 return segv;
1003}
1004
1861c454
PM		 1005/* AArch64 main loop */
1006void cpu_loop(CPUARMState *env)
1007{
1008 CPUState *cs = CPU(arm_env_get_cpu(env));
1009 int trapnr, sig;
1010 target_siginfo_t info;
1011 uint32_t addr;
1012
1013 for (;;) {
1014 cpu_exec_start(cs);
1015 trapnr = cpu_arm_exec(env);
1016 cpu_exec_end(cs);
1017
1018 switch (trapnr) {
1019 case EXCP_SWI:
1020 env->xregs[0] = do_syscall(env,
1021 env->xregs[8],
1022 env->xregs[0],
1023 env->xregs[1],
1024 env->xregs[2],
1025 env->xregs[3],
1026 env->xregs[4],
1027 env->xregs[5],
1028 0, 0);
1029 break;
1030 case EXCP_INTERRUPT:
1031 /* just indicate that signals should be handled asap */
1032 break;
1033 case EXCP_UDEF:
1034 info.si_signo = SIGILL;
1035 info.si_errno = 0;
1036 info.si_code = TARGET_ILL_ILLOPN;
1037 info._sifields._sigfault._addr = env->pc;
1038 queue_signal(env, info.si_signo, &info);
1039 break;
1040 case EXCP_PREFETCH_ABORT:
1041 addr = env->cp15.c6_insn;
1042 goto do_segv;
1043 case EXCP_DATA_ABORT:
1044 addr = env->cp15.c6_data;
1045 do_segv:
1046 info.si_signo = SIGSEGV;
1047 info.si_errno = 0;
1048 /* XXX: check env->error_code */
1049 info.si_code = TARGET_SEGV_MAPERR;
1050 info._sifields._sigfault._addr = addr;
1051 queue_signal(env, info.si_signo, &info);
1052 break;
1053 case EXCP_DEBUG:
1054 case EXCP_BKPT:
1055 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1056 if (sig) {
1057 info.si_signo = sig;
1058 info.si_errno = 0;
1059 info.si_code = TARGET_TRAP_BRKPT;
1060 queue_signal(env, info.si_signo, &info);
1061 }
1062 break;
1063 case EXCP_STREX:
fa2ef212 1064 if (do_strex_a64(env)) {
1861c454
PM		 1065 addr = env->cp15.c6_data;
1066 goto do_segv;
1067 }
1068 break;
1069 default:
1070 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
1071 trapnr);
1072 cpu_dump_state(cs, stderr, fprintf, 0);
1073 abort();
1074 }
1075 process_pending_signals(env);
fa2ef212
MM		 1076 /* Exception return on AArch64 always clears the exclusive monitor,
1077 * so any return to running guest code implies this.
1078 * A strex (successful or otherwise) also clears the monitor, so
1079 * we don't need to specialcase EXCP_STREX.
1080 */
1081 env->exclusive_addr = -1;
1861c454
PM		 1082 }
1083}
1084#endif /* ndef TARGET_ABI32 */
1085
b346ff46 1086#endif
1b6b029e 1087
d2fbca94
GX		 1088#ifdef TARGET_UNICORE32
1089
05390248 1090void cpu_loop(CPUUniCore32State *env)
d2fbca94 1091{
0315c31c 1092 CPUState *cs = CPU(uc32_env_get_cpu(env));
d2fbca94
GX		 1093 int trapnr;
1094 unsigned int n, insn;
1095 target_siginfo_t info;
1096
1097 for (;;) {
0315c31c 1098 cpu_exec_start(cs);
d2fbca94 1099 trapnr = uc32_cpu_exec(env);
0315c31c 1100 cpu_exec_end(cs);
d2fbca94
GX		 1101 switch (trapnr) {
1102 case UC32_EXCP_PRIV:
1103 {
1104 /* system call */
1105 get_user_u32(insn, env->regs[31] - 4);
1106 n = insn & 0xffffff;
1107
1108 if (n >= UC32_SYSCALL_BASE) {
1109 /* linux syscall */
1110 n -= UC32_SYSCALL_BASE;
1111 if (n == UC32_SYSCALL_NR_set_tls) {
1112 cpu_set_tls(env, env->regs[0]);
1113 env->regs[0] = 0;
1114 } else {
1115 env->regs[0] = do_syscall(env,
1116 n,
1117 env->regs[0],
1118 env->regs[1],
1119 env->regs[2],
1120 env->regs[3],
1121 env->regs[4],
5945cfcb
PM		 1122 env->regs[5],
1123 0, 0);
d2fbca94
GX		 1124 }
1125 } else {
1126 goto error;
1127 }
1128 }
1129 break;
d48813dd
GX		 1130 case UC32_EXCP_DTRAP:
1131 case UC32_EXCP_ITRAP:
d2fbca94
GX		 1132 info.si_signo = SIGSEGV;
1133 info.si_errno = 0;
1134 /* XXX: check env->error_code */
1135 info.si_code = TARGET_SEGV_MAPERR;
1136 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1137 queue_signal(env, info.si_signo, &info);
1138 break;
1139 case EXCP_INTERRUPT:
1140 /* just indicate that signals should be handled asap */
1141 break;
1142 case EXCP_DEBUG:
1143 {
1144 int sig;
1145
db6b81d4 1146 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d2fbca94
GX		 1147 if (sig) {
1148 info.si_signo = sig;
1149 info.si_errno = 0;
1150 info.si_code = TARGET_TRAP_BRKPT;
1151 queue_signal(env, info.si_signo, &info);
1152 }
1153 }
1154 break;
1155 default:
1156 goto error;
1157 }
1158 process_pending_signals(env);
1159 }
1160
1161error:
1162 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
878096ee 1163 cpu_dump_state(cs, stderr, fprintf, 0);
d2fbca94
GX		 1164 abort();
1165}
1166#endif
1167
93ac68bc 1168#ifdef TARGET_SPARC
ed23fbd9 1169#define SPARC64_STACK_BIAS 2047
93ac68bc 1170
060366c5
FB		 1171//#define DEBUG_WIN
1172
2623cbaf
FB		 1173/* WARNING: dealing with register windows _is_ complicated. More info
1174 can be found at http://www.sics.se/~psm/sparcstack.html */
060366c5
FB		 1175static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1176{
1a14026e 1177 index = (index + cwp * 16) % (16 * env->nwindows);
060366c5
FB		 1178 /* wrap handling : if cwp is on the last window, then we use the
1179 registers 'after' the end */
1a14026e
BS		 1180 if (index < 8 && env->cwp == env->nwindows - 1)
1181 index += 16 * env->nwindows;
060366c5
FB		 1182 return index;
1183}
1184
2623cbaf
FB		 1185/* save the register window 'cwp1' */
1186static inline void save_window_offset(CPUSPARCState *env, int cwp1)
060366c5 1187{
2623cbaf 1188 unsigned int i;
992f48a0 1189 abi_ulong sp_ptr;
3b46e624 1190
53a5960a 1191 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1192#ifdef TARGET_SPARC64
1193 if (sp_ptr & 3)
1194 sp_ptr += SPARC64_STACK_BIAS;
1195#endif
060366c5 1196#if defined(DEBUG_WIN)
2daf0284
BS		 1197 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1198 sp_ptr, cwp1);
060366c5 1199#endif
2623cbaf 1200 for(i = 0; i < 16; i++) {
2f619698
FB		 1201 /* FIXME - what to do if put_user() fails? */
1202 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1203 sp_ptr += sizeof(abi_ulong);
2623cbaf 1204 }
060366c5
FB		 1205}
1206
1207static void save_window(CPUSPARCState *env)
1208{
5ef54116 1209#ifndef TARGET_SPARC64
2623cbaf 1210 unsigned int new_wim;
1a14026e
BS		 1211 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1212 ((1LL << env->nwindows) - 1);
1213 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
2623cbaf 1214 env->wim = new_wim;
5ef54116 1215#else
1a14026e 1216 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
5ef54116
FB		 1217 env->cansave++;
1218 env->canrestore--;
1219#endif
060366c5
FB		 1220}
1221
1222static void restore_window(CPUSPARCState *env)
1223{
eda52953
BS		 1224#ifndef TARGET_SPARC64
1225 unsigned int new_wim;
1226#endif
1227 unsigned int i, cwp1;
992f48a0 1228 abi_ulong sp_ptr;
3b46e624 1229
eda52953 1230#ifndef TARGET_SPARC64
1a14026e
BS		 1231 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1232 ((1LL << env->nwindows) - 1);
eda52953 1233#endif
3b46e624 1234
060366c5 1235 /* restore the invalid window */
1a14026e 1236 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
53a5960a 1237 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1238#ifdef TARGET_SPARC64
1239 if (sp_ptr & 3)
1240 sp_ptr += SPARC64_STACK_BIAS;
1241#endif
060366c5 1242#if defined(DEBUG_WIN)
2daf0284
BS		 1243 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1244 sp_ptr, cwp1);
060366c5 1245#endif
2623cbaf 1246 for(i = 0; i < 16; i++) {
2f619698
FB		 1247 /* FIXME - what to do if get_user() fails? */
1248 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1249 sp_ptr += sizeof(abi_ulong);
2623cbaf 1250 }
5ef54116
FB		 1251#ifdef TARGET_SPARC64
1252 env->canrestore++;
1a14026e
BS		 1253 if (env->cleanwin < env->nwindows - 1)
1254 env->cleanwin++;
5ef54116 1255 env->cansave--;
eda52953
BS		 1256#else
1257 env->wim = new_wim;
5ef54116 1258#endif
060366c5
FB		 1259}
1260
1261static void flush_windows(CPUSPARCState *env)
1262{
1263 int offset, cwp1;
2623cbaf
FB		 1264
1265 offset = 1;
060366c5
FB		 1266 for(;;) {
1267 /* if restore would invoke restore_window(), then we can stop */
1a14026e 1268 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
eda52953 1269#ifndef TARGET_SPARC64
060366c5
FB		 1270 if (env->wim & (1 << cwp1))
1271 break;
eda52953
BS		 1272#else
1273 if (env->canrestore == 0)
1274 break;
1275 env->cansave++;
1276 env->canrestore--;
1277#endif
2623cbaf 1278 save_window_offset(env, cwp1);
060366c5
FB		 1279 offset++;
1280 }
1a14026e 1281 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
eda52953
BS		 1282#ifndef TARGET_SPARC64
1283 /* set wim so that restore will reload the registers */
2623cbaf 1284 env->wim = 1 << cwp1;
eda52953 1285#endif
2623cbaf
FB		 1286#if defined(DEBUG_WIN)
1287 printf("flush_windows: nb=%d\n", offset - 1);
80a9d035 1288#endif
2623cbaf 1289}
060366c5 1290
93ac68bc
FB		 1291void cpu_loop (CPUSPARCState *env)
1292{
878096ee 1293 CPUState *cs = CPU(sparc_env_get_cpu(env));
2cc20260
RH		 1294 int trapnr;
1295 abi_long ret;
c227f099 1296 target_siginfo_t info;
3b46e624 1297
060366c5
FB		 1298 while (1) {
1299 trapnr = cpu_sparc_exec (env);
3b46e624 1300
20132b96
RH		 1301 /* Compute PSR before exposing state. */
1302 if (env->cc_op != CC_OP_FLAGS) {
1303 cpu_get_psr(env);
1304 }
1305
060366c5 1306 switch (trapnr) {
5ef54116 1307#ifndef TARGET_SPARC64
5fafdf24 1308 case 0x88:
060366c5 1309 case 0x90:
5ef54116 1310#else
cb33da57 1311 case 0x110:
5ef54116
FB		 1312 case 0x16d:
1313#endif
060366c5 1314 ret = do_syscall (env, env->gregs[1],
5fafdf24
TS		 1315 env->regwptr[0], env->regwptr[1],
1316 env->regwptr[2], env->regwptr[3],
5945cfcb
PM		 1317 env->regwptr[4], env->regwptr[5],
1318 0, 0);
2cc20260 1319 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
992f48a0 1320#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1321 env->xcc |= PSR_CARRY;
1322#else
060366c5 1323 env->psr |= PSR_CARRY;
27908725 1324#endif
060366c5
FB		 1325 ret = -ret;
1326 } else {
992f48a0 1327#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1328 env->xcc &= ~PSR_CARRY;
1329#else
060366c5 1330 env->psr &= ~PSR_CARRY;
27908725 1331#endif
060366c5
FB		 1332 }
1333 env->regwptr[0] = ret;
1334 /* next instruction */
1335 env->pc = env->npc;
1336 env->npc = env->npc + 4;
1337 break;
1338 case 0x83: /* flush windows */
992f48a0
BS		 1339#ifdef TARGET_ABI32
1340 case 0x103:
1341#endif
2623cbaf 1342 flush_windows(env);
060366c5
FB		 1343 /* next instruction */
1344 env->pc = env->npc;
1345 env->npc = env->npc + 4;
1346 break;
3475187d 1347#ifndef TARGET_SPARC64
060366c5
FB		 1348 case TT_WIN_OVF: /* window overflow */
1349 save_window(env);
1350 break;
1351 case TT_WIN_UNF: /* window underflow */
1352 restore_window(env);
1353 break;
61ff6f58
FB		 1354 case TT_TFAULT:
1355 case TT_DFAULT:
1356 {
59f7182f 1357 info.si_signo = TARGET_SIGSEGV;
61ff6f58
FB		 1358 info.si_errno = 0;
1359 /* XXX: check env->error_code */
1360 info.si_code = TARGET_SEGV_MAPERR;
1361 info._sifields._sigfault._addr = env->mmuregs[4];
624f7979 1362 queue_signal(env, info.si_signo, &info);
61ff6f58
FB		 1363 }
1364 break;
3475187d 1365#else
5ef54116
FB		 1366 case TT_SPILL: /* window overflow */
1367 save_window(env);
1368 break;
1369 case TT_FILL: /* window underflow */
1370 restore_window(env);
1371 break;
7f84a729
BS		 1372 case TT_TFAULT:
1373 case TT_DFAULT:
1374 {
59f7182f 1375 info.si_signo = TARGET_SIGSEGV;
7f84a729
BS		 1376 info.si_errno = 0;
1377 /* XXX: check env->error_code */
1378 info.si_code = TARGET_SEGV_MAPERR;
1379 if (trapnr == TT_DFAULT)
1380 info._sifields._sigfault._addr = env->dmmuregs[4];
1381 else
8194f35a 1382 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
624f7979 1383 queue_signal(env, info.si_signo, &info);
7f84a729
BS		 1384 }
1385 break;
27524dc3 1386#ifndef TARGET_ABI32
5bfb56b2
BS		 1387 case 0x16e:
1388 flush_windows(env);
1389 sparc64_get_context(env);
1390 break;
1391 case 0x16f:
1392 flush_windows(env);
1393 sparc64_set_context(env);
1394 break;
27524dc3 1395#endif
3475187d 1396#endif
48dc41eb
FB		 1397 case EXCP_INTERRUPT:
1398 /* just indicate that signals should be handled asap */
1399 break;
75f22e4e
RH		 1400 case TT_ILL_INSN:
1401 {
1402 info.si_signo = TARGET_SIGILL;
1403 info.si_errno = 0;
1404 info.si_code = TARGET_ILL_ILLOPC;
1405 info._sifields._sigfault._addr = env->pc;
1406 queue_signal(env, info.si_signo, &info);
1407 }
1408 break;
1fddef4b
FB		 1409 case EXCP_DEBUG:
1410 {
1411 int sig;
1412
db6b81d4 1413 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 1414 if (sig)
1415 {
1416 info.si_signo = sig;
1417 info.si_errno = 0;
1418 info.si_code = TARGET_TRAP_BRKPT;
624f7979 1419 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 1420 }
1421 }
1422 break;
060366c5
FB		 1423 default:
1424 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 1425 cpu_dump_state(cs, stderr, fprintf, 0);
060366c5
FB		 1426 exit (1);
1427 }
1428 process_pending_signals (env);
1429 }
93ac68bc
FB		 1430}
1431
1432#endif
1433
67867308 1434#ifdef TARGET_PPC
05390248 1435static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
9fddaa0c
FB		 1436{
1437 /* TO FIX */
1438 return 0;
1439}
3b46e624 1440
05390248 1441uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
9fddaa0c 1442{
e3ea6529 1443 return cpu_ppc_get_tb(env);
9fddaa0c 1444}
3b46e624 1445
05390248 1446uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
9fddaa0c
FB		 1447{
1448 return cpu_ppc_get_tb(env) >> 32;
1449}
3b46e624 1450
05390248 1451uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
9fddaa0c 1452{
b711de95 1453 return cpu_ppc_get_tb(env);
9fddaa0c 1454}
5fafdf24 1455
05390248 1456uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
9fddaa0c 1457{
a062e36c 1458 return cpu_ppc_get_tb(env) >> 32;
9fddaa0c 1459}
76a66253 1460
05390248 1461uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
76a66253
JM		 1462__attribute__ (( alias ("cpu_ppc_load_tbu") ));
1463
05390248 1464uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
9fddaa0c 1465{
76a66253 1466 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
9fddaa0c 1467}
76a66253 1468
a750fc0b 1469/* XXX: to be fixed */
73b01960 1470int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
a750fc0b
JM		 1471{
1472 return -1;
1473}
1474
73b01960 1475int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
a750fc0b
JM		 1476{
1477 return -1;
1478}
1479
001faf32
BS		 1480#define EXCP_DUMP(env, fmt, ...) \
1481do { \
a0762859 1482 CPUState *cs = ENV_GET_CPU(env); \
001faf32 1483 fprintf(stderr, fmt , ## __VA_ARGS__); \
a0762859 1484 cpu_dump_state(cs, stderr, fprintf, 0); \
001faf32 1485 qemu_log(fmt, ## __VA_ARGS__); \
eeacee4d 1486 if (qemu_log_enabled()) { \
a0762859 1487 log_cpu_state(cs, 0); \
eeacee4d 1488 } \
e1833e1f
JM		 1489} while (0)
1490
56f066bb
NF		 1491static int do_store_exclusive(CPUPPCState *env)
1492{
1493 target_ulong addr;
1494 target_ulong page_addr;
27b95bfe 1495 target_ulong val, val2 __attribute__((unused));
56f066bb
NF		 1496 int flags;
1497 int segv = 0;
1498
1499 addr = env->reserve_ea;
1500 page_addr = addr & TARGET_PAGE_MASK;
1501 start_exclusive();
1502 mmap_lock();
1503 flags = page_get_flags(page_addr);
1504 if ((flags & PAGE_READ) == 0) {
1505 segv = 1;
1506 } else {
1507 int reg = env->reserve_info & 0x1f;
1508 int size = (env->reserve_info >> 5) & 0xf;
1509 int stored = 0;
1510
1511 if (addr == env->reserve_addr) {
1512 switch (size) {
1513 case 1: segv = get_user_u8(val, addr); break;
1514 case 2: segv = get_user_u16(val, addr); break;
1515 case 4: segv = get_user_u32(val, addr); break;
1516#if defined(TARGET_PPC64)
1517 case 8: segv = get_user_u64(val, addr); break;
27b95bfe
TM		 1518 case 16: {
1519 segv = get_user_u64(val, addr);
1520 if (!segv) {
1521 segv = get_user_u64(val2, addr + 8);
1522 }
1523 break;
1524 }
56f066bb
NF		 1525#endif
1526 default: abort();
1527 }
1528 if (!segv && val == env->reserve_val) {
1529 val = env->gpr[reg];
1530 switch (size) {
1531 case 1: segv = put_user_u8(val, addr); break;
1532 case 2: segv = put_user_u16(val, addr); break;
1533 case 4: segv = put_user_u32(val, addr); break;
1534#if defined(TARGET_PPC64)
1535 case 8: segv = put_user_u64(val, addr); break;
27b95bfe
TM		 1536 case 16: {
1537 if (val2 == env->reserve_val2) {
1538 segv = put_user_u64(val, addr);
1539 if (!segv) {
1540 segv = put_user_u64(val2, addr + 8);
1541 }
1542 }
1543 break;
1544 }
56f066bb
NF		 1545#endif
1546 default: abort();
1547 }
1548 if (!segv) {
1549 stored = 1;
1550 }
1551 }
1552 }
1553 env->crf[0] = (stored << 1) | xer_so;
1554 env->reserve_addr = (target_ulong)-1;
1555 }
1556 if (!segv) {
1557 env->nip += 4;
1558 }
1559 mmap_unlock();
1560 end_exclusive();
1561 return segv;
1562}
1563
67867308
FB		 1564void cpu_loop(CPUPPCState *env)
1565{
0315c31c 1566 CPUState *cs = CPU(ppc_env_get_cpu(env));
c227f099 1567 target_siginfo_t info;
61190b14 1568 int trapnr;
9e0e2f96 1569 target_ulong ret;
3b46e624 1570
67867308 1571 for(;;) {
0315c31c 1572 cpu_exec_start(cs);
67867308 1573 trapnr = cpu_ppc_exec(env);
0315c31c 1574 cpu_exec_end(cs);
67867308 1575 switch(trapnr) {
e1833e1f
JM		 1576 case POWERPC_EXCP_NONE:
1577 /* Just go on */
67867308 1578 break;
e1833e1f 1579 case POWERPC_EXCP_CRITICAL: /* Critical input */
a47dddd7 1580 cpu_abort(cs, "Critical interrupt while in user mode. "
e1833e1f 1581 "Aborting\n");
61190b14 1582 break;
e1833e1f 1583 case POWERPC_EXCP_MCHECK: /* Machine check exception */
a47dddd7 1584 cpu_abort(cs, "Machine check exception while in user mode. "
e1833e1f
JM		 1585 "Aborting\n");
1586 break;
1587 case POWERPC_EXCP_DSI: /* Data storage exception */
90e189ec 1588 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
e1833e1f
JM		 1589 env->spr[SPR_DAR]);
1590 /* XXX: check this. Seems bugged */
2be0071f
FB		 1591 switch (env->error_code & 0xFF000000) {
1592 case 0x40000000:
61190b14
FB		 1593 info.si_signo = TARGET_SIGSEGV;
1594 info.si_errno = 0;
1595 info.si_code = TARGET_SEGV_MAPERR;
1596 break;
2be0071f 1597 case 0x04000000:
61190b14
FB		 1598 info.si_signo = TARGET_SIGILL;
1599 info.si_errno = 0;
1600 info.si_code = TARGET_ILL_ILLADR;
1601 break;
2be0071f 1602 case 0x08000000:
61190b14
FB		 1603 info.si_signo = TARGET_SIGSEGV;
1604 info.si_errno = 0;
1605 info.si_code = TARGET_SEGV_ACCERR;
1606 break;
61190b14
FB		 1607 default:
1608 /* Let's send a regular segfault... */
e1833e1f
JM		 1609 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1610 env->error_code);
61190b14
FB		 1611 info.si_signo = TARGET_SIGSEGV;
1612 info.si_errno = 0;
1613 info.si_code = TARGET_SEGV_MAPERR;
1614 break;
1615 }
67867308 1616 info._sifields._sigfault._addr = env->nip;
624f7979 1617 queue_signal(env, info.si_signo, &info);
67867308 1618 break;
e1833e1f 1619 case POWERPC_EXCP_ISI: /* Instruction storage exception */
90e189ec
BS		 1620 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1621 "\n", env->spr[SPR_SRR0]);
e1833e1f 1622 /* XXX: check this */
2be0071f
FB		 1623 switch (env->error_code & 0xFF000000) {
1624 case 0x40000000:
61190b14 1625 info.si_signo = TARGET_SIGSEGV;
67867308 1626 info.si_errno = 0;
61190b14
FB		 1627 info.si_code = TARGET_SEGV_MAPERR;
1628 break;
2be0071f
FB		 1629 case 0x10000000:
1630 case 0x08000000:
61190b14
FB		 1631 info.si_signo = TARGET_SIGSEGV;
1632 info.si_errno = 0;
1633 info.si_code = TARGET_SEGV_ACCERR;
1634 break;
1635 default:
1636 /* Let's send a regular segfault... */
e1833e1f
JM		 1637 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1638 env->error_code);
61190b14
FB		 1639 info.si_signo = TARGET_SIGSEGV;
1640 info.si_errno = 0;
1641 info.si_code = TARGET_SEGV_MAPERR;
1642 break;
1643 }
1644 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1645 queue_signal(env, info.si_signo, &info);
67867308 1646 break;
e1833e1f 1647 case POWERPC_EXCP_EXTERNAL: /* External input */
a47dddd7 1648 cpu_abort(cs, "External interrupt while in user mode. "
e1833e1f
JM		 1649 "Aborting\n");
1650 break;
1651 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1652 EXCP_DUMP(env, "Unaligned memory access\n");
1653 /* XXX: check this */
61190b14 1654 info.si_signo = TARGET_SIGBUS;
67867308 1655 info.si_errno = 0;
61190b14
FB		 1656 info.si_code = TARGET_BUS_ADRALN;
1657 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1658 queue_signal(env, info.si_signo, &info);
67867308 1659 break;
e1833e1f
JM		 1660 case POWERPC_EXCP_PROGRAM: /* Program exception */
1661 /* XXX: check this */
61190b14 1662 switch (env->error_code & ~0xF) {
e1833e1f
JM		 1663 case POWERPC_EXCP_FP:
1664 EXCP_DUMP(env, "Floating point program exception\n");
61190b14
FB		 1665 info.si_signo = TARGET_SIGFPE;
1666 info.si_errno = 0;
1667 switch (env->error_code & 0xF) {
e1833e1f 1668 case POWERPC_EXCP_FP_OX:
61190b14
FB		 1669 info.si_code = TARGET_FPE_FLTOVF;
1670 break;
e1833e1f 1671 case POWERPC_EXCP_FP_UX:
61190b14
FB		 1672 info.si_code = TARGET_FPE_FLTUND;
1673 break;
e1833e1f
JM		 1674 case POWERPC_EXCP_FP_ZX:
1675 case POWERPC_EXCP_FP_VXZDZ:
61190b14
FB		 1676 info.si_code = TARGET_FPE_FLTDIV;
1677 break;
e1833e1f 1678 case POWERPC_EXCP_FP_XX:
61190b14
FB		 1679 info.si_code = TARGET_FPE_FLTRES;
1680 break;
e1833e1f 1681 case POWERPC_EXCP_FP_VXSOFT:
61190b14
FB		 1682 info.si_code = TARGET_FPE_FLTINV;
1683 break;
7c58044c 1684 case POWERPC_EXCP_FP_VXSNAN:
e1833e1f
JM		 1685 case POWERPC_EXCP_FP_VXISI:
1686 case POWERPC_EXCP_FP_VXIDI:
1687 case POWERPC_EXCP_FP_VXIMZ:
1688 case POWERPC_EXCP_FP_VXVC:
1689 case POWERPC_EXCP_FP_VXSQRT:
1690 case POWERPC_EXCP_FP_VXCVI:
61190b14
FB		 1691 info.si_code = TARGET_FPE_FLTSUB;
1692 break;
1693 default:
e1833e1f
JM		 1694 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1695 env->error_code);
1696 break;
61190b14 1697 }
e1833e1f
JM		 1698 break;
1699 case POWERPC_EXCP_INVAL:
1700 EXCP_DUMP(env, "Invalid instruction\n");
61190b14
FB		 1701 info.si_signo = TARGET_SIGILL;
1702 info.si_errno = 0;
1703 switch (env->error_code & 0xF) {
e1833e1f 1704 case POWERPC_EXCP_INVAL_INVAL:
61190b14
FB		 1705 info.si_code = TARGET_ILL_ILLOPC;
1706 break;
e1833e1f 1707 case POWERPC_EXCP_INVAL_LSWX:
a750fc0b 1708 info.si_code = TARGET_ILL_ILLOPN;
61190b14 1709 break;
e1833e1f 1710 case POWERPC_EXCP_INVAL_SPR:
61190b14
FB		 1711 info.si_code = TARGET_ILL_PRVREG;
1712 break;
e1833e1f 1713 case POWERPC_EXCP_INVAL_FP:
61190b14
FB		 1714 info.si_code = TARGET_ILL_COPROC;
1715 break;
1716 default:
e1833e1f
JM		 1717 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1718 env->error_code & 0xF);
61190b14
FB		 1719 info.si_code = TARGET_ILL_ILLADR;
1720 break;
1721 }
1722 break;
e1833e1f
JM		 1723 case POWERPC_EXCP_PRIV:
1724 EXCP_DUMP(env, "Privilege violation\n");
61190b14
FB		 1725 info.si_signo = TARGET_SIGILL;
1726 info.si_errno = 0;
1727 switch (env->error_code & 0xF) {
e1833e1f 1728 case POWERPC_EXCP_PRIV_OPC:
61190b14
FB		 1729 info.si_code = TARGET_ILL_PRVOPC;
1730 break;
e1833e1f 1731 case POWERPC_EXCP_PRIV_REG:
61190b14 1732 info.si_code = TARGET_ILL_PRVREG;
e1833e1f 1733 break;
61190b14 1734 default:
e1833e1f
JM		 1735 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1736 env->error_code & 0xF);
61190b14
FB		 1737 info.si_code = TARGET_ILL_PRVOPC;
1738 break;
1739 }
1740 break;
e1833e1f 1741 case POWERPC_EXCP_TRAP:
a47dddd7 1742 cpu_abort(cs, "Tried to call a TRAP\n");
e1833e1f 1743 break;
61190b14
FB		 1744 default:
1745 /* Should not happen ! */
a47dddd7 1746 cpu_abort(cs, "Unknown program exception (%02x)\n",
e1833e1f
JM		 1747 env->error_code);
1748 break;
61190b14
FB		 1749 }
1750 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1751 queue_signal(env, info.si_signo, &info);
67867308 1752 break;
e1833e1f
JM		 1753 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1754 EXCP_DUMP(env, "No floating point allowed\n");
61190b14 1755 info.si_signo = TARGET_SIGILL;
67867308 1756 info.si_errno = 0;
61190b14
FB		 1757 info.si_code = TARGET_ILL_COPROC;
1758 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1759 queue_signal(env, info.si_signo, &info);
67867308 1760 break;
e1833e1f 1761 case POWERPC_EXCP_SYSCALL: /* System call exception */
a47dddd7 1762 cpu_abort(cs, "Syscall exception while in user mode. "
e1833e1f 1763 "Aborting\n");
61190b14 1764 break;
e1833e1f
JM		 1765 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1766 EXCP_DUMP(env, "No APU instruction allowed\n");
1767 info.si_signo = TARGET_SIGILL;
1768 info.si_errno = 0;
1769 info.si_code = TARGET_ILL_COPROC;
1770 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1771 queue_signal(env, info.si_signo, &info);
61190b14 1772 break;
e1833e1f 1773 case POWERPC_EXCP_DECR: /* Decrementer exception */
a47dddd7 1774 cpu_abort(cs, "Decrementer interrupt while in user mode. "
e1833e1f 1775 "Aborting\n");
61190b14 1776 break;
e1833e1f 1777 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
a47dddd7 1778 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
e1833e1f
JM		 1779 "Aborting\n");
1780 break;
1781 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
a47dddd7 1782 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
e1833e1f
JM		 1783 "Aborting\n");
1784 break;
1785 case POWERPC_EXCP_DTLB: /* Data TLB error */
a47dddd7 1786 cpu_abort(cs, "Data TLB exception while in user mode. "
e1833e1f
JM		 1787 "Aborting\n");
1788 break;
1789 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
a47dddd7 1790 cpu_abort(cs, "Instruction TLB exception while in user mode. "
e1833e1f
JM		 1791 "Aborting\n");
1792 break;
e1833e1f
JM		 1793 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1794 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1795 info.si_signo = TARGET_SIGILL;
1796 info.si_errno = 0;
1797 info.si_code = TARGET_ILL_COPROC;
1798 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1799 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1800 break;
1801 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
a47dddd7 1802 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
e1833e1f
JM		 1803 break;
1804 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
a47dddd7 1805 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
e1833e1f
JM		 1806 break;
1807 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
a47dddd7 1808 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1809 break;
1810 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
a47dddd7 1811 cpu_abort(cs, "Doorbell interrupt while in user mode. "
e1833e1f
JM		 1812 "Aborting\n");
1813 break;
1814 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
a47dddd7 1815 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
e1833e1f
JM		 1816 "Aborting\n");
1817 break;
1818 case POWERPC_EXCP_RESET: /* System reset exception */
a47dddd7 1819 cpu_abort(cs, "Reset interrupt while in user mode. "
e1833e1f
JM		 1820 "Aborting\n");
1821 break;
e1833e1f 1822 case POWERPC_EXCP_DSEG: /* Data segment exception */
a47dddd7 1823 cpu_abort(cs, "Data segment exception while in user mode. "
e1833e1f
JM		 1824 "Aborting\n");
1825 break;
1826 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
a47dddd7 1827 cpu_abort(cs, "Instruction segment exception "
e1833e1f
JM		 1828 "while in user mode. Aborting\n");
1829 break;
e85e7c6e 1830 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1831 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
a47dddd7 1832 cpu_abort(cs, "Hypervisor decrementer interrupt "
e1833e1f
JM		 1833 "while in user mode. Aborting\n");
1834 break;
e1833e1f
JM		 1835 case POWERPC_EXCP_TRACE: /* Trace exception */
1836 /* Nothing to do:
1837 * we use this exception to emulate step-by-step execution mode.
1838 */
1839 break;
e85e7c6e 1840 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1841 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
a47dddd7 1842 cpu_abort(cs, "Hypervisor data storage exception "
e1833e1f
JM		 1843 "while in user mode. Aborting\n");
1844 break;
1845 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
a47dddd7 1846 cpu_abort(cs, "Hypervisor instruction storage exception "
e1833e1f
JM		 1847 "while in user mode. Aborting\n");
1848 break;
1849 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
a47dddd7 1850 cpu_abort(cs, "Hypervisor data segment exception "
e1833e1f
JM		 1851 "while in user mode. Aborting\n");
1852 break;
1853 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
a47dddd7 1854 cpu_abort(cs, "Hypervisor instruction segment exception "
e1833e1f
JM		 1855 "while in user mode. Aborting\n");
1856 break;
e1833e1f
JM		 1857 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1858 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1859 info.si_signo = TARGET_SIGILL;
1860 info.si_errno = 0;
1861 info.si_code = TARGET_ILL_COPROC;
1862 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1863 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1864 break;
1865 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
a47dddd7 1866 cpu_abort(cs, "Programmable interval timer interrupt "
e1833e1f
JM		 1867 "while in user mode. Aborting\n");
1868 break;
1869 case POWERPC_EXCP_IO: /* IO error exception */
a47dddd7 1870 cpu_abort(cs, "IO error exception while in user mode. "
e1833e1f
JM		 1871 "Aborting\n");
1872 break;
1873 case POWERPC_EXCP_RUNM: /* Run mode exception */
a47dddd7 1874 cpu_abort(cs, "Run mode exception while in user mode. "
e1833e1f
JM		 1875 "Aborting\n");
1876 break;
1877 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
a47dddd7 1878 cpu_abort(cs, "Emulation trap exception not handled\n");
e1833e1f
JM		 1879 break;
1880 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
a47dddd7 1881 cpu_abort(cs, "Instruction fetch TLB exception "
e1833e1f
JM		 1882 "while in user-mode. Aborting");
1883 break;
1884 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
a47dddd7 1885 cpu_abort(cs, "Data load TLB exception while in user-mode. "
e1833e1f
JM		 1886 "Aborting");
1887 break;
1888 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
a47dddd7 1889 cpu_abort(cs, "Data store TLB exception while in user-mode. "
e1833e1f
JM		 1890 "Aborting");
1891 break;
1892 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
a47dddd7 1893 cpu_abort(cs, "Floating-point assist exception not handled\n");
e1833e1f
JM		 1894 break;
1895 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
a47dddd7 1896 cpu_abort(cs, "Instruction address breakpoint exception "
e1833e1f
JM		 1897 "not handled\n");
1898 break;
1899 case POWERPC_EXCP_SMI: /* System management interrupt */
a47dddd7 1900 cpu_abort(cs, "System management interrupt while in user mode. "
e1833e1f
JM		 1901 "Aborting\n");
1902 break;
1903 case POWERPC_EXCP_THERM: /* Thermal interrupt */
a47dddd7 1904 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
e1833e1f
JM		 1905 "Aborting\n");
1906 break;
1907 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
a47dddd7 1908 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1909 break;
1910 case POWERPC_EXCP_VPUA: /* Vector assist exception */
a47dddd7 1911 cpu_abort(cs, "Vector assist exception not handled\n");
e1833e1f
JM		 1912 break;
1913 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
a47dddd7 1914 cpu_abort(cs, "Soft patch exception not handled\n");
e1833e1f
JM		 1915 break;
1916 case POWERPC_EXCP_MAINT: /* Maintenance exception */
a47dddd7 1917 cpu_abort(cs, "Maintenance exception while in user mode. "
e1833e1f
JM		 1918 "Aborting\n");
1919 break;
1920 case POWERPC_EXCP_STOP: /* stop translation */
1921 /* We did invalidate the instruction cache. Go on */
1922 break;
1923 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1924 /* We just stopped because of a branch. Go on */
1925 break;
1926 case POWERPC_EXCP_SYSCALL_USER:
1927 /* system call in user-mode emulation */
1928 /* WARNING:
1929 * PPC ABI uses overflow flag in cr0 to signal an error
1930 * in syscalls.
1931 */
e1833e1f
JM		 1932 env->crf[0] &= ~0x1;
1933 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1934 env->gpr[5], env->gpr[6], env->gpr[7],
5945cfcb 1935 env->gpr[8], 0, 0);
9e0e2f96 1936 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
bcd4933a
NF		 1937 /* Returning from a successful sigreturn syscall.
1938 Avoid corrupting register state. */
1939 break;
1940 }
9e0e2f96 1941 if (ret > (target_ulong)(-515)) {
e1833e1f
JM		 1942 env->crf[0] |= 0x1;
1943 ret = -ret;
61190b14 1944 }
e1833e1f 1945 env->gpr[3] = ret;
e1833e1f 1946 break;
56f066bb
NF		 1947 case POWERPC_EXCP_STCX:
1948 if (do_store_exclusive(env)) {
1949 info.si_signo = TARGET_SIGSEGV;
1950 info.si_errno = 0;
1951 info.si_code = TARGET_SEGV_MAPERR;
1952 info._sifields._sigfault._addr = env->nip;
1953 queue_signal(env, info.si_signo, &info);
1954 }
1955 break;
71f75756
AJ		 1956 case EXCP_DEBUG:
1957 {
1958 int sig;
1959
db6b81d4 1960 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
71f75756
AJ		 1961 if (sig) {
1962 info.si_signo = sig;
1963 info.si_errno = 0;
1964 info.si_code = TARGET_TRAP_BRKPT;
1965 queue_signal(env, info.si_signo, &info);
1966 }
1967 }
1968 break;
56ba31ff
JM		 1969 case EXCP_INTERRUPT:
1970 /* just indicate that signals should be handled asap */
1971 break;
e1833e1f 1972 default:
a47dddd7 1973 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
e1833e1f 1974 break;
67867308
FB		 1975 }
1976 process_pending_signals(env);
1977 }
1978}
1979#endif
1980
048f6b4d
FB		 1981#ifdef TARGET_MIPS
1982
ff4f7382
RH		 1983# ifdef TARGET_ABI_MIPSO32
1984# define MIPS_SYS(name, args) args,
048f6b4d 1985static const uint8_t mips_syscall_args[] = {
29fb0f25 1986 MIPS_SYS(sys_syscall , 8) /* 4000 */
048f6b4d
FB		 1987 MIPS_SYS(sys_exit , 1)
1988 MIPS_SYS(sys_fork , 0)
1989 MIPS_SYS(sys_read , 3)
1990 MIPS_SYS(sys_write , 3)
1991 MIPS_SYS(sys_open , 3) /* 4005 */
1992 MIPS_SYS(sys_close , 1)
1993 MIPS_SYS(sys_waitpid , 3)
1994 MIPS_SYS(sys_creat , 2)
1995 MIPS_SYS(sys_link , 2)
1996 MIPS_SYS(sys_unlink , 1) /* 4010 */
1997 MIPS_SYS(sys_execve , 0)
1998 MIPS_SYS(sys_chdir , 1)
1999 MIPS_SYS(sys_time , 1)
2000 MIPS_SYS(sys_mknod , 3)
2001 MIPS_SYS(sys_chmod , 2) /* 4015 */
2002 MIPS_SYS(sys_lchown , 3)
2003 MIPS_SYS(sys_ni_syscall , 0)
2004 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2005 MIPS_SYS(sys_lseek , 3)
2006 MIPS_SYS(sys_getpid , 0) /* 4020 */
2007 MIPS_SYS(sys_mount , 5)
868e34d7 2008 MIPS_SYS(sys_umount , 1)
048f6b4d
FB		 2009 MIPS_SYS(sys_setuid , 1)
2010 MIPS_SYS(sys_getuid , 0)
2011 MIPS_SYS(sys_stime , 1) /* 4025 */
2012 MIPS_SYS(sys_ptrace , 4)
2013 MIPS_SYS(sys_alarm , 1)
2014 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2015 MIPS_SYS(sys_pause , 0)
2016 MIPS_SYS(sys_utime , 2) /* 4030 */
2017 MIPS_SYS(sys_ni_syscall , 0)
2018 MIPS_SYS(sys_ni_syscall , 0)
2019 MIPS_SYS(sys_access , 2)
2020 MIPS_SYS(sys_nice , 1)
2021 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2022 MIPS_SYS(sys_sync , 0)
2023 MIPS_SYS(sys_kill , 2)
2024 MIPS_SYS(sys_rename , 2)
2025 MIPS_SYS(sys_mkdir , 2)
2026 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2027 MIPS_SYS(sys_dup , 1)
2028 MIPS_SYS(sys_pipe , 0)
2029 MIPS_SYS(sys_times , 1)
2030 MIPS_SYS(sys_ni_syscall , 0)
2031 MIPS_SYS(sys_brk , 1) /* 4045 */
2032 MIPS_SYS(sys_setgid , 1)
2033 MIPS_SYS(sys_getgid , 0)
2034 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2035 MIPS_SYS(sys_geteuid , 0)
2036 MIPS_SYS(sys_getegid , 0) /* 4050 */
2037 MIPS_SYS(sys_acct , 0)
868e34d7 2038 MIPS_SYS(sys_umount2 , 2)
048f6b4d
FB		 2039 MIPS_SYS(sys_ni_syscall , 0)
2040 MIPS_SYS(sys_ioctl , 3)
2041 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2042 MIPS_SYS(sys_ni_syscall , 2)
2043 MIPS_SYS(sys_setpgid , 2)
2044 MIPS_SYS(sys_ni_syscall , 0)
2045 MIPS_SYS(sys_olduname , 1)
2046 MIPS_SYS(sys_umask , 1) /* 4060 */
2047 MIPS_SYS(sys_chroot , 1)
2048 MIPS_SYS(sys_ustat , 2)
2049 MIPS_SYS(sys_dup2 , 2)
2050 MIPS_SYS(sys_getppid , 0)
2051 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2052 MIPS_SYS(sys_setsid , 0)
2053 MIPS_SYS(sys_sigaction , 3)
2054 MIPS_SYS(sys_sgetmask , 0)
2055 MIPS_SYS(sys_ssetmask , 1)
2056 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2057 MIPS_SYS(sys_setregid , 2)
2058 MIPS_SYS(sys_sigsuspend , 0)
2059 MIPS_SYS(sys_sigpending , 1)
2060 MIPS_SYS(sys_sethostname , 2)
2061 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2062 MIPS_SYS(sys_getrlimit , 2)
2063 MIPS_SYS(sys_getrusage , 2)
2064 MIPS_SYS(sys_gettimeofday, 2)
2065 MIPS_SYS(sys_settimeofday, 2)
2066 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2067 MIPS_SYS(sys_setgroups , 2)
2068 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2069 MIPS_SYS(sys_symlink , 2)
2070 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2071 MIPS_SYS(sys_readlink , 3) /* 4085 */
2072 MIPS_SYS(sys_uselib , 1)
2073 MIPS_SYS(sys_swapon , 2)
2074 MIPS_SYS(sys_reboot , 3)
2075 MIPS_SYS(old_readdir , 3)
2076 MIPS_SYS(old_mmap , 6) /* 4090 */
2077 MIPS_SYS(sys_munmap , 2)
2078 MIPS_SYS(sys_truncate , 2)
2079 MIPS_SYS(sys_ftruncate , 2)
2080 MIPS_SYS(sys_fchmod , 2)
2081 MIPS_SYS(sys_fchown , 3) /* 4095 */
2082 MIPS_SYS(sys_getpriority , 2)
2083 MIPS_SYS(sys_setpriority , 3)
2084 MIPS_SYS(sys_ni_syscall , 0)
2085 MIPS_SYS(sys_statfs , 2)
2086 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2087 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2088 MIPS_SYS(sys_socketcall , 2)
2089 MIPS_SYS(sys_syslog , 3)
2090 MIPS_SYS(sys_setitimer , 3)
2091 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2092 MIPS_SYS(sys_newstat , 2)
2093 MIPS_SYS(sys_newlstat , 2)
2094 MIPS_SYS(sys_newfstat , 2)
2095 MIPS_SYS(sys_uname , 1)
2096 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2097 MIPS_SYS(sys_vhangup , 0)
2098 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2099 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2100 MIPS_SYS(sys_wait4 , 4)
2101 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2102 MIPS_SYS(sys_sysinfo , 1)
2103 MIPS_SYS(sys_ipc , 6)
2104 MIPS_SYS(sys_fsync , 1)
2105 MIPS_SYS(sys_sigreturn , 0)
18113962 2106 MIPS_SYS(sys_clone , 6) /* 4120 */
048f6b4d
FB		 2107 MIPS_SYS(sys_setdomainname, 2)
2108 MIPS_SYS(sys_newuname , 1)
2109 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2110 MIPS_SYS(sys_adjtimex , 1)
2111 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2112 MIPS_SYS(sys_sigprocmask , 3)
2113 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2114 MIPS_SYS(sys_init_module , 5)
2115 MIPS_SYS(sys_delete_module, 1)
2116 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2117 MIPS_SYS(sys_quotactl , 0)
2118 MIPS_SYS(sys_getpgid , 1)
2119 MIPS_SYS(sys_fchdir , 1)
2120 MIPS_SYS(sys_bdflush , 2)
2121 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2122 MIPS_SYS(sys_personality , 1)
2123 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2124 MIPS_SYS(sys_setfsuid , 1)
2125 MIPS_SYS(sys_setfsgid , 1)
2126 MIPS_SYS(sys_llseek , 5) /* 4140 */
2127 MIPS_SYS(sys_getdents , 3)
2128 MIPS_SYS(sys_select , 5)
2129 MIPS_SYS(sys_flock , 2)
2130 MIPS_SYS(sys_msync , 3)
2131 MIPS_SYS(sys_readv , 3) /* 4145 */
2132 MIPS_SYS(sys_writev , 3)
2133 MIPS_SYS(sys_cacheflush , 3)
2134 MIPS_SYS(sys_cachectl , 3)
2135 MIPS_SYS(sys_sysmips , 4)
2136 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2137 MIPS_SYS(sys_getsid , 1)
2138 MIPS_SYS(sys_fdatasync , 0)
2139 MIPS_SYS(sys_sysctl , 1)
2140 MIPS_SYS(sys_mlock , 2)
2141 MIPS_SYS(sys_munlock , 2) /* 4155 */
2142 MIPS_SYS(sys_mlockall , 1)
2143 MIPS_SYS(sys_munlockall , 0)
2144 MIPS_SYS(sys_sched_setparam, 2)
2145 MIPS_SYS(sys_sched_getparam, 2)
2146 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2147 MIPS_SYS(sys_sched_getscheduler, 1)
2148 MIPS_SYS(sys_sched_yield , 0)
2149 MIPS_SYS(sys_sched_get_priority_max, 1)
2150 MIPS_SYS(sys_sched_get_priority_min, 1)
2151 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2152 MIPS_SYS(sys_nanosleep, 2)
b0932e06 2153 MIPS_SYS(sys_mremap , 5)
048f6b4d
FB		 2154 MIPS_SYS(sys_accept , 3)
2155 MIPS_SYS(sys_bind , 3)
2156 MIPS_SYS(sys_connect , 3) /* 4170 */
2157 MIPS_SYS(sys_getpeername , 3)
2158 MIPS_SYS(sys_getsockname , 3)
2159 MIPS_SYS(sys_getsockopt , 5)
2160 MIPS_SYS(sys_listen , 2)
2161 MIPS_SYS(sys_recv , 4) /* 4175 */
2162 MIPS_SYS(sys_recvfrom , 6)
2163 MIPS_SYS(sys_recvmsg , 3)
2164 MIPS_SYS(sys_send , 4)
2165 MIPS_SYS(sys_sendmsg , 3)
2166 MIPS_SYS(sys_sendto , 6) /* 4180 */
2167 MIPS_SYS(sys_setsockopt , 5)
2168 MIPS_SYS(sys_shutdown , 2)
2169 MIPS_SYS(sys_socket , 3)
2170 MIPS_SYS(sys_socketpair , 4)
2171 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2172 MIPS_SYS(sys_getresuid , 3)
2173 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2174 MIPS_SYS(sys_poll , 3)
2175 MIPS_SYS(sys_nfsservctl , 3)
2176 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2177 MIPS_SYS(sys_getresgid , 3)
2178 MIPS_SYS(sys_prctl , 5)
2179 MIPS_SYS(sys_rt_sigreturn, 0)
2180 MIPS_SYS(sys_rt_sigaction, 4)
2181 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2182 MIPS_SYS(sys_rt_sigpending, 2)
2183 MIPS_SYS(sys_rt_sigtimedwait, 4)
2184 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2185 MIPS_SYS(sys_rt_sigsuspend, 0)
2186 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2187 MIPS_SYS(sys_pwrite64 , 6)
2188 MIPS_SYS(sys_chown , 3)
2189 MIPS_SYS(sys_getcwd , 2)
2190 MIPS_SYS(sys_capget , 2)
2191 MIPS_SYS(sys_capset , 2) /* 4205 */
053ebb27 2192 MIPS_SYS(sys_sigaltstack , 2)
048f6b4d
FB		 2193 MIPS_SYS(sys_sendfile , 4)
2194 MIPS_SYS(sys_ni_syscall , 0)
2195 MIPS_SYS(sys_ni_syscall , 0)
2196 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2197 MIPS_SYS(sys_truncate64 , 4)
2198 MIPS_SYS(sys_ftruncate64 , 4)
2199 MIPS_SYS(sys_stat64 , 2)
2200 MIPS_SYS(sys_lstat64 , 2)
2201 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2202 MIPS_SYS(sys_pivot_root , 2)
2203 MIPS_SYS(sys_mincore , 3)
2204 MIPS_SYS(sys_madvise , 3)
2205 MIPS_SYS(sys_getdents64 , 3)
2206 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2207 MIPS_SYS(sys_ni_syscall , 0)
2208 MIPS_SYS(sys_gettid , 0)
2209 MIPS_SYS(sys_readahead , 5)
2210 MIPS_SYS(sys_setxattr , 5)
2211 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2212 MIPS_SYS(sys_fsetxattr , 5)
2213 MIPS_SYS(sys_getxattr , 4)
2214 MIPS_SYS(sys_lgetxattr , 4)
2215 MIPS_SYS(sys_fgetxattr , 4)
2216 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2217 MIPS_SYS(sys_llistxattr , 3)
2218 MIPS_SYS(sys_flistxattr , 3)
2219 MIPS_SYS(sys_removexattr , 2)
2220 MIPS_SYS(sys_lremovexattr, 2)
2221 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2222 MIPS_SYS(sys_tkill , 2)
2223 MIPS_SYS(sys_sendfile64 , 5)
43be1343 2224 MIPS_SYS(sys_futex , 6)
048f6b4d
FB		 2225 MIPS_SYS(sys_sched_setaffinity, 3)
2226 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2227 MIPS_SYS(sys_io_setup , 2)
2228 MIPS_SYS(sys_io_destroy , 1)
2229 MIPS_SYS(sys_io_getevents, 5)
2230 MIPS_SYS(sys_io_submit , 3)
2231 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2232 MIPS_SYS(sys_exit_group , 1)
2233 MIPS_SYS(sys_lookup_dcookie, 3)
2234 MIPS_SYS(sys_epoll_create, 1)
2235 MIPS_SYS(sys_epoll_ctl , 4)
2236 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2237 MIPS_SYS(sys_remap_file_pages, 5)
2238 MIPS_SYS(sys_set_tid_address, 1)
2239 MIPS_SYS(sys_restart_syscall, 0)
2240 MIPS_SYS(sys_fadvise64_64, 7)
2241 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2242 MIPS_SYS(sys_fstatfs64 , 2)
2243 MIPS_SYS(sys_timer_create, 3)
2244 MIPS_SYS(sys_timer_settime, 4)
2245 MIPS_SYS(sys_timer_gettime, 2)
2246 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2247 MIPS_SYS(sys_timer_delete, 1)
2248 MIPS_SYS(sys_clock_settime, 2)
2249 MIPS_SYS(sys_clock_gettime, 2)
2250 MIPS_SYS(sys_clock_getres, 2)
2251 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2252 MIPS_SYS(sys_tgkill , 3)
2253 MIPS_SYS(sys_utimes , 2)
2254 MIPS_SYS(sys_mbind , 4)
2255 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2256 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2257 MIPS_SYS(sys_mq_open , 4)
2258 MIPS_SYS(sys_mq_unlink , 1)
2259 MIPS_SYS(sys_mq_timedsend, 5)
2260 MIPS_SYS(sys_mq_timedreceive, 5)
2261 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2262 MIPS_SYS(sys_mq_getsetattr, 3)
2263 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2264 MIPS_SYS(sys_waitid , 4)
2265 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2266 MIPS_SYS(sys_add_key , 5)
388bb21a 2267 MIPS_SYS(sys_request_key, 4)
048f6b4d 2268 MIPS_SYS(sys_keyctl , 5)
6f5b89a0 2269 MIPS_SYS(sys_set_thread_area, 1)
388bb21a
TS		 2270 MIPS_SYS(sys_inotify_init, 0)
2271 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2272 MIPS_SYS(sys_inotify_rm_watch, 2)
2273 MIPS_SYS(sys_migrate_pages, 4)
2274 MIPS_SYS(sys_openat, 4)
2275 MIPS_SYS(sys_mkdirat, 3)
2276 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2277 MIPS_SYS(sys_fchownat, 5)
2278 MIPS_SYS(sys_futimesat, 3)
2279 MIPS_SYS(sys_fstatat64, 4)
2280 MIPS_SYS(sys_unlinkat, 3)
2281 MIPS_SYS(sys_renameat, 4) /* 4295 */
2282 MIPS_SYS(sys_linkat, 5)
2283 MIPS_SYS(sys_symlinkat, 3)
2284 MIPS_SYS(sys_readlinkat, 4)
2285 MIPS_SYS(sys_fchmodat, 3)
2286 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2287 MIPS_SYS(sys_pselect6, 6)
2288 MIPS_SYS(sys_ppoll, 5)
2289 MIPS_SYS(sys_unshare, 1)
b0932e06 2290 MIPS_SYS(sys_splice, 6)
388bb21a
TS		 2291 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2292 MIPS_SYS(sys_tee, 4)
2293 MIPS_SYS(sys_vmsplice, 4)
2294 MIPS_SYS(sys_move_pages, 6)
2295 MIPS_SYS(sys_set_robust_list, 2)
2296 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2297 MIPS_SYS(sys_kexec_load, 4)
2298 MIPS_SYS(sys_getcpu, 3)
2299 MIPS_SYS(sys_epoll_pwait, 6)
2300 MIPS_SYS(sys_ioprio_set, 3)
2301 MIPS_SYS(sys_ioprio_get, 2)
d979e8eb
PM		 2302 MIPS_SYS(sys_utimensat, 4)
2303 MIPS_SYS(sys_signalfd, 3)
2304 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2305 MIPS_SYS(sys_eventfd, 1)
2306 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2307 MIPS_SYS(sys_timerfd_create, 2)
2308 MIPS_SYS(sys_timerfd_gettime, 2)
2309 MIPS_SYS(sys_timerfd_settime, 4)
2310 MIPS_SYS(sys_signalfd4, 4)
2311 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2312 MIPS_SYS(sys_epoll_create1, 1)
2313 MIPS_SYS(sys_dup3, 3)
2314 MIPS_SYS(sys_pipe2, 2)
2315 MIPS_SYS(sys_inotify_init1, 1)
2316 MIPS_SYS(sys_preadv, 6) /* 4330 */
2317 MIPS_SYS(sys_pwritev, 6)
2318 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2319 MIPS_SYS(sys_perf_event_open, 5)
2320 MIPS_SYS(sys_accept4, 4)
2321 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2322 MIPS_SYS(sys_fanotify_init, 2)
2323 MIPS_SYS(sys_fanotify_mark, 6)
2324 MIPS_SYS(sys_prlimit64, 4)
2325 MIPS_SYS(sys_name_to_handle_at, 5)
2326 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2327 MIPS_SYS(sys_clock_adjtime, 2)
2328 MIPS_SYS(sys_syncfs, 1)
048f6b4d 2329};
ff4f7382
RH		 2330# undef MIPS_SYS
2331# endif /* O32 */
048f6b4d 2332
590bc601
PB		 2333static int do_store_exclusive(CPUMIPSState *env)
2334{
2335 target_ulong addr;
2336 target_ulong page_addr;
2337 target_ulong val;
2338 int flags;
2339 int segv = 0;
2340 int reg;
2341 int d;
2342
5499b6ff 2343 addr = env->lladdr;
590bc601
PB		 2344 page_addr = addr & TARGET_PAGE_MASK;
2345 start_exclusive();
2346 mmap_lock();
2347 flags = page_get_flags(page_addr);
2348 if ((flags & PAGE_READ) == 0) {
2349 segv = 1;
2350 } else {
2351 reg = env->llreg & 0x1f;
2352 d = (env->llreg & 0x20) != 0;
2353 if (d) {
2354 segv = get_user_s64(val, addr);
2355 } else {
2356 segv = get_user_s32(val, addr);
2357 }
2358 if (!segv) {
2359 if (val != env->llval) {
2360 env->active_tc.gpr[reg] = 0;
2361 } else {
2362 if (d) {
2363 segv = put_user_u64(env->llnewval, addr);
2364 } else {
2365 segv = put_user_u32(env->llnewval, addr);
2366 }
2367 if (!segv) {
2368 env->active_tc.gpr[reg] = 1;
2369 }
2370 }
2371 }
2372 }
5499b6ff 2373 env->lladdr = -1;
590bc601
PB		 2374 if (!segv) {
2375 env->active_tc.PC += 4;
2376 }
2377 mmap_unlock();
2378 end_exclusive();
2379 return segv;
2380}
2381
54b2f42c
MI		 2382/* Break codes */
2383enum {
2384 BRK_OVERFLOW = 6,
2385 BRK_DIVZERO = 7
2386};
2387
2388static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2389 unsigned int code)
2390{
2391 int ret = -1;
2392
2393 switch (code) {
2394 case BRK_OVERFLOW:
2395 case BRK_DIVZERO:
2396 info->si_signo = TARGET_SIGFPE;
2397 info->si_errno = 0;
2398 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2399 queue_signal(env, info->si_signo, &*info);
2400 ret = 0;
2401 break;
2402 default:
b51910ba
PJ		 2403 info->si_signo = TARGET_SIGTRAP;
2404 info->si_errno = 0;
2405 queue_signal(env, info->si_signo, &*info);
2406 ret = 0;
54b2f42c
MI		 2407 break;
2408 }
2409
2410 return ret;
2411}
2412
048f6b4d
FB		 2413void cpu_loop(CPUMIPSState *env)
2414{
0315c31c 2415 CPUState *cs = CPU(mips_env_get_cpu(env));
c227f099 2416 target_siginfo_t info;
ff4f7382
RH		 2417 int trapnr;
2418 abi_long ret;
2419# ifdef TARGET_ABI_MIPSO32
048f6b4d 2420 unsigned int syscall_num;
ff4f7382 2421# endif
048f6b4d
FB		 2422
2423 for(;;) {
0315c31c 2424 cpu_exec_start(cs);
048f6b4d 2425 trapnr = cpu_mips_exec(env);
0315c31c 2426 cpu_exec_end(cs);
048f6b4d
FB		 2427 switch(trapnr) {
2428 case EXCP_SYSCALL:
b5dc7732 2429 env->active_tc.PC += 4;
ff4f7382
RH		 2430# ifdef TARGET_ABI_MIPSO32
2431 syscall_num = env->active_tc.gpr[2] - 4000;
388bb21a 2432 if (syscall_num >= sizeof(mips_syscall_args)) {
7c2f6157 2433 ret = -TARGET_ENOSYS;
388bb21a
TS		 2434 } else {
2435 int nb_args;
992f48a0
BS		 2436 abi_ulong sp_reg;
2437 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
388bb21a
TS		 2438
2439 nb_args = mips_syscall_args[syscall_num];
b5dc7732 2440 sp_reg = env->active_tc.gpr[29];
388bb21a
TS		 2441 switch (nb_args) {
2442 /* these arguments are taken from the stack */
94c19610
ACH		 2443 case 8:
2444 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2445 goto done_syscall;
2446 }
2447 case 7:
2448 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2449 goto done_syscall;
2450 }
2451 case 6:
2452 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2453 goto done_syscall;
2454 }
2455 case 5:
2456 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2457 goto done_syscall;
2458 }
388bb21a
TS		 2459 default:
2460 break;
048f6b4d 2461 }
b5dc7732
TS		 2462 ret = do_syscall(env, env->active_tc.gpr[2],
2463 env->active_tc.gpr[4],
2464 env->active_tc.gpr[5],
2465 env->active_tc.gpr[6],
2466 env->active_tc.gpr[7],
5945cfcb 2467 arg5, arg6, arg7, arg8);
388bb21a 2468 }
94c19610 2469done_syscall:
ff4f7382
RH		 2470# else
2471 ret = do_syscall(env, env->active_tc.gpr[2],
2472 env->active_tc.gpr[4], env->active_tc.gpr[5],
2473 env->active_tc.gpr[6], env->active_tc.gpr[7],
2474 env->active_tc.gpr[8], env->active_tc.gpr[9],
2475 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2476# endif /* O32 */
0b1bcb00
PB		 2477 if (ret == -TARGET_QEMU_ESIGRETURN) {
2478 /* Returning from a successful sigreturn syscall.
2479 Avoid clobbering register state. */
2480 break;
2481 }
ff4f7382 2482 if ((abi_ulong)ret >= (abi_ulong)-1133) {
b5dc7732 2483 env->active_tc.gpr[7] = 1; /* error flag */
388bb21a
TS		 2484 ret = -ret;
2485 } else {
b5dc7732 2486 env->active_tc.gpr[7] = 0; /* error flag */
048f6b4d 2487 }
b5dc7732 2488 env->active_tc.gpr[2] = ret;
048f6b4d 2489 break;
ca7c2b1b
TS		 2490 case EXCP_TLBL:
2491 case EXCP_TLBS:
e6e5bd2d
WT		 2492 case EXCP_AdEL:
2493 case EXCP_AdES:
e4474235
PB		 2494 info.si_signo = TARGET_SIGSEGV;
2495 info.si_errno = 0;
2496 /* XXX: check env->error_code */
2497 info.si_code = TARGET_SEGV_MAPERR;
2498 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2499 queue_signal(env, info.si_signo, &info);
2500 break;
6900e84b 2501 case EXCP_CpU:
048f6b4d 2502 case EXCP_RI:
bc1ad2de
FB		 2503 info.si_signo = TARGET_SIGILL;
2504 info.si_errno = 0;
2505 info.si_code = 0;
624f7979 2506 queue_signal(env, info.si_signo, &info);
048f6b4d 2507 break;
106ec879
FB		 2508 case EXCP_INTERRUPT:
2509 /* just indicate that signals should be handled asap */
2510 break;
d08b2a28
PB		 2511 case EXCP_DEBUG:
2512 {
2513 int sig;
2514
db6b81d4 2515 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d08b2a28
PB		 2516 if (sig)
2517 {
2518 info.si_signo = sig;
2519 info.si_errno = 0;
2520 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2521 queue_signal(env, info.si_signo, &info);
d08b2a28
PB		 2522 }
2523 }
2524 break;
590bc601
PB		 2525 case EXCP_SC:
2526 if (do_store_exclusive(env)) {
2527 info.si_signo = TARGET_SIGSEGV;
2528 info.si_errno = 0;
2529 info.si_code = TARGET_SEGV_MAPERR;
2530 info._sifields._sigfault._addr = env->active_tc.PC;
2531 queue_signal(env, info.si_signo, &info);
2532 }
2533 break;
853c3240
JL		 2534 case EXCP_DSPDIS:
2535 info.si_signo = TARGET_SIGILL;
2536 info.si_errno = 0;
2537 info.si_code = TARGET_ILL_ILLOPC;
2538 queue_signal(env, info.si_signo, &info);
2539 break;
54b2f42c
MI		 2540 /* The code below was inspired by the MIPS Linux kernel trap
2541 * handling code in arch/mips/kernel/traps.c.
2542 */
2543 case EXCP_BREAK:
2544 {
2545 abi_ulong trap_instr;
2546 unsigned int code;
2547
a0333817
KCY		 2548 if (env->hflags & MIPS_HFLAG_M16) {
2549 if (env->insn_flags & ASE_MICROMIPS) {
2550 /* microMIPS mode */
1308c464
KCY		 2551 ret = get_user_u16(trap_instr, env->active_tc.PC);
2552 if (ret != 0) {
2553 goto error;
2554 }
a0333817 2555
1308c464
KCY		 2556 if ((trap_instr >> 10) == 0x11) {
2557 /* 16-bit instruction */
2558 code = trap_instr & 0xf;
2559 } else {
2560 /* 32-bit instruction */
2561 abi_ulong instr_lo;
2562
2563 ret = get_user_u16(instr_lo,
2564 env->active_tc.PC + 2);
2565 if (ret != 0) {
2566 goto error;
2567 }
2568 trap_instr = (trap_instr << 16) | instr_lo;
2569 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2570 /* Unfortunately, microMIPS also suffers from
2571 the old assembler bug... */
2572 if (code >= (1 << 10)) {
2573 code >>= 10;
2574 }
2575 }
a0333817
KCY		 2576 } else {
2577 /* MIPS16e mode */
2578 ret = get_user_u16(trap_instr, env->active_tc.PC);
2579 if (ret != 0) {
2580 goto error;
2581 }
2582 code = (trap_instr >> 6) & 0x3f;
a0333817
KCY		 2583 }
2584 } else {
2585 ret = get_user_ual(trap_instr, env->active_tc.PC);
1308c464
KCY		 2586 if (ret != 0) {
2587 goto error;
2588 }
54b2f42c 2589
1308c464
KCY		 2590 /* As described in the original Linux kernel code, the
2591 * below checks on 'code' are to work around an old
2592 * assembly bug.
2593 */
2594 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2595 if (code >= (1 << 10)) {
2596 code >>= 10;
2597 }
54b2f42c
MI		 2598 }
2599
2600 if (do_break(env, &info, code) != 0) {
2601 goto error;
2602 }
2603 }
2604 break;
2605 case EXCP_TRAP:
2606 {
2607 abi_ulong trap_instr;
2608 unsigned int code = 0;
2609
a0333817
KCY		 2610 if (env->hflags & MIPS_HFLAG_M16) {
2611 /* microMIPS mode */
2612 abi_ulong instr[2];
2613
2614 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2615 get_user_u16(instr[1], env->active_tc.PC + 2);
2616
2617 trap_instr = (instr[0] << 16) | instr[1];
2618 } else {
2619 ret = get_user_ual(trap_instr, env->active_tc.PC);
2620 }
2621
54b2f42c
MI		 2622 if (ret != 0) {
2623 goto error;
2624 }
2625
2626 /* The immediate versions don't provide a code. */
2627 if (!(trap_instr & 0xFC000000)) {
a0333817
KCY		 2628 if (env->hflags & MIPS_HFLAG_M16) {
2629 /* microMIPS mode */
2630 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2631 } else {
2632 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2633 }
54b2f42c
MI		 2634 }
2635
2636 if (do_break(env, &info, code) != 0) {
2637 goto error;
2638 }
2639 }
2640 break;
048f6b4d 2641 default:
54b2f42c 2642error:
5fafdf24 2643 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
048f6b4d 2644 trapnr);
878096ee 2645 cpu_dump_state(cs, stderr, fprintf, 0);
048f6b4d
FB		 2646 abort();
2647 }
2648 process_pending_signals(env);
2649 }
2650}
2651#endif
2652
d962783e
JL		 2653#ifdef TARGET_OPENRISC
2654
2655void cpu_loop(CPUOpenRISCState *env)
2656{
878096ee 2657 CPUState *cs = CPU(openrisc_env_get_cpu(env));
d962783e
JL		 2658 int trapnr, gdbsig;
2659
2660 for (;;) {
2661 trapnr = cpu_exec(env);
2662 gdbsig = 0;
2663
2664 switch (trapnr) {
2665 case EXCP_RESET:
2666 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2667 exit(1);
2668 break;
2669 case EXCP_BUSERR:
2670 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
2671 gdbsig = SIGBUS;
2672 break;
2673 case EXCP_DPF:
2674 case EXCP_IPF:
878096ee 2675 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2676 gdbsig = TARGET_SIGSEGV;
2677 break;
2678 case EXCP_TICK:
2679 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2680 break;
2681 case EXCP_ALIGN:
2682 qemu_log("\nAlignment pc is %#x\n", env->pc);
2683 gdbsig = SIGBUS;
2684 break;
2685 case EXCP_ILLEGAL:
2686 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
2687 gdbsig = SIGILL;
2688 break;
2689 case EXCP_INT:
2690 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2691 break;
2692 case EXCP_DTLBMISS:
2693 case EXCP_ITLBMISS:
2694 qemu_log("\nTLB miss\n");
2695 break;
2696 case EXCP_RANGE:
2697 qemu_log("\nRange\n");
2698 gdbsig = SIGSEGV;
2699 break;
2700 case EXCP_SYSCALL:
2701 env->pc += 4; /* 0xc00; */
2702 env->gpr[11] = do_syscall(env,
2703 env->gpr[11], /* return value */
2704 env->gpr[3], /* r3 - r7 are params */
2705 env->gpr[4],
2706 env->gpr[5],
2707 env->gpr[6],
2708 env->gpr[7],
2709 env->gpr[8], 0, 0);
2710 break;
2711 case EXCP_FPE:
2712 qemu_log("\nFloating point error\n");
2713 break;
2714 case EXCP_TRAP:
2715 qemu_log("\nTrap\n");
2716 gdbsig = SIGTRAP;
2717 break;
2718 case EXCP_NR:
2719 qemu_log("\nNR\n");
2720 break;
2721 default:
2722 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2723 trapnr);
878096ee 2724 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2725 gdbsig = TARGET_SIGILL;
2726 break;
2727 }
2728 if (gdbsig) {
db6b81d4 2729 gdb_handlesig(cs, gdbsig);
d962783e
JL		 2730 if (gdbsig != TARGET_SIGTRAP) {
2731 exit(1);
2732 }
2733 }
2734
2735 process_pending_signals(env);
2736 }
2737}
2738
2739#endif /* TARGET_OPENRISC */
2740
fdf9b3e8 2741#ifdef TARGET_SH4
05390248 2742void cpu_loop(CPUSH4State *env)
fdf9b3e8 2743{
878096ee 2744 CPUState *cs = CPU(sh_env_get_cpu(env));
fdf9b3e8 2745 int trapnr, ret;
c227f099 2746 target_siginfo_t info;
3b46e624 2747
fdf9b3e8
FB		 2748 while (1) {
2749 trapnr = cpu_sh4_exec (env);
3b46e624 2750
fdf9b3e8
FB		 2751 switch (trapnr) {
2752 case 0x160:
0b6d3ae0 2753 env->pc += 2;
5fafdf24
TS		 2754 ret = do_syscall(env,
2755 env->gregs[3],
2756 env->gregs[4],
2757 env->gregs[5],
2758 env->gregs[6],
2759 env->gregs[7],
2760 env->gregs[0],
5945cfcb
PM		 2761 env->gregs[1],
2762 0, 0);
9c2a9ea1 2763 env->gregs[0] = ret;
fdf9b3e8 2764 break;
c3b5bc8a
TS		 2765 case EXCP_INTERRUPT:
2766 /* just indicate that signals should be handled asap */
2767 break;
355fb23d
PB		 2768 case EXCP_DEBUG:
2769 {
2770 int sig;
2771
db6b81d4 2772 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
355fb23d
PB		 2773 if (sig)
2774 {
2775 info.si_signo = sig;
2776 info.si_errno = 0;
2777 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2778 queue_signal(env, info.si_signo, &info);
355fb23d
PB		 2779 }
2780 }
2781 break;
c3b5bc8a
TS		 2782 case 0xa0:
2783 case 0xc0:
2784 info.si_signo = SIGSEGV;
2785 info.si_errno = 0;
2786 info.si_code = TARGET_SEGV_MAPERR;
2787 info._sifields._sigfault._addr = env->tea;
624f7979 2788 queue_signal(env, info.si_signo, &info);
c3b5bc8a
TS		 2789 break;
2790
fdf9b3e8
FB		 2791 default:
2792 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2793 cpu_dump_state(cs, stderr, fprintf, 0);
fdf9b3e8
FB		 2794 exit (1);
2795 }
2796 process_pending_signals (env);
2797 }
2798}
2799#endif
2800
48733d19 2801#ifdef TARGET_CRIS
05390248 2802void cpu_loop(CPUCRISState *env)
48733d19 2803{
878096ee 2804 CPUState *cs = CPU(cris_env_get_cpu(env));
48733d19 2805 int trapnr, ret;
c227f099 2806 target_siginfo_t info;
48733d19
TS		 2807
2808 while (1) {
2809 trapnr = cpu_cris_exec (env);
2810 switch (trapnr) {
2811 case 0xaa:
2812 {
2813 info.si_signo = SIGSEGV;
2814 info.si_errno = 0;
2815 /* XXX: check env->error_code */
2816 info.si_code = TARGET_SEGV_MAPERR;
e00c1e71 2817 info._sifields._sigfault._addr = env->pregs[PR_EDA];
624f7979 2818 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2819 }
2820 break;
b6d3abda
EI		 2821 case EXCP_INTERRUPT:
2822 /* just indicate that signals should be handled asap */
2823 break;
48733d19
TS		 2824 case EXCP_BREAK:
2825 ret = do_syscall(env,
2826 env->regs[9],
2827 env->regs[10],
2828 env->regs[11],
2829 env->regs[12],
2830 env->regs[13],
2831 env->pregs[7],
5945cfcb
PM		 2832 env->pregs[11],
2833 0, 0);
48733d19 2834 env->regs[10] = ret;
48733d19
TS		 2835 break;
2836 case EXCP_DEBUG:
2837 {
2838 int sig;
2839
db6b81d4 2840 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
48733d19
TS		 2841 if (sig)
2842 {
2843 info.si_signo = sig;
2844 info.si_errno = 0;
2845 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2846 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2847 }
2848 }
2849 break;
2850 default:
2851 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2852 cpu_dump_state(cs, stderr, fprintf, 0);
48733d19
TS		 2853 exit (1);
2854 }
2855 process_pending_signals (env);
2856 }
2857}
2858#endif
2859
b779e29e 2860#ifdef TARGET_MICROBLAZE
05390248 2861void cpu_loop(CPUMBState *env)
b779e29e 2862{
878096ee 2863 CPUState *cs = CPU(mb_env_get_cpu(env));
b779e29e 2864 int trapnr, ret;
c227f099 2865 target_siginfo_t info;
b779e29e
EI		 2866
2867 while (1) {
2868 trapnr = cpu_mb_exec (env);
2869 switch (trapnr) {
2870 case 0xaa:
2871 {
2872 info.si_signo = SIGSEGV;
2873 info.si_errno = 0;
2874 /* XXX: check env->error_code */
2875 info.si_code = TARGET_SEGV_MAPERR;
2876 info._sifields._sigfault._addr = 0;
2877 queue_signal(env, info.si_signo, &info);
2878 }
2879 break;
2880 case EXCP_INTERRUPT:
2881 /* just indicate that signals should be handled asap */
2882 break;
2883 case EXCP_BREAK:
2884 /* Return address is 4 bytes after the call. */
2885 env->regs[14] += 4;
d7dce494 2886 env->sregs[SR_PC] = env->regs[14];
b779e29e
EI		 2887 ret = do_syscall(env,
2888 env->regs[12],
2889 env->regs[5],
2890 env->regs[6],
2891 env->regs[7],
2892 env->regs[8],
2893 env->regs[9],
5945cfcb
PM		 2894 env->regs[10],
2895 0, 0);
b779e29e 2896 env->regs[3] = ret;
b779e29e 2897 break;
b76da7e3
EI		 2898 case EXCP_HW_EXCP:
2899 env->regs[17] = env->sregs[SR_PC] + 4;
2900 if (env->iflags & D_FLAG) {
2901 env->sregs[SR_ESR] |= 1 << 12;
2902 env->sregs[SR_PC] -= 4;
b4916d7b 2903 /* FIXME: if branch was immed, replay the imm as well. */
b76da7e3
EI		 2904 }
2905
2906 env->iflags &= ~(IMM_FLAG | D_FLAG);
2907
2908 switch (env->sregs[SR_ESR] & 31) {
22a78d64
EI		 2909 case ESR_EC_DIVZERO:
2910 info.si_signo = SIGFPE;
2911 info.si_errno = 0;
2912 info.si_code = TARGET_FPE_FLTDIV;
2913 info._sifields._sigfault._addr = 0;
2914 queue_signal(env, info.si_signo, &info);
2915 break;
b76da7e3
EI		 2916 case ESR_EC_FPU:
2917 info.si_signo = SIGFPE;
2918 info.si_errno = 0;
2919 if (env->sregs[SR_FSR] & FSR_IO) {
2920 info.si_code = TARGET_FPE_FLTINV;
2921 }
2922 if (env->sregs[SR_FSR] & FSR_DZ) {
2923 info.si_code = TARGET_FPE_FLTDIV;
2924 }
2925 info._sifields._sigfault._addr = 0;
2926 queue_signal(env, info.si_signo, &info);
2927 break;
2928 default:
2929 printf ("Unhandled hw-exception: 0x%x\n",
2e42d52d 2930 env->sregs[SR_ESR] & ESR_EC_MASK);
878096ee 2931 cpu_dump_state(cs, stderr, fprintf, 0);
b76da7e3
EI		 2932 exit (1);
2933 break;
2934 }
2935 break;
b779e29e
EI		 2936 case EXCP_DEBUG:
2937 {
2938 int sig;
2939
db6b81d4 2940 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
b779e29e
EI		 2941 if (sig)
2942 {
2943 info.si_signo = sig;
2944 info.si_errno = 0;
2945 info.si_code = TARGET_TRAP_BRKPT;
2946 queue_signal(env, info.si_signo, &info);
2947 }
2948 }
2949 break;
2950 default:
2951 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2952 cpu_dump_state(cs, stderr, fprintf, 0);
b779e29e
EI		 2953 exit (1);
2954 }
2955 process_pending_signals (env);
2956 }
2957}
2958#endif
2959
e6e5906b
PB		 2960#ifdef TARGET_M68K
2961
2962void cpu_loop(CPUM68KState *env)
2963{
878096ee 2964 CPUState *cs = CPU(m68k_env_get_cpu(env));
e6e5906b
PB		 2965 int trapnr;
2966 unsigned int n;
c227f099 2967 target_siginfo_t info;
0429a971 2968 TaskState *ts = cs->opaque;
3b46e624 2969
e6e5906b
PB		 2970 for(;;) {
2971 trapnr = cpu_m68k_exec(env);
2972 switch(trapnr) {
2973 case EXCP_ILLEGAL:
2974 {
2975 if (ts->sim_syscalls) {
2976 uint16_t nr;
2977 nr = lduw(env->pc + 2);
2978 env->pc += 4;
2979 do_m68k_simcall(env, nr);
2980 } else {
2981 goto do_sigill;
2982 }
2983 }
2984 break;
a87295e8 2985 case EXCP_HALT_INSN:
e6e5906b 2986 /* Semihosing syscall. */
a87295e8 2987 env->pc += 4;
e6e5906b
PB		 2988 do_m68k_semihosting(env, env->dregs[0]);
2989 break;
2990 case EXCP_LINEA:
2991 case EXCP_LINEF:
2992 case EXCP_UNSUPPORTED:
2993 do_sigill:
2994 info.si_signo = SIGILL;
2995 info.si_errno = 0;
2996 info.si_code = TARGET_ILL_ILLOPN;
2997 info._sifields._sigfault._addr = env->pc;
624f7979 2998 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2999 break;
3000 case EXCP_TRAP0:
3001 {
3002 ts->sim_syscalls = 0;
3003 n = env->dregs[0];
3004 env->pc += 2;
5fafdf24
TS		 3005 env->dregs[0] = do_syscall(env,
3006 n,
e6e5906b
PB		 3007 env->dregs[1],
3008 env->dregs[2],
3009 env->dregs[3],
3010 env->dregs[4],
3011 env->dregs[5],
5945cfcb
PM		 3012 env->aregs[0],
3013 0, 0);
e6e5906b
PB		 3014 }
3015 break;
3016 case EXCP_INTERRUPT:
3017 /* just indicate that signals should be handled asap */
3018 break;
3019 case EXCP_ACCESS:
3020 {
3021 info.si_signo = SIGSEGV;
3022 info.si_errno = 0;
3023 /* XXX: check env->error_code */
3024 info.si_code = TARGET_SEGV_MAPERR;
3025 info._sifields._sigfault._addr = env->mmu.ar;
624f7979 3026 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3027 }
3028 break;
3029 case EXCP_DEBUG:
3030 {
3031 int sig;
3032
db6b81d4 3033 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
e6e5906b
PB		 3034 if (sig)
3035 {
3036 info.si_signo = sig;
3037 info.si_errno = 0;
3038 info.si_code = TARGET_TRAP_BRKPT;
624f7979 3039 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3040 }
3041 }
3042 break;
3043 default:
5fafdf24 3044 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
e6e5906b 3045 trapnr);
878096ee 3046 cpu_dump_state(cs, stderr, fprintf, 0);
e6e5906b
PB		 3047 abort();
3048 }
3049 process_pending_signals(env);
3050 }
3051}
3052#endif /* TARGET_M68K */
3053
7a3148a9 3054#ifdef TARGET_ALPHA
6910b8f6
RH		 3055static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3056{
3057 target_ulong addr, val, tmp;
3058 target_siginfo_t info;
3059 int ret = 0;
3060
3061 addr = env->lock_addr;
3062 tmp = env->lock_st_addr;
3063 env->lock_addr = -1;
3064 env->lock_st_addr = 0;
3065
3066 start_exclusive();
3067 mmap_lock();
3068
3069 if (addr == tmp) {
3070 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3071 goto do_sigsegv;
3072 }
3073
3074 if (val == env->lock_value) {
3075 tmp = env->ir[reg];
3076 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3077 goto do_sigsegv;
3078 }
3079 ret = 1;
3080 }
3081 }
3082 env->ir[reg] = ret;
3083 env->pc += 4;
3084
3085 mmap_unlock();
3086 end_exclusive();
3087 return;
3088
3089 do_sigsegv:
3090 mmap_unlock();
3091 end_exclusive();
3092
3093 info.si_signo = TARGET_SIGSEGV;
3094 info.si_errno = 0;
3095 info.si_code = TARGET_SEGV_MAPERR;
3096 info._sifields._sigfault._addr = addr;
3097 queue_signal(env, TARGET_SIGSEGV, &info);
3098}
3099
05390248 3100void cpu_loop(CPUAlphaState *env)
7a3148a9 3101{
878096ee 3102 CPUState *cs = CPU(alpha_env_get_cpu(env));
e96efcfc 3103 int trapnr;
c227f099 3104 target_siginfo_t info;
6049f4f8 3105 abi_long sysret;
3b46e624 3106
7a3148a9
JM		 3107 while (1) {
3108 trapnr = cpu_alpha_exec (env);
3b46e624 3109
ac316ca4
RH		 3110 /* All of the traps imply a transition through PALcode, which
3111 implies an REI instruction has been executed. Which means
3112 that the intr_flag should be cleared. */
3113 env->intr_flag = 0;
3114
7a3148a9
JM		 3115 switch (trapnr) {
3116 case EXCP_RESET:
3117 fprintf(stderr, "Reset requested. Exit\n");
3118 exit(1);
3119 break;
3120 case EXCP_MCHK:
3121 fprintf(stderr, "Machine check exception. Exit\n");
3122 exit(1);
3123 break;
07b6c13b
RH		 3124 case EXCP_SMP_INTERRUPT:
3125 case EXCP_CLK_INTERRUPT:
3126 case EXCP_DEV_INTERRUPT:
5fafdf24 3127 fprintf(stderr, "External interrupt. Exit\n");
7a3148a9
JM		 3128 exit(1);
3129 break;
07b6c13b 3130 case EXCP_MMFAULT:
6910b8f6 3131 env->lock_addr = -1;
6049f4f8
RH		 3132 info.si_signo = TARGET_SIGSEGV;
3133 info.si_errno = 0;
129d8aa5 3134 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
0be1d07c 3135 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
129d8aa5 3136 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3137 queue_signal(env, info.si_signo, &info);
7a3148a9 3138 break;
7a3148a9 3139 case EXCP_UNALIGN:
6910b8f6 3140 env->lock_addr = -1;
6049f4f8
RH		 3141 info.si_signo = TARGET_SIGBUS;
3142 info.si_errno = 0;
3143 info.si_code = TARGET_BUS_ADRALN;
129d8aa5 3144 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3145 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3146 break;
3147 case EXCP_OPCDEC:
6049f4f8 3148 do_sigill:
6910b8f6 3149 env->lock_addr = -1;
6049f4f8
RH		 3150 info.si_signo = TARGET_SIGILL;
3151 info.si_errno = 0;
3152 info.si_code = TARGET_ILL_ILLOPC;
3153 info._sifields._sigfault._addr = env->pc;
3154 queue_signal(env, info.si_signo, &info);
7a3148a9 3155 break;
07b6c13b
RH		 3156 case EXCP_ARITH:
3157 env->lock_addr = -1;
3158 info.si_signo = TARGET_SIGFPE;
3159 info.si_errno = 0;
3160 info.si_code = TARGET_FPE_FLTINV;
3161 info._sifields._sigfault._addr = env->pc;
3162 queue_signal(env, info.si_signo, &info);
3163 break;
7a3148a9 3164 case EXCP_FEN:
6049f4f8 3165 /* No-op. Linux simply re-enables the FPU. */
7a3148a9 3166 break;
07b6c13b 3167 case EXCP_CALL_PAL:
6910b8f6 3168 env->lock_addr = -1;
07b6c13b 3169 switch (env->error_code) {
6049f4f8
RH		 3170 case 0x80:
3171 /* BPT */
3172 info.si_signo = TARGET_SIGTRAP;
3173 info.si_errno = 0;
3174 info.si_code = TARGET_TRAP_BRKPT;
3175 info._sifields._sigfault._addr = env->pc;
3176 queue_signal(env, info.si_signo, &info);
3177 break;
3178 case 0x81:
3179 /* BUGCHK */
3180 info.si_signo = TARGET_SIGTRAP;
3181 info.si_errno = 0;
3182 info.si_code = 0;
3183 info._sifields._sigfault._addr = env->pc;
3184 queue_signal(env, info.si_signo, &info);
3185 break;
3186 case 0x83:
3187 /* CALLSYS */
3188 trapnr = env->ir[IR_V0];
3189 sysret = do_syscall(env, trapnr,
3190 env->ir[IR_A0], env->ir[IR_A1],
3191 env->ir[IR_A2], env->ir[IR_A3],
5945cfcb
PM		 3192 env->ir[IR_A4], env->ir[IR_A5],
3193 0, 0);
a5b3b13b
RH		 3194 if (trapnr == TARGET_NR_sigreturn
3195 || trapnr == TARGET_NR_rt_sigreturn) {
3196 break;
3197 }
3198 /* Syscall writes 0 to V0 to bypass error check, similar
0e141977
RH		 3199 to how this is handled internal to Linux kernel.
3200 (Ab)use trapnr temporarily as boolean indicating error. */
3201 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3202 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3203 env->ir[IR_A3] = trapnr;
6049f4f8
RH		 3204 break;
3205 case 0x86:
3206 /* IMB */
3207 /* ??? We can probably elide the code using page_unprotect
3208 that is checking for self-modifying code. Instead we
3209 could simply call tb_flush here. Until we work out the
3210 changes required to turn off the extra write protection,
3211 this can be a no-op. */
3212 break;
3213 case 0x9E:
3214 /* RDUNIQUE */
3215 /* Handled in the translator for usermode. */
3216 abort();
3217 case 0x9F:
3218 /* WRUNIQUE */
3219 /* Handled in the translator for usermode. */
3220 abort();
3221 case 0xAA:
3222 /* GENTRAP */
3223 info.si_signo = TARGET_SIGFPE;
3224 switch (env->ir[IR_A0]) {
3225 case TARGET_GEN_INTOVF:
3226 info.si_code = TARGET_FPE_INTOVF;
3227 break;
3228 case TARGET_GEN_INTDIV:
3229 info.si_code = TARGET_FPE_INTDIV;
3230 break;
3231 case TARGET_GEN_FLTOVF:
3232 info.si_code = TARGET_FPE_FLTOVF;
3233 break;
3234 case TARGET_GEN_FLTUND:
3235 info.si_code = TARGET_FPE_FLTUND;
3236 break;
3237 case TARGET_GEN_FLTINV:
3238 info.si_code = TARGET_FPE_FLTINV;
3239 break;
3240 case TARGET_GEN_FLTINE:
3241 info.si_code = TARGET_FPE_FLTRES;
3242 break;
3243 case TARGET_GEN_ROPRAND:
3244 info.si_code = 0;
3245 break;
3246 default:
3247 info.si_signo = TARGET_SIGTRAP;
3248 info.si_code = 0;
3249 break;
3250 }
3251 info.si_errno = 0;
3252 info._sifields._sigfault._addr = env->pc;
3253 queue_signal(env, info.si_signo, &info);
3254 break;
3255 default:
3256 goto do_sigill;
3257 }
7a3148a9 3258 break;
7a3148a9 3259 case EXCP_DEBUG:
db6b81d4 3260 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
6049f4f8 3261 if (info.si_signo) {
6910b8f6 3262 env->lock_addr = -1;
6049f4f8
RH		 3263 info.si_errno = 0;
3264 info.si_code = TARGET_TRAP_BRKPT;
3265 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3266 }
3267 break;
6910b8f6
RH		 3268 case EXCP_STL_C:
3269 case EXCP_STQ_C:
3270 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3271 break;
d0f20495
RH		 3272 case EXCP_INTERRUPT:
3273 /* Just indicate that signals should be handled asap. */
3274 break;
7a3148a9
JM		 3275 default:
3276 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3277 cpu_dump_state(cs, stderr, fprintf, 0);
7a3148a9
JM		 3278 exit (1);
3279 }
3280 process_pending_signals (env);
3281 }
3282}
3283#endif /* TARGET_ALPHA */
3284
a4c075f1
UH		 3285#ifdef TARGET_S390X
3286void cpu_loop(CPUS390XState *env)
3287{
878096ee 3288 CPUState *cs = CPU(s390_env_get_cpu(env));
d5a103cd 3289 int trapnr, n, sig;
a4c075f1 3290 target_siginfo_t info;
d5a103cd 3291 target_ulong addr;
a4c075f1
UH		 3292
3293 while (1) {
d5a103cd 3294 trapnr = cpu_s390x_exec(env);
a4c075f1
UH		 3295 switch (trapnr) {
3296 case EXCP_INTERRUPT:
d5a103cd 3297 /* Just indicate that signals should be handled asap. */
a4c075f1 3298 break;
a4c075f1 3299
d5a103cd
RH		 3300 case EXCP_SVC:
3301 n = env->int_svc_code;
3302 if (!n) {
3303 /* syscalls > 255 */
3304 n = env->regs[1];
a4c075f1 3305 }
d5a103cd
RH		 3306 env->psw.addr += env->int_svc_ilen;
3307 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3308 env->regs[4], env->regs[5],
3309 env->regs[6], env->regs[7], 0, 0);
a4c075f1 3310 break;
d5a103cd
RH		 3311
3312 case EXCP_DEBUG:
db6b81d4 3313 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d5a103cd
RH		 3314 if (sig) {
3315 n = TARGET_TRAP_BRKPT;
3316 goto do_signal_pc;
a4c075f1
UH		 3317 }
3318 break;
d5a103cd
RH		 3319 case EXCP_PGM:
3320 n = env->int_pgm_code;
3321 switch (n) {
3322 case PGM_OPERATION:
3323 case PGM_PRIVILEGED:
3324 sig = SIGILL;
3325 n = TARGET_ILL_ILLOPC;
3326 goto do_signal_pc;
3327 case PGM_PROTECTION:
3328 case PGM_ADDRESSING:
3329 sig = SIGSEGV;
a4c075f1 3330 /* XXX: check env->error_code */
d5a103cd
RH		 3331 n = TARGET_SEGV_MAPERR;
3332 addr = env->__excp_addr;
3333 goto do_signal;
3334 case PGM_EXECUTE:
3335 case PGM_SPECIFICATION:
3336 case PGM_SPECIAL_OP:
3337 case PGM_OPERAND:
3338 do_sigill_opn:
3339 sig = SIGILL;
3340 n = TARGET_ILL_ILLOPN;
3341 goto do_signal_pc;
3342
3343 case PGM_FIXPT_OVERFLOW:
3344 sig = SIGFPE;
3345 n = TARGET_FPE_INTOVF;
3346 goto do_signal_pc;
3347 case PGM_FIXPT_DIVIDE:
3348 sig = SIGFPE;
3349 n = TARGET_FPE_INTDIV;
3350 goto do_signal_pc;
3351
3352 case PGM_DATA:
3353 n = (env->fpc >> 8) & 0xff;
3354 if (n == 0xff) {
3355 /* compare-and-trap */
3356 goto do_sigill_opn;
3357 } else {
3358 /* An IEEE exception, simulated or otherwise. */
3359 if (n & 0x80) {
3360 n = TARGET_FPE_FLTINV;
3361 } else if (n & 0x40) {
3362 n = TARGET_FPE_FLTDIV;
3363 } else if (n & 0x20) {
3364 n = TARGET_FPE_FLTOVF;
3365 } else if (n & 0x10) {
3366 n = TARGET_FPE_FLTUND;
3367 } else if (n & 0x08) {
3368 n = TARGET_FPE_FLTRES;
3369 } else {
3370 /* ??? Quantum exception; BFP, DFP error. */
3371 goto do_sigill_opn;
3372 }
3373 sig = SIGFPE;
3374 goto do_signal_pc;
3375 }
3376
3377 default:
3378 fprintf(stderr, "Unhandled program exception: %#x\n", n);
878096ee 3379 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3380 exit(1);
a4c075f1
UH		 3381 }
3382 break;
d5a103cd
RH		 3383
3384 do_signal_pc:
3385 addr = env->psw.addr;
3386 do_signal:
3387 info.si_signo = sig;
3388 info.si_errno = 0;
3389 info.si_code = n;
3390 info._sifields._sigfault._addr = addr;
3391 queue_signal(env, info.si_signo, &info);
a4c075f1 3392 break;
d5a103cd 3393
a4c075f1 3394 default:
d5a103cd 3395 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
878096ee 3396 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3397 exit(1);
a4c075f1
UH		 3398 }
3399 process_pending_signals (env);
3400 }
3401}
3402
3403#endif /* TARGET_S390X */
3404
a2247f8e 3405THREAD CPUState *thread_cpu;
59faf6d6 3406
edf8e2af
MW		 3407void task_settid(TaskState *ts)
3408{
3409 if (ts->ts_tid == 0) {
edf8e2af 3410 ts->ts_tid = (pid_t)syscall(SYS_gettid);
edf8e2af
MW		 3411 }
3412}
3413
3414void stop_all_tasks(void)
3415{
3416 /*
3417 * We trust that when using NPTL, start_exclusive()
3418 * handles thread stopping correctly.
3419 */
3420 start_exclusive();
3421}
3422
c3a92833 3423/* Assumes contents are already zeroed. */
624f7979
PB		 3424void init_task_state(TaskState *ts)
3425{
3426 int i;
3427
624f7979
PB		 3428 ts->used = 1;
3429 ts->first_free = ts->sigqueue_table;
3430 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3431 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3432 }
3433 ts->sigqueue_table[i].next = NULL;
3434}
fc9c5412 3435
30ba0ee5
AF		 3436CPUArchState *cpu_copy(CPUArchState *env)
3437{
ff4700b0 3438 CPUState *cpu = ENV_GET_CPU(env);
51fb256a 3439 CPUArchState *new_env = cpu_init(cpu_model);
75a34036 3440 CPUState *new_cpu = ENV_GET_CPU(new_env);
30ba0ee5
AF		 3441#if defined(TARGET_HAS_ICE)
3442 CPUBreakpoint *bp;
3443 CPUWatchpoint *wp;
3444#endif
3445
3446 /* Reset non arch specific state */
75a34036 3447 cpu_reset(new_cpu);
30ba0ee5
AF		 3448
3449 memcpy(new_env, env, sizeof(CPUArchState));
3450
3451 /* Clone all break/watchpoints.
3452 Note: Once we support ptrace with hw-debug register access, make sure
3453 BP_CPU break/watchpoints are handled correctly on clone. */
f0c3c505 3454 QTAILQ_INIT(&cpu->breakpoints);
ff4700b0 3455 QTAILQ_INIT(&cpu->watchpoints);
30ba0ee5 3456#if defined(TARGET_HAS_ICE)
f0c3c505 3457 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
b3310ab3 3458 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
30ba0ee5 3459 }
ff4700b0 3460 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
75a34036 3461 cpu_watchpoint_insert(new_cpu, wp->vaddr, (~wp->len_mask) + 1,
30ba0ee5
AF		 3462 wp->flags, NULL);
3463 }
3464#endif
3465
3466 return new_env;
3467}
3468
fc9c5412
JS		 3469static void handle_arg_help(const char *arg)
3470{
3471 usage();
3472}
3473
3474static void handle_arg_log(const char *arg)
3475{
3476 int mask;
fc9c5412 3477
4fde1eba 3478 mask = qemu_str_to_log_mask(arg);
fc9c5412 3479 if (!mask) {
59a6fa6e 3480 qemu_print_log_usage(stdout);
fc9c5412
JS		 3481 exit(1);
3482 }
24537a01 3483 qemu_set_log(mask);
fc9c5412
JS		 3484}
3485
50171d42
CWR		 3486static void handle_arg_log_filename(const char *arg)
3487{
9a7e5424 3488 qemu_set_log_filename(arg);
50171d42
CWR		 3489}
3490
fc9c5412
JS		 3491static void handle_arg_set_env(const char *arg)
3492{
3493 char *r, *p, *token;
3494 r = p = strdup(arg);
3495 while ((token = strsep(&p, ",")) != NULL) {
3496 if (envlist_setenv(envlist, token) != 0) {
3497 usage();
3498 }
3499 }
3500 free(r);
3501}
3502
3503static void handle_arg_unset_env(const char *arg)
3504{
3505 char *r, *p, *token;
3506 r = p = strdup(arg);
3507 while ((token = strsep(&p, ",")) != NULL) {
3508 if (envlist_unsetenv(envlist, token) != 0) {
3509 usage();
3510 }
3511 }
3512 free(r);
3513}
3514
3515static void handle_arg_argv0(const char *arg)
3516{
3517 argv0 = strdup(arg);
3518}
3519
3520static void handle_arg_stack_size(const char *arg)
3521{
3522 char *p;
3523 guest_stack_size = strtoul(arg, &p, 0);
3524 if (guest_stack_size == 0) {
3525 usage();
3526 }
3527
3528 if (*p == 'M') {
3529 guest_stack_size *= 1024 * 1024;
3530 } else if (*p == 'k' || *p == 'K') {
3531 guest_stack_size *= 1024;
3532 }
3533}
3534
3535static void handle_arg_ld_prefix(const char *arg)
3536{
3537 interp_prefix = strdup(arg);
3538}
3539
3540static void handle_arg_pagesize(const char *arg)
3541{
3542 qemu_host_page_size = atoi(arg);
3543 if (qemu_host_page_size == 0 ||
3544 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3545 fprintf(stderr, "page size must be a power of two\n");
3546 exit(1);
3547 }
3548}
3549
3550static void handle_arg_gdb(const char *arg)
3551{
3552 gdbstub_port = atoi(arg);
3553}
3554
3555static void handle_arg_uname(const char *arg)
3556{
3557 qemu_uname_release = strdup(arg);
3558}
3559
3560static void handle_arg_cpu(const char *arg)
3561{
3562 cpu_model = strdup(arg);
c8057f95 3563 if (cpu_model == NULL || is_help_option(cpu_model)) {
fc9c5412 3564 /* XXX: implement xxx_cpu_list for targets that still miss it */
e916cbf8
PM		 3565#if defined(cpu_list)
3566 cpu_list(stdout, &fprintf);
fc9c5412
JS		 3567#endif
3568 exit(1);
3569 }
3570}
3571
3572#if defined(CONFIG_USE_GUEST_BASE)
3573static void handle_arg_guest_base(const char *arg)
3574{
3575 guest_base = strtol(arg, NULL, 0);
3576 have_guest_base = 1;
3577}
3578
3579static void handle_arg_reserved_va(const char *arg)
3580{
3581 char *p;
3582 int shift = 0;
3583 reserved_va = strtoul(arg, &p, 0);
3584 switch (*p) {
3585 case 'k':
3586 case 'K':
3587 shift = 10;
3588 break;
3589 case 'M':
3590 shift = 20;
3591 break;
3592 case 'G':
3593 shift = 30;
3594 break;
3595 }
3596 if (shift) {
3597 unsigned long unshifted = reserved_va;
3598 p++;
3599 reserved_va <<= shift;
3600 if (((reserved_va >> shift) != unshifted)
3601#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3602 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3603#endif
3604 ) {
3605 fprintf(stderr, "Reserved virtual address too big\n");
3606 exit(1);
3607 }
3608 }
3609 if (*p) {
3610 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3611 exit(1);
3612 }
3613}
3614#endif
3615
3616static void handle_arg_singlestep(const char *arg)
3617{
3618 singlestep = 1;
3619}
3620
3621static void handle_arg_strace(const char *arg)
3622{
3623 do_strace = 1;
3624}
3625
3626static void handle_arg_version(const char *arg)
3627{
2e59915d 3628 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
fc9c5412 3629 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
1386d4c0 3630 exit(0);
fc9c5412
JS		 3631}
3632
3633struct qemu_argument {
3634 const char *argv;
3635 const char *env;
3636 bool has_arg;
3637 void (*handle_opt)(const char *arg);
3638 const char *example;
3639 const char *help;
3640};
3641
42644cee 3642static const struct qemu_argument arg_table[] = {
fc9c5412
JS		 3643 {"h", "", false, handle_arg_help,
3644 "", "print this help"},
3645 {"g", "QEMU_GDB", true, handle_arg_gdb,
3646 "port", "wait gdb connection to 'port'"},
3647 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3648 "path", "set the elf interpreter prefix to 'path'"},
3649 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3650 "size", "set the stack size to 'size' bytes"},
3651 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
c8057f95 3652 "model", "select CPU (-cpu help for list)"},
fc9c5412
JS		 3653 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3654 "var=value", "sets targets environment variable (see below)"},
3655 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3656 "var", "unsets targets environment variable (see below)"},
3657 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3658 "argv0", "forces target process argv[0] to be 'argv0'"},
3659 {"r", "QEMU_UNAME", true, handle_arg_uname,
3660 "uname", "set qemu uname release string to 'uname'"},
3661#if defined(CONFIG_USE_GUEST_BASE)
3662 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3663 "address", "set guest_base address to 'address'"},
3664 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3665 "size", "reserve 'size' bytes for guest virtual address space"},
3666#endif
3667 {"d", "QEMU_LOG", true, handle_arg_log,
989b697d
PM		 3668 "item[,...]", "enable logging of specified items "
3669 "(use '-d help' for a list of items)"},
50171d42 3670 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
989b697d 3671 "logfile", "write logs to 'logfile' (default stderr)"},
fc9c5412
JS		 3672 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3673 "pagesize", "set the host page size to 'pagesize'"},
3674 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3675 "", "run in singlestep mode"},
3676 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3677 "", "log system calls"},
3678 {"version", "QEMU_VERSION", false, handle_arg_version,
1386d4c0 3679 "", "display version information and exit"},
fc9c5412
JS		 3680 {NULL, NULL, false, NULL, NULL, NULL}
3681};
3682
3683static void usage(void)
3684{
42644cee 3685 const struct qemu_argument *arginfo;
fc9c5412
JS		 3686 int maxarglen;
3687 int maxenvlen;
3688
2e59915d
PB		 3689 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3690 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
fc9c5412
JS		 3691 "\n"
3692 "Options and associated environment variables:\n"
3693 "\n");
3694
63ec54d7
PM		 3695 /* Calculate column widths. We must always have at least enough space
3696 * for the column header.
3697 */
3698 maxarglen = strlen("Argument");
3699 maxenvlen = strlen("Env-variable");
fc9c5412
JS		 3700
3701 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
63ec54d7
PM		 3702 int arglen = strlen(arginfo->argv);
3703 if (arginfo->has_arg) {
3704 arglen += strlen(arginfo->example) + 1;
3705 }
fc9c5412
JS		 3706 if (strlen(arginfo->env) > maxenvlen) {
3707 maxenvlen = strlen(arginfo->env);
3708 }
63ec54d7
PM		 3709 if (arglen > maxarglen) {
3710 maxarglen = arglen;
fc9c5412
JS		 3711 }
3712 }
3713
63ec54d7
PM		 3714 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3715 maxenvlen, "Env-variable");
fc9c5412
JS		 3716
3717 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3718 if (arginfo->has_arg) {
3719 printf("-%s %-*s %-*s %s\n", arginfo->argv,
63ec54d7
PM		 3720 (int)(maxarglen - strlen(arginfo->argv) - 1),
3721 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
fc9c5412 3722 } else {
63ec54d7 3723 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
fc9c5412
JS		 3724 maxenvlen, arginfo->env,
3725 arginfo->help);
3726 }
3727 }
3728
3729 printf("\n"
3730 "Defaults:\n"
3731 "QEMU_LD_PREFIX = %s\n"
989b697d 3732 "QEMU_STACK_SIZE = %ld byte\n",
fc9c5412 3733 interp_prefix,
989b697d 3734 guest_stack_size);
fc9c5412
JS		 3735
3736 printf("\n"
3737 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3738 "QEMU_UNSET_ENV environment variables to set and unset\n"
3739 "environment variables for the target process.\n"
3740 "It is possible to provide several variables by separating them\n"
3741 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3742 "provide the -E and -U options multiple times.\n"
3743 "The following lines are equivalent:\n"
3744 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3745 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3746 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3747 "Note that if you provide several changes to a single variable\n"
3748 "the last change will stay in effect.\n");
3749
3750 exit(1);
3751}
3752
3753static int parse_args(int argc, char **argv)
3754{
3755 const char *r;
3756 int optind;
42644cee 3757 const struct qemu_argument *arginfo;
fc9c5412
JS		 3758
3759 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3760 if (arginfo->env == NULL) {
3761 continue;
3762 }
3763
3764 r = getenv(arginfo->env);
3765 if (r != NULL) {
3766 arginfo->handle_opt(r);
3767 }
3768 }
3769
3770 optind = 1;
3771 for (;;) {
3772 if (optind >= argc) {
3773 break;
3774 }
3775 r = argv[optind];
3776 if (r[0] != '-') {
3777 break;
3778 }
3779 optind++;
3780 r++;
3781 if (!strcmp(r, "-")) {
3782 break;
3783 }
3784
3785 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3786 if (!strcmp(r, arginfo->argv)) {
fc9c5412 3787 if (arginfo->has_arg) {
1386d4c0
PM		 3788 if (optind >= argc) {
3789 usage();
3790 }
3791 arginfo->handle_opt(argv[optind]);
fc9c5412 3792 optind++;
1386d4c0
PM		 3793 } else {
3794 arginfo->handle_opt(NULL);
fc9c5412 3795 }
fc9c5412
JS		 3796 break;
3797 }
3798 }
3799
3800 /* no option matched the current argv */
3801 if (arginfo->handle_opt == NULL) {
3802 usage();
3803 }
3804 }
3805
3806 if (optind >= argc) {
3807 usage();
3808 }
3809
3810 filename = argv[optind];
3811 exec_path = argv[optind];
3812
3813 return optind;
3814}
3815
902b3d5c 3816int main(int argc, char **argv, char **envp)
31e31b8a 3817{
01ffc75b 3818 struct target_pt_regs regs1, *regs = &regs1;
31e31b8a 3819 struct image_info info1, *info = &info1;
edf8e2af 3820 struct linux_binprm bprm;
48e15fc2 3821 TaskState *ts;
9349b4f9 3822 CPUArchState *env;
db6b81d4 3823 CPUState *cpu;
586314f2 3824 int optind;
04a6dfeb 3825 char **target_environ, **wrk;
7d8cec95
AJ		 3826 char **target_argv;
3827 int target_argc;
7d8cec95 3828 int i;
fd4d81dd 3829 int ret;
03cfd8fa 3830 int execfd;
b12b6a18 3831
ce008c1f
AF		 3832 module_call_init(MODULE_INIT_QOM);
3833
b6a3e690 3834 qemu_init_auxval(envp);
664d2c44 3835 qemu_cache_utils_init();
902b3d5c 3836
04a6dfeb
AJ		 3837 if ((envlist = envlist_create()) == NULL) {
3838 (void) fprintf(stderr, "Unable to allocate envlist\n");
3839 exit(1);
3840 }
3841
3842 /* add current environment into the list */
3843 for (wrk = environ; *wrk != NULL; wrk++) {
3844 (void) envlist_setenv(envlist, *wrk);
3845 }
3846
703e0e89
RH		 3847 /* Read the stack limit from the kernel. If it's "unlimited",
3848 then we can do little else besides use the default. */
3849 {
3850 struct rlimit lim;
3851 if (getrlimit(RLIMIT_STACK, &lim) == 0
81bbe906
TY		 3852 && lim.rlim_cur != RLIM_INFINITY
3853 && lim.rlim_cur == (target_long)lim.rlim_cur) {
703e0e89
RH		 3854 guest_stack_size = lim.rlim_cur;
3855 }
3856 }
3857
b1f9be31 3858 cpu_model = NULL;
b5ec5ce0 3859#if defined(cpudef_setup)
3860 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3861#endif
3862
fc9c5412 3863 optind = parse_args(argc, argv);
586314f2 3864
31e31b8a 3865 /* Zero out regs */
01ffc75b 3866 memset(regs, 0, sizeof(struct target_pt_regs));
31e31b8a
FB		 3867
3868 /* Zero out image_info */
3869 memset(info, 0, sizeof(struct image_info));
3870
edf8e2af
MW		 3871 memset(&bprm, 0, sizeof (bprm));
3872
74cd30b8
FB		 3873 /* Scan interp_prefix dir for replacement files. */
3874 init_paths(interp_prefix);
3875
4a24a758
PM		 3876 init_qemu_uname_release();
3877
46027c07 3878 if (cpu_model == NULL) {
aaed909a 3879#if defined(TARGET_I386)
46027c07
FB		 3880#ifdef TARGET_X86_64
3881 cpu_model = "qemu64";
3882#else
3883 cpu_model = "qemu32";
3884#endif
aaed909a 3885#elif defined(TARGET_ARM)
088ab16c 3886 cpu_model = "any";
d2fbca94
GX		 3887#elif defined(TARGET_UNICORE32)
3888 cpu_model = "any";
aaed909a
FB		 3889#elif defined(TARGET_M68K)
3890 cpu_model = "any";
3891#elif defined(TARGET_SPARC)
3892#ifdef TARGET_SPARC64
3893 cpu_model = "TI UltraSparc II";
3894#else
3895 cpu_model = "Fujitsu MB86904";
46027c07 3896#endif
aaed909a
FB		 3897#elif defined(TARGET_MIPS)
3898#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
3899 cpu_model = "20Kc";
3900#else
3901 cpu_model = "24Kf";
3902#endif
d962783e
JL		 3903#elif defined TARGET_OPENRISC
3904 cpu_model = "or1200";
aaed909a 3905#elif defined(TARGET_PPC)
7ded4f52 3906#ifdef TARGET_PPC64
f7177937 3907 cpu_model = "970fx";
7ded4f52 3908#else
aaed909a 3909 cpu_model = "750";
7ded4f52 3910#endif
aaed909a
FB		 3911#else
3912 cpu_model = "any";
3913#endif
3914 }
d5ab9713
JK		 3915 tcg_exec_init(0);
3916 cpu_exec_init_all();
83fb7adf
FB		 3917 /* NOTE: we need to init the CPU at this stage to get
3918 qemu_host_page_size */
aaed909a
FB		 3919 env = cpu_init(cpu_model);
3920 if (!env) {
3921 fprintf(stderr, "Unable to find CPU definition\n");
3922 exit(1);
3923 }
db6b81d4 3924 cpu = ENV_GET_CPU(env);
0ac46af3 3925 cpu_reset(cpu);
b55a37c9 3926
db6b81d4 3927 thread_cpu = cpu;
3b46e624 3928
b6741956
FB		 3929 if (getenv("QEMU_STRACE")) {
3930 do_strace = 1;
b92c47c1
TS		 3931 }
3932
04a6dfeb
AJ		 3933 target_environ = envlist_to_environ(envlist, NULL);
3934 envlist_free(envlist);
b12b6a18 3935
379f6698
PB		 3936#if defined(CONFIG_USE_GUEST_BASE)
3937 /*
3938 * Now that page sizes are configured in cpu_init() we can do
3939 * proper page alignment for guest_base.
3940 */
3941 guest_base = HOST_PAGE_ALIGN(guest_base);
68a1c816 3942
806d1021
MI		 3943 if (reserved_va || have_guest_base) {
3944 guest_base = init_guest_space(guest_base, reserved_va, 0,
3945 have_guest_base);
3946 if (guest_base == (unsigned long)-1) {
097b8cb8
PM		 3947 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
3948 "space for use as guest address space (check your virtual "
3949 "memory ulimit setting or reserve less using -R option)\n",
3950 reserved_va);
68a1c816
PB		 3951 exit(1);
3952 }
97cc7560 3953
806d1021
MI		 3954 if (reserved_va) {
3955 mmap_next_start = reserved_va;
97cc7560
DDAG		 3956 }
3957 }
14f24e14 3958#endif /* CONFIG_USE_GUEST_BASE */
379f6698
PB		 3959
3960 /*
3961 * Read in mmap_min_addr kernel parameter. This value is used
3962 * When loading the ELF image to determine whether guest_base
14f24e14 3963 * is needed. It is also used in mmap_find_vma.
379f6698 3964 */
14f24e14 3965 {
379f6698
PB		 3966 FILE *fp;
3967
3968 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
3969 unsigned long tmp;
3970 if (fscanf(fp, "%lu", &tmp) == 1) {
3971 mmap_min_addr = tmp;
3972 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
3973 }
3974 fclose(fp);
3975 }
3976 }
379f6698 3977
7d8cec95
AJ		 3978 /*
3979 * Prepare copy of argv vector for target.
3980 */
3981 target_argc = argc - optind;
3982 target_argv = calloc(target_argc + 1, sizeof (char *));
3983 if (target_argv == NULL) {
3984 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
3985 exit(1);
3986 }
3987
3988 /*
3989 * If argv0 is specified (using '-0' switch) we replace
3990 * argv[0] pointer with the given one.
3991 */
3992 i = 0;
3993 if (argv0 != NULL) {
3994 target_argv[i++] = strdup(argv0);
3995 }
3996 for (; i < target_argc; i++) {
3997 target_argv[i] = strdup(argv[optind + i]);
3998 }
3999 target_argv[target_argc] = NULL;
4000
7267c094 4001 ts = g_malloc0 (sizeof(TaskState));
edf8e2af
MW		 4002 init_task_state(ts);
4003 /* build Task State */
4004 ts->info = info;
4005 ts->bprm = &bprm;
0429a971 4006 cpu->opaque = ts;
edf8e2af
MW		 4007 task_settid(ts);
4008
0b959cf5
RH		 4009 execfd = qemu_getauxval(AT_EXECFD);
4010 if (execfd == 0) {
03cfd8fa 4011 execfd = open(filename, O_RDONLY);
0b959cf5
RH		 4012 if (execfd < 0) {
4013 printf("Error while loading %s: %s\n", filename, strerror(errno));
4014 _exit(1);
4015 }
03cfd8fa
LV		 4016 }
4017
4018 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
fd4d81dd
AP		 4019 info, &bprm);
4020 if (ret != 0) {
885c1d10 4021 printf("Error while loading %s: %s\n", filename, strerror(-ret));
b12b6a18
TS		 4022 _exit(1);
4023 }
4024
4025 for (wrk = target_environ; *wrk; wrk++) {
4026 free(*wrk);
31e31b8a 4027 }
3b46e624 4028
b12b6a18
TS		 4029 free(target_environ);
4030
2e77eac6 4031 if (qemu_log_enabled()) {
379f6698
PB		 4032#if defined(CONFIG_USE_GUEST_BASE)
4033 qemu_log("guest_base 0x%lx\n", guest_base);
4034#endif
2e77eac6
BS		 4035 log_page_dump();
4036
4037 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4038 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4039 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4040 info->start_code);
4041 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4042 info->start_data);
4043 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4044 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4045 info->start_stack);
4046 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4047 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4048 }
31e31b8a 4049
53a5960a 4050 target_set_brk(info->brk);
31e31b8a 4051 syscall_init();
66fb9763 4052 signal_init();
31e31b8a 4053
9002ec79
RH		 4054#if defined(CONFIG_USE_GUEST_BASE)
4055 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4056 generating the prologue until now so that the prologue can take
4057 the real value of GUEST_BASE into account. */
4058 tcg_prologue_init(&tcg_ctx);
4059#endif
4060
b346ff46 4061#if defined(TARGET_I386)
2e255c6b
FB		 4062 cpu_x86_set_cpl(env, 3);
4063
3802ce26 4064 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
1bde465e 4065 env->hflags |= HF_PE_MASK;
0514ef2f 4066 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
1bde465e
FB		 4067 env->cr[4] |= CR4_OSFXSR_MASK;
4068 env->hflags |= HF_OSFXSR_MASK;
4069 }
d2fd1af7 4070#ifndef TARGET_ABI32
4dbc422b 4071 /* enable 64 bit mode if possible */
0514ef2f 4072 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4dbc422b
FB		 4073 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4074 exit(1);
4075 }
d2fd1af7 4076 env->cr[4] |= CR4_PAE_MASK;
4dbc422b 4077 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
d2fd1af7
FB		 4078 env->hflags |= HF_LMA_MASK;
4079#endif
1bde465e 4080
415e561f
FB		 4081 /* flags setup : we activate the IRQs by default as in user mode */
4082 env->eflags |= IF_MASK;
3b46e624 4083
6dbad63e 4084 /* linux register setup */
d2fd1af7 4085#ifndef TARGET_ABI32
84409ddb
JM		 4086 env->regs[R_EAX] = regs->rax;
4087 env->regs[R_EBX] = regs->rbx;
4088 env->regs[R_ECX] = regs->rcx;
4089 env->regs[R_EDX] = regs->rdx;
4090 env->regs[R_ESI] = regs->rsi;
4091 env->regs[R_EDI] = regs->rdi;
4092 env->regs[R_EBP] = regs->rbp;
4093 env->regs[R_ESP] = regs->rsp;
4094 env->eip = regs->rip;
4095#else
0ecfa993
FB		 4096 env->regs[R_EAX] = regs->eax;
4097 env->regs[R_EBX] = regs->ebx;
4098 env->regs[R_ECX] = regs->ecx;
4099 env->regs[R_EDX] = regs->edx;
4100 env->regs[R_ESI] = regs->esi;
4101 env->regs[R_EDI] = regs->edi;
4102 env->regs[R_EBP] = regs->ebp;
4103 env->regs[R_ESP] = regs->esp;
dab2ed99 4104 env->eip = regs->eip;
84409ddb 4105#endif
31e31b8a 4106
f4beb510 4107 /* linux interrupt setup */
e441570f
AZ		 4108#ifndef TARGET_ABI32
4109 env->idt.limit = 511;
4110#else
4111 env->idt.limit = 255;
4112#endif
4113 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4114 PROT_READ|PROT_WRITE,
4115 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4116 idt_table = g2h(env->idt.base);
f4beb510
FB		 4117 set_idt(0, 0);
4118 set_idt(1, 0);
4119 set_idt(2, 0);
4120 set_idt(3, 3);
4121 set_idt(4, 3);
ec95da6c 4122 set_idt(5, 0);
f4beb510
FB		 4123 set_idt(6, 0);
4124 set_idt(7, 0);
4125 set_idt(8, 0);
4126 set_idt(9, 0);
4127 set_idt(10, 0);
4128 set_idt(11, 0);
4129 set_idt(12, 0);
4130 set_idt(13, 0);
4131 set_idt(14, 0);
4132 set_idt(15, 0);
4133 set_idt(16, 0);
4134 set_idt(17, 0);
4135 set_idt(18, 0);
4136 set_idt(19, 0);
4137 set_idt(0x80, 3);
4138
6dbad63e 4139 /* linux segment setup */
8d18e893
FB		 4140 {
4141 uint64_t *gdt_table;
e441570f
AZ		 4142 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4143 PROT_READ|PROT_WRITE,
4144 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
8d18e893 4145 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
e441570f 4146 gdt_table = g2h(env->gdt.base);
d2fd1af7 4147#ifdef TARGET_ABI32
8d18e893
FB		 4148 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4149 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4150 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
d2fd1af7
FB		 4151#else
4152 /* 64 bit code segment */
4153 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4154 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4155 DESC_L_MASK |
4156 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4157#endif
8d18e893
FB		 4158 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4159 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4160 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4161 }
6dbad63e 4162 cpu_x86_load_seg(env, R_CS, __USER_CS);
d2fd1af7
FB		 4163 cpu_x86_load_seg(env, R_SS, __USER_DS);
4164#ifdef TARGET_ABI32
6dbad63e
FB		 4165 cpu_x86_load_seg(env, R_DS, __USER_DS);
4166 cpu_x86_load_seg(env, R_ES, __USER_DS);
6dbad63e
FB		 4167 cpu_x86_load_seg(env, R_FS, __USER_DS);
4168 cpu_x86_load_seg(env, R_GS, __USER_DS);
d6eb40f6
TS		 4169 /* This hack makes Wine work... */
4170 env->segs[R_FS].selector = 0;
d2fd1af7
FB		 4171#else
4172 cpu_x86_load_seg(env, R_DS, 0);
4173 cpu_x86_load_seg(env, R_ES, 0);
4174 cpu_x86_load_seg(env, R_FS, 0);
4175 cpu_x86_load_seg(env, R_GS, 0);
4176#endif
99033cae
AG		 4177#elif defined(TARGET_AARCH64)
4178 {
4179 int i;
4180
4181 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4182 fprintf(stderr,
4183 "The selected ARM CPU does not support 64 bit mode\n");
4184 exit(1);
4185 }
4186
4187 for (i = 0; i < 31; i++) {
4188 env->xregs[i] = regs->regs[i];
4189 }
4190 env->pc = regs->pc;
4191 env->xregs[31] = regs->sp;
4192 }
b346ff46
FB		 4193#elif defined(TARGET_ARM)
4194 {
4195 int i;
b5ff1b31 4196 cpsr_write(env, regs->uregs[16], 0xffffffff);
b346ff46
FB		 4197 for(i = 0; i < 16; i++) {
4198 env->regs[i] = regs->uregs[i];
4199 }
d8fd2954
PB		 4200 /* Enable BE8. */
4201 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4202 && (info->elf_flags & EF_ARM_BE8)) {
4203 env->bswap_code = 1;
4204 }
b346ff46 4205 }
d2fbca94
GX		 4206#elif defined(TARGET_UNICORE32)
4207 {
4208 int i;
4209 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4210 for (i = 0; i < 32; i++) {
4211 env->regs[i] = regs->uregs[i];
4212 }
4213 }
93ac68bc 4214#elif defined(TARGET_SPARC)
060366c5
FB		 4215 {
4216 int i;
4217 env->pc = regs->pc;
4218 env->npc = regs->npc;
4219 env->y = regs->y;
4220 for(i = 0; i < 8; i++)
4221 env->gregs[i] = regs->u_regs[i];
4222 for(i = 0; i < 8; i++)
4223 env->regwptr[i] = regs->u_regs[i + 8];
4224 }
67867308
FB		 4225#elif defined(TARGET_PPC)
4226 {
4227 int i;
3fc6c082 4228
0411a972
JM		 4229#if defined(TARGET_PPC64)
4230#if defined(TARGET_ABI32)
4231 env->msr &= ~((target_ulong)1 << MSR_SF);
e85e7c6e 4232#else
0411a972
JM		 4233 env->msr |= (target_ulong)1 << MSR_SF;
4234#endif
84409ddb 4235#endif
67867308
FB		 4236 env->nip = regs->nip;
4237 for(i = 0; i < 32; i++) {
4238 env->gpr[i] = regs->gpr[i];
4239 }
4240 }
e6e5906b
PB		 4241#elif defined(TARGET_M68K)
4242 {
e6e5906b
PB		 4243 env->pc = regs->pc;
4244 env->dregs[0] = regs->d0;
4245 env->dregs[1] = regs->d1;
4246 env->dregs[2] = regs->d2;
4247 env->dregs[3] = regs->d3;
4248 env->dregs[4] = regs->d4;
4249 env->dregs[5] = regs->d5;
4250 env->dregs[6] = regs->d6;
4251 env->dregs[7] = regs->d7;
4252 env->aregs[0] = regs->a0;
4253 env->aregs[1] = regs->a1;
4254 env->aregs[2] = regs->a2;
4255 env->aregs[3] = regs->a3;
4256 env->aregs[4] = regs->a4;
4257 env->aregs[5] = regs->a5;
4258 env->aregs[6] = regs->a6;
4259 env->aregs[7] = regs->usp;
4260 env->sr = regs->sr;
4261 ts->sim_syscalls = 1;
4262 }
b779e29e
EI		 4263#elif defined(TARGET_MICROBLAZE)
4264 {
4265 env->regs[0] = regs->r0;
4266 env->regs[1] = regs->r1;
4267 env->regs[2] = regs->r2;
4268 env->regs[3] = regs->r3;
4269 env->regs[4] = regs->r4;
4270 env->regs[5] = regs->r5;
4271 env->regs[6] = regs->r6;
4272 env->regs[7] = regs->r7;
4273 env->regs[8] = regs->r8;
4274 env->regs[9] = regs->r9;
4275 env->regs[10] = regs->r10;
4276 env->regs[11] = regs->r11;
4277 env->regs[12] = regs->r12;
4278 env->regs[13] = regs->r13;
4279 env->regs[14] = regs->r14;
4280 env->regs[15] = regs->r15;
4281 env->regs[16] = regs->r16;
4282 env->regs[17] = regs->r17;
4283 env->regs[18] = regs->r18;
4284 env->regs[19] = regs->r19;
4285 env->regs[20] = regs->r20;
4286 env->regs[21] = regs->r21;
4287 env->regs[22] = regs->r22;
4288 env->regs[23] = regs->r23;
4289 env->regs[24] = regs->r24;
4290 env->regs[25] = regs->r25;
4291 env->regs[26] = regs->r26;
4292 env->regs[27] = regs->r27;
4293 env->regs[28] = regs->r28;
4294 env->regs[29] = regs->r29;
4295 env->regs[30] = regs->r30;
4296 env->regs[31] = regs->r31;
4297 env->sregs[SR_PC] = regs->pc;
4298 }
048f6b4d
FB		 4299#elif defined(TARGET_MIPS)
4300 {
4301 int i;
4302
4303 for(i = 0; i < 32; i++) {
b5dc7732 4304 env->active_tc.gpr[i] = regs->regs[i];
048f6b4d 4305 }
0fddbbf2
NF		 4306 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4307 if (regs->cp0_epc & 1) {
4308 env->hflags |= MIPS_HFLAG_M16;
4309 }
048f6b4d 4310 }
d962783e
JL		 4311#elif defined(TARGET_OPENRISC)
4312 {
4313 int i;
4314
4315 for (i = 0; i < 32; i++) {
4316 env->gpr[i] = regs->gpr[i];
4317 }
4318
4319 env->sr = regs->sr;
4320 env->pc = regs->pc;
4321 }
fdf9b3e8
FB		 4322#elif defined(TARGET_SH4)
4323 {
4324 int i;
4325
4326 for(i = 0; i < 16; i++) {
4327 env->gregs[i] = regs->regs[i];
4328 }
4329 env->pc = regs->pc;
4330 }
7a3148a9
JM		 4331#elif defined(TARGET_ALPHA)
4332 {
4333 int i;
4334
4335 for(i = 0; i < 28; i++) {
992f48a0 4336 env->ir[i] = ((abi_ulong *)regs)[i];
7a3148a9 4337 }
dad081ee 4338 env->ir[IR_SP] = regs->usp;
7a3148a9 4339 env->pc = regs->pc;
7a3148a9 4340 }
48733d19
TS		 4341#elif defined(TARGET_CRIS)
4342 {
4343 env->regs[0] = regs->r0;
4344 env->regs[1] = regs->r1;
4345 env->regs[2] = regs->r2;
4346 env->regs[3] = regs->r3;
4347 env->regs[4] = regs->r4;
4348 env->regs[5] = regs->r5;
4349 env->regs[6] = regs->r6;
4350 env->regs[7] = regs->r7;
4351 env->regs[8] = regs->r8;
4352 env->regs[9] = regs->r9;
4353 env->regs[10] = regs->r10;
4354 env->regs[11] = regs->r11;
4355 env->regs[12] = regs->r12;
4356 env->regs[13] = regs->r13;
4357 env->regs[14] = info->start_stack;
4358 env->regs[15] = regs->acr;
4359 env->pc = regs->erp;
4360 }
a4c075f1
UH		 4361#elif defined(TARGET_S390X)
4362 {
4363 int i;
4364 for (i = 0; i < 16; i++) {
4365 env->regs[i] = regs->gprs[i];
4366 }
4367 env->psw.mask = regs->psw.mask;
4368 env->psw.addr = regs->psw.addr;
4369 }
b346ff46
FB		 4370#else
4371#error unsupported target CPU
4372#endif
31e31b8a 4373
d2fbca94 4374#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
a87295e8
PB		 4375 ts->stack_base = info->start_stack;
4376 ts->heap_base = info->brk;
4377 /* This will be filled in on the first SYS_HEAPINFO call. */
4378 ts->heap_limit = 0;
4379#endif
4380
74c33bed 4381 if (gdbstub_port) {
ff7a981a
PM		 4382 if (gdbserver_start(gdbstub_port) < 0) {
4383 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4384 gdbstub_port);
4385 exit(1);
4386 }
db6b81d4 4387 gdb_handlesig(cpu, 0);
1fddef4b 4388 }
1b6b029e
FB		 4389 cpu_loop(env);
4390 /* never exits */
31e31b8a
FB		 4391 return 0;
4392}
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