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cpu-exec: Purge all uses of ENV_GET_CPU()
[mirror_qemu.git] / linux-user / main.c
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31e31b8a 1/*
93ac68bc 2 * qemu user main
5fafdf24 3 *
68d0f70e 4 * Copyright (c) 2003-2008 Fabrice Bellard
31e31b8a
FB		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
8167ee88 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31e31b8a
FB		 18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <stdarg.h>
04369ff2 22#include <string.h>
31e31b8a 23#include <errno.h>
0ecfa993 24#include <unistd.h>
e441570f 25#include <sys/mman.h>
edf8e2af 26#include <sys/syscall.h>
703e0e89 27#include <sys/resource.h>
31e31b8a 28
3ef693a0 29#include "qemu.h"
ca10f867 30#include "qemu-common.h"
2b41f10e 31#include "cpu.h"
9002ec79 32#include "tcg.h"
1de7afc9
PB		 33#include "qemu/timer.h"
34#include "qemu/envlist.h"
d8fd2954 35#include "elf.h"
04a6dfeb 36
d088d664
AJ		 37char *exec_path;
38
1b530a6d 39int singlestep;
fc9c5412
JS		 40const char *filename;
41const char *argv0;
42int gdbstub_port;
43envlist_t *envlist;
51fb256a 44static const char *cpu_model;
379f6698 45unsigned long mmap_min_addr;
14f24e14 46#if defined(CONFIG_USE_GUEST_BASE)
379f6698
PB		 47unsigned long guest_base;
48int have_guest_base;
288e65b9
AG		 49#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
50/*
51 * When running 32-on-64 we should make sure we can fit all of the possible
52 * guest address space into a contiguous chunk of virtual host memory.
53 *
54 * This way we will never overlap with our own libraries or binaries or stack
55 * or anything else that QEMU maps.
56 */
314992b1
AG		 57# ifdef TARGET_MIPS
58/* MIPS only supports 31 bits of virtual address space for user space */
59unsigned long reserved_va = 0x77000000;
60# else
288e65b9 61unsigned long reserved_va = 0xf7000000;
314992b1 62# endif
288e65b9 63#else
68a1c816 64unsigned long reserved_va;
379f6698 65#endif
288e65b9 66#endif
1b530a6d 67
fc9c5412
JS		 68static void usage(void);
69
7ee2822c 70static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
e586822a 71const char *qemu_uname_release;
586314f2 72
9de5e440
FB		 73/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
74 we allocate a bigger stack. Need a better solution, for example
75 by remapping the process stack directly at the right place */
703e0e89 76unsigned long guest_stack_size = 8 * 1024 * 1024UL;
31e31b8a
FB		 77
78void gemu_log(const char *fmt, ...)
79{
80 va_list ap;
81
82 va_start(ap, fmt);
83 vfprintf(stderr, fmt, ap);
84 va_end(ap);
85}
86
8fcd3692 87#if defined(TARGET_I386)
05390248 88int cpu_get_pic_interrupt(CPUX86State *env)
92ccca6a
FB		 89{
90 return -1;
91}
8fcd3692 92#endif
92ccca6a 93
d5975363
PB		 94/***********************************************************/
95/* Helper routines for implementing atomic operations. */
96
97/* To implement exclusive operations we force all cpus to syncronise.
98 We don't require a full sync, only that no cpus are executing guest code.
99 The alternative is to map target atomic ops onto host equivalents,
100 which requires quite a lot of per host/target work. */
c2764719 101static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
d5975363
PB		 102static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
103static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
104static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
105static int pending_cpus;
106
107/* Make sure everything is in a consistent state for calling fork(). */
108void fork_start(void)
109{
5e5f07e0 110 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 111 pthread_mutex_lock(&exclusive_lock);
d032d1b4 112 mmap_fork_start();
d5975363
PB		 113}
114
115void fork_end(int child)
116{
d032d1b4 117 mmap_fork_end(child);
d5975363 118 if (child) {
bdc44640 119 CPUState *cpu, *next_cpu;
d5975363
PB		 120 /* Child processes created by fork() only have a single thread.
121 Discard information about the parent threads. */
bdc44640
AF		 122 CPU_FOREACH_SAFE(cpu, next_cpu) {
123 if (cpu != thread_cpu) {
124 QTAILQ_REMOVE(&cpus, thread_cpu, node);
125 }
126 }
d5975363
PB		 127 pending_cpus = 0;
128 pthread_mutex_init(&exclusive_lock, NULL);
c2764719 129 pthread_mutex_init(&cpu_list_mutex, NULL);
d5975363
PB		 130 pthread_cond_init(&exclusive_cond, NULL);
131 pthread_cond_init(&exclusive_resume, NULL);
5e5f07e0 132 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
f7ec7f7b 133 gdbserver_fork(thread_cpu);
d5975363
PB		 134 } else {
135 pthread_mutex_unlock(&exclusive_lock);
5e5f07e0 136 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 137 }
d5975363
PB		 138}
139
140/* Wait for pending exclusive operations to complete. The exclusive lock
141 must be held. */
142static inline void exclusive_idle(void)
143{
144 while (pending_cpus) {
145 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
146 }
147}
148
149/* Start an exclusive operation.
150 Must only be called from outside cpu_arm_exec. */
151static inline void start_exclusive(void)
152{
0315c31c
AF		 153 CPUState *other_cpu;
154
d5975363
PB		 155 pthread_mutex_lock(&exclusive_lock);
156 exclusive_idle();
157
158 pending_cpus = 1;
159 /* Make all other cpus stop executing. */
bdc44640 160 CPU_FOREACH(other_cpu) {
0315c31c 161 if (other_cpu->running) {
d5975363 162 pending_cpus++;
60a3e17a 163 cpu_exit(other_cpu);
d5975363
PB		 164 }
165 }
166 if (pending_cpus > 1) {
167 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
168 }
169}
170
171/* Finish an exclusive operation. */
f7e61b22 172static inline void __attribute__((unused)) end_exclusive(void)
d5975363
PB		 173{
174 pending_cpus = 0;
175 pthread_cond_broadcast(&exclusive_resume);
176 pthread_mutex_unlock(&exclusive_lock);
177}
178
179/* Wait for exclusive ops to finish, and begin cpu execution. */
0315c31c 180static inline void cpu_exec_start(CPUState *cpu)
d5975363
PB		 181{
182 pthread_mutex_lock(&exclusive_lock);
183 exclusive_idle();
0315c31c 184 cpu->running = true;
d5975363
PB		 185 pthread_mutex_unlock(&exclusive_lock);
186}
187
188/* Mark cpu as not executing, and release pending exclusive ops. */
0315c31c 189static inline void cpu_exec_end(CPUState *cpu)
d5975363
PB		 190{
191 pthread_mutex_lock(&exclusive_lock);
0315c31c 192 cpu->running = false;
d5975363
PB		 193 if (pending_cpus > 1) {
194 pending_cpus--;
195 if (pending_cpus == 1) {
196 pthread_cond_signal(&exclusive_cond);
197 }
198 }
199 exclusive_idle();
200 pthread_mutex_unlock(&exclusive_lock);
201}
c2764719
PB		 202
203void cpu_list_lock(void)
204{
205 pthread_mutex_lock(&cpu_list_mutex);
206}
207
208void cpu_list_unlock(void)
209{
210 pthread_mutex_unlock(&cpu_list_mutex);
211}
d5975363
PB		 212
213
a541f297
FB		 214#ifdef TARGET_I386
215/***********************************************************/
216/* CPUX86 core interface */
217
28ab0e2e
FB		 218uint64_t cpu_get_tsc(CPUX86State *env)
219{
220 return cpu_get_real_ticks();
221}
222
5fafdf24 223static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
f4beb510 224 int flags)
6dbad63e 225{
f4beb510 226 unsigned int e1, e2;
53a5960a 227 uint32_t *p;
6dbad63e
FB		 228 e1 = (addr << 16) | (limit & 0xffff);
229 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
f4beb510 230 e2 |= flags;
53a5960a 231 p = ptr;
d538e8f5 232 p[0] = tswap32(e1);
233 p[1] = tswap32(e2);
f4beb510
FB		 234}
235
e441570f 236static uint64_t *idt_table;
eb38c52c 237#ifdef TARGET_X86_64
d2fd1af7
FB		 238static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
239 uint64_t addr, unsigned int sel)
f4beb510 240{
4dbc422b 241 uint32_t *p, e1, e2;
f4beb510
FB		 242 e1 = (addr & 0xffff) | (sel << 16);
243 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
53a5960a 244 p = ptr;
4dbc422b
FB		 245 p[0] = tswap32(e1);
246 p[1] = tswap32(e2);
247 p[2] = tswap32(addr >> 32);
248 p[3] = 0;
6dbad63e 249}
d2fd1af7
FB		 250/* only dpl matters as we do only user space emulation */
251static void set_idt(int n, unsigned int dpl)
252{
253 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
254}
255#else
d2fd1af7
FB		 256static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
257 uint32_t addr, unsigned int sel)
258{
4dbc422b 259 uint32_t *p, e1, e2;
d2fd1af7
FB		 260 e1 = (addr & 0xffff) | (sel << 16);
261 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
262 p = ptr;
4dbc422b
FB		 263 p[0] = tswap32(e1);
264 p[1] = tswap32(e2);
d2fd1af7
FB		 265}
266
f4beb510
FB		 267/* only dpl matters as we do only user space emulation */
268static void set_idt(int n, unsigned int dpl)
269{
270 set_gate(idt_table + n, 0, dpl, 0, 0);
271}
d2fd1af7 272#endif
31e31b8a 273
89e957e7 274void cpu_loop(CPUX86State *env)
1b6b029e 275{
db6b81d4 276 CPUState *cs = CPU(x86_env_get_cpu(env));
bc8a22cc 277 int trapnr;
992f48a0 278 abi_ulong pc;
c227f099 279 target_siginfo_t info;
851e67a1 280
1b6b029e 281 for(;;) {
b040bc9c 282 cpu_exec_start(cs);
ea3e9847 283 trapnr = cpu_x86_exec(cs);
b040bc9c 284 cpu_exec_end(cs);
bc8a22cc 285 switch(trapnr) {
f4beb510 286 case 0x80:
d2fd1af7 287 /* linux syscall from int $0x80 */
5fafdf24
TS		 288 env->regs[R_EAX] = do_syscall(env,
289 env->regs[R_EAX],
f4beb510
FB		 290 env->regs[R_EBX],
291 env->regs[R_ECX],
292 env->regs[R_EDX],
293 env->regs[R_ESI],
294 env->regs[R_EDI],
5945cfcb
PM		 295 env->regs[R_EBP],
296 0, 0);
f4beb510 297 break;
d2fd1af7
FB		 298#ifndef TARGET_ABI32
299 case EXCP_SYSCALL:
5ba18547 300 /* linux syscall from syscall instruction */
d2fd1af7
FB		 301 env->regs[R_EAX] = do_syscall(env,
302 env->regs[R_EAX],
303 env->regs[R_EDI],
304 env->regs[R_ESI],
305 env->regs[R_EDX],
306 env->regs[10],
307 env->regs[8],
5945cfcb
PM		 308 env->regs[9],
309 0, 0);
d2fd1af7
FB		 310 break;
311#endif
f4beb510
FB		 312 case EXCP0B_NOSEG:
313 case EXCP0C_STACK:
a86b3c64 314 info.si_signo = TARGET_SIGBUS;
f4beb510
FB		 315 info.si_errno = 0;
316 info.si_code = TARGET_SI_KERNEL;
317 info._sifields._sigfault._addr = 0;
624f7979 318 queue_signal(env, info.si_signo, &info);
f4beb510 319 break;
1b6b029e 320 case EXCP0D_GPF:
d2fd1af7 321 /* XXX: potential problem if ABI32 */
84409ddb 322#ifndef TARGET_X86_64
851e67a1 323 if (env->eflags & VM_MASK) {
89e957e7 324 handle_vm86_fault(env);
84409ddb
JM		 325 } else
326#endif
327 {
a86b3c64 328 info.si_signo = TARGET_SIGSEGV;
f4beb510
FB		 329 info.si_errno = 0;
330 info.si_code = TARGET_SI_KERNEL;
331 info._sifields._sigfault._addr = 0;
624f7979 332 queue_signal(env, info.si_signo, &info);
1b6b029e
FB		 333 }
334 break;
b689bc57 335 case EXCP0E_PAGE:
a86b3c64 336 info.si_signo = TARGET_SIGSEGV;
b689bc57
FB		 337 info.si_errno = 0;
338 if (!(env->error_code & 1))
339 info.si_code = TARGET_SEGV_MAPERR;
340 else
341 info.si_code = TARGET_SEGV_ACCERR;
970a87a6 342 info._sifields._sigfault._addr = env->cr[2];
624f7979 343 queue_signal(env, info.si_signo, &info);
b689bc57 344 break;
9de5e440 345 case EXCP00_DIVZ:
84409ddb 346#ifndef TARGET_X86_64
bc8a22cc 347 if (env->eflags & VM_MASK) {
447db213 348 handle_vm86_trap(env, trapnr);
84409ddb
JM		 349 } else
350#endif
351 {
bc8a22cc 352 /* division by zero */
a86b3c64 353 info.si_signo = TARGET_SIGFPE;
bc8a22cc
FB		 354 info.si_errno = 0;
355 info.si_code = TARGET_FPE_INTDIV;
356 info._sifields._sigfault._addr = env->eip;
624f7979 357 queue_signal(env, info.si_signo, &info);
bc8a22cc 358 }
9de5e440 359 break;
01df040b 360 case EXCP01_DB:
447db213 361 case EXCP03_INT3:
84409ddb 362#ifndef TARGET_X86_64
447db213
FB		 363 if (env->eflags & VM_MASK) {
364 handle_vm86_trap(env, trapnr);
84409ddb
JM		 365 } else
366#endif
367 {
a86b3c64 368 info.si_signo = TARGET_SIGTRAP;
447db213 369 info.si_errno = 0;
01df040b 370 if (trapnr == EXCP01_DB) {
447db213
FB		 371 info.si_code = TARGET_TRAP_BRKPT;
372 info._sifields._sigfault._addr = env->eip;
373 } else {
374 info.si_code = TARGET_SI_KERNEL;
375 info._sifields._sigfault._addr = 0;
376 }
624f7979 377 queue_signal(env, info.si_signo, &info);
447db213
FB		 378 }
379 break;
9de5e440
FB		 380 case EXCP04_INTO:
381 case EXCP05_BOUND:
84409ddb 382#ifndef TARGET_X86_64
bc8a22cc 383 if (env->eflags & VM_MASK) {
447db213 384 handle_vm86_trap(env, trapnr);
84409ddb
JM		 385 } else
386#endif
387 {
a86b3c64 388 info.si_signo = TARGET_SIGSEGV;
bc8a22cc 389 info.si_errno = 0;
b689bc57 390 info.si_code = TARGET_SI_KERNEL;
bc8a22cc 391 info._sifields._sigfault._addr = 0;
624f7979 392 queue_signal(env, info.si_signo, &info);
bc8a22cc 393 }
9de5e440
FB		 394 break;
395 case EXCP06_ILLOP:
a86b3c64 396 info.si_signo = TARGET_SIGILL;
9de5e440
FB		 397 info.si_errno = 0;
398 info.si_code = TARGET_ILL_ILLOPN;
399 info._sifields._sigfault._addr = env->eip;
624f7979 400 queue_signal(env, info.si_signo, &info);
9de5e440
FB		 401 break;
402 case EXCP_INTERRUPT:
403 /* just indicate that signals should be handled asap */
404 break;
1fddef4b
FB		 405 case EXCP_DEBUG:
406 {
407 int sig;
408
db6b81d4 409 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 410 if (sig)
411 {
412 info.si_signo = sig;
413 info.si_errno = 0;
414 info.si_code = TARGET_TRAP_BRKPT;
624f7979 415 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 416 }
417 }
418 break;
1b6b029e 419 default:
970a87a6 420 pc = env->segs[R_CS].base + env->eip;
5fafdf24 421 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
bc8a22cc 422 (long)pc, trapnr);
1b6b029e
FB		 423 abort();
424 }
66fb9763 425 process_pending_signals(env);
1b6b029e
FB		 426 }
427}
b346ff46
FB		 428#endif
429
430#ifdef TARGET_ARM
431
d8fd2954
PB		 432#define get_user_code_u32(x, gaddr, doswap) \
433 ({ abi_long __r = get_user_u32((x), (gaddr)); \
434 if (!__r && (doswap)) { \
435 (x) = bswap32(x); \
436 } \
437 __r; \
438 })
439
440#define get_user_code_u16(x, gaddr, doswap) \
441 ({ abi_long __r = get_user_u16((x), (gaddr)); \
442 if (!__r && (doswap)) { \
443 (x) = bswap16(x); \
444 } \
445 __r; \
446 })
447
1861c454
PM		 448#ifdef TARGET_ABI32
449/* Commpage handling -- there is no commpage for AArch64 */
450
97cc7560
DDAG		 451/*
452 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
453 * Input:
454 * r0 = pointer to oldval
455 * r1 = pointer to newval
456 * r2 = pointer to target value
457 *
458 * Output:
459 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
460 * C set if *ptr was changed, clear if no exchange happened
461 *
462 * Note segv's in kernel helpers are a bit tricky, we can set the
463 * data address sensibly but the PC address is just the entry point.
464 */
465static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
466{
467 uint64_t oldval, newval, val;
468 uint32_t addr, cpsr;
469 target_siginfo_t info;
470
471 /* Based on the 32 bit code in do_kernel_trap */
472
473 /* XXX: This only works between threads, not between processes.
474 It's probably possible to implement this with native host
475 operations. However things like ldrex/strex are much harder so
476 there's not much point trying. */
477 start_exclusive();
478 cpsr = cpsr_read(env);
479 addr = env->regs[2];
480
481 if (get_user_u64(oldval, env->regs[0])) {
abf1172f 482 env->exception.vaddress = env->regs[0];
97cc7560
DDAG		 483 goto segv;
484 };
485
486 if (get_user_u64(newval, env->regs[1])) {
abf1172f 487 env->exception.vaddress = env->regs[1];
97cc7560
DDAG		 488 goto segv;
489 };
490
491 if (get_user_u64(val, addr)) {
abf1172f 492 env->exception.vaddress = addr;
97cc7560
DDAG		 493 goto segv;
494 }
495
496 if (val == oldval) {
497 val = newval;
498
499 if (put_user_u64(val, addr)) {
abf1172f 500 env->exception.vaddress = addr;
97cc7560
DDAG		 501 goto segv;
502 };
503
504 env->regs[0] = 0;
505 cpsr |= CPSR_C;
506 } else {
507 env->regs[0] = -1;
508 cpsr &= ~CPSR_C;
509 }
510 cpsr_write(env, cpsr, CPSR_C);
511 end_exclusive();
512 return;
513
514segv:
515 end_exclusive();
516 /* We get the PC of the entry address - which is as good as anything,
517 on a real kernel what you get depends on which mode it uses. */
a86b3c64 518 info.si_signo = TARGET_SIGSEGV;
97cc7560
DDAG		 519 info.si_errno = 0;
520 /* XXX: check env->error_code */
521 info.si_code = TARGET_SEGV_MAPERR;
abf1172f 522 info._sifields._sigfault._addr = env->exception.vaddress;
97cc7560 523 queue_signal(env, info.si_signo, &info);
97cc7560
DDAG		 524}
525
fbb4a2e3
PB		 526/* Handle a jump to the kernel code page. */
527static int
528do_kernel_trap(CPUARMState *env)
529{
530 uint32_t addr;
531 uint32_t cpsr;
532 uint32_t val;
533
534 switch (env->regs[15]) {
535 case 0xffff0fa0: /* __kernel_memory_barrier */
536 /* ??? No-op. Will need to do better for SMP. */
537 break;
538 case 0xffff0fc0: /* __kernel_cmpxchg */
d5975363
PB		 539 /* XXX: This only works between threads, not between processes.
540 It's probably possible to implement this with native host
541 operations. However things like ldrex/strex are much harder so
542 there's not much point trying. */
543 start_exclusive();
fbb4a2e3
PB		 544 cpsr = cpsr_read(env);
545 addr = env->regs[2];
546 /* FIXME: This should SEGV if the access fails. */
547 if (get_user_u32(val, addr))
548 val = ~env->regs[0];
549 if (val == env->regs[0]) {
550 val = env->regs[1];
551 /* FIXME: Check for segfaults. */
552 put_user_u32(val, addr);
553 env->regs[0] = 0;
554 cpsr |= CPSR_C;
555 } else {
556 env->regs[0] = -1;
557 cpsr &= ~CPSR_C;
558 }
559 cpsr_write(env, cpsr, CPSR_C);
d5975363 560 end_exclusive();
fbb4a2e3
PB		 561 break;
562 case 0xffff0fe0: /* __kernel_get_tls */
b8d43285 563 env->regs[0] = cpu_get_tls(env);
fbb4a2e3 564 break;
97cc7560
DDAG		 565 case 0xffff0f60: /* __kernel_cmpxchg64 */
566 arm_kernel_cmpxchg64_helper(env);
567 break;
568
fbb4a2e3
PB		 569 default:
570 return 1;
571 }
572 /* Jump back to the caller. */
573 addr = env->regs[14];
574 if (addr & 1) {
575 env->thumb = 1;
576 addr &= ~1;
577 }
578 env->regs[15] = addr;
579
580 return 0;
581}
582
fa2ef212 583/* Store exclusive handling for AArch32 */
426f5abc
PB		 584static int do_strex(CPUARMState *env)
585{
03d05e2d 586 uint64_t val;
426f5abc
PB		 587 int size;
588 int rc = 1;
589 int segv = 0;
590 uint32_t addr;
591 start_exclusive();
03d05e2d 592 if (env->exclusive_addr != env->exclusive_test) {
426f5abc
PB		 593 goto fail;
594 }
03d05e2d
PM		 595 /* We know we're always AArch32 so the address is in uint32_t range
596 * unless it was the -1 exclusive-monitor-lost value (which won't
597 * match exclusive_test above).
598 */
599 assert(extract64(env->exclusive_addr, 32, 32) == 0);
600 addr = env->exclusive_addr;
426f5abc
PB		 601 size = env->exclusive_info & 0xf;
602 switch (size) {
603 case 0:
604 segv = get_user_u8(val, addr);
605 break;
606 case 1:
607 segv = get_user_u16(val, addr);
608 break;
609 case 2:
610 case 3:
611 segv = get_user_u32(val, addr);
612 break;
f7001a3b
AJ		 613 default:
614 abort();
426f5abc
PB		 615 }
616 if (segv) {
abf1172f 617 env->exception.vaddress = addr;
426f5abc
PB		 618 goto done;
619 }
426f5abc 620 if (size == 3) {
03d05e2d
PM		 621 uint32_t valhi;
622 segv = get_user_u32(valhi, addr + 4);
426f5abc 623 if (segv) {
abf1172f 624 env->exception.vaddress = addr + 4;
426f5abc
PB		 625 goto done;
626 }
03d05e2d 627 val = deposit64(val, 32, 32, valhi);
426f5abc 628 }
03d05e2d
PM		 629 if (val != env->exclusive_val) {
630 goto fail;
631 }
632
426f5abc
PB		 633 val = env->regs[(env->exclusive_info >> 8) & 0xf];
634 switch (size) {
635 case 0:
636 segv = put_user_u8(val, addr);
637 break;
638 case 1:
639 segv = put_user_u16(val, addr);
640 break;
641 case 2:
642 case 3:
643 segv = put_user_u32(val, addr);
644 break;
645 }
646 if (segv) {
abf1172f 647 env->exception.vaddress = addr;
426f5abc
PB		 648 goto done;
649 }
650 if (size == 3) {
651 val = env->regs[(env->exclusive_info >> 12) & 0xf];
2c9adbda 652 segv = put_user_u32(val, addr + 4);
426f5abc 653 if (segv) {
abf1172f 654 env->exception.vaddress = addr + 4;
426f5abc
PB		 655 goto done;
656 }
657 }
658 rc = 0;
659fail:
725b8a69 660 env->regs[15] += 4;
426f5abc
PB		 661 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
662done:
663 end_exclusive();
664 return segv;
665}
666
b346ff46
FB		 667void cpu_loop(CPUARMState *env)
668{
0315c31c 669 CPUState *cs = CPU(arm_env_get_cpu(env));
b346ff46
FB		 670 int trapnr;
671 unsigned int n, insn;
c227f099 672 target_siginfo_t info;
b5ff1b31 673 uint32_t addr;
3b46e624 674
b346ff46 675 for(;;) {
0315c31c 676 cpu_exec_start(cs);
ea3e9847 677 trapnr = cpu_arm_exec(cs);
0315c31c 678 cpu_exec_end(cs);
b346ff46
FB		 679 switch(trapnr) {
680 case EXCP_UDEF:
c6981055 681 {
0429a971 682 TaskState *ts = cs->opaque;
c6981055 683 uint32_t opcode;
6d9a42be 684 int rc;
c6981055
FB		 685
686 /* we handle the FPU emulation here, as Linux */
687 /* we get the opcode */
2f619698 688 /* FIXME - what to do if get_user() fails? */
d8fd2954 689 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
3b46e624 690
6d9a42be
AJ		 691 rc = EmulateAll(opcode, &ts->fpa, env);
692 if (rc == 0) { /* illegal instruction */
a86b3c64 693 info.si_signo = TARGET_SIGILL;
c6981055
FB		 694 info.si_errno = 0;
695 info.si_code = TARGET_ILL_ILLOPN;
696 info._sifields._sigfault._addr = env->regs[15];
624f7979 697 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 698 } else if (rc < 0) { /* FP exception */
699 int arm_fpe=0;
700
701 /* translate softfloat flags to FPSR flags */
702 if (-rc & float_flag_invalid)
703 arm_fpe |= BIT_IOC;
704 if (-rc & float_flag_divbyzero)
705 arm_fpe |= BIT_DZC;
706 if (-rc & float_flag_overflow)
707 arm_fpe |= BIT_OFC;
708 if (-rc & float_flag_underflow)
709 arm_fpe |= BIT_UFC;
710 if (-rc & float_flag_inexact)
711 arm_fpe |= BIT_IXC;
712
713 FPSR fpsr = ts->fpa.fpsr;
714 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
715
716 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
a86b3c64 717 info.si_signo = TARGET_SIGFPE;
6d9a42be
AJ		 718 info.si_errno = 0;
719
720 /* ordered by priority, least first */
721 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
722 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
723 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
724 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
725 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
726
727 info._sifields._sigfault._addr = env->regs[15];
624f7979 728 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 729 } else {
730 env->regs[15] += 4;
731 }
732
733 /* accumulate unenabled exceptions */
734 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
735 fpsr |= BIT_IXC;
736 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
737 fpsr |= BIT_UFC;
738 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
739 fpsr |= BIT_OFC;
740 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
741 fpsr |= BIT_DZC;
742 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
743 fpsr |= BIT_IOC;
744 ts->fpa.fpsr=fpsr;
745 } else { /* everything OK */
c6981055
FB		 746 /* increment PC */
747 env->regs[15] += 4;
748 }
749 }
b346ff46
FB		 750 break;
751 case EXCP_SWI:
06c949e6 752 case EXCP_BKPT:
b346ff46 753 {
ce4defa0 754 env->eabi = 1;
b346ff46 755 /* system call */
06c949e6
PB		 756 if (trapnr == EXCP_BKPT) {
757 if (env->thumb) {
2f619698 758 /* FIXME - what to do if get_user() fails? */
d8fd2954 759 get_user_code_u16(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 760 n = insn & 0xff;
761 env->regs[15] += 2;
762 } else {
2f619698 763 /* FIXME - what to do if get_user() fails? */
d8fd2954 764 get_user_code_u32(insn, env->regs[15], env->bswap_code);
06c949e6
PB		 765 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
766 env->regs[15] += 4;
767 }
192c7bd9 768 } else {
06c949e6 769 if (env->thumb) {
2f619698 770 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 771 get_user_code_u16(insn, env->regs[15] - 2,
772 env->bswap_code);
06c949e6
PB		 773 n = insn & 0xff;
774 } else {
2f619698 775 /* FIXME - what to do if get_user() fails? */
d8fd2954
PB		 776 get_user_code_u32(insn, env->regs[15] - 4,
777 env->bswap_code);
06c949e6
PB		 778 n = insn & 0xffffff;
779 }
192c7bd9
FB		 780 }
781
6f1f31c0 782 if (n == ARM_NR_cacheflush) {
dcfd14b3 783 /* nop */
a4f81979
FB		 784 } else if (n == ARM_NR_semihosting
785 || n == ARM_NR_thumb_semihosting) {
786 env->regs[0] = do_arm_semihosting (env);
3a1363ac 787 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
b346ff46 788 /* linux syscall */
ce4defa0 789 if (env->thumb || n == 0) {
192c7bd9
FB		 790 n = env->regs[7];
791 } else {
792 n -= ARM_SYSCALL_BASE;
ce4defa0 793 env->eabi = 0;
192c7bd9 794 }
fbb4a2e3
PB		 795 if ( n > ARM_NR_BASE) {
796 switch (n) {
797 case ARM_NR_cacheflush:
dcfd14b3 798 /* nop */
fbb4a2e3
PB		 799 break;
800 case ARM_NR_set_tls:
801 cpu_set_tls(env, env->regs[0]);
802 env->regs[0] = 0;
803 break;
d5355087
HL		 804 case ARM_NR_breakpoint:
805 env->regs[15] -= env->thumb ? 2 : 4;
806 goto excp_debug;
fbb4a2e3
PB		 807 default:
808 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
809 n);
810 env->regs[0] = -TARGET_ENOSYS;
811 break;
812 }
813 } else {
814 env->regs[0] = do_syscall(env,
815 n,
816 env->regs[0],
817 env->regs[1],
818 env->regs[2],
819 env->regs[3],
820 env->regs[4],
5945cfcb
PM		 821 env->regs[5],
822 0, 0);
fbb4a2e3 823 }
b346ff46
FB		 824 } else {
825 goto error;
826 }
827 }
828 break;
43fff238
FB		 829 case EXCP_INTERRUPT:
830 /* just indicate that signals should be handled asap */
831 break;
abf1172f
PM		 832 case EXCP_STREX:
833 if (!do_strex(env)) {
834 break;
835 }
836 /* fall through for segv */
68016c62
FB		 837 case EXCP_PREFETCH_ABORT:
838 case EXCP_DATA_ABORT:
abf1172f 839 addr = env->exception.vaddress;
68016c62 840 {
a86b3c64 841 info.si_signo = TARGET_SIGSEGV;
68016c62
FB		 842 info.si_errno = 0;
843 /* XXX: check env->error_code */
844 info.si_code = TARGET_SEGV_MAPERR;
b5ff1b31 845 info._sifields._sigfault._addr = addr;
624f7979 846 queue_signal(env, info.si_signo, &info);
68016c62
FB		 847 }
848 break;
1fddef4b 849 case EXCP_DEBUG:
d5355087 850 excp_debug:
1fddef4b
FB		 851 {
852 int sig;
853
db6b81d4 854 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 855 if (sig)
856 {
857 info.si_signo = sig;
858 info.si_errno = 0;
859 info.si_code = TARGET_TRAP_BRKPT;
624f7979 860 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 861 }
862 }
863 break;
fbb4a2e3
PB		 864 case EXCP_KERNEL_TRAP:
865 if (do_kernel_trap(env))
866 goto error;
867 break;
b346ff46
FB		 868 default:
869 error:
5fafdf24 870 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
b346ff46 871 trapnr);
878096ee 872 cpu_dump_state(cs, stderr, fprintf, 0);
b346ff46
FB		 873 abort();
874 }
875 process_pending_signals(env);
876 }
877}
878
1861c454
PM		 879#else
880
fa2ef212
MM		 881/*
882 * Handle AArch64 store-release exclusive
883 *
884 * rs = gets the status result of store exclusive
885 * rt = is the register that is stored
886 * rt2 = is the second register store (in STP)
887 *
888 */
889static int do_strex_a64(CPUARMState *env)
890{
891 uint64_t val;
892 int size;
893 bool is_pair;
894 int rc = 1;
895 int segv = 0;
896 uint64_t addr;
897 int rs, rt, rt2;
898
899 start_exclusive();
900 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
901 size = extract32(env->exclusive_info, 0, 2);
902 is_pair = extract32(env->exclusive_info, 2, 1);
903 rs = extract32(env->exclusive_info, 4, 5);
904 rt = extract32(env->exclusive_info, 9, 5);
905 rt2 = extract32(env->exclusive_info, 14, 5);
906
907 addr = env->exclusive_addr;
908
909 if (addr != env->exclusive_test) {
910 goto finish;
911 }
912
913 switch (size) {
914 case 0:
915 segv = get_user_u8(val, addr);
916 break;
917 case 1:
918 segv = get_user_u16(val, addr);
919 break;
920 case 2:
921 segv = get_user_u32(val, addr);
922 break;
923 case 3:
924 segv = get_user_u64(val, addr);
925 break;
926 default:
927 abort();
928 }
929 if (segv) {
abf1172f 930 env->exception.vaddress = addr;
fa2ef212
MM		 931 goto error;
932 }
933 if (val != env->exclusive_val) {
934 goto finish;
935 }
936 if (is_pair) {
937 if (size == 2) {
938 segv = get_user_u32(val, addr + 4);
939 } else {
940 segv = get_user_u64(val, addr + 8);
941 }
942 if (segv) {
abf1172f 943 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 944 goto error;
945 }
946 if (val != env->exclusive_high) {
947 goto finish;
948 }
949 }
2ea5a2ca
JG		 950 /* handle the zero register */
951 val = rt == 31 ? 0 : env->xregs[rt];
fa2ef212
MM		 952 switch (size) {
953 case 0:
954 segv = put_user_u8(val, addr);
955 break;
956 case 1:
957 segv = put_user_u16(val, addr);
958 break;
959 case 2:
960 segv = put_user_u32(val, addr);
961 break;
962 case 3:
963 segv = put_user_u64(val, addr);
964 break;
965 }
966 if (segv) {
967 goto error;
968 }
969 if (is_pair) {
2ea5a2ca
JG		 970 /* handle the zero register */
971 val = rt2 == 31 ? 0 : env->xregs[rt2];
fa2ef212
MM		 972 if (size == 2) {
973 segv = put_user_u32(val, addr + 4);
974 } else {
975 segv = put_user_u64(val, addr + 8);
976 }
977 if (segv) {
abf1172f 978 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 979 goto error;
980 }
981 }
982 rc = 0;
983finish:
984 env->pc += 4;
985 /* rs == 31 encodes a write to the ZR, thus throwing away
986 * the status return. This is rather silly but valid.
987 */
988 if (rs < 31) {
989 env->xregs[rs] = rc;
990 }
991error:
992 /* instruction faulted, PC does not advance */
993 /* either way a strex releases any exclusive lock we have */
994 env->exclusive_addr = -1;
995 end_exclusive();
996 return segv;
997}
998
1861c454
PM		 999/* AArch64 main loop */
1000void cpu_loop(CPUARMState *env)
1001{
1002 CPUState *cs = CPU(arm_env_get_cpu(env));
1003 int trapnr, sig;
1004 target_siginfo_t info;
1861c454
PM		 1005
1006 for (;;) {
1007 cpu_exec_start(cs);
ea3e9847 1008 trapnr = cpu_arm_exec(cs);
1861c454
PM		 1009 cpu_exec_end(cs);
1010
1011 switch (trapnr) {
1012 case EXCP_SWI:
1013 env->xregs[0] = do_syscall(env,
1014 env->xregs[8],
1015 env->xregs[0],
1016 env->xregs[1],
1017 env->xregs[2],
1018 env->xregs[3],
1019 env->xregs[4],
1020 env->xregs[5],
1021 0, 0);
1022 break;
1023 case EXCP_INTERRUPT:
1024 /* just indicate that signals should be handled asap */
1025 break;
1026 case EXCP_UDEF:
a86b3c64 1027 info.si_signo = TARGET_SIGILL;
1861c454
PM		 1028 info.si_errno = 0;
1029 info.si_code = TARGET_ILL_ILLOPN;
1030 info._sifields._sigfault._addr = env->pc;
1031 queue_signal(env, info.si_signo, &info);
1032 break;
abf1172f
PM		 1033 case EXCP_STREX:
1034 if (!do_strex_a64(env)) {
1035 break;
1036 }
1037 /* fall through for segv */
1861c454 1038 case EXCP_PREFETCH_ABORT:
1861c454 1039 case EXCP_DATA_ABORT:
a86b3c64 1040 info.si_signo = TARGET_SIGSEGV;
1861c454
PM		 1041 info.si_errno = 0;
1042 /* XXX: check env->error_code */
1043 info.si_code = TARGET_SEGV_MAPERR;
686581ad 1044 info._sifields._sigfault._addr = env->exception.vaddress;
1861c454
PM		 1045 queue_signal(env, info.si_signo, &info);
1046 break;
1047 case EXCP_DEBUG:
1048 case EXCP_BKPT:
1049 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1050 if (sig) {
1051 info.si_signo = sig;
1052 info.si_errno = 0;
1053 info.si_code = TARGET_TRAP_BRKPT;
1054 queue_signal(env, info.si_signo, &info);
1055 }
1056 break;
1861c454
PM		 1057 default:
1058 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
1059 trapnr);
1060 cpu_dump_state(cs, stderr, fprintf, 0);
1061 abort();
1062 }
1063 process_pending_signals(env);
fa2ef212
MM		 1064 /* Exception return on AArch64 always clears the exclusive monitor,
1065 * so any return to running guest code implies this.
1066 * A strex (successful or otherwise) also clears the monitor, so
1067 * we don't need to specialcase EXCP_STREX.
1068 */
1069 env->exclusive_addr = -1;
1861c454
PM		 1070 }
1071}
1072#endif /* ndef TARGET_ABI32 */
1073
b346ff46 1074#endif
1b6b029e 1075
d2fbca94
GX		 1076#ifdef TARGET_UNICORE32
1077
05390248 1078void cpu_loop(CPUUniCore32State *env)
d2fbca94 1079{
0315c31c 1080 CPUState *cs = CPU(uc32_env_get_cpu(env));
d2fbca94
GX		 1081 int trapnr;
1082 unsigned int n, insn;
1083 target_siginfo_t info;
1084
1085 for (;;) {
0315c31c 1086 cpu_exec_start(cs);
ea3e9847 1087 trapnr = uc32_cpu_exec(cs);
0315c31c 1088 cpu_exec_end(cs);
d2fbca94
GX		 1089 switch (trapnr) {
1090 case UC32_EXCP_PRIV:
1091 {
1092 /* system call */
1093 get_user_u32(insn, env->regs[31] - 4);
1094 n = insn & 0xffffff;
1095
1096 if (n >= UC32_SYSCALL_BASE) {
1097 /* linux syscall */
1098 n -= UC32_SYSCALL_BASE;
1099 if (n == UC32_SYSCALL_NR_set_tls) {
1100 cpu_set_tls(env, env->regs[0]);
1101 env->regs[0] = 0;
1102 } else {
1103 env->regs[0] = do_syscall(env,
1104 n,
1105 env->regs[0],
1106 env->regs[1],
1107 env->regs[2],
1108 env->regs[3],
1109 env->regs[4],
5945cfcb
PM		 1110 env->regs[5],
1111 0, 0);
d2fbca94
GX		 1112 }
1113 } else {
1114 goto error;
1115 }
1116 }
1117 break;
d48813dd
GX		 1118 case UC32_EXCP_DTRAP:
1119 case UC32_EXCP_ITRAP:
a86b3c64 1120 info.si_signo = TARGET_SIGSEGV;
d2fbca94
GX		 1121 info.si_errno = 0;
1122 /* XXX: check env->error_code */
1123 info.si_code = TARGET_SEGV_MAPERR;
1124 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1125 queue_signal(env, info.si_signo, &info);
1126 break;
1127 case EXCP_INTERRUPT:
1128 /* just indicate that signals should be handled asap */
1129 break;
1130 case EXCP_DEBUG:
1131 {
1132 int sig;
1133
db6b81d4 1134 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d2fbca94
GX		 1135 if (sig) {
1136 info.si_signo = sig;
1137 info.si_errno = 0;
1138 info.si_code = TARGET_TRAP_BRKPT;
1139 queue_signal(env, info.si_signo, &info);
1140 }
1141 }
1142 break;
1143 default:
1144 goto error;
1145 }
1146 process_pending_signals(env);
1147 }
1148
1149error:
1150 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
878096ee 1151 cpu_dump_state(cs, stderr, fprintf, 0);
d2fbca94
GX		 1152 abort();
1153}
1154#endif
1155
93ac68bc 1156#ifdef TARGET_SPARC
ed23fbd9 1157#define SPARC64_STACK_BIAS 2047
93ac68bc 1158
060366c5
FB		 1159//#define DEBUG_WIN
1160
2623cbaf
FB		 1161/* WARNING: dealing with register windows _is_ complicated. More info
1162 can be found at http://www.sics.se/~psm/sparcstack.html */
060366c5
FB		 1163static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1164{
1a14026e 1165 index = (index + cwp * 16) % (16 * env->nwindows);
060366c5
FB		 1166 /* wrap handling : if cwp is on the last window, then we use the
1167 registers 'after' the end */
1a14026e
BS		 1168 if (index < 8 && env->cwp == env->nwindows - 1)
1169 index += 16 * env->nwindows;
060366c5
FB		 1170 return index;
1171}
1172
2623cbaf
FB		 1173/* save the register window 'cwp1' */
1174static inline void save_window_offset(CPUSPARCState *env, int cwp1)
060366c5 1175{
2623cbaf 1176 unsigned int i;
992f48a0 1177 abi_ulong sp_ptr;
3b46e624 1178
53a5960a 1179 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1180#ifdef TARGET_SPARC64
1181 if (sp_ptr & 3)
1182 sp_ptr += SPARC64_STACK_BIAS;
1183#endif
060366c5 1184#if defined(DEBUG_WIN)
2daf0284
BS		 1185 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1186 sp_ptr, cwp1);
060366c5 1187#endif
2623cbaf 1188 for(i = 0; i < 16; i++) {
2f619698
FB		 1189 /* FIXME - what to do if put_user() fails? */
1190 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1191 sp_ptr += sizeof(abi_ulong);
2623cbaf 1192 }
060366c5
FB		 1193}
1194
1195static void save_window(CPUSPARCState *env)
1196{
5ef54116 1197#ifndef TARGET_SPARC64
2623cbaf 1198 unsigned int new_wim;
1a14026e
BS		 1199 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1200 ((1LL << env->nwindows) - 1);
1201 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
2623cbaf 1202 env->wim = new_wim;
5ef54116 1203#else
1a14026e 1204 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
5ef54116
FB		 1205 env->cansave++;
1206 env->canrestore--;
1207#endif
060366c5
FB		 1208}
1209
1210static void restore_window(CPUSPARCState *env)
1211{
eda52953
BS		 1212#ifndef TARGET_SPARC64
1213 unsigned int new_wim;
1214#endif
1215 unsigned int i, cwp1;
992f48a0 1216 abi_ulong sp_ptr;
3b46e624 1217
eda52953 1218#ifndef TARGET_SPARC64
1a14026e
BS		 1219 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1220 ((1LL << env->nwindows) - 1);
eda52953 1221#endif
3b46e624 1222
060366c5 1223 /* restore the invalid window */
1a14026e 1224 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
53a5960a 1225 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1226#ifdef TARGET_SPARC64
1227 if (sp_ptr & 3)
1228 sp_ptr += SPARC64_STACK_BIAS;
1229#endif
060366c5 1230#if defined(DEBUG_WIN)
2daf0284
BS		 1231 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1232 sp_ptr, cwp1);
060366c5 1233#endif
2623cbaf 1234 for(i = 0; i < 16; i++) {
2f619698
FB		 1235 /* FIXME - what to do if get_user() fails? */
1236 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1237 sp_ptr += sizeof(abi_ulong);
2623cbaf 1238 }
5ef54116
FB		 1239#ifdef TARGET_SPARC64
1240 env->canrestore++;
1a14026e
BS		 1241 if (env->cleanwin < env->nwindows - 1)
1242 env->cleanwin++;
5ef54116 1243 env->cansave--;
eda52953
BS		 1244#else
1245 env->wim = new_wim;
5ef54116 1246#endif
060366c5
FB		 1247}
1248
1249static void flush_windows(CPUSPARCState *env)
1250{
1251 int offset, cwp1;
2623cbaf
FB		 1252
1253 offset = 1;
060366c5
FB		 1254 for(;;) {
1255 /* if restore would invoke restore_window(), then we can stop */
1a14026e 1256 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
eda52953 1257#ifndef TARGET_SPARC64
060366c5
FB		 1258 if (env->wim & (1 << cwp1))
1259 break;
eda52953
BS		 1260#else
1261 if (env->canrestore == 0)
1262 break;
1263 env->cansave++;
1264 env->canrestore--;
1265#endif
2623cbaf 1266 save_window_offset(env, cwp1);
060366c5
FB		 1267 offset++;
1268 }
1a14026e 1269 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
eda52953
BS		 1270#ifndef TARGET_SPARC64
1271 /* set wim so that restore will reload the registers */
2623cbaf 1272 env->wim = 1 << cwp1;
eda52953 1273#endif
2623cbaf
FB		 1274#if defined(DEBUG_WIN)
1275 printf("flush_windows: nb=%d\n", offset - 1);
80a9d035 1276#endif
2623cbaf 1277}
060366c5 1278
93ac68bc
FB		 1279void cpu_loop (CPUSPARCState *env)
1280{
878096ee 1281 CPUState *cs = CPU(sparc_env_get_cpu(env));
2cc20260
RH		 1282 int trapnr;
1283 abi_long ret;
c227f099 1284 target_siginfo_t info;
3b46e624 1285
060366c5 1286 while (1) {
b040bc9c 1287 cpu_exec_start(cs);
ea3e9847 1288 trapnr = cpu_sparc_exec(cs);
b040bc9c 1289 cpu_exec_end(cs);
3b46e624 1290
20132b96
RH		 1291 /* Compute PSR before exposing state. */
1292 if (env->cc_op != CC_OP_FLAGS) {
1293 cpu_get_psr(env);
1294 }
1295
060366c5 1296 switch (trapnr) {
5ef54116 1297#ifndef TARGET_SPARC64
5fafdf24 1298 case 0x88:
060366c5 1299 case 0x90:
5ef54116 1300#else
cb33da57 1301 case 0x110:
5ef54116
FB		 1302 case 0x16d:
1303#endif
060366c5 1304 ret = do_syscall (env, env->gregs[1],
5fafdf24
TS		 1305 env->regwptr[0], env->regwptr[1],
1306 env->regwptr[2], env->regwptr[3],
5945cfcb
PM		 1307 env->regwptr[4], env->regwptr[5],
1308 0, 0);
2cc20260 1309 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
992f48a0 1310#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1311 env->xcc |= PSR_CARRY;
1312#else
060366c5 1313 env->psr |= PSR_CARRY;
27908725 1314#endif
060366c5
FB		 1315 ret = -ret;
1316 } else {
992f48a0 1317#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1318 env->xcc &= ~PSR_CARRY;
1319#else
060366c5 1320 env->psr &= ~PSR_CARRY;
27908725 1321#endif
060366c5
FB		 1322 }
1323 env->regwptr[0] = ret;
1324 /* next instruction */
1325 env->pc = env->npc;
1326 env->npc = env->npc + 4;
1327 break;
1328 case 0x83: /* flush windows */
992f48a0
BS		 1329#ifdef TARGET_ABI32
1330 case 0x103:
1331#endif
2623cbaf 1332 flush_windows(env);
060366c5
FB		 1333 /* next instruction */
1334 env->pc = env->npc;
1335 env->npc = env->npc + 4;
1336 break;
3475187d 1337#ifndef TARGET_SPARC64
060366c5
FB		 1338 case TT_WIN_OVF: /* window overflow */
1339 save_window(env);
1340 break;
1341 case TT_WIN_UNF: /* window underflow */
1342 restore_window(env);
1343 break;
61ff6f58
FB		 1344 case TT_TFAULT:
1345 case TT_DFAULT:
1346 {
59f7182f 1347 info.si_signo = TARGET_SIGSEGV;
61ff6f58
FB		 1348 info.si_errno = 0;
1349 /* XXX: check env->error_code */
1350 info.si_code = TARGET_SEGV_MAPERR;
1351 info._sifields._sigfault._addr = env->mmuregs[4];
624f7979 1352 queue_signal(env, info.si_signo, &info);
61ff6f58
FB		 1353 }
1354 break;
3475187d 1355#else
5ef54116
FB		 1356 case TT_SPILL: /* window overflow */
1357 save_window(env);
1358 break;
1359 case TT_FILL: /* window underflow */
1360 restore_window(env);
1361 break;
7f84a729
BS		 1362 case TT_TFAULT:
1363 case TT_DFAULT:
1364 {
59f7182f 1365 info.si_signo = TARGET_SIGSEGV;
7f84a729
BS		 1366 info.si_errno = 0;
1367 /* XXX: check env->error_code */
1368 info.si_code = TARGET_SEGV_MAPERR;
1369 if (trapnr == TT_DFAULT)
1370 info._sifields._sigfault._addr = env->dmmuregs[4];
1371 else
8194f35a 1372 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
624f7979 1373 queue_signal(env, info.si_signo, &info);
7f84a729
BS		 1374 }
1375 break;
27524dc3 1376#ifndef TARGET_ABI32
5bfb56b2
BS		 1377 case 0x16e:
1378 flush_windows(env);
1379 sparc64_get_context(env);
1380 break;
1381 case 0x16f:
1382 flush_windows(env);
1383 sparc64_set_context(env);
1384 break;
27524dc3 1385#endif
3475187d 1386#endif
48dc41eb
FB		 1387 case EXCP_INTERRUPT:
1388 /* just indicate that signals should be handled asap */
1389 break;
75f22e4e
RH		 1390 case TT_ILL_INSN:
1391 {
1392 info.si_signo = TARGET_SIGILL;
1393 info.si_errno = 0;
1394 info.si_code = TARGET_ILL_ILLOPC;
1395 info._sifields._sigfault._addr = env->pc;
1396 queue_signal(env, info.si_signo, &info);
1397 }
1398 break;
1fddef4b
FB		 1399 case EXCP_DEBUG:
1400 {
1401 int sig;
1402
db6b81d4 1403 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 1404 if (sig)
1405 {
1406 info.si_signo = sig;
1407 info.si_errno = 0;
1408 info.si_code = TARGET_TRAP_BRKPT;
624f7979 1409 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 1410 }
1411 }
1412 break;
060366c5
FB		 1413 default:
1414 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 1415 cpu_dump_state(cs, stderr, fprintf, 0);
060366c5
FB		 1416 exit (1);
1417 }
1418 process_pending_signals (env);
1419 }
93ac68bc
FB		 1420}
1421
1422#endif
1423
67867308 1424#ifdef TARGET_PPC
05390248 1425static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
9fddaa0c 1426{
7d6b1dae 1427 return cpu_get_real_ticks();
9fddaa0c 1428}
3b46e624 1429
05390248 1430uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
9fddaa0c 1431{
e3ea6529 1432 return cpu_ppc_get_tb(env);
9fddaa0c 1433}
3b46e624 1434
05390248 1435uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
9fddaa0c
FB		 1436{
1437 return cpu_ppc_get_tb(env) >> 32;
1438}
3b46e624 1439
05390248 1440uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
9fddaa0c 1441{
b711de95 1442 return cpu_ppc_get_tb(env);
9fddaa0c 1443}
5fafdf24 1444
05390248 1445uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
9fddaa0c 1446{
a062e36c 1447 return cpu_ppc_get_tb(env) >> 32;
9fddaa0c 1448}
76a66253 1449
05390248 1450uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
76a66253
JM		 1451__attribute__ (( alias ("cpu_ppc_load_tbu") ));
1452
05390248 1453uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
9fddaa0c 1454{
76a66253 1455 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
9fddaa0c 1456}
76a66253 1457
a750fc0b 1458/* XXX: to be fixed */
73b01960 1459int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
a750fc0b
JM		 1460{
1461 return -1;
1462}
1463
73b01960 1464int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
a750fc0b
JM		 1465{
1466 return -1;
1467}
1468
001faf32
BS		 1469#define EXCP_DUMP(env, fmt, ...) \
1470do { \
a0762859 1471 CPUState *cs = ENV_GET_CPU(env); \
001faf32 1472 fprintf(stderr, fmt , ## __VA_ARGS__); \
a0762859 1473 cpu_dump_state(cs, stderr, fprintf, 0); \
001faf32 1474 qemu_log(fmt, ## __VA_ARGS__); \
eeacee4d 1475 if (qemu_log_enabled()) { \
a0762859 1476 log_cpu_state(cs, 0); \
eeacee4d 1477 } \
e1833e1f
JM		 1478} while (0)
1479
56f066bb
NF		 1480static int do_store_exclusive(CPUPPCState *env)
1481{
1482 target_ulong addr;
1483 target_ulong page_addr;
e22c357b 1484 target_ulong val, val2 __attribute__((unused)) = 0;
56f066bb
NF		 1485 int flags;
1486 int segv = 0;
1487
1488 addr = env->reserve_ea;
1489 page_addr = addr & TARGET_PAGE_MASK;
1490 start_exclusive();
1491 mmap_lock();
1492 flags = page_get_flags(page_addr);
1493 if ((flags & PAGE_READ) == 0) {
1494 segv = 1;
1495 } else {
1496 int reg = env->reserve_info & 0x1f;
4b1daa72 1497 int size = env->reserve_info >> 5;
56f066bb
NF		 1498 int stored = 0;
1499
1500 if (addr == env->reserve_addr) {
1501 switch (size) {
1502 case 1: segv = get_user_u8(val, addr); break;
1503 case 2: segv = get_user_u16(val, addr); break;
1504 case 4: segv = get_user_u32(val, addr); break;
1505#if defined(TARGET_PPC64)
1506 case 8: segv = get_user_u64(val, addr); break;
27b95bfe
TM		 1507 case 16: {
1508 segv = get_user_u64(val, addr);
1509 if (!segv) {
1510 segv = get_user_u64(val2, addr + 8);
1511 }
1512 break;
1513 }
56f066bb
NF		 1514#endif
1515 default: abort();
1516 }
1517 if (!segv && val == env->reserve_val) {
1518 val = env->gpr[reg];
1519 switch (size) {
1520 case 1: segv = put_user_u8(val, addr); break;
1521 case 2: segv = put_user_u16(val, addr); break;
1522 case 4: segv = put_user_u32(val, addr); break;
1523#if defined(TARGET_PPC64)
1524 case 8: segv = put_user_u64(val, addr); break;
27b95bfe
TM		 1525 case 16: {
1526 if (val2 == env->reserve_val2) {
e22c357b
DK		 1527 if (msr_le) {
1528 val2 = val;
1529 val = env->gpr[reg+1];
1530 } else {
1531 val2 = env->gpr[reg+1];
1532 }
27b95bfe
TM		 1533 segv = put_user_u64(val, addr);
1534 if (!segv) {
1535 segv = put_user_u64(val2, addr + 8);
1536 }
1537 }
1538 break;
1539 }
56f066bb
NF		 1540#endif
1541 default: abort();
1542 }
1543 if (!segv) {
1544 stored = 1;
1545 }
1546 }
1547 }
1548 env->crf[0] = (stored << 1) | xer_so;
1549 env->reserve_addr = (target_ulong)-1;
1550 }
1551 if (!segv) {
1552 env->nip += 4;
1553 }
1554 mmap_unlock();
1555 end_exclusive();
1556 return segv;
1557}
1558
67867308
FB		 1559void cpu_loop(CPUPPCState *env)
1560{
0315c31c 1561 CPUState *cs = CPU(ppc_env_get_cpu(env));
c227f099 1562 target_siginfo_t info;
61190b14 1563 int trapnr;
9e0e2f96 1564 target_ulong ret;
3b46e624 1565
67867308 1566 for(;;) {
0315c31c 1567 cpu_exec_start(cs);
ea3e9847 1568 trapnr = cpu_ppc_exec(cs);
0315c31c 1569 cpu_exec_end(cs);
67867308 1570 switch(trapnr) {
e1833e1f
JM		 1571 case POWERPC_EXCP_NONE:
1572 /* Just go on */
67867308 1573 break;
e1833e1f 1574 case POWERPC_EXCP_CRITICAL: /* Critical input */
a47dddd7 1575 cpu_abort(cs, "Critical interrupt while in user mode. "
e1833e1f 1576 "Aborting\n");
61190b14 1577 break;
e1833e1f 1578 case POWERPC_EXCP_MCHECK: /* Machine check exception */
a47dddd7 1579 cpu_abort(cs, "Machine check exception while in user mode. "
e1833e1f
JM		 1580 "Aborting\n");
1581 break;
1582 case POWERPC_EXCP_DSI: /* Data storage exception */
90e189ec 1583 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
e1833e1f
JM		 1584 env->spr[SPR_DAR]);
1585 /* XXX: check this. Seems bugged */
2be0071f
FB		 1586 switch (env->error_code & 0xFF000000) {
1587 case 0x40000000:
61190b14
FB		 1588 info.si_signo = TARGET_SIGSEGV;
1589 info.si_errno = 0;
1590 info.si_code = TARGET_SEGV_MAPERR;
1591 break;
2be0071f 1592 case 0x04000000:
61190b14
FB		 1593 info.si_signo = TARGET_SIGILL;
1594 info.si_errno = 0;
1595 info.si_code = TARGET_ILL_ILLADR;
1596 break;
2be0071f 1597 case 0x08000000:
61190b14
FB		 1598 info.si_signo = TARGET_SIGSEGV;
1599 info.si_errno = 0;
1600 info.si_code = TARGET_SEGV_ACCERR;
1601 break;
61190b14
FB		 1602 default:
1603 /* Let's send a regular segfault... */
e1833e1f
JM		 1604 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1605 env->error_code);
61190b14
FB		 1606 info.si_signo = TARGET_SIGSEGV;
1607 info.si_errno = 0;
1608 info.si_code = TARGET_SEGV_MAPERR;
1609 break;
1610 }
67867308 1611 info._sifields._sigfault._addr = env->nip;
624f7979 1612 queue_signal(env, info.si_signo, &info);
67867308 1613 break;
e1833e1f 1614 case POWERPC_EXCP_ISI: /* Instruction storage exception */
90e189ec
BS		 1615 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1616 "\n", env->spr[SPR_SRR0]);
e1833e1f 1617 /* XXX: check this */
2be0071f
FB		 1618 switch (env->error_code & 0xFF000000) {
1619 case 0x40000000:
61190b14 1620 info.si_signo = TARGET_SIGSEGV;
67867308 1621 info.si_errno = 0;
61190b14
FB		 1622 info.si_code = TARGET_SEGV_MAPERR;
1623 break;
2be0071f
FB		 1624 case 0x10000000:
1625 case 0x08000000:
61190b14
FB		 1626 info.si_signo = TARGET_SIGSEGV;
1627 info.si_errno = 0;
1628 info.si_code = TARGET_SEGV_ACCERR;
1629 break;
1630 default:
1631 /* Let's send a regular segfault... */
e1833e1f
JM		 1632 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1633 env->error_code);
61190b14
FB		 1634 info.si_signo = TARGET_SIGSEGV;
1635 info.si_errno = 0;
1636 info.si_code = TARGET_SEGV_MAPERR;
1637 break;
1638 }
1639 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1640 queue_signal(env, info.si_signo, &info);
67867308 1641 break;
e1833e1f 1642 case POWERPC_EXCP_EXTERNAL: /* External input */
a47dddd7 1643 cpu_abort(cs, "External interrupt while in user mode. "
e1833e1f
JM		 1644 "Aborting\n");
1645 break;
1646 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1647 EXCP_DUMP(env, "Unaligned memory access\n");
1648 /* XXX: check this */
61190b14 1649 info.si_signo = TARGET_SIGBUS;
67867308 1650 info.si_errno = 0;
61190b14
FB		 1651 info.si_code = TARGET_BUS_ADRALN;
1652 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1653 queue_signal(env, info.si_signo, &info);
67867308 1654 break;
e1833e1f
JM		 1655 case POWERPC_EXCP_PROGRAM: /* Program exception */
1656 /* XXX: check this */
61190b14 1657 switch (env->error_code & ~0xF) {
e1833e1f
JM		 1658 case POWERPC_EXCP_FP:
1659 EXCP_DUMP(env, "Floating point program exception\n");
61190b14
FB		 1660 info.si_signo = TARGET_SIGFPE;
1661 info.si_errno = 0;
1662 switch (env->error_code & 0xF) {
e1833e1f 1663 case POWERPC_EXCP_FP_OX:
61190b14
FB		 1664 info.si_code = TARGET_FPE_FLTOVF;
1665 break;
e1833e1f 1666 case POWERPC_EXCP_FP_UX:
61190b14
FB		 1667 info.si_code = TARGET_FPE_FLTUND;
1668 break;
e1833e1f
JM		 1669 case POWERPC_EXCP_FP_ZX:
1670 case POWERPC_EXCP_FP_VXZDZ:
61190b14
FB		 1671 info.si_code = TARGET_FPE_FLTDIV;
1672 break;
e1833e1f 1673 case POWERPC_EXCP_FP_XX:
61190b14
FB		 1674 info.si_code = TARGET_FPE_FLTRES;
1675 break;
e1833e1f 1676 case POWERPC_EXCP_FP_VXSOFT:
61190b14
FB		 1677 info.si_code = TARGET_FPE_FLTINV;
1678 break;
7c58044c 1679 case POWERPC_EXCP_FP_VXSNAN:
e1833e1f
JM		 1680 case POWERPC_EXCP_FP_VXISI:
1681 case POWERPC_EXCP_FP_VXIDI:
1682 case POWERPC_EXCP_FP_VXIMZ:
1683 case POWERPC_EXCP_FP_VXVC:
1684 case POWERPC_EXCP_FP_VXSQRT:
1685 case POWERPC_EXCP_FP_VXCVI:
61190b14
FB		 1686 info.si_code = TARGET_FPE_FLTSUB;
1687 break;
1688 default:
e1833e1f
JM		 1689 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1690 env->error_code);
1691 break;
61190b14 1692 }
e1833e1f
JM		 1693 break;
1694 case POWERPC_EXCP_INVAL:
1695 EXCP_DUMP(env, "Invalid instruction\n");
61190b14
FB		 1696 info.si_signo = TARGET_SIGILL;
1697 info.si_errno = 0;
1698 switch (env->error_code & 0xF) {
e1833e1f 1699 case POWERPC_EXCP_INVAL_INVAL:
61190b14
FB		 1700 info.si_code = TARGET_ILL_ILLOPC;
1701 break;
e1833e1f 1702 case POWERPC_EXCP_INVAL_LSWX:
a750fc0b 1703 info.si_code = TARGET_ILL_ILLOPN;
61190b14 1704 break;
e1833e1f 1705 case POWERPC_EXCP_INVAL_SPR:
61190b14
FB		 1706 info.si_code = TARGET_ILL_PRVREG;
1707 break;
e1833e1f 1708 case POWERPC_EXCP_INVAL_FP:
61190b14
FB		 1709 info.si_code = TARGET_ILL_COPROC;
1710 break;
1711 default:
e1833e1f
JM		 1712 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1713 env->error_code & 0xF);
61190b14
FB		 1714 info.si_code = TARGET_ILL_ILLADR;
1715 break;
1716 }
1717 break;
e1833e1f
JM		 1718 case POWERPC_EXCP_PRIV:
1719 EXCP_DUMP(env, "Privilege violation\n");
61190b14
FB		 1720 info.si_signo = TARGET_SIGILL;
1721 info.si_errno = 0;
1722 switch (env->error_code & 0xF) {
e1833e1f 1723 case POWERPC_EXCP_PRIV_OPC:
61190b14
FB		 1724 info.si_code = TARGET_ILL_PRVOPC;
1725 break;
e1833e1f 1726 case POWERPC_EXCP_PRIV_REG:
61190b14 1727 info.si_code = TARGET_ILL_PRVREG;
e1833e1f 1728 break;
61190b14 1729 default:
e1833e1f
JM		 1730 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1731 env->error_code & 0xF);
61190b14
FB		 1732 info.si_code = TARGET_ILL_PRVOPC;
1733 break;
1734 }
1735 break;
e1833e1f 1736 case POWERPC_EXCP_TRAP:
a47dddd7 1737 cpu_abort(cs, "Tried to call a TRAP\n");
e1833e1f 1738 break;
61190b14
FB		 1739 default:
1740 /* Should not happen ! */
a47dddd7 1741 cpu_abort(cs, "Unknown program exception (%02x)\n",
e1833e1f
JM		 1742 env->error_code);
1743 break;
61190b14
FB		 1744 }
1745 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1746 queue_signal(env, info.si_signo, &info);
67867308 1747 break;
e1833e1f
JM		 1748 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1749 EXCP_DUMP(env, "No floating point allowed\n");
61190b14 1750 info.si_signo = TARGET_SIGILL;
67867308 1751 info.si_errno = 0;
61190b14
FB		 1752 info.si_code = TARGET_ILL_COPROC;
1753 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1754 queue_signal(env, info.si_signo, &info);
67867308 1755 break;
e1833e1f 1756 case POWERPC_EXCP_SYSCALL: /* System call exception */
a47dddd7 1757 cpu_abort(cs, "Syscall exception while in user mode. "
e1833e1f 1758 "Aborting\n");
61190b14 1759 break;
e1833e1f
JM		 1760 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1761 EXCP_DUMP(env, "No APU instruction allowed\n");
1762 info.si_signo = TARGET_SIGILL;
1763 info.si_errno = 0;
1764 info.si_code = TARGET_ILL_COPROC;
1765 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1766 queue_signal(env, info.si_signo, &info);
61190b14 1767 break;
e1833e1f 1768 case POWERPC_EXCP_DECR: /* Decrementer exception */
a47dddd7 1769 cpu_abort(cs, "Decrementer interrupt while in user mode. "
e1833e1f 1770 "Aborting\n");
61190b14 1771 break;
e1833e1f 1772 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
a47dddd7 1773 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
e1833e1f
JM		 1774 "Aborting\n");
1775 break;
1776 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
a47dddd7 1777 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
e1833e1f
JM		 1778 "Aborting\n");
1779 break;
1780 case POWERPC_EXCP_DTLB: /* Data TLB error */
a47dddd7 1781 cpu_abort(cs, "Data TLB exception while in user mode. "
e1833e1f
JM		 1782 "Aborting\n");
1783 break;
1784 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
a47dddd7 1785 cpu_abort(cs, "Instruction TLB exception while in user mode. "
e1833e1f
JM		 1786 "Aborting\n");
1787 break;
e1833e1f
JM		 1788 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1789 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1790 info.si_signo = TARGET_SIGILL;
1791 info.si_errno = 0;
1792 info.si_code = TARGET_ILL_COPROC;
1793 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1794 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1795 break;
1796 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
a47dddd7 1797 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
e1833e1f
JM		 1798 break;
1799 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
a47dddd7 1800 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
e1833e1f
JM		 1801 break;
1802 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
a47dddd7 1803 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1804 break;
1805 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
a47dddd7 1806 cpu_abort(cs, "Doorbell interrupt while in user mode. "
e1833e1f
JM		 1807 "Aborting\n");
1808 break;
1809 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
a47dddd7 1810 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
e1833e1f
JM		 1811 "Aborting\n");
1812 break;
1813 case POWERPC_EXCP_RESET: /* System reset exception */
a47dddd7 1814 cpu_abort(cs, "Reset interrupt while in user mode. "
e1833e1f
JM		 1815 "Aborting\n");
1816 break;
e1833e1f 1817 case POWERPC_EXCP_DSEG: /* Data segment exception */
a47dddd7 1818 cpu_abort(cs, "Data segment exception while in user mode. "
e1833e1f
JM		 1819 "Aborting\n");
1820 break;
1821 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
a47dddd7 1822 cpu_abort(cs, "Instruction segment exception "
e1833e1f
JM		 1823 "while in user mode. Aborting\n");
1824 break;
e85e7c6e 1825 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1826 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
a47dddd7 1827 cpu_abort(cs, "Hypervisor decrementer interrupt "
e1833e1f
JM		 1828 "while in user mode. Aborting\n");
1829 break;
e1833e1f
JM		 1830 case POWERPC_EXCP_TRACE: /* Trace exception */
1831 /* Nothing to do:
1832 * we use this exception to emulate step-by-step execution mode.
1833 */
1834 break;
e85e7c6e 1835 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1836 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
a47dddd7 1837 cpu_abort(cs, "Hypervisor data storage exception "
e1833e1f
JM		 1838 "while in user mode. Aborting\n");
1839 break;
1840 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
a47dddd7 1841 cpu_abort(cs, "Hypervisor instruction storage exception "
e1833e1f
JM		 1842 "while in user mode. Aborting\n");
1843 break;
1844 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
a47dddd7 1845 cpu_abort(cs, "Hypervisor data segment exception "
e1833e1f
JM		 1846 "while in user mode. Aborting\n");
1847 break;
1848 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
a47dddd7 1849 cpu_abort(cs, "Hypervisor instruction segment exception "
e1833e1f
JM		 1850 "while in user mode. Aborting\n");
1851 break;
e1833e1f
JM		 1852 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1853 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1854 info.si_signo = TARGET_SIGILL;
1855 info.si_errno = 0;
1856 info.si_code = TARGET_ILL_COPROC;
1857 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1858 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1859 break;
1860 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
a47dddd7 1861 cpu_abort(cs, "Programmable interval timer interrupt "
e1833e1f
JM		 1862 "while in user mode. Aborting\n");
1863 break;
1864 case POWERPC_EXCP_IO: /* IO error exception */
a47dddd7 1865 cpu_abort(cs, "IO error exception while in user mode. "
e1833e1f
JM		 1866 "Aborting\n");
1867 break;
1868 case POWERPC_EXCP_RUNM: /* Run mode exception */
a47dddd7 1869 cpu_abort(cs, "Run mode exception while in user mode. "
e1833e1f
JM		 1870 "Aborting\n");
1871 break;
1872 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
a47dddd7 1873 cpu_abort(cs, "Emulation trap exception not handled\n");
e1833e1f
JM		 1874 break;
1875 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
a47dddd7 1876 cpu_abort(cs, "Instruction fetch TLB exception "
e1833e1f
JM		 1877 "while in user-mode. Aborting");
1878 break;
1879 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
a47dddd7 1880 cpu_abort(cs, "Data load TLB exception while in user-mode. "
e1833e1f
JM		 1881 "Aborting");
1882 break;
1883 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
a47dddd7 1884 cpu_abort(cs, "Data store TLB exception while in user-mode. "
e1833e1f
JM		 1885 "Aborting");
1886 break;
1887 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
a47dddd7 1888 cpu_abort(cs, "Floating-point assist exception not handled\n");
e1833e1f
JM		 1889 break;
1890 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
a47dddd7 1891 cpu_abort(cs, "Instruction address breakpoint exception "
e1833e1f
JM		 1892 "not handled\n");
1893 break;
1894 case POWERPC_EXCP_SMI: /* System management interrupt */
a47dddd7 1895 cpu_abort(cs, "System management interrupt while in user mode. "
e1833e1f
JM		 1896 "Aborting\n");
1897 break;
1898 case POWERPC_EXCP_THERM: /* Thermal interrupt */
a47dddd7 1899 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
e1833e1f
JM		 1900 "Aborting\n");
1901 break;
1902 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
a47dddd7 1903 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1904 break;
1905 case POWERPC_EXCP_VPUA: /* Vector assist exception */
a47dddd7 1906 cpu_abort(cs, "Vector assist exception not handled\n");
e1833e1f
JM		 1907 break;
1908 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
a47dddd7 1909 cpu_abort(cs, "Soft patch exception not handled\n");
e1833e1f
JM		 1910 break;
1911 case POWERPC_EXCP_MAINT: /* Maintenance exception */
a47dddd7 1912 cpu_abort(cs, "Maintenance exception while in user mode. "
e1833e1f
JM		 1913 "Aborting\n");
1914 break;
1915 case POWERPC_EXCP_STOP: /* stop translation */
1916 /* We did invalidate the instruction cache. Go on */
1917 break;
1918 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1919 /* We just stopped because of a branch. Go on */
1920 break;
1921 case POWERPC_EXCP_SYSCALL_USER:
1922 /* system call in user-mode emulation */
1923 /* WARNING:
1924 * PPC ABI uses overflow flag in cr0 to signal an error
1925 * in syscalls.
1926 */
e1833e1f
JM		 1927 env->crf[0] &= ~0x1;
1928 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1929 env->gpr[5], env->gpr[6], env->gpr[7],
5945cfcb 1930 env->gpr[8], 0, 0);
9e0e2f96 1931 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
bcd4933a
NF		 1932 /* Returning from a successful sigreturn syscall.
1933 Avoid corrupting register state. */
1934 break;
1935 }
9e0e2f96 1936 if (ret > (target_ulong)(-515)) {
e1833e1f
JM		 1937 env->crf[0] |= 0x1;
1938 ret = -ret;
61190b14 1939 }
e1833e1f 1940 env->gpr[3] = ret;
e1833e1f 1941 break;
56f066bb
NF		 1942 case POWERPC_EXCP_STCX:
1943 if (do_store_exclusive(env)) {
1944 info.si_signo = TARGET_SIGSEGV;
1945 info.si_errno = 0;
1946 info.si_code = TARGET_SEGV_MAPERR;
1947 info._sifields._sigfault._addr = env->nip;
1948 queue_signal(env, info.si_signo, &info);
1949 }
1950 break;
71f75756
AJ		 1951 case EXCP_DEBUG:
1952 {
1953 int sig;
1954
db6b81d4 1955 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
71f75756
AJ		 1956 if (sig) {
1957 info.si_signo = sig;
1958 info.si_errno = 0;
1959 info.si_code = TARGET_TRAP_BRKPT;
1960 queue_signal(env, info.si_signo, &info);
1961 }
1962 }
1963 break;
56ba31ff
JM		 1964 case EXCP_INTERRUPT:
1965 /* just indicate that signals should be handled asap */
1966 break;
e1833e1f 1967 default:
a47dddd7 1968 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
e1833e1f 1969 break;
67867308
FB		 1970 }
1971 process_pending_signals(env);
1972 }
1973}
1974#endif
1975
048f6b4d
FB		 1976#ifdef TARGET_MIPS
1977
ff4f7382
RH		 1978# ifdef TARGET_ABI_MIPSO32
1979# define MIPS_SYS(name, args) args,
048f6b4d 1980static const uint8_t mips_syscall_args[] = {
29fb0f25 1981 MIPS_SYS(sys_syscall , 8) /* 4000 */
048f6b4d
FB		 1982 MIPS_SYS(sys_exit , 1)
1983 MIPS_SYS(sys_fork , 0)
1984 MIPS_SYS(sys_read , 3)
1985 MIPS_SYS(sys_write , 3)
1986 MIPS_SYS(sys_open , 3) /* 4005 */
1987 MIPS_SYS(sys_close , 1)
1988 MIPS_SYS(sys_waitpid , 3)
1989 MIPS_SYS(sys_creat , 2)
1990 MIPS_SYS(sys_link , 2)
1991 MIPS_SYS(sys_unlink , 1) /* 4010 */
1992 MIPS_SYS(sys_execve , 0)
1993 MIPS_SYS(sys_chdir , 1)
1994 MIPS_SYS(sys_time , 1)
1995 MIPS_SYS(sys_mknod , 3)
1996 MIPS_SYS(sys_chmod , 2) /* 4015 */
1997 MIPS_SYS(sys_lchown , 3)
1998 MIPS_SYS(sys_ni_syscall , 0)
1999 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2000 MIPS_SYS(sys_lseek , 3)
2001 MIPS_SYS(sys_getpid , 0) /* 4020 */
2002 MIPS_SYS(sys_mount , 5)
868e34d7 2003 MIPS_SYS(sys_umount , 1)
048f6b4d
FB		 2004 MIPS_SYS(sys_setuid , 1)
2005 MIPS_SYS(sys_getuid , 0)
2006 MIPS_SYS(sys_stime , 1) /* 4025 */
2007 MIPS_SYS(sys_ptrace , 4)
2008 MIPS_SYS(sys_alarm , 1)
2009 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2010 MIPS_SYS(sys_pause , 0)
2011 MIPS_SYS(sys_utime , 2) /* 4030 */
2012 MIPS_SYS(sys_ni_syscall , 0)
2013 MIPS_SYS(sys_ni_syscall , 0)
2014 MIPS_SYS(sys_access , 2)
2015 MIPS_SYS(sys_nice , 1)
2016 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2017 MIPS_SYS(sys_sync , 0)
2018 MIPS_SYS(sys_kill , 2)
2019 MIPS_SYS(sys_rename , 2)
2020 MIPS_SYS(sys_mkdir , 2)
2021 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2022 MIPS_SYS(sys_dup , 1)
2023 MIPS_SYS(sys_pipe , 0)
2024 MIPS_SYS(sys_times , 1)
2025 MIPS_SYS(sys_ni_syscall , 0)
2026 MIPS_SYS(sys_brk , 1) /* 4045 */
2027 MIPS_SYS(sys_setgid , 1)
2028 MIPS_SYS(sys_getgid , 0)
2029 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2030 MIPS_SYS(sys_geteuid , 0)
2031 MIPS_SYS(sys_getegid , 0) /* 4050 */
2032 MIPS_SYS(sys_acct , 0)
868e34d7 2033 MIPS_SYS(sys_umount2 , 2)
048f6b4d
FB		 2034 MIPS_SYS(sys_ni_syscall , 0)
2035 MIPS_SYS(sys_ioctl , 3)
2036 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2037 MIPS_SYS(sys_ni_syscall , 2)
2038 MIPS_SYS(sys_setpgid , 2)
2039 MIPS_SYS(sys_ni_syscall , 0)
2040 MIPS_SYS(sys_olduname , 1)
2041 MIPS_SYS(sys_umask , 1) /* 4060 */
2042 MIPS_SYS(sys_chroot , 1)
2043 MIPS_SYS(sys_ustat , 2)
2044 MIPS_SYS(sys_dup2 , 2)
2045 MIPS_SYS(sys_getppid , 0)
2046 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2047 MIPS_SYS(sys_setsid , 0)
2048 MIPS_SYS(sys_sigaction , 3)
2049 MIPS_SYS(sys_sgetmask , 0)
2050 MIPS_SYS(sys_ssetmask , 1)
2051 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2052 MIPS_SYS(sys_setregid , 2)
2053 MIPS_SYS(sys_sigsuspend , 0)
2054 MIPS_SYS(sys_sigpending , 1)
2055 MIPS_SYS(sys_sethostname , 2)
2056 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2057 MIPS_SYS(sys_getrlimit , 2)
2058 MIPS_SYS(sys_getrusage , 2)
2059 MIPS_SYS(sys_gettimeofday, 2)
2060 MIPS_SYS(sys_settimeofday, 2)
2061 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2062 MIPS_SYS(sys_setgroups , 2)
2063 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2064 MIPS_SYS(sys_symlink , 2)
2065 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2066 MIPS_SYS(sys_readlink , 3) /* 4085 */
2067 MIPS_SYS(sys_uselib , 1)
2068 MIPS_SYS(sys_swapon , 2)
2069 MIPS_SYS(sys_reboot , 3)
2070 MIPS_SYS(old_readdir , 3)
2071 MIPS_SYS(old_mmap , 6) /* 4090 */
2072 MIPS_SYS(sys_munmap , 2)
2073 MIPS_SYS(sys_truncate , 2)
2074 MIPS_SYS(sys_ftruncate , 2)
2075 MIPS_SYS(sys_fchmod , 2)
2076 MIPS_SYS(sys_fchown , 3) /* 4095 */
2077 MIPS_SYS(sys_getpriority , 2)
2078 MIPS_SYS(sys_setpriority , 3)
2079 MIPS_SYS(sys_ni_syscall , 0)
2080 MIPS_SYS(sys_statfs , 2)
2081 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2082 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2083 MIPS_SYS(sys_socketcall , 2)
2084 MIPS_SYS(sys_syslog , 3)
2085 MIPS_SYS(sys_setitimer , 3)
2086 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2087 MIPS_SYS(sys_newstat , 2)
2088 MIPS_SYS(sys_newlstat , 2)
2089 MIPS_SYS(sys_newfstat , 2)
2090 MIPS_SYS(sys_uname , 1)
2091 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2092 MIPS_SYS(sys_vhangup , 0)
2093 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2094 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2095 MIPS_SYS(sys_wait4 , 4)
2096 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2097 MIPS_SYS(sys_sysinfo , 1)
2098 MIPS_SYS(sys_ipc , 6)
2099 MIPS_SYS(sys_fsync , 1)
2100 MIPS_SYS(sys_sigreturn , 0)
18113962 2101 MIPS_SYS(sys_clone , 6) /* 4120 */
048f6b4d
FB		 2102 MIPS_SYS(sys_setdomainname, 2)
2103 MIPS_SYS(sys_newuname , 1)
2104 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2105 MIPS_SYS(sys_adjtimex , 1)
2106 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2107 MIPS_SYS(sys_sigprocmask , 3)
2108 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2109 MIPS_SYS(sys_init_module , 5)
2110 MIPS_SYS(sys_delete_module, 1)
2111 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2112 MIPS_SYS(sys_quotactl , 0)
2113 MIPS_SYS(sys_getpgid , 1)
2114 MIPS_SYS(sys_fchdir , 1)
2115 MIPS_SYS(sys_bdflush , 2)
2116 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2117 MIPS_SYS(sys_personality , 1)
2118 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2119 MIPS_SYS(sys_setfsuid , 1)
2120 MIPS_SYS(sys_setfsgid , 1)
2121 MIPS_SYS(sys_llseek , 5) /* 4140 */
2122 MIPS_SYS(sys_getdents , 3)
2123 MIPS_SYS(sys_select , 5)
2124 MIPS_SYS(sys_flock , 2)
2125 MIPS_SYS(sys_msync , 3)
2126 MIPS_SYS(sys_readv , 3) /* 4145 */
2127 MIPS_SYS(sys_writev , 3)
2128 MIPS_SYS(sys_cacheflush , 3)
2129 MIPS_SYS(sys_cachectl , 3)
2130 MIPS_SYS(sys_sysmips , 4)
2131 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2132 MIPS_SYS(sys_getsid , 1)
2133 MIPS_SYS(sys_fdatasync , 0)
2134 MIPS_SYS(sys_sysctl , 1)
2135 MIPS_SYS(sys_mlock , 2)
2136 MIPS_SYS(sys_munlock , 2) /* 4155 */
2137 MIPS_SYS(sys_mlockall , 1)
2138 MIPS_SYS(sys_munlockall , 0)
2139 MIPS_SYS(sys_sched_setparam, 2)
2140 MIPS_SYS(sys_sched_getparam, 2)
2141 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2142 MIPS_SYS(sys_sched_getscheduler, 1)
2143 MIPS_SYS(sys_sched_yield , 0)
2144 MIPS_SYS(sys_sched_get_priority_max, 1)
2145 MIPS_SYS(sys_sched_get_priority_min, 1)
2146 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2147 MIPS_SYS(sys_nanosleep, 2)
b0932e06 2148 MIPS_SYS(sys_mremap , 5)
048f6b4d
FB		 2149 MIPS_SYS(sys_accept , 3)
2150 MIPS_SYS(sys_bind , 3)
2151 MIPS_SYS(sys_connect , 3) /* 4170 */
2152 MIPS_SYS(sys_getpeername , 3)
2153 MIPS_SYS(sys_getsockname , 3)
2154 MIPS_SYS(sys_getsockopt , 5)
2155 MIPS_SYS(sys_listen , 2)
2156 MIPS_SYS(sys_recv , 4) /* 4175 */
2157 MIPS_SYS(sys_recvfrom , 6)
2158 MIPS_SYS(sys_recvmsg , 3)
2159 MIPS_SYS(sys_send , 4)
2160 MIPS_SYS(sys_sendmsg , 3)
2161 MIPS_SYS(sys_sendto , 6) /* 4180 */
2162 MIPS_SYS(sys_setsockopt , 5)
2163 MIPS_SYS(sys_shutdown , 2)
2164 MIPS_SYS(sys_socket , 3)
2165 MIPS_SYS(sys_socketpair , 4)
2166 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2167 MIPS_SYS(sys_getresuid , 3)
2168 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2169 MIPS_SYS(sys_poll , 3)
2170 MIPS_SYS(sys_nfsservctl , 3)
2171 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2172 MIPS_SYS(sys_getresgid , 3)
2173 MIPS_SYS(sys_prctl , 5)
2174 MIPS_SYS(sys_rt_sigreturn, 0)
2175 MIPS_SYS(sys_rt_sigaction, 4)
2176 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2177 MIPS_SYS(sys_rt_sigpending, 2)
2178 MIPS_SYS(sys_rt_sigtimedwait, 4)
2179 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2180 MIPS_SYS(sys_rt_sigsuspend, 0)
2181 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2182 MIPS_SYS(sys_pwrite64 , 6)
2183 MIPS_SYS(sys_chown , 3)
2184 MIPS_SYS(sys_getcwd , 2)
2185 MIPS_SYS(sys_capget , 2)
2186 MIPS_SYS(sys_capset , 2) /* 4205 */
053ebb27 2187 MIPS_SYS(sys_sigaltstack , 2)
048f6b4d
FB		 2188 MIPS_SYS(sys_sendfile , 4)
2189 MIPS_SYS(sys_ni_syscall , 0)
2190 MIPS_SYS(sys_ni_syscall , 0)
2191 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2192 MIPS_SYS(sys_truncate64 , 4)
2193 MIPS_SYS(sys_ftruncate64 , 4)
2194 MIPS_SYS(sys_stat64 , 2)
2195 MIPS_SYS(sys_lstat64 , 2)
2196 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2197 MIPS_SYS(sys_pivot_root , 2)
2198 MIPS_SYS(sys_mincore , 3)
2199 MIPS_SYS(sys_madvise , 3)
2200 MIPS_SYS(sys_getdents64 , 3)
2201 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2202 MIPS_SYS(sys_ni_syscall , 0)
2203 MIPS_SYS(sys_gettid , 0)
2204 MIPS_SYS(sys_readahead , 5)
2205 MIPS_SYS(sys_setxattr , 5)
2206 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2207 MIPS_SYS(sys_fsetxattr , 5)
2208 MIPS_SYS(sys_getxattr , 4)
2209 MIPS_SYS(sys_lgetxattr , 4)
2210 MIPS_SYS(sys_fgetxattr , 4)
2211 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2212 MIPS_SYS(sys_llistxattr , 3)
2213 MIPS_SYS(sys_flistxattr , 3)
2214 MIPS_SYS(sys_removexattr , 2)
2215 MIPS_SYS(sys_lremovexattr, 2)
2216 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2217 MIPS_SYS(sys_tkill , 2)
2218 MIPS_SYS(sys_sendfile64 , 5)
43be1343 2219 MIPS_SYS(sys_futex , 6)
048f6b4d
FB		 2220 MIPS_SYS(sys_sched_setaffinity, 3)
2221 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2222 MIPS_SYS(sys_io_setup , 2)
2223 MIPS_SYS(sys_io_destroy , 1)
2224 MIPS_SYS(sys_io_getevents, 5)
2225 MIPS_SYS(sys_io_submit , 3)
2226 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2227 MIPS_SYS(sys_exit_group , 1)
2228 MIPS_SYS(sys_lookup_dcookie, 3)
2229 MIPS_SYS(sys_epoll_create, 1)
2230 MIPS_SYS(sys_epoll_ctl , 4)
2231 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2232 MIPS_SYS(sys_remap_file_pages, 5)
2233 MIPS_SYS(sys_set_tid_address, 1)
2234 MIPS_SYS(sys_restart_syscall, 0)
2235 MIPS_SYS(sys_fadvise64_64, 7)
2236 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2237 MIPS_SYS(sys_fstatfs64 , 2)
2238 MIPS_SYS(sys_timer_create, 3)
2239 MIPS_SYS(sys_timer_settime, 4)
2240 MIPS_SYS(sys_timer_gettime, 2)
2241 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2242 MIPS_SYS(sys_timer_delete, 1)
2243 MIPS_SYS(sys_clock_settime, 2)
2244 MIPS_SYS(sys_clock_gettime, 2)
2245 MIPS_SYS(sys_clock_getres, 2)
2246 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2247 MIPS_SYS(sys_tgkill , 3)
2248 MIPS_SYS(sys_utimes , 2)
2249 MIPS_SYS(sys_mbind , 4)
2250 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2251 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2252 MIPS_SYS(sys_mq_open , 4)
2253 MIPS_SYS(sys_mq_unlink , 1)
2254 MIPS_SYS(sys_mq_timedsend, 5)
2255 MIPS_SYS(sys_mq_timedreceive, 5)
2256 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2257 MIPS_SYS(sys_mq_getsetattr, 3)
2258 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2259 MIPS_SYS(sys_waitid , 4)
2260 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2261 MIPS_SYS(sys_add_key , 5)
388bb21a 2262 MIPS_SYS(sys_request_key, 4)
048f6b4d 2263 MIPS_SYS(sys_keyctl , 5)
6f5b89a0 2264 MIPS_SYS(sys_set_thread_area, 1)
388bb21a
TS		 2265 MIPS_SYS(sys_inotify_init, 0)
2266 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2267 MIPS_SYS(sys_inotify_rm_watch, 2)
2268 MIPS_SYS(sys_migrate_pages, 4)
2269 MIPS_SYS(sys_openat, 4)
2270 MIPS_SYS(sys_mkdirat, 3)
2271 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2272 MIPS_SYS(sys_fchownat, 5)
2273 MIPS_SYS(sys_futimesat, 3)
2274 MIPS_SYS(sys_fstatat64, 4)
2275 MIPS_SYS(sys_unlinkat, 3)
2276 MIPS_SYS(sys_renameat, 4) /* 4295 */
2277 MIPS_SYS(sys_linkat, 5)
2278 MIPS_SYS(sys_symlinkat, 3)
2279 MIPS_SYS(sys_readlinkat, 4)
2280 MIPS_SYS(sys_fchmodat, 3)
2281 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2282 MIPS_SYS(sys_pselect6, 6)
2283 MIPS_SYS(sys_ppoll, 5)
2284 MIPS_SYS(sys_unshare, 1)
b0932e06 2285 MIPS_SYS(sys_splice, 6)
388bb21a
TS		 2286 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2287 MIPS_SYS(sys_tee, 4)
2288 MIPS_SYS(sys_vmsplice, 4)
2289 MIPS_SYS(sys_move_pages, 6)
2290 MIPS_SYS(sys_set_robust_list, 2)
2291 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2292 MIPS_SYS(sys_kexec_load, 4)
2293 MIPS_SYS(sys_getcpu, 3)
2294 MIPS_SYS(sys_epoll_pwait, 6)
2295 MIPS_SYS(sys_ioprio_set, 3)
2296 MIPS_SYS(sys_ioprio_get, 2)
d979e8eb
PM		 2297 MIPS_SYS(sys_utimensat, 4)
2298 MIPS_SYS(sys_signalfd, 3)
2299 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2300 MIPS_SYS(sys_eventfd, 1)
2301 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2302 MIPS_SYS(sys_timerfd_create, 2)
2303 MIPS_SYS(sys_timerfd_gettime, 2)
2304 MIPS_SYS(sys_timerfd_settime, 4)
2305 MIPS_SYS(sys_signalfd4, 4)
2306 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2307 MIPS_SYS(sys_epoll_create1, 1)
2308 MIPS_SYS(sys_dup3, 3)
2309 MIPS_SYS(sys_pipe2, 2)
2310 MIPS_SYS(sys_inotify_init1, 1)
2311 MIPS_SYS(sys_preadv, 6) /* 4330 */
2312 MIPS_SYS(sys_pwritev, 6)
2313 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2314 MIPS_SYS(sys_perf_event_open, 5)
2315 MIPS_SYS(sys_accept4, 4)
2316 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2317 MIPS_SYS(sys_fanotify_init, 2)
2318 MIPS_SYS(sys_fanotify_mark, 6)
2319 MIPS_SYS(sys_prlimit64, 4)
2320 MIPS_SYS(sys_name_to_handle_at, 5)
2321 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2322 MIPS_SYS(sys_clock_adjtime, 2)
2323 MIPS_SYS(sys_syncfs, 1)
048f6b4d 2324};
ff4f7382
RH		 2325# undef MIPS_SYS
2326# endif /* O32 */
048f6b4d 2327
590bc601
PB		 2328static int do_store_exclusive(CPUMIPSState *env)
2329{
2330 target_ulong addr;
2331 target_ulong page_addr;
2332 target_ulong val;
2333 int flags;
2334 int segv = 0;
2335 int reg;
2336 int d;
2337
5499b6ff 2338 addr = env->lladdr;
590bc601
PB		 2339 page_addr = addr & TARGET_PAGE_MASK;
2340 start_exclusive();
2341 mmap_lock();
2342 flags = page_get_flags(page_addr);
2343 if ((flags & PAGE_READ) == 0) {
2344 segv = 1;
2345 } else {
2346 reg = env->llreg & 0x1f;
2347 d = (env->llreg & 0x20) != 0;
2348 if (d) {
2349 segv = get_user_s64(val, addr);
2350 } else {
2351 segv = get_user_s32(val, addr);
2352 }
2353 if (!segv) {
2354 if (val != env->llval) {
2355 env->active_tc.gpr[reg] = 0;
2356 } else {
2357 if (d) {
2358 segv = put_user_u64(env->llnewval, addr);
2359 } else {
2360 segv = put_user_u32(env->llnewval, addr);
2361 }
2362 if (!segv) {
2363 env->active_tc.gpr[reg] = 1;
2364 }
2365 }
2366 }
2367 }
5499b6ff 2368 env->lladdr = -1;
590bc601
PB		 2369 if (!segv) {
2370 env->active_tc.PC += 4;
2371 }
2372 mmap_unlock();
2373 end_exclusive();
2374 return segv;
2375}
2376
54b2f42c
MI		 2377/* Break codes */
2378enum {
2379 BRK_OVERFLOW = 6,
2380 BRK_DIVZERO = 7
2381};
2382
2383static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2384 unsigned int code)
2385{
2386 int ret = -1;
2387
2388 switch (code) {
2389 case BRK_OVERFLOW:
2390 case BRK_DIVZERO:
2391 info->si_signo = TARGET_SIGFPE;
2392 info->si_errno = 0;
2393 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2394 queue_signal(env, info->si_signo, &*info);
2395 ret = 0;
2396 break;
2397 default:
b51910ba
PJ		 2398 info->si_signo = TARGET_SIGTRAP;
2399 info->si_errno = 0;
2400 queue_signal(env, info->si_signo, &*info);
2401 ret = 0;
54b2f42c
MI		 2402 break;
2403 }
2404
2405 return ret;
2406}
2407
048f6b4d
FB		 2408void cpu_loop(CPUMIPSState *env)
2409{
0315c31c 2410 CPUState *cs = CPU(mips_env_get_cpu(env));
c227f099 2411 target_siginfo_t info;
ff4f7382
RH		 2412 int trapnr;
2413 abi_long ret;
2414# ifdef TARGET_ABI_MIPSO32
048f6b4d 2415 unsigned int syscall_num;
ff4f7382 2416# endif
048f6b4d
FB		 2417
2418 for(;;) {
0315c31c 2419 cpu_exec_start(cs);
ea3e9847 2420 trapnr = cpu_mips_exec(cs);
0315c31c 2421 cpu_exec_end(cs);
048f6b4d
FB		 2422 switch(trapnr) {
2423 case EXCP_SYSCALL:
b5dc7732 2424 env->active_tc.PC += 4;
ff4f7382
RH		 2425# ifdef TARGET_ABI_MIPSO32
2426 syscall_num = env->active_tc.gpr[2] - 4000;
388bb21a 2427 if (syscall_num >= sizeof(mips_syscall_args)) {
7c2f6157 2428 ret = -TARGET_ENOSYS;
388bb21a
TS		 2429 } else {
2430 int nb_args;
992f48a0
BS		 2431 abi_ulong sp_reg;
2432 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
388bb21a
TS		 2433
2434 nb_args = mips_syscall_args[syscall_num];
b5dc7732 2435 sp_reg = env->active_tc.gpr[29];
388bb21a
TS		 2436 switch (nb_args) {
2437 /* these arguments are taken from the stack */
94c19610
ACH		 2438 case 8:
2439 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2440 goto done_syscall;
2441 }
2442 case 7:
2443 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2444 goto done_syscall;
2445 }
2446 case 6:
2447 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2448 goto done_syscall;
2449 }
2450 case 5:
2451 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2452 goto done_syscall;
2453 }
388bb21a
TS		 2454 default:
2455 break;
048f6b4d 2456 }
b5dc7732
TS		 2457 ret = do_syscall(env, env->active_tc.gpr[2],
2458 env->active_tc.gpr[4],
2459 env->active_tc.gpr[5],
2460 env->active_tc.gpr[6],
2461 env->active_tc.gpr[7],
5945cfcb 2462 arg5, arg6, arg7, arg8);
388bb21a 2463 }
94c19610 2464done_syscall:
ff4f7382
RH		 2465# else
2466 ret = do_syscall(env, env->active_tc.gpr[2],
2467 env->active_tc.gpr[4], env->active_tc.gpr[5],
2468 env->active_tc.gpr[6], env->active_tc.gpr[7],
2469 env->active_tc.gpr[8], env->active_tc.gpr[9],
2470 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2471# endif /* O32 */
0b1bcb00
PB		 2472 if (ret == -TARGET_QEMU_ESIGRETURN) {
2473 /* Returning from a successful sigreturn syscall.
2474 Avoid clobbering register state. */
2475 break;
2476 }
ff4f7382 2477 if ((abi_ulong)ret >= (abi_ulong)-1133) {
b5dc7732 2478 env->active_tc.gpr[7] = 1; /* error flag */
388bb21a
TS		 2479 ret = -ret;
2480 } else {
b5dc7732 2481 env->active_tc.gpr[7] = 0; /* error flag */
048f6b4d 2482 }
b5dc7732 2483 env->active_tc.gpr[2] = ret;
048f6b4d 2484 break;
ca7c2b1b
TS		 2485 case EXCP_TLBL:
2486 case EXCP_TLBS:
e6e5bd2d
WT		 2487 case EXCP_AdEL:
2488 case EXCP_AdES:
e4474235
PB		 2489 info.si_signo = TARGET_SIGSEGV;
2490 info.si_errno = 0;
2491 /* XXX: check env->error_code */
2492 info.si_code = TARGET_SEGV_MAPERR;
2493 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2494 queue_signal(env, info.si_signo, &info);
2495 break;
6900e84b 2496 case EXCP_CpU:
048f6b4d 2497 case EXCP_RI:
bc1ad2de
FB		 2498 info.si_signo = TARGET_SIGILL;
2499 info.si_errno = 0;
2500 info.si_code = 0;
624f7979 2501 queue_signal(env, info.si_signo, &info);
048f6b4d 2502 break;
106ec879
FB		 2503 case EXCP_INTERRUPT:
2504 /* just indicate that signals should be handled asap */
2505 break;
d08b2a28
PB		 2506 case EXCP_DEBUG:
2507 {
2508 int sig;
2509
db6b81d4 2510 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d08b2a28
PB		 2511 if (sig)
2512 {
2513 info.si_signo = sig;
2514 info.si_errno = 0;
2515 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2516 queue_signal(env, info.si_signo, &info);
d08b2a28
PB		 2517 }
2518 }
2519 break;
590bc601
PB		 2520 case EXCP_SC:
2521 if (do_store_exclusive(env)) {
2522 info.si_signo = TARGET_SIGSEGV;
2523 info.si_errno = 0;
2524 info.si_code = TARGET_SEGV_MAPERR;
2525 info._sifields._sigfault._addr = env->active_tc.PC;
2526 queue_signal(env, info.si_signo, &info);
2527 }
2528 break;
853c3240
JL		 2529 case EXCP_DSPDIS:
2530 info.si_signo = TARGET_SIGILL;
2531 info.si_errno = 0;
2532 info.si_code = TARGET_ILL_ILLOPC;
2533 queue_signal(env, info.si_signo, &info);
2534 break;
54b2f42c
MI		 2535 /* The code below was inspired by the MIPS Linux kernel trap
2536 * handling code in arch/mips/kernel/traps.c.
2537 */
2538 case EXCP_BREAK:
2539 {
2540 abi_ulong trap_instr;
2541 unsigned int code;
2542
a0333817
KCY		 2543 if (env->hflags & MIPS_HFLAG_M16) {
2544 if (env->insn_flags & ASE_MICROMIPS) {
2545 /* microMIPS mode */
1308c464
KCY		 2546 ret = get_user_u16(trap_instr, env->active_tc.PC);
2547 if (ret != 0) {
2548 goto error;
2549 }
a0333817 2550
1308c464
KCY		 2551 if ((trap_instr >> 10) == 0x11) {
2552 /* 16-bit instruction */
2553 code = trap_instr & 0xf;
2554 } else {
2555 /* 32-bit instruction */
2556 abi_ulong instr_lo;
2557
2558 ret = get_user_u16(instr_lo,
2559 env->active_tc.PC + 2);
2560 if (ret != 0) {
2561 goto error;
2562 }
2563 trap_instr = (trap_instr << 16) | instr_lo;
2564 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2565 /* Unfortunately, microMIPS also suffers from
2566 the old assembler bug... */
2567 if (code >= (1 << 10)) {
2568 code >>= 10;
2569 }
2570 }
a0333817
KCY		 2571 } else {
2572 /* MIPS16e mode */
2573 ret = get_user_u16(trap_instr, env->active_tc.PC);
2574 if (ret != 0) {
2575 goto error;
2576 }
2577 code = (trap_instr >> 6) & 0x3f;
a0333817
KCY		 2578 }
2579 } else {
2580 ret = get_user_ual(trap_instr, env->active_tc.PC);
1308c464
KCY		 2581 if (ret != 0) {
2582 goto error;
2583 }
54b2f42c 2584
1308c464
KCY		 2585 /* As described in the original Linux kernel code, the
2586 * below checks on 'code' are to work around an old
2587 * assembly bug.
2588 */
2589 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2590 if (code >= (1 << 10)) {
2591 code >>= 10;
2592 }
54b2f42c
MI		 2593 }
2594
2595 if (do_break(env, &info, code) != 0) {
2596 goto error;
2597 }
2598 }
2599 break;
2600 case EXCP_TRAP:
2601 {
2602 abi_ulong trap_instr;
2603 unsigned int code = 0;
2604
a0333817
KCY		 2605 if (env->hflags & MIPS_HFLAG_M16) {
2606 /* microMIPS mode */
2607 abi_ulong instr[2];
2608
2609 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2610 get_user_u16(instr[1], env->active_tc.PC + 2);
2611
2612 trap_instr = (instr[0] << 16) | instr[1];
2613 } else {
2614 ret = get_user_ual(trap_instr, env->active_tc.PC);
2615 }
2616
54b2f42c
MI		 2617 if (ret != 0) {
2618 goto error;
2619 }
2620
2621 /* The immediate versions don't provide a code. */
2622 if (!(trap_instr & 0xFC000000)) {
a0333817
KCY		 2623 if (env->hflags & MIPS_HFLAG_M16) {
2624 /* microMIPS mode */
2625 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2626 } else {
2627 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2628 }
54b2f42c
MI		 2629 }
2630
2631 if (do_break(env, &info, code) != 0) {
2632 goto error;
2633 }
2634 }
2635 break;
048f6b4d 2636 default:
54b2f42c 2637error:
5fafdf24 2638 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
048f6b4d 2639 trapnr);
878096ee 2640 cpu_dump_state(cs, stderr, fprintf, 0);
048f6b4d
FB		 2641 abort();
2642 }
2643 process_pending_signals(env);
2644 }
2645}
2646#endif
2647
d962783e
JL		 2648#ifdef TARGET_OPENRISC
2649
2650void cpu_loop(CPUOpenRISCState *env)
2651{
878096ee 2652 CPUState *cs = CPU(openrisc_env_get_cpu(env));
d962783e
JL		 2653 int trapnr, gdbsig;
2654
2655 for (;;) {
b040bc9c 2656 cpu_exec_start(cs);
ea3e9847 2657 trapnr = cpu_openrisc_exec(cs);
b040bc9c 2658 cpu_exec_end(cs);
d962783e
JL		 2659 gdbsig = 0;
2660
2661 switch (trapnr) {
2662 case EXCP_RESET:
2663 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2664 exit(1);
2665 break;
2666 case EXCP_BUSERR:
2667 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
a86b3c64 2668 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2669 break;
2670 case EXCP_DPF:
2671 case EXCP_IPF:
878096ee 2672 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2673 gdbsig = TARGET_SIGSEGV;
2674 break;
2675 case EXCP_TICK:
2676 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2677 break;
2678 case EXCP_ALIGN:
2679 qemu_log("\nAlignment pc is %#x\n", env->pc);
a86b3c64 2680 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2681 break;
2682 case EXCP_ILLEGAL:
2683 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
a86b3c64 2684 gdbsig = TARGET_SIGILL;
d962783e
JL		 2685 break;
2686 case EXCP_INT:
2687 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2688 break;
2689 case EXCP_DTLBMISS:
2690 case EXCP_ITLBMISS:
2691 qemu_log("\nTLB miss\n");
2692 break;
2693 case EXCP_RANGE:
2694 qemu_log("\nRange\n");
a86b3c64 2695 gdbsig = TARGET_SIGSEGV;
d962783e
JL		 2696 break;
2697 case EXCP_SYSCALL:
2698 env->pc += 4; /* 0xc00; */
2699 env->gpr[11] = do_syscall(env,
2700 env->gpr[11], /* return value */
2701 env->gpr[3], /* r3 - r7 are params */
2702 env->gpr[4],
2703 env->gpr[5],
2704 env->gpr[6],
2705 env->gpr[7],
2706 env->gpr[8], 0, 0);
2707 break;
2708 case EXCP_FPE:
2709 qemu_log("\nFloating point error\n");
2710 break;
2711 case EXCP_TRAP:
2712 qemu_log("\nTrap\n");
a86b3c64 2713 gdbsig = TARGET_SIGTRAP;
d962783e
JL		 2714 break;
2715 case EXCP_NR:
2716 qemu_log("\nNR\n");
2717 break;
2718 default:
2719 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2720 trapnr);
878096ee 2721 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2722 gdbsig = TARGET_SIGILL;
2723 break;
2724 }
2725 if (gdbsig) {
db6b81d4 2726 gdb_handlesig(cs, gdbsig);
d962783e
JL		 2727 if (gdbsig != TARGET_SIGTRAP) {
2728 exit(1);
2729 }
2730 }
2731
2732 process_pending_signals(env);
2733 }
2734}
2735
2736#endif /* TARGET_OPENRISC */
2737
fdf9b3e8 2738#ifdef TARGET_SH4
05390248 2739void cpu_loop(CPUSH4State *env)
fdf9b3e8 2740{
878096ee 2741 CPUState *cs = CPU(sh_env_get_cpu(env));
fdf9b3e8 2742 int trapnr, ret;
c227f099 2743 target_siginfo_t info;
3b46e624 2744
fdf9b3e8 2745 while (1) {
b040bc9c 2746 cpu_exec_start(cs);
ea3e9847 2747 trapnr = cpu_sh4_exec(cs);
b040bc9c 2748 cpu_exec_end(cs);
3b46e624 2749
fdf9b3e8
FB		 2750 switch (trapnr) {
2751 case 0x160:
0b6d3ae0 2752 env->pc += 2;
5fafdf24
TS		 2753 ret = do_syscall(env,
2754 env->gregs[3],
2755 env->gregs[4],
2756 env->gregs[5],
2757 env->gregs[6],
2758 env->gregs[7],
2759 env->gregs[0],
5945cfcb
PM		 2760 env->gregs[1],
2761 0, 0);
9c2a9ea1 2762 env->gregs[0] = ret;
fdf9b3e8 2763 break;
c3b5bc8a
TS		 2764 case EXCP_INTERRUPT:
2765 /* just indicate that signals should be handled asap */
2766 break;
355fb23d
PB		 2767 case EXCP_DEBUG:
2768 {
2769 int sig;
2770
db6b81d4 2771 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
355fb23d
PB		 2772 if (sig)
2773 {
2774 info.si_signo = sig;
2775 info.si_errno = 0;
2776 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2777 queue_signal(env, info.si_signo, &info);
355fb23d
PB		 2778 }
2779 }
2780 break;
c3b5bc8a
TS		 2781 case 0xa0:
2782 case 0xc0:
a86b3c64 2783 info.si_signo = TARGET_SIGSEGV;
c3b5bc8a
TS		 2784 info.si_errno = 0;
2785 info.si_code = TARGET_SEGV_MAPERR;
2786 info._sifields._sigfault._addr = env->tea;
624f7979 2787 queue_signal(env, info.si_signo, &info);
c3b5bc8a
TS		 2788 break;
2789
fdf9b3e8
FB		 2790 default:
2791 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2792 cpu_dump_state(cs, stderr, fprintf, 0);
fdf9b3e8
FB		 2793 exit (1);
2794 }
2795 process_pending_signals (env);
2796 }
2797}
2798#endif
2799
48733d19 2800#ifdef TARGET_CRIS
05390248 2801void cpu_loop(CPUCRISState *env)
48733d19 2802{
878096ee 2803 CPUState *cs = CPU(cris_env_get_cpu(env));
48733d19 2804 int trapnr, ret;
c227f099 2805 target_siginfo_t info;
48733d19
TS		 2806
2807 while (1) {
b040bc9c 2808 cpu_exec_start(cs);
ea3e9847 2809 trapnr = cpu_cris_exec(cs);
b040bc9c 2810 cpu_exec_end(cs);
48733d19
TS		 2811 switch (trapnr) {
2812 case 0xaa:
2813 {
a86b3c64 2814 info.si_signo = TARGET_SIGSEGV;
48733d19
TS		 2815 info.si_errno = 0;
2816 /* XXX: check env->error_code */
2817 info.si_code = TARGET_SEGV_MAPERR;
e00c1e71 2818 info._sifields._sigfault._addr = env->pregs[PR_EDA];
624f7979 2819 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2820 }
2821 break;
b6d3abda
EI		 2822 case EXCP_INTERRUPT:
2823 /* just indicate that signals should be handled asap */
2824 break;
48733d19
TS		 2825 case EXCP_BREAK:
2826 ret = do_syscall(env,
2827 env->regs[9],
2828 env->regs[10],
2829 env->regs[11],
2830 env->regs[12],
2831 env->regs[13],
2832 env->pregs[7],
5945cfcb
PM		 2833 env->pregs[11],
2834 0, 0);
48733d19 2835 env->regs[10] = ret;
48733d19
TS		 2836 break;
2837 case EXCP_DEBUG:
2838 {
2839 int sig;
2840
db6b81d4 2841 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
48733d19
TS		 2842 if (sig)
2843 {
2844 info.si_signo = sig;
2845 info.si_errno = 0;
2846 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2847 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2848 }
2849 }
2850 break;
2851 default:
2852 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2853 cpu_dump_state(cs, stderr, fprintf, 0);
48733d19
TS		 2854 exit (1);
2855 }
2856 process_pending_signals (env);
2857 }
2858}
2859#endif
2860
b779e29e 2861#ifdef TARGET_MICROBLAZE
05390248 2862void cpu_loop(CPUMBState *env)
b779e29e 2863{
878096ee 2864 CPUState *cs = CPU(mb_env_get_cpu(env));
b779e29e 2865 int trapnr, ret;
c227f099 2866 target_siginfo_t info;
b779e29e
EI		 2867
2868 while (1) {
b040bc9c 2869 cpu_exec_start(cs);
ea3e9847 2870 trapnr = cpu_mb_exec(cs);
b040bc9c 2871 cpu_exec_end(cs);
b779e29e
EI		 2872 switch (trapnr) {
2873 case 0xaa:
2874 {
a86b3c64 2875 info.si_signo = TARGET_SIGSEGV;
b779e29e
EI		 2876 info.si_errno = 0;
2877 /* XXX: check env->error_code */
2878 info.si_code = TARGET_SEGV_MAPERR;
2879 info._sifields._sigfault._addr = 0;
2880 queue_signal(env, info.si_signo, &info);
2881 }
2882 break;
2883 case EXCP_INTERRUPT:
2884 /* just indicate that signals should be handled asap */
2885 break;
2886 case EXCP_BREAK:
2887 /* Return address is 4 bytes after the call. */
2888 env->regs[14] += 4;
d7dce494 2889 env->sregs[SR_PC] = env->regs[14];
b779e29e
EI		 2890 ret = do_syscall(env,
2891 env->regs[12],
2892 env->regs[5],
2893 env->regs[6],
2894 env->regs[7],
2895 env->regs[8],
2896 env->regs[9],
5945cfcb
PM		 2897 env->regs[10],
2898 0, 0);
b779e29e 2899 env->regs[3] = ret;
b779e29e 2900 break;
b76da7e3
EI		 2901 case EXCP_HW_EXCP:
2902 env->regs[17] = env->sregs[SR_PC] + 4;
2903 if (env->iflags & D_FLAG) {
2904 env->sregs[SR_ESR] |= 1 << 12;
2905 env->sregs[SR_PC] -= 4;
b4916d7b 2906 /* FIXME: if branch was immed, replay the imm as well. */
b76da7e3
EI		 2907 }
2908
2909 env->iflags &= ~(IMM_FLAG | D_FLAG);
2910
2911 switch (env->sregs[SR_ESR] & 31) {
22a78d64 2912 case ESR_EC_DIVZERO:
a86b3c64 2913 info.si_signo = TARGET_SIGFPE;
22a78d64
EI		 2914 info.si_errno = 0;
2915 info.si_code = TARGET_FPE_FLTDIV;
2916 info._sifields._sigfault._addr = 0;
2917 queue_signal(env, info.si_signo, &info);
2918 break;
b76da7e3 2919 case ESR_EC_FPU:
a86b3c64 2920 info.si_signo = TARGET_SIGFPE;
b76da7e3
EI		 2921 info.si_errno = 0;
2922 if (env->sregs[SR_FSR] & FSR_IO) {
2923 info.si_code = TARGET_FPE_FLTINV;
2924 }
2925 if (env->sregs[SR_FSR] & FSR_DZ) {
2926 info.si_code = TARGET_FPE_FLTDIV;
2927 }
2928 info._sifields._sigfault._addr = 0;
2929 queue_signal(env, info.si_signo, &info);
2930 break;
2931 default:
2932 printf ("Unhandled hw-exception: 0x%x\n",
2e42d52d 2933 env->sregs[SR_ESR] & ESR_EC_MASK);
878096ee 2934 cpu_dump_state(cs, stderr, fprintf, 0);
b76da7e3
EI		 2935 exit (1);
2936 break;
2937 }
2938 break;
b779e29e
EI		 2939 case EXCP_DEBUG:
2940 {
2941 int sig;
2942
db6b81d4 2943 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
b779e29e
EI		 2944 if (sig)
2945 {
2946 info.si_signo = sig;
2947 info.si_errno = 0;
2948 info.si_code = TARGET_TRAP_BRKPT;
2949 queue_signal(env, info.si_signo, &info);
2950 }
2951 }
2952 break;
2953 default:
2954 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2955 cpu_dump_state(cs, stderr, fprintf, 0);
b779e29e
EI		 2956 exit (1);
2957 }
2958 process_pending_signals (env);
2959 }
2960}
2961#endif
2962
e6e5906b
PB		 2963#ifdef TARGET_M68K
2964
2965void cpu_loop(CPUM68KState *env)
2966{
878096ee 2967 CPUState *cs = CPU(m68k_env_get_cpu(env));
e6e5906b
PB		 2968 int trapnr;
2969 unsigned int n;
c227f099 2970 target_siginfo_t info;
0429a971 2971 TaskState *ts = cs->opaque;
3b46e624 2972
e6e5906b 2973 for(;;) {
b040bc9c 2974 cpu_exec_start(cs);
ea3e9847 2975 trapnr = cpu_m68k_exec(cs);
b040bc9c 2976 cpu_exec_end(cs);
e6e5906b
PB		 2977 switch(trapnr) {
2978 case EXCP_ILLEGAL:
2979 {
2980 if (ts->sim_syscalls) {
2981 uint16_t nr;
d8d5119c 2982 get_user_u16(nr, env->pc + 2);
e6e5906b
PB		 2983 env->pc += 4;
2984 do_m68k_simcall(env, nr);
2985 } else {
2986 goto do_sigill;
2987 }
2988 }
2989 break;
a87295e8 2990 case EXCP_HALT_INSN:
e6e5906b 2991 /* Semihosing syscall. */
a87295e8 2992 env->pc += 4;
e6e5906b
PB		 2993 do_m68k_semihosting(env, env->dregs[0]);
2994 break;
2995 case EXCP_LINEA:
2996 case EXCP_LINEF:
2997 case EXCP_UNSUPPORTED:
2998 do_sigill:
a86b3c64 2999 info.si_signo = TARGET_SIGILL;
e6e5906b
PB		 3000 info.si_errno = 0;
3001 info.si_code = TARGET_ILL_ILLOPN;
3002 info._sifields._sigfault._addr = env->pc;
624f7979 3003 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3004 break;
3005 case EXCP_TRAP0:
3006 {
3007 ts->sim_syscalls = 0;
3008 n = env->dregs[0];
3009 env->pc += 2;
5fafdf24
TS		 3010 env->dregs[0] = do_syscall(env,
3011 n,
e6e5906b
PB		 3012 env->dregs[1],
3013 env->dregs[2],
3014 env->dregs[3],
3015 env->dregs[4],
3016 env->dregs[5],
5945cfcb
PM		 3017 env->aregs[0],
3018 0, 0);
e6e5906b
PB		 3019 }
3020 break;
3021 case EXCP_INTERRUPT:
3022 /* just indicate that signals should be handled asap */
3023 break;
3024 case EXCP_ACCESS:
3025 {
a86b3c64 3026 info.si_signo = TARGET_SIGSEGV;
e6e5906b
PB		 3027 info.si_errno = 0;
3028 /* XXX: check env->error_code */
3029 info.si_code = TARGET_SEGV_MAPERR;
3030 info._sifields._sigfault._addr = env->mmu.ar;
624f7979 3031 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3032 }
3033 break;
3034 case EXCP_DEBUG:
3035 {
3036 int sig;
3037
db6b81d4 3038 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
e6e5906b
PB		 3039 if (sig)
3040 {
3041 info.si_signo = sig;
3042 info.si_errno = 0;
3043 info.si_code = TARGET_TRAP_BRKPT;
624f7979 3044 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3045 }
3046 }
3047 break;
3048 default:
5fafdf24 3049 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
e6e5906b 3050 trapnr);
878096ee 3051 cpu_dump_state(cs, stderr, fprintf, 0);
e6e5906b
PB		 3052 abort();
3053 }
3054 process_pending_signals(env);
3055 }
3056}
3057#endif /* TARGET_M68K */
3058
7a3148a9 3059#ifdef TARGET_ALPHA
6910b8f6
RH		 3060static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3061{
3062 target_ulong addr, val, tmp;
3063 target_siginfo_t info;
3064 int ret = 0;
3065
3066 addr = env->lock_addr;
3067 tmp = env->lock_st_addr;
3068 env->lock_addr = -1;
3069 env->lock_st_addr = 0;
3070
3071 start_exclusive();
3072 mmap_lock();
3073
3074 if (addr == tmp) {
3075 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3076 goto do_sigsegv;
3077 }
3078
3079 if (val == env->lock_value) {
3080 tmp = env->ir[reg];
3081 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3082 goto do_sigsegv;
3083 }
3084 ret = 1;
3085 }
3086 }
3087 env->ir[reg] = ret;
3088 env->pc += 4;
3089
3090 mmap_unlock();
3091 end_exclusive();
3092 return;
3093
3094 do_sigsegv:
3095 mmap_unlock();
3096 end_exclusive();
3097
3098 info.si_signo = TARGET_SIGSEGV;
3099 info.si_errno = 0;
3100 info.si_code = TARGET_SEGV_MAPERR;
3101 info._sifields._sigfault._addr = addr;
3102 queue_signal(env, TARGET_SIGSEGV, &info);
3103}
3104
05390248 3105void cpu_loop(CPUAlphaState *env)
7a3148a9 3106{
878096ee 3107 CPUState *cs = CPU(alpha_env_get_cpu(env));
e96efcfc 3108 int trapnr;
c227f099 3109 target_siginfo_t info;
6049f4f8 3110 abi_long sysret;
3b46e624 3111
7a3148a9 3112 while (1) {
b040bc9c 3113 cpu_exec_start(cs);
ea3e9847 3114 trapnr = cpu_alpha_exec(cs);
b040bc9c 3115 cpu_exec_end(cs);
3b46e624 3116
ac316ca4
RH		 3117 /* All of the traps imply a transition through PALcode, which
3118 implies an REI instruction has been executed. Which means
3119 that the intr_flag should be cleared. */
3120 env->intr_flag = 0;
3121
7a3148a9
JM		 3122 switch (trapnr) {
3123 case EXCP_RESET:
3124 fprintf(stderr, "Reset requested. Exit\n");
3125 exit(1);
3126 break;
3127 case EXCP_MCHK:
3128 fprintf(stderr, "Machine check exception. Exit\n");
3129 exit(1);
3130 break;
07b6c13b
RH		 3131 case EXCP_SMP_INTERRUPT:
3132 case EXCP_CLK_INTERRUPT:
3133 case EXCP_DEV_INTERRUPT:
5fafdf24 3134 fprintf(stderr, "External interrupt. Exit\n");
7a3148a9
JM		 3135 exit(1);
3136 break;
07b6c13b 3137 case EXCP_MMFAULT:
6910b8f6 3138 env->lock_addr = -1;
6049f4f8
RH		 3139 info.si_signo = TARGET_SIGSEGV;
3140 info.si_errno = 0;
129d8aa5 3141 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
0be1d07c 3142 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
129d8aa5 3143 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3144 queue_signal(env, info.si_signo, &info);
7a3148a9 3145 break;
7a3148a9 3146 case EXCP_UNALIGN:
6910b8f6 3147 env->lock_addr = -1;
6049f4f8
RH		 3148 info.si_signo = TARGET_SIGBUS;
3149 info.si_errno = 0;
3150 info.si_code = TARGET_BUS_ADRALN;
129d8aa5 3151 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3152 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3153 break;
3154 case EXCP_OPCDEC:
6049f4f8 3155 do_sigill:
6910b8f6 3156 env->lock_addr = -1;
6049f4f8
RH		 3157 info.si_signo = TARGET_SIGILL;
3158 info.si_errno = 0;
3159 info.si_code = TARGET_ILL_ILLOPC;
3160 info._sifields._sigfault._addr = env->pc;
3161 queue_signal(env, info.si_signo, &info);
7a3148a9 3162 break;
07b6c13b
RH		 3163 case EXCP_ARITH:
3164 env->lock_addr = -1;
3165 info.si_signo = TARGET_SIGFPE;
3166 info.si_errno = 0;
3167 info.si_code = TARGET_FPE_FLTINV;
3168 info._sifields._sigfault._addr = env->pc;
3169 queue_signal(env, info.si_signo, &info);
3170 break;
7a3148a9 3171 case EXCP_FEN:
6049f4f8 3172 /* No-op. Linux simply re-enables the FPU. */
7a3148a9 3173 break;
07b6c13b 3174 case EXCP_CALL_PAL:
6910b8f6 3175 env->lock_addr = -1;
07b6c13b 3176 switch (env->error_code) {
6049f4f8
RH		 3177 case 0x80:
3178 /* BPT */
3179 info.si_signo = TARGET_SIGTRAP;
3180 info.si_errno = 0;
3181 info.si_code = TARGET_TRAP_BRKPT;
3182 info._sifields._sigfault._addr = env->pc;
3183 queue_signal(env, info.si_signo, &info);
3184 break;
3185 case 0x81:
3186 /* BUGCHK */
3187 info.si_signo = TARGET_SIGTRAP;
3188 info.si_errno = 0;
3189 info.si_code = 0;
3190 info._sifields._sigfault._addr = env->pc;
3191 queue_signal(env, info.si_signo, &info);
3192 break;
3193 case 0x83:
3194 /* CALLSYS */
3195 trapnr = env->ir[IR_V0];
3196 sysret = do_syscall(env, trapnr,
3197 env->ir[IR_A0], env->ir[IR_A1],
3198 env->ir[IR_A2], env->ir[IR_A3],
5945cfcb
PM		 3199 env->ir[IR_A4], env->ir[IR_A5],
3200 0, 0);
a5b3b13b
RH		 3201 if (trapnr == TARGET_NR_sigreturn
3202 || trapnr == TARGET_NR_rt_sigreturn) {
3203 break;
3204 }
3205 /* Syscall writes 0 to V0 to bypass error check, similar
0e141977
RH		 3206 to how this is handled internal to Linux kernel.
3207 (Ab)use trapnr temporarily as boolean indicating error. */
3208 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3209 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3210 env->ir[IR_A3] = trapnr;
6049f4f8
RH		 3211 break;
3212 case 0x86:
3213 /* IMB */
3214 /* ??? We can probably elide the code using page_unprotect
3215 that is checking for self-modifying code. Instead we
3216 could simply call tb_flush here. Until we work out the
3217 changes required to turn off the extra write protection,
3218 this can be a no-op. */
3219 break;
3220 case 0x9E:
3221 /* RDUNIQUE */
3222 /* Handled in the translator for usermode. */
3223 abort();
3224 case 0x9F:
3225 /* WRUNIQUE */
3226 /* Handled in the translator for usermode. */
3227 abort();
3228 case 0xAA:
3229 /* GENTRAP */
3230 info.si_signo = TARGET_SIGFPE;
3231 switch (env->ir[IR_A0]) {
3232 case TARGET_GEN_INTOVF:
3233 info.si_code = TARGET_FPE_INTOVF;
3234 break;
3235 case TARGET_GEN_INTDIV:
3236 info.si_code = TARGET_FPE_INTDIV;
3237 break;
3238 case TARGET_GEN_FLTOVF:
3239 info.si_code = TARGET_FPE_FLTOVF;
3240 break;
3241 case TARGET_GEN_FLTUND:
3242 info.si_code = TARGET_FPE_FLTUND;
3243 break;
3244 case TARGET_GEN_FLTINV:
3245 info.si_code = TARGET_FPE_FLTINV;
3246 break;
3247 case TARGET_GEN_FLTINE:
3248 info.si_code = TARGET_FPE_FLTRES;
3249 break;
3250 case TARGET_GEN_ROPRAND:
3251 info.si_code = 0;
3252 break;
3253 default:
3254 info.si_signo = TARGET_SIGTRAP;
3255 info.si_code = 0;
3256 break;
3257 }
3258 info.si_errno = 0;
3259 info._sifields._sigfault._addr = env->pc;
3260 queue_signal(env, info.si_signo, &info);
3261 break;
3262 default:
3263 goto do_sigill;
3264 }
7a3148a9 3265 break;
7a3148a9 3266 case EXCP_DEBUG:
db6b81d4 3267 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
6049f4f8 3268 if (info.si_signo) {
6910b8f6 3269 env->lock_addr = -1;
6049f4f8
RH		 3270 info.si_errno = 0;
3271 info.si_code = TARGET_TRAP_BRKPT;
3272 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3273 }
3274 break;
6910b8f6
RH		 3275 case EXCP_STL_C:
3276 case EXCP_STQ_C:
3277 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3278 break;
d0f20495
RH		 3279 case EXCP_INTERRUPT:
3280 /* Just indicate that signals should be handled asap. */
3281 break;
7a3148a9
JM		 3282 default:
3283 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3284 cpu_dump_state(cs, stderr, fprintf, 0);
7a3148a9
JM		 3285 exit (1);
3286 }
3287 process_pending_signals (env);
3288 }
3289}
3290#endif /* TARGET_ALPHA */
3291
a4c075f1
UH		 3292#ifdef TARGET_S390X
3293void cpu_loop(CPUS390XState *env)
3294{
878096ee 3295 CPUState *cs = CPU(s390_env_get_cpu(env));
d5a103cd 3296 int trapnr, n, sig;
a4c075f1 3297 target_siginfo_t info;
d5a103cd 3298 target_ulong addr;
a4c075f1
UH		 3299
3300 while (1) {
b040bc9c 3301 cpu_exec_start(cs);
ea3e9847 3302 trapnr = cpu_s390x_exec(cs);
b040bc9c 3303 cpu_exec_end(cs);
a4c075f1
UH		 3304 switch (trapnr) {
3305 case EXCP_INTERRUPT:
d5a103cd 3306 /* Just indicate that signals should be handled asap. */
a4c075f1 3307 break;
a4c075f1 3308
d5a103cd
RH		 3309 case EXCP_SVC:
3310 n = env->int_svc_code;
3311 if (!n) {
3312 /* syscalls > 255 */
3313 n = env->regs[1];
a4c075f1 3314 }
d5a103cd
RH		 3315 env->psw.addr += env->int_svc_ilen;
3316 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3317 env->regs[4], env->regs[5],
3318 env->regs[6], env->regs[7], 0, 0);
a4c075f1 3319 break;
d5a103cd
RH		 3320
3321 case EXCP_DEBUG:
db6b81d4 3322 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d5a103cd
RH		 3323 if (sig) {
3324 n = TARGET_TRAP_BRKPT;
3325 goto do_signal_pc;
a4c075f1
UH		 3326 }
3327 break;
d5a103cd
RH		 3328 case EXCP_PGM:
3329 n = env->int_pgm_code;
3330 switch (n) {
3331 case PGM_OPERATION:
3332 case PGM_PRIVILEGED:
a86b3c64 3333 sig = TARGET_SIGILL;
d5a103cd
RH		 3334 n = TARGET_ILL_ILLOPC;
3335 goto do_signal_pc;
3336 case PGM_PROTECTION:
3337 case PGM_ADDRESSING:
a86b3c64 3338 sig = TARGET_SIGSEGV;
a4c075f1 3339 /* XXX: check env->error_code */
d5a103cd
RH		 3340 n = TARGET_SEGV_MAPERR;
3341 addr = env->__excp_addr;
3342 goto do_signal;
3343 case PGM_EXECUTE:
3344 case PGM_SPECIFICATION:
3345 case PGM_SPECIAL_OP:
3346 case PGM_OPERAND:
3347 do_sigill_opn:
a86b3c64 3348 sig = TARGET_SIGILL;
d5a103cd
RH		 3349 n = TARGET_ILL_ILLOPN;
3350 goto do_signal_pc;
3351
3352 case PGM_FIXPT_OVERFLOW:
a86b3c64 3353 sig = TARGET_SIGFPE;
d5a103cd
RH		 3354 n = TARGET_FPE_INTOVF;
3355 goto do_signal_pc;
3356 case PGM_FIXPT_DIVIDE:
a86b3c64 3357 sig = TARGET_SIGFPE;
d5a103cd
RH		 3358 n = TARGET_FPE_INTDIV;
3359 goto do_signal_pc;
3360
3361 case PGM_DATA:
3362 n = (env->fpc >> 8) & 0xff;
3363 if (n == 0xff) {
3364 /* compare-and-trap */
3365 goto do_sigill_opn;
3366 } else {
3367 /* An IEEE exception, simulated or otherwise. */
3368 if (n & 0x80) {
3369 n = TARGET_FPE_FLTINV;
3370 } else if (n & 0x40) {
3371 n = TARGET_FPE_FLTDIV;
3372 } else if (n & 0x20) {
3373 n = TARGET_FPE_FLTOVF;
3374 } else if (n & 0x10) {
3375 n = TARGET_FPE_FLTUND;
3376 } else if (n & 0x08) {
3377 n = TARGET_FPE_FLTRES;
3378 } else {
3379 /* ??? Quantum exception; BFP, DFP error. */
3380 goto do_sigill_opn;
3381 }
a86b3c64 3382 sig = TARGET_SIGFPE;
d5a103cd
RH		 3383 goto do_signal_pc;
3384 }
3385
3386 default:
3387 fprintf(stderr, "Unhandled program exception: %#x\n", n);
878096ee 3388 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3389 exit(1);
a4c075f1
UH		 3390 }
3391 break;
d5a103cd
RH		 3392
3393 do_signal_pc:
3394 addr = env->psw.addr;
3395 do_signal:
3396 info.si_signo = sig;
3397 info.si_errno = 0;
3398 info.si_code = n;
3399 info._sifields._sigfault._addr = addr;
3400 queue_signal(env, info.si_signo, &info);
a4c075f1 3401 break;
d5a103cd 3402
a4c075f1 3403 default:
d5a103cd 3404 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
878096ee 3405 cpu_dump_state(cs, stderr, fprintf, 0);
d5a103cd 3406 exit(1);
a4c075f1
UH		 3407 }
3408 process_pending_signals (env);
3409 }
3410}
3411
3412#endif /* TARGET_S390X */
3413
a2247f8e 3414THREAD CPUState *thread_cpu;
59faf6d6 3415
edf8e2af
MW		 3416void task_settid(TaskState *ts)
3417{
3418 if (ts->ts_tid == 0) {
edf8e2af 3419 ts->ts_tid = (pid_t)syscall(SYS_gettid);
edf8e2af
MW		 3420 }
3421}
3422
3423void stop_all_tasks(void)
3424{
3425 /*
3426 * We trust that when using NPTL, start_exclusive()
3427 * handles thread stopping correctly.
3428 */
3429 start_exclusive();
3430}
3431
c3a92833 3432/* Assumes contents are already zeroed. */
624f7979
PB		 3433void init_task_state(TaskState *ts)
3434{
3435 int i;
3436
624f7979
PB		 3437 ts->used = 1;
3438 ts->first_free = ts->sigqueue_table;
3439 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3440 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3441 }
3442 ts->sigqueue_table[i].next = NULL;
3443}
fc9c5412 3444
30ba0ee5
AF		 3445CPUArchState *cpu_copy(CPUArchState *env)
3446{
ff4700b0 3447 CPUState *cpu = ENV_GET_CPU(env);
2994fd96 3448 CPUState *new_cpu = cpu_init(cpu_model);
61c7480f 3449 CPUArchState *new_env = new_cpu->env_ptr;
30ba0ee5
AF		 3450 CPUBreakpoint *bp;
3451 CPUWatchpoint *wp;
30ba0ee5
AF		 3452
3453 /* Reset non arch specific state */
75a34036 3454 cpu_reset(new_cpu);
30ba0ee5
AF		 3455
3456 memcpy(new_env, env, sizeof(CPUArchState));
3457
3458 /* Clone all break/watchpoints.
3459 Note: Once we support ptrace with hw-debug register access, make sure
3460 BP_CPU break/watchpoints are handled correctly on clone. */
1d085f6c
TB		 3461 QTAILQ_INIT(&new_cpu->breakpoints);
3462 QTAILQ_INIT(&new_cpu->watchpoints);
f0c3c505 3463 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
b3310ab3 3464 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
30ba0ee5 3465 }
ff4700b0 3466 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
05068c0d 3467 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
30ba0ee5 3468 }
30ba0ee5
AF		 3469
3470 return new_env;
3471}
3472
fc9c5412
JS		 3473static void handle_arg_help(const char *arg)
3474{
3475 usage();
3476}
3477
3478static void handle_arg_log(const char *arg)
3479{
3480 int mask;
fc9c5412 3481
4fde1eba 3482 mask = qemu_str_to_log_mask(arg);
fc9c5412 3483 if (!mask) {
59a6fa6e 3484 qemu_print_log_usage(stdout);
fc9c5412
JS		 3485 exit(1);
3486 }
24537a01 3487 qemu_set_log(mask);
fc9c5412
JS		 3488}
3489
50171d42
CWR		 3490static void handle_arg_log_filename(const char *arg)
3491{
9a7e5424 3492 qemu_set_log_filename(arg);
50171d42
CWR		 3493}
3494
fc9c5412
JS		 3495static void handle_arg_set_env(const char *arg)
3496{
3497 char *r, *p, *token;
3498 r = p = strdup(arg);
3499 while ((token = strsep(&p, ",")) != NULL) {
3500 if (envlist_setenv(envlist, token) != 0) {
3501 usage();
3502 }
3503 }
3504 free(r);
3505}
3506
3507static void handle_arg_unset_env(const char *arg)
3508{
3509 char *r, *p, *token;
3510 r = p = strdup(arg);
3511 while ((token = strsep(&p, ",")) != NULL) {
3512 if (envlist_unsetenv(envlist, token) != 0) {
3513 usage();
3514 }
3515 }
3516 free(r);
3517}
3518
3519static void handle_arg_argv0(const char *arg)
3520{
3521 argv0 = strdup(arg);
3522}
3523
3524static void handle_arg_stack_size(const char *arg)
3525{
3526 char *p;
3527 guest_stack_size = strtoul(arg, &p, 0);
3528 if (guest_stack_size == 0) {
3529 usage();
3530 }
3531
3532 if (*p == 'M') {
3533 guest_stack_size *= 1024 * 1024;
3534 } else if (*p == 'k' || *p == 'K') {
3535 guest_stack_size *= 1024;
3536 }
3537}
3538
3539static void handle_arg_ld_prefix(const char *arg)
3540{
3541 interp_prefix = strdup(arg);
3542}
3543
3544static void handle_arg_pagesize(const char *arg)
3545{
3546 qemu_host_page_size = atoi(arg);
3547 if (qemu_host_page_size == 0 ||
3548 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3549 fprintf(stderr, "page size must be a power of two\n");
3550 exit(1);
3551 }
3552}
3553
c5e4a5a9
MR		 3554static void handle_arg_randseed(const char *arg)
3555{
3556 unsigned long long seed;
3557
3558 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3559 fprintf(stderr, "Invalid seed number: %s\n", arg);
3560 exit(1);
3561 }
3562 srand(seed);
3563}
3564
fc9c5412
JS		 3565static void handle_arg_gdb(const char *arg)
3566{
3567 gdbstub_port = atoi(arg);
3568}
3569
3570static void handle_arg_uname(const char *arg)
3571{
3572 qemu_uname_release = strdup(arg);
3573}
3574
3575static void handle_arg_cpu(const char *arg)
3576{
3577 cpu_model = strdup(arg);
c8057f95 3578 if (cpu_model == NULL || is_help_option(cpu_model)) {
fc9c5412 3579 /* XXX: implement xxx_cpu_list for targets that still miss it */
e916cbf8
PM		 3580#if defined(cpu_list)
3581 cpu_list(stdout, &fprintf);
fc9c5412
JS		 3582#endif
3583 exit(1);
3584 }
3585}
3586
3587#if defined(CONFIG_USE_GUEST_BASE)
3588static void handle_arg_guest_base(const char *arg)
3589{
3590 guest_base = strtol(arg, NULL, 0);
3591 have_guest_base = 1;
3592}
3593
3594static void handle_arg_reserved_va(const char *arg)
3595{
3596 char *p;
3597 int shift = 0;
3598 reserved_va = strtoul(arg, &p, 0);
3599 switch (*p) {
3600 case 'k':
3601 case 'K':
3602 shift = 10;
3603 break;
3604 case 'M':
3605 shift = 20;
3606 break;
3607 case 'G':
3608 shift = 30;
3609 break;
3610 }
3611 if (shift) {
3612 unsigned long unshifted = reserved_va;
3613 p++;
3614 reserved_va <<= shift;
3615 if (((reserved_va >> shift) != unshifted)
3616#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3617 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3618#endif
3619 ) {
3620 fprintf(stderr, "Reserved virtual address too big\n");
3621 exit(1);
3622 }
3623 }
3624 if (*p) {
3625 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3626 exit(1);
3627 }
3628}
3629#endif
3630
3631static void handle_arg_singlestep(const char *arg)
3632{
3633 singlestep = 1;
3634}
3635
3636static void handle_arg_strace(const char *arg)
3637{
3638 do_strace = 1;
3639}
3640
3641static void handle_arg_version(const char *arg)
3642{
2e59915d 3643 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
fc9c5412 3644 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
1386d4c0 3645 exit(0);
fc9c5412
JS		 3646}
3647
3648struct qemu_argument {
3649 const char *argv;
3650 const char *env;
3651 bool has_arg;
3652 void (*handle_opt)(const char *arg);
3653 const char *example;
3654 const char *help;
3655};
3656
42644cee 3657static const struct qemu_argument arg_table[] = {
fc9c5412
JS		 3658 {"h", "", false, handle_arg_help,
3659 "", "print this help"},
3660 {"g", "QEMU_GDB", true, handle_arg_gdb,
3661 "port", "wait gdb connection to 'port'"},
3662 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3663 "path", "set the elf interpreter prefix to 'path'"},
3664 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3665 "size", "set the stack size to 'size' bytes"},
3666 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
c8057f95 3667 "model", "select CPU (-cpu help for list)"},
fc9c5412
JS		 3668 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3669 "var=value", "sets targets environment variable (see below)"},
3670 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3671 "var", "unsets targets environment variable (see below)"},
3672 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3673 "argv0", "forces target process argv[0] to be 'argv0'"},
3674 {"r", "QEMU_UNAME", true, handle_arg_uname,
3675 "uname", "set qemu uname release string to 'uname'"},
3676#if defined(CONFIG_USE_GUEST_BASE)
3677 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3678 "address", "set guest_base address to 'address'"},
3679 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3680 "size", "reserve 'size' bytes for guest virtual address space"},
3681#endif
3682 {"d", "QEMU_LOG", true, handle_arg_log,
989b697d
PM		 3683 "item[,...]", "enable logging of specified items "
3684 "(use '-d help' for a list of items)"},
50171d42 3685 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
989b697d 3686 "logfile", "write logs to 'logfile' (default stderr)"},
fc9c5412
JS		 3687 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3688 "pagesize", "set the host page size to 'pagesize'"},
3689 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3690 "", "run in singlestep mode"},
3691 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3692 "", "log system calls"},
c5e4a5a9
MR		 3693 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
3694 "", "Seed for pseudo-random number generator"},
fc9c5412 3695 {"version", "QEMU_VERSION", false, handle_arg_version,
1386d4c0 3696 "", "display version information and exit"},
fc9c5412
JS		 3697 {NULL, NULL, false, NULL, NULL, NULL}
3698};
3699
3700static void usage(void)
3701{
42644cee 3702 const struct qemu_argument *arginfo;
fc9c5412
JS		 3703 int maxarglen;
3704 int maxenvlen;
3705
2e59915d
PB		 3706 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3707 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
fc9c5412
JS		 3708 "\n"
3709 "Options and associated environment variables:\n"
3710 "\n");
3711
63ec54d7
PM		 3712 /* Calculate column widths. We must always have at least enough space
3713 * for the column header.
3714 */
3715 maxarglen = strlen("Argument");
3716 maxenvlen = strlen("Env-variable");
fc9c5412
JS		 3717
3718 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
63ec54d7
PM		 3719 int arglen = strlen(arginfo->argv);
3720 if (arginfo->has_arg) {
3721 arglen += strlen(arginfo->example) + 1;
3722 }
fc9c5412
JS		 3723 if (strlen(arginfo->env) > maxenvlen) {
3724 maxenvlen = strlen(arginfo->env);
3725 }
63ec54d7
PM		 3726 if (arglen > maxarglen) {
3727 maxarglen = arglen;
fc9c5412
JS		 3728 }
3729 }
3730
63ec54d7
PM		 3731 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3732 maxenvlen, "Env-variable");
fc9c5412
JS		 3733
3734 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3735 if (arginfo->has_arg) {
3736 printf("-%s %-*s %-*s %s\n", arginfo->argv,
63ec54d7
PM		 3737 (int)(maxarglen - strlen(arginfo->argv) - 1),
3738 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
fc9c5412 3739 } else {
63ec54d7 3740 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
fc9c5412
JS		 3741 maxenvlen, arginfo->env,
3742 arginfo->help);
3743 }
3744 }
3745
3746 printf("\n"
3747 "Defaults:\n"
3748 "QEMU_LD_PREFIX = %s\n"
989b697d 3749 "QEMU_STACK_SIZE = %ld byte\n",
fc9c5412 3750 interp_prefix,
989b697d 3751 guest_stack_size);
fc9c5412
JS		 3752
3753 printf("\n"
3754 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3755 "QEMU_UNSET_ENV environment variables to set and unset\n"
3756 "environment variables for the target process.\n"
3757 "It is possible to provide several variables by separating them\n"
3758 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3759 "provide the -E and -U options multiple times.\n"
3760 "The following lines are equivalent:\n"
3761 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3762 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3763 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3764 "Note that if you provide several changes to a single variable\n"
3765 "the last change will stay in effect.\n");
3766
3767 exit(1);
3768}
3769
3770static int parse_args(int argc, char **argv)
3771{
3772 const char *r;
3773 int optind;
42644cee 3774 const struct qemu_argument *arginfo;
fc9c5412
JS		 3775
3776 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3777 if (arginfo->env == NULL) {
3778 continue;
3779 }
3780
3781 r = getenv(arginfo->env);
3782 if (r != NULL) {
3783 arginfo->handle_opt(r);
3784 }
3785 }
3786
3787 optind = 1;
3788 for (;;) {
3789 if (optind >= argc) {
3790 break;
3791 }
3792 r = argv[optind];
3793 if (r[0] != '-') {
3794 break;
3795 }
3796 optind++;
3797 r++;
3798 if (!strcmp(r, "-")) {
3799 break;
3800 }
3801
3802 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3803 if (!strcmp(r, arginfo->argv)) {
fc9c5412 3804 if (arginfo->has_arg) {
1386d4c0
PM		 3805 if (optind >= argc) {
3806 usage();
3807 }
3808 arginfo->handle_opt(argv[optind]);
fc9c5412 3809 optind++;
1386d4c0
PM		 3810 } else {
3811 arginfo->handle_opt(NULL);
fc9c5412 3812 }
fc9c5412
JS		 3813 break;
3814 }
3815 }
3816
3817 /* no option matched the current argv */
3818 if (arginfo->handle_opt == NULL) {
3819 usage();
3820 }
3821 }
3822
3823 if (optind >= argc) {
3824 usage();
3825 }
3826
3827 filename = argv[optind];
3828 exec_path = argv[optind];
3829
3830 return optind;
3831}
3832
902b3d5c 3833int main(int argc, char **argv, char **envp)
31e31b8a 3834{
01ffc75b 3835 struct target_pt_regs regs1, *regs = &regs1;
31e31b8a 3836 struct image_info info1, *info = &info1;
edf8e2af 3837 struct linux_binprm bprm;
48e15fc2 3838 TaskState *ts;
9349b4f9 3839 CPUArchState *env;
db6b81d4 3840 CPUState *cpu;
586314f2 3841 int optind;
04a6dfeb 3842 char **target_environ, **wrk;
7d8cec95
AJ		 3843 char **target_argv;
3844 int target_argc;
7d8cec95 3845 int i;
fd4d81dd 3846 int ret;
03cfd8fa 3847 int execfd;
b12b6a18 3848
ce008c1f
AF		 3849 module_call_init(MODULE_INIT_QOM);
3850
04a6dfeb
AJ		 3851 if ((envlist = envlist_create()) == NULL) {
3852 (void) fprintf(stderr, "Unable to allocate envlist\n");
3853 exit(1);
3854 }
3855
3856 /* add current environment into the list */
3857 for (wrk = environ; *wrk != NULL; wrk++) {
3858 (void) envlist_setenv(envlist, *wrk);
3859 }
3860
703e0e89
RH		 3861 /* Read the stack limit from the kernel. If it's "unlimited",
3862 then we can do little else besides use the default. */
3863 {
3864 struct rlimit lim;
3865 if (getrlimit(RLIMIT_STACK, &lim) == 0
81bbe906
TY		 3866 && lim.rlim_cur != RLIM_INFINITY
3867 && lim.rlim_cur == (target_long)lim.rlim_cur) {
703e0e89
RH		 3868 guest_stack_size = lim.rlim_cur;
3869 }
3870 }
3871
b1f9be31 3872 cpu_model = NULL;
b5ec5ce0 3873#if defined(cpudef_setup)
3874 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3875#endif
3876
c5e4a5a9
MR		 3877 srand(time(NULL));
3878
fc9c5412 3879 optind = parse_args(argc, argv);
586314f2 3880
31e31b8a 3881 /* Zero out regs */
01ffc75b 3882 memset(regs, 0, sizeof(struct target_pt_regs));
31e31b8a
FB		 3883
3884 /* Zero out image_info */
3885 memset(info, 0, sizeof(struct image_info));
3886
edf8e2af
MW		 3887 memset(&bprm, 0, sizeof (bprm));
3888
74cd30b8
FB		 3889 /* Scan interp_prefix dir for replacement files. */
3890 init_paths(interp_prefix);
3891
4a24a758
PM		 3892 init_qemu_uname_release();
3893
46027c07 3894 if (cpu_model == NULL) {
aaed909a 3895#if defined(TARGET_I386)
46027c07
FB		 3896#ifdef TARGET_X86_64
3897 cpu_model = "qemu64";
3898#else
3899 cpu_model = "qemu32";
3900#endif
aaed909a 3901#elif defined(TARGET_ARM)
088ab16c 3902 cpu_model = "any";
d2fbca94
GX		 3903#elif defined(TARGET_UNICORE32)
3904 cpu_model = "any";
aaed909a
FB		 3905#elif defined(TARGET_M68K)
3906 cpu_model = "any";
3907#elif defined(TARGET_SPARC)
3908#ifdef TARGET_SPARC64
3909 cpu_model = "TI UltraSparc II";
3910#else
3911 cpu_model = "Fujitsu MB86904";
46027c07 3912#endif
aaed909a
FB		 3913#elif defined(TARGET_MIPS)
3914#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
74797f40 3915 cpu_model = "5KEf";
aaed909a
FB		 3916#else
3917 cpu_model = "24Kf";
3918#endif
d962783e
JL		 3919#elif defined TARGET_OPENRISC
3920 cpu_model = "or1200";
aaed909a 3921#elif defined(TARGET_PPC)
a74029f6
RH		 3922# ifdef TARGET_PPC64
3923 cpu_model = "POWER7";
3924# else
aaed909a 3925 cpu_model = "750";
a74029f6 3926# endif
91c45a38
RH		 3927#elif defined TARGET_SH4
3928 cpu_model = TYPE_SH7785_CPU;
aaed909a
FB		 3929#else
3930 cpu_model = "any";
3931#endif
3932 }
d5ab9713 3933 tcg_exec_init(0);
83fb7adf
FB		 3934 /* NOTE: we need to init the CPU at this stage to get
3935 qemu_host_page_size */
2994fd96
EH		 3936 cpu = cpu_init(cpu_model);
3937 if (!cpu) {
aaed909a
FB		 3938 fprintf(stderr, "Unable to find CPU definition\n");
3939 exit(1);
3940 }
2994fd96 3941 env = cpu->env_ptr;
0ac46af3 3942 cpu_reset(cpu);
b55a37c9 3943
db6b81d4 3944 thread_cpu = cpu;
3b46e624 3945
b6741956
FB		 3946 if (getenv("QEMU_STRACE")) {
3947 do_strace = 1;
b92c47c1
TS		 3948 }
3949
c5e4a5a9
MR		 3950 if (getenv("QEMU_RAND_SEED")) {
3951 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
3952 }
3953
04a6dfeb
AJ		 3954 target_environ = envlist_to_environ(envlist, NULL);
3955 envlist_free(envlist);
b12b6a18 3956
379f6698
PB		 3957#if defined(CONFIG_USE_GUEST_BASE)
3958 /*
3959 * Now that page sizes are configured in cpu_init() we can do
3960 * proper page alignment for guest_base.
3961 */
3962 guest_base = HOST_PAGE_ALIGN(guest_base);
68a1c816 3963
806d1021
MI		 3964 if (reserved_va || have_guest_base) {
3965 guest_base = init_guest_space(guest_base, reserved_va, 0,
3966 have_guest_base);
3967 if (guest_base == (unsigned long)-1) {
097b8cb8
PM		 3968 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
3969 "space for use as guest address space (check your virtual "
3970 "memory ulimit setting or reserve less using -R option)\n",
3971 reserved_va);
68a1c816
PB		 3972 exit(1);
3973 }
97cc7560 3974
806d1021
MI		 3975 if (reserved_va) {
3976 mmap_next_start = reserved_va;
97cc7560
DDAG		 3977 }
3978 }
14f24e14 3979#endif /* CONFIG_USE_GUEST_BASE */
379f6698
PB		 3980
3981 /*
3982 * Read in mmap_min_addr kernel parameter. This value is used
3983 * When loading the ELF image to determine whether guest_base
14f24e14 3984 * is needed. It is also used in mmap_find_vma.
379f6698 3985 */
14f24e14 3986 {
379f6698
PB		 3987 FILE *fp;
3988
3989 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
3990 unsigned long tmp;
3991 if (fscanf(fp, "%lu", &tmp) == 1) {
3992 mmap_min_addr = tmp;
3993 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
3994 }
3995 fclose(fp);
3996 }
3997 }
379f6698 3998
7d8cec95
AJ		 3999 /*
4000 * Prepare copy of argv vector for target.
4001 */
4002 target_argc = argc - optind;
4003 target_argv = calloc(target_argc + 1, sizeof (char *));
4004 if (target_argv == NULL) {
4005 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4006 exit(1);
4007 }
4008
4009 /*
4010 * If argv0 is specified (using '-0' switch) we replace
4011 * argv[0] pointer with the given one.
4012 */
4013 i = 0;
4014 if (argv0 != NULL) {
4015 target_argv[i++] = strdup(argv0);
4016 }
4017 for (; i < target_argc; i++) {
4018 target_argv[i] = strdup(argv[optind + i]);
4019 }
4020 target_argv[target_argc] = NULL;
4021
7267c094 4022 ts = g_malloc0 (sizeof(TaskState));
edf8e2af
MW		 4023 init_task_state(ts);
4024 /* build Task State */
4025 ts->info = info;
4026 ts->bprm = &bprm;
0429a971 4027 cpu->opaque = ts;
edf8e2af
MW		 4028 task_settid(ts);
4029
0b959cf5
RH		 4030 execfd = qemu_getauxval(AT_EXECFD);
4031 if (execfd == 0) {
03cfd8fa 4032 execfd = open(filename, O_RDONLY);
0b959cf5
RH		 4033 if (execfd < 0) {
4034 printf("Error while loading %s: %s\n", filename, strerror(errno));
4035 _exit(1);
4036 }
03cfd8fa
LV		 4037 }
4038
4039 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
fd4d81dd
AP		 4040 info, &bprm);
4041 if (ret != 0) {
885c1d10 4042 printf("Error while loading %s: %s\n", filename, strerror(-ret));
b12b6a18
TS		 4043 _exit(1);
4044 }
4045
4046 for (wrk = target_environ; *wrk; wrk++) {
4047 free(*wrk);
31e31b8a 4048 }
3b46e624 4049
b12b6a18
TS		 4050 free(target_environ);
4051
2e77eac6 4052 if (qemu_log_enabled()) {
379f6698
PB		 4053#if defined(CONFIG_USE_GUEST_BASE)
4054 qemu_log("guest_base 0x%lx\n", guest_base);
4055#endif
2e77eac6
BS		 4056 log_page_dump();
4057
4058 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4059 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4060 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4061 info->start_code);
4062 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4063 info->start_data);
4064 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4065 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4066 info->start_stack);
4067 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4068 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4069 }
31e31b8a 4070
53a5960a 4071 target_set_brk(info->brk);
31e31b8a 4072 syscall_init();
66fb9763 4073 signal_init();
31e31b8a 4074
9002ec79
RH		 4075#if defined(CONFIG_USE_GUEST_BASE)
4076 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4077 generating the prologue until now so that the prologue can take
4078 the real value of GUEST_BASE into account. */
4079 tcg_prologue_init(&tcg_ctx);
4080#endif
4081
b346ff46 4082#if defined(TARGET_I386)
3802ce26 4083 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
b98dbc90 4084 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
0514ef2f 4085 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
1bde465e
FB		 4086 env->cr[4] |= CR4_OSFXSR_MASK;
4087 env->hflags |= HF_OSFXSR_MASK;
4088 }
d2fd1af7 4089#ifndef TARGET_ABI32
4dbc422b 4090 /* enable 64 bit mode if possible */
0514ef2f 4091 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4dbc422b
FB		 4092 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4093 exit(1);
4094 }
d2fd1af7 4095 env->cr[4] |= CR4_PAE_MASK;
4dbc422b 4096 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
d2fd1af7
FB		 4097 env->hflags |= HF_LMA_MASK;
4098#endif
1bde465e 4099
415e561f
FB		 4100 /* flags setup : we activate the IRQs by default as in user mode */
4101 env->eflags |= IF_MASK;
3b46e624 4102
6dbad63e 4103 /* linux register setup */
d2fd1af7 4104#ifndef TARGET_ABI32
84409ddb
JM		 4105 env->regs[R_EAX] = regs->rax;
4106 env->regs[R_EBX] = regs->rbx;
4107 env->regs[R_ECX] = regs->rcx;
4108 env->regs[R_EDX] = regs->rdx;
4109 env->regs[R_ESI] = regs->rsi;
4110 env->regs[R_EDI] = regs->rdi;
4111 env->regs[R_EBP] = regs->rbp;
4112 env->regs[R_ESP] = regs->rsp;
4113 env->eip = regs->rip;
4114#else
0ecfa993
FB		 4115 env->regs[R_EAX] = regs->eax;
4116 env->regs[R_EBX] = regs->ebx;
4117 env->regs[R_ECX] = regs->ecx;
4118 env->regs[R_EDX] = regs->edx;
4119 env->regs[R_ESI] = regs->esi;
4120 env->regs[R_EDI] = regs->edi;
4121 env->regs[R_EBP] = regs->ebp;
4122 env->regs[R_ESP] = regs->esp;
dab2ed99 4123 env->eip = regs->eip;
84409ddb 4124#endif
31e31b8a 4125
f4beb510 4126 /* linux interrupt setup */
e441570f
AZ		 4127#ifndef TARGET_ABI32
4128 env->idt.limit = 511;
4129#else
4130 env->idt.limit = 255;
4131#endif
4132 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4133 PROT_READ|PROT_WRITE,
4134 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4135 idt_table = g2h(env->idt.base);
f4beb510
FB		 4136 set_idt(0, 0);
4137 set_idt(1, 0);
4138 set_idt(2, 0);
4139 set_idt(3, 3);
4140 set_idt(4, 3);
ec95da6c 4141 set_idt(5, 0);
f4beb510
FB		 4142 set_idt(6, 0);
4143 set_idt(7, 0);
4144 set_idt(8, 0);
4145 set_idt(9, 0);
4146 set_idt(10, 0);
4147 set_idt(11, 0);
4148 set_idt(12, 0);
4149 set_idt(13, 0);
4150 set_idt(14, 0);
4151 set_idt(15, 0);
4152 set_idt(16, 0);
4153 set_idt(17, 0);
4154 set_idt(18, 0);
4155 set_idt(19, 0);
4156 set_idt(0x80, 3);
4157
6dbad63e 4158 /* linux segment setup */
8d18e893
FB		 4159 {
4160 uint64_t *gdt_table;
e441570f
AZ		 4161 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4162 PROT_READ|PROT_WRITE,
4163 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
8d18e893 4164 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
e441570f 4165 gdt_table = g2h(env->gdt.base);
d2fd1af7 4166#ifdef TARGET_ABI32
8d18e893
FB		 4167 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4168 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4169 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
d2fd1af7
FB		 4170#else
4171 /* 64 bit code segment */
4172 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4173 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4174 DESC_L_MASK |
4175 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4176#endif
8d18e893
FB		 4177 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4178 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4179 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4180 }
6dbad63e 4181 cpu_x86_load_seg(env, R_CS, __USER_CS);
d2fd1af7
FB		 4182 cpu_x86_load_seg(env, R_SS, __USER_DS);
4183#ifdef TARGET_ABI32
6dbad63e
FB		 4184 cpu_x86_load_seg(env, R_DS, __USER_DS);
4185 cpu_x86_load_seg(env, R_ES, __USER_DS);
6dbad63e
FB		 4186 cpu_x86_load_seg(env, R_FS, __USER_DS);
4187 cpu_x86_load_seg(env, R_GS, __USER_DS);
d6eb40f6
TS		 4188 /* This hack makes Wine work... */
4189 env->segs[R_FS].selector = 0;
d2fd1af7
FB		 4190#else
4191 cpu_x86_load_seg(env, R_DS, 0);
4192 cpu_x86_load_seg(env, R_ES, 0);
4193 cpu_x86_load_seg(env, R_FS, 0);
4194 cpu_x86_load_seg(env, R_GS, 0);
4195#endif
99033cae
AG		 4196#elif defined(TARGET_AARCH64)
4197 {
4198 int i;
4199
4200 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4201 fprintf(stderr,
4202 "The selected ARM CPU does not support 64 bit mode\n");
4203 exit(1);
4204 }
4205
4206 for (i = 0; i < 31; i++) {
4207 env->xregs[i] = regs->regs[i];
4208 }
4209 env->pc = regs->pc;
4210 env->xregs[31] = regs->sp;
4211 }
b346ff46
FB		 4212#elif defined(TARGET_ARM)
4213 {
4214 int i;
b5ff1b31 4215 cpsr_write(env, regs->uregs[16], 0xffffffff);
b346ff46
FB		 4216 for(i = 0; i < 16; i++) {
4217 env->regs[i] = regs->uregs[i];
4218 }
d8fd2954
PB		 4219 /* Enable BE8. */
4220 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4221 && (info->elf_flags & EF_ARM_BE8)) {
4222 env->bswap_code = 1;
4223 }
b346ff46 4224 }
d2fbca94
GX		 4225#elif defined(TARGET_UNICORE32)
4226 {
4227 int i;
4228 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4229 for (i = 0; i < 32; i++) {
4230 env->regs[i] = regs->uregs[i];
4231 }
4232 }
93ac68bc 4233#elif defined(TARGET_SPARC)
060366c5
FB		 4234 {
4235 int i;
4236 env->pc = regs->pc;
4237 env->npc = regs->npc;
4238 env->y = regs->y;
4239 for(i = 0; i < 8; i++)
4240 env->gregs[i] = regs->u_regs[i];
4241 for(i = 0; i < 8; i++)
4242 env->regwptr[i] = regs->u_regs[i + 8];
4243 }
67867308
FB		 4244#elif defined(TARGET_PPC)
4245 {
4246 int i;
3fc6c082 4247
0411a972
JM		 4248#if defined(TARGET_PPC64)
4249#if defined(TARGET_ABI32)
4250 env->msr &= ~((target_ulong)1 << MSR_SF);
e85e7c6e 4251#else
0411a972
JM		 4252 env->msr |= (target_ulong)1 << MSR_SF;
4253#endif
84409ddb 4254#endif
67867308
FB		 4255 env->nip = regs->nip;
4256 for(i = 0; i < 32; i++) {
4257 env->gpr[i] = regs->gpr[i];
4258 }
4259 }
e6e5906b
PB		 4260#elif defined(TARGET_M68K)
4261 {
e6e5906b
PB		 4262 env->pc = regs->pc;
4263 env->dregs[0] = regs->d0;
4264 env->dregs[1] = regs->d1;
4265 env->dregs[2] = regs->d2;
4266 env->dregs[3] = regs->d3;
4267 env->dregs[4] = regs->d4;
4268 env->dregs[5] = regs->d5;
4269 env->dregs[6] = regs->d6;
4270 env->dregs[7] = regs->d7;
4271 env->aregs[0] = regs->a0;
4272 env->aregs[1] = regs->a1;
4273 env->aregs[2] = regs->a2;
4274 env->aregs[3] = regs->a3;
4275 env->aregs[4] = regs->a4;
4276 env->aregs[5] = regs->a5;
4277 env->aregs[6] = regs->a6;
4278 env->aregs[7] = regs->usp;
4279 env->sr = regs->sr;
4280 ts->sim_syscalls = 1;
4281 }
b779e29e
EI		 4282#elif defined(TARGET_MICROBLAZE)
4283 {
4284 env->regs[0] = regs->r0;
4285 env->regs[1] = regs->r1;
4286 env->regs[2] = regs->r2;
4287 env->regs[3] = regs->r3;
4288 env->regs[4] = regs->r4;
4289 env->regs[5] = regs->r5;
4290 env->regs[6] = regs->r6;
4291 env->regs[7] = regs->r7;
4292 env->regs[8] = regs->r8;
4293 env->regs[9] = regs->r9;
4294 env->regs[10] = regs->r10;
4295 env->regs[11] = regs->r11;
4296 env->regs[12] = regs->r12;
4297 env->regs[13] = regs->r13;
4298 env->regs[14] = regs->r14;
4299 env->regs[15] = regs->r15;
4300 env->regs[16] = regs->r16;
4301 env->regs[17] = regs->r17;
4302 env->regs[18] = regs->r18;
4303 env->regs[19] = regs->r19;
4304 env->regs[20] = regs->r20;
4305 env->regs[21] = regs->r21;
4306 env->regs[22] = regs->r22;
4307 env->regs[23] = regs->r23;
4308 env->regs[24] = regs->r24;
4309 env->regs[25] = regs->r25;
4310 env->regs[26] = regs->r26;
4311 env->regs[27] = regs->r27;
4312 env->regs[28] = regs->r28;
4313 env->regs[29] = regs->r29;
4314 env->regs[30] = regs->r30;
4315 env->regs[31] = regs->r31;
4316 env->sregs[SR_PC] = regs->pc;
4317 }
048f6b4d
FB		 4318#elif defined(TARGET_MIPS)
4319 {
4320 int i;
4321
4322 for(i = 0; i < 32; i++) {
b5dc7732 4323 env->active_tc.gpr[i] = regs->regs[i];
048f6b4d 4324 }
0fddbbf2
NF		 4325 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4326 if (regs->cp0_epc & 1) {
4327 env->hflags |= MIPS_HFLAG_M16;
4328 }
048f6b4d 4329 }
d962783e
JL		 4330#elif defined(TARGET_OPENRISC)
4331 {
4332 int i;
4333
4334 for (i = 0; i < 32; i++) {
4335 env->gpr[i] = regs->gpr[i];
4336 }
4337
4338 env->sr = regs->sr;
4339 env->pc = regs->pc;
4340 }
fdf9b3e8
FB		 4341#elif defined(TARGET_SH4)
4342 {
4343 int i;
4344
4345 for(i = 0; i < 16; i++) {
4346 env->gregs[i] = regs->regs[i];
4347 }
4348 env->pc = regs->pc;
4349 }
7a3148a9
JM		 4350#elif defined(TARGET_ALPHA)
4351 {
4352 int i;
4353
4354 for(i = 0; i < 28; i++) {
992f48a0 4355 env->ir[i] = ((abi_ulong *)regs)[i];
7a3148a9 4356 }
dad081ee 4357 env->ir[IR_SP] = regs->usp;
7a3148a9 4358 env->pc = regs->pc;
7a3148a9 4359 }
48733d19
TS		 4360#elif defined(TARGET_CRIS)
4361 {
4362 env->regs[0] = regs->r0;
4363 env->regs[1] = regs->r1;
4364 env->regs[2] = regs->r2;
4365 env->regs[3] = regs->r3;
4366 env->regs[4] = regs->r4;
4367 env->regs[5] = regs->r5;
4368 env->regs[6] = regs->r6;
4369 env->regs[7] = regs->r7;
4370 env->regs[8] = regs->r8;
4371 env->regs[9] = regs->r9;
4372 env->regs[10] = regs->r10;
4373 env->regs[11] = regs->r11;
4374 env->regs[12] = regs->r12;
4375 env->regs[13] = regs->r13;
4376 env->regs[14] = info->start_stack;
4377 env->regs[15] = regs->acr;
4378 env->pc = regs->erp;
4379 }
a4c075f1
UH		 4380#elif defined(TARGET_S390X)
4381 {
4382 int i;
4383 for (i = 0; i < 16; i++) {
4384 env->regs[i] = regs->gprs[i];
4385 }
4386 env->psw.mask = regs->psw.mask;
4387 env->psw.addr = regs->psw.addr;
4388 }
b346ff46
FB		 4389#else
4390#error unsupported target CPU
4391#endif
31e31b8a 4392
d2fbca94 4393#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
a87295e8
PB		 4394 ts->stack_base = info->start_stack;
4395 ts->heap_base = info->brk;
4396 /* This will be filled in on the first SYS_HEAPINFO call. */
4397 ts->heap_limit = 0;
4398#endif
4399
74c33bed 4400 if (gdbstub_port) {
ff7a981a
PM		 4401 if (gdbserver_start(gdbstub_port) < 0) {
4402 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4403 gdbstub_port);
4404 exit(1);
4405 }
db6b81d4 4406 gdb_handlesig(cpu, 0);
1fddef4b 4407 }
1b6b029e
FB		 4408 cpu_loop(env);
4409 /* never exits */
31e31b8a
FB		 4410 return 0;
4411}
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