[mirror_qemu.git] / linux-user / mips / cpu_loop.c

/*
 *  qemu user cpu loop
 *
 *  Copyright (c) 2003-2008 Fabrice Bellard
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu.h"
#include "user-internals.h"
#include "cpu_loop-common.h"
#include "signal-common.h"
#include "elf.h"
#include "internal.h"
#include "fpu_helper.h"

# ifdef TARGET_ABI_MIPSO32
#  define MIPS_SYSCALL_NUMBER_UNUSED -1
static const int8_t mips_syscall_args[] = {
#include "syscall-args-o32.c.inc"
};
# endif /* O32 */

/* Break codes */
enum {
    BRK_OVERFLOW = 6,
    BRK_DIVZERO = 7
};

static void do_tr_or_bp(CPUMIPSState *env, unsigned int code, bool trap)
{
    target_ulong pc = env->active_tc.PC;

    switch (code) {
    case BRK_OVERFLOW:
        force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, pc);
        break;
    case BRK_DIVZERO:
        force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, pc);
        break;
    default:
        if (trap) {
            force_sig(TARGET_SIGTRAP);
        } else {
            force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, pc);
        }
        break;
    }
}

void cpu_loop(CPUMIPSState *env)
{
    CPUState *cs = env_cpu(env);
    int trapnr, si_code;
    unsigned int code;
    abi_long ret;
# ifdef TARGET_ABI_MIPSO32
    unsigned int syscall_num;
# endif

    for(;;) {
        cpu_exec_start(cs);
        trapnr = cpu_exec(cs);
        cpu_exec_end(cs);
        process_queued_cpu_work(cs);

        switch(trapnr) {
        case EXCP_SYSCALL:
            env->active_tc.PC += 4;
# ifdef TARGET_ABI_MIPSO32
            syscall_num = env->active_tc.gpr[2] - 4000;
            if (syscall_num >= sizeof(mips_syscall_args)) {
                /* syscall_num is larger that any defined for MIPS O32 */
                ret = -TARGET_ENOSYS;
            } else if (mips_syscall_args[syscall_num] ==
                       MIPS_SYSCALL_NUMBER_UNUSED) {
                /* syscall_num belongs to the range not defined for MIPS O32 */
                ret = -TARGET_ENOSYS;
            } else {
                /* syscall_num is valid */
                int nb_args;
                abi_ulong sp_reg;
                abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;

                nb_args = mips_syscall_args[syscall_num];
                sp_reg = env->active_tc.gpr[29];
                switch (nb_args) {
                /* these arguments are taken from the stack */
                case 8:
                    if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
                        goto done_syscall;
                    }
                    /* fall through */
                case 7:
                    if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
                        goto done_syscall;
                    }
                    /* fall through */
                case 6:
                    if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
                        goto done_syscall;
                    }
                    /* fall through */
                case 5:
                    if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
                        goto done_syscall;
                    }
                    /* fall through */
                default:
                    break;
                }
                ret = do_syscall(env, env->active_tc.gpr[2],
                                 env->active_tc.gpr[4],
                                 env->active_tc.gpr[5],
                                 env->active_tc.gpr[6],
                                 env->active_tc.gpr[7],
                                 arg5, arg6, arg7, arg8);
            }
done_syscall:
# else
            ret = do_syscall(env, env->active_tc.gpr[2],
                             env->active_tc.gpr[4], env->active_tc.gpr[5],
                             env->active_tc.gpr[6], env->active_tc.gpr[7],
                             env->active_tc.gpr[8], env->active_tc.gpr[9],
                             env->active_tc.gpr[10], env->active_tc.gpr[11]);
# endif /* O32 */
            if (ret == -QEMU_ERESTARTSYS) {
                env->active_tc.PC -= 4;
                break;
            }
            if (ret == -QEMU_ESIGRETURN) {
                /* Returning from a successful sigreturn syscall.
                   Avoid clobbering register state.  */
                break;
            }
            if ((abi_ulong)ret >= (abi_ulong)-1133) {
                env->active_tc.gpr[7] = 1; /* error flag */
                ret = -ret;
            } else {
                env->active_tc.gpr[7] = 0; /* error flag */
            }
            env->active_tc.gpr[2] = ret;
            break;
        case EXCP_CpU:
        case EXCP_RI:
        case EXCP_DSPDIS:
            force_sig(TARGET_SIGILL);
            break;
        case EXCP_INTERRUPT:
            /* just indicate that signals should be handled asap */
            break;
        case EXCP_DEBUG:
            force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT,
                            env->active_tc.PC);
            break;
        case EXCP_FPE:
            si_code = TARGET_FPE_FLTUNK;
            if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) {
                si_code = TARGET_FPE_FLTINV;
            } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_DIV0) {
                si_code = TARGET_FPE_FLTDIV;
            } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_OVERFLOW) {
                si_code = TARGET_FPE_FLTOVF;
            } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_UNDERFLOW) {
                si_code = TARGET_FPE_FLTUND;
            } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INEXACT) {
                si_code = TARGET_FPE_FLTRES;
            }
            force_sig_fault(TARGET_SIGFPE, si_code, env->active_tc.PC);
            break;

        /* The code below was inspired by the MIPS Linux kernel trap
         * handling code in arch/mips/kernel/traps.c.
         */
        case EXCP_BREAK:
            /*
             * As described in the original Linux kernel code, the below
             * checks on 'code' are to work around an old assembly bug.
             */
            code = env->error_code;
            if (code >= (1 << 10)) {
                code >>= 10;
            }
            do_tr_or_bp(env, code, false);
            break;
        case EXCP_TRAP:
            do_tr_or_bp(env, env->error_code, true);
            break;
        case EXCP_ATOMIC:
            cpu_exec_step_atomic(cs);
            break;
        default:
            EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
            abort();
        }
        process_pending_signals(env);
    }
}

void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
{
    CPUState *cpu = env_cpu(env);
    TaskState *ts = cpu->opaque;
    struct image_info *info = ts->info;
    int i;

    struct mode_req {
        bool single;
        bool soft;
        bool fr1;
        bool frdefault;
        bool fre;
    };

    static const struct mode_req fpu_reqs[] = {
        [MIPS_ABI_FP_ANY]    = { true,  true,  true,  true,  true  },
        [MIPS_ABI_FP_DOUBLE] = { false, false, false, true,  true  },
        [MIPS_ABI_FP_SINGLE] = { true,  false, false, false, false },
        [MIPS_ABI_FP_SOFT]   = { false, true,  false, false, false },
        [MIPS_ABI_FP_OLD_64] = { false, false, false, false, false },
        [MIPS_ABI_FP_XX]     = { false, false, true,  true,  true  },
        [MIPS_ABI_FP_64]     = { false, false, true,  false, false },
        [MIPS_ABI_FP_64A]    = { false, false, true,  false, true  }
    };

    /*
     * Mode requirements when .MIPS.abiflags is not present in the ELF.
     * Not present means that everything is acceptable except FR1.
     */
    static struct mode_req none_req = { true, true, false, true, true };

    struct mode_req prog_req;
    struct mode_req interp_req;

    for(i = 0; i < 32; i++) {
        env->active_tc.gpr[i] = regs->regs[i];
    }
    env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
    if (regs->cp0_epc & 1) {
        env->hflags |= MIPS_HFLAG_M16;
    }

#ifdef TARGET_ABI_MIPSO32
# define MAX_FP_ABI MIPS_ABI_FP_64A
#else
# define MAX_FP_ABI MIPS_ABI_FP_SOFT
#endif
     if ((info->fp_abi > MAX_FP_ABI && info->fp_abi != MIPS_ABI_FP_UNKNOWN)
        || (info->interp_fp_abi > MAX_FP_ABI &&
            info->interp_fp_abi != MIPS_ABI_FP_UNKNOWN)) {
        fprintf(stderr, "qemu: Unexpected FPU mode\n");
        exit(1);
    }

    prog_req = (info->fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req
                                            : fpu_reqs[info->fp_abi];
    interp_req = (info->interp_fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req
                                            : fpu_reqs[info->interp_fp_abi];

    prog_req.single &= interp_req.single;
    prog_req.soft &= interp_req.soft;
    prog_req.fr1 &= interp_req.fr1;
    prog_req.frdefault &= interp_req.frdefault;
    prog_req.fre &= interp_req.fre;

    bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS_R2 ||
                              env->insn_flags & ISA_MIPS_R6;

    if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) {
        env->CP0_Config5 |= (1 << CP0C5_FRE);
        if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
            env->hflags |= MIPS_HFLAG_FRE;
        }
    } else if ((prog_req.fr1 && prog_req.frdefault) ||
         (prog_req.single && !prog_req.frdefault)) {
        if ((env->active_fpu.fcr0 & (1 << FCR0_F64)
            && cpu_has_mips_r2_r6) || prog_req.fr1) {
            env->CP0_Status |= (1 << CP0St_FR);
            env->hflags |= MIPS_HFLAG_F64;
        }
    } else  if (!prog_req.fre && !prog_req.frdefault &&
          !prog_req.fr1 && !prog_req.single && !prog_req.soft) {
        fprintf(stderr, "qemu: Can't find a matching FPU mode\n");
        exit(1);
    }

    if (env->insn_flags & ISA_NANOMIPS32) {
        return;
    }
    if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
        ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
        if ((env->active_fpu.fcr31_rw_bitmask &
              (1 << FCR31_NAN2008)) == 0) {
            fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n");
            exit(1);
        }
        if ((info->elf_flags & EF_MIPS_NAN2008) != 0) {
            env->active_fpu.fcr31 |= (1 << FCR31_NAN2008);
        } else {
            env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008);
        }
        restore_snan_bit_mode(env);
    }
}
Commit	Line	Data
cd71c089 LV	1	/*
	2	* qemu user cpu loop
	3	*
	4	* Copyright (c) 2003-2008 Fabrice Bellard
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "qemu/osdep.h"
a8d25326	21	#include "qemu-common.h"
cd71c089	22	#include "qemu.h"
3b249d26	23	#include "user-internals.h"
cd71c089	24	#include "cpu_loop-common.h"
2113aed6	25	#include "signal-common.h"
58908ef6	26	#include "elf.h"
502700d0	27	#include "internal.h"
81ddae7c	28	#include "fpu_helper.h"
58908ef6 LV	29
58908ef6 LV	30	# ifdef TARGET_ABI_MIPSO32
8d6d4c1b	31	# define MIPS_SYSCALL_NUMBER_UNUSED -1
8d6d4c1b	32	static const int8_t mips_syscall_args[] = {
ac5d3c67	33	#include "syscall-args-o32.c.inc"
58908ef6	34	};
58908ef6 LV	35	# endif /* O32 */
58908ef6 LV	36
58908ef6 LV	37	/* Break codes */
	38	enum {
	39	BRK_OVERFLOW = 6,
	40	BRK_DIVZERO = 7
	41	};
	42
bf19bdb8	43	static void do_tr_or_bp(CPUMIPSState *env, unsigned int code, bool trap)
58908ef6	44	{
bf19bdb8	45	target_ulong pc = env->active_tc.PC;
58908ef6 LV	46
	47	switch (code) {
	48	case BRK_OVERFLOW:
bf19bdb8 RH	49	force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, pc);
bf19bdb8 RH	50	break;
58908ef6	51	case BRK_DIVZERO:
bf19bdb8	52	force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, pc);
58908ef6 LV	53	break;
58908ef6 LV	54	default:
bf19bdb8 RH	55	if (trap) {
	56	force_sig(TARGET_SIGTRAP);
	57	} else {
	58	force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, pc);
	59	}
58908ef6 LV	60	break;
58908ef6 LV	61	}
58908ef6 LV	62	}
	63
	64	void cpu_loop(CPUMIPSState *env)
	65	{
5a7330b3	66	CPUState *cs = env_cpu(env);
73c0aa6a	67	int trapnr, si_code;
6f3533dd	68	unsigned int code;
58908ef6 LV	69	abi_long ret;
	70	# ifdef TARGET_ABI_MIPSO32
	71	unsigned int syscall_num;
	72	# endif
	73
	74	for(;;) {
	75	cpu_exec_start(cs);
	76	trapnr = cpu_exec(cs);
	77	cpu_exec_end(cs);
	78	process_queued_cpu_work(cs);
	79
	80	switch(trapnr) {
	81	case EXCP_SYSCALL:
	82	env->active_tc.PC += 4;
	83	# ifdef TARGET_ABI_MIPSO32
	84	syscall_num = env->active_tc.gpr[2] - 4000;
	85	if (syscall_num >= sizeof(mips_syscall_args)) {
8d6d4c1b AM	86	/* syscall_num is larger that any defined for MIPS O32 */
	87	ret = -TARGET_ENOSYS;
	88	} else if (mips_syscall_args[syscall_num] ==
	89	MIPS_SYSCALL_NUMBER_UNUSED) {
	90	/* syscall_num belongs to the range not defined for MIPS O32 */
58908ef6 LV	91	ret = -TARGET_ENOSYS;
58908ef6 LV	92	} else {
8d6d4c1b	93	/* syscall_num is valid */
58908ef6 LV	94	int nb_args;
	95	abi_ulong sp_reg;
	96	abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
	97
	98	nb_args = mips_syscall_args[syscall_num];
	99	sp_reg = env->active_tc.gpr[29];
	100	switch (nb_args) {
	101	/* these arguments are taken from the stack */
	102	case 8:
	103	if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
	104	goto done_syscall;
	105	}
81966c18	106	/* fall through */
58908ef6 LV	107	case 7:
	108	if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
	109	goto done_syscall;
	110	}
81966c18	111	/* fall through */
58908ef6 LV	112	case 6:
	113	if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
	114	goto done_syscall;
	115	}
81966c18	116	/* fall through */
58908ef6 LV	117	case 5:
	118	if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
	119	goto done_syscall;
	120	}
81966c18	121	/* fall through */
58908ef6 LV	122	default:
	123	break;
	124	}
	125	ret = do_syscall(env, env->active_tc.gpr[2],
	126	env->active_tc.gpr[4],
	127	env->active_tc.gpr[5],
	128	env->active_tc.gpr[6],
	129	env->active_tc.gpr[7],
	130	arg5, arg6, arg7, arg8);
	131	}
	132	done_syscall:
	133	# else
	134	ret = do_syscall(env, env->active_tc.gpr[2],
	135	env->active_tc.gpr[4], env->active_tc.gpr[5],
	136	env->active_tc.gpr[6], env->active_tc.gpr[7],
	137	env->active_tc.gpr[8], env->active_tc.gpr[9],
	138	env->active_tc.gpr[10], env->active_tc.gpr[11]);
	139	# endif /* O32 */
af254a27	140	if (ret == -QEMU_ERESTARTSYS) {
58908ef6 LV	141	env->active_tc.PC -= 4;
	142	break;
	143	}
57a0c938	144	if (ret == -QEMU_ESIGRETURN) {
58908ef6 LV	145	/* Returning from a successful sigreturn syscall.
	146	Avoid clobbering register state. */
	147	break;
	148	}
	149	if ((abi_ulong)ret >= (abi_ulong)-1133) {
	150	env->active_tc.gpr[7] = 1; /* error flag */
	151	ret = -ret;
	152	} else {
	153	env->active_tc.gpr[7] = 0; /* error flag */
	154	}
	155	env->active_tc.gpr[2] = ret;
	156	break;
58908ef6 LV	157	case EXCP_CpU:
58908ef6 LV	158	case EXCP_RI:
73c0aa6a RH	159	case EXCP_DSPDIS:
73c0aa6a RH	160	force_sig(TARGET_SIGILL);
58908ef6 LV	161	break;
	162	case EXCP_INTERRUPT:
	163	/* just indicate that signals should be handled asap */
	164	break;
	165	case EXCP_DEBUG:
73c0aa6a RH	166	force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT,
73c0aa6a RH	167	env->active_tc.PC);
58908ef6	168	break;
64ce541c	169	case EXCP_FPE:
73c0aa6a	170	si_code = TARGET_FPE_FLTUNK;
64ce541c	171	if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) {
73c0aa6a	172	si_code = TARGET_FPE_FLTINV;
64ce541c	173	} else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_DIV0) {
73c0aa6a	174	si_code = TARGET_FPE_FLTDIV;
64ce541c	175	} else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_OVERFLOW) {
73c0aa6a	176	si_code = TARGET_FPE_FLTOVF;
64ce541c	177	} else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_UNDERFLOW) {
73c0aa6a	178	si_code = TARGET_FPE_FLTUND;
64ce541c	179	} else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INEXACT) {
73c0aa6a	180	si_code = TARGET_FPE_FLTRES;
64ce541c	181	}
73c0aa6a	182	force_sig_fault(TARGET_SIGFPE, si_code, env->active_tc.PC);
64ce541c	183	break;
73c0aa6a	184
58908ef6 LV	185	/* The code below was inspired by the MIPS Linux kernel trap
	186	* handling code in arch/mips/kernel/traps.c.
	187	*/
	188	case EXCP_BREAK:
6f3533dd RH	189	/*
	190	* As described in the original Linux kernel code, the below
	191	* checks on 'code' are to work around an old assembly bug.
	192	*/
	193	code = env->error_code;
	194	if (code >= (1 << 10)) {
	195	code >>= 10;
58908ef6	196	}
6f3533dd	197	do_tr_or_bp(env, code, false);
58908ef6 LV	198	break;
58908ef6 LV	199	case EXCP_TRAP:
0a3336f6	200	do_tr_or_bp(env, env->error_code, true);
58908ef6 LV	201	break;
	202	case EXCP_ATOMIC:
	203	cpu_exec_step_atomic(cs);
	204	break;
	205	default:
58908ef6 LV	206	EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
	207	abort();
	208	}
	209	process_pending_signals(env);
	210	}
	211	}
cd71c089 LV	212
	213	void target_cpu_copy_regs(CPUArchState env, struct target_pt_regs regs)
	214	{
29a0af61	215	CPUState *cpu = env_cpu(env);
58908ef6 LV	216	TaskState *ts = cpu->opaque;
	217	struct image_info *info = ts->info;
	218	int i;
	219
0c1bbedc SM	220	struct mode_req {
	221	bool single;
	222	bool soft;
	223	bool fr1;
	224	bool frdefault;
	225	bool fre;
	226	};
	227
	228	static const struct mode_req fpu_reqs[] = {
	229	[MIPS_ABI_FP_ANY] = { true, true, true, true, true },
	230	[MIPS_ABI_FP_DOUBLE] = { false, false, false, true, true },
	231	[MIPS_ABI_FP_SINGLE] = { true, false, false, false, false },
	232	[MIPS_ABI_FP_SOFT] = { false, true, false, false, false },
	233	[MIPS_ABI_FP_OLD_64] = { false, false, false, false, false },
	234	[MIPS_ABI_FP_XX] = { false, false, true, true, true },
	235	[MIPS_ABI_FP_64] = { false, false, true, false, false },
	236	[MIPS_ABI_FP_64A] = { false, false, true, false, true }
	237	};
	238
	239	/*
	240	* Mode requirements when .MIPS.abiflags is not present in the ELF.
	241	* Not present means that everything is acceptable except FR1.
	242	*/
	243	static struct mode_req none_req = { true, true, false, true, true };
	244
	245	struct mode_req prog_req;
	246	struct mode_req interp_req;
	247
58908ef6 LV	248	for(i = 0; i < 32; i++) {
	249	env->active_tc.gpr[i] = regs->regs[i];
	250	}
	251	env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
	252	if (regs->cp0_epc & 1) {
	253	env->hflags \|= MIPS_HFLAG_M16;
	254	}
0c1bbedc SM	255
	256	#ifdef TARGET_ABI_MIPSO32
	257	# define MAX_FP_ABI MIPS_ABI_FP_64A
	258	#else
	259	# define MAX_FP_ABI MIPS_ABI_FP_SOFT
	260	#endif
	261	if ((info->fp_abi > MAX_FP_ABI && info->fp_abi != MIPS_ABI_FP_UNKNOWN)
	262	\|\| (info->interp_fp_abi > MAX_FP_ABI &&
	263	info->interp_fp_abi != MIPS_ABI_FP_UNKNOWN)) {
	264	fprintf(stderr, "qemu: Unexpected FPU mode\n");
	265	exit(1);
	266	}
	267
	268	prog_req = (info->fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req
	269	: fpu_reqs[info->fp_abi];
	270	interp_req = (info->interp_fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req
	271	: fpu_reqs[info->interp_fp_abi];
	272
	273	prog_req.single &= interp_req.single;
	274	prog_req.soft &= interp_req.soft;
	275	prog_req.fr1 &= interp_req.fr1;
	276	prog_req.frdefault &= interp_req.frdefault;
	277	prog_req.fre &= interp_req.fre;
	278
7a47bae5	279	bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS_R2 \|\|
2e211e0a	280	env->insn_flags & ISA_MIPS_R6;
0c1bbedc SM	281
	282	if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) {
	283	env->CP0_Config5 \|= (1 << CP0C5_FRE);
	284	if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
	285	env->hflags \|= MIPS_HFLAG_FRE;
	286	}
	287	} else if ((prog_req.fr1 && prog_req.frdefault) \|\|
	288	(prog_req.single && !prog_req.frdefault)) {
	289	if ((env->active_fpu.fcr0 & (1 << FCR0_F64)
	290	&& cpu_has_mips_r2_r6) \|\| prog_req.fr1) {
	291	env->CP0_Status \|= (1 << CP0St_FR);
	292	env->hflags \|= MIPS_HFLAG_F64;
	293	}
	294	} else if (!prog_req.fre && !prog_req.frdefault &&
	295	!prog_req.fr1 && !prog_req.single && !prog_req.soft) {
	296	fprintf(stderr, "qemu: Can't find a matching FPU mode\n");
	297	exit(1);
	298	}
	299
722ac96c AM	300	if (env->insn_flags & ISA_NANOMIPS32) {
	301	return;
	302	}
58908ef6 LV	303	if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
	304	((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
	305	if ((env->active_fpu.fcr31_rw_bitmask &
	306	(1 << FCR31_NAN2008)) == 0) {
	307	fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n");
	308	exit(1);
	309	}
	310	if ((info->elf_flags & EF_MIPS_NAN2008) != 0) {
	311	env->active_fpu.fcr31 \|= (1 << FCR31_NAN2008);
	312	} else {
	313	env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008);
	314	}
	315	restore_snan_bit_mode(env);
	316	}
cd71c089	317	}