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linux-user/riscv: Use force_sig_fault
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CommitLineData
cd71c089
LV
1/*
2 * qemu user cpu loop
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
a8d25326 21#include "qemu-common.h"
cd71c089 22#include "qemu.h"
3b249d26 23#include "user-internals.h"
cd71c089 24#include "cpu_loop-common.h"
2113aed6 25#include "signal-common.h"
cd71c089 26
a5fd8ee1 27
ccb5f270
JA
28static int get_pgm_data_si_code(int dxc_code)
29{
30 switch (dxc_code) {
31 /* Non-simulated IEEE exceptions */
32 case 0x80:
33 return TARGET_FPE_FLTINV;
34 case 0x40:
35 return TARGET_FPE_FLTDIV;
36 case 0x20:
37 case 0x28:
38 case 0x2c:
39 return TARGET_FPE_FLTOVF;
40 case 0x10:
41 case 0x18:
42 case 0x1c:
43 return TARGET_FPE_FLTUND;
44 case 0x08:
45 case 0x0c:
46 return TARGET_FPE_FLTRES;
47 }
48 /*
49 * Non-IEEE and simulated IEEE:
50 * Includes compare-and-trap, quantum exception, etc.
51 * Simulated IEEE are included here to match current
52 * s390x linux kernel.
53 */
54 return 0;
55}
56
a5fd8ee1
LV
57void cpu_loop(CPUS390XState *env)
58{
dc79e928 59 CPUState *cs = env_cpu(env);
a5fd8ee1
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60 int trapnr, n, sig;
61 target_siginfo_t info;
62 target_ulong addr;
63 abi_long ret;
64
65 while (1) {
66 cpu_exec_start(cs);
67 trapnr = cpu_exec(cs);
68 cpu_exec_end(cs);
69 process_queued_cpu_work(cs);
70
71 switch (trapnr) {
72 case EXCP_INTERRUPT:
73 /* Just indicate that signals should be handled asap. */
74 break;
75
76 case EXCP_SVC:
77 n = env->int_svc_code;
78 if (!n) {
79 /* syscalls > 255 */
80 n = env->regs[1];
81 }
82 env->psw.addr += env->int_svc_ilen;
83 ret = do_syscall(env, n, env->regs[2], env->regs[3],
84 env->regs[4], env->regs[5],
85 env->regs[6], env->regs[7], 0, 0);
af254a27 86 if (ret == -QEMU_ERESTARTSYS) {
a5fd8ee1 87 env->psw.addr -= env->int_svc_ilen;
57a0c938 88 } else if (ret != -QEMU_ESIGRETURN) {
a5fd8ee1
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89 env->regs[2] = ret;
90 }
91 break;
92
93 case EXCP_DEBUG:
b10089a1
PM
94 sig = TARGET_SIGTRAP;
95 n = TARGET_TRAP_BRKPT;
54ba2161
IL
96 /*
97 * For SIGTRAP the PSW must point after the instruction, which it
98 * already does thanks to s390x_tr_tb_stop(). si_addr doesn't need
99 * to be filled.
100 */
101 addr = 0;
102 goto do_signal;
a5fd8ee1
LV
103 case EXCP_PGM:
104 n = env->int_pgm_code;
105 switch (n) {
106 case PGM_OPERATION:
107 case PGM_PRIVILEGED:
108 sig = TARGET_SIGILL;
109 n = TARGET_ILL_ILLOPC;
110 goto do_signal_pc;
111 case PGM_PROTECTION:
c8e7fef1
RH
112 force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_ACCERR,
113 env->__excp_addr);
114 break;
a5fd8ee1 115 case PGM_ADDRESSING:
c8e7fef1
RH
116 force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR,
117 env->__excp_addr);
118 break;
a5fd8ee1
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119 case PGM_EXECUTE:
120 case PGM_SPECIFICATION:
121 case PGM_SPECIAL_OP:
122 case PGM_OPERAND:
123 do_sigill_opn:
124 sig = TARGET_SIGILL;
125 n = TARGET_ILL_ILLOPN;
126 goto do_signal_pc;
127
128 case PGM_FIXPT_OVERFLOW:
129 sig = TARGET_SIGFPE;
130 n = TARGET_FPE_INTOVF;
131 goto do_signal_pc;
132 case PGM_FIXPT_DIVIDE:
133 sig = TARGET_SIGFPE;
134 n = TARGET_FPE_INTDIV;
135 goto do_signal_pc;
136
137 case PGM_DATA:
138 n = (env->fpc >> 8) & 0xff;
ccb5f270 139 if (n == 0) {
a5fd8ee1 140 goto do_sigill_opn;
a5fd8ee1
LV
141 }
142
ccb5f270
JA
143 sig = TARGET_SIGFPE;
144 n = get_pgm_data_si_code(n);
145 goto do_signal_pc;
146
a5fd8ee1
LV
147 default:
148 fprintf(stderr, "Unhandled program exception: %#x\n", n);
90c84c56 149 cpu_dump_state(cs, stderr, 0);
a5fd8ee1
LV
150 exit(EXIT_FAILURE);
151 }
152 break;
153
154 do_signal_pc:
155 addr = env->psw.addr;
54ba2161
IL
156 /*
157 * For SIGILL and SIGFPE the PSW must point after the instruction.
158 */
159 env->psw.addr += env->int_pgm_ilen;
a5fd8ee1
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160 do_signal:
161 info.si_signo = sig;
162 info.si_errno = 0;
163 info.si_code = n;
164 info._sifields._sigfault._addr = addr;
165 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
166 break;
167
168 case EXCP_ATOMIC:
169 cpu_exec_step_atomic(cs);
170 break;
171 default:
172 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
90c84c56 173 cpu_dump_state(cs, stderr, 0);
a5fd8ee1
LV
174 exit(EXIT_FAILURE);
175 }
176 process_pending_signals (env);
177 }
178}
179
cd71c089
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180void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
181{
a5fd8ee1
LV
182 int i;
183 for (i = 0; i < 16; i++) {
184 env->regs[i] = regs->gprs[i];
185 }
186 env->psw.mask = regs->psw.mask;
187 env->psw.addr = regs->psw.addr;
cd71c089 188}