[mirror_qemu.git] / linux-user / vm86.c

/*
 *  vm86 linux syscall support
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, see <http://www.gnu.org/licenses/>.
 */
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#include <string.h>
#include <errno.h>
#include <unistd.h>

#include "qemu.h"

//#define DEBUG_VM86

#ifdef DEBUG_VM86
#  define LOG_VM86(...) qemu_log(__VA_ARGS__);
#else
#  define LOG_VM86(...) do { } while (0)
#endif


#define set_flags(X,new,mask) \
((X) = ((X) & ~(mask)) | ((new) & (mask)))

#define SAFE_MASK	(0xDD5)
#define RETURN_MASK	(0xDFF)

static inline int is_revectored(int nr, struct target_revectored_struct *bitmap)
{
    return (((uint8_t *)bitmap)[nr >> 3] >> (nr & 7)) & 1;
}

static inline void vm_putw(CPUX86State *env, uint32_t segptr,
                           unsigned int reg16, unsigned int val)
{
    cpu_stw_data(env, segptr + (reg16 & 0xffff), val);
}

static inline void vm_putl(CPUX86State *env, uint32_t segptr,
                           unsigned int reg16, unsigned int val)
{
    cpu_stl_data(env, segptr + (reg16 & 0xffff), val);
}

static inline unsigned int vm_getb(CPUX86State *env,
                                   uint32_t segptr, unsigned int reg16)
{
    return cpu_ldub_data(env, segptr + (reg16 & 0xffff));
}

static inline unsigned int vm_getw(CPUX86State *env,
                                   uint32_t segptr, unsigned int reg16)
{
    return cpu_lduw_data(env, segptr + (reg16 & 0xffff));
}

static inline unsigned int vm_getl(CPUX86State *env,
                                   uint32_t segptr, unsigned int reg16)
{
    return cpu_ldl_data(env, segptr + (reg16 & 0xffff));
}

void save_v86_state(CPUX86State *env)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));
    TaskState *ts = cs->opaque;
    struct target_vm86plus_struct * target_v86;

    if (!lock_user_struct(VERIFY_WRITE, target_v86, ts->target_v86, 0))
        /* FIXME - should return an error */
        return;
    /* put the VM86 registers in the userspace register structure */
    target_v86->regs.eax = tswap32(env->regs[R_EAX]);
    target_v86->regs.ebx = tswap32(env->regs[R_EBX]);
    target_v86->regs.ecx = tswap32(env->regs[R_ECX]);
    target_v86->regs.edx = tswap32(env->regs[R_EDX]);
    target_v86->regs.esi = tswap32(env->regs[R_ESI]);
    target_v86->regs.edi = tswap32(env->regs[R_EDI]);
    target_v86->regs.ebp = tswap32(env->regs[R_EBP]);
    target_v86->regs.esp = tswap32(env->regs[R_ESP]);
    target_v86->regs.eip = tswap32(env->eip);
    target_v86->regs.cs = tswap16(env->segs[R_CS].selector);
    target_v86->regs.ss = tswap16(env->segs[R_SS].selector);
    target_v86->regs.ds = tswap16(env->segs[R_DS].selector);
    target_v86->regs.es = tswap16(env->segs[R_ES].selector);
    target_v86->regs.fs = tswap16(env->segs[R_FS].selector);
    target_v86->regs.gs = tswap16(env->segs[R_GS].selector);
    set_flags(env->eflags, ts->v86flags, VIF_MASK | ts->v86mask);
    target_v86->regs.eflags = tswap32(env->eflags);
    unlock_user_struct(target_v86, ts->target_v86, 1);
    LOG_VM86("save_v86_state: eflags=%08x cs:ip=%04x:%04x\n",
             env->eflags, env->segs[R_CS].selector, env->eip);

    /* restore 32 bit registers */
    env->regs[R_EAX] = ts->vm86_saved_regs.eax;
    env->regs[R_EBX] = ts->vm86_saved_regs.ebx;
    env->regs[R_ECX] = ts->vm86_saved_regs.ecx;
    env->regs[R_EDX] = ts->vm86_saved_regs.edx;
    env->regs[R_ESI] = ts->vm86_saved_regs.esi;
    env->regs[R_EDI] = ts->vm86_saved_regs.edi;
    env->regs[R_EBP] = ts->vm86_saved_regs.ebp;
    env->regs[R_ESP] = ts->vm86_saved_regs.esp;
    env->eflags = ts->vm86_saved_regs.eflags;
    env->eip = ts->vm86_saved_regs.eip;

    cpu_x86_load_seg(env, R_CS, ts->vm86_saved_regs.cs);
    cpu_x86_load_seg(env, R_SS, ts->vm86_saved_regs.ss);
    cpu_x86_load_seg(env, R_DS, ts->vm86_saved_regs.ds);
    cpu_x86_load_seg(env, R_ES, ts->vm86_saved_regs.es);
    cpu_x86_load_seg(env, R_FS, ts->vm86_saved_regs.fs);
    cpu_x86_load_seg(env, R_GS, ts->vm86_saved_regs.gs);
}

/* return from vm86 mode to 32 bit. The vm86() syscall will return
   'retval' */
static inline void return_to_32bit(CPUX86State *env, int retval)
{
    LOG_VM86("return_to_32bit: ret=0x%x\n", retval);
    save_v86_state(env);
    env->regs[R_EAX] = retval;
}

static inline int set_IF(CPUX86State *env)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));
    TaskState *ts = cs->opaque;

    ts->v86flags |= VIF_MASK;
    if (ts->v86flags & VIP_MASK) {
        return_to_32bit(env, TARGET_VM86_STI);
        return 1;
    }
    return 0;
}

static inline void clear_IF(CPUX86State *env)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));
    TaskState *ts = cs->opaque;

    ts->v86flags &= ~VIF_MASK;
}

static inline void clear_TF(CPUX86State *env)
{
    env->eflags &= ~TF_MASK;
}

static inline void clear_AC(CPUX86State *env)
{
    env->eflags &= ~AC_MASK;
}

static inline int set_vflags_long(unsigned long eflags, CPUX86State *env)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));
    TaskState *ts = cs->opaque;

    set_flags(ts->v86flags, eflags, ts->v86mask);
    set_flags(env->eflags, eflags, SAFE_MASK);
    if (eflags & IF_MASK)
        return set_IF(env);
    else
        clear_IF(env);
    return 0;
}

static inline int set_vflags_short(unsigned short flags, CPUX86State *env)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));
    TaskState *ts = cs->opaque;

    set_flags(ts->v86flags, flags, ts->v86mask & 0xffff);
    set_flags(env->eflags, flags, SAFE_MASK);
    if (flags & IF_MASK)
        return set_IF(env);
    else
        clear_IF(env);
    return 0;
}

static inline unsigned int get_vflags(CPUX86State *env)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));
    TaskState *ts = cs->opaque;
    unsigned int flags;

    flags = env->eflags & RETURN_MASK;
    if (ts->v86flags & VIF_MASK)
        flags |= IF_MASK;
    flags |= IOPL_MASK;
    return flags | (ts->v86flags & ts->v86mask);
}

#define ADD16(reg, val) reg = (reg & ~0xffff) | ((reg + (val)) & 0xffff)

/* handle VM86 interrupt (NOTE: the CPU core currently does not
   support TSS interrupt revectoring, so this code is always executed) */
static void do_int(CPUX86State *env, int intno)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));
    TaskState *ts = cs->opaque;
    uint32_t int_addr, segoffs, ssp;
    unsigned int sp;

    if (env->segs[R_CS].selector == TARGET_BIOSSEG)
        goto cannot_handle;
    if (is_revectored(intno, &ts->vm86plus.int_revectored))
        goto cannot_handle;
    if (intno == 0x21 && is_revectored((env->regs[R_EAX] >> 8) & 0xff,
                                       &ts->vm86plus.int21_revectored))
        goto cannot_handle;
    int_addr = (intno << 2);
    segoffs = cpu_ldl_data(env, int_addr);
    if ((segoffs >> 16) == TARGET_BIOSSEG)
        goto cannot_handle;
    LOG_VM86("VM86: emulating int 0x%x. CS:IP=%04x:%04x\n",
             intno, segoffs >> 16, segoffs & 0xffff);
    /* save old state */
    ssp = env->segs[R_SS].selector << 4;
    sp = env->regs[R_ESP] & 0xffff;
    vm_putw(env, ssp, sp - 2, get_vflags(env));
    vm_putw(env, ssp, sp - 4, env->segs[R_CS].selector);
    vm_putw(env, ssp, sp - 6, env->eip);
    ADD16(env->regs[R_ESP], -6);
    /* goto interrupt handler */
    env->eip = segoffs & 0xffff;
    cpu_x86_load_seg(env, R_CS, segoffs >> 16);
    clear_TF(env);
    clear_IF(env);
    clear_AC(env);
    return;
 cannot_handle:
    LOG_VM86("VM86: return to 32 bits int 0x%x\n", intno);
    return_to_32bit(env, TARGET_VM86_INTx | (intno << 8));
}

void handle_vm86_trap(CPUX86State *env, int trapno)
{
    if (trapno == 1 || trapno == 3) {
        return_to_32bit(env, TARGET_VM86_TRAP + (trapno << 8));
    } else {
        do_int(env, trapno);
    }
}

#define CHECK_IF_IN_TRAP() \
      if ((ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) && \
          (ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_TFpendig)) \
		newflags |= TF_MASK

#define VM86_FAULT_RETURN \
        if ((ts->vm86plus.vm86plus.flags & TARGET_force_return_for_pic) && \
            (ts->v86flags & (IF_MASK | VIF_MASK))) \
            return_to_32bit(env, TARGET_VM86_PICRETURN); \
        return

void handle_vm86_fault(CPUX86State *env)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));
    TaskState *ts = cs->opaque;
    uint32_t csp, ssp;
    unsigned int ip, sp, newflags, newip, newcs, opcode, intno;
    int data32, pref_done;

    csp = env->segs[R_CS].selector << 4;
    ip = env->eip & 0xffff;

    ssp = env->segs[R_SS].selector << 4;
    sp = env->regs[R_ESP] & 0xffff;

    LOG_VM86("VM86 exception %04x:%08x\n",
             env->segs[R_CS].selector, env->eip);

    data32 = 0;
    pref_done = 0;
    do {
        opcode = vm_getb(env, csp, ip);
        ADD16(ip, 1);
        switch (opcode) {
        case 0x66:      /* 32-bit data */     data32=1; break;
        case 0x67:      /* 32-bit address */  break;
        case 0x2e:      /* CS */              break;
        case 0x3e:      /* DS */              break;
        case 0x26:      /* ES */              break;
        case 0x36:      /* SS */              break;
        case 0x65:      /* GS */              break;
        case 0x64:      /* FS */              break;
        case 0xf2:      /* repnz */	      break;
        case 0xf3:      /* rep */             break;
        default: pref_done = 1;
        }
    } while (!pref_done);

    /* VM86 mode */
    switch(opcode) {
    case 0x9c: /* pushf */
        if (data32) {
            vm_putl(env, ssp, sp - 4, get_vflags(env));
            ADD16(env->regs[R_ESP], -4);
        } else {
            vm_putw(env, ssp, sp - 2, get_vflags(env));
            ADD16(env->regs[R_ESP], -2);
        }
        env->eip = ip;
        VM86_FAULT_RETURN;

    case 0x9d: /* popf */
        if (data32) {
            newflags = vm_getl(env, ssp, sp);
            ADD16(env->regs[R_ESP], 4);
        } else {
            newflags = vm_getw(env, ssp, sp);
            ADD16(env->regs[R_ESP], 2);
        }
        env->eip = ip;
        CHECK_IF_IN_TRAP();
        if (data32) {
            if (set_vflags_long(newflags, env))
                return;
        } else {
            if (set_vflags_short(newflags, env))
                return;
        }
        VM86_FAULT_RETURN;

    case 0xcd: /* int */
        intno = vm_getb(env, csp, ip);
        ADD16(ip, 1);
        env->eip = ip;
        if (ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) {
            if ( (ts->vm86plus.vm86plus.vm86dbg_intxxtab[intno >> 3] >>
                  (intno &7)) & 1) {
                return_to_32bit(env, TARGET_VM86_INTx + (intno << 8));
                return;
            }
        }
        do_int(env, intno);
        break;

    case 0xcf: /* iret */
        if (data32) {
            newip = vm_getl(env, ssp, sp) & 0xffff;
            newcs = vm_getl(env, ssp, sp + 4) & 0xffff;
            newflags = vm_getl(env, ssp, sp + 8);
            ADD16(env->regs[R_ESP], 12);
        } else {
            newip = vm_getw(env, ssp, sp);
            newcs = vm_getw(env, ssp, sp + 2);
            newflags = vm_getw(env, ssp, sp + 4);
            ADD16(env->regs[R_ESP], 6);
        }
        env->eip = newip;
        cpu_x86_load_seg(env, R_CS, newcs);
        CHECK_IF_IN_TRAP();
        if (data32) {
            if (set_vflags_long(newflags, env))
                return;
        } else {
            if (set_vflags_short(newflags, env))
                return;
        }
        VM86_FAULT_RETURN;

    case 0xfa: /* cli */
        env->eip = ip;
        clear_IF(env);
        VM86_FAULT_RETURN;

    case 0xfb: /* sti */
        env->eip = ip;
        if (set_IF(env))
            return;
        VM86_FAULT_RETURN;

    default:
        /* real VM86 GPF exception */
        return_to_32bit(env, TARGET_VM86_UNKNOWN);
        break;
    }
}

int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));
    TaskState *ts = cs->opaque;
    struct target_vm86plus_struct * target_v86;
    int ret;

    switch (subfunction) {
    case TARGET_VM86_REQUEST_IRQ:
    case TARGET_VM86_FREE_IRQ:
    case TARGET_VM86_GET_IRQ_BITS:
    case TARGET_VM86_GET_AND_RESET_IRQ:
        gemu_log("qemu: unsupported vm86 subfunction (%ld)\n", subfunction);
        ret = -TARGET_EINVAL;
        goto out;
    case TARGET_VM86_PLUS_INSTALL_CHECK:
        /* NOTE: on old vm86 stuff this will return the error
           from verify_area(), because the subfunction is
           interpreted as (invalid) address to vm86_struct.
           So the installation check works.
            */
        ret = 0;
        goto out;
    }

    /* save current CPU regs */
    ts->vm86_saved_regs.eax = 0; /* default vm86 syscall return code */
    ts->vm86_saved_regs.ebx = env->regs[R_EBX];
    ts->vm86_saved_regs.ecx = env->regs[R_ECX];
    ts->vm86_saved_regs.edx = env->regs[R_EDX];
    ts->vm86_saved_regs.esi = env->regs[R_ESI];
    ts->vm86_saved_regs.edi = env->regs[R_EDI];
    ts->vm86_saved_regs.ebp = env->regs[R_EBP];
    ts->vm86_saved_regs.esp = env->regs[R_ESP];
    ts->vm86_saved_regs.eflags = env->eflags;
    ts->vm86_saved_regs.eip  = env->eip;
    ts->vm86_saved_regs.cs = env->segs[R_CS].selector;
    ts->vm86_saved_regs.ss = env->segs[R_SS].selector;
    ts->vm86_saved_regs.ds = env->segs[R_DS].selector;
    ts->vm86_saved_regs.es = env->segs[R_ES].selector;
    ts->vm86_saved_regs.fs = env->segs[R_FS].selector;
    ts->vm86_saved_regs.gs = env->segs[R_GS].selector;

    ts->target_v86 = vm86_addr;
    if (!lock_user_struct(VERIFY_READ, target_v86, vm86_addr, 1))
        return -TARGET_EFAULT;
    /* build vm86 CPU state */
    ts->v86flags = tswap32(target_v86->regs.eflags);
    env->eflags = (env->eflags & ~SAFE_MASK) |
        (tswap32(target_v86->regs.eflags) & SAFE_MASK) | VM_MASK;

    ts->vm86plus.cpu_type = tswapal(target_v86->cpu_type);
    switch (ts->vm86plus.cpu_type) {
    case TARGET_CPU_286:
        ts->v86mask = 0;
        break;
    case TARGET_CPU_386:
        ts->v86mask = NT_MASK | IOPL_MASK;
        break;
    case TARGET_CPU_486:
        ts->v86mask = AC_MASK | NT_MASK | IOPL_MASK;
        break;
    default:
        ts->v86mask = ID_MASK | AC_MASK | NT_MASK | IOPL_MASK;
        break;
    }

    env->regs[R_EBX] = tswap32(target_v86->regs.ebx);
    env->regs[R_ECX] = tswap32(target_v86->regs.ecx);
    env->regs[R_EDX] = tswap32(target_v86->regs.edx);
    env->regs[R_ESI] = tswap32(target_v86->regs.esi);
    env->regs[R_EDI] = tswap32(target_v86->regs.edi);
    env->regs[R_EBP] = tswap32(target_v86->regs.ebp);
    env->regs[R_ESP] = tswap32(target_v86->regs.esp);
    env->eip = tswap32(target_v86->regs.eip);
    cpu_x86_load_seg(env, R_CS, tswap16(target_v86->regs.cs));
    cpu_x86_load_seg(env, R_SS, tswap16(target_v86->regs.ss));
    cpu_x86_load_seg(env, R_DS, tswap16(target_v86->regs.ds));
    cpu_x86_load_seg(env, R_ES, tswap16(target_v86->regs.es));
    cpu_x86_load_seg(env, R_FS, tswap16(target_v86->regs.fs));
    cpu_x86_load_seg(env, R_GS, tswap16(target_v86->regs.gs));
    ret = tswap32(target_v86->regs.eax); /* eax will be restored at
                                            the end of the syscall */
    memcpy(&ts->vm86plus.int_revectored,
           &target_v86->int_revectored, 32);
    memcpy(&ts->vm86plus.int21_revectored,
           &target_v86->int21_revectored, 32);
    ts->vm86plus.vm86plus.flags = tswapal(target_v86->vm86plus.flags);
    memcpy(&ts->vm86plus.vm86plus.vm86dbg_intxxtab,
           target_v86->vm86plus.vm86dbg_intxxtab, 32);
    unlock_user_struct(target_v86, vm86_addr, 0);

    LOG_VM86("do_vm86: cs:ip=%04x:%04x\n",
             env->segs[R_CS].selector, env->eip);
    /* now the virtual CPU is ready for vm86 execution ! */
 out:
    return ret;
}
Commit	Line	Data
46ddf551 FB	1	/*
46ddf551 FB	2	* vm86 linux syscall support
5fafdf24	3	*
46ddf551 FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
8167ee88	17	* along with this program; if not, see <http://www.gnu.org/licenses/>.
46ddf551 FB	18	*/
	19	#include <stdlib.h>
	20	#include <stdio.h>
	21	#include <stdarg.h>
	22	#include <string.h>
	23	#include <errno.h>
	24	#include <unistd.h>
	25
	26	#include "qemu.h"
	27
	28	//#define DEBUG_VM86
	29
d12d51d5	30	#ifdef DEBUG_VM86
93fcfe39	31	# define LOG_VM86(...) qemu_log(__VA_ARGS__);
d12d51d5 AL	32	#else
	33	# define LOG_VM86(...) do { } while (0)
	34	#endif
	35
	36
46ddf551 FB	37	#define set_flags(X,new,mask) \
	38	((X) = ((X) & ~(mask)) \| ((new) & (mask)))
	39
	40	#define SAFE_MASK (0xDD5)
	41	#define RETURN_MASK (0xDFF)
	42
	43	static inline int is_revectored(int nr, struct target_revectored_struct *bitmap)
	44	{
b333af06	45	return (((uint8_t *)bitmap)[nr >> 3] >> (nr & 7)) & 1;
46ddf551 FB	46	}
46ddf551 FB	47
5899d6d0 PM	48	static inline void vm_putw(CPUX86State *env, uint32_t segptr,
5899d6d0 PM	49	unsigned int reg16, unsigned int val)
46ddf551	50	{
5899d6d0	51	cpu_stw_data(env, segptr + (reg16 & 0xffff), val);
46ddf551 FB	52	}
46ddf551 FB	53
5899d6d0 PM	54	static inline void vm_putl(CPUX86State *env, uint32_t segptr,
5899d6d0 PM	55	unsigned int reg16, unsigned int val)
46ddf551	56	{
5899d6d0	57	cpu_stl_data(env, segptr + (reg16 & 0xffff), val);
46ddf551 FB	58	}
46ddf551 FB	59
5899d6d0 PM	60	static inline unsigned int vm_getb(CPUX86State *env,
5899d6d0 PM	61	uint32_t segptr, unsigned int reg16)
1455bf48	62	{
5899d6d0	63	return cpu_ldub_data(env, segptr + (reg16 & 0xffff));
1455bf48 FB	64	}
1455bf48 FB	65
5899d6d0 PM	66	static inline unsigned int vm_getw(CPUX86State *env,
5899d6d0 PM	67	uint32_t segptr, unsigned int reg16)
46ddf551	68	{
5899d6d0	69	return cpu_lduw_data(env, segptr + (reg16 & 0xffff));
46ddf551 FB	70	}
46ddf551 FB	71
5899d6d0 PM	72	static inline unsigned int vm_getl(CPUX86State *env,
5899d6d0 PM	73	uint32_t segptr, unsigned int reg16)
46ddf551	74	{
5899d6d0	75	return cpu_ldl_data(env, segptr + (reg16 & 0xffff));
46ddf551 FB	76	}
	77
	78	void save_v86_state(CPUX86State *env)
	79	{
0429a971 AF	80	CPUState *cs = CPU(x86_env_get_cpu(env));
0429a971 AF	81	TaskState *ts = cs->opaque;
53a5960a	82	struct target_vm86plus_struct * target_v86;
46ddf551	83
579a97f7 FB	84	if (!lock_user_struct(VERIFY_WRITE, target_v86, ts->target_v86, 0))
	85	/* FIXME - should return an error */
	86	return;
46ddf551	87	/* put the VM86 registers in the userspace register structure */
53a5960a PB	88	target_v86->regs.eax = tswap32(env->regs[R_EAX]);
	89	target_v86->regs.ebx = tswap32(env->regs[R_EBX]);
	90	target_v86->regs.ecx = tswap32(env->regs[R_ECX]);
	91	target_v86->regs.edx = tswap32(env->regs[R_EDX]);
	92	target_v86->regs.esi = tswap32(env->regs[R_ESI]);
	93	target_v86->regs.edi = tswap32(env->regs[R_EDI]);
	94	target_v86->regs.ebp = tswap32(env->regs[R_EBP]);
	95	target_v86->regs.esp = tswap32(env->regs[R_ESP]);
	96	target_v86->regs.eip = tswap32(env->eip);
	97	target_v86->regs.cs = tswap16(env->segs[R_CS].selector);
	98	target_v86->regs.ss = tswap16(env->segs[R_SS].selector);
	99	target_v86->regs.ds = tswap16(env->segs[R_DS].selector);
	100	target_v86->regs.es = tswap16(env->segs[R_ES].selector);
	101	target_v86->regs.fs = tswap16(env->segs[R_FS].selector);
	102	target_v86->regs.gs = tswap16(env->segs[R_GS].selector);
46ddf551	103	set_flags(env->eflags, ts->v86flags, VIF_MASK \| ts->v86mask);
53a5960a PB	104	target_v86->regs.eflags = tswap32(env->eflags);
53a5960a PB	105	unlock_user_struct(target_v86, ts->target_v86, 1);
d12d51d5 AL	106	LOG_VM86("save_v86_state: eflags=%08x cs:ip=%04x:%04x\n",
d12d51d5 AL	107	env->eflags, env->segs[R_CS].selector, env->eip);
46ddf551 FB	108
	109	/* restore 32 bit registers */
	110	env->regs[R_EAX] = ts->vm86_saved_regs.eax;
	111	env->regs[R_EBX] = ts->vm86_saved_regs.ebx;
	112	env->regs[R_ECX] = ts->vm86_saved_regs.ecx;
	113	env->regs[R_EDX] = ts->vm86_saved_regs.edx;
	114	env->regs[R_ESI] = ts->vm86_saved_regs.esi;
	115	env->regs[R_EDI] = ts->vm86_saved_regs.edi;
	116	env->regs[R_EBP] = ts->vm86_saved_regs.ebp;
	117	env->regs[R_ESP] = ts->vm86_saved_regs.esp;
	118	env->eflags = ts->vm86_saved_regs.eflags;
	119	env->eip = ts->vm86_saved_regs.eip;
	120
	121	cpu_x86_load_seg(env, R_CS, ts->vm86_saved_regs.cs);
	122	cpu_x86_load_seg(env, R_SS, ts->vm86_saved_regs.ss);
	123	cpu_x86_load_seg(env, R_DS, ts->vm86_saved_regs.ds);
	124	cpu_x86_load_seg(env, R_ES, ts->vm86_saved_regs.es);
	125	cpu_x86_load_seg(env, R_FS, ts->vm86_saved_regs.fs);
	126	cpu_x86_load_seg(env, R_GS, ts->vm86_saved_regs.gs);
	127	}
	128
	129	/* return from vm86 mode to 32 bit. The vm86() syscall will return
	130	'retval' */
	131	static inline void return_to_32bit(CPUX86State *env, int retval)
	132	{
d12d51d5	133	LOG_VM86("return_to_32bit: ret=0x%x\n", retval);
46ddf551 FB	134	save_v86_state(env);
	135	env->regs[R_EAX] = retval;
	136	}
	137
	138	static inline int set_IF(CPUX86State *env)
	139	{
0429a971 AF	140	CPUState *cs = CPU(x86_env_get_cpu(env));
0429a971 AF	141	TaskState *ts = cs->opaque;
3b46e624	142
46ddf551 FB	143	ts->v86flags \|= VIF_MASK;
	144	if (ts->v86flags & VIP_MASK) {
	145	return_to_32bit(env, TARGET_VM86_STI);
	146	return 1;
	147	}
	148	return 0;
	149	}
	150
	151	static inline void clear_IF(CPUX86State *env)
	152	{
0429a971 AF	153	CPUState *cs = CPU(x86_env_get_cpu(env));
0429a971 AF	154	TaskState *ts = cs->opaque;
46ddf551 FB	155
	156	ts->v86flags &= ~VIF_MASK;
	157	}
	158
	159	static inline void clear_TF(CPUX86State *env)
	160	{
	161	env->eflags &= ~TF_MASK;
	162	}
	163
226c9132 FB	164	static inline void clear_AC(CPUX86State *env)
	165	{
	166	env->eflags &= ~AC_MASK;
	167	}
	168
46ddf551 FB	169	static inline int set_vflags_long(unsigned long eflags, CPUX86State *env)
46ddf551 FB	170	{
0429a971 AF	171	CPUState *cs = CPU(x86_env_get_cpu(env));
0429a971 AF	172	TaskState *ts = cs->opaque;
46ddf551 FB	173
	174	set_flags(ts->v86flags, eflags, ts->v86mask);
	175	set_flags(env->eflags, eflags, SAFE_MASK);
	176	if (eflags & IF_MASK)
	177	return set_IF(env);
226c9132 FB	178	else
226c9132 FB	179	clear_IF(env);
46ddf551 FB	180	return 0;
	181	}
	182
	183	static inline int set_vflags_short(unsigned short flags, CPUX86State *env)
	184	{
0429a971 AF	185	CPUState *cs = CPU(x86_env_get_cpu(env));
0429a971 AF	186	TaskState *ts = cs->opaque;
46ddf551 FB	187
	188	set_flags(ts->v86flags, flags, ts->v86mask & 0xffff);
	189	set_flags(env->eflags, flags, SAFE_MASK);
	190	if (flags & IF_MASK)
	191	return set_IF(env);
226c9132 FB	192	else
226c9132 FB	193	clear_IF(env);
46ddf551 FB	194	return 0;
	195	}
	196
	197	static inline unsigned int get_vflags(CPUX86State *env)
	198	{
0429a971 AF	199	CPUState *cs = CPU(x86_env_get_cpu(env));
0429a971 AF	200	TaskState *ts = cs->opaque;
46ddf551 FB	201	unsigned int flags;
	202
	203	flags = env->eflags & RETURN_MASK;
	204	if (ts->v86flags & VIF_MASK)
	205	flags \|= IF_MASK;
c05bab77	206	flags \|= IOPL_MASK;
46ddf551 FB	207	return flags \| (ts->v86flags & ts->v86mask);
	208	}
	209
	210	#define ADD16(reg, val) reg = (reg & ~0xffff) \| ((reg + (val)) & 0xffff)
	211
	212	/* handle VM86 interrupt (NOTE: the CPU core currently does not
	213	support TSS interrupt revectoring, so this code is always executed) */
447db213	214	static void do_int(CPUX86State *env, int intno)
46ddf551	215	{
0429a971 AF	216	CPUState *cs = CPU(x86_env_get_cpu(env));
0429a971 AF	217	TaskState *ts = cs->opaque;
1455bf48	218	uint32_t int_addr, segoffs, ssp;
46ddf551 FB	219	unsigned int sp;
46ddf551 FB	220
c05bab77	221	if (env->segs[R_CS].selector == TARGET_BIOSSEG)
46ddf551	222	goto cannot_handle;
b333af06	223	if (is_revectored(intno, &ts->vm86plus.int_revectored))
46ddf551	224	goto cannot_handle;
5fafdf24	225	if (intno == 0x21 && is_revectored((env->regs[R_EAX] >> 8) & 0xff,
b333af06	226	&ts->vm86plus.int21_revectored))
46ddf551	227	goto cannot_handle;
1455bf48	228	int_addr = (intno << 2);
5899d6d0	229	segoffs = cpu_ldl_data(env, int_addr);
46ddf551 FB	230	if ((segoffs >> 16) == TARGET_BIOSSEG)
46ddf551 FB	231	goto cannot_handle;
d12d51d5 AL	232	LOG_VM86("VM86: emulating int 0x%x. CS:IP=%04x:%04x\n",
d12d51d5 AL	233	intno, segoffs >> 16, segoffs & 0xffff);
46ddf551	234	/* save old state */
1455bf48	235	ssp = env->segs[R_SS].selector << 4;
46ddf551	236	sp = env->regs[R_ESP] & 0xffff;
5899d6d0 PM	237	vm_putw(env, ssp, sp - 2, get_vflags(env));
	238	vm_putw(env, ssp, sp - 4, env->segs[R_CS].selector);
	239	vm_putw(env, ssp, sp - 6, env->eip);
46ddf551 FB	240	ADD16(env->regs[R_ESP], -6);
	241	/* goto interrupt handler */
	242	env->eip = segoffs & 0xffff;
	243	cpu_x86_load_seg(env, R_CS, segoffs >> 16);
	244	clear_TF(env);
	245	clear_IF(env);
226c9132	246	clear_AC(env);
46ddf551 FB	247	return;
46ddf551 FB	248	cannot_handle:
d12d51d5	249	LOG_VM86("VM86: return to 32 bits int 0x%x\n", intno);
46ddf551 FB	250	return_to_32bit(env, TARGET_VM86_INTx \| (intno << 8));
	251	}
	252
447db213 FB	253	void handle_vm86_trap(CPUX86State *env, int trapno)
	254	{
	255	if (trapno == 1 \|\| trapno == 3) {
	256	return_to_32bit(env, TARGET_VM86_TRAP + (trapno << 8));
	257	} else {
	258	do_int(env, trapno);
	259	}
	260	}
	261
b333af06 FB	262	#define CHECK_IF_IN_TRAP() \
	263	if ((ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) && \
	264	(ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_TFpendig)) \
	265	newflags \|= TF_MASK
46ddf551 FB	266
46ddf551 FB	267	#define VM86_FAULT_RETURN \
b333af06	268	if ((ts->vm86plus.vm86plus.flags & TARGET_force_return_for_pic) && \
46ddf551 FB	269	(ts->v86flags & (IF_MASK \| VIF_MASK))) \
	270	return_to_32bit(env, TARGET_VM86_PICRETURN); \
	271	return
	272
	273	void handle_vm86_fault(CPUX86State *env)
	274	{
0429a971 AF	275	CPUState *cs = CPU(x86_env_get_cpu(env));
0429a971 AF	276	TaskState *ts = cs->opaque;
1455bf48	277	uint32_t csp, ssp;
b333af06 FB	278	unsigned int ip, sp, newflags, newip, newcs, opcode, intno;
b333af06 FB	279	int data32, pref_done;
46ddf551	280
1455bf48	281	csp = env->segs[R_CS].selector << 4;
46ddf551	282	ip = env->eip & 0xffff;
3b46e624	283
1455bf48	284	ssp = env->segs[R_SS].selector << 4;
46ddf551 FB	285	sp = env->regs[R_ESP] & 0xffff;
46ddf551 FB	286
d12d51d5 AL	287	LOG_VM86("VM86 exception %04x:%08x\n",
d12d51d5 AL	288	env->segs[R_CS].selector, env->eip);
46ddf551	289
b333af06 FB	290	data32 = 0;
	291	pref_done = 0;
	292	do {
5899d6d0	293	opcode = vm_getb(env, csp, ip);
b333af06 FB	294	ADD16(ip, 1);
	295	switch (opcode) {
	296	case 0x66: /* 32-bit data */ data32=1; break;
	297	case 0x67: /* 32-bit address */ break;
	298	case 0x2e: /* CS */ break;
	299	case 0x3e: /* DS */ break;
	300	case 0x26: /* ES */ break;
	301	case 0x36: /* SS */ break;
	302	case 0x65: /* GS */ break;
	303	case 0x64: /* FS */ break;
	304	case 0xf2: /* repnz */ break;
	305	case 0xf3: /* rep */ break;
	306	default: pref_done = 1;
	307	}
	308	} while (!pref_done);
	309
46ddf551	310	/* VM86 mode */
b333af06 FB	311	switch(opcode) {
b333af06 FB	312	case 0x9c: /* pushf */
b333af06	313	if (data32) {
5899d6d0	314	vm_putl(env, ssp, sp - 4, get_vflags(env));
b333af06 FB	315	ADD16(env->regs[R_ESP], -4);
b333af06 FB	316	} else {
5899d6d0	317	vm_putw(env, ssp, sp - 2, get_vflags(env));
b333af06 FB	318	ADD16(env->regs[R_ESP], -2);
	319	}
	320	env->eip = ip;
	321	VM86_FAULT_RETURN;
46ddf551	322
b333af06 FB	323	case 0x9d: /* popf */
b333af06 FB	324	if (data32) {
5899d6d0	325	newflags = vm_getl(env, ssp, sp);
46ddf551	326	ADD16(env->regs[R_ESP], 4);
b333af06	327	} else {
5899d6d0	328	newflags = vm_getw(env, ssp, sp);
b333af06 FB	329	ADD16(env->regs[R_ESP], 2);
	330	}
	331	env->eip = ip;
	332	CHECK_IF_IN_TRAP();
	333	if (data32) {
	334	if (set_vflags_long(newflags, env))
46ddf551	335	return;
b333af06 FB	336	} else {
b333af06 FB	337	if (set_vflags_short(newflags, env))
46ddf551	338	return;
46ddf551	339	}
46ddf551 FB	340	VM86_FAULT_RETURN;
	341
	342	case 0xcd: /* int */
5899d6d0	343	intno = vm_getb(env, csp, ip);
b333af06 FB	344	ADD16(ip, 1);
	345	env->eip = ip;
	346	if (ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) {
5fafdf24	347	if ( (ts->vm86plus.vm86plus.vm86dbg_intxxtab[intno >> 3] >>
b333af06 FB	348	(intno &7)) & 1) {
	349	return_to_32bit(env, TARGET_VM86_INTx + (intno << 8));
	350	return;
	351	}
	352	}
	353	do_int(env, intno);
46ddf551 FB	354	break;
	355
	356	case 0xcf: /* iret */
b333af06	357	if (data32) {
5899d6d0 PM	358	newip = vm_getl(env, ssp, sp) & 0xffff;
	359	newcs = vm_getl(env, ssp, sp + 4) & 0xffff;
	360	newflags = vm_getl(env, ssp, sp + 8);
b333af06 FB	361	ADD16(env->regs[R_ESP], 12);
b333af06 FB	362	} else {
5899d6d0 PM	363	newip = vm_getw(env, ssp, sp);
	364	newcs = vm_getw(env, ssp, sp + 2);
	365	newflags = vm_getw(env, ssp, sp + 4);
b333af06 FB	366	ADD16(env->regs[R_ESP], 6);
	367	}
	368	env->eip = newip;
	369	cpu_x86_load_seg(env, R_CS, newcs);
	370	CHECK_IF_IN_TRAP();
	371	if (data32) {
	372	if (set_vflags_long(newflags, env))
	373	return;
	374	} else {
	375	if (set_vflags_short(newflags, env))
	376	return;
	377	}
46ddf551	378	VM86_FAULT_RETURN;
3b46e624	379
46ddf551	380	case 0xfa: /* cli */
b333af06	381	env->eip = ip;
46ddf551 FB	382	clear_IF(env);
46ddf551 FB	383	VM86_FAULT_RETURN;
3b46e624	384
46ddf551	385	case 0xfb: /* sti */
b333af06	386	env->eip = ip;
46ddf551 FB	387	if (set_IF(env))
	388	return;
	389	VM86_FAULT_RETURN;
	390
	391	default:
46ddf551 FB	392	/* real VM86 GPF exception */
	393	return_to_32bit(env, TARGET_VM86_UNKNOWN);
	394	break;
	395	}
	396	}
	397
992f48a0	398	int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr)
46ddf551	399	{
0429a971 AF	400	CPUState *cs = CPU(x86_env_get_cpu(env));
0429a971 AF	401	TaskState *ts = cs->opaque;
53a5960a	402	struct target_vm86plus_struct * target_v86;
46ddf551	403	int ret;
3b46e624	404
46ddf551 FB	405	switch (subfunction) {
	406	case TARGET_VM86_REQUEST_IRQ:
	407	case TARGET_VM86_FREE_IRQ:
	408	case TARGET_VM86_GET_IRQ_BITS:
	409	case TARGET_VM86_GET_AND_RESET_IRQ:
	410	gemu_log("qemu: unsupported vm86 subfunction (%ld)\n", subfunction);
6c30b07f	411	ret = -TARGET_EINVAL;
46ddf551 FB	412	goto out;
	413	case TARGET_VM86_PLUS_INSTALL_CHECK:
	414	/* NOTE: on old vm86 stuff this will return the error
	415	from verify_area(), because the subfunction is
	416	interpreted as (invalid) address to vm86_struct.
	417	So the installation check works.
	418	*/
	419	ret = 0;
	420	goto out;
	421	}
	422
46ddf551 FB	423	/* save current CPU regs */
	424	ts->vm86_saved_regs.eax = 0; /* default vm86 syscall return code */
	425	ts->vm86_saved_regs.ebx = env->regs[R_EBX];
	426	ts->vm86_saved_regs.ecx = env->regs[R_ECX];
	427	ts->vm86_saved_regs.edx = env->regs[R_EDX];
	428	ts->vm86_saved_regs.esi = env->regs[R_ESI];
	429	ts->vm86_saved_regs.edi = env->regs[R_EDI];
	430	ts->vm86_saved_regs.ebp = env->regs[R_EBP];
	431	ts->vm86_saved_regs.esp = env->regs[R_ESP];
	432	ts->vm86_saved_regs.eflags = env->eflags;
	433	ts->vm86_saved_regs.eip = env->eip;
c05bab77 FB	434	ts->vm86_saved_regs.cs = env->segs[R_CS].selector;
	435	ts->vm86_saved_regs.ss = env->segs[R_SS].selector;
	436	ts->vm86_saved_regs.ds = env->segs[R_DS].selector;
	437	ts->vm86_saved_regs.es = env->segs[R_ES].selector;
	438	ts->vm86_saved_regs.fs = env->segs[R_FS].selector;
	439	ts->vm86_saved_regs.gs = env->segs[R_GS].selector;
46ddf551	440
53a5960a	441	ts->target_v86 = vm86_addr;
579a97f7	442	if (!lock_user_struct(VERIFY_READ, target_v86, vm86_addr, 1))
6c30b07f	443	return -TARGET_EFAULT;
46ddf551 FB	444	/* build vm86 CPU state */
46ddf551 FB	445	ts->v86flags = tswap32(target_v86->regs.eflags);
5fafdf24	446	env->eflags = (env->eflags & ~SAFE_MASK) \|
46ddf551	447	(tswap32(target_v86->regs.eflags) & SAFE_MASK) \| VM_MASK;
b333af06	448
cbb21eed	449	ts->vm86plus.cpu_type = tswapal(target_v86->cpu_type);
b333af06 FB	450	switch (ts->vm86plus.cpu_type) {
	451	case TARGET_CPU_286:
	452	ts->v86mask = 0;
	453	break;
	454	case TARGET_CPU_386:
	455	ts->v86mask = NT_MASK \| IOPL_MASK;
	456	break;
	457	case TARGET_CPU_486:
	458	ts->v86mask = AC_MASK \| NT_MASK \| IOPL_MASK;
	459	break;
	460	default:
	461	ts->v86mask = ID_MASK \| AC_MASK \| NT_MASK \| IOPL_MASK;
	462	break;
	463	}
46ddf551 FB	464
	465	env->regs[R_EBX] = tswap32(target_v86->regs.ebx);
	466	env->regs[R_ECX] = tswap32(target_v86->regs.ecx);
	467	env->regs[R_EDX] = tswap32(target_v86->regs.edx);
	468	env->regs[R_ESI] = tswap32(target_v86->regs.esi);
	469	env->regs[R_EDI] = tswap32(target_v86->regs.edi);
	470	env->regs[R_EBP] = tswap32(target_v86->regs.ebp);
	471	env->regs[R_ESP] = tswap32(target_v86->regs.esp);
	472	env->eip = tswap32(target_v86->regs.eip);
	473	cpu_x86_load_seg(env, R_CS, tswap16(target_v86->regs.cs));
	474	cpu_x86_load_seg(env, R_SS, tswap16(target_v86->regs.ss));
	475	cpu_x86_load_seg(env, R_DS, tswap16(target_v86->regs.ds));
	476	cpu_x86_load_seg(env, R_ES, tswap16(target_v86->regs.es));
	477	cpu_x86_load_seg(env, R_FS, tswap16(target_v86->regs.fs));
	478	cpu_x86_load_seg(env, R_GS, tswap16(target_v86->regs.gs));
	479	ret = tswap32(target_v86->regs.eax); /* eax will be restored at
	480	the end of the syscall */
5fafdf24	481	memcpy(&ts->vm86plus.int_revectored,
b333af06	482	&target_v86->int_revectored, 32);
5fafdf24	483	memcpy(&ts->vm86plus.int21_revectored,
b333af06	484	&target_v86->int21_revectored, 32);
cbb21eed	485	ts->vm86plus.vm86plus.flags = tswapal(target_v86->vm86plus.flags);
5fafdf24	486	memcpy(&ts->vm86plus.vm86plus.vm86dbg_intxxtab,
b333af06	487	target_v86->vm86plus.vm86dbg_intxxtab, 32);
53a5960a	488	unlock_user_struct(target_v86, vm86_addr, 0);
3b46e624	489
d12d51d5 AL	490	LOG_VM86("do_vm86: cs:ip=%04x:%04x\n",
d12d51d5 AL	491	env->segs[R_CS].selector, env->eip);
46ddf551 FB	492	/* now the virtual CPU is ready for vm86 execution ! */
	493	out:
	494	return ret;
	495	}