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memory: add memory_region_is_rom()
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1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 */
13
14#include "memory.h"
1c0ffa58 15#include "exec-memory.h"
658b2224 16#include "ioport.h"
74901c3b 17#include "bitops.h"
3e9d69e7 18#include "kvm.h"
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19#include <assert.h>
20
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21#define WANT_EXEC_OBSOLETE
22#include "exec-obsolete.h"
23
4ef4db86 24unsigned memory_region_transaction_depth = 0;
e87c099f 25static bool memory_region_update_pending = false;
4ef4db86 26
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27typedef struct AddrRange AddrRange;
28
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29/*
30 * Note using signed integers limits us to physical addresses at most
31 * 63 bits wide. They are needed for negative offsetting in aliases
32 * (large MemoryRegion::alias_offset).
33 */
093bc2cd 34struct AddrRange {
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35 Int128 start;
36 Int128 size;
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37};
38
08dafab4 39static AddrRange addrrange_make(Int128 start, Int128 size)
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40{
41 return (AddrRange) { start, size };
42}
43
44static bool addrrange_equal(AddrRange r1, AddrRange r2)
45{
08dafab4 46 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
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47}
48
08dafab4 49static Int128 addrrange_end(AddrRange r)
093bc2cd 50{
08dafab4 51 return int128_add(r.start, r.size);
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52}
53
08dafab4 54static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 55{
08dafab4 56 int128_addto(&range.start, delta);
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57 return range;
58}
59
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60static bool addrrange_contains(AddrRange range, Int128 addr)
61{
62 return int128_ge(addr, range.start)
63 && int128_lt(addr, addrrange_end(range));
64}
65
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66static bool addrrange_intersects(AddrRange r1, AddrRange r2)
67{
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68 return addrrange_contains(r1, r2.start)
69 || addrrange_contains(r2, r1.start);
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70}
71
72static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
73{
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74 Int128 start = int128_max(r1.start, r2.start);
75 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
76 return addrrange_make(start, int128_sub(end, start));
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77}
78
79struct CoalescedMemoryRange {
80 AddrRange addr;
81 QTAILQ_ENTRY(CoalescedMemoryRange) link;
82};
83
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84struct MemoryRegionIoeventfd {
85 AddrRange addr;
86 bool match_data;
87 uint64_t data;
88 int fd;
89};
90
91static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
92 MemoryRegionIoeventfd b)
93{
08dafab4 94 if (int128_lt(a.addr.start, b.addr.start)) {
3e9d69e7 95 return true;
08dafab4 96 } else if (int128_gt(a.addr.start, b.addr.start)) {
3e9d69e7 97 return false;
08dafab4 98 } else if (int128_lt(a.addr.size, b.addr.size)) {
3e9d69e7 99 return true;
08dafab4 100 } else if (int128_gt(a.addr.size, b.addr.size)) {
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101 return false;
102 } else if (a.match_data < b.match_data) {
103 return true;
104 } else if (a.match_data > b.match_data) {
105 return false;
106 } else if (a.match_data) {
107 if (a.data < b.data) {
108 return true;
109 } else if (a.data > b.data) {
110 return false;
111 }
112 }
113 if (a.fd < b.fd) {
114 return true;
115 } else if (a.fd > b.fd) {
116 return false;
117 }
118 return false;
119}
120
121static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
122 MemoryRegionIoeventfd b)
123{
124 return !memory_region_ioeventfd_before(a, b)
125 && !memory_region_ioeventfd_before(b, a);
126}
127
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128typedef struct FlatRange FlatRange;
129typedef struct FlatView FlatView;
130
131/* Range of memory in the global map. Addresses are absolute. */
132struct FlatRange {
133 MemoryRegion *mr;
134 target_phys_addr_t offset_in_region;
135 AddrRange addr;
5a583347 136 uint8_t dirty_log_mask;
d0a9b5bc 137 bool readable;
fb1cd6f9 138 bool readonly;
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139};
140
141/* Flattened global view of current active memory hierarchy. Kept in sorted
142 * order.
143 */
144struct FlatView {
145 FlatRange *ranges;
146 unsigned nr;
147 unsigned nr_allocated;
148};
149
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150typedef struct AddressSpace AddressSpace;
151typedef struct AddressSpaceOps AddressSpaceOps;
152
153/* A system address space - I/O, memory, etc. */
154struct AddressSpace {
155 const AddressSpaceOps *ops;
156 MemoryRegion *root;
157 FlatView current_map;
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158 int ioeventfd_nb;
159 MemoryRegionIoeventfd *ioeventfds;
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160};
161
162struct AddressSpaceOps {
163 void (*range_add)(AddressSpace *as, FlatRange *fr);
164 void (*range_del)(AddressSpace *as, FlatRange *fr);
165 void (*log_start)(AddressSpace *as, FlatRange *fr);
166 void (*log_stop)(AddressSpace *as, FlatRange *fr);
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167 void (*ioeventfd_add)(AddressSpace *as, MemoryRegionIoeventfd *fd);
168 void (*ioeventfd_del)(AddressSpace *as, MemoryRegionIoeventfd *fd);
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169};
170
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171#define FOR_EACH_FLAT_RANGE(var, view) \
172 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
173
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174static bool flatrange_equal(FlatRange *a, FlatRange *b)
175{
176 return a->mr == b->mr
177 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 178 && a->offset_in_region == b->offset_in_region
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179 && a->readable == b->readable
180 && a->readonly == b->readonly;
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181}
182
183static void flatview_init(FlatView *view)
184{
185 view->ranges = NULL;
186 view->nr = 0;
187 view->nr_allocated = 0;
188}
189
190/* Insert a range into a given position. Caller is responsible for maintaining
191 * sorting order.
192 */
193static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
194{
195 if (view->nr == view->nr_allocated) {
196 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 197 view->ranges = g_realloc(view->ranges,
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198 view->nr_allocated * sizeof(*view->ranges));
199 }
200 memmove(view->ranges + pos + 1, view->ranges + pos,
201 (view->nr - pos) * sizeof(FlatRange));
202 view->ranges[pos] = *range;
203 ++view->nr;
204}
205
206static void flatview_destroy(FlatView *view)
207{
7267c094 208 g_free(view->ranges);
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209}
210
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211static bool can_merge(FlatRange *r1, FlatRange *r2)
212{
08dafab4 213 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 214 && r1->mr == r2->mr
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215 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
216 r1->addr.size),
217 int128_make64(r2->offset_in_region))
d0a9b5bc 218 && r1->dirty_log_mask == r2->dirty_log_mask
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219 && r1->readable == r2->readable
220 && r1->readonly == r2->readonly;
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221}
222
223/* Attempt to simplify a view by merging ajacent ranges */
224static void flatview_simplify(FlatView *view)
225{
226 unsigned i, j;
227
228 i = 0;
229 while (i < view->nr) {
230 j = i + 1;
231 while (j < view->nr
232 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 233 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
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234 ++j;
235 }
236 ++i;
237 memmove(&view->ranges[i], &view->ranges[j],
238 (view->nr - j) * sizeof(view->ranges[j]));
239 view->nr -= j - i;
240 }
241}
242
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243static void memory_region_read_accessor(void *opaque,
244 target_phys_addr_t addr,
245 uint64_t *value,
246 unsigned size,
247 unsigned shift,
248 uint64_t mask)
249{
250 MemoryRegion *mr = opaque;
251 uint64_t tmp;
252
253 tmp = mr->ops->read(mr->opaque, addr, size);
254 *value |= (tmp & mask) << shift;
255}
256
257static void memory_region_write_accessor(void *opaque,
258 target_phys_addr_t addr,
259 uint64_t *value,
260 unsigned size,
261 unsigned shift,
262 uint64_t mask)
263{
264 MemoryRegion *mr = opaque;
265 uint64_t tmp;
266
267 tmp = (*value >> shift) & mask;
268 mr->ops->write(mr->opaque, addr, tmp, size);
269}
270
271static void access_with_adjusted_size(target_phys_addr_t addr,
272 uint64_t *value,
273 unsigned size,
274 unsigned access_size_min,
275 unsigned access_size_max,
276 void (*access)(void *opaque,
277 target_phys_addr_t addr,
278 uint64_t *value,
279 unsigned size,
280 unsigned shift,
281 uint64_t mask),
282 void *opaque)
283{
284 uint64_t access_mask;
285 unsigned access_size;
286 unsigned i;
287
288 if (!access_size_min) {
289 access_size_min = 1;
290 }
291 if (!access_size_max) {
292 access_size_max = 4;
293 }
294 access_size = MAX(MIN(size, access_size_max), access_size_min);
295 access_mask = -1ULL >> (64 - access_size * 8);
296 for (i = 0; i < size; i += access_size) {
297 /* FIXME: big-endian support */
298 access(opaque, addr + i, value, access_size, i * 8, access_mask);
299 }
300}
301
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302static void memory_region_prepare_ram_addr(MemoryRegion *mr);
303
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304static void as_memory_range_add(AddressSpace *as, FlatRange *fr)
305{
306 ram_addr_t phys_offset, region_offset;
307
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308 memory_region_prepare_ram_addr(fr->mr);
309
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310 phys_offset = fr->mr->ram_addr;
311 region_offset = fr->offset_in_region;
312 /* cpu_register_physical_memory_log() wants region_offset for
313 * mmio, but prefers offseting phys_offset for RAM. Humour it.
314 */
315 if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) {
316 phys_offset += region_offset;
317 region_offset = 0;
318 }
319
d0a9b5bc 320 if (!fr->readable) {
b5fe14cc 321 phys_offset &= ~TARGET_PAGE_MASK & ~IO_MEM_ROMD;
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322 }
323
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324 if (fr->readonly) {
325 phys_offset |= IO_MEM_ROM;
326 }
327
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328 cpu_register_physical_memory_log(int128_get64(fr->addr.start),
329 int128_get64(fr->addr.size),
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330 phys_offset,
331 region_offset,
332 fr->dirty_log_mask);
333}
334
335static void as_memory_range_del(AddressSpace *as, FlatRange *fr)
336{
39b796f2 337 if (fr->dirty_log_mask) {
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338 Int128 end = addrrange_end(fr->addr);
339 cpu_physical_sync_dirty_bitmap(int128_get64(fr->addr.start),
340 int128_get64(end));
39b796f2 341 }
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342 cpu_register_physical_memory(int128_get64(fr->addr.start),
343 int128_get64(fr->addr.size),
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344 IO_MEM_UNASSIGNED);
345}
346
347static void as_memory_log_start(AddressSpace *as, FlatRange *fr)
348{
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349 cpu_physical_log_start(int128_get64(fr->addr.start),
350 int128_get64(fr->addr.size));
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351}
352
353static void as_memory_log_stop(AddressSpace *as, FlatRange *fr)
354{
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355 cpu_physical_log_stop(int128_get64(fr->addr.start),
356 int128_get64(fr->addr.size));
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357}
358
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359static void as_memory_ioeventfd_add(AddressSpace *as, MemoryRegionIoeventfd *fd)
360{
361 int r;
362
08dafab4 363 assert(fd->match_data && int128_get64(fd->addr.size) == 4);
3e9d69e7 364
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365 r = kvm_set_ioeventfd_mmio_long(fd->fd, int128_get64(fd->addr.start),
366 fd->data, true);
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367 if (r < 0) {
368 abort();
369 }
370}
371
372static void as_memory_ioeventfd_del(AddressSpace *as, MemoryRegionIoeventfd *fd)
373{
374 int r;
375
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376 r = kvm_set_ioeventfd_mmio_long(fd->fd, int128_get64(fd->addr.start),
377 fd->data, false);
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378 if (r < 0) {
379 abort();
380 }
381}
382
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383static const AddressSpaceOps address_space_ops_memory = {
384 .range_add = as_memory_range_add,
385 .range_del = as_memory_range_del,
386 .log_start = as_memory_log_start,
387 .log_stop = as_memory_log_stop,
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388 .ioeventfd_add = as_memory_ioeventfd_add,
389 .ioeventfd_del = as_memory_ioeventfd_del,
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390};
391
392static AddressSpace address_space_memory = {
393 .ops = &address_space_ops_memory,
394};
395
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396static const MemoryRegionPortio *find_portio(MemoryRegion *mr, uint64_t offset,
397 unsigned width, bool write)
398{
399 const MemoryRegionPortio *mrp;
400
401 for (mrp = mr->ops->old_portio; mrp->size; ++mrp) {
402 if (offset >= mrp->offset && offset < mrp->offset + mrp->len
403 && width == mrp->size
404 && (write ? (bool)mrp->write : (bool)mrp->read)) {
405 return mrp;
406 }
407 }
408 return NULL;
409}
410
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411static void memory_region_iorange_read(IORange *iorange,
412 uint64_t offset,
413 unsigned width,
414 uint64_t *data)
415{
416 MemoryRegion *mr = container_of(iorange, MemoryRegion, iorange);
417
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418 if (mr->ops->old_portio) {
419 const MemoryRegionPortio *mrp = find_portio(mr, offset, width, false);
420
421 *data = ((uint64_t)1 << (width * 8)) - 1;
422 if (mrp) {
6bf9fd43 423 *data = mrp->read(mr->opaque, offset + mr->offset);
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424 } else if (width == 2) {
425 mrp = find_portio(mr, offset, 1, false);
426 assert(mrp);
427 *data = mrp->read(mr->opaque, offset + mr->offset) |
428 (mrp->read(mr->opaque, offset + mr->offset + 1) << 8);
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429 }
430 return;
431 }
3a130f4e 432 *data = 0;
6bf9fd43 433 access_with_adjusted_size(offset + mr->offset, data, width,
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434 mr->ops->impl.min_access_size,
435 mr->ops->impl.max_access_size,
436 memory_region_read_accessor, mr);
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437}
438
439static void memory_region_iorange_write(IORange *iorange,
440 uint64_t offset,
441 unsigned width,
442 uint64_t data)
443{
444 MemoryRegion *mr = container_of(iorange, MemoryRegion, iorange);
445
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446 if (mr->ops->old_portio) {
447 const MemoryRegionPortio *mrp = find_portio(mr, offset, width, true);
448
449 if (mrp) {
6bf9fd43 450 mrp->write(mr->opaque, offset + mr->offset, data);
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451 } else if (width == 2) {
452 mrp = find_portio(mr, offset, 1, false);
453 assert(mrp);
454 mrp->write(mr->opaque, offset + mr->offset, data & 0xff);
455 mrp->write(mr->opaque, offset + mr->offset + 1, data >> 8);
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456 }
457 return;
458 }
6bf9fd43 459 access_with_adjusted_size(offset + mr->offset, &data, width,
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460 mr->ops->impl.min_access_size,
461 mr->ops->impl.max_access_size,
462 memory_region_write_accessor, mr);
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463}
464
465static const IORangeOps memory_region_iorange_ops = {
466 .read = memory_region_iorange_read,
467 .write = memory_region_iorange_write,
468};
469
470static void as_io_range_add(AddressSpace *as, FlatRange *fr)
471{
472 iorange_init(&fr->mr->iorange, &memory_region_iorange_ops,
08dafab4 473 int128_get64(fr->addr.start), int128_get64(fr->addr.size));
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474 ioport_register(&fr->mr->iorange);
475}
476
477static void as_io_range_del(AddressSpace *as, FlatRange *fr)
478{
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479 isa_unassign_ioport(int128_get64(fr->addr.start),
480 int128_get64(fr->addr.size));
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481}
482
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483static void as_io_ioeventfd_add(AddressSpace *as, MemoryRegionIoeventfd *fd)
484{
485 int r;
486
08dafab4 487 assert(fd->match_data && int128_get64(fd->addr.size) == 2);
3e9d69e7 488
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489 r = kvm_set_ioeventfd_pio_word(fd->fd, int128_get64(fd->addr.start),
490 fd->data, true);
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491 if (r < 0) {
492 abort();
493 }
494}
495
496static void as_io_ioeventfd_del(AddressSpace *as, MemoryRegionIoeventfd *fd)
497{
498 int r;
499
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500 r = kvm_set_ioeventfd_pio_word(fd->fd, int128_get64(fd->addr.start),
501 fd->data, false);
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502 if (r < 0) {
503 abort();
504 }
505}
506
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507static const AddressSpaceOps address_space_ops_io = {
508 .range_add = as_io_range_add,
509 .range_del = as_io_range_del,
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510 .ioeventfd_add = as_io_ioeventfd_add,
511 .ioeventfd_del = as_io_ioeventfd_del,
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512};
513
514static AddressSpace address_space_io = {
515 .ops = &address_space_ops_io,
516};
517
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518/* Render a memory region into the global view. Ranges in @view obscure
519 * ranges in @mr.
520 */
521static void render_memory_region(FlatView *view,
522 MemoryRegion *mr,
08dafab4 523 Int128 base,
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524 AddrRange clip,
525 bool readonly)
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526{
527 MemoryRegion *subregion;
528 unsigned i;
529 target_phys_addr_t offset_in_region;
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530 Int128 remain;
531 Int128 now;
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532 FlatRange fr;
533 AddrRange tmp;
534
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535 if (!mr->enabled) {
536 return;
537 }
538
08dafab4 539 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 540 readonly |= mr->readonly;
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541
542 tmp = addrrange_make(base, mr->size);
543
544 if (!addrrange_intersects(tmp, clip)) {
545 return;
546 }
547
548 clip = addrrange_intersection(tmp, clip);
549
550 if (mr->alias) {
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551 int128_subfrom(&base, int128_make64(mr->alias->addr));
552 int128_subfrom(&base, int128_make64(mr->alias_offset));
fb1cd6f9 553 render_memory_region(view, mr->alias, base, clip, readonly);
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554 return;
555 }
556
557 /* Render subregions in priority order. */
558 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
fb1cd6f9 559 render_memory_region(view, subregion, base, clip, readonly);
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560 }
561
14a3c10a 562 if (!mr->terminates) {
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563 return;
564 }
565
08dafab4 566 offset_in_region = int128_get64(int128_sub(clip.start, base));
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567 base = clip.start;
568 remain = clip.size;
569
570 /* Render the region itself into any gaps left by the current view. */
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571 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
572 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
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573 continue;
574 }
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575 if (int128_lt(base, view->ranges[i].addr.start)) {
576 now = int128_min(remain,
577 int128_sub(view->ranges[i].addr.start, base));
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578 fr.mr = mr;
579 fr.offset_in_region = offset_in_region;
580 fr.addr = addrrange_make(base, now);
5a583347 581 fr.dirty_log_mask = mr->dirty_log_mask;
d0a9b5bc 582 fr.readable = mr->readable;
fb1cd6f9 583 fr.readonly = readonly;
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584 flatview_insert(view, i, &fr);
585 ++i;
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586 int128_addto(&base, now);
587 offset_in_region += int128_get64(now);
588 int128_subfrom(&remain, now);
093bc2cd 589 }
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590 if (int128_eq(base, view->ranges[i].addr.start)) {
591 now = int128_min(remain, view->ranges[i].addr.size);
592 int128_addto(&base, now);
593 offset_in_region += int128_get64(now);
594 int128_subfrom(&remain, now);
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595 }
596 }
08dafab4 597 if (int128_nz(remain)) {
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598 fr.mr = mr;
599 fr.offset_in_region = offset_in_region;
600 fr.addr = addrrange_make(base, remain);
5a583347 601 fr.dirty_log_mask = mr->dirty_log_mask;
d0a9b5bc 602 fr.readable = mr->readable;
fb1cd6f9 603 fr.readonly = readonly;
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604 flatview_insert(view, i, &fr);
605 }
606}
607
608/* Render a memory topology into a list of disjoint absolute ranges. */
609static FlatView generate_memory_topology(MemoryRegion *mr)
610{
611 FlatView view;
612
613 flatview_init(&view);
614
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615 render_memory_region(&view, mr, int128_zero(),
616 addrrange_make(int128_zero(), int128_2_64()), false);
3d8e6bf9 617 flatview_simplify(&view);
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618
619 return view;
620}
621
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622static void address_space_add_del_ioeventfds(AddressSpace *as,
623 MemoryRegionIoeventfd *fds_new,
624 unsigned fds_new_nb,
625 MemoryRegionIoeventfd *fds_old,
626 unsigned fds_old_nb)
627{
628 unsigned iold, inew;
629
630 /* Generate a symmetric difference of the old and new fd sets, adding
631 * and deleting as necessary.
632 */
633
634 iold = inew = 0;
635 while (iold < fds_old_nb || inew < fds_new_nb) {
636 if (iold < fds_old_nb
637 && (inew == fds_new_nb
638 || memory_region_ioeventfd_before(fds_old[iold],
639 fds_new[inew]))) {
640 as->ops->ioeventfd_del(as, &fds_old[iold]);
641 ++iold;
642 } else if (inew < fds_new_nb
643 && (iold == fds_old_nb
644 || memory_region_ioeventfd_before(fds_new[inew],
645 fds_old[iold]))) {
646 as->ops->ioeventfd_add(as, &fds_new[inew]);
647 ++inew;
648 } else {
649 ++iold;
650 ++inew;
651 }
652 }
653}
654
655static void address_space_update_ioeventfds(AddressSpace *as)
656{
657 FlatRange *fr;
658 unsigned ioeventfd_nb = 0;
659 MemoryRegionIoeventfd *ioeventfds = NULL;
660 AddrRange tmp;
661 unsigned i;
662
663 FOR_EACH_FLAT_RANGE(fr, &as->current_map) {
664 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
665 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
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666 int128_sub(fr->addr.start,
667 int128_make64(fr->offset_in_region)));
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668 if (addrrange_intersects(fr->addr, tmp)) {
669 ++ioeventfd_nb;
7267c094 670 ioeventfds = g_realloc(ioeventfds,
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671 ioeventfd_nb * sizeof(*ioeventfds));
672 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
673 ioeventfds[ioeventfd_nb-1].addr = tmp;
674 }
675 }
676 }
677
678 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
679 as->ioeventfds, as->ioeventfd_nb);
680
7267c094 681 g_free(as->ioeventfds);
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682 as->ioeventfds = ioeventfds;
683 as->ioeventfd_nb = ioeventfd_nb;
684}
685
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686static void address_space_update_topology_pass(AddressSpace *as,
687 FlatView old_view,
688 FlatView new_view,
689 bool adding)
093bc2cd 690{
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691 unsigned iold, inew;
692 FlatRange *frold, *frnew;
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693
694 /* Generate a symmetric difference of the old and new memory maps.
695 * Kill ranges in the old map, and instantiate ranges in the new map.
696 */
697 iold = inew = 0;
698 while (iold < old_view.nr || inew < new_view.nr) {
699 if (iold < old_view.nr) {
700 frold = &old_view.ranges[iold];
701 } else {
702 frold = NULL;
703 }
704 if (inew < new_view.nr) {
705 frnew = &new_view.ranges[inew];
706 } else {
707 frnew = NULL;
708 }
709
710 if (frold
711 && (!frnew
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712 || int128_lt(frold->addr.start, frnew->addr.start)
713 || (int128_eq(frold->addr.start, frnew->addr.start)
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714 && !flatrange_equal(frold, frnew)))) {
715 /* In old, but (not in new, or in new but attributes changed). */
716
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717 if (!adding) {
718 as->ops->range_del(as, frold);
719 }
720
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721 ++iold;
722 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
723 /* In both (logging may have changed) */
724
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725 if (adding) {
726 if (frold->dirty_log_mask && !frnew->dirty_log_mask) {
727 as->ops->log_stop(as, frnew);
728 } else if (frnew->dirty_log_mask && !frold->dirty_log_mask) {
729 as->ops->log_start(as, frnew);
730 }
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731 }
732
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733 ++iold;
734 ++inew;
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735 } else {
736 /* In new */
737
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738 if (adding) {
739 as->ops->range_add(as, frnew);
740 }
741
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742 ++inew;
743 }
744 }
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745}
746
747
748static void address_space_update_topology(AddressSpace *as)
749{
750 FlatView old_view = as->current_map;
751 FlatView new_view = generate_memory_topology(as->root);
752
753 address_space_update_topology_pass(as, old_view, new_view, false);
754 address_space_update_topology_pass(as, old_view, new_view, true);
755
cc31e6e7 756 as->current_map = new_view;
093bc2cd 757 flatview_destroy(&old_view);
3e9d69e7 758 address_space_update_ioeventfds(as);
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759}
760
6bba19ba 761static void memory_region_update_topology(MemoryRegion *mr)
cc31e6e7 762{
4ef4db86 763 if (memory_region_transaction_depth) {
e87c099f 764 memory_region_update_pending |= !mr || mr->enabled;
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765 return;
766 }
767
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768 if (mr && !mr->enabled) {
769 return;
770 }
771
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772 if (address_space_memory.root) {
773 address_space_update_topology(&address_space_memory);
774 }
775 if (address_space_io.root) {
776 address_space_update_topology(&address_space_io);
777 }
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778
779 memory_region_update_pending = false;
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780}
781
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782void memory_region_transaction_begin(void)
783{
784 ++memory_region_transaction_depth;
785}
786
787void memory_region_transaction_commit(void)
788{
789 assert(memory_region_transaction_depth);
790 --memory_region_transaction_depth;
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791 if (!memory_region_transaction_depth && memory_region_update_pending) {
792 memory_region_update_topology(NULL);
793 }
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794}
795
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796static void memory_region_destructor_none(MemoryRegion *mr)
797{
798}
799
800static void memory_region_destructor_ram(MemoryRegion *mr)
801{
802 qemu_ram_free(mr->ram_addr);
803}
804
805static void memory_region_destructor_ram_from_ptr(MemoryRegion *mr)
806{
807 qemu_ram_free_from_ptr(mr->ram_addr);
808}
809
810static void memory_region_destructor_iomem(MemoryRegion *mr)
811{
812 cpu_unregister_io_memory(mr->ram_addr);
813}
814
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815static void memory_region_destructor_rom_device(MemoryRegion *mr)
816{
817 qemu_ram_free(mr->ram_addr & TARGET_PAGE_MASK);
818 cpu_unregister_io_memory(mr->ram_addr & ~(TARGET_PAGE_MASK | IO_MEM_ROMD));
819}
820
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821void memory_region_init(MemoryRegion *mr,
822 const char *name,
823 uint64_t size)
824{
825 mr->ops = NULL;
826 mr->parent = NULL;
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827 mr->size = int128_make64(size);
828 if (size == UINT64_MAX) {
829 mr->size = int128_2_64();
830 }
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831 mr->addr = 0;
832 mr->offset = 0;
6bba19ba 833 mr->enabled = true;
14a3c10a 834 mr->terminates = false;
8ea9252a 835 mr->ram = false;
d0a9b5bc 836 mr->readable = true;
fb1cd6f9 837 mr->readonly = false;
545e92e0 838 mr->destructor = memory_region_destructor_none;
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839 mr->priority = 0;
840 mr->may_overlap = false;
841 mr->alias = NULL;
842 QTAILQ_INIT(&mr->subregions);
843 memset(&mr->subregions_link, 0, sizeof mr->subregions_link);
844 QTAILQ_INIT(&mr->coalesced);
7267c094 845 mr->name = g_strdup(name);
5a583347 846 mr->dirty_log_mask = 0;
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847 mr->ioeventfd_nb = 0;
848 mr->ioeventfds = NULL;
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849}
850
851static bool memory_region_access_valid(MemoryRegion *mr,
852 target_phys_addr_t addr,
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853 unsigned size,
854 bool is_write)
093bc2cd 855{
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856 if (mr->ops->valid.accepts
857 && !mr->ops->valid.accepts(mr->opaque, addr, size, is_write)) {
858 return false;
859 }
860
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861 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
862 return false;
863 }
864
865 /* Treat zero as compatibility all valid */
866 if (!mr->ops->valid.max_access_size) {
867 return true;
868 }
869
870 if (size > mr->ops->valid.max_access_size
871 || size < mr->ops->valid.min_access_size) {
872 return false;
873 }
874 return true;
875}
876
877static uint32_t memory_region_read_thunk_n(void *_mr,
878 target_phys_addr_t addr,
879 unsigned size)
880{
881 MemoryRegion *mr = _mr;
164a4dcd 882 uint64_t data = 0;
093bc2cd 883
897fa7cf 884 if (!memory_region_access_valid(mr, addr, size, false)) {
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885 return -1U; /* FIXME: better signalling */
886 }
887
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888 if (!mr->ops->read) {
889 return mr->ops->old_mmio.read[bitops_ffsl(size)](mr->opaque, addr);
890 }
891
093bc2cd 892 /* FIXME: support unaligned access */
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893 access_with_adjusted_size(addr + mr->offset, &data, size,
894 mr->ops->impl.min_access_size,
895 mr->ops->impl.max_access_size,
896 memory_region_read_accessor, mr);
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897
898 return data;
899}
900
901static void memory_region_write_thunk_n(void *_mr,
902 target_phys_addr_t addr,
903 unsigned size,
904 uint64_t data)
905{
906 MemoryRegion *mr = _mr;
093bc2cd 907
897fa7cf 908 if (!memory_region_access_valid(mr, addr, size, true)) {
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909 return; /* FIXME: better signalling */
910 }
911
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912 if (!mr->ops->write) {
913 mr->ops->old_mmio.write[bitops_ffsl(size)](mr->opaque, addr, data);
914 return;
915 }
916
093bc2cd 917 /* FIXME: support unaligned access */
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918 access_with_adjusted_size(addr + mr->offset, &data, size,
919 mr->ops->impl.min_access_size,
920 mr->ops->impl.max_access_size,
921 memory_region_write_accessor, mr);
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922}
923
924static uint32_t memory_region_read_thunk_b(void *mr, target_phys_addr_t addr)
925{
926 return memory_region_read_thunk_n(mr, addr, 1);
927}
928
929static uint32_t memory_region_read_thunk_w(void *mr, target_phys_addr_t addr)
930{
931 return memory_region_read_thunk_n(mr, addr, 2);
932}
933
934static uint32_t memory_region_read_thunk_l(void *mr, target_phys_addr_t addr)
935{
936 return memory_region_read_thunk_n(mr, addr, 4);
937}
938
939static void memory_region_write_thunk_b(void *mr, target_phys_addr_t addr,
940 uint32_t data)
941{
942 memory_region_write_thunk_n(mr, addr, 1, data);
943}
944
945static void memory_region_write_thunk_w(void *mr, target_phys_addr_t addr,
946 uint32_t data)
947{
948 memory_region_write_thunk_n(mr, addr, 2, data);
949}
950
951static void memory_region_write_thunk_l(void *mr, target_phys_addr_t addr,
952 uint32_t data)
953{
954 memory_region_write_thunk_n(mr, addr, 4, data);
955}
956
957static CPUReadMemoryFunc * const memory_region_read_thunk[] = {
958 memory_region_read_thunk_b,
959 memory_region_read_thunk_w,
960 memory_region_read_thunk_l,
961};
962
963static CPUWriteMemoryFunc * const memory_region_write_thunk[] = {
964 memory_region_write_thunk_b,
965 memory_region_write_thunk_w,
966 memory_region_write_thunk_l,
967};
968
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969static void memory_region_prepare_ram_addr(MemoryRegion *mr)
970{
971 if (mr->backend_registered) {
972 return;
973 }
974
545e92e0 975 mr->destructor = memory_region_destructor_iomem;
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976 mr->ram_addr = cpu_register_io_memory(memory_region_read_thunk,
977 memory_region_write_thunk,
978 mr,
979 mr->ops->endianness);
980 mr->backend_registered = true;
981}
982
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983void memory_region_init_io(MemoryRegion *mr,
984 const MemoryRegionOps *ops,
985 void *opaque,
986 const char *name,
987 uint64_t size)
988{
989 memory_region_init(mr, name, size);
990 mr->ops = ops;
991 mr->opaque = opaque;
14a3c10a 992 mr->terminates = true;
16ef61c9 993 mr->backend_registered = false;
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994}
995
996void memory_region_init_ram(MemoryRegion *mr,
997 DeviceState *dev,
998 const char *name,
999 uint64_t size)
1000{
1001 memory_region_init(mr, name, size);
8ea9252a 1002 mr->ram = true;
14a3c10a 1003 mr->terminates = true;
545e92e0 1004 mr->destructor = memory_region_destructor_ram;
fce537d4 1005 mr->ram_addr = qemu_ram_alloc(dev, name, size, mr);
16ef61c9 1006 mr->backend_registered = true;
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1007}
1008
1009void memory_region_init_ram_ptr(MemoryRegion *mr,
1010 DeviceState *dev,
1011 const char *name,
1012 uint64_t size,
1013 void *ptr)
1014{
1015 memory_region_init(mr, name, size);
8ea9252a 1016 mr->ram = true;
14a3c10a 1017 mr->terminates = true;
545e92e0 1018 mr->destructor = memory_region_destructor_ram_from_ptr;
fce537d4 1019 mr->ram_addr = qemu_ram_alloc_from_ptr(dev, name, size, ptr, mr);
16ef61c9 1020 mr->backend_registered = true;
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1021}
1022
1023void memory_region_init_alias(MemoryRegion *mr,
1024 const char *name,
1025 MemoryRegion *orig,
1026 target_phys_addr_t offset,
1027 uint64_t size)
1028{
1029 memory_region_init(mr, name, size);
1030 mr->alias = orig;
1031 mr->alias_offset = offset;
1032}
1033
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1034void memory_region_init_rom_device(MemoryRegion *mr,
1035 const MemoryRegionOps *ops,
75f5941c 1036 void *opaque,
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1037 DeviceState *dev,
1038 const char *name,
1039 uint64_t size)
1040{
1041 memory_region_init(mr, name, size);
7bc2b9cd 1042 mr->ops = ops;
75f5941c 1043 mr->opaque = opaque;
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1044 mr->terminates = true;
1045 mr->destructor = memory_region_destructor_rom_device;
fce537d4 1046 mr->ram_addr = qemu_ram_alloc(dev, name, size, mr);
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1047 mr->ram_addr |= cpu_register_io_memory(memory_region_read_thunk,
1048 memory_region_write_thunk,
1049 mr,
1050 mr->ops->endianness);
1051 mr->ram_addr |= IO_MEM_ROMD;
1052 mr->backend_registered = true;
1053}
1054
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1055void memory_region_destroy(MemoryRegion *mr)
1056{
1057 assert(QTAILQ_EMPTY(&mr->subregions));
545e92e0 1058 mr->destructor(mr);
093bc2cd 1059 memory_region_clear_coalescing(mr);
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1060 g_free((char *)mr->name);
1061 g_free(mr->ioeventfds);
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1062}
1063
1064uint64_t memory_region_size(MemoryRegion *mr)
1065{
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1066 if (int128_eq(mr->size, int128_2_64())) {
1067 return UINT64_MAX;
1068 }
1069 return int128_get64(mr->size);
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1070}
1071
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1072bool memory_region_is_ram(MemoryRegion *mr)
1073{
1074 return mr->ram;
1075}
1076
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1077bool memory_region_is_rom(MemoryRegion *mr)
1078{
1079 return mr->ram && mr->readonly;
1080}
1081
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1082void memory_region_set_offset(MemoryRegion *mr, target_phys_addr_t offset)
1083{
1084 mr->offset = offset;
1085}
1086
1087void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1088{
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1089 uint8_t mask = 1 << client;
1090
1091 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
6bba19ba 1092 memory_region_update_topology(mr);
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1093}
1094
1095bool memory_region_get_dirty(MemoryRegion *mr, target_phys_addr_t addr,
1096 unsigned client)
1097{
14a3c10a 1098 assert(mr->terminates);
5a583347 1099 return cpu_physical_memory_get_dirty(mr->ram_addr + addr, 1 << client);
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1100}
1101
1102void memory_region_set_dirty(MemoryRegion *mr, target_phys_addr_t addr)
1103{
14a3c10a 1104 assert(mr->terminates);
5a583347 1105 return cpu_physical_memory_set_dirty(mr->ram_addr + addr);
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1106}
1107
1108void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1109{
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1110 FlatRange *fr;
1111
cc31e6e7 1112 FOR_EACH_FLAT_RANGE(fr, &address_space_memory.current_map) {
5a583347 1113 if (fr->mr == mr) {
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1114 cpu_physical_sync_dirty_bitmap(int128_get64(fr->addr.start),
1115 int128_get64(addrrange_end(fr->addr)));
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1116 }
1117 }
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1118}
1119
1120void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
1121{
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1122 if (mr->readonly != readonly) {
1123 mr->readonly = readonly;
6bba19ba 1124 memory_region_update_topology(mr);
fb1cd6f9 1125 }
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1126}
1127
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1128void memory_region_rom_device_set_readable(MemoryRegion *mr, bool readable)
1129{
1130 if (mr->readable != readable) {
1131 mr->readable = readable;
6bba19ba 1132 memory_region_update_topology(mr);
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1133 }
1134}
1135
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1136void memory_region_reset_dirty(MemoryRegion *mr, target_phys_addr_t addr,
1137 target_phys_addr_t size, unsigned client)
1138{
14a3c10a 1139 assert(mr->terminates);
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1140 cpu_physical_memory_reset_dirty(mr->ram_addr + addr,
1141 mr->ram_addr + addr + size,
1142 1 << client);
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1143}
1144
1145void *memory_region_get_ram_ptr(MemoryRegion *mr)
1146{
1147 if (mr->alias) {
1148 return memory_region_get_ram_ptr(mr->alias) + mr->alias_offset;
1149 }
1150
14a3c10a 1151 assert(mr->terminates);
093bc2cd 1152
021d26d1 1153 return qemu_get_ram_ptr(mr->ram_addr & TARGET_PAGE_MASK);
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1154}
1155
1156static void memory_region_update_coalesced_range(MemoryRegion *mr)
1157{
1158 FlatRange *fr;
1159 CoalescedMemoryRange *cmr;
1160 AddrRange tmp;
1161
cc31e6e7 1162 FOR_EACH_FLAT_RANGE(fr, &address_space_memory.current_map) {
093bc2cd 1163 if (fr->mr == mr) {
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1164 qemu_unregister_coalesced_mmio(int128_get64(fr->addr.start),
1165 int128_get64(fr->addr.size));
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1166 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
1167 tmp = addrrange_shift(cmr->addr,
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1168 int128_sub(fr->addr.start,
1169 int128_make64(fr->offset_in_region)));
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1170 if (!addrrange_intersects(tmp, fr->addr)) {
1171 continue;
1172 }
1173 tmp = addrrange_intersection(tmp, fr->addr);
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1174 qemu_register_coalesced_mmio(int128_get64(tmp.start),
1175 int128_get64(tmp.size));
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1176 }
1177 }
1178 }
1179}
1180
1181void memory_region_set_coalescing(MemoryRegion *mr)
1182{
1183 memory_region_clear_coalescing(mr);
08dafab4 1184 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
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1185}
1186
1187void memory_region_add_coalescing(MemoryRegion *mr,
1188 target_phys_addr_t offset,
1189 uint64_t size)
1190{
7267c094 1191 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 1192
08dafab4 1193 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
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1194 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
1195 memory_region_update_coalesced_range(mr);
1196}
1197
1198void memory_region_clear_coalescing(MemoryRegion *mr)
1199{
1200 CoalescedMemoryRange *cmr;
1201
1202 while (!QTAILQ_EMPTY(&mr->coalesced)) {
1203 cmr = QTAILQ_FIRST(&mr->coalesced);
1204 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
7267c094 1205 g_free(cmr);
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1206 }
1207 memory_region_update_coalesced_range(mr);
1208}
1209
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1210void memory_region_add_eventfd(MemoryRegion *mr,
1211 target_phys_addr_t addr,
1212 unsigned size,
1213 bool match_data,
1214 uint64_t data,
1215 int fd)
1216{
1217 MemoryRegionIoeventfd mrfd = {
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1218 .addr.start = int128_make64(addr),
1219 .addr.size = int128_make64(size),
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1220 .match_data = match_data,
1221 .data = data,
1222 .fd = fd,
1223 };
1224 unsigned i;
1225
1226 for (i = 0; i < mr->ioeventfd_nb; ++i) {
1227 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
1228 break;
1229 }
1230 }
1231 ++mr->ioeventfd_nb;
7267c094 1232 mr->ioeventfds = g_realloc(mr->ioeventfds,
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1233 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
1234 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
1235 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
1236 mr->ioeventfds[i] = mrfd;
6bba19ba 1237 memory_region_update_topology(mr);
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1238}
1239
1240void memory_region_del_eventfd(MemoryRegion *mr,
1241 target_phys_addr_t addr,
1242 unsigned size,
1243 bool match_data,
1244 uint64_t data,
1245 int fd)
1246{
1247 MemoryRegionIoeventfd mrfd = {
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1248 .addr.start = int128_make64(addr),
1249 .addr.size = int128_make64(size),
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1250 .match_data = match_data,
1251 .data = data,
1252 .fd = fd,
1253 };
1254 unsigned i;
1255
1256 for (i = 0; i < mr->ioeventfd_nb; ++i) {
1257 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
1258 break;
1259 }
1260 }
1261 assert(i != mr->ioeventfd_nb);
1262 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
1263 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
1264 --mr->ioeventfd_nb;
7267c094 1265 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 1266 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
6bba19ba 1267 memory_region_update_topology(mr);
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1268}
1269
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1270static void memory_region_add_subregion_common(MemoryRegion *mr,
1271 target_phys_addr_t offset,
1272 MemoryRegion *subregion)
1273{
1274 MemoryRegion *other;
1275
1276 assert(!subregion->parent);
1277 subregion->parent = mr;
1278 subregion->addr = offset;
1279 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
1280 if (subregion->may_overlap || other->may_overlap) {
1281 continue;
1282 }
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1283 if (int128_gt(int128_make64(offset),
1284 int128_add(int128_make64(other->addr), other->size))
1285 || int128_le(int128_add(int128_make64(offset), subregion->size),
1286 int128_make64(other->addr))) {
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1287 continue;
1288 }
a5e1cbc8 1289#if 0
860329b2
MW
1290 printf("warning: subregion collision %llx/%llx (%s) "
1291 "vs %llx/%llx (%s)\n",
093bc2cd 1292 (unsigned long long)offset,
08dafab4 1293 (unsigned long long)int128_get64(subregion->size),
860329b2
MW
1294 subregion->name,
1295 (unsigned long long)other->addr,
08dafab4 1296 (unsigned long long)int128_get64(other->size),
860329b2 1297 other->name);
a5e1cbc8 1298#endif
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1299 }
1300 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
1301 if (subregion->priority >= other->priority) {
1302 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
1303 goto done;
1304 }
1305 }
1306 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
1307done:
6bba19ba 1308 memory_region_update_topology(mr);
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1309}
1310
1311
1312void memory_region_add_subregion(MemoryRegion *mr,
1313 target_phys_addr_t offset,
1314 MemoryRegion *subregion)
1315{
1316 subregion->may_overlap = false;
1317 subregion->priority = 0;
1318 memory_region_add_subregion_common(mr, offset, subregion);
1319}
1320
1321void memory_region_add_subregion_overlap(MemoryRegion *mr,
1322 target_phys_addr_t offset,
1323 MemoryRegion *subregion,
1324 unsigned priority)
1325{
1326 subregion->may_overlap = true;
1327 subregion->priority = priority;
1328 memory_region_add_subregion_common(mr, offset, subregion);
1329}
1330
1331void memory_region_del_subregion(MemoryRegion *mr,
1332 MemoryRegion *subregion)
1333{
1334 assert(subregion->parent == mr);
1335 subregion->parent = NULL;
1336 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
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1337 memory_region_update_topology(mr);
1338}
1339
1340void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
1341{
1342 if (enabled == mr->enabled) {
1343 return;
1344 }
1345 mr->enabled = enabled;
1346 memory_region_update_topology(NULL);
093bc2cd 1347}
1c0ffa58 1348
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1349void memory_region_set_address(MemoryRegion *mr, target_phys_addr_t addr)
1350{
1351 MemoryRegion *parent = mr->parent;
1352 unsigned priority = mr->priority;
1353 bool may_overlap = mr->may_overlap;
1354
1355 if (addr == mr->addr || !parent) {
1356 mr->addr = addr;
1357 return;
1358 }
1359
1360 memory_region_transaction_begin();
1361 memory_region_del_subregion(parent, mr);
1362 if (may_overlap) {
1363 memory_region_add_subregion_overlap(parent, addr, mr, priority);
1364 } else {
1365 memory_region_add_subregion(parent, addr, mr);
1366 }
1367 memory_region_transaction_commit();
1368}
1369
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1370void memory_region_set_alias_offset(MemoryRegion *mr, target_phys_addr_t offset)
1371{
1372 target_phys_addr_t old_offset = mr->alias_offset;
1373
1374 assert(mr->alias);
1375 mr->alias_offset = offset;
1376
1377 if (offset == old_offset || !mr->parent) {
1378 return;
1379 }
1380
1381 memory_region_update_topology(mr);
1382}
1383
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1384void set_system_memory_map(MemoryRegion *mr)
1385{
cc31e6e7 1386 address_space_memory.root = mr;
6bba19ba 1387 memory_region_update_topology(NULL);
1c0ffa58 1388}
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1389
1390void set_system_io_map(MemoryRegion *mr)
1391{
1392 address_space_io.root = mr;
6bba19ba 1393 memory_region_update_topology(NULL);
658b2224 1394}
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1395
1396typedef struct MemoryRegionList MemoryRegionList;
1397
1398struct MemoryRegionList {
1399 const MemoryRegion *mr;
1400 bool printed;
1401 QTAILQ_ENTRY(MemoryRegionList) queue;
1402};
1403
1404typedef QTAILQ_HEAD(queue, MemoryRegionList) MemoryRegionListHead;
1405
1406static void mtree_print_mr(fprintf_function mon_printf, void *f,
1407 const MemoryRegion *mr, unsigned int level,
1408 target_phys_addr_t base,
9479c57a 1409 MemoryRegionListHead *alias_print_queue)
314e2987 1410{
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JK
1411 MemoryRegionList *new_ml, *ml, *next_ml;
1412 MemoryRegionListHead submr_print_queue;
314e2987
BS
1413 const MemoryRegion *submr;
1414 unsigned int i;
1415
314e2987
BS
1416 if (!mr) {
1417 return;
1418 }
1419
1420 for (i = 0; i < level; i++) {
1421 mon_printf(f, " ");
1422 }
1423
1424 if (mr->alias) {
1425 MemoryRegionList *ml;
1426 bool found = false;
1427
1428 /* check if the alias is already in the queue */
9479c57a 1429 QTAILQ_FOREACH(ml, alias_print_queue, queue) {
314e2987
BS
1430 if (ml->mr == mr->alias && !ml->printed) {
1431 found = true;
1432 }
1433 }
1434
1435 if (!found) {
1436 ml = g_new(MemoryRegionList, 1);
1437 ml->mr = mr->alias;
1438 ml->printed = false;
9479c57a 1439 QTAILQ_INSERT_TAIL(alias_print_queue, ml, queue);
314e2987 1440 }
4b474ba7 1441 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d): alias %s @%s "
314e2987
BS
1442 TARGET_FMT_plx "-" TARGET_FMT_plx "\n",
1443 base + mr->addr,
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1444 base + mr->addr
1445 + (target_phys_addr_t)int128_get64(mr->size) - 1,
4b474ba7 1446 mr->priority,
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1447 mr->name,
1448 mr->alias->name,
1449 mr->alias_offset,
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1450 mr->alias_offset
1451 + (target_phys_addr_t)int128_get64(mr->size) - 1);
314e2987 1452 } else {
4b474ba7 1453 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d): %s\n",
314e2987 1454 base + mr->addr,
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1455 base + mr->addr
1456 + (target_phys_addr_t)int128_get64(mr->size) - 1,
4b474ba7 1457 mr->priority,
314e2987
BS
1458 mr->name);
1459 }
9479c57a
JK
1460
1461 QTAILQ_INIT(&submr_print_queue);
1462
314e2987 1463 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK
1464 new_ml = g_new(MemoryRegionList, 1);
1465 new_ml->mr = submr;
1466 QTAILQ_FOREACH(ml, &submr_print_queue, queue) {
1467 if (new_ml->mr->addr < ml->mr->addr ||
1468 (new_ml->mr->addr == ml->mr->addr &&
1469 new_ml->mr->priority > ml->mr->priority)) {
1470 QTAILQ_INSERT_BEFORE(ml, new_ml, queue);
1471 new_ml = NULL;
1472 break;
1473 }
1474 }
1475 if (new_ml) {
1476 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, queue);
1477 }
1478 }
1479
1480 QTAILQ_FOREACH(ml, &submr_print_queue, queue) {
1481 mtree_print_mr(mon_printf, f, ml->mr, level + 1, base + mr->addr,
1482 alias_print_queue);
1483 }
1484
88365e47 1485 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, queue, next_ml) {
9479c57a 1486 g_free(ml);
314e2987
BS
1487 }
1488}
1489
1490void mtree_info(fprintf_function mon_printf, void *f)
1491{
1492 MemoryRegionListHead ml_head;
1493 MemoryRegionList *ml, *ml2;
1494
1495 QTAILQ_INIT(&ml_head);
1496
1497 mon_printf(f, "memory\n");
1498 mtree_print_mr(mon_printf, f, address_space_memory.root, 0, 0, &ml_head);
1499
1500 /* print aliased regions */
1501 QTAILQ_FOREACH(ml, &ml_head, queue) {
1502 if (!ml->printed) {
1503 mon_printf(f, "%s\n", ml->mr->name);
1504 mtree_print_mr(mon_printf, f, ml->mr, 0, 0, &ml_head);
1505 }
1506 }
1507
1508 QTAILQ_FOREACH_SAFE(ml, &ml_head, queue, ml2) {
88365e47 1509 g_free(ml);
314e2987
BS
1510 }
1511
06631810
JK
1512 if (address_space_io.root &&
1513 !QTAILQ_EMPTY(&address_space_io.root->subregions)) {
1514 QTAILQ_INIT(&ml_head);
1515 mon_printf(f, "I/O\n");
1516 mtree_print_mr(mon_printf, f, address_space_io.root, 0, 0, &ml_head);
1517 }
314e2987 1518}