]> git.proxmox.com Git - mirror_qemu.git/blame - numa.c
ppc: implement xsrqpxp instruction
[mirror_qemu.git] / numa.c
CommitLineData
96d0e26c
WG
1/*
2 * NUMA parameter parsing routines
3 *
4 * Copyright (c) 2014 Fujitsu Ltd.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
d38ea87a 25#include "qemu/osdep.h"
e35704ba 26#include "sysemu/numa.h"
96d0e26c 27#include "exec/cpu-common.h"
0987d735 28#include "exec/ramlist.h"
96d0e26c
WG
29#include "qemu/bitmap.h"
30#include "qom/cpu.h"
2b631ec2
WG
31#include "qemu/error-report.h"
32#include "include/exec/cpu-common.h" /* for RAM_ADDR_FMT */
0042109a
WG
33#include "qapi-visit.h"
34#include "qapi/opts-visitor.h"
dfabb8b9 35#include "hw/boards.h"
7febe36f 36#include "sysemu/hostmem.h"
76b5d850 37#include "qmp-commands.h"
5b009e40 38#include "hw/mem/pc-dimm.h"
7dcd1d70
EH
39#include "qemu/option.h"
40#include "qemu/config-file.h"
0042109a
WG
41
42QemuOptsList qemu_numa_opts = {
43 .name = "numa",
44 .implied_opt_name = "type",
45 .head = QTAILQ_HEAD_INITIALIZER(qemu_numa_opts.head),
46 .desc = { { 0 } } /* validated with OptsVisitor */
47};
48
7febe36f 49static int have_memdevs = -1;
25712ffe
EH
50static int max_numa_nodeid; /* Highest specified NUMA node ID, plus one.
51 * For all nodes, nodeid < max_numa_nodeid
52 */
de1a7c84 53int nb_numa_nodes;
de1a7c84 54NodeInfo numa_info[MAX_NODES];
7febe36f 55
fa9ea81d
BR
56void numa_set_mem_node_id(ram_addr_t addr, uint64_t size, uint32_t node)
57{
672558d2 58 struct numa_addr_range *range;
fa9ea81d 59
abafabd8
BR
60 /*
61 * Memory-less nodes can come here with 0 size in which case,
62 * there is nothing to do.
63 */
64 if (!size) {
65 return;
66 }
67
672558d2 68 range = g_malloc0(sizeof(*range));
fa9ea81d
BR
69 range->mem_start = addr;
70 range->mem_end = addr + size - 1;
71 QLIST_INSERT_HEAD(&numa_info[node].addr, range, entry);
72}
73
74void numa_unset_mem_node_id(ram_addr_t addr, uint64_t size, uint32_t node)
75{
76 struct numa_addr_range *range, *next;
77
78 QLIST_FOREACH_SAFE(range, &numa_info[node].addr, entry, next) {
79 if (addr == range->mem_start && (addr + size - 1) == range->mem_end) {
80 QLIST_REMOVE(range, entry);
81 g_free(range);
82 return;
83 }
84 }
85}
86
abafabd8
BR
87static void numa_set_mem_ranges(void)
88{
89 int i;
90 ram_addr_t mem_start = 0;
91
92 /*
93 * Deduce start address of each node and use it to store
94 * the address range info in numa_info address range list
95 */
96 for (i = 0; i < nb_numa_nodes; i++) {
97 numa_set_mem_node_id(mem_start, numa_info[i].node_mem, i);
98 mem_start += numa_info[i].node_mem;
99 }
100}
101
e75e2a14
BR
102/*
103 * Check if @addr falls under NUMA @node.
104 */
105static bool numa_addr_belongs_to_node(ram_addr_t addr, uint32_t node)
106{
107 struct numa_addr_range *range;
108
109 QLIST_FOREACH(range, &numa_info[node].addr, entry) {
110 if (addr >= range->mem_start && addr <= range->mem_end) {
111 return true;
112 }
113 }
114 return false;
115}
116
117/*
118 * Given an address, return the index of the NUMA node to which the
119 * address belongs to.
120 */
121uint32_t numa_get_node(ram_addr_t addr, Error **errp)
122{
123 uint32_t i;
124
125 /* For non NUMA configurations, check if the addr falls under node 0 */
126 if (!nb_numa_nodes) {
127 if (numa_addr_belongs_to_node(addr, 0)) {
128 return 0;
129 }
130 }
131
132 for (i = 0; i < nb_numa_nodes; i++) {
133 if (numa_addr_belongs_to_node(addr, i)) {
134 return i;
135 }
136 }
137
138 error_setg(errp, "Address 0x" RAM_ADDR_FMT " doesn't belong to any "
139 "NUMA node", addr);
140 return -1;
141}
142
0042109a 143static void numa_node_parse(NumaNodeOptions *node, QemuOpts *opts, Error **errp)
96d0e26c 144{
0042109a
WG
145 uint16_t nodenr;
146 uint16List *cpus = NULL;
96d0e26c 147
0042109a
WG
148 if (node->has_nodeid) {
149 nodenr = node->nodeid;
96d0e26c 150 } else {
0042109a 151 nodenr = nb_numa_nodes;
96d0e26c
WG
152 }
153
0042109a
WG
154 if (nodenr >= MAX_NODES) {
155 error_setg(errp, "Max number of NUMA nodes reached: %"
01bbbcf4 156 PRIu16 "", nodenr);
0042109a 157 return;
96d0e26c
WG
158 }
159
1945b9d8
EH
160 if (numa_info[nodenr].present) {
161 error_setg(errp, "Duplicate NUMA nodeid: %" PRIu16, nodenr);
162 return;
163 }
164
0042109a 165 for (cpus = node->cpus; cpus; cpus = cpus->next) {
8979c945
EH
166 if (cpus->value >= max_cpus) {
167 error_setg(errp,
168 "CPU index (%" PRIu16 ")"
169 " should be smaller than maxcpus (%d)",
170 cpus->value, max_cpus);
0042109a
WG
171 return;
172 }
173 bitmap_set(numa_info[nodenr].node_cpu, cpus->value, 1);
96d0e26c
WG
174 }
175
7febe36f 176 if (node->has_mem && node->has_memdev) {
01bbbcf4 177 error_setg(errp, "qemu: cannot specify both mem= and memdev=");
7febe36f
PB
178 return;
179 }
180
181 if (have_memdevs == -1) {
182 have_memdevs = node->has_memdev;
183 }
184 if (node->has_memdev != have_memdevs) {
185 error_setg(errp, "qemu: memdev option must be specified for either "
01bbbcf4 186 "all or no nodes");
7febe36f
PB
187 return;
188 }
189
0042109a
WG
190 if (node->has_mem) {
191 uint64_t mem_size = node->mem;
192 const char *mem_str = qemu_opt_get(opts, "mem");
193 /* Fix up legacy suffix-less format */
194 if (g_ascii_isdigit(mem_str[strlen(mem_str) - 1])) {
195 mem_size <<= 20;
196 }
197 numa_info[nodenr].node_mem = mem_size;
198 }
7febe36f
PB
199 if (node->has_memdev) {
200 Object *o;
201 o = object_resolve_path_type(node->memdev, TYPE_MEMORY_BACKEND, NULL);
202 if (!o) {
203 error_setg(errp, "memdev=%s is ambiguous", node->memdev);
204 return;
205 }
206
207 object_ref(o);
208 numa_info[nodenr].node_mem = object_property_get_int(o, "size", NULL);
209 numa_info[nodenr].node_memdev = MEMORY_BACKEND(o);
210 }
1af878e0
EH
211 numa_info[nodenr].present = true;
212 max_numa_nodeid = MAX(max_numa_nodeid, nodenr + 1);
96d0e26c
WG
213}
214
28d0de7a 215static int parse_numa(void *opaque, QemuOpts *opts, Error **errp)
96d0e26c 216{
0042109a
WG
217 NumaOptions *object = NULL;
218 Error *err = NULL;
96d0e26c 219
0042109a 220 {
09204eac
EB
221 Visitor *v = opts_visitor_new(opts);
222 visit_type_NumaOptions(v, NULL, &object, &err);
223 visit_free(v);
96d0e26c 224 }
96d0e26c 225
0042109a 226 if (err) {
157e94e8 227 goto end;
0042109a 228 }
96d0e26c 229
1fd5d4fe 230 switch (object->type) {
0042109a 231 case NUMA_OPTIONS_KIND_NODE:
32bafa8f 232 numa_node_parse(object->u.node.data, opts, &err);
0042109a 233 if (err) {
157e94e8 234 goto end;
96d0e26c 235 }
0042109a
WG
236 nb_numa_nodes++;
237 break;
238 default:
239 abort();
240 }
96d0e26c 241
157e94e8 242end:
96a1616c 243 qapi_free_NumaOptions(object);
157e94e8
MAL
244 if (err) {
245 error_report_err(err);
246 return -1;
247 }
0042109a 248
157e94e8 249 return 0;
96d0e26c
WG
250}
251
3ef71975
EH
252static char *enumerate_cpus(unsigned long *cpus, int max_cpus)
253{
254 int cpu;
255 bool first = true;
256 GString *s = g_string_new(NULL);
257
258 for (cpu = find_first_bit(cpus, max_cpus);
259 cpu < max_cpus;
260 cpu = find_next_bit(cpus, max_cpus, cpu + 1)) {
261 g_string_append_printf(s, "%s%d", first ? "" : " ", cpu);
262 first = false;
263 }
264 return g_string_free(s, FALSE);
265}
266
267static void validate_numa_cpus(void)
268{
269 int i;
cdda2018 270 unsigned long *seen_cpus = bitmap_new(max_cpus);
3ef71975 271
3ef71975 272 for (i = 0; i < nb_numa_nodes; i++) {
cdda2018 273 if (bitmap_intersects(seen_cpus, numa_info[i].node_cpu, max_cpus)) {
3ef71975 274 bitmap_and(seen_cpus, seen_cpus,
cdda2018 275 numa_info[i].node_cpu, max_cpus);
3ef71975 276 error_report("CPU(s) present in multiple NUMA nodes: %s",
a8f15a27 277 enumerate_cpus(seen_cpus, max_cpus));
cdda2018 278 g_free(seen_cpus);
3ef71975
EH
279 exit(EXIT_FAILURE);
280 }
281 bitmap_or(seen_cpus, seen_cpus,
cdda2018 282 numa_info[i].node_cpu, max_cpus);
3ef71975 283 }
549fc54b
EH
284
285 if (!bitmap_full(seen_cpus, max_cpus)) {
286 char *msg;
287 bitmap_complement(seen_cpus, seen_cpus, max_cpus);
288 msg = enumerate_cpus(seen_cpus, max_cpus);
289 error_report("warning: CPU(s) not present in any NUMA nodes: %s", msg);
290 error_report("warning: All CPU(s) up to maxcpus should be described "
291 "in NUMA config");
292 g_free(msg);
293 }
cdda2018 294 g_free(seen_cpus);
3ef71975
EH
295}
296
57924bcd 297void parse_numa_opts(MachineClass *mc)
96d0e26c 298{
12d6e464
EH
299 int i;
300
cdda2018
IM
301 for (i = 0; i < MAX_NODES; i++) {
302 numa_info[i].node_cpu = bitmap_new(max_cpus);
303 }
304
28d0de7a 305 if (qemu_opts_foreach(qemu_find_opts("numa"), parse_numa, NULL, NULL)) {
7dcd1d70
EH
306 exit(1);
307 }
308
12d6e464
EH
309 assert(max_numa_nodeid <= MAX_NODES);
310
311 /* No support for sparse NUMA node IDs yet: */
312 for (i = max_numa_nodeid - 1; i >= 0; i--) {
313 /* Report large node IDs first, to make mistakes easier to spot */
314 if (!numa_info[i].present) {
315 error_report("numa: Node ID missing: %d", i);
316 exit(1);
317 }
318 }
319
320 /* This must be always true if all nodes are present: */
321 assert(nb_numa_nodes == max_numa_nodeid);
322
96d0e26c 323 if (nb_numa_nodes > 0) {
2b631ec2 324 uint64_t numa_total;
96d0e26c
WG
325
326 if (nb_numa_nodes > MAX_NODES) {
327 nb_numa_nodes = MAX_NODES;
328 }
329
9851d0fe 330 /* If no memory size is given for any node, assume the default case
96d0e26c
WG
331 * and distribute the available memory equally across all nodes
332 */
333 for (i = 0; i < nb_numa_nodes; i++) {
8c85901e 334 if (numa_info[i].node_mem != 0) {
96d0e26c
WG
335 break;
336 }
337 }
338 if (i == nb_numa_nodes) {
339 uint64_t usedmem = 0;
340
d75e2f68 341 /* On Linux, each node's border has to be 8MB aligned,
96d0e26c
WG
342 * the final node gets the rest.
343 */
344 for (i = 0; i < nb_numa_nodes - 1; i++) {
8c85901e
WG
345 numa_info[i].node_mem = (ram_size / nb_numa_nodes) &
346 ~((1 << 23UL) - 1);
347 usedmem += numa_info[i].node_mem;
96d0e26c 348 }
8c85901e 349 numa_info[i].node_mem = ram_size - usedmem;
96d0e26c
WG
350 }
351
2b631ec2
WG
352 numa_total = 0;
353 for (i = 0; i < nb_numa_nodes; i++) {
8c85901e 354 numa_total += numa_info[i].node_mem;
2b631ec2
WG
355 }
356 if (numa_total != ram_size) {
c68233ae
HT
357 error_report("total memory for NUMA nodes (0x%" PRIx64 ")"
358 " should equal RAM size (0x" RAM_ADDR_FMT ")",
2b631ec2
WG
359 numa_total, ram_size);
360 exit(1);
361 }
362
fa9ea81d
BR
363 for (i = 0; i < nb_numa_nodes; i++) {
364 QLIST_INIT(&numa_info[i].addr);
365 }
366
abafabd8
BR
367 numa_set_mem_ranges();
368
96d0e26c 369 for (i = 0; i < nb_numa_nodes; i++) {
cdda2018 370 if (!bitmap_empty(numa_info[i].node_cpu, max_cpus)) {
96d0e26c
WG
371 break;
372 }
373 }
57924bcd
IM
374 /* Historically VCPUs were assigned in round-robin order to NUMA
375 * nodes. However it causes issues with guest not handling it nice
376 * in case where cores/threads from a multicore CPU appear on
377 * different nodes. So allow boards to override default distribution
378 * rule grouping VCPUs by socket so that VCPUs from the same socket
379 * would be on the same node.
96d0e26c
WG
380 */
381 if (i == nb_numa_nodes) {
382 for (i = 0; i < max_cpus; i++) {
57924bcd
IM
383 unsigned node_id = i % nb_numa_nodes;
384 if (mc->cpu_index_to_socket_id) {
385 node_id = mc->cpu_index_to_socket_id(i) % nb_numa_nodes;
386 }
387
388 set_bit(i, numa_info[node_id].node_cpu);
96d0e26c
WG
389 }
390 }
3ef71975
EH
391
392 validate_numa_cpus();
abafabd8
BR
393 } else {
394 numa_set_mem_node_id(0, ram_size, 0);
96d0e26c
WG
395 }
396}
397
dde11116 398void numa_post_machine_init(void)
96d0e26c
WG
399{
400 CPUState *cpu;
401 int i;
402
403 CPU_FOREACH(cpu) {
404 for (i = 0; i < nb_numa_nodes; i++) {
cdda2018 405 assert(cpu->cpu_index < max_cpus);
8c85901e 406 if (test_bit(cpu->cpu_index, numa_info[i].node_cpu)) {
96d0e26c
WG
407 cpu->numa_node = i;
408 }
409 }
410 }
411}
dfabb8b9 412
7febe36f
PB
413static void allocate_system_memory_nonnuma(MemoryRegion *mr, Object *owner,
414 const char *name,
415 uint64_t ram_size)
416{
0b183fc8
PB
417 if (mem_path) {
418#ifdef __linux__
7f56e740 419 Error *err = NULL;
dbcb8981 420 memory_region_init_ram_from_file(mr, owner, name, ram_size, false,
7f56e740 421 mem_path, &err);
c3ba3095 422 if (err) {
29b762f5 423 error_report_err(err);
fae947b0
LC
424 if (mem_prealloc) {
425 exit(1);
426 }
427
428 /* Legacy behavior: if allocation failed, fall back to
429 * regular RAM allocation.
430 */
f8ed85ac 431 memory_region_init_ram(mr, owner, name, ram_size, &error_fatal);
7f56e740 432 }
0b183fc8
PB
433#else
434 fprintf(stderr, "-mem-path not supported on this host\n");
435 exit(1);
436#endif
437 } else {
f8ed85ac 438 memory_region_init_ram(mr, owner, name, ram_size, &error_fatal);
0b183fc8 439 }
7febe36f
PB
440 vmstate_register_ram_global(mr);
441}
442
dfabb8b9
PB
443void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner,
444 const char *name,
445 uint64_t ram_size)
446{
7febe36f
PB
447 uint64_t addr = 0;
448 int i;
449
450 if (nb_numa_nodes == 0 || !have_memdevs) {
451 allocate_system_memory_nonnuma(mr, owner, name, ram_size);
452 return;
453 }
454
455 memory_region_init(mr, owner, name, ram_size);
456 for (i = 0; i < MAX_NODES; i++) {
7febe36f
PB
457 uint64_t size = numa_info[i].node_mem;
458 HostMemoryBackend *backend = numa_info[i].node_memdev;
459 if (!backend) {
460 continue;
461 }
007b0657
MA
462 MemoryRegion *seg = host_memory_backend_get_memory(backend,
463 &error_fatal);
7febe36f 464
0462faee
HT
465 if (memory_region_is_mapped(seg)) {
466 char *path = object_get_canonical_path_component(OBJECT(backend));
467 error_report("memory backend %s is used multiple times. Each "
468 "-numa option must use a different memdev value.",
469 path);
470 exit(1);
471 }
472
0b217571 473 host_memory_backend_set_mapped(backend, true);
7febe36f
PB
474 memory_region_add_subregion(mr, addr, seg);
475 vmstate_register_ram_global(seg);
476 addr += size;
477 }
dfabb8b9 478}
76b5d850 479
5b009e40
HZ
480static void numa_stat_memory_devices(uint64_t node_mem[])
481{
482 MemoryDeviceInfoList *info_list = NULL;
483 MemoryDeviceInfoList **prev = &info_list;
484 MemoryDeviceInfoList *info;
485
486 qmp_pc_dimm_device_list(qdev_get_machine(), &prev);
487 for (info = info_list; info; info = info->next) {
488 MemoryDeviceInfo *value = info->value;
489
490 if (value) {
1fd5d4fe 491 switch (value->type) {
5b009e40 492 case MEMORY_DEVICE_INFO_KIND_DIMM:
32bafa8f 493 node_mem[value->u.dimm.data->node] += value->u.dimm.data->size;
5b009e40
HZ
494 break;
495 default:
496 break;
497 }
498 }
499 }
500 qapi_free_MemoryDeviceInfoList(info_list);
501}
502
503void query_numa_node_mem(uint64_t node_mem[])
504{
505 int i;
506
507 if (nb_numa_nodes <= 0) {
508 return;
509 }
510
511 numa_stat_memory_devices(node_mem);
512 for (i = 0; i < nb_numa_nodes; i++) {
513 node_mem[i] += numa_info[i].node_mem;
514 }
515}
516
76b5d850
HT
517static int query_memdev(Object *obj, void *opaque)
518{
519 MemdevList **list = opaque;
b0e90181 520 MemdevList *m = NULL;
76b5d850
HT
521
522 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
b0e90181 523 m = g_malloc0(sizeof(*m));
76b5d850
HT
524
525 m->value = g_malloc0(sizeof(*m->value));
526
e1ff3c67
IM
527 m->value->id = object_property_get_str(obj, "id", NULL);
528 m->value->has_id = !!m->value->id;
529
76b5d850 530 m->value->size = object_property_get_int(obj, "size",
2f6f826e 531 &error_abort);
76b5d850 532 m->value->merge = object_property_get_bool(obj, "merge",
2f6f826e 533 &error_abort);
76b5d850 534 m->value->dump = object_property_get_bool(obj, "dump",
2f6f826e 535 &error_abort);
76b5d850 536 m->value->prealloc = object_property_get_bool(obj,
2f6f826e
MA
537 "prealloc",
538 &error_abort);
76b5d850
HT
539 m->value->policy = object_property_get_enum(obj,
540 "policy",
a3590dac 541 "HostMemPolicy",
2f6f826e 542 &error_abort);
76b5d850 543 object_property_get_uint16List(obj, "host-nodes",
2f6f826e
MA
544 &m->value->host_nodes,
545 &error_abort);
76b5d850
HT
546
547 m->next = *list;
548 *list = m;
549 }
550
551 return 0;
76b5d850
HT
552}
553
554MemdevList *qmp_query_memdev(Error **errp)
555{
2f6f826e 556 Object *obj = object_get_objects_root();
ecaf54a0 557 MemdevList *list = NULL;
76b5d850 558
2f6f826e 559 object_child_foreach(obj, query_memdev, &list);
76b5d850 560 return list;
76b5d850 561}
6bea1ddf
IM
562
563int numa_get_node_for_cpu(int idx)
564{
565 int i;
566
cdda2018
IM
567 assert(idx < max_cpus);
568
6bea1ddf
IM
569 for (i = 0; i < nb_numa_nodes; i++) {
570 if (test_bit(idx, numa_info[i].node_cpu)) {
571 break;
572 }
573 }
574 return i;
575}
0987d735
PB
576
577void ram_block_notifier_add(RAMBlockNotifier *n)
578{
579 QLIST_INSERT_HEAD(&ram_list.ramblock_notifiers, n, next);
580}
581
582void ram_block_notifier_remove(RAMBlockNotifier *n)
583{
584 QLIST_REMOVE(n, next);
585}
586
587void ram_block_notify_add(void *host, size_t size)
588{
589 RAMBlockNotifier *notifier;
590
591 QLIST_FOREACH(notifier, &ram_list.ramblock_notifiers, next) {
592 notifier->ram_block_added(notifier, host, size);
593 }
594}
595
596void ram_block_notify_remove(void *host, size_t size)
597{
598 RAMBlockNotifier *notifier;
599
600 QLIST_FOREACH(notifier, &ram_list.ramblock_notifiers, next) {
601 notifier->ram_block_removed(notifier, host, size);
602 }
603}