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CommitLineData
96d0e26c
WG
1/*
2 * NUMA parameter parsing routines
3 *
4 * Copyright (c) 2014 Fujitsu Ltd.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
e35704ba 25#include "sysemu/numa.h"
96d0e26c
WG
26#include "exec/cpu-common.h"
27#include "qemu/bitmap.h"
28#include "qom/cpu.h"
2b631ec2
WG
29#include "qemu/error-report.h"
30#include "include/exec/cpu-common.h" /* for RAM_ADDR_FMT */
0042109a
WG
31#include "qapi-visit.h"
32#include "qapi/opts-visitor.h"
33#include "qapi/dealloc-visitor.h"
dfabb8b9 34#include "hw/boards.h"
7febe36f 35#include "sysemu/hostmem.h"
76b5d850 36#include "qmp-commands.h"
5b009e40 37#include "hw/mem/pc-dimm.h"
7dcd1d70
EH
38#include "qemu/option.h"
39#include "qemu/config-file.h"
0042109a
WG
40
41QemuOptsList qemu_numa_opts = {
42 .name = "numa",
43 .implied_opt_name = "type",
44 .head = QTAILQ_HEAD_INITIALIZER(qemu_numa_opts.head),
45 .desc = { { 0 } } /* validated with OptsVisitor */
46};
47
7febe36f 48static int have_memdevs = -1;
25712ffe
EH
49static int max_numa_nodeid; /* Highest specified NUMA node ID, plus one.
50 * For all nodes, nodeid < max_numa_nodeid
51 */
de1a7c84 52int nb_numa_nodes;
de1a7c84 53NodeInfo numa_info[MAX_NODES];
7febe36f 54
fa9ea81d
BR
55void numa_set_mem_node_id(ram_addr_t addr, uint64_t size, uint32_t node)
56{
57 struct numa_addr_range *range = g_malloc0(sizeof(*range));
58
abafabd8
BR
59 /*
60 * Memory-less nodes can come here with 0 size in which case,
61 * there is nothing to do.
62 */
63 if (!size) {
64 return;
65 }
66
fa9ea81d
BR
67 range->mem_start = addr;
68 range->mem_end = addr + size - 1;
69 QLIST_INSERT_HEAD(&numa_info[node].addr, range, entry);
70}
71
72void numa_unset_mem_node_id(ram_addr_t addr, uint64_t size, uint32_t node)
73{
74 struct numa_addr_range *range, *next;
75
76 QLIST_FOREACH_SAFE(range, &numa_info[node].addr, entry, next) {
77 if (addr == range->mem_start && (addr + size - 1) == range->mem_end) {
78 QLIST_REMOVE(range, entry);
79 g_free(range);
80 return;
81 }
82 }
83}
84
abafabd8
BR
85static void numa_set_mem_ranges(void)
86{
87 int i;
88 ram_addr_t mem_start = 0;
89
90 /*
91 * Deduce start address of each node and use it to store
92 * the address range info in numa_info address range list
93 */
94 for (i = 0; i < nb_numa_nodes; i++) {
95 numa_set_mem_node_id(mem_start, numa_info[i].node_mem, i);
96 mem_start += numa_info[i].node_mem;
97 }
98}
99
e75e2a14
BR
100/*
101 * Check if @addr falls under NUMA @node.
102 */
103static bool numa_addr_belongs_to_node(ram_addr_t addr, uint32_t node)
104{
105 struct numa_addr_range *range;
106
107 QLIST_FOREACH(range, &numa_info[node].addr, entry) {
108 if (addr >= range->mem_start && addr <= range->mem_end) {
109 return true;
110 }
111 }
112 return false;
113}
114
115/*
116 * Given an address, return the index of the NUMA node to which the
117 * address belongs to.
118 */
119uint32_t numa_get_node(ram_addr_t addr, Error **errp)
120{
121 uint32_t i;
122
123 /* For non NUMA configurations, check if the addr falls under node 0 */
124 if (!nb_numa_nodes) {
125 if (numa_addr_belongs_to_node(addr, 0)) {
126 return 0;
127 }
128 }
129
130 for (i = 0; i < nb_numa_nodes; i++) {
131 if (numa_addr_belongs_to_node(addr, i)) {
132 return i;
133 }
134 }
135
136 error_setg(errp, "Address 0x" RAM_ADDR_FMT " doesn't belong to any "
137 "NUMA node", addr);
138 return -1;
139}
140
0042109a 141static void numa_node_parse(NumaNodeOptions *node, QemuOpts *opts, Error **errp)
96d0e26c 142{
0042109a
WG
143 uint16_t nodenr;
144 uint16List *cpus = NULL;
96d0e26c 145
0042109a
WG
146 if (node->has_nodeid) {
147 nodenr = node->nodeid;
96d0e26c 148 } else {
0042109a 149 nodenr = nb_numa_nodes;
96d0e26c
WG
150 }
151
0042109a
WG
152 if (nodenr >= MAX_NODES) {
153 error_setg(errp, "Max number of NUMA nodes reached: %"
01bbbcf4 154 PRIu16 "", nodenr);
0042109a 155 return;
96d0e26c
WG
156 }
157
1945b9d8
EH
158 if (numa_info[nodenr].present) {
159 error_setg(errp, "Duplicate NUMA nodeid: %" PRIu16, nodenr);
160 return;
161 }
162
0042109a 163 for (cpus = node->cpus; cpus; cpus = cpus->next) {
8979c945
EH
164 if (cpus->value >= max_cpus) {
165 error_setg(errp,
166 "CPU index (%" PRIu16 ")"
167 " should be smaller than maxcpus (%d)",
168 cpus->value, max_cpus);
0042109a
WG
169 return;
170 }
171 bitmap_set(numa_info[nodenr].node_cpu, cpus->value, 1);
96d0e26c
WG
172 }
173
7febe36f 174 if (node->has_mem && node->has_memdev) {
01bbbcf4 175 error_setg(errp, "qemu: cannot specify both mem= and memdev=");
7febe36f
PB
176 return;
177 }
178
179 if (have_memdevs == -1) {
180 have_memdevs = node->has_memdev;
181 }
182 if (node->has_memdev != have_memdevs) {
183 error_setg(errp, "qemu: memdev option must be specified for either "
01bbbcf4 184 "all or no nodes");
7febe36f
PB
185 return;
186 }
187
0042109a
WG
188 if (node->has_mem) {
189 uint64_t mem_size = node->mem;
190 const char *mem_str = qemu_opt_get(opts, "mem");
191 /* Fix up legacy suffix-less format */
192 if (g_ascii_isdigit(mem_str[strlen(mem_str) - 1])) {
193 mem_size <<= 20;
194 }
195 numa_info[nodenr].node_mem = mem_size;
196 }
7febe36f
PB
197 if (node->has_memdev) {
198 Object *o;
199 o = object_resolve_path_type(node->memdev, TYPE_MEMORY_BACKEND, NULL);
200 if (!o) {
201 error_setg(errp, "memdev=%s is ambiguous", node->memdev);
202 return;
203 }
204
205 object_ref(o);
206 numa_info[nodenr].node_mem = object_property_get_int(o, "size", NULL);
207 numa_info[nodenr].node_memdev = MEMORY_BACKEND(o);
208 }
1af878e0
EH
209 numa_info[nodenr].present = true;
210 max_numa_nodeid = MAX(max_numa_nodeid, nodenr + 1);
96d0e26c
WG
211}
212
28d0de7a 213static int parse_numa(void *opaque, QemuOpts *opts, Error **errp)
96d0e26c 214{
0042109a
WG
215 NumaOptions *object = NULL;
216 Error *err = NULL;
96d0e26c 217
0042109a
WG
218 {
219 OptsVisitor *ov = opts_visitor_new(opts);
220 visit_type_NumaOptions(opts_get_visitor(ov), &object, NULL, &err);
221 opts_visitor_cleanup(ov);
96d0e26c 222 }
96d0e26c 223
0042109a
WG
224 if (err) {
225 goto error;
226 }
96d0e26c 227
0042109a
WG
228 switch (object->kind) {
229 case NUMA_OPTIONS_KIND_NODE:
230 numa_node_parse(object->node, opts, &err);
231 if (err) {
232 goto error;
96d0e26c 233 }
0042109a
WG
234 nb_numa_nodes++;
235 break;
236 default:
237 abort();
238 }
96d0e26c 239
0042109a 240 return 0;
96d0e26c 241
0042109a 242error:
29b762f5 243 error_report_err(err);
0042109a
WG
244
245 if (object) {
246 QapiDeallocVisitor *dv = qapi_dealloc_visitor_new();
247 visit_type_NumaOptions(qapi_dealloc_get_visitor(dv),
248 &object, NULL, NULL);
249 qapi_dealloc_visitor_cleanup(dv);
96d0e26c 250 }
0042109a
WG
251
252 return -1;
96d0e26c
WG
253}
254
3ef71975
EH
255static char *enumerate_cpus(unsigned long *cpus, int max_cpus)
256{
257 int cpu;
258 bool first = true;
259 GString *s = g_string_new(NULL);
260
261 for (cpu = find_first_bit(cpus, max_cpus);
262 cpu < max_cpus;
263 cpu = find_next_bit(cpus, max_cpus, cpu + 1)) {
264 g_string_append_printf(s, "%s%d", first ? "" : " ", cpu);
265 first = false;
266 }
267 return g_string_free(s, FALSE);
268}
269
270static void validate_numa_cpus(void)
271{
272 int i;
273 DECLARE_BITMAP(seen_cpus, MAX_CPUMASK_BITS);
274
275 bitmap_zero(seen_cpus, MAX_CPUMASK_BITS);
276 for (i = 0; i < nb_numa_nodes; i++) {
277 if (bitmap_intersects(seen_cpus, numa_info[i].node_cpu,
278 MAX_CPUMASK_BITS)) {
279 bitmap_and(seen_cpus, seen_cpus,
280 numa_info[i].node_cpu, MAX_CPUMASK_BITS);
281 error_report("CPU(s) present in multiple NUMA nodes: %s",
282 enumerate_cpus(seen_cpus, max_cpus));;
283 exit(EXIT_FAILURE);
284 }
285 bitmap_or(seen_cpus, seen_cpus,
286 numa_info[i].node_cpu, MAX_CPUMASK_BITS);
287 }
549fc54b
EH
288
289 if (!bitmap_full(seen_cpus, max_cpus)) {
290 char *msg;
291 bitmap_complement(seen_cpus, seen_cpus, max_cpus);
292 msg = enumerate_cpus(seen_cpus, max_cpus);
293 error_report("warning: CPU(s) not present in any NUMA nodes: %s", msg);
294 error_report("warning: All CPU(s) up to maxcpus should be described "
295 "in NUMA config");
296 g_free(msg);
297 }
3ef71975
EH
298}
299
57924bcd 300void parse_numa_opts(MachineClass *mc)
96d0e26c 301{
12d6e464
EH
302 int i;
303
28d0de7a 304 if (qemu_opts_foreach(qemu_find_opts("numa"), parse_numa, NULL, NULL)) {
7dcd1d70
EH
305 exit(1);
306 }
307
12d6e464
EH
308 assert(max_numa_nodeid <= MAX_NODES);
309
310 /* No support for sparse NUMA node IDs yet: */
311 for (i = max_numa_nodeid - 1; i >= 0; i--) {
312 /* Report large node IDs first, to make mistakes easier to spot */
313 if (!numa_info[i].present) {
314 error_report("numa: Node ID missing: %d", i);
315 exit(1);
316 }
317 }
318
319 /* This must be always true if all nodes are present: */
320 assert(nb_numa_nodes == max_numa_nodeid);
321
96d0e26c 322 if (nb_numa_nodes > 0) {
2b631ec2 323 uint64_t numa_total;
96d0e26c
WG
324
325 if (nb_numa_nodes > MAX_NODES) {
326 nb_numa_nodes = MAX_NODES;
327 }
328
9851d0fe 329 /* If no memory size is given for any node, assume the default case
96d0e26c
WG
330 * and distribute the available memory equally across all nodes
331 */
332 for (i = 0; i < nb_numa_nodes; i++) {
8c85901e 333 if (numa_info[i].node_mem != 0) {
96d0e26c
WG
334 break;
335 }
336 }
337 if (i == nb_numa_nodes) {
338 uint64_t usedmem = 0;
339
d75e2f68 340 /* On Linux, each node's border has to be 8MB aligned,
96d0e26c
WG
341 * the final node gets the rest.
342 */
343 for (i = 0; i < nb_numa_nodes - 1; i++) {
8c85901e
WG
344 numa_info[i].node_mem = (ram_size / nb_numa_nodes) &
345 ~((1 << 23UL) - 1);
346 usedmem += numa_info[i].node_mem;
96d0e26c 347 }
8c85901e 348 numa_info[i].node_mem = ram_size - usedmem;
96d0e26c
WG
349 }
350
2b631ec2
WG
351 numa_total = 0;
352 for (i = 0; i < nb_numa_nodes; i++) {
8c85901e 353 numa_total += numa_info[i].node_mem;
2b631ec2
WG
354 }
355 if (numa_total != ram_size) {
c68233ae
HT
356 error_report("total memory for NUMA nodes (0x%" PRIx64 ")"
357 " should equal RAM size (0x" RAM_ADDR_FMT ")",
2b631ec2
WG
358 numa_total, ram_size);
359 exit(1);
360 }
361
fa9ea81d
BR
362 for (i = 0; i < nb_numa_nodes; i++) {
363 QLIST_INIT(&numa_info[i].addr);
364 }
365
abafabd8
BR
366 numa_set_mem_ranges();
367
96d0e26c 368 for (i = 0; i < nb_numa_nodes; i++) {
8c85901e 369 if (!bitmap_empty(numa_info[i].node_cpu, MAX_CPUMASK_BITS)) {
96d0e26c
WG
370 break;
371 }
372 }
57924bcd
IM
373 /* Historically VCPUs were assigned in round-robin order to NUMA
374 * nodes. However it causes issues with guest not handling it nice
375 * in case where cores/threads from a multicore CPU appear on
376 * different nodes. So allow boards to override default distribution
377 * rule grouping VCPUs by socket so that VCPUs from the same socket
378 * would be on the same node.
96d0e26c
WG
379 */
380 if (i == nb_numa_nodes) {
381 for (i = 0; i < max_cpus; i++) {
57924bcd
IM
382 unsigned node_id = i % nb_numa_nodes;
383 if (mc->cpu_index_to_socket_id) {
384 node_id = mc->cpu_index_to_socket_id(i) % nb_numa_nodes;
385 }
386
387 set_bit(i, numa_info[node_id].node_cpu);
96d0e26c
WG
388 }
389 }
3ef71975
EH
390
391 validate_numa_cpus();
abafabd8
BR
392 } else {
393 numa_set_mem_node_id(0, ram_size, 0);
96d0e26c
WG
394 }
395}
396
dde11116 397void numa_post_machine_init(void)
96d0e26c
WG
398{
399 CPUState *cpu;
400 int i;
401
402 CPU_FOREACH(cpu) {
403 for (i = 0; i < nb_numa_nodes; i++) {
8c85901e 404 if (test_bit(cpu->cpu_index, numa_info[i].node_cpu)) {
96d0e26c
WG
405 cpu->numa_node = i;
406 }
407 }
408 }
409}
dfabb8b9 410
7febe36f
PB
411static void allocate_system_memory_nonnuma(MemoryRegion *mr, Object *owner,
412 const char *name,
413 uint64_t ram_size)
414{
0b183fc8
PB
415 if (mem_path) {
416#ifdef __linux__
7f56e740 417 Error *err = NULL;
dbcb8981 418 memory_region_init_ram_from_file(mr, owner, name, ram_size, false,
7f56e740
PB
419 mem_path, &err);
420
421 /* Legacy behavior: if allocation failed, fall back to
422 * regular RAM allocation.
423 */
c3ba3095 424 if (err) {
29b762f5 425 error_report_err(err);
49946538 426 memory_region_init_ram(mr, owner, name, ram_size, &error_abort);
7f56e740 427 }
0b183fc8
PB
428#else
429 fprintf(stderr, "-mem-path not supported on this host\n");
430 exit(1);
431#endif
432 } else {
49946538 433 memory_region_init_ram(mr, owner, name, ram_size, &error_abort);
0b183fc8 434 }
7febe36f
PB
435 vmstate_register_ram_global(mr);
436}
437
dfabb8b9
PB
438void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner,
439 const char *name,
440 uint64_t ram_size)
441{
7febe36f
PB
442 uint64_t addr = 0;
443 int i;
444
445 if (nb_numa_nodes == 0 || !have_memdevs) {
446 allocate_system_memory_nonnuma(mr, owner, name, ram_size);
447 return;
448 }
449
450 memory_region_init(mr, owner, name, ram_size);
451 for (i = 0; i < MAX_NODES; i++) {
452 Error *local_err = NULL;
453 uint64_t size = numa_info[i].node_mem;
454 HostMemoryBackend *backend = numa_info[i].node_memdev;
455 if (!backend) {
456 continue;
457 }
458 MemoryRegion *seg = host_memory_backend_get_memory(backend, &local_err);
459 if (local_err) {
29b762f5 460 error_report_err(local_err);
7febe36f
PB
461 exit(1);
462 }
463
0462faee
HT
464 if (memory_region_is_mapped(seg)) {
465 char *path = object_get_canonical_path_component(OBJECT(backend));
466 error_report("memory backend %s is used multiple times. Each "
467 "-numa option must use a different memdev value.",
468 path);
469 exit(1);
470 }
471
7febe36f
PB
472 memory_region_add_subregion(mr, addr, seg);
473 vmstate_register_ram_global(seg);
474 addr += size;
475 }
dfabb8b9 476}
76b5d850 477
5b009e40
HZ
478static void numa_stat_memory_devices(uint64_t node_mem[])
479{
480 MemoryDeviceInfoList *info_list = NULL;
481 MemoryDeviceInfoList **prev = &info_list;
482 MemoryDeviceInfoList *info;
483
484 qmp_pc_dimm_device_list(qdev_get_machine(), &prev);
485 for (info = info_list; info; info = info->next) {
486 MemoryDeviceInfo *value = info->value;
487
488 if (value) {
489 switch (value->kind) {
490 case MEMORY_DEVICE_INFO_KIND_DIMM:
491 node_mem[value->dimm->node] += value->dimm->size;
492 break;
493 default:
494 break;
495 }
496 }
497 }
498 qapi_free_MemoryDeviceInfoList(info_list);
499}
500
501void query_numa_node_mem(uint64_t node_mem[])
502{
503 int i;
504
505 if (nb_numa_nodes <= 0) {
506 return;
507 }
508
509 numa_stat_memory_devices(node_mem);
510 for (i = 0; i < nb_numa_nodes; i++) {
511 node_mem[i] += numa_info[i].node_mem;
512 }
513}
514
76b5d850
HT
515static int query_memdev(Object *obj, void *opaque)
516{
517 MemdevList **list = opaque;
b0e90181 518 MemdevList *m = NULL;
76b5d850
HT
519 Error *err = NULL;
520
521 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
b0e90181 522 m = g_malloc0(sizeof(*m));
76b5d850
HT
523
524 m->value = g_malloc0(sizeof(*m->value));
525
526 m->value->size = object_property_get_int(obj, "size",
527 &err);
528 if (err) {
529 goto error;
530 }
531
532 m->value->merge = object_property_get_bool(obj, "merge",
533 &err);
534 if (err) {
535 goto error;
536 }
537
538 m->value->dump = object_property_get_bool(obj, "dump",
539 &err);
540 if (err) {
541 goto error;
542 }
543
544 m->value->prealloc = object_property_get_bool(obj,
545 "prealloc", &err);
546 if (err) {
547 goto error;
548 }
549
550 m->value->policy = object_property_get_enum(obj,
551 "policy",
a3590dac 552 "HostMemPolicy",
76b5d850
HT
553 &err);
554 if (err) {
555 goto error;
556 }
557
558 object_property_get_uint16List(obj, "host-nodes",
559 &m->value->host_nodes, &err);
560 if (err) {
561 goto error;
562 }
563
564 m->next = *list;
565 *list = m;
566 }
567
568 return 0;
569error:
b0e90181
CF
570 g_free(m->value);
571 g_free(m);
572
76b5d850
HT
573 return -1;
574}
575
576MemdevList *qmp_query_memdev(Error **errp)
577{
578 Object *obj;
ecaf54a0 579 MemdevList *list = NULL;
76b5d850 580
bc2256c4 581 obj = object_get_objects_root();
76b5d850
HT
582 if (obj == NULL) {
583 return NULL;
584 }
585
586 if (object_child_foreach(obj, query_memdev, &list) != 0) {
587 goto error;
588 }
589
590 return list;
591
592error:
ecaf54a0 593 qapi_free_MemdevList(list);
76b5d850
HT
594 return NULL;
595}