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Commit | Line | Data |
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96d0e26c WG |
1 | /* |
2 | * NUMA parameter parsing routines | |
3 | * | |
4 | * Copyright (c) 2014 Fujitsu Ltd. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
e35704ba | 25 | #include "sysemu/numa.h" |
96d0e26c WG |
26 | #include "exec/cpu-common.h" |
27 | #include "qemu/bitmap.h" | |
28 | #include "qom/cpu.h" | |
2b631ec2 WG |
29 | #include "qemu/error-report.h" |
30 | #include "include/exec/cpu-common.h" /* for RAM_ADDR_FMT */ | |
0042109a WG |
31 | #include "qapi-visit.h" |
32 | #include "qapi/opts-visitor.h" | |
33 | #include "qapi/dealloc-visitor.h" | |
dfabb8b9 | 34 | #include "hw/boards.h" |
7febe36f | 35 | #include "sysemu/hostmem.h" |
76b5d850 | 36 | #include "qmp-commands.h" |
5b009e40 | 37 | #include "hw/mem/pc-dimm.h" |
7dcd1d70 EH |
38 | #include "qemu/option.h" |
39 | #include "qemu/config-file.h" | |
0042109a WG |
40 | |
41 | QemuOptsList qemu_numa_opts = { | |
42 | .name = "numa", | |
43 | .implied_opt_name = "type", | |
44 | .head = QTAILQ_HEAD_INITIALIZER(qemu_numa_opts.head), | |
45 | .desc = { { 0 } } /* validated with OptsVisitor */ | |
46 | }; | |
47 | ||
7febe36f | 48 | static int have_memdevs = -1; |
25712ffe EH |
49 | static int max_numa_nodeid; /* Highest specified NUMA node ID, plus one. |
50 | * For all nodes, nodeid < max_numa_nodeid | |
51 | */ | |
de1a7c84 | 52 | int nb_numa_nodes; |
de1a7c84 | 53 | NodeInfo numa_info[MAX_NODES]; |
7febe36f | 54 | |
fa9ea81d BR |
55 | void numa_set_mem_node_id(ram_addr_t addr, uint64_t size, uint32_t node) |
56 | { | |
57 | struct numa_addr_range *range = g_malloc0(sizeof(*range)); | |
58 | ||
abafabd8 BR |
59 | /* |
60 | * Memory-less nodes can come here with 0 size in which case, | |
61 | * there is nothing to do. | |
62 | */ | |
63 | if (!size) { | |
64 | return; | |
65 | } | |
66 | ||
fa9ea81d BR |
67 | range->mem_start = addr; |
68 | range->mem_end = addr + size - 1; | |
69 | QLIST_INSERT_HEAD(&numa_info[node].addr, range, entry); | |
70 | } | |
71 | ||
72 | void numa_unset_mem_node_id(ram_addr_t addr, uint64_t size, uint32_t node) | |
73 | { | |
74 | struct numa_addr_range *range, *next; | |
75 | ||
76 | QLIST_FOREACH_SAFE(range, &numa_info[node].addr, entry, next) { | |
77 | if (addr == range->mem_start && (addr + size - 1) == range->mem_end) { | |
78 | QLIST_REMOVE(range, entry); | |
79 | g_free(range); | |
80 | return; | |
81 | } | |
82 | } | |
83 | } | |
84 | ||
abafabd8 BR |
85 | static void numa_set_mem_ranges(void) |
86 | { | |
87 | int i; | |
88 | ram_addr_t mem_start = 0; | |
89 | ||
90 | /* | |
91 | * Deduce start address of each node and use it to store | |
92 | * the address range info in numa_info address range list | |
93 | */ | |
94 | for (i = 0; i < nb_numa_nodes; i++) { | |
95 | numa_set_mem_node_id(mem_start, numa_info[i].node_mem, i); | |
96 | mem_start += numa_info[i].node_mem; | |
97 | } | |
98 | } | |
99 | ||
0042109a | 100 | static void numa_node_parse(NumaNodeOptions *node, QemuOpts *opts, Error **errp) |
96d0e26c | 101 | { |
0042109a WG |
102 | uint16_t nodenr; |
103 | uint16List *cpus = NULL; | |
96d0e26c | 104 | |
0042109a WG |
105 | if (node->has_nodeid) { |
106 | nodenr = node->nodeid; | |
96d0e26c | 107 | } else { |
0042109a | 108 | nodenr = nb_numa_nodes; |
96d0e26c WG |
109 | } |
110 | ||
0042109a WG |
111 | if (nodenr >= MAX_NODES) { |
112 | error_setg(errp, "Max number of NUMA nodes reached: %" | |
01bbbcf4 | 113 | PRIu16 "", nodenr); |
0042109a | 114 | return; |
96d0e26c WG |
115 | } |
116 | ||
1945b9d8 EH |
117 | if (numa_info[nodenr].present) { |
118 | error_setg(errp, "Duplicate NUMA nodeid: %" PRIu16, nodenr); | |
119 | return; | |
120 | } | |
121 | ||
0042109a | 122 | for (cpus = node->cpus; cpus; cpus = cpus->next) { |
8979c945 EH |
123 | if (cpus->value >= max_cpus) { |
124 | error_setg(errp, | |
125 | "CPU index (%" PRIu16 ")" | |
126 | " should be smaller than maxcpus (%d)", | |
127 | cpus->value, max_cpus); | |
0042109a WG |
128 | return; |
129 | } | |
130 | bitmap_set(numa_info[nodenr].node_cpu, cpus->value, 1); | |
96d0e26c WG |
131 | } |
132 | ||
7febe36f | 133 | if (node->has_mem && node->has_memdev) { |
01bbbcf4 | 134 | error_setg(errp, "qemu: cannot specify both mem= and memdev="); |
7febe36f PB |
135 | return; |
136 | } | |
137 | ||
138 | if (have_memdevs == -1) { | |
139 | have_memdevs = node->has_memdev; | |
140 | } | |
141 | if (node->has_memdev != have_memdevs) { | |
142 | error_setg(errp, "qemu: memdev option must be specified for either " | |
01bbbcf4 | 143 | "all or no nodes"); |
7febe36f PB |
144 | return; |
145 | } | |
146 | ||
0042109a WG |
147 | if (node->has_mem) { |
148 | uint64_t mem_size = node->mem; | |
149 | const char *mem_str = qemu_opt_get(opts, "mem"); | |
150 | /* Fix up legacy suffix-less format */ | |
151 | if (g_ascii_isdigit(mem_str[strlen(mem_str) - 1])) { | |
152 | mem_size <<= 20; | |
153 | } | |
154 | numa_info[nodenr].node_mem = mem_size; | |
155 | } | |
7febe36f PB |
156 | if (node->has_memdev) { |
157 | Object *o; | |
158 | o = object_resolve_path_type(node->memdev, TYPE_MEMORY_BACKEND, NULL); | |
159 | if (!o) { | |
160 | error_setg(errp, "memdev=%s is ambiguous", node->memdev); | |
161 | return; | |
162 | } | |
163 | ||
164 | object_ref(o); | |
165 | numa_info[nodenr].node_mem = object_property_get_int(o, "size", NULL); | |
166 | numa_info[nodenr].node_memdev = MEMORY_BACKEND(o); | |
167 | } | |
1af878e0 EH |
168 | numa_info[nodenr].present = true; |
169 | max_numa_nodeid = MAX(max_numa_nodeid, nodenr + 1); | |
96d0e26c WG |
170 | } |
171 | ||
28d0de7a | 172 | static int parse_numa(void *opaque, QemuOpts *opts, Error **errp) |
96d0e26c | 173 | { |
0042109a WG |
174 | NumaOptions *object = NULL; |
175 | Error *err = NULL; | |
96d0e26c | 176 | |
0042109a WG |
177 | { |
178 | OptsVisitor *ov = opts_visitor_new(opts); | |
179 | visit_type_NumaOptions(opts_get_visitor(ov), &object, NULL, &err); | |
180 | opts_visitor_cleanup(ov); | |
96d0e26c | 181 | } |
96d0e26c | 182 | |
0042109a WG |
183 | if (err) { |
184 | goto error; | |
185 | } | |
96d0e26c | 186 | |
0042109a WG |
187 | switch (object->kind) { |
188 | case NUMA_OPTIONS_KIND_NODE: | |
189 | numa_node_parse(object->node, opts, &err); | |
190 | if (err) { | |
191 | goto error; | |
96d0e26c | 192 | } |
0042109a WG |
193 | nb_numa_nodes++; |
194 | break; | |
195 | default: | |
196 | abort(); | |
197 | } | |
96d0e26c | 198 | |
0042109a | 199 | return 0; |
96d0e26c | 200 | |
0042109a | 201 | error: |
29b762f5 | 202 | error_report_err(err); |
0042109a WG |
203 | |
204 | if (object) { | |
205 | QapiDeallocVisitor *dv = qapi_dealloc_visitor_new(); | |
206 | visit_type_NumaOptions(qapi_dealloc_get_visitor(dv), | |
207 | &object, NULL, NULL); | |
208 | qapi_dealloc_visitor_cleanup(dv); | |
96d0e26c | 209 | } |
0042109a WG |
210 | |
211 | return -1; | |
96d0e26c WG |
212 | } |
213 | ||
3ef71975 EH |
214 | static char *enumerate_cpus(unsigned long *cpus, int max_cpus) |
215 | { | |
216 | int cpu; | |
217 | bool first = true; | |
218 | GString *s = g_string_new(NULL); | |
219 | ||
220 | for (cpu = find_first_bit(cpus, max_cpus); | |
221 | cpu < max_cpus; | |
222 | cpu = find_next_bit(cpus, max_cpus, cpu + 1)) { | |
223 | g_string_append_printf(s, "%s%d", first ? "" : " ", cpu); | |
224 | first = false; | |
225 | } | |
226 | return g_string_free(s, FALSE); | |
227 | } | |
228 | ||
229 | static void validate_numa_cpus(void) | |
230 | { | |
231 | int i; | |
232 | DECLARE_BITMAP(seen_cpus, MAX_CPUMASK_BITS); | |
233 | ||
234 | bitmap_zero(seen_cpus, MAX_CPUMASK_BITS); | |
235 | for (i = 0; i < nb_numa_nodes; i++) { | |
236 | if (bitmap_intersects(seen_cpus, numa_info[i].node_cpu, | |
237 | MAX_CPUMASK_BITS)) { | |
238 | bitmap_and(seen_cpus, seen_cpus, | |
239 | numa_info[i].node_cpu, MAX_CPUMASK_BITS); | |
240 | error_report("CPU(s) present in multiple NUMA nodes: %s", | |
241 | enumerate_cpus(seen_cpus, max_cpus));; | |
242 | exit(EXIT_FAILURE); | |
243 | } | |
244 | bitmap_or(seen_cpus, seen_cpus, | |
245 | numa_info[i].node_cpu, MAX_CPUMASK_BITS); | |
246 | } | |
549fc54b EH |
247 | |
248 | if (!bitmap_full(seen_cpus, max_cpus)) { | |
249 | char *msg; | |
250 | bitmap_complement(seen_cpus, seen_cpus, max_cpus); | |
251 | msg = enumerate_cpus(seen_cpus, max_cpus); | |
252 | error_report("warning: CPU(s) not present in any NUMA nodes: %s", msg); | |
253 | error_report("warning: All CPU(s) up to maxcpus should be described " | |
254 | "in NUMA config"); | |
255 | g_free(msg); | |
256 | } | |
3ef71975 EH |
257 | } |
258 | ||
57924bcd | 259 | void parse_numa_opts(MachineClass *mc) |
96d0e26c | 260 | { |
12d6e464 EH |
261 | int i; |
262 | ||
28d0de7a | 263 | if (qemu_opts_foreach(qemu_find_opts("numa"), parse_numa, NULL, NULL)) { |
7dcd1d70 EH |
264 | exit(1); |
265 | } | |
266 | ||
12d6e464 EH |
267 | assert(max_numa_nodeid <= MAX_NODES); |
268 | ||
269 | /* No support for sparse NUMA node IDs yet: */ | |
270 | for (i = max_numa_nodeid - 1; i >= 0; i--) { | |
271 | /* Report large node IDs first, to make mistakes easier to spot */ | |
272 | if (!numa_info[i].present) { | |
273 | error_report("numa: Node ID missing: %d", i); | |
274 | exit(1); | |
275 | } | |
276 | } | |
277 | ||
278 | /* This must be always true if all nodes are present: */ | |
279 | assert(nb_numa_nodes == max_numa_nodeid); | |
280 | ||
96d0e26c | 281 | if (nb_numa_nodes > 0) { |
2b631ec2 | 282 | uint64_t numa_total; |
96d0e26c WG |
283 | |
284 | if (nb_numa_nodes > MAX_NODES) { | |
285 | nb_numa_nodes = MAX_NODES; | |
286 | } | |
287 | ||
9851d0fe | 288 | /* If no memory size is given for any node, assume the default case |
96d0e26c WG |
289 | * and distribute the available memory equally across all nodes |
290 | */ | |
291 | for (i = 0; i < nb_numa_nodes; i++) { | |
8c85901e | 292 | if (numa_info[i].node_mem != 0) { |
96d0e26c WG |
293 | break; |
294 | } | |
295 | } | |
296 | if (i == nb_numa_nodes) { | |
297 | uint64_t usedmem = 0; | |
298 | ||
d75e2f68 | 299 | /* On Linux, each node's border has to be 8MB aligned, |
96d0e26c WG |
300 | * the final node gets the rest. |
301 | */ | |
302 | for (i = 0; i < nb_numa_nodes - 1; i++) { | |
8c85901e WG |
303 | numa_info[i].node_mem = (ram_size / nb_numa_nodes) & |
304 | ~((1 << 23UL) - 1); | |
305 | usedmem += numa_info[i].node_mem; | |
96d0e26c | 306 | } |
8c85901e | 307 | numa_info[i].node_mem = ram_size - usedmem; |
96d0e26c WG |
308 | } |
309 | ||
2b631ec2 WG |
310 | numa_total = 0; |
311 | for (i = 0; i < nb_numa_nodes; i++) { | |
8c85901e | 312 | numa_total += numa_info[i].node_mem; |
2b631ec2 WG |
313 | } |
314 | if (numa_total != ram_size) { | |
c68233ae HT |
315 | error_report("total memory for NUMA nodes (0x%" PRIx64 ")" |
316 | " should equal RAM size (0x" RAM_ADDR_FMT ")", | |
2b631ec2 WG |
317 | numa_total, ram_size); |
318 | exit(1); | |
319 | } | |
320 | ||
fa9ea81d BR |
321 | for (i = 0; i < nb_numa_nodes; i++) { |
322 | QLIST_INIT(&numa_info[i].addr); | |
323 | } | |
324 | ||
abafabd8 BR |
325 | numa_set_mem_ranges(); |
326 | ||
96d0e26c | 327 | for (i = 0; i < nb_numa_nodes; i++) { |
8c85901e | 328 | if (!bitmap_empty(numa_info[i].node_cpu, MAX_CPUMASK_BITS)) { |
96d0e26c WG |
329 | break; |
330 | } | |
331 | } | |
57924bcd IM |
332 | /* Historically VCPUs were assigned in round-robin order to NUMA |
333 | * nodes. However it causes issues with guest not handling it nice | |
334 | * in case where cores/threads from a multicore CPU appear on | |
335 | * different nodes. So allow boards to override default distribution | |
336 | * rule grouping VCPUs by socket so that VCPUs from the same socket | |
337 | * would be on the same node. | |
96d0e26c WG |
338 | */ |
339 | if (i == nb_numa_nodes) { | |
340 | for (i = 0; i < max_cpus; i++) { | |
57924bcd IM |
341 | unsigned node_id = i % nb_numa_nodes; |
342 | if (mc->cpu_index_to_socket_id) { | |
343 | node_id = mc->cpu_index_to_socket_id(i) % nb_numa_nodes; | |
344 | } | |
345 | ||
346 | set_bit(i, numa_info[node_id].node_cpu); | |
96d0e26c WG |
347 | } |
348 | } | |
3ef71975 EH |
349 | |
350 | validate_numa_cpus(); | |
abafabd8 BR |
351 | } else { |
352 | numa_set_mem_node_id(0, ram_size, 0); | |
96d0e26c WG |
353 | } |
354 | } | |
355 | ||
dde11116 | 356 | void numa_post_machine_init(void) |
96d0e26c WG |
357 | { |
358 | CPUState *cpu; | |
359 | int i; | |
360 | ||
361 | CPU_FOREACH(cpu) { | |
362 | for (i = 0; i < nb_numa_nodes; i++) { | |
8c85901e | 363 | if (test_bit(cpu->cpu_index, numa_info[i].node_cpu)) { |
96d0e26c WG |
364 | cpu->numa_node = i; |
365 | } | |
366 | } | |
367 | } | |
368 | } | |
dfabb8b9 | 369 | |
7febe36f PB |
370 | static void allocate_system_memory_nonnuma(MemoryRegion *mr, Object *owner, |
371 | const char *name, | |
372 | uint64_t ram_size) | |
373 | { | |
0b183fc8 PB |
374 | if (mem_path) { |
375 | #ifdef __linux__ | |
7f56e740 | 376 | Error *err = NULL; |
dbcb8981 | 377 | memory_region_init_ram_from_file(mr, owner, name, ram_size, false, |
7f56e740 PB |
378 | mem_path, &err); |
379 | ||
380 | /* Legacy behavior: if allocation failed, fall back to | |
381 | * regular RAM allocation. | |
382 | */ | |
c3ba3095 | 383 | if (err) { |
29b762f5 | 384 | error_report_err(err); |
49946538 | 385 | memory_region_init_ram(mr, owner, name, ram_size, &error_abort); |
7f56e740 | 386 | } |
0b183fc8 PB |
387 | #else |
388 | fprintf(stderr, "-mem-path not supported on this host\n"); | |
389 | exit(1); | |
390 | #endif | |
391 | } else { | |
49946538 | 392 | memory_region_init_ram(mr, owner, name, ram_size, &error_abort); |
0b183fc8 | 393 | } |
7febe36f PB |
394 | vmstate_register_ram_global(mr); |
395 | } | |
396 | ||
dfabb8b9 PB |
397 | void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner, |
398 | const char *name, | |
399 | uint64_t ram_size) | |
400 | { | |
7febe36f PB |
401 | uint64_t addr = 0; |
402 | int i; | |
403 | ||
404 | if (nb_numa_nodes == 0 || !have_memdevs) { | |
405 | allocate_system_memory_nonnuma(mr, owner, name, ram_size); | |
406 | return; | |
407 | } | |
408 | ||
409 | memory_region_init(mr, owner, name, ram_size); | |
410 | for (i = 0; i < MAX_NODES; i++) { | |
411 | Error *local_err = NULL; | |
412 | uint64_t size = numa_info[i].node_mem; | |
413 | HostMemoryBackend *backend = numa_info[i].node_memdev; | |
414 | if (!backend) { | |
415 | continue; | |
416 | } | |
417 | MemoryRegion *seg = host_memory_backend_get_memory(backend, &local_err); | |
418 | if (local_err) { | |
29b762f5 | 419 | error_report_err(local_err); |
7febe36f PB |
420 | exit(1); |
421 | } | |
422 | ||
0462faee HT |
423 | if (memory_region_is_mapped(seg)) { |
424 | char *path = object_get_canonical_path_component(OBJECT(backend)); | |
425 | error_report("memory backend %s is used multiple times. Each " | |
426 | "-numa option must use a different memdev value.", | |
427 | path); | |
428 | exit(1); | |
429 | } | |
430 | ||
7febe36f PB |
431 | memory_region_add_subregion(mr, addr, seg); |
432 | vmstate_register_ram_global(seg); | |
433 | addr += size; | |
434 | } | |
dfabb8b9 | 435 | } |
76b5d850 | 436 | |
5b009e40 HZ |
437 | static void numa_stat_memory_devices(uint64_t node_mem[]) |
438 | { | |
439 | MemoryDeviceInfoList *info_list = NULL; | |
440 | MemoryDeviceInfoList **prev = &info_list; | |
441 | MemoryDeviceInfoList *info; | |
442 | ||
443 | qmp_pc_dimm_device_list(qdev_get_machine(), &prev); | |
444 | for (info = info_list; info; info = info->next) { | |
445 | MemoryDeviceInfo *value = info->value; | |
446 | ||
447 | if (value) { | |
448 | switch (value->kind) { | |
449 | case MEMORY_DEVICE_INFO_KIND_DIMM: | |
450 | node_mem[value->dimm->node] += value->dimm->size; | |
451 | break; | |
452 | default: | |
453 | break; | |
454 | } | |
455 | } | |
456 | } | |
457 | qapi_free_MemoryDeviceInfoList(info_list); | |
458 | } | |
459 | ||
460 | void query_numa_node_mem(uint64_t node_mem[]) | |
461 | { | |
462 | int i; | |
463 | ||
464 | if (nb_numa_nodes <= 0) { | |
465 | return; | |
466 | } | |
467 | ||
468 | numa_stat_memory_devices(node_mem); | |
469 | for (i = 0; i < nb_numa_nodes; i++) { | |
470 | node_mem[i] += numa_info[i].node_mem; | |
471 | } | |
472 | } | |
473 | ||
76b5d850 HT |
474 | static int query_memdev(Object *obj, void *opaque) |
475 | { | |
476 | MemdevList **list = opaque; | |
b0e90181 | 477 | MemdevList *m = NULL; |
76b5d850 HT |
478 | Error *err = NULL; |
479 | ||
480 | if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) { | |
b0e90181 | 481 | m = g_malloc0(sizeof(*m)); |
76b5d850 HT |
482 | |
483 | m->value = g_malloc0(sizeof(*m->value)); | |
484 | ||
485 | m->value->size = object_property_get_int(obj, "size", | |
486 | &err); | |
487 | if (err) { | |
488 | goto error; | |
489 | } | |
490 | ||
491 | m->value->merge = object_property_get_bool(obj, "merge", | |
492 | &err); | |
493 | if (err) { | |
494 | goto error; | |
495 | } | |
496 | ||
497 | m->value->dump = object_property_get_bool(obj, "dump", | |
498 | &err); | |
499 | if (err) { | |
500 | goto error; | |
501 | } | |
502 | ||
503 | m->value->prealloc = object_property_get_bool(obj, | |
504 | "prealloc", &err); | |
505 | if (err) { | |
506 | goto error; | |
507 | } | |
508 | ||
509 | m->value->policy = object_property_get_enum(obj, | |
510 | "policy", | |
a3590dac | 511 | "HostMemPolicy", |
76b5d850 HT |
512 | &err); |
513 | if (err) { | |
514 | goto error; | |
515 | } | |
516 | ||
517 | object_property_get_uint16List(obj, "host-nodes", | |
518 | &m->value->host_nodes, &err); | |
519 | if (err) { | |
520 | goto error; | |
521 | } | |
522 | ||
523 | m->next = *list; | |
524 | *list = m; | |
525 | } | |
526 | ||
527 | return 0; | |
528 | error: | |
b0e90181 CF |
529 | g_free(m->value); |
530 | g_free(m); | |
531 | ||
76b5d850 HT |
532 | return -1; |
533 | } | |
534 | ||
535 | MemdevList *qmp_query_memdev(Error **errp) | |
536 | { | |
537 | Object *obj; | |
ecaf54a0 | 538 | MemdevList *list = NULL; |
76b5d850 | 539 | |
bc2256c4 | 540 | obj = object_get_objects_root(); |
76b5d850 HT |
541 | if (obj == NULL) { |
542 | return NULL; | |
543 | } | |
544 | ||
545 | if (object_child_foreach(obj, query_memdev, &list) != 0) { | |
546 | goto error; | |
547 | } | |
548 | ||
549 | return list; | |
550 | ||
551 | error: | |
ecaf54a0 | 552 | qapi_free_MemdevList(list); |
76b5d850 HT |
553 | return NULL; |
554 | } |