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96d0e26c
WG
1/*
2 * NUMA parameter parsing routines
3 *
4 * Copyright (c) 2014 Fujitsu Ltd.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
d38ea87a 25#include "qemu/osdep.h"
e35704ba 26#include "sysemu/numa.h"
96d0e26c
WG
27#include "exec/cpu-common.h"
28#include "qemu/bitmap.h"
29#include "qom/cpu.h"
2b631ec2
WG
30#include "qemu/error-report.h"
31#include "include/exec/cpu-common.h" /* for RAM_ADDR_FMT */
0042109a
WG
32#include "qapi-visit.h"
33#include "qapi/opts-visitor.h"
dfabb8b9 34#include "hw/boards.h"
7febe36f 35#include "sysemu/hostmem.h"
76b5d850 36#include "qmp-commands.h"
5b009e40 37#include "hw/mem/pc-dimm.h"
7dcd1d70
EH
38#include "qemu/option.h"
39#include "qemu/config-file.h"
0042109a
WG
40
41QemuOptsList qemu_numa_opts = {
42 .name = "numa",
43 .implied_opt_name = "type",
44 .head = QTAILQ_HEAD_INITIALIZER(qemu_numa_opts.head),
45 .desc = { { 0 } } /* validated with OptsVisitor */
46};
47
7febe36f 48static int have_memdevs = -1;
25712ffe
EH
49static int max_numa_nodeid; /* Highest specified NUMA node ID, plus one.
50 * For all nodes, nodeid < max_numa_nodeid
51 */
de1a7c84 52int nb_numa_nodes;
de1a7c84 53NodeInfo numa_info[MAX_NODES];
7febe36f 54
fa9ea81d
BR
55void numa_set_mem_node_id(ram_addr_t addr, uint64_t size, uint32_t node)
56{
672558d2 57 struct numa_addr_range *range;
fa9ea81d 58
abafabd8
BR
59 /*
60 * Memory-less nodes can come here with 0 size in which case,
61 * there is nothing to do.
62 */
63 if (!size) {
64 return;
65 }
66
672558d2 67 range = g_malloc0(sizeof(*range));
fa9ea81d
BR
68 range->mem_start = addr;
69 range->mem_end = addr + size - 1;
70 QLIST_INSERT_HEAD(&numa_info[node].addr, range, entry);
71}
72
73void numa_unset_mem_node_id(ram_addr_t addr, uint64_t size, uint32_t node)
74{
75 struct numa_addr_range *range, *next;
76
77 QLIST_FOREACH_SAFE(range, &numa_info[node].addr, entry, next) {
78 if (addr == range->mem_start && (addr + size - 1) == range->mem_end) {
79 QLIST_REMOVE(range, entry);
80 g_free(range);
81 return;
82 }
83 }
84}
85
abafabd8
BR
86static void numa_set_mem_ranges(void)
87{
88 int i;
89 ram_addr_t mem_start = 0;
90
91 /*
92 * Deduce start address of each node and use it to store
93 * the address range info in numa_info address range list
94 */
95 for (i = 0; i < nb_numa_nodes; i++) {
96 numa_set_mem_node_id(mem_start, numa_info[i].node_mem, i);
97 mem_start += numa_info[i].node_mem;
98 }
99}
100
e75e2a14
BR
101/*
102 * Check if @addr falls under NUMA @node.
103 */
104static bool numa_addr_belongs_to_node(ram_addr_t addr, uint32_t node)
105{
106 struct numa_addr_range *range;
107
108 QLIST_FOREACH(range, &numa_info[node].addr, entry) {
109 if (addr >= range->mem_start && addr <= range->mem_end) {
110 return true;
111 }
112 }
113 return false;
114}
115
116/*
117 * Given an address, return the index of the NUMA node to which the
118 * address belongs to.
119 */
120uint32_t numa_get_node(ram_addr_t addr, Error **errp)
121{
122 uint32_t i;
123
124 /* For non NUMA configurations, check if the addr falls under node 0 */
125 if (!nb_numa_nodes) {
126 if (numa_addr_belongs_to_node(addr, 0)) {
127 return 0;
128 }
129 }
130
131 for (i = 0; i < nb_numa_nodes; i++) {
132 if (numa_addr_belongs_to_node(addr, i)) {
133 return i;
134 }
135 }
136
137 error_setg(errp, "Address 0x" RAM_ADDR_FMT " doesn't belong to any "
138 "NUMA node", addr);
139 return -1;
140}
141
0042109a 142static void numa_node_parse(NumaNodeOptions *node, QemuOpts *opts, Error **errp)
96d0e26c 143{
0042109a
WG
144 uint16_t nodenr;
145 uint16List *cpus = NULL;
96d0e26c 146
0042109a
WG
147 if (node->has_nodeid) {
148 nodenr = node->nodeid;
96d0e26c 149 } else {
0042109a 150 nodenr = nb_numa_nodes;
96d0e26c
WG
151 }
152
0042109a
WG
153 if (nodenr >= MAX_NODES) {
154 error_setg(errp, "Max number of NUMA nodes reached: %"
01bbbcf4 155 PRIu16 "", nodenr);
0042109a 156 return;
96d0e26c
WG
157 }
158
1945b9d8
EH
159 if (numa_info[nodenr].present) {
160 error_setg(errp, "Duplicate NUMA nodeid: %" PRIu16, nodenr);
161 return;
162 }
163
0042109a 164 for (cpus = node->cpus; cpus; cpus = cpus->next) {
8979c945
EH
165 if (cpus->value >= max_cpus) {
166 error_setg(errp,
167 "CPU index (%" PRIu16 ")"
168 " should be smaller than maxcpus (%d)",
169 cpus->value, max_cpus);
0042109a
WG
170 return;
171 }
172 bitmap_set(numa_info[nodenr].node_cpu, cpus->value, 1);
96d0e26c
WG
173 }
174
7febe36f 175 if (node->has_mem && node->has_memdev) {
01bbbcf4 176 error_setg(errp, "qemu: cannot specify both mem= and memdev=");
7febe36f
PB
177 return;
178 }
179
180 if (have_memdevs == -1) {
181 have_memdevs = node->has_memdev;
182 }
183 if (node->has_memdev != have_memdevs) {
184 error_setg(errp, "qemu: memdev option must be specified for either "
01bbbcf4 185 "all or no nodes");
7febe36f
PB
186 return;
187 }
188
0042109a
WG
189 if (node->has_mem) {
190 uint64_t mem_size = node->mem;
191 const char *mem_str = qemu_opt_get(opts, "mem");
192 /* Fix up legacy suffix-less format */
193 if (g_ascii_isdigit(mem_str[strlen(mem_str) - 1])) {
194 mem_size <<= 20;
195 }
196 numa_info[nodenr].node_mem = mem_size;
197 }
7febe36f
PB
198 if (node->has_memdev) {
199 Object *o;
200 o = object_resolve_path_type(node->memdev, TYPE_MEMORY_BACKEND, NULL);
201 if (!o) {
202 error_setg(errp, "memdev=%s is ambiguous", node->memdev);
203 return;
204 }
205
206 object_ref(o);
207 numa_info[nodenr].node_mem = object_property_get_int(o, "size", NULL);
208 numa_info[nodenr].node_memdev = MEMORY_BACKEND(o);
209 }
1af878e0
EH
210 numa_info[nodenr].present = true;
211 max_numa_nodeid = MAX(max_numa_nodeid, nodenr + 1);
96d0e26c
WG
212}
213
28d0de7a 214static int parse_numa(void *opaque, QemuOpts *opts, Error **errp)
96d0e26c 215{
0042109a
WG
216 NumaOptions *object = NULL;
217 Error *err = NULL;
96d0e26c 218
0042109a 219 {
09204eac
EB
220 Visitor *v = opts_visitor_new(opts);
221 visit_type_NumaOptions(v, NULL, &object, &err);
222 visit_free(v);
96d0e26c 223 }
96d0e26c 224
0042109a 225 if (err) {
157e94e8 226 goto end;
0042109a 227 }
96d0e26c 228
1fd5d4fe 229 switch (object->type) {
0042109a 230 case NUMA_OPTIONS_KIND_NODE:
32bafa8f 231 numa_node_parse(object->u.node.data, opts, &err);
0042109a 232 if (err) {
157e94e8 233 goto end;
96d0e26c 234 }
0042109a
WG
235 nb_numa_nodes++;
236 break;
237 default:
238 abort();
239 }
96d0e26c 240
157e94e8 241end:
96a1616c 242 qapi_free_NumaOptions(object);
157e94e8
MAL
243 if (err) {
244 error_report_err(err);
245 return -1;
246 }
0042109a 247
157e94e8 248 return 0;
96d0e26c
WG
249}
250
3ef71975
EH
251static char *enumerate_cpus(unsigned long *cpus, int max_cpus)
252{
253 int cpu;
254 bool first = true;
255 GString *s = g_string_new(NULL);
256
257 for (cpu = find_first_bit(cpus, max_cpus);
258 cpu < max_cpus;
259 cpu = find_next_bit(cpus, max_cpus, cpu + 1)) {
260 g_string_append_printf(s, "%s%d", first ? "" : " ", cpu);
261 first = false;
262 }
263 return g_string_free(s, FALSE);
264}
265
266static void validate_numa_cpus(void)
267{
268 int i;
cdda2018 269 unsigned long *seen_cpus = bitmap_new(max_cpus);
3ef71975 270
3ef71975 271 for (i = 0; i < nb_numa_nodes; i++) {
cdda2018 272 if (bitmap_intersects(seen_cpus, numa_info[i].node_cpu, max_cpus)) {
3ef71975 273 bitmap_and(seen_cpus, seen_cpus,
cdda2018 274 numa_info[i].node_cpu, max_cpus);
3ef71975 275 error_report("CPU(s) present in multiple NUMA nodes: %s",
a8f15a27 276 enumerate_cpus(seen_cpus, max_cpus));
cdda2018 277 g_free(seen_cpus);
3ef71975
EH
278 exit(EXIT_FAILURE);
279 }
280 bitmap_or(seen_cpus, seen_cpus,
cdda2018 281 numa_info[i].node_cpu, max_cpus);
3ef71975 282 }
549fc54b
EH
283
284 if (!bitmap_full(seen_cpus, max_cpus)) {
285 char *msg;
286 bitmap_complement(seen_cpus, seen_cpus, max_cpus);
287 msg = enumerate_cpus(seen_cpus, max_cpus);
288 error_report("warning: CPU(s) not present in any NUMA nodes: %s", msg);
289 error_report("warning: All CPU(s) up to maxcpus should be described "
290 "in NUMA config");
291 g_free(msg);
292 }
cdda2018 293 g_free(seen_cpus);
3ef71975
EH
294}
295
57924bcd 296void parse_numa_opts(MachineClass *mc)
96d0e26c 297{
12d6e464
EH
298 int i;
299
cdda2018
IM
300 for (i = 0; i < MAX_NODES; i++) {
301 numa_info[i].node_cpu = bitmap_new(max_cpus);
302 }
303
28d0de7a 304 if (qemu_opts_foreach(qemu_find_opts("numa"), parse_numa, NULL, NULL)) {
7dcd1d70
EH
305 exit(1);
306 }
307
12d6e464
EH
308 assert(max_numa_nodeid <= MAX_NODES);
309
310 /* No support for sparse NUMA node IDs yet: */
311 for (i = max_numa_nodeid - 1; i >= 0; i--) {
312 /* Report large node IDs first, to make mistakes easier to spot */
313 if (!numa_info[i].present) {
314 error_report("numa: Node ID missing: %d", i);
315 exit(1);
316 }
317 }
318
319 /* This must be always true if all nodes are present: */
320 assert(nb_numa_nodes == max_numa_nodeid);
321
96d0e26c 322 if (nb_numa_nodes > 0) {
2b631ec2 323 uint64_t numa_total;
96d0e26c
WG
324
325 if (nb_numa_nodes > MAX_NODES) {
326 nb_numa_nodes = MAX_NODES;
327 }
328
9851d0fe 329 /* If no memory size is given for any node, assume the default case
96d0e26c
WG
330 * and distribute the available memory equally across all nodes
331 */
332 for (i = 0; i < nb_numa_nodes; i++) {
8c85901e 333 if (numa_info[i].node_mem != 0) {
96d0e26c
WG
334 break;
335 }
336 }
337 if (i == nb_numa_nodes) {
338 uint64_t usedmem = 0;
339
d75e2f68 340 /* On Linux, each node's border has to be 8MB aligned,
96d0e26c
WG
341 * the final node gets the rest.
342 */
343 for (i = 0; i < nb_numa_nodes - 1; i++) {
8c85901e
WG
344 numa_info[i].node_mem = (ram_size / nb_numa_nodes) &
345 ~((1 << 23UL) - 1);
346 usedmem += numa_info[i].node_mem;
96d0e26c 347 }
8c85901e 348 numa_info[i].node_mem = ram_size - usedmem;
96d0e26c
WG
349 }
350
2b631ec2
WG
351 numa_total = 0;
352 for (i = 0; i < nb_numa_nodes; i++) {
8c85901e 353 numa_total += numa_info[i].node_mem;
2b631ec2
WG
354 }
355 if (numa_total != ram_size) {
c68233ae
HT
356 error_report("total memory for NUMA nodes (0x%" PRIx64 ")"
357 " should equal RAM size (0x" RAM_ADDR_FMT ")",
2b631ec2
WG
358 numa_total, ram_size);
359 exit(1);
360 }
361
fa9ea81d
BR
362 for (i = 0; i < nb_numa_nodes; i++) {
363 QLIST_INIT(&numa_info[i].addr);
364 }
365
abafabd8
BR
366 numa_set_mem_ranges();
367
96d0e26c 368 for (i = 0; i < nb_numa_nodes; i++) {
cdda2018 369 if (!bitmap_empty(numa_info[i].node_cpu, max_cpus)) {
96d0e26c
WG
370 break;
371 }
372 }
57924bcd
IM
373 /* Historically VCPUs were assigned in round-robin order to NUMA
374 * nodes. However it causes issues with guest not handling it nice
375 * in case where cores/threads from a multicore CPU appear on
376 * different nodes. So allow boards to override default distribution
377 * rule grouping VCPUs by socket so that VCPUs from the same socket
378 * would be on the same node.
96d0e26c
WG
379 */
380 if (i == nb_numa_nodes) {
381 for (i = 0; i < max_cpus; i++) {
57924bcd
IM
382 unsigned node_id = i % nb_numa_nodes;
383 if (mc->cpu_index_to_socket_id) {
384 node_id = mc->cpu_index_to_socket_id(i) % nb_numa_nodes;
385 }
386
387 set_bit(i, numa_info[node_id].node_cpu);
96d0e26c
WG
388 }
389 }
3ef71975
EH
390
391 validate_numa_cpus();
abafabd8
BR
392 } else {
393 numa_set_mem_node_id(0, ram_size, 0);
96d0e26c
WG
394 }
395}
396
dde11116 397void numa_post_machine_init(void)
96d0e26c
WG
398{
399 CPUState *cpu;
400 int i;
401
402 CPU_FOREACH(cpu) {
403 for (i = 0; i < nb_numa_nodes; i++) {
cdda2018 404 assert(cpu->cpu_index < max_cpus);
8c85901e 405 if (test_bit(cpu->cpu_index, numa_info[i].node_cpu)) {
96d0e26c
WG
406 cpu->numa_node = i;
407 }
408 }
409 }
410}
dfabb8b9 411
7febe36f
PB
412static void allocate_system_memory_nonnuma(MemoryRegion *mr, Object *owner,
413 const char *name,
414 uint64_t ram_size)
415{
0b183fc8
PB
416 if (mem_path) {
417#ifdef __linux__
7f56e740 418 Error *err = NULL;
dbcb8981 419 memory_region_init_ram_from_file(mr, owner, name, ram_size, false,
7f56e740 420 mem_path, &err);
c3ba3095 421 if (err) {
29b762f5 422 error_report_err(err);
fae947b0
LC
423 if (mem_prealloc) {
424 exit(1);
425 }
426
427 /* Legacy behavior: if allocation failed, fall back to
428 * regular RAM allocation.
429 */
f8ed85ac 430 memory_region_init_ram(mr, owner, name, ram_size, &error_fatal);
7f56e740 431 }
0b183fc8
PB
432#else
433 fprintf(stderr, "-mem-path not supported on this host\n");
434 exit(1);
435#endif
436 } else {
f8ed85ac 437 memory_region_init_ram(mr, owner, name, ram_size, &error_fatal);
0b183fc8 438 }
7febe36f
PB
439 vmstate_register_ram_global(mr);
440}
441
dfabb8b9
PB
442void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner,
443 const char *name,
444 uint64_t ram_size)
445{
7febe36f
PB
446 uint64_t addr = 0;
447 int i;
448
449 if (nb_numa_nodes == 0 || !have_memdevs) {
450 allocate_system_memory_nonnuma(mr, owner, name, ram_size);
451 return;
452 }
453
454 memory_region_init(mr, owner, name, ram_size);
455 for (i = 0; i < MAX_NODES; i++) {
7febe36f
PB
456 uint64_t size = numa_info[i].node_mem;
457 HostMemoryBackend *backend = numa_info[i].node_memdev;
458 if (!backend) {
459 continue;
460 }
007b0657
MA
461 MemoryRegion *seg = host_memory_backend_get_memory(backend,
462 &error_fatal);
7febe36f 463
0462faee
HT
464 if (memory_region_is_mapped(seg)) {
465 char *path = object_get_canonical_path_component(OBJECT(backend));
466 error_report("memory backend %s is used multiple times. Each "
467 "-numa option must use a different memdev value.",
468 path);
469 exit(1);
470 }
471
0b217571 472 host_memory_backend_set_mapped(backend, true);
7febe36f
PB
473 memory_region_add_subregion(mr, addr, seg);
474 vmstate_register_ram_global(seg);
475 addr += size;
476 }
dfabb8b9 477}
76b5d850 478
5b009e40
HZ
479static void numa_stat_memory_devices(uint64_t node_mem[])
480{
481 MemoryDeviceInfoList *info_list = NULL;
482 MemoryDeviceInfoList **prev = &info_list;
483 MemoryDeviceInfoList *info;
484
485 qmp_pc_dimm_device_list(qdev_get_machine(), &prev);
486 for (info = info_list; info; info = info->next) {
487 MemoryDeviceInfo *value = info->value;
488
489 if (value) {
1fd5d4fe 490 switch (value->type) {
5b009e40 491 case MEMORY_DEVICE_INFO_KIND_DIMM:
32bafa8f 492 node_mem[value->u.dimm.data->node] += value->u.dimm.data->size;
5b009e40
HZ
493 break;
494 default:
495 break;
496 }
497 }
498 }
499 qapi_free_MemoryDeviceInfoList(info_list);
500}
501
502void query_numa_node_mem(uint64_t node_mem[])
503{
504 int i;
505
506 if (nb_numa_nodes <= 0) {
507 return;
508 }
509
510 numa_stat_memory_devices(node_mem);
511 for (i = 0; i < nb_numa_nodes; i++) {
512 node_mem[i] += numa_info[i].node_mem;
513 }
514}
515
76b5d850
HT
516static int query_memdev(Object *obj, void *opaque)
517{
518 MemdevList **list = opaque;
b0e90181 519 MemdevList *m = NULL;
76b5d850
HT
520
521 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
b0e90181 522 m = g_malloc0(sizeof(*m));
76b5d850
HT
523
524 m->value = g_malloc0(sizeof(*m->value));
525
e1ff3c67
IM
526 m->value->id = object_property_get_str(obj, "id", NULL);
527 m->value->has_id = !!m->value->id;
528
76b5d850 529 m->value->size = object_property_get_int(obj, "size",
2f6f826e 530 &error_abort);
76b5d850 531 m->value->merge = object_property_get_bool(obj, "merge",
2f6f826e 532 &error_abort);
76b5d850 533 m->value->dump = object_property_get_bool(obj, "dump",
2f6f826e 534 &error_abort);
76b5d850 535 m->value->prealloc = object_property_get_bool(obj,
2f6f826e
MA
536 "prealloc",
537 &error_abort);
76b5d850
HT
538 m->value->policy = object_property_get_enum(obj,
539 "policy",
a3590dac 540 "HostMemPolicy",
2f6f826e 541 &error_abort);
76b5d850 542 object_property_get_uint16List(obj, "host-nodes",
2f6f826e
MA
543 &m->value->host_nodes,
544 &error_abort);
76b5d850
HT
545
546 m->next = *list;
547 *list = m;
548 }
549
550 return 0;
76b5d850
HT
551}
552
553MemdevList *qmp_query_memdev(Error **errp)
554{
2f6f826e 555 Object *obj = object_get_objects_root();
ecaf54a0 556 MemdevList *list = NULL;
76b5d850 557
2f6f826e 558 object_child_foreach(obj, query_memdev, &list);
76b5d850 559 return list;
76b5d850 560}
6bea1ddf
IM
561
562int numa_get_node_for_cpu(int idx)
563{
564 int i;
565
cdda2018
IM
566 assert(idx < max_cpus);
567
6bea1ddf
IM
568 for (i = 0; i < nb_numa_nodes; i++) {
569 if (test_bit(idx, numa_info[i].node_cpu)) {
570 break;
571 }
572 }
573 return i;
574}