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1 | From 866f4c5de45ae13aa590de0d40819a0c38f3f682 Mon Sep 17 00:00:00 2001 |
2 | From: Mark Weiman <mark.weiman@markzz.com> | |
3 | Date: Sun, 23 Oct 2016 12:57:37 -0400 | |
4 | Subject: [PATCH] pci: Enable overrides for missing ACS capabilities (4.8+) | |
5 | ||
6 | This an updated version of Alex Williamson's patch from: | |
7 | https://lkml.org/lkml/2013/5/30/513 | |
8 | ||
9 | Original commit message follows: | |
10 | --- | |
11 | PCIe ACS (Access Control Services) is the PCIe 2.0+ feature that | |
12 | allows us to control whether transactions are allowed to be redirected | |
13 | in various subnodes of a PCIe topology. For instance, if two | |
14 | endpoints are below a root port or downsteam switch port, the | |
15 | downstream port may optionally redirect transactions between the | |
16 | devices, bypassing upstream devices. The same can happen internally | |
17 | on multifunction devices. The transaction may never be visible to the | |
18 | upstream devices. | |
19 | ||
20 | One upstream device that we particularly care about is the IOMMU. If | |
21 | a redirection occurs in the topology below the IOMMU, then the IOMMU | |
22 | cannot provide isolation between devices. This is why the PCIe spec | |
23 | encourages topologies to include ACS support. Without it, we have to | |
24 | assume peer-to-peer DMA within a hierarchy can bypass IOMMU isolation. | |
25 | ||
26 | Unfortunately, far too many topologies do not support ACS to make this | |
27 | a steadfast requirement. Even the latest chipsets from Intel are only | |
28 | sporadically supporting ACS. We have trouble getting interconnect | |
29 | vendors to include the PCIe spec required PCIe capability, let alone | |
30 | suggested features. | |
31 | ||
32 | Therefore, we need to add some flexibility. The pcie_acs_override= | |
33 | boot option lets users opt-in specific devices or sets of devices to | |
34 | assume ACS support. The "downstream" option assumes full ACS support | |
35 | on root ports and downstream switch ports. The "multifunction" | |
36 | option assumes the subset of ACS features available on multifunction | |
37 | endpoints and upstream switch ports are supported. The "id:nnnn:nnnn" | |
38 | option enables ACS support on devices matching the provided vendor | |
39 | and device IDs, allowing more strategic ACS overrides. These options | |
40 | may be combined in any order. A maximum of 16 id specific overrides | |
41 | are available. It's suggested to use the most limited set of options | |
42 | necessary to avoid completely disabling ACS across the topology. | |
43 | Note to hardware vendors, we have facilities to permanently quirk | |
44 | specific devices which enforce isolation but not provide an ACS | |
45 | capability. Please contact me to have your devices added and save | |
46 | your customers the hassle of this boot option. | |
47 | ||
48 | Signed-off-by: Mark Weiman <mark.weiman@markzz.com> | |
49 | --- | |
50 | Documentation/admin-guide/kernel-parameters.txt | 9 ++++ | |
51 | drivers/pci/quirks.c | 101 ++++++++++++++++++++++++++++++++++++ | |
52 | 2 files changed, 110 insertions(+) | |
53 | ||
54 | diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt | |
55 | index a4f4d69..d68cfab 100644 | |
56 | --- a/Documentation/admin-guide/kernel-parameters.txt | |
57 | +++ b/Documentation/admin-guide/kernel-parameters.txt | |
58 | @@ -2928,6 +2928,15 @@ bytes respectively. Such letter suffixes can also be entirely omitted. | |
59 | nomsi [MSI] If the PCI_MSI kernel config parameter is | |
60 | enabled, this kernel boot option can be used to | |
61 | disable the use of MSI interrupts system-wide. | |
62 | + pci_acs_override = | |
63 | + [PCIE] Override missing PCIe ACS support for: | |
64 | + downstream | |
65 | + All downstream ports - full ACS capabilities | |
66 | + multfunction | |
67 | + All multifunction devices - multifunction ACS subset | |
68 | + id:nnnn:nnnn | |
69 | + Specfic device - full ACS capabilities | |
70 | + Specified as vid:did (vendor/device ID) in hex | |
71 | noioapicquirk [APIC] Disable all boot interrupt quirks. | |
72 | Safety option to keep boot IRQs enabled. This | |
73 | should never be necessary. | |
74 | diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c | |
75 | index 44e0ff3..32016cb 100644 | |
76 | --- a/drivers/pci/quirks.c | |
77 | +++ b/drivers/pci/quirks.c | |
78 | @@ -3487,6 +3487,106 @@ static int __init pci_apply_final_quirks(void) | |
79 | ||
80 | fs_initcall_sync(pci_apply_final_quirks); | |
81 | ||
82 | +static bool acs_on_downstream; | |
83 | +static bool acs_on_multifunction; | |
84 | + | |
85 | +#define NUM_ACS_IDS 16 | |
86 | +struct acs_on_id { | |
87 | + unsigned short vendor; | |
88 | + unsigned short device; | |
89 | +}; | |
90 | +static struct acs_on_id acs_on_ids[NUM_ACS_IDS]; | |
91 | +static u8 max_acs_id; | |
92 | + | |
93 | +static __init int pcie_acs_override_setup(char *p) | |
94 | +{ | |
95 | + if (!p) | |
96 | + return -EINVAL; | |
97 | + | |
98 | + while (*p) { | |
99 | + if (!strncmp(p, "downstream", 10)) | |
100 | + acs_on_downstream = true; | |
101 | + if (!strncmp(p, "multifunction", 13)) | |
102 | + acs_on_multifunction = true; | |
103 | + if (!strncmp(p, "id:", 3)) { | |
104 | + char opt[5]; | |
105 | + int ret; | |
106 | + long val; | |
107 | + | |
108 | + if (max_acs_id >= NUM_ACS_IDS - 1) { | |
109 | + pr_warn("Out of PCIe ACS override slots (%d)\n", | |
110 | + NUM_ACS_IDS); | |
111 | + goto next; | |
112 | + } | |
113 | + | |
114 | + p += 3; | |
115 | + snprintf(opt, 5, "%s", p); | |
116 | + ret = kstrtol(opt, 16, &val); | |
117 | + if (ret) { | |
118 | + pr_warn("PCIe ACS ID parse error %d\n", ret); | |
119 | + goto next; | |
120 | + } | |
121 | + acs_on_ids[max_acs_id].vendor = val; | |
122 | + | |
123 | + p += strcspn(p, ":"); | |
124 | + if (*p != ';') { | |
125 | + pr_warn("PCIe ACS invalid ID\n"); | |
126 | + goto next; | |
127 | + } | |
128 | + | |
129 | + p++; | |
130 | + snprintf(opt, 5, "%s", p); | |
131 | + ret = kstrtol(opt, 16, &val); | |
132 | + if (ret) { | |
133 | + pr_warn("PCIe ACS ID parse error %d\n", ret); | |
134 | + goto next; | |
135 | + } | |
136 | + acs_on_ids[max_acs_id].device = val; | |
137 | + max_acs_id++; | |
138 | + } | |
139 | +next: | |
140 | + p += strcspn(p, ","); | |
141 | + if (*p == ',') | |
142 | + p++; | |
143 | + } | |
144 | + | |
145 | + if (acs_on_downstream || acs_on_multifunction || max_acs_id) | |
146 | + pr_warn("Warning: PCIe ACS overrides enabled; This may allow non-IOMMU protected peer-to-peer DMA\n"); | |
147 | + | |
148 | + return 0; | |
149 | +} | |
150 | +early_param("pcie_acs_override", pcie_acs_override_setup); | |
151 | + | |
152 | +static int pcie_acs_overrides(struct pci_dev *dev, u16 acs_flags) | |
153 | +{ | |
154 | + int i; | |
155 | + | |
156 | + /* Never override ACS for legacy devices or devices with ACS caps */ | |
157 | + if (!pci_is_pcie(dev) || | |
158 | + pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS)) | |
159 | + return -ENOTTY; | |
160 | + | |
161 | + for (i = 0; i < max_acs_id; i++) | |
162 | + if (acs_on_ids[i].vendor == dev->vendor && | |
163 | + acs_on_ids[i].device == dev->device) | |
164 | + return 1; | |
165 | + | |
166 | + switch (pci_pcie_type(dev)) { | |
167 | + case PCI_EXP_TYPE_DOWNSTREAM: | |
168 | + case PCI_EXP_TYPE_ROOT_PORT: | |
169 | + if (acs_on_downstream) | |
170 | + return 1; | |
171 | + break; | |
172 | + case PCI_EXP_TYPE_ENDPOINT: | |
173 | + case PCI_EXP_TYPE_UPSTREAM: | |
174 | + case PCI_EXP_TYPE_LEG_END: | |
175 | + case PCI_EXP_TYPE_RC_END: | |
176 | + if (acs_on_multifunction && dev->multifunction) | |
177 | + return 1; | |
178 | + } | |
179 | + | |
180 | + return -ENOTTY; | |
181 | +} | |
182 | /* | |
183 | * Followings are device-specific reset methods which can be used to | |
184 | * reset a single function if other methods (e.g. FLR, PM D0->D3) are | |
185 | @@ -4160,6 +4260,7 @@ static const struct pci_dev_acs_enabled { | |
186 | { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ | |
187 | /* Cavium ThunderX */ | |
188 | { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, | |
189 | + { PCI_ANY_ID, PCI_ANY_ID, pcie_acs_overrides }, | |
190 | { 0 } | |
191 | }; | |
192 | ||
193 | -- | |
194 | 2.10.1 | |
195 |