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59d5af67 | 1 | From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 |
321d628a FG |
2 | From: Ingo Molnar <mingo@kernel.org> |
3 | Date: Tue, 31 Oct 2017 13:17:22 +0100 | |
59d5af67 | 4 | Subject: [PATCH] x86/cpufeatures: Re-tabulate the X86_FEATURE definitions |
321d628a FG |
5 | MIME-Version: 1.0 |
6 | Content-Type: text/plain; charset=UTF-8 | |
7 | Content-Transfer-Encoding: 8bit | |
8 | ||
9 | CVE-2017-5754 | |
10 | ||
11 | Over the years asm/cpufeatures.h has become somewhat of a mess: the original | |
12 | tabulation style was too narrow, while x86 feature names also kept growing | |
13 | in length, creating frequent field width overflows. | |
14 | ||
15 | Re-tabulate it to make it wider and easier to read/modify. Also harmonize | |
16 | the tabulation of the other defines in this file to match it. | |
17 | ||
18 | Cc: Andrew Morton <akpm@linux-foundation.org> | |
19 | Cc: Andy Lutomirski <luto@amacapital.net> | |
20 | Cc: Andy Lutomirski <luto@kernel.org> | |
21 | Cc: Borislav Petkov <bp@alien8.de> | |
22 | Cc: Brian Gerst <brgerst@gmail.com> | |
23 | Cc: Denys Vlasenko <dvlasenk@redhat.com> | |
24 | Cc: Josh Poimboeuf <jpoimboe@redhat.com> | |
25 | Cc: Linus Torvalds <torvalds@linux-foundation.org> | |
26 | Cc: Peter Zijlstra <peterz@infradead.org> | |
27 | Cc: Thomas Gleixner <tglx@linutronix.de> | |
28 | Link: http://lkml.kernel.org/r/20171031121723.28524-3-mingo@kernel.org | |
29 | Signed-off-by: Ingo Molnar <mingo@kernel.org> | |
30 | (backported from commit acbc845ffefd9fb70466182cd8555a26189462b2) | |
31 | Signed-off-by: Andy Whitcroft <apw@canonical.com> | |
32 | Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com> | |
33 | (cherry picked from commit df7c6e7b62274889a028357a579acfb2215c3f98) | |
34 | Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com> | |
35 | --- | |
36 | arch/x86/include/asm/cpufeatures.h | 506 +++++++++++++++++++------------------ | |
37 | 1 file changed, 254 insertions(+), 252 deletions(-) | |
38 | ||
39 | diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h | |
40 | index c465bd6613ed..a021b0756af6 100644 | |
41 | --- a/arch/x86/include/asm/cpufeatures.h | |
42 | +++ b/arch/x86/include/asm/cpufeatures.h | |
43 | @@ -12,8 +12,8 @@ | |
44 | /* | |
45 | * Defines x86 CPU feature bits | |
46 | */ | |
47 | -#define NCAPINTS 18 /* N 32-bit words worth of info */ | |
48 | -#define NBUGINTS 1 /* N 32-bit bug flags */ | |
49 | +#define NCAPINTS 18 /* N 32-bit words worth of info */ | |
50 | +#define NBUGINTS 1 /* N 32-bit bug flags */ | |
51 | ||
52 | /* | |
53 | * Note: If the comment begins with a quoted string, that string is used | |
54 | @@ -27,163 +27,163 @@ | |
55 | */ | |
56 | ||
57 | /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ | |
58 | -#define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ | |
59 | -#define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ | |
60 | -#define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ | |
61 | -#define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */ | |
62 | -#define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */ | |
63 | -#define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */ | |
64 | -#define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */ | |
65 | -#define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */ | |
66 | -#define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */ | |
67 | -#define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */ | |
68 | -#define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */ | |
69 | -#define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ | |
70 | -#define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ | |
71 | -#define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ | |
72 | -#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */ | |
73 | +#define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ | |
74 | +#define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ | |
75 | +#define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ | |
76 | +#define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */ | |
77 | +#define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */ | |
78 | +#define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */ | |
79 | +#define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */ | |
80 | +#define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */ | |
81 | +#define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */ | |
82 | +#define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */ | |
83 | +#define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */ | |
84 | +#define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ | |
85 | +#define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ | |
86 | +#define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ | |
87 | +#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */ | |
88 | /* (plus FCMOVcc, FCOMI with FPU) */ | |
89 | -#define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ | |
90 | -#define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ | |
91 | -#define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ | |
92 | -#define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */ | |
93 | -#define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ | |
94 | -#define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */ | |
95 | -#define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */ | |
96 | -#define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ | |
97 | -#define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ | |
98 | -#define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ | |
99 | -#define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ | |
100 | -#define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */ | |
101 | -#define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ | |
102 | -#define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */ | |
103 | -#define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */ | |
104 | +#define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ | |
105 | +#define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ | |
106 | +#define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ | |
107 | +#define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */ | |
108 | +#define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ | |
109 | +#define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */ | |
110 | +#define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */ | |
111 | +#define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ | |
112 | +#define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ | |
113 | +#define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ | |
114 | +#define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ | |
115 | +#define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */ | |
116 | +#define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ | |
117 | +#define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */ | |
118 | +#define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */ | |
119 | ||
120 | /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ | |
121 | /* Don't duplicate feature flags which are redundant with Intel! */ | |
122 | -#define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ | |
123 | -#define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */ | |
124 | -#define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ | |
125 | -#define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ | |
126 | -#define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ | |
127 | -#define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ | |
128 | -#define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ | |
129 | -#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */ | |
130 | -#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */ | |
131 | -#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */ | |
132 | +#define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ | |
133 | +#define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */ | |
134 | +#define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ | |
135 | +#define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ | |
136 | +#define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ | |
137 | +#define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ | |
138 | +#define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ | |
139 | +#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */ | |
140 | +#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */ | |
141 | +#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */ | |
142 | ||
143 | /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ | |
144 | -#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ | |
145 | -#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ | |
146 | -#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ | |
147 | +#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ | |
148 | +#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ | |
149 | +#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ | |
150 | ||
151 | /* Other features, Linux-defined mapping, word 3 */ | |
152 | /* This range is used for feature bits which conflict or are synthesized */ | |
153 | -#define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */ | |
154 | -#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ | |
155 | -#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ | |
156 | -#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ | |
157 | +#define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */ | |
158 | +#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ | |
159 | +#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ | |
160 | +#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ | |
161 | /* cpu types for specific tunings: */ | |
162 | -#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ | |
163 | -#define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ | |
164 | -#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ | |
165 | -#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ | |
166 | -#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ | |
167 | -#define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */ | |
168 | -#define X86_FEATURE_ART ( 3*32+10) /* Platform has always running timer (ART) */ | |
169 | -#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ | |
170 | -#define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ | |
171 | -#define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ | |
172 | -#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */ | |
173 | -#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */ | |
174 | -#define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */ | |
175 | -#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */ | |
176 | -#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */ | |
177 | -#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ | |
178 | -#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ | |
179 | -#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ | |
180 | -#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */ | |
181 | -#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ | |
182 | -#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ | |
183 | -#define X86_FEATURE_CPUID ( 3*32+25) /* CPU has CPUID instruction itself */ | |
184 | -#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */ | |
185 | -#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */ | |
186 | -#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ | |
187 | -#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ | |
188 | -#define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */ | |
189 | +#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ | |
190 | +#define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ | |
191 | +#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ | |
192 | +#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ | |
193 | +#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ | |
194 | +#define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */ | |
195 | +#define X86_FEATURE_ART ( 3*32+10) /* Platform has always running timer (ART) */ | |
196 | +#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ | |
197 | +#define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ | |
198 | +#define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ | |
199 | +#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */ | |
200 | +#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */ | |
201 | +#define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */ | |
202 | +#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */ | |
203 | +#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */ | |
204 | +#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ | |
205 | +#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ | |
206 | +#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ | |
207 | +#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */ | |
208 | +#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ | |
209 | +#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ | |
210 | +#define X86_FEATURE_CPUID ( 3*32+25) /* CPU has CPUID instruction itself */ | |
211 | +#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */ | |
212 | +#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */ | |
213 | +#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ | |
214 | +#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ | |
215 | +#define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */ | |
216 | ||
217 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ | |
218 | -#define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ | |
219 | -#define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ | |
220 | -#define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ | |
221 | -#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */ | |
222 | -#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ | |
223 | -#define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ | |
224 | -#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */ | |
225 | -#define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ | |
226 | -#define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ | |
227 | -#define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ | |
228 | -#define X86_FEATURE_CID ( 4*32+10) /* Context ID */ | |
229 | -#define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */ | |
230 | -#define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ | |
231 | -#define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */ | |
232 | -#define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ | |
233 | -#define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */ | |
234 | -#define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ | |
235 | -#define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ | |
236 | -#define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ | |
237 | -#define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ | |
238 | -#define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */ | |
239 | -#define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ | |
240 | -#define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ | |
241 | +#define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ | |
242 | +#define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ | |
243 | +#define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ | |
244 | +#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */ | |
245 | +#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ | |
246 | +#define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ | |
247 | +#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */ | |
248 | +#define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ | |
249 | +#define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ | |
250 | +#define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ | |
251 | +#define X86_FEATURE_CID ( 4*32+10) /* Context ID */ | |
252 | +#define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */ | |
253 | +#define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ | |
254 | +#define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */ | |
255 | +#define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ | |
256 | +#define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */ | |
257 | +#define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ | |
258 | +#define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ | |
259 | +#define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ | |
260 | +#define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ | |
261 | +#define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */ | |
262 | +#define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ | |
263 | +#define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ | |
264 | #define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */ | |
265 | -#define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ | |
266 | -#define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ | |
267 | -#define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */ | |
268 | -#define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ | |
269 | -#define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */ | |
270 | -#define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */ | |
271 | -#define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ | |
272 | +#define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ | |
273 | +#define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ | |
274 | +#define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */ | |
275 | +#define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ | |
276 | +#define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */ | |
277 | +#define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */ | |
278 | +#define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ | |
279 | ||
280 | /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ | |
281 | -#define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */ | |
282 | -#define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */ | |
283 | -#define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ | |
284 | -#define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */ | |
285 | -#define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */ | |
286 | -#define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */ | |
287 | -#define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */ | |
288 | -#define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */ | |
289 | -#define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ | |
290 | -#define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ | |
291 | +#define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */ | |
292 | +#define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */ | |
293 | +#define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ | |
294 | +#define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */ | |
295 | +#define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */ | |
296 | +#define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */ | |
297 | +#define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */ | |
298 | +#define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */ | |
299 | +#define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ | |
300 | +#define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ | |
301 | ||
302 | /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ | |
303 | -#define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ | |
304 | -#define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ | |
305 | -#define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */ | |
306 | -#define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ | |
307 | -#define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ | |
308 | -#define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ | |
309 | -#define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */ | |
310 | -#define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */ | |
311 | -#define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */ | |
312 | -#define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */ | |
313 | -#define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */ | |
314 | -#define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */ | |
315 | -#define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */ | |
316 | -#define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ | |
317 | -#define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ | |
318 | -#define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ | |
319 | -#define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */ | |
320 | -#define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ | |
321 | -#define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */ | |
322 | -#define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */ | |
323 | -#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */ | |
324 | -#define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ | |
325 | -#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ | |
326 | -#define X86_FEATURE_PTSC ( 6*32+27) /* performance time-stamp counter */ | |
327 | -#define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */ | |
328 | -#define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */ | |
329 | +#define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ | |
330 | +#define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ | |
331 | +#define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */ | |
332 | +#define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ | |
333 | +#define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ | |
334 | +#define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ | |
335 | +#define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */ | |
336 | +#define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */ | |
337 | +#define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */ | |
338 | +#define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */ | |
339 | +#define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */ | |
340 | +#define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */ | |
341 | +#define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */ | |
342 | +#define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ | |
343 | +#define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ | |
344 | +#define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ | |
345 | +#define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */ | |
346 | +#define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ | |
347 | +#define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */ | |
348 | +#define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */ | |
349 | +#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */ | |
350 | +#define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ | |
351 | +#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ | |
352 | +#define X86_FEATURE_PTSC ( 6*32+27) /* performance time-stamp counter */ | |
353 | +#define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* Last Level Cache performance counter extensions */ | |
354 | +#define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */ | |
355 | ||
356 | /* | |
357 | * Auxiliary flags: Linux defined - For features scattered in various | |
358 | @@ -191,150 +191,152 @@ | |
359 | * | |
360 | * Reuse free bits when adding new feature flags! | |
361 | */ | |
362 | -#define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT */ | |
363 | -#define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */ | |
364 | -#define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ | |
365 | -#define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ | |
366 | -#define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */ | |
367 | -#define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */ | |
368 | -#define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */ | |
369 | +#define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT */ | |
370 | +#define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */ | |
371 | +#define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ | |
372 | +#define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ | |
373 | +#define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */ | |
374 | +#define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */ | |
375 | +#define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */ | |
376 | ||
377 | -#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ | |
378 | -#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ | |
379 | +#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ | |
380 | +#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ | |
381 | +#define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */ | |
382 | ||
383 | -#define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ | |
384 | -#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ | |
385 | -#define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */ | |
386 | -#define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */ | |
387 | +#define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ | |
388 | +#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ | |
389 | +#define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */ | |
390 | +#define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */ | |
391 | ||
392 | -#define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ | |
393 | +#define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ | |
394 | ||
395 | /* Virtualization flags: Linux defined, word 8 */ | |
396 | -#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ | |
397 | -#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ | |
398 | -#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ | |
399 | -#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ | |
400 | -#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ | |
401 | +#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ | |
402 | +#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ | |
403 | +#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ | |
404 | +#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ | |
405 | +#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ | |
406 | ||
407 | -#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ | |
408 | -#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ | |
409 | +#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ | |
410 | +#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ | |
411 | ||
412 | ||
413 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ | |
414 | -#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ | |
415 | -#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */ | |
416 | -#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ | |
417 | -#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ | |
418 | -#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ | |
419 | -#define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ | |
420 | -#define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ | |
421 | -#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */ | |
422 | -#define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ | |
423 | -#define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ | |
424 | -#define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ | |
425 | -#define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ | |
426 | -#define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */ | |
427 | -#define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ | |
428 | -#define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */ | |
429 | -#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ | |
430 | -#define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */ | |
431 | -#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ | |
432 | -#define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */ | |
433 | -#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ | |
434 | -#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ | |
435 | -#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ | |
436 | -#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ | |
437 | -#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ | |
438 | -#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ | |
439 | -#define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */ | |
440 | -#define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */ | |
441 | +#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ | |
442 | +#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */ | |
443 | +#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ | |
444 | +#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ | |
445 | +#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ | |
446 | +#define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ | |
447 | +#define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ | |
448 | +#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */ | |
449 | +#define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ | |
450 | +#define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ | |
451 | +#define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ | |
452 | +#define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ | |
453 | +#define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */ | |
454 | +#define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ | |
455 | +#define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */ | |
456 | +#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ | |
457 | +#define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */ | |
458 | +#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ | |
459 | +#define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */ | |
460 | +#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ | |
461 | +#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ | |
462 | +#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ | |
463 | +#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ | |
464 | +#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ | |
465 | +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ | |
466 | +#define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */ | |
467 | +#define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */ | |
468 | ||
469 | /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ | |
470 | -#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ | |
471 | -#define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */ | |
472 | -#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */ | |
473 | -#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */ | |
474 | +#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ | |
475 | +#define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */ | |
476 | +#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */ | |
477 | +#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */ | |
478 | ||
479 | /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */ | |
480 | -#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */ | |
481 | +#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */ | |
482 | ||
483 | /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */ | |
484 | -#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ | |
485 | -#define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */ | |
486 | -#define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */ | |
487 | +#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ | |
488 | +#define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */ | |
489 | +#define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */ | |
490 | ||
491 | /* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ | |
492 | -#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ | |
493 | -#define X86_FEATURE_IRPERF (13*32+1) /* Instructions Retired Count */ | |
494 | +#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ | |
495 | +#define X86_FEATURE_IRPERF (13*32+1) /* Instructions Retired Count */ | |
496 | ||
497 | /* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */ | |
498 | -#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ | |
499 | -#define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */ | |
500 | -#define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */ | |
501 | -#define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */ | |
502 | -#define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */ | |
503 | -#define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */ | |
504 | -#define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */ | |
505 | -#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */ | |
506 | -#define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ | |
507 | -#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ | |
508 | +#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ | |
509 | +#define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */ | |
510 | +#define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */ | |
511 | +#define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */ | |
512 | +#define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */ | |
513 | +#define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */ | |
514 | +#define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */ | |
515 | +#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */ | |
516 | +#define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ | |
517 | +#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ | |
518 | ||
519 | /* AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15 */ | |
520 | -#define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ | |
521 | -#define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */ | |
522 | -#define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */ | |
523 | -#define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */ | |
524 | -#define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */ | |
525 | -#define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */ | |
526 | -#define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */ | |
527 | -#define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */ | |
528 | -#define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */ | |
529 | -#define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */ | |
530 | -#define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */ | |
531 | -#define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */ | |
532 | +#define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ | |
533 | +#define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */ | |
534 | +#define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */ | |
535 | +#define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */ | |
536 | +#define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */ | |
537 | +#define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */ | |
538 | +#define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */ | |
539 | +#define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */ | |
540 | +#define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */ | |
541 | +#define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */ | |
542 | +#define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */ | |
543 | +#define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */ | |
544 | +#define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */ | |
545 | ||
546 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */ | |
547 | -#define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ | |
548 | -#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ | |
549 | -#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ | |
550 | -#define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */ | |
551 | -#define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */ | |
552 | -#define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */ | |
553 | -#define X86_FEATURE_VPCLMULQDQ (16*32+ 10) /* Carry-Less Multiplication Double Quadword */ | |
554 | -#define X86_FEATURE_AVX512_VNNI (16*32+ 11) /* Vector Neural Network Instructions */ | |
555 | -#define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB */ | |
556 | -#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */ | |
557 | -#define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */ | |
558 | -#define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */ | |
559 | +#define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ | |
560 | +#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ | |
561 | +#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ | |
562 | +#define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */ | |
563 | +#define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */ | |
564 | +#define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */ | |
565 | +#define X86_FEATURE_VPCLMULQDQ (16*32+ 10) /* Carry-Less Multiplication Double Quadword */ | |
566 | +#define X86_FEATURE_AVX512_VNNI (16*32+ 11) /* Vector Neural Network Instructions */ | |
567 | +#define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB */ | |
568 | +#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */ | |
569 | +#define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */ | |
570 | +#define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */ | |
571 | ||
572 | /* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */ | |
573 | -#define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */ | |
574 | -#define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment and recovery */ | |
575 | -#define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */ | |
576 | +#define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */ | |
577 | +#define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment and recovery */ | |
578 | +#define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */ | |
579 | ||
580 | /* | |
581 | * BUG word(s) | |
582 | */ | |
583 | -#define X86_BUG(x) (NCAPINTS*32 + (x)) | |
584 | +#define X86_BUG(x) (NCAPINTS*32 + (x)) | |
585 | ||
586 | -#define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ | |
587 | -#define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ | |
588 | -#define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ | |
589 | -#define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */ | |
590 | -#define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */ | |
591 | -#define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */ | |
592 | -#define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */ | |
593 | -#define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */ | |
594 | -#define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */ | |
595 | +#define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ | |
596 | +#define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ | |
597 | +#define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ | |
598 | +#define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */ | |
599 | +#define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */ | |
600 | +#define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */ | |
601 | +#define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */ | |
602 | +#define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */ | |
603 | +#define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */ | |
604 | #ifdef CONFIG_X86_32 | |
605 | /* | |
606 | * 64-bit kernels don't use X86_BUG_ESPFIX. Make the define conditional | |
607 | * to avoid confusion. | |
608 | */ | |
609 | -#define X86_BUG_ESPFIX X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */ | |
610 | +#define X86_BUG_ESPFIX X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */ | |
611 | #endif | |
612 | -#define X86_BUG_NULL_SEG X86_BUG(10) /* Nulling a selector preserves the base */ | |
613 | -#define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */ | |
614 | -#define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */ | |
615 | -#define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */ | |
616 | +#define X86_BUG_NULL_SEG X86_BUG(10) /* Nulling a selector preserves the base */ | |
617 | +#define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */ | |
618 | +#define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */ | |
619 | +#define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */ | |
620 | #endif /* _ASM_X86_CPUFEATURES_H */ | |
621 | -- | |
622 | 2.14.2 | |
623 |