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Commit | Line | Data |
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035dbe67 FG |
1 | From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 |
2 | From: Tim Chen <tim.c.chen@linux.intel.com> | |
3 | Date: Thu, 24 Aug 2017 09:34:41 -0700 | |
4 | Subject: [PATCH] x86/feature: Enable the x86 feature to control Speculation | |
5 | MIME-Version: 1.0 | |
6 | Content-Type: text/plain; charset=UTF-8 | |
7 | Content-Transfer-Encoding: 8bit | |
8 | ||
9 | CVE-2017-5753 | |
10 | CVE-2017-5715 | |
11 | ||
12 | cpuid ax=0x7, return rdx bit 26 to indicate presence of this feature | |
13 | IA32_SPEC_CTRL (0x48) and IA32_PRED_CMD (0x49) | |
14 | IA32_SPEC_CTRL, bit0 – Indirect Branch Restricted Speculation (IBRS) | |
15 | IA32_PRED_CMD, bit0 – Indirect Branch Prediction Barrier (IBPB) | |
16 | ||
17 | Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com> | |
18 | Signed-off-by: Andy Whitcroft <apw@canonical.com> | |
19 | Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com> | |
20 | (cherry picked from commit f1f160a92b70c25d6e6e76788463bbec86a73313) | |
21 | Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com> | |
22 | --- | |
23 | arch/x86/include/asm/cpufeatures.h | 1 + | |
24 | arch/x86/include/asm/msr-index.h | 5 +++++ | |
25 | arch/x86/kernel/cpu/scattered.c | 1 + | |
26 | 3 files changed, 7 insertions(+) | |
27 | ||
28 | diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h | |
29 | index 3928050b51b0..44be8fd069bf 100644 | |
30 | --- a/arch/x86/include/asm/cpufeatures.h | |
31 | +++ b/arch/x86/include/asm/cpufeatures.h | |
32 | @@ -208,6 +208,7 @@ | |
33 | #define X86_FEATURE_AVX512_4FMAPS ( 7*32+17) /* AVX-512 Multiply Accumulation Single precision */ | |
34 | ||
35 | #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ | |
36 | +#define X86_FEATURE_SPEC_CTRL ( 7*32+19) /* Control Speculation Control */ | |
37 | ||
38 | /* Virtualization flags: Linux defined, word 8 */ | |
39 | #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ | |
40 | diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h | |
41 | index db88b7f852b4..4e3438a00a50 100644 | |
42 | --- a/arch/x86/include/asm/msr-index.h | |
43 | +++ b/arch/x86/include/asm/msr-index.h | |
44 | @@ -41,6 +41,9 @@ | |
45 | #define MSR_PPIN_CTL 0x0000004e | |
46 | #define MSR_PPIN 0x0000004f | |
47 | ||
48 | +#define MSR_IA32_SPEC_CTRL 0x00000048 | |
49 | +#define MSR_IA32_PRED_CMD 0x00000049 | |
50 | + | |
51 | #define MSR_IA32_PERFCTR0 0x000000c1 | |
52 | #define MSR_IA32_PERFCTR1 0x000000c2 | |
53 | #define MSR_FSB_FREQ 0x000000cd | |
54 | @@ -437,6 +440,8 @@ | |
55 | #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) | |
56 | #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) | |
57 | #define FEATURE_CONTROL_LMCE (1<<20) | |
58 | +#define FEATURE_ENABLE_IBRS (1<<0) | |
59 | +#define FEATURE_SET_IBPB (1<<0) | |
60 | ||
61 | #define MSR_IA32_APICBASE 0x0000001b | |
62 | #define MSR_IA32_APICBASE_BSP (1<<8) | |
63 | diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c | |
64 | index 23c23508c012..9651ea395812 100644 | |
65 | --- a/arch/x86/kernel/cpu/scattered.c | |
66 | +++ b/arch/x86/kernel/cpu/scattered.c | |
67 | @@ -24,6 +24,7 @@ static const struct cpuid_bit cpuid_bits[] = { | |
68 | { X86_FEATURE_INTEL_PT, CPUID_EBX, 25, 0x00000007, 0 }, | |
69 | { X86_FEATURE_AVX512_4VNNIW, CPUID_EDX, 2, 0x00000007, 0 }, | |
70 | { X86_FEATURE_AVX512_4FMAPS, CPUID_EDX, 3, 0x00000007, 0 }, | |
71 | + { X86_FEATURE_SPEC_CTRL, CPUID_EDX, 26, 0x00000007, 0 }, | |
72 | { X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 }, | |
73 | { X86_FEATURE_CAT_L2, CPUID_EBX, 2, 0x00000010, 0 }, | |
74 | { X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 }, | |
75 | -- | |
76 | 2.14.2 | |
77 |