projects / pve-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 035dbe67 FG |
1 | From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 |
| 2 | From: Tim Chen <tim.c.chen@linux.intel.com> | |
| 3 | Date: Fri, 15 Sep 2017 18:04:53 -0700 | |
| 4 | Subject: [PATCH] x86/enter: MACROS to set/clear IBRS and set IBPB | |
| 5 | MIME-Version: 1.0 | |
| 6 | Content-Type: text/plain; charset=UTF-8 | |
| 7 | Content-Transfer-Encoding: 8bit | |
| 8 | ||
| 9 | CVE-2017-5753 | |
| 10 | CVE-2017-5715 | |
| 11 | ||
| 12 | Setup macros to control IBRS and IBPB | |
| 13 | ||
| 14 | Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com> | |
| 15 | Signed-off-by: Andy Whitcroft <apw@canonical.com> | |
| 16 | Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com> | |
| 17 | (cherry picked from commit 171d754fe3b783d361555cf2569e68a7b0e0d54a) | |
| 18 | Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com> | |
| 19 | --- | |
| 20 | arch/x86/include/asm/spec_ctrl.h | 52 ++++++++++++++++++++++++++++++++++++++++ | |
| 21 | 1 file changed, 52 insertions(+) | |
| 22 | create mode 100644 arch/x86/include/asm/spec_ctrl.h | |
| 23 | ||
| 24 | diff --git a/arch/x86/include/asm/spec_ctrl.h b/arch/x86/include/asm/spec_ctrl.h | |
| 25 | new file mode 100644 | |
| 26 | index 000000000000..7f8bb09b6acb | |
| 27 | --- /dev/null | |
| 28 | +++ b/arch/x86/include/asm/spec_ctrl.h | |
| 29 | @@ -0,0 +1,52 @@ | |
| 30 | +#ifndef _ASM_X86_SPEC_CTRL_H | |
| 31 | +#define _ASM_X86_SPEC_CTRL_H | |
| 32 | + | |
| 33 | +#include <linux/stringify.h> | |
| 34 | +#include <asm/msr-index.h> | |
| 35 | +#include <asm/cpufeatures.h> | |
| 36 | +#include <asm/alternative-asm.h> | |
| 37 | + | |
| 38 | +#ifdef __ASSEMBLY__ | |
| 39 | + | |
| 40 | +#define __ASM_ENABLE_IBRS \ | |
| 41 | + pushq %rax; \ | |
| 42 | + pushq %rcx; \ | |
| 43 | + pushq %rdx; \ | |
| 44 | + movl $MSR_IA32_SPEC_CTRL, %ecx; \ | |
| 45 | + movl $0, %edx; \ | |
| 46 | + movl $FEATURE_ENABLE_IBRS, %eax; \ | |
| 47 | + wrmsr; \ | |
| 48 | + popq %rdx; \ | |
| 49 | + popq %rcx; \ | |
| 50 | + popq %rax | |
| 51 | +#define __ASM_ENABLE_IBRS_CLOBBER \ | |
| 52 | + movl $MSR_IA32_SPEC_CTRL, %ecx; \ | |
| 53 | + movl $0, %edx; \ | |
| 54 | + movl $FEATURE_ENABLE_IBRS, %eax; \ | |
| 55 | + wrmsr; | |
| 56 | +#define __ASM_DISABLE_IBRS \ | |
| 57 | + pushq %rax; \ | |
| 58 | + pushq %rcx; \ | |
| 59 | + pushq %rdx; \ | |
| 60 | + movl $MSR_IA32_SPEC_CTRL, %ecx; \ | |
| 61 | + movl $0, %edx; \ | |
| 62 | + movl $0, %eax; \ | |
| 63 | + wrmsr; \ | |
| 64 | + popq %rdx; \ | |
| 65 | + popq %rcx; \ | |
| 66 | + popq %rax | |
| 67 | + | |
| 68 | +.macro ENABLE_IBRS | |
| 69 | +ALTERNATIVE "", __stringify(__ASM_ENABLE_IBRS), X86_FEATURE_SPEC_CTRL | |
| 70 | +.endm | |
| 71 | + | |
| 72 | +.macro ENABLE_IBRS_CLOBBER | |
| 73 | +ALTERNATIVE "", __stringify(__ASM_ENABLE_IBRS_CLOBBER), X86_FEATURE_SPEC_CTRL | |
| 74 | +.endm | |
| 75 | + | |
| 76 | +.macro DISABLE_IBRS | |
| 77 | +ALTERNATIVE "", __stringify(__ASM_DISABLE_IBRS), X86_FEATURE_SPEC_CTRL | |
| 78 | +.endm | |
| 79 | + | |
| 80 | +#endif /* __ASSEMBLY__ */ | |
| 81 | +#endif /* _ASM_X86_SPEC_CTRL_H */ | |
| 82 | -- | |
| 83 | 2.14.2 | |
| 84 |