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5aa54b75 FG |
1 | From 78388cbea036c9a9e2fd0c71e21d608cfc63939a Mon Sep 17 00:00:00 2001 |
2 | From: Julia Cartwright <julia@ni.com> | |
3 | Date: Thu, 1 Jun 2017 13:12:16 +0800 | |
4 | Subject: [PATCH] pinctrl: amd: make use of raw_spinlock variants | |
5 | MIME-Version: 1.0 | |
6 | Content-Type: text/plain; charset=UTF-8 | |
7 | Content-Transfer-Encoding: 8bit | |
8 | ||
9 | BugLink: https://bugs.launchpad.net/bugs/1671360 | |
10 | ||
11 | The amd pinctrl drivers currently implement an irq_chip for handling | |
12 | interrupts; due to how irq_chip handling is done, it's necessary for the | |
13 | irq_chip methods to be invoked from hardirq context, even on a a | |
14 | real-time kernel. Because the spinlock_t type becomes a "sleeping" | |
15 | spinlock w/ RT kernels, it is not suitable to be used with irq_chips. | |
16 | ||
17 | A quick audit of the operations under the lock reveal that they do only | |
18 | minimal, bounded work, and are therefore safe to do under a raw spinlock. | |
19 | ||
20 | Signed-off-by: Julia Cartwright <julia@ni.com> | |
21 | Signed-off-by: Linus Walleij <linus.walleij@linaro.org> | |
22 | (cherry picked from commit 229710fecdd805abb753c480778ea0de47cbb1e2) | |
23 | Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> | |
24 | Acked-by: Stefan Bader <stefan.bader@canonical.com> | |
25 | Acked-by: Seth Forshee <seth.forshee@canonical.com> | |
26 | Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com> | |
27 | Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com> | |
28 | --- | |
29 | drivers/pinctrl/pinctrl-amd.h | 2 +- | |
30 | drivers/pinctrl/pinctrl-amd.c | 66 +++++++++++++++++++++---------------------- | |
31 | 2 files changed, 34 insertions(+), 34 deletions(-) | |
32 | ||
33 | diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h | |
34 | index 7bfea47dbb47..4d5d5cac48a9 100644 | |
35 | --- a/drivers/pinctrl/pinctrl-amd.h | |
36 | +++ b/drivers/pinctrl/pinctrl-amd.h | |
37 | @@ -86,7 +86,7 @@ struct amd_function { | |
38 | }; | |
39 | ||
40 | struct amd_gpio { | |
41 | - spinlock_t lock; | |
42 | + raw_spinlock_t lock; | |
43 | void __iomem *base; | |
44 | ||
45 | const struct amd_pingroup *groups; | |
46 | diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c | |
47 | index 537b52055756..cfcf9db02c7d 100644 | |
48 | --- a/drivers/pinctrl/pinctrl-amd.c | |
49 | +++ b/drivers/pinctrl/pinctrl-amd.c | |
50 | @@ -41,11 +41,11 @@ static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) | |
51 | u32 pin_reg; | |
52 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); | |
53 | ||
54 | - spin_lock_irqsave(&gpio_dev->lock, flags); | |
55 | + raw_spin_lock_irqsave(&gpio_dev->lock, flags); | |
56 | pin_reg = readl(gpio_dev->base + offset * 4); | |
57 | pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); | |
58 | writel(pin_reg, gpio_dev->base + offset * 4); | |
59 | - spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
60 | + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
61 | ||
62 | return 0; | |
63 | } | |
64 | @@ -57,7 +57,7 @@ static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, | |
65 | unsigned long flags; | |
66 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); | |
67 | ||
68 | - spin_lock_irqsave(&gpio_dev->lock, flags); | |
69 | + raw_spin_lock_irqsave(&gpio_dev->lock, flags); | |
70 | pin_reg = readl(gpio_dev->base + offset * 4); | |
71 | pin_reg |= BIT(OUTPUT_ENABLE_OFF); | |
72 | if (value) | |
73 | @@ -65,7 +65,7 @@ static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, | |
74 | else | |
75 | pin_reg &= ~BIT(OUTPUT_VALUE_OFF); | |
76 | writel(pin_reg, gpio_dev->base + offset * 4); | |
77 | - spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
78 | + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
79 | ||
80 | return 0; | |
81 | } | |
82 | @@ -76,9 +76,9 @@ static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) | |
83 | unsigned long flags; | |
84 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); | |
85 | ||
86 | - spin_lock_irqsave(&gpio_dev->lock, flags); | |
87 | + raw_spin_lock_irqsave(&gpio_dev->lock, flags); | |
88 | pin_reg = readl(gpio_dev->base + offset * 4); | |
89 | - spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
90 | + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
91 | ||
92 | return !!(pin_reg & BIT(PIN_STS_OFF)); | |
93 | } | |
94 | @@ -89,14 +89,14 @@ static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) | |
95 | unsigned long flags; | |
96 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); | |
97 | ||
98 | - spin_lock_irqsave(&gpio_dev->lock, flags); | |
99 | + raw_spin_lock_irqsave(&gpio_dev->lock, flags); | |
100 | pin_reg = readl(gpio_dev->base + offset * 4); | |
101 | if (value) | |
102 | pin_reg |= BIT(OUTPUT_VALUE_OFF); | |
103 | else | |
104 | pin_reg &= ~BIT(OUTPUT_VALUE_OFF); | |
105 | writel(pin_reg, gpio_dev->base + offset * 4); | |
106 | - spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
107 | + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
108 | } | |
109 | ||
110 | static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, | |
111 | @@ -108,7 +108,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, | |
112 | unsigned long flags; | |
113 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); | |
114 | ||
115 | - spin_lock_irqsave(&gpio_dev->lock, flags); | |
116 | + raw_spin_lock_irqsave(&gpio_dev->lock, flags); | |
117 | pin_reg = readl(gpio_dev->base + offset * 4); | |
118 | ||
119 | if (debounce) { | |
120 | @@ -159,7 +159,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, | |
121 | pin_reg &= ~DB_CNTRl_MASK; | |
122 | } | |
123 | writel(pin_reg, gpio_dev->base + offset * 4); | |
124 | - spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
125 | + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
126 | ||
127 | return ret; | |
128 | } | |
129 | @@ -208,9 +208,9 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) | |
130 | ||
131 | for (; i < pin_num; i++) { | |
132 | seq_printf(s, "pin%d\t", i); | |
133 | - spin_lock_irqsave(&gpio_dev->lock, flags); | |
134 | + raw_spin_lock_irqsave(&gpio_dev->lock, flags); | |
135 | pin_reg = readl(gpio_dev->base + i * 4); | |
136 | - spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
137 | + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
138 | ||
139 | if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { | |
140 | interrupt_enable = "interrupt is enabled|"; | |
141 | @@ -315,12 +315,12 @@ static void amd_gpio_irq_enable(struct irq_data *d) | |
142 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
143 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); | |
144 | ||
145 | - spin_lock_irqsave(&gpio_dev->lock, flags); | |
146 | + raw_spin_lock_irqsave(&gpio_dev->lock, flags); | |
147 | pin_reg = readl(gpio_dev->base + (d->hwirq)*4); | |
148 | pin_reg |= BIT(INTERRUPT_ENABLE_OFF); | |
149 | pin_reg |= BIT(INTERRUPT_MASK_OFF); | |
150 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); | |
151 | - spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
152 | + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
153 | } | |
154 | ||
155 | static void amd_gpio_irq_disable(struct irq_data *d) | |
156 | @@ -330,12 +330,12 @@ static void amd_gpio_irq_disable(struct irq_data *d) | |
157 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
158 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); | |
159 | ||
160 | - spin_lock_irqsave(&gpio_dev->lock, flags); | |
161 | + raw_spin_lock_irqsave(&gpio_dev->lock, flags); | |
162 | pin_reg = readl(gpio_dev->base + (d->hwirq)*4); | |
163 | pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); | |
164 | pin_reg &= ~BIT(INTERRUPT_MASK_OFF); | |
165 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); | |
166 | - spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
167 | + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
168 | } | |
169 | ||
170 | static void amd_gpio_irq_mask(struct irq_data *d) | |
171 | @@ -345,11 +345,11 @@ static void amd_gpio_irq_mask(struct irq_data *d) | |
172 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
173 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); | |
174 | ||
175 | - spin_lock_irqsave(&gpio_dev->lock, flags); | |
176 | + raw_spin_lock_irqsave(&gpio_dev->lock, flags); | |
177 | pin_reg = readl(gpio_dev->base + (d->hwirq)*4); | |
178 | pin_reg &= ~BIT(INTERRUPT_MASK_OFF); | |
179 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); | |
180 | - spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
181 | + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
182 | } | |
183 | ||
184 | static void amd_gpio_irq_unmask(struct irq_data *d) | |
185 | @@ -359,11 +359,11 @@ static void amd_gpio_irq_unmask(struct irq_data *d) | |
186 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
187 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); | |
188 | ||
189 | - spin_lock_irqsave(&gpio_dev->lock, flags); | |
190 | + raw_spin_lock_irqsave(&gpio_dev->lock, flags); | |
191 | pin_reg = readl(gpio_dev->base + (d->hwirq)*4); | |
192 | pin_reg |= BIT(INTERRUPT_MASK_OFF); | |
193 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); | |
194 | - spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
195 | + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
196 | } | |
197 | ||
198 | static void amd_gpio_irq_eoi(struct irq_data *d) | |
199 | @@ -373,11 +373,11 @@ static void amd_gpio_irq_eoi(struct irq_data *d) | |
200 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
201 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); | |
202 | ||
203 | - spin_lock_irqsave(&gpio_dev->lock, flags); | |
204 | + raw_spin_lock_irqsave(&gpio_dev->lock, flags); | |
205 | reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); | |
206 | reg |= EOI_MASK; | |
207 | writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); | |
208 | - spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
209 | + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
210 | } | |
211 | ||
212 | static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |
213 | @@ -388,7 +388,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |
214 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
215 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); | |
216 | ||
217 | - spin_lock_irqsave(&gpio_dev->lock, flags); | |
218 | + raw_spin_lock_irqsave(&gpio_dev->lock, flags); | |
219 | pin_reg = readl(gpio_dev->base + (d->hwirq)*4); | |
220 | ||
221 | /* Ignore the settings coming from the client and | |
222 | @@ -453,7 +453,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |
223 | ||
224 | pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; | |
225 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); | |
226 | - spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
227 | + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
228 | ||
229 | return ret; | |
230 | } | |
231 | @@ -494,14 +494,14 @@ static void amd_gpio_irq_handler(struct irq_desc *desc) | |
232 | ||
233 | chained_irq_enter(chip, desc); | |
234 | /*enable GPIO interrupt again*/ | |
235 | - spin_lock_irqsave(&gpio_dev->lock, flags); | |
236 | + raw_spin_lock_irqsave(&gpio_dev->lock, flags); | |
237 | reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); | |
238 | reg64 = reg; | |
239 | reg64 = reg64 << 32; | |
240 | ||
241 | reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0); | |
242 | reg64 |= reg; | |
243 | - spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
244 | + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
245 | ||
246 | /* | |
247 | * first 46 bits indicates interrupt status. | |
248 | @@ -529,11 +529,11 @@ static void amd_gpio_irq_handler(struct irq_desc *desc) | |
249 | if (handled == 0) | |
250 | handle_bad_irq(desc); | |
251 | ||
252 | - spin_lock_irqsave(&gpio_dev->lock, flags); | |
253 | + raw_spin_lock_irqsave(&gpio_dev->lock, flags); | |
254 | reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); | |
255 | reg |= EOI_MASK; | |
256 | writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); | |
257 | - spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
258 | + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
259 | ||
260 | chained_irq_exit(chip, desc); | |
261 | } | |
262 | @@ -585,9 +585,9 @@ static int amd_pinconf_get(struct pinctrl_dev *pctldev, | |
263 | struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); | |
264 | enum pin_config_param param = pinconf_to_config_param(*config); | |
265 | ||
266 | - spin_lock_irqsave(&gpio_dev->lock, flags); | |
267 | + raw_spin_lock_irqsave(&gpio_dev->lock, flags); | |
268 | pin_reg = readl(gpio_dev->base + pin*4); | |
269 | - spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
270 | + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
271 | switch (param) { | |
272 | case PIN_CONFIG_INPUT_DEBOUNCE: | |
273 | arg = pin_reg & DB_TMR_OUT_MASK; | |
274 | @@ -627,7 +627,7 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
275 | enum pin_config_param param; | |
276 | struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); | |
277 | ||
278 | - spin_lock_irqsave(&gpio_dev->lock, flags); | |
279 | + raw_spin_lock_irqsave(&gpio_dev->lock, flags); | |
280 | for (i = 0; i < num_configs; i++) { | |
281 | param = pinconf_to_config_param(configs[i]); | |
282 | arg = pinconf_to_config_argument(configs[i]); | |
283 | @@ -666,7 +666,7 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
284 | ||
285 | writel(pin_reg, gpio_dev->base + pin*4); | |
286 | } | |
287 | - spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
288 | + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
289 | ||
290 | return ret; | |
291 | } | |
292 | @@ -734,7 +734,7 @@ static int amd_gpio_probe(struct platform_device *pdev) | |
293 | if (!gpio_dev) | |
294 | return -ENOMEM; | |
295 | ||
296 | - spin_lock_init(&gpio_dev->lock); | |
297 | + raw_spin_lock_init(&gpio_dev->lock); | |
298 | ||
299 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
300 | if (!res) { | |
301 | -- | |
302 | 2.11.0 | |
303 |