]> git.proxmox.com Git - mirror_qemu.git/blame - qemu-barrier.h
qmp: add NBD server commands
[mirror_qemu.git] / qemu-barrier.h
CommitLineData
85199474
MT
1#ifndef __QEMU_BARRIER_H
2#define __QEMU_BARRIER_H 1
3
1d93f0f0
JK
4/* Compiler barrier */
5#define barrier() asm volatile("" ::: "memory")
6
a281ebc1 7#if defined(__i386__)
e2251708 8
f1829782 9#include "compiler.h" /* QEMU_GNUC_PREREQ */
1d31fca4 10
e2251708 11/*
a821ce59 12 * Because of the strongly ordered x86 storage model, wmb() and rmb() are nops
e2251708
DG
13 * on x86(well, a compiler barrier only). Well, at least as long as
14 * qemu doesn't do accesses to write-combining memory or non-temporal
15 * load/stores from C code.
16 */
17#define smp_wmb() barrier()
a821ce59 18#define smp_rmb() barrier()
a281ebc1
MT
19/*
20 * We use GCC builtin if it's available, as that can use
21 * mfence on 32 bit as well, e.g. if built with -march=pentium-m.
22 * However, on i386, there seem to be known bugs as recently as 4.3.
23 * */
610b823e 24#if QEMU_GNUC_PREREQ(4, 4)
a281ebc1
MT
25#define smp_mb() __sync_synchronize()
26#else
27#define smp_mb() asm volatile("lock; addl $0,0(%%esp) " ::: "memory")
28#endif
29
30#elif defined(__x86_64__)
31
32#define smp_wmb() barrier()
a821ce59 33#define smp_rmb() barrier()
a281ebc1 34#define smp_mb() asm volatile("mfence" ::: "memory")
e2251708 35
463ce4ae 36#elif defined(_ARCH_PPC)
e2251708
DG
37
38/*
a281ebc1 39 * We use an eieio() for wmb() on powerpc. This assumes we don't
e2251708
DG
40 * need to order cacheable and non-cacheable stores with respect to
41 * each other
42 */
43#define smp_wmb() asm volatile("eieio" ::: "memory")
a821ce59
MT
44
45#if defined(__powerpc64__)
46#define smp_rmb() asm volatile("lwsync" ::: "memory")
47#else
48#define smp_rmb() asm volatile("sync" ::: "memory")
49#endif
50
a281ebc1 51#define smp_mb() asm volatile("sync" ::: "memory")
e2251708
DG
52
53#else
54
55/*
56 * For (host) platforms we don't have explicit barrier definitions
57 * for, we use the gcc __sync_synchronize() primitive to generate a
58 * full barrier. This should be safe on all platforms, though it may
a821ce59 59 * be overkill for wmb() and rmb().
e2251708
DG
60 */
61#define smp_wmb() __sync_synchronize()
a281ebc1 62#define smp_mb() __sync_synchronize()
a821ce59 63#define smp_rmb() __sync_synchronize()
e2251708
DG
64
65#endif
66
85199474 67#endif