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Commit | Line | Data |
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dd83b06a AF |
1 | /* |
2 | * QEMU CPU model | |
3 | * | |
1590bbcb | 4 | * Copyright (c) 2012-2014 SUSE LINUX Products GmbH |
dd83b06a AF |
5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
1ef26b1f | 21 | #include "qemu/osdep.h" |
da34e65c | 22 | #include "qapi/error.h" |
dd83b06a | 23 | #include "qemu-common.h" |
878096ee | 24 | #include "qom/cpu.h" |
b3946626 | 25 | #include "sysemu/hw_accel.h" |
066e9b27 | 26 | #include "qemu/notify.h" |
91b1df8c | 27 | #include "qemu/log.h" |
508127e2 | 28 | #include "exec/log.h" |
2cd53943 | 29 | #include "exec/cpu-common.h" |
9262685b | 30 | #include "qemu/error-report.h" |
066e9b27 | 31 | #include "sysemu/sysemu.h" |
ed860129 | 32 | #include "hw/boards.h" |
62a48a2a | 33 | #include "hw/qdev-properties.h" |
0ab8ed18 | 34 | #include "trace-root.h" |
066e9b27 | 35 | |
290dae46 PB |
36 | CPUInterruptHandler cpu_interrupt_handler; |
37 | ||
5ce46cb3 | 38 | CPUState *cpu_by_arch_id(int64_t id) |
69e5ff06 | 39 | { |
38fcbd3f AF |
40 | CPUState *cpu; |
41 | ||
42 | CPU_FOREACH(cpu) { | |
43 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
69e5ff06 | 44 | |
38fcbd3f | 45 | if (cc->get_arch_id(cpu) == id) { |
5ce46cb3 | 46 | return cpu; |
38fcbd3f AF |
47 | } |
48 | } | |
5ce46cb3 EH |
49 | return NULL; |
50 | } | |
51 | ||
52 | bool cpu_exists(int64_t id) | |
53 | { | |
54 | return !!cpu_by_arch_id(id); | |
69e5ff06 IM |
55 | } |
56 | ||
3c72234c IM |
57 | CPUState *cpu_create(const char *typename) |
58 | { | |
59 | Error *err = NULL; | |
60 | CPUState *cpu = CPU(object_new(typename)); | |
61 | object_property_set_bool(OBJECT(cpu), true, "realized", &err); | |
62 | if (err != NULL) { | |
63 | error_report_err(err); | |
64 | object_unref(OBJECT(cpu)); | |
4482e05c | 65 | exit(EXIT_FAILURE); |
3c72234c IM |
66 | } |
67 | return cpu; | |
68 | } | |
69 | ||
70 | const char *cpu_parse_cpu_model(const char *typename, const char *cpu_model) | |
9262685b | 71 | { |
9262685b AF |
72 | ObjectClass *oc; |
73 | CPUClass *cc; | |
3e2cf187 | 74 | gchar **model_pieces; |
3c72234c | 75 | const char *cpu_type; |
9262685b | 76 | |
3e2cf187 | 77 | model_pieces = g_strsplit(cpu_model, ",", 2); |
9262685b | 78 | |
3e2cf187 | 79 | oc = cpu_class_by_name(typename, model_pieces[0]); |
9262685b | 80 | if (oc == NULL) { |
4482e05c | 81 | error_report("unable to find CPU model '%s'", model_pieces[0]); |
3e2cf187 | 82 | g_strfreev(model_pieces); |
4482e05c | 83 | exit(EXIT_FAILURE); |
9262685b AF |
84 | } |
85 | ||
3c72234c | 86 | cpu_type = object_class_get_name(oc); |
62a48a2a | 87 | cc = CPU_CLASS(oc); |
4482e05c | 88 | cc->parse_features(cpu_type, model_pieces[1], &error_fatal); |
3e2cf187 | 89 | g_strfreev(model_pieces); |
3c72234c IM |
90 | return cpu_type; |
91 | } | |
9262685b | 92 | |
3c72234c IM |
93 | CPUState *cpu_generic_init(const char *typename, const char *cpu_model) |
94 | { | |
95 | /* TODO: all callers of cpu_generic_init() need to be converted to | |
96 | * call cpu_parse_features() only once, before calling cpu_generic_init(). | |
97 | */ | |
4482e05c | 98 | return cpu_create(cpu_parse_cpu_model(typename, cpu_model)); |
9262685b AF |
99 | } |
100 | ||
444d5590 AF |
101 | bool cpu_paging_enabled(const CPUState *cpu) |
102 | { | |
103 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
104 | ||
105 | return cc->get_paging_enabled(cpu); | |
106 | } | |
107 | ||
108 | static bool cpu_common_get_paging_enabled(const CPUState *cpu) | |
109 | { | |
6db297ea | 110 | return false; |
444d5590 AF |
111 | } |
112 | ||
a23bbfda AF |
113 | void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, |
114 | Error **errp) | |
115 | { | |
116 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
117 | ||
fbe95bfb | 118 | cc->get_memory_mapping(cpu, list, errp); |
a23bbfda AF |
119 | } |
120 | ||
121 | static void cpu_common_get_memory_mapping(CPUState *cpu, | |
122 | MemoryMappingList *list, | |
123 | Error **errp) | |
124 | { | |
125 | error_setg(errp, "Obtaining memory mappings is unsupported on this CPU."); | |
126 | } | |
127 | ||
8d04fb55 JK |
128 | /* Resetting the IRQ comes from across the code base so we take the |
129 | * BQL here if we need to. cpu_interrupt assumes it is held.*/ | |
d8ed887b AF |
130 | void cpu_reset_interrupt(CPUState *cpu, int mask) |
131 | { | |
8d04fb55 JK |
132 | bool need_lock = !qemu_mutex_iothread_locked(); |
133 | ||
134 | if (need_lock) { | |
135 | qemu_mutex_lock_iothread(); | |
136 | } | |
d8ed887b | 137 | cpu->interrupt_request &= ~mask; |
8d04fb55 JK |
138 | if (need_lock) { |
139 | qemu_mutex_unlock_iothread(); | |
140 | } | |
d8ed887b AF |
141 | } |
142 | ||
60a3e17a AF |
143 | void cpu_exit(CPUState *cpu) |
144 | { | |
027d9a7d | 145 | atomic_set(&cpu->exit_request, 1); |
ab096a75 PB |
146 | /* Ensure cpu_exec will see the exit request after TCG has exited. */ |
147 | smp_wmb(); | |
1aab16c2 | 148 | atomic_set(&cpu->icount_decr.u16.high, -1); |
60a3e17a AF |
149 | } |
150 | ||
c72bf468 JF |
151 | int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, |
152 | void *opaque) | |
153 | { | |
154 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
155 | ||
156 | return (*cc->write_elf32_qemunote)(f, cpu, opaque); | |
157 | } | |
158 | ||
159 | static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f, | |
160 | CPUState *cpu, void *opaque) | |
161 | { | |
b09afd58 | 162 | return 0; |
c72bf468 JF |
163 | } |
164 | ||
165 | int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
166 | int cpuid, void *opaque) | |
167 | { | |
168 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
169 | ||
170 | return (*cc->write_elf32_note)(f, cpu, cpuid, opaque); | |
171 | } | |
172 | ||
173 | static int cpu_common_write_elf32_note(WriteCoreDumpFunction f, | |
174 | CPUState *cpu, int cpuid, | |
175 | void *opaque) | |
176 | { | |
177 | return -1; | |
178 | } | |
179 | ||
180 | int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
181 | void *opaque) | |
182 | { | |
183 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
184 | ||
185 | return (*cc->write_elf64_qemunote)(f, cpu, opaque); | |
186 | } | |
187 | ||
188 | static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f, | |
189 | CPUState *cpu, void *opaque) | |
190 | { | |
b09afd58 | 191 | return 0; |
c72bf468 JF |
192 | } |
193 | ||
194 | int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
195 | int cpuid, void *opaque) | |
196 | { | |
197 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
198 | ||
199 | return (*cc->write_elf64_note)(f, cpu, cpuid, opaque); | |
200 | } | |
201 | ||
202 | static int cpu_common_write_elf64_note(WriteCoreDumpFunction f, | |
203 | CPUState *cpu, int cpuid, | |
204 | void *opaque) | |
205 | { | |
206 | return -1; | |
207 | } | |
208 | ||
209 | ||
5b50e790 AF |
210 | static int cpu_common_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg) |
211 | { | |
212 | return 0; | |
213 | } | |
214 | ||
215 | static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg) | |
216 | { | |
217 | return 0; | |
218 | } | |
219 | ||
568496c0 SF |
220 | static bool cpu_common_debug_check_watchpoint(CPUState *cpu, CPUWatchpoint *wp) |
221 | { | |
222 | /* If no extra check is required, QEMU watchpoint match can be considered | |
223 | * as an architectural match. | |
224 | */ | |
225 | return true; | |
226 | } | |
227 | ||
bf7663c4 GK |
228 | bool target_words_bigendian(void); |
229 | static bool cpu_common_virtio_is_big_endian(CPUState *cpu) | |
230 | { | |
231 | return target_words_bigendian(); | |
232 | } | |
5b50e790 | 233 | |
cffe7b32 | 234 | static void cpu_common_noop(CPUState *cpu) |
86025ee4 PM |
235 | { |
236 | } | |
237 | ||
9585db68 RH |
238 | static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req) |
239 | { | |
240 | return false; | |
241 | } | |
242 | ||
c86f106b AN |
243 | GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) |
244 | { | |
245 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
246 | GuestPanicInformation *res = NULL; | |
247 | ||
248 | if (cc->get_crash_info) { | |
249 | res = cc->get_crash_info(cpu); | |
250 | } | |
251 | return res; | |
252 | } | |
253 | ||
878096ee AF |
254 | void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, |
255 | int flags) | |
256 | { | |
257 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
258 | ||
259 | if (cc->dump_state) { | |
97577fd4 | 260 | cpu_synchronize_state(cpu); |
878096ee AF |
261 | cc->dump_state(cpu, f, cpu_fprintf, flags); |
262 | } | |
263 | } | |
264 | ||
265 | void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
266 | int flags) | |
267 | { | |
268 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
269 | ||
270 | if (cc->dump_statistics) { | |
271 | cc->dump_statistics(cpu, f, cpu_fprintf, flags); | |
272 | } | |
273 | } | |
274 | ||
dd83b06a AF |
275 | void cpu_reset(CPUState *cpu) |
276 | { | |
277 | CPUClass *klass = CPU_GET_CLASS(cpu); | |
278 | ||
279 | if (klass->reset != NULL) { | |
280 | (*klass->reset)(cpu); | |
281 | } | |
2cc2d082 LV |
282 | |
283 | trace_guest_cpu_reset(cpu); | |
dd83b06a AF |
284 | } |
285 | ||
286 | static void cpu_common_reset(CPUState *cpu) | |
287 | { | |
91b1df8c AF |
288 | CPUClass *cc = CPU_GET_CLASS(cpu); |
289 | ||
290 | if (qemu_loglevel_mask(CPU_LOG_RESET)) { | |
291 | qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index); | |
292 | log_cpu_state(cpu, cc->reset_dump_flags); | |
293 | } | |
294 | ||
259186a7 | 295 | cpu->interrupt_request = 0; |
259186a7 | 296 | cpu->halted = 0; |
93afeade AF |
297 | cpu->mem_io_pc = 0; |
298 | cpu->mem_io_vaddr = 0; | |
efee7340 | 299 | cpu->icount_extra = 0; |
28ecfd7a | 300 | cpu->icount_decr.u32 = 0; |
414b15c9 | 301 | cpu->can_do_io = 1; |
f9d8f667 | 302 | cpu->exception_index = -1; |
bac05aa9 | 303 | cpu->crash_occurred = false; |
9b990ee5 | 304 | cpu->cflags_next_tb = -1; |
ce7cf6a9 | 305 | |
ba7d3d18 | 306 | if (tcg_enabled()) { |
f3ced3c5 | 307 | cpu_tb_jmp_cache_clear(cpu); |
1f5c00cf | 308 | |
2cd53943 | 309 | tcg_flush_softmmu_tlb(cpu); |
ba7d3d18 | 310 | } |
dd83b06a AF |
311 | } |
312 | ||
8c2e1b00 AF |
313 | static bool cpu_common_has_work(CPUState *cs) |
314 | { | |
315 | return false; | |
316 | } | |
317 | ||
2b8c2754 AF |
318 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model) |
319 | { | |
8301ea44 PMD |
320 | CPUClass *cc; |
321 | ||
322 | if (!cpu_model) { | |
323 | return NULL; | |
324 | } | |
325 | cc = CPU_CLASS(object_class_by_name(typename)); | |
2b8c2754 AF |
326 | |
327 | return cc->class_by_name(cpu_model); | |
328 | } | |
329 | ||
330 | static ObjectClass *cpu_common_class_by_name(const char *cpu_model) | |
331 | { | |
332 | return NULL; | |
333 | } | |
334 | ||
62a48a2a | 335 | static void cpu_common_parse_features(const char *typename, char *features, |
1590bbcb AF |
336 | Error **errp) |
337 | { | |
338 | char *featurestr; /* Single "key=value" string being parsed */ | |
339 | char *val; | |
62a48a2a IM |
340 | static bool cpu_globals_initialized; |
341 | ||
342 | /* TODO: all callers of ->parse_features() need to be changed to | |
343 | * call it only once, so we can remove this check (or change it | |
344 | * to assert(!cpu_globals_initialized). | |
345 | * Current callers of ->parse_features() are: | |
62a48a2a | 346 | * - cpu_generic_init() |
62a48a2a IM |
347 | */ |
348 | if (cpu_globals_initialized) { | |
349 | return; | |
350 | } | |
351 | cpu_globals_initialized = true; | |
1590bbcb AF |
352 | |
353 | featurestr = features ? strtok(features, ",") : NULL; | |
354 | ||
355 | while (featurestr) { | |
356 | val = strchr(featurestr, '='); | |
357 | if (val) { | |
62a48a2a | 358 | GlobalProperty *prop = g_new0(typeof(*prop), 1); |
1590bbcb AF |
359 | *val = 0; |
360 | val++; | |
62a48a2a IM |
361 | prop->driver = typename; |
362 | prop->property = g_strdup(featurestr); | |
363 | prop->value = g_strdup(val); | |
364 | prop->errp = &error_fatal; | |
365 | qdev_prop_register_global(prop); | |
1590bbcb AF |
366 | } else { |
367 | error_setg(errp, "Expected key=value format, found %s.", | |
368 | featurestr); | |
369 | return; | |
370 | } | |
371 | featurestr = strtok(NULL, ","); | |
372 | } | |
373 | } | |
374 | ||
4f658099 AF |
375 | static void cpu_common_realizefn(DeviceState *dev, Error **errp) |
376 | { | |
13eed94e | 377 | CPUState *cpu = CPU(dev); |
ed860129 PM |
378 | Object *machine = qdev_get_machine(); |
379 | ||
380 | /* qdev_get_machine() can return something that's not TYPE_MACHINE | |
381 | * if this is one of the user-only emulators; in that case there's | |
382 | * no need to check the ignore_memory_transaction_failures board flag. | |
383 | */ | |
384 | if (object_dynamic_cast(machine, TYPE_MACHINE)) { | |
385 | ObjectClass *oc = object_get_class(machine); | |
386 | MachineClass *mc = MACHINE_CLASS(oc); | |
387 | ||
388 | if (mc) { | |
389 | cpu->ignore_memory_transaction_failures = | |
390 | mc->ignore_memory_transaction_failures; | |
391 | } | |
392 | } | |
13eed94e IM |
393 | |
394 | if (dev->hotplugged) { | |
395 | cpu_synchronize_post_init(cpu); | |
6afb4721 | 396 | cpu_resume(cpu); |
13eed94e | 397 | } |
2bfe11c8 LV |
398 | |
399 | /* NOTE: latest generic point where the cpu is fully realized */ | |
400 | trace_init_vcpu(cpu); | |
4f658099 AF |
401 | } |
402 | ||
7bbc124e LV |
403 | static void cpu_common_unrealizefn(DeviceState *dev, Error **errp) |
404 | { | |
405 | CPUState *cpu = CPU(dev); | |
82e95ec8 LV |
406 | /* NOTE: latest generic point before the cpu is fully unrealized */ |
407 | trace_fini_vcpu(cpu); | |
7bbc124e LV |
408 | cpu_exec_unrealizefn(cpu); |
409 | } | |
410 | ||
a0e372f0 AF |
411 | static void cpu_common_initfn(Object *obj) |
412 | { | |
413 | CPUState *cpu = CPU(obj); | |
414 | CPUClass *cc = CPU_GET_CLASS(obj); | |
415 | ||
a07f953e | 416 | cpu->cpu_index = UNASSIGNED_CPU_INDEX; |
35143f01 | 417 | cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs; |
fa5376dd MAL |
418 | /* *-user doesn't have configurable SMP topology */ |
419 | /* the default value is changed by qemu_init_vcpu() for softmmu */ | |
420 | cpu->nr_cores = 1; | |
421 | cpu->nr_threads = 1; | |
422 | ||
376692b9 | 423 | qemu_mutex_init(&cpu->work_mutex); |
7c39163e EH |
424 | QTAILQ_INIT(&cpu->breakpoints); |
425 | QTAILQ_INIT(&cpu->watchpoints); | |
b7d48952 | 426 | |
39e329e3 | 427 | cpu_exec_initfn(cpu); |
a0e372f0 AF |
428 | } |
429 | ||
b7bca733 BR |
430 | static void cpu_common_finalize(Object *obj) |
431 | { | |
b7bca733 BR |
432 | } |
433 | ||
997395d3 IM |
434 | static int64_t cpu_common_get_arch_id(CPUState *cpu) |
435 | { | |
436 | return cpu->cpu_index; | |
437 | } | |
438 | ||
40612000 JB |
439 | static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len) |
440 | { | |
441 | return addr; | |
442 | } | |
443 | ||
290dae46 PB |
444 | static void generic_handle_interrupt(CPUState *cpu, int mask) |
445 | { | |
446 | cpu->interrupt_request |= mask; | |
447 | ||
448 | if (!qemu_cpu_is_self(cpu)) { | |
449 | qemu_cpu_kick(cpu); | |
450 | } | |
451 | } | |
452 | ||
453 | CPUInterruptHandler cpu_interrupt_handler = generic_handle_interrupt; | |
454 | ||
dd83b06a AF |
455 | static void cpu_class_init(ObjectClass *klass, void *data) |
456 | { | |
961f8395 | 457 | DeviceClass *dc = DEVICE_CLASS(klass); |
dd83b06a AF |
458 | CPUClass *k = CPU_CLASS(klass); |
459 | ||
2b8c2754 | 460 | k->class_by_name = cpu_common_class_by_name; |
1590bbcb | 461 | k->parse_features = cpu_common_parse_features; |
dd83b06a | 462 | k->reset = cpu_common_reset; |
997395d3 | 463 | k->get_arch_id = cpu_common_get_arch_id; |
8c2e1b00 | 464 | k->has_work = cpu_common_has_work; |
444d5590 | 465 | k->get_paging_enabled = cpu_common_get_paging_enabled; |
a23bbfda | 466 | k->get_memory_mapping = cpu_common_get_memory_mapping; |
c72bf468 JF |
467 | k->write_elf32_qemunote = cpu_common_write_elf32_qemunote; |
468 | k->write_elf32_note = cpu_common_write_elf32_note; | |
469 | k->write_elf64_qemunote = cpu_common_write_elf64_qemunote; | |
470 | k->write_elf64_note = cpu_common_write_elf64_note; | |
5b50e790 AF |
471 | k->gdb_read_register = cpu_common_gdb_read_register; |
472 | k->gdb_write_register = cpu_common_gdb_write_register; | |
bf7663c4 | 473 | k->virtio_is_big_endian = cpu_common_virtio_is_big_endian; |
cffe7b32 | 474 | k->debug_excp_handler = cpu_common_noop; |
568496c0 | 475 | k->debug_check_watchpoint = cpu_common_debug_check_watchpoint; |
cffe7b32 RH |
476 | k->cpu_exec_enter = cpu_common_noop; |
477 | k->cpu_exec_exit = cpu_common_noop; | |
9585db68 | 478 | k->cpu_exec_interrupt = cpu_common_exec_interrupt; |
40612000 | 479 | k->adjust_watchpoint_address = cpu_adjust_watchpoint_address; |
ba31cc72 | 480 | set_bit(DEVICE_CATEGORY_CPU, dc->categories); |
4f658099 | 481 | dc->realize = cpu_common_realizefn; |
7bbc124e | 482 | dc->unrealize = cpu_common_unrealizefn; |
c7e002c5 | 483 | dc->props = cpu_common_props; |
ffa95714 MA |
484 | /* |
485 | * Reason: CPUs still need special care by board code: wiring up | |
486 | * IRQs, adding reset handlers, halting non-first CPUs, ... | |
487 | */ | |
e90f2a8c | 488 | dc->user_creatable = false; |
dd83b06a AF |
489 | } |
490 | ||
961f8395 | 491 | static const TypeInfo cpu_type_info = { |
dd83b06a | 492 | .name = TYPE_CPU, |
961f8395 | 493 | .parent = TYPE_DEVICE, |
dd83b06a | 494 | .instance_size = sizeof(CPUState), |
a0e372f0 | 495 | .instance_init = cpu_common_initfn, |
b7bca733 | 496 | .instance_finalize = cpu_common_finalize, |
dd83b06a AF |
497 | .abstract = true, |
498 | .class_size = sizeof(CPUClass), | |
499 | .class_init = cpu_class_init, | |
500 | }; | |
501 | ||
502 | static void cpu_register_types(void) | |
503 | { | |
504 | type_register_static(&cpu_type_info); | |
505 | } | |
506 | ||
507 | type_init(cpu_register_types) |