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CommitLineData
dd83b06a
AF
1/*
2 * QEMU CPU model
3 *
1590bbcb 4 * Copyright (c) 2012-2014 SUSE LINUX Products GmbH
dd83b06a
AF
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
1ef26b1f 21#include "qemu/osdep.h"
da34e65c 22#include "qapi/error.h"
dd83b06a 23#include "qemu-common.h"
878096ee 24#include "qom/cpu.h"
b3946626 25#include "sysemu/hw_accel.h"
066e9b27 26#include "qemu/notify.h"
91b1df8c 27#include "qemu/log.h"
508127e2 28#include "exec/log.h"
9262685b 29#include "qemu/error-report.h"
066e9b27 30#include "sysemu/sysemu.h"
62a48a2a 31#include "hw/qdev-properties.h"
0ab8ed18 32#include "trace-root.h"
066e9b27 33
69e5ff06
IM
34bool cpu_exists(int64_t id)
35{
38fcbd3f
AF
36 CPUState *cpu;
37
38 CPU_FOREACH(cpu) {
39 CPUClass *cc = CPU_GET_CLASS(cpu);
69e5ff06 40
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AF
41 if (cc->get_arch_id(cpu) == id) {
42 return true;
43 }
44 }
45 return false;
69e5ff06
IM
46}
47
9262685b
AF
48CPUState *cpu_generic_init(const char *typename, const char *cpu_model)
49{
50 char *str, *name, *featurestr;
62a48a2a 51 CPUState *cpu = NULL;
9262685b
AF
52 ObjectClass *oc;
53 CPUClass *cc;
54 Error *err = NULL;
55
56 str = g_strdup(cpu_model);
57 name = strtok(str, ",");
58
59 oc = cpu_class_by_name(typename, name);
60 if (oc == NULL) {
61 g_free(str);
62 return NULL;
63 }
64
62a48a2a 65 cc = CPU_CLASS(oc);
9262685b 66 featurestr = strtok(NULL, ",");
62a48a2a
IM
67 /* TODO: all callers of cpu_generic_init() need to be converted to
68 * call parse_features() only once, before calling cpu_generic_init().
69 */
70 cc->parse_features(object_class_get_name(oc), featurestr, &err);
9262685b
AF
71 g_free(str);
72 if (err != NULL) {
73 goto out;
74 }
75
62a48a2a 76 cpu = CPU(object_new(object_class_get_name(oc)));
9262685b
AF
77 object_property_set_bool(OBJECT(cpu), true, "realized", &err);
78
79out:
80 if (err != NULL) {
565f65d2 81 error_report_err(err);
9262685b
AF
82 object_unref(OBJECT(cpu));
83 return NULL;
84 }
85
86 return cpu;
87}
88
444d5590
AF
89bool cpu_paging_enabled(const CPUState *cpu)
90{
91 CPUClass *cc = CPU_GET_CLASS(cpu);
92
93 return cc->get_paging_enabled(cpu);
94}
95
96static bool cpu_common_get_paging_enabled(const CPUState *cpu)
97{
6db297ea 98 return false;
444d5590
AF
99}
100
a23bbfda
AF
101void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
102 Error **errp)
103{
104 CPUClass *cc = CPU_GET_CLASS(cpu);
105
fbe95bfb 106 cc->get_memory_mapping(cpu, list, errp);
a23bbfda
AF
107}
108
109static void cpu_common_get_memory_mapping(CPUState *cpu,
110 MemoryMappingList *list,
111 Error **errp)
112{
113 error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
114}
115
8d04fb55
JK
116/* Resetting the IRQ comes from across the code base so we take the
117 * BQL here if we need to. cpu_interrupt assumes it is held.*/
d8ed887b
AF
118void cpu_reset_interrupt(CPUState *cpu, int mask)
119{
8d04fb55
JK
120 bool need_lock = !qemu_mutex_iothread_locked();
121
122 if (need_lock) {
123 qemu_mutex_lock_iothread();
124 }
d8ed887b 125 cpu->interrupt_request &= ~mask;
8d04fb55
JK
126 if (need_lock) {
127 qemu_mutex_unlock_iothread();
128 }
d8ed887b
AF
129}
130
60a3e17a
AF
131void cpu_exit(CPUState *cpu)
132{
027d9a7d 133 atomic_set(&cpu->exit_request, 1);
ab096a75
PB
134 /* Ensure cpu_exec will see the exit request after TCG has exited. */
135 smp_wmb();
1aab16c2 136 atomic_set(&cpu->icount_decr.u16.high, -1);
60a3e17a
AF
137}
138
c72bf468
JF
139int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
140 void *opaque)
141{
142 CPUClass *cc = CPU_GET_CLASS(cpu);
143
144 return (*cc->write_elf32_qemunote)(f, cpu, opaque);
145}
146
147static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f,
148 CPUState *cpu, void *opaque)
149{
b09afd58 150 return 0;
c72bf468
JF
151}
152
153int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
154 int cpuid, void *opaque)
155{
156 CPUClass *cc = CPU_GET_CLASS(cpu);
157
158 return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
159}
160
161static int cpu_common_write_elf32_note(WriteCoreDumpFunction f,
162 CPUState *cpu, int cpuid,
163 void *opaque)
164{
165 return -1;
166}
167
168int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
169 void *opaque)
170{
171 CPUClass *cc = CPU_GET_CLASS(cpu);
172
173 return (*cc->write_elf64_qemunote)(f, cpu, opaque);
174}
175
176static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f,
177 CPUState *cpu, void *opaque)
178{
b09afd58 179 return 0;
c72bf468
JF
180}
181
182int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
183 int cpuid, void *opaque)
184{
185 CPUClass *cc = CPU_GET_CLASS(cpu);
186
187 return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
188}
189
190static int cpu_common_write_elf64_note(WriteCoreDumpFunction f,
191 CPUState *cpu, int cpuid,
192 void *opaque)
193{
194 return -1;
195}
196
197
5b50e790
AF
198static int cpu_common_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg)
199{
200 return 0;
201}
202
203static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
204{
205 return 0;
206}
207
568496c0
SF
208static bool cpu_common_debug_check_watchpoint(CPUState *cpu, CPUWatchpoint *wp)
209{
210 /* If no extra check is required, QEMU watchpoint match can be considered
211 * as an architectural match.
212 */
213 return true;
214}
215
bf7663c4
GK
216bool target_words_bigendian(void);
217static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
218{
219 return target_words_bigendian();
220}
5b50e790 221
cffe7b32 222static void cpu_common_noop(CPUState *cpu)
86025ee4
PM
223{
224}
225
9585db68
RH
226static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req)
227{
228 return false;
229}
230
c86f106b
AN
231GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
232{
233 CPUClass *cc = CPU_GET_CLASS(cpu);
234 GuestPanicInformation *res = NULL;
235
236 if (cc->get_crash_info) {
237 res = cc->get_crash_info(cpu);
238 }
239 return res;
240}
241
878096ee
AF
242void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
243 int flags)
244{
245 CPUClass *cc = CPU_GET_CLASS(cpu);
246
247 if (cc->dump_state) {
97577fd4 248 cpu_synchronize_state(cpu);
878096ee
AF
249 cc->dump_state(cpu, f, cpu_fprintf, flags);
250 }
251}
252
253void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
254 int flags)
255{
256 CPUClass *cc = CPU_GET_CLASS(cpu);
257
258 if (cc->dump_statistics) {
259 cc->dump_statistics(cpu, f, cpu_fprintf, flags);
260 }
261}
262
dd83b06a
AF
263void cpu_reset(CPUState *cpu)
264{
265 CPUClass *klass = CPU_GET_CLASS(cpu);
266
267 if (klass->reset != NULL) {
268 (*klass->reset)(cpu);
269 }
2cc2d082
LV
270
271 trace_guest_cpu_reset(cpu);
dd83b06a
AF
272}
273
274static void cpu_common_reset(CPUState *cpu)
275{
91b1df8c 276 CPUClass *cc = CPU_GET_CLASS(cpu);
ce7cf6a9 277 int i;
91b1df8c
AF
278
279 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
280 qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index);
281 log_cpu_state(cpu, cc->reset_dump_flags);
282 }
283
259186a7 284 cpu->interrupt_request = 0;
259186a7 285 cpu->halted = 0;
93afeade
AF
286 cpu->mem_io_pc = 0;
287 cpu->mem_io_vaddr = 0;
efee7340 288 cpu->icount_extra = 0;
28ecfd7a 289 cpu->icount_decr.u32 = 0;
414b15c9 290 cpu->can_do_io = 1;
f9d8f667 291 cpu->exception_index = -1;
bac05aa9 292 cpu->crash_occurred = false;
ce7cf6a9 293
ba7d3d18
AB
294 if (tcg_enabled()) {
295 for (i = 0; i < TB_JMP_CACHE_SIZE; ++i) {
296 atomic_set(&cpu->tb_jmp_cache[i], NULL);
297 }
1f5c00cf
AB
298
299#ifdef CONFIG_SOFTMMU
ba7d3d18 300 tlb_flush(cpu, 0);
1f5c00cf 301#endif
ba7d3d18 302 }
dd83b06a
AF
303}
304
8c2e1b00
AF
305static bool cpu_common_has_work(CPUState *cs)
306{
307 return false;
308}
309
2b8c2754
AF
310ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
311{
312 CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
313
314 return cc->class_by_name(cpu_model);
315}
316
317static ObjectClass *cpu_common_class_by_name(const char *cpu_model)
318{
319 return NULL;
320}
321
62a48a2a 322static void cpu_common_parse_features(const char *typename, char *features,
1590bbcb
AF
323 Error **errp)
324{
325 char *featurestr; /* Single "key=value" string being parsed */
326 char *val;
62a48a2a
IM
327 static bool cpu_globals_initialized;
328
329 /* TODO: all callers of ->parse_features() need to be changed to
330 * call it only once, so we can remove this check (or change it
331 * to assert(!cpu_globals_initialized).
332 * Current callers of ->parse_features() are:
62a48a2a 333 * - cpu_generic_init()
62a48a2a
IM
334 */
335 if (cpu_globals_initialized) {
336 return;
337 }
338 cpu_globals_initialized = true;
1590bbcb
AF
339
340 featurestr = features ? strtok(features, ",") : NULL;
341
342 while (featurestr) {
343 val = strchr(featurestr, '=');
344 if (val) {
62a48a2a 345 GlobalProperty *prop = g_new0(typeof(*prop), 1);
1590bbcb
AF
346 *val = 0;
347 val++;
62a48a2a
IM
348 prop->driver = typename;
349 prop->property = g_strdup(featurestr);
350 prop->value = g_strdup(val);
351 prop->errp = &error_fatal;
352 qdev_prop_register_global(prop);
1590bbcb
AF
353 } else {
354 error_setg(errp, "Expected key=value format, found %s.",
355 featurestr);
356 return;
357 }
358 featurestr = strtok(NULL, ",");
359 }
360}
361
4f658099
AF
362static void cpu_common_realizefn(DeviceState *dev, Error **errp)
363{
13eed94e
IM
364 CPUState *cpu = CPU(dev);
365
366 if (dev->hotplugged) {
367 cpu_synchronize_post_init(cpu);
6afb4721 368 cpu_resume(cpu);
13eed94e 369 }
2bfe11c8
LV
370
371 /* NOTE: latest generic point where the cpu is fully realized */
372 trace_init_vcpu(cpu);
4f658099
AF
373}
374
7bbc124e
LV
375static void cpu_common_unrealizefn(DeviceState *dev, Error **errp)
376{
377 CPUState *cpu = CPU(dev);
82e95ec8
LV
378 /* NOTE: latest generic point before the cpu is fully unrealized */
379 trace_fini_vcpu(cpu);
7bbc124e
LV
380 cpu_exec_unrealizefn(cpu);
381}
382
a0e372f0
AF
383static void cpu_common_initfn(Object *obj)
384{
385 CPUState *cpu = CPU(obj);
386 CPUClass *cc = CPU_GET_CLASS(obj);
387
a07f953e 388 cpu->cpu_index = UNASSIGNED_CPU_INDEX;
35143f01 389 cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
fa5376dd
MAL
390 /* *-user doesn't have configurable SMP topology */
391 /* the default value is changed by qemu_init_vcpu() for softmmu */
392 cpu->nr_cores = 1;
393 cpu->nr_threads = 1;
394
376692b9 395 qemu_mutex_init(&cpu->work_mutex);
7c39163e
EH
396 QTAILQ_INIT(&cpu->breakpoints);
397 QTAILQ_INIT(&cpu->watchpoints);
b7d48952
DB
398
399 cpu->trace_dstate = bitmap_new(trace_get_vcpu_event_count());
39e329e3
LV
400
401 cpu_exec_initfn(cpu);
a0e372f0
AF
402}
403
b7bca733
BR
404static void cpu_common_finalize(Object *obj)
405{
b7d48952 406 CPUState *cpu = CPU(obj);
b7d48952 407 g_free(cpu->trace_dstate);
b7bca733
BR
408}
409
997395d3
IM
410static int64_t cpu_common_get_arch_id(CPUState *cpu)
411{
412 return cpu->cpu_index;
413}
414
40612000
JB
415static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len)
416{
417 return addr;
418}
419
dd83b06a
AF
420static void cpu_class_init(ObjectClass *klass, void *data)
421{
961f8395 422 DeviceClass *dc = DEVICE_CLASS(klass);
dd83b06a
AF
423 CPUClass *k = CPU_CLASS(klass);
424
2b8c2754 425 k->class_by_name = cpu_common_class_by_name;
1590bbcb 426 k->parse_features = cpu_common_parse_features;
dd83b06a 427 k->reset = cpu_common_reset;
997395d3 428 k->get_arch_id = cpu_common_get_arch_id;
8c2e1b00 429 k->has_work = cpu_common_has_work;
444d5590 430 k->get_paging_enabled = cpu_common_get_paging_enabled;
a23bbfda 431 k->get_memory_mapping = cpu_common_get_memory_mapping;
c72bf468
JF
432 k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
433 k->write_elf32_note = cpu_common_write_elf32_note;
434 k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
435 k->write_elf64_note = cpu_common_write_elf64_note;
5b50e790
AF
436 k->gdb_read_register = cpu_common_gdb_read_register;
437 k->gdb_write_register = cpu_common_gdb_write_register;
bf7663c4 438 k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
cffe7b32 439 k->debug_excp_handler = cpu_common_noop;
568496c0 440 k->debug_check_watchpoint = cpu_common_debug_check_watchpoint;
cffe7b32
RH
441 k->cpu_exec_enter = cpu_common_noop;
442 k->cpu_exec_exit = cpu_common_noop;
9585db68 443 k->cpu_exec_interrupt = cpu_common_exec_interrupt;
40612000 444 k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;
ba31cc72 445 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
4f658099 446 dc->realize = cpu_common_realizefn;
7bbc124e 447 dc->unrealize = cpu_common_unrealizefn;
ffa95714
MA
448 /*
449 * Reason: CPUs still need special care by board code: wiring up
450 * IRQs, adding reset handlers, halting non-first CPUs, ...
451 */
452 dc->cannot_instantiate_with_device_add_yet = true;
dd83b06a
AF
453}
454
961f8395 455static const TypeInfo cpu_type_info = {
dd83b06a 456 .name = TYPE_CPU,
961f8395 457 .parent = TYPE_DEVICE,
dd83b06a 458 .instance_size = sizeof(CPUState),
a0e372f0 459 .instance_init = cpu_common_initfn,
b7bca733 460 .instance_finalize = cpu_common_finalize,
dd83b06a
AF
461 .abstract = true,
462 .class_size = sizeof(CPUClass),
463 .class_init = cpu_class_init,
464};
465
466static void cpu_register_types(void)
467{
468 type_register_static(&cpu_type_info);
469}
470
471type_init(cpu_register_types)