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CommitLineData
dd83b06a
AF
1/*
2 * QEMU CPU model
3 *
1590bbcb 4 * Copyright (c) 2012-2014 SUSE LINUX Products GmbH
dd83b06a
AF
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
1ef26b1f 21#include "qemu/osdep.h"
da34e65c 22#include "qapi/error.h"
dd83b06a 23#include "qemu-common.h"
878096ee 24#include "qom/cpu.h"
b3946626 25#include "sysemu/hw_accel.h"
066e9b27 26#include "qemu/notify.h"
91b1df8c 27#include "qemu/log.h"
508127e2 28#include "exec/log.h"
2cd53943 29#include "exec/cpu-common.h"
9262685b 30#include "qemu/error-report.h"
066e9b27 31#include "sysemu/sysemu.h"
62a48a2a 32#include "hw/qdev-properties.h"
0ab8ed18 33#include "trace-root.h"
066e9b27 34
290dae46
PB
35CPUInterruptHandler cpu_interrupt_handler;
36
69e5ff06
IM
37bool cpu_exists(int64_t id)
38{
38fcbd3f
AF
39 CPUState *cpu;
40
41 CPU_FOREACH(cpu) {
42 CPUClass *cc = CPU_GET_CLASS(cpu);
69e5ff06 43
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AF
44 if (cc->get_arch_id(cpu) == id) {
45 return true;
46 }
47 }
48 return false;
69e5ff06
IM
49}
50
9262685b
AF
51CPUState *cpu_generic_init(const char *typename, const char *cpu_model)
52{
53 char *str, *name, *featurestr;
62a48a2a 54 CPUState *cpu = NULL;
9262685b
AF
55 ObjectClass *oc;
56 CPUClass *cc;
57 Error *err = NULL;
58
59 str = g_strdup(cpu_model);
60 name = strtok(str, ",");
61
62 oc = cpu_class_by_name(typename, name);
63 if (oc == NULL) {
64 g_free(str);
65 return NULL;
66 }
67
62a48a2a 68 cc = CPU_CLASS(oc);
9262685b 69 featurestr = strtok(NULL, ",");
62a48a2a
IM
70 /* TODO: all callers of cpu_generic_init() need to be converted to
71 * call parse_features() only once, before calling cpu_generic_init().
72 */
73 cc->parse_features(object_class_get_name(oc), featurestr, &err);
9262685b
AF
74 g_free(str);
75 if (err != NULL) {
76 goto out;
77 }
78
62a48a2a 79 cpu = CPU(object_new(object_class_get_name(oc)));
9262685b
AF
80 object_property_set_bool(OBJECT(cpu), true, "realized", &err);
81
82out:
83 if (err != NULL) {
565f65d2 84 error_report_err(err);
9262685b
AF
85 object_unref(OBJECT(cpu));
86 return NULL;
87 }
88
89 return cpu;
90}
91
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AF
92bool cpu_paging_enabled(const CPUState *cpu)
93{
94 CPUClass *cc = CPU_GET_CLASS(cpu);
95
96 return cc->get_paging_enabled(cpu);
97}
98
99static bool cpu_common_get_paging_enabled(const CPUState *cpu)
100{
6db297ea 101 return false;
444d5590
AF
102}
103
a23bbfda
AF
104void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
105 Error **errp)
106{
107 CPUClass *cc = CPU_GET_CLASS(cpu);
108
fbe95bfb 109 cc->get_memory_mapping(cpu, list, errp);
a23bbfda
AF
110}
111
112static void cpu_common_get_memory_mapping(CPUState *cpu,
113 MemoryMappingList *list,
114 Error **errp)
115{
116 error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
117}
118
8d04fb55
JK
119/* Resetting the IRQ comes from across the code base so we take the
120 * BQL here if we need to. cpu_interrupt assumes it is held.*/
d8ed887b
AF
121void cpu_reset_interrupt(CPUState *cpu, int mask)
122{
8d04fb55
JK
123 bool need_lock = !qemu_mutex_iothread_locked();
124
125 if (need_lock) {
126 qemu_mutex_lock_iothread();
127 }
d8ed887b 128 cpu->interrupt_request &= ~mask;
8d04fb55
JK
129 if (need_lock) {
130 qemu_mutex_unlock_iothread();
131 }
d8ed887b
AF
132}
133
60a3e17a
AF
134void cpu_exit(CPUState *cpu)
135{
027d9a7d 136 atomic_set(&cpu->exit_request, 1);
ab096a75
PB
137 /* Ensure cpu_exec will see the exit request after TCG has exited. */
138 smp_wmb();
1aab16c2 139 atomic_set(&cpu->icount_decr.u16.high, -1);
60a3e17a
AF
140}
141
c72bf468
JF
142int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
143 void *opaque)
144{
145 CPUClass *cc = CPU_GET_CLASS(cpu);
146
147 return (*cc->write_elf32_qemunote)(f, cpu, opaque);
148}
149
150static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f,
151 CPUState *cpu, void *opaque)
152{
b09afd58 153 return 0;
c72bf468
JF
154}
155
156int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
157 int cpuid, void *opaque)
158{
159 CPUClass *cc = CPU_GET_CLASS(cpu);
160
161 return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
162}
163
164static int cpu_common_write_elf32_note(WriteCoreDumpFunction f,
165 CPUState *cpu, int cpuid,
166 void *opaque)
167{
168 return -1;
169}
170
171int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
172 void *opaque)
173{
174 CPUClass *cc = CPU_GET_CLASS(cpu);
175
176 return (*cc->write_elf64_qemunote)(f, cpu, opaque);
177}
178
179static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f,
180 CPUState *cpu, void *opaque)
181{
b09afd58 182 return 0;
c72bf468
JF
183}
184
185int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
186 int cpuid, void *opaque)
187{
188 CPUClass *cc = CPU_GET_CLASS(cpu);
189
190 return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
191}
192
193static int cpu_common_write_elf64_note(WriteCoreDumpFunction f,
194 CPUState *cpu, int cpuid,
195 void *opaque)
196{
197 return -1;
198}
199
200
5b50e790
AF
201static int cpu_common_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg)
202{
203 return 0;
204}
205
206static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
207{
208 return 0;
209}
210
568496c0
SF
211static bool cpu_common_debug_check_watchpoint(CPUState *cpu, CPUWatchpoint *wp)
212{
213 /* If no extra check is required, QEMU watchpoint match can be considered
214 * as an architectural match.
215 */
216 return true;
217}
218
bf7663c4
GK
219bool target_words_bigendian(void);
220static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
221{
222 return target_words_bigendian();
223}
5b50e790 224
cffe7b32 225static void cpu_common_noop(CPUState *cpu)
86025ee4
PM
226{
227}
228
9585db68
RH
229static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req)
230{
231 return false;
232}
233
c86f106b
AN
234GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
235{
236 CPUClass *cc = CPU_GET_CLASS(cpu);
237 GuestPanicInformation *res = NULL;
238
239 if (cc->get_crash_info) {
240 res = cc->get_crash_info(cpu);
241 }
242 return res;
243}
244
878096ee
AF
245void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
246 int flags)
247{
248 CPUClass *cc = CPU_GET_CLASS(cpu);
249
250 if (cc->dump_state) {
97577fd4 251 cpu_synchronize_state(cpu);
878096ee
AF
252 cc->dump_state(cpu, f, cpu_fprintf, flags);
253 }
254}
255
256void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
257 int flags)
258{
259 CPUClass *cc = CPU_GET_CLASS(cpu);
260
261 if (cc->dump_statistics) {
262 cc->dump_statistics(cpu, f, cpu_fprintf, flags);
263 }
264}
265
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AF
266void cpu_reset(CPUState *cpu)
267{
268 CPUClass *klass = CPU_GET_CLASS(cpu);
269
270 if (klass->reset != NULL) {
271 (*klass->reset)(cpu);
272 }
2cc2d082
LV
273
274 trace_guest_cpu_reset(cpu);
dd83b06a
AF
275}
276
277static void cpu_common_reset(CPUState *cpu)
278{
91b1df8c
AF
279 CPUClass *cc = CPU_GET_CLASS(cpu);
280
281 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
282 qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index);
283 log_cpu_state(cpu, cc->reset_dump_flags);
284 }
285
259186a7 286 cpu->interrupt_request = 0;
259186a7 287 cpu->halted = 0;
93afeade
AF
288 cpu->mem_io_pc = 0;
289 cpu->mem_io_vaddr = 0;
efee7340 290 cpu->icount_extra = 0;
28ecfd7a 291 cpu->icount_decr.u32 = 0;
414b15c9 292 cpu->can_do_io = 1;
f9d8f667 293 cpu->exception_index = -1;
bac05aa9 294 cpu->crash_occurred = false;
ce7cf6a9 295
ba7d3d18 296 if (tcg_enabled()) {
f3ced3c5 297 cpu_tb_jmp_cache_clear(cpu);
1f5c00cf 298
2cd53943 299 tcg_flush_softmmu_tlb(cpu);
ba7d3d18 300 }
dd83b06a
AF
301}
302
8c2e1b00
AF
303static bool cpu_common_has_work(CPUState *cs)
304{
305 return false;
306}
307
2b8c2754
AF
308ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
309{
310 CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
311
312 return cc->class_by_name(cpu_model);
313}
314
315static ObjectClass *cpu_common_class_by_name(const char *cpu_model)
316{
317 return NULL;
318}
319
62a48a2a 320static void cpu_common_parse_features(const char *typename, char *features,
1590bbcb
AF
321 Error **errp)
322{
323 char *featurestr; /* Single "key=value" string being parsed */
324 char *val;
62a48a2a
IM
325 static bool cpu_globals_initialized;
326
327 /* TODO: all callers of ->parse_features() need to be changed to
328 * call it only once, so we can remove this check (or change it
329 * to assert(!cpu_globals_initialized).
330 * Current callers of ->parse_features() are:
62a48a2a 331 * - cpu_generic_init()
62a48a2a
IM
332 */
333 if (cpu_globals_initialized) {
334 return;
335 }
336 cpu_globals_initialized = true;
1590bbcb
AF
337
338 featurestr = features ? strtok(features, ",") : NULL;
339
340 while (featurestr) {
341 val = strchr(featurestr, '=');
342 if (val) {
62a48a2a 343 GlobalProperty *prop = g_new0(typeof(*prop), 1);
1590bbcb
AF
344 *val = 0;
345 val++;
62a48a2a
IM
346 prop->driver = typename;
347 prop->property = g_strdup(featurestr);
348 prop->value = g_strdup(val);
349 prop->errp = &error_fatal;
350 qdev_prop_register_global(prop);
1590bbcb
AF
351 } else {
352 error_setg(errp, "Expected key=value format, found %s.",
353 featurestr);
354 return;
355 }
356 featurestr = strtok(NULL, ",");
357 }
358}
359
4f658099
AF
360static void cpu_common_realizefn(DeviceState *dev, Error **errp)
361{
13eed94e
IM
362 CPUState *cpu = CPU(dev);
363
364 if (dev->hotplugged) {
365 cpu_synchronize_post_init(cpu);
6afb4721 366 cpu_resume(cpu);
13eed94e 367 }
2bfe11c8
LV
368
369 /* NOTE: latest generic point where the cpu is fully realized */
370 trace_init_vcpu(cpu);
4f658099
AF
371}
372
7bbc124e
LV
373static void cpu_common_unrealizefn(DeviceState *dev, Error **errp)
374{
375 CPUState *cpu = CPU(dev);
82e95ec8
LV
376 /* NOTE: latest generic point before the cpu is fully unrealized */
377 trace_fini_vcpu(cpu);
7bbc124e
LV
378 cpu_exec_unrealizefn(cpu);
379}
380
a0e372f0
AF
381static void cpu_common_initfn(Object *obj)
382{
383 CPUState *cpu = CPU(obj);
384 CPUClass *cc = CPU_GET_CLASS(obj);
385
a07f953e 386 cpu->cpu_index = UNASSIGNED_CPU_INDEX;
35143f01 387 cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
fa5376dd
MAL
388 /* *-user doesn't have configurable SMP topology */
389 /* the default value is changed by qemu_init_vcpu() for softmmu */
390 cpu->nr_cores = 1;
391 cpu->nr_threads = 1;
392
376692b9 393 qemu_mutex_init(&cpu->work_mutex);
7c39163e
EH
394 QTAILQ_INIT(&cpu->breakpoints);
395 QTAILQ_INIT(&cpu->watchpoints);
b7d48952 396
39e329e3 397 cpu_exec_initfn(cpu);
a0e372f0
AF
398}
399
b7bca733
BR
400static void cpu_common_finalize(Object *obj)
401{
b7bca733
BR
402}
403
997395d3
IM
404static int64_t cpu_common_get_arch_id(CPUState *cpu)
405{
406 return cpu->cpu_index;
407}
408
40612000
JB
409static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len)
410{
411 return addr;
412}
413
290dae46
PB
414static void generic_handle_interrupt(CPUState *cpu, int mask)
415{
416 cpu->interrupt_request |= mask;
417
418 if (!qemu_cpu_is_self(cpu)) {
419 qemu_cpu_kick(cpu);
420 }
421}
422
423CPUInterruptHandler cpu_interrupt_handler = generic_handle_interrupt;
424
dd83b06a
AF
425static void cpu_class_init(ObjectClass *klass, void *data)
426{
961f8395 427 DeviceClass *dc = DEVICE_CLASS(klass);
dd83b06a
AF
428 CPUClass *k = CPU_CLASS(klass);
429
2b8c2754 430 k->class_by_name = cpu_common_class_by_name;
1590bbcb 431 k->parse_features = cpu_common_parse_features;
dd83b06a 432 k->reset = cpu_common_reset;
997395d3 433 k->get_arch_id = cpu_common_get_arch_id;
8c2e1b00 434 k->has_work = cpu_common_has_work;
444d5590 435 k->get_paging_enabled = cpu_common_get_paging_enabled;
a23bbfda 436 k->get_memory_mapping = cpu_common_get_memory_mapping;
c72bf468
JF
437 k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
438 k->write_elf32_note = cpu_common_write_elf32_note;
439 k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
440 k->write_elf64_note = cpu_common_write_elf64_note;
5b50e790
AF
441 k->gdb_read_register = cpu_common_gdb_read_register;
442 k->gdb_write_register = cpu_common_gdb_write_register;
bf7663c4 443 k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
cffe7b32 444 k->debug_excp_handler = cpu_common_noop;
568496c0 445 k->debug_check_watchpoint = cpu_common_debug_check_watchpoint;
cffe7b32
RH
446 k->cpu_exec_enter = cpu_common_noop;
447 k->cpu_exec_exit = cpu_common_noop;
9585db68 448 k->cpu_exec_interrupt = cpu_common_exec_interrupt;
40612000 449 k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;
ba31cc72 450 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
4f658099 451 dc->realize = cpu_common_realizefn;
7bbc124e 452 dc->unrealize = cpu_common_unrealizefn;
c7e002c5 453 dc->props = cpu_common_props;
ffa95714
MA
454 /*
455 * Reason: CPUs still need special care by board code: wiring up
456 * IRQs, adding reset handlers, halting non-first CPUs, ...
457 */
e90f2a8c 458 dc->user_creatable = false;
dd83b06a
AF
459}
460
961f8395 461static const TypeInfo cpu_type_info = {
dd83b06a 462 .name = TYPE_CPU,
961f8395 463 .parent = TYPE_DEVICE,
dd83b06a 464 .instance_size = sizeof(CPUState),
a0e372f0 465 .instance_init = cpu_common_initfn,
b7bca733 466 .instance_finalize = cpu_common_finalize,
dd83b06a
AF
467 .abstract = true,
468 .class_size = sizeof(CPUClass),
469 .class_init = cpu_class_init,
470};
471
472static void cpu_register_types(void)
473{
474 type_register_static(&cpu_type_info);
475}
476
477type_init(cpu_register_types)