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c7f0f3b1
AL
1/*
2 * Test Server
3 *
4 * Copyright IBM, Corp. 2011
5 *
6 * Authors:
7 * Anthony Liguori <aliguori@us.ibm.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
11 *
12 */
13
d38ea87a 14#include "qemu/osdep.h"
da34e65c 15#include "qapi/error.h"
33c11879
PB
16#include "qemu-common.h"
17#include "cpu.h"
9c17d615 18#include "sysemu/qtest.h"
20288345 19#include "hw/qdev.h"
dccfcd0e 20#include "sysemu/char.h"
022c62cb
PB
21#include "exec/ioport.h"
22#include "exec/memory.h"
c7f0f3b1 23#include "hw/irq.h"
3a6ce514 24#include "sysemu/accel.h"
9c17d615
PB
25#include "sysemu/sysemu.h"
26#include "sysemu/cpus.h"
1ad9580b
ST
27#include "qemu/config-file.h"
28#include "qemu/option.h"
29#include "qemu/error-report.h"
c7f0f3b1
AL
30
31#define MAX_IRQ 256
32
d5286af5 33bool qtest_allowed;
c7f0f3b1 34
20288345 35static DeviceState *irq_intercept_dev;
c7f0f3b1
AL
36static FILE *qtest_log_fp;
37static CharDriverState *qtest_chr;
38static GString *inbuf;
39static int irq_levels[MAX_IRQ];
6e92466a 40static qemu_timeval start_time;
c7f0f3b1
AL
41static bool qtest_opened;
42
6b7cff76 43#define FMT_timeval "%ld.%06ld"
c7f0f3b1
AL
44
45/**
46 * QTest Protocol
47 *
48 * Line based protocol, request/response based. Server can send async messages
49 * so clients should always handle many async messages before the response
50 * comes in.
51 *
52 * Valid requests
53 *
8156be56
PB
54 * Clock management:
55 *
bc72ad67 56 * The qtest client is completely in charge of the QEMU_CLOCK_VIRTUAL. qtest commands
8156be56
PB
57 * let you adjust the value of the clock (monotonically). All the commands
58 * return the current value of the clock in nanoseconds.
59 *
60 * > clock_step
61 * < OK VALUE
62 *
63 * Advance the clock to the next deadline. Useful when waiting for
64 * asynchronous events.
65 *
66 * > clock_step NS
67 * < OK VALUE
68 *
69 * Advance the clock by NS nanoseconds.
70 *
71 * > clock_set NS
72 * < OK VALUE
73 *
74 * Advance the clock to NS nanoseconds (do nothing if it's already past).
75 *
76 * PIO and memory access:
77 *
c7f0f3b1
AL
78 * > outb ADDR VALUE
79 * < OK
80 *
81 * > outw ADDR VALUE
82 * < OK
83 *
84 * > outl ADDR VALUE
85 * < OK
86 *
87 * > inb ADDR
88 * < OK VALUE
89 *
90 * > inw ADDR
91 * < OK VALUE
92 *
93 * > inl ADDR
94 * < OK VALUE
95 *
872536bf
AF
96 * > writeb ADDR VALUE
97 * < OK
98 *
99 * > writew ADDR VALUE
100 * < OK
101 *
102 * > writel ADDR VALUE
103 * < OK
104 *
105 * > writeq ADDR VALUE
106 * < OK
107 *
108 * > readb ADDR
109 * < OK VALUE
110 *
111 * > readw ADDR
112 * < OK VALUE
113 *
114 * > readl ADDR
115 * < OK VALUE
116 *
117 * > readq ADDR
118 * < OK VALUE
119 *
c7f0f3b1
AL
120 * > read ADDR SIZE
121 * < OK DATA
122 *
123 * > write ADDR SIZE DATA
124 * < OK
125 *
7a6a740d
JS
126 * > b64read ADDR SIZE
127 * < OK B64_DATA
128 *
129 * > b64write ADDR SIZE B64_DATA
130 * < OK
131 *
4d007963
JS
132 * > memset ADDR SIZE VALUE
133 * < OK
134 *
c7f0f3b1 135 * ADDR, SIZE, VALUE are all integers parsed with strtoul() with a base of 0.
5f31bbf1 136 * For 'memset' a zero size is permitted and does nothing.
c7f0f3b1
AL
137 *
138 * DATA is an arbitrarily long hex number prefixed with '0x'. If it's smaller
139 * than the expected size, the value will be zero filled at the end of the data
140 * sequence.
141 *
7a6a740d
JS
142 * B64_DATA is an arbitrarily long base64 encoded string.
143 * If the sizes do not match, the data will be truncated.
144 *
20288345
PB
145 * IRQ management:
146 *
147 * > irq_intercept_in QOM-PATH
148 * < OK
149 *
150 * > irq_intercept_out QOM-PATH
151 * < OK
152 *
153 * Attach to the gpio-in (resp. gpio-out) pins exported by the device at
154 * QOM-PATH. When the pin is triggered, one of the following async messages
155 * will be printed to the qtest stream:
156 *
157 * IRQ raise NUM
158 * IRQ lower NUM
159 *
160 * where NUM is an IRQ number. For the PC, interrupts can be intercepted
161 * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
162 * NUM=0 even though it is remapped to GSI 2).
c7f0f3b1
AL
163 */
164
165static int hex2nib(char ch)
166{
167 if (ch >= '0' && ch <= '9') {
168 return ch - '0';
169 } else if (ch >= 'a' && ch <= 'f') {
170 return 10 + (ch - 'a');
171 } else if (ch >= 'A' && ch <= 'F') {
2a802aaf 172 return 10 + (ch - 'A');
c7f0f3b1
AL
173 } else {
174 return -1;
175 }
176}
177
6e92466a 178static void qtest_get_time(qemu_timeval *tv)
c7f0f3b1 179{
6e92466a 180 qemu_gettimeofday(tv);
c7f0f3b1
AL
181 tv->tv_sec -= start_time.tv_sec;
182 tv->tv_usec -= start_time.tv_usec;
183 if (tv->tv_usec < 0) {
184 tv->tv_usec += 1000000;
185 tv->tv_sec -= 1;
186 }
187}
188
189static void qtest_send_prefix(CharDriverState *chr)
190{
6e92466a 191 qemu_timeval tv;
c7f0f3b1
AL
192
193 if (!qtest_log_fp || !qtest_opened) {
194 return;
195 }
196
197 qtest_get_time(&tv);
198 fprintf(qtest_log_fp, "[S +" FMT_timeval "] ",
35aa3fb3 199 (long) tv.tv_sec, (long) tv.tv_usec);
c7f0f3b1
AL
200}
201
7a6a740d
JS
202static void GCC_FMT_ATTR(1, 2) qtest_log_send(const char *fmt, ...)
203{
204 va_list ap;
205
206 if (!qtest_log_fp || !qtest_opened) {
207 return;
208 }
209
210 qtest_send_prefix(NULL);
211
212 va_start(ap, fmt);
213 vfprintf(qtest_log_fp, fmt, ap);
214 va_end(ap);
215}
216
332cc7e9
JS
217static void do_qtest_send(CharDriverState *chr, const char *str, size_t len)
218{
219 qemu_chr_fe_write_all(chr, (uint8_t *)str, len);
220 if (qtest_log_fp && qtest_opened) {
221 fprintf(qtest_log_fp, "%s", str);
222 }
223}
224
225static void qtest_send(CharDriverState *chr, const char *str)
226{
227 do_qtest_send(chr, str, strlen(str));
228}
229
230static void GCC_FMT_ATTR(2, 3) qtest_sendf(CharDriverState *chr,
231 const char *fmt, ...)
c7f0f3b1
AL
232{
233 va_list ap;
332cc7e9 234 gchar *buffer;
c7f0f3b1
AL
235
236 va_start(ap, fmt);
332cc7e9
JS
237 buffer = g_strdup_vprintf(fmt, ap);
238 qtest_send(chr, buffer);
c7f0f3b1 239 va_end(ap);
c7f0f3b1
AL
240}
241
20288345
PB
242static void qtest_irq_handler(void *opaque, int n, int level)
243{
60a79016
PC
244 qemu_irq old_irq = *(qemu_irq *)opaque;
245 qemu_set_irq(old_irq, level);
20288345
PB
246
247 if (irq_levels[n] != level) {
248 CharDriverState *chr = qtest_chr;
249 irq_levels[n] = level;
250 qtest_send_prefix(chr);
332cc7e9
JS
251 qtest_sendf(chr, "IRQ %s %d\n",
252 level ? "raise" : "lower", n);
20288345
PB
253 }
254}
255
c7f0f3b1
AL
256static void qtest_process_command(CharDriverState *chr, gchar **words)
257{
258 const gchar *command;
259
260 g_assert(words);
261
262 command = words[0];
263
264 if (qtest_log_fp) {
6e92466a 265 qemu_timeval tv;
c7f0f3b1
AL
266 int i;
267
268 qtest_get_time(&tv);
269 fprintf(qtest_log_fp, "[R +" FMT_timeval "]",
35aa3fb3 270 (long) tv.tv_sec, (long) tv.tv_usec);
c7f0f3b1
AL
271 for (i = 0; words[i]; i++) {
272 fprintf(qtest_log_fp, " %s", words[i]);
273 }
274 fprintf(qtest_log_fp, "\n");
275 }
276
277 g_assert(command);
20288345
PB
278 if (strcmp(words[0], "irq_intercept_out") == 0
279 || strcmp(words[0], "irq_intercept_in") == 0) {
a5f54290
PC
280 DeviceState *dev;
281 NamedGPIOList *ngl;
20288345
PB
282
283 g_assert(words[1]);
284 dev = DEVICE(object_resolve_path(words[1], NULL));
285 if (!dev) {
286 qtest_send_prefix(chr);
287 qtest_send(chr, "FAIL Unknown device\n");
288 return;
289 }
290
291 if (irq_intercept_dev) {
292 qtest_send_prefix(chr);
293 if (irq_intercept_dev != dev) {
294 qtest_send(chr, "FAIL IRQ intercept already enabled\n");
295 } else {
296 qtest_send(chr, "OK\n");
297 }
298 return;
299 }
300
a5f54290
PC
301 QLIST_FOREACH(ngl, &dev->gpios, node) {
302 /* We don't support intercept of named GPIOs yet */
303 if (ngl->name) {
304 continue;
305 }
306 if (words[0][14] == 'o') {
60a79016
PC
307 int i;
308 for (i = 0; i < ngl->num_out; ++i) {
309 qemu_irq *disconnected = g_new0(qemu_irq, 1);
310 qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler,
311 disconnected, i);
312
313 *disconnected = qdev_intercept_gpio_out(dev, icpt,
314 ngl->name, i);
315 }
a5f54290
PC
316 } else {
317 qemu_irq_intercept_in(ngl->in, qtest_irq_handler,
318 ngl->num_in);
319 }
20288345
PB
320 }
321 irq_intercept_dev = dev;
322 qtest_send_prefix(chr);
323 qtest_send(chr, "OK\n");
324
325 } else if (strcmp(words[0], "outb") == 0 ||
326 strcmp(words[0], "outw") == 0 ||
327 strcmp(words[0], "outl") == 0) {
c7f0f3b1
AL
328 uint16_t addr;
329 uint32_t value;
330
331 g_assert(words[1] && words[2]);
56863d4f
PM
332 addr = strtoul(words[1], NULL, 0);
333 value = strtoul(words[2], NULL, 0);
c7f0f3b1
AL
334
335 if (words[0][3] == 'b') {
336 cpu_outb(addr, value);
337 } else if (words[0][3] == 'w') {
338 cpu_outw(addr, value);
339 } else if (words[0][3] == 'l') {
340 cpu_outl(addr, value);
341 }
342 qtest_send_prefix(chr);
343 qtest_send(chr, "OK\n");
344 } else if (strcmp(words[0], "inb") == 0 ||
345 strcmp(words[0], "inw") == 0 ||
346 strcmp(words[0], "inl") == 0) {
347 uint16_t addr;
348 uint32_t value = -1U;
349
350 g_assert(words[1]);
56863d4f 351 addr = strtoul(words[1], NULL, 0);
c7f0f3b1
AL
352
353 if (words[0][2] == 'b') {
354 value = cpu_inb(addr);
355 } else if (words[0][2] == 'w') {
356 value = cpu_inw(addr);
357 } else if (words[0][2] == 'l') {
358 value = cpu_inl(addr);
359 }
360 qtest_send_prefix(chr);
332cc7e9 361 qtest_sendf(chr, "OK 0x%04x\n", value);
872536bf
AF
362 } else if (strcmp(words[0], "writeb") == 0 ||
363 strcmp(words[0], "writew") == 0 ||
364 strcmp(words[0], "writel") == 0 ||
365 strcmp(words[0], "writeq") == 0) {
366 uint64_t addr;
367 uint64_t value;
368
369 g_assert(words[1] && words[2]);
370 addr = strtoull(words[1], NULL, 0);
371 value = strtoull(words[2], NULL, 0);
372
373 if (words[0][5] == 'b') {
374 uint8_t data = value;
375 cpu_physical_memory_write(addr, &data, 1);
376 } else if (words[0][5] == 'w') {
377 uint16_t data = value;
378 tswap16s(&data);
379 cpu_physical_memory_write(addr, &data, 2);
380 } else if (words[0][5] == 'l') {
381 uint32_t data = value;
382 tswap32s(&data);
383 cpu_physical_memory_write(addr, &data, 4);
384 } else if (words[0][5] == 'q') {
385 uint64_t data = value;
386 tswap64s(&data);
387 cpu_physical_memory_write(addr, &data, 8);
388 }
389 qtest_send_prefix(chr);
390 qtest_send(chr, "OK\n");
391 } else if (strcmp(words[0], "readb") == 0 ||
392 strcmp(words[0], "readw") == 0 ||
393 strcmp(words[0], "readl") == 0 ||
394 strcmp(words[0], "readq") == 0) {
395 uint64_t addr;
396 uint64_t value = UINT64_C(-1);
397
398 g_assert(words[1]);
399 addr = strtoull(words[1], NULL, 0);
400
401 if (words[0][4] == 'b') {
402 uint8_t data;
403 cpu_physical_memory_read(addr, &data, 1);
404 value = data;
405 } else if (words[0][4] == 'w') {
406 uint16_t data;
407 cpu_physical_memory_read(addr, &data, 2);
408 value = tswap16(data);
409 } else if (words[0][4] == 'l') {
410 uint32_t data;
411 cpu_physical_memory_read(addr, &data, 4);
412 value = tswap32(data);
413 } else if (words[0][4] == 'q') {
414 cpu_physical_memory_read(addr, &value, 8);
415 tswap64s(&value);
416 }
417 qtest_send_prefix(chr);
332cc7e9 418 qtest_sendf(chr, "OK 0x%016" PRIx64 "\n", value);
c7f0f3b1
AL
419 } else if (strcmp(words[0], "read") == 0) {
420 uint64_t addr, len, i;
421 uint8_t *data;
5560b85a 422 char *enc;
c7f0f3b1
AL
423
424 g_assert(words[1] && words[2]);
5dd6be06
AF
425 addr = strtoull(words[1], NULL, 0);
426 len = strtoull(words[2], NULL, 0);
c7f0f3b1
AL
427
428 data = g_malloc(len);
429 cpu_physical_memory_read(addr, data, len);
430
5560b85a 431 enc = g_malloc(2 * len + 1);
c7f0f3b1 432 for (i = 0; i < len; i++) {
5560b85a 433 sprintf(&enc[i * 2], "%02x", data[i]);
c7f0f3b1 434 }
5560b85a
JS
435
436 qtest_send_prefix(chr);
437 qtest_sendf(chr, "OK 0x%s\n", enc);
c7f0f3b1
AL
438
439 g_free(data);
5560b85a 440 g_free(enc);
7a6a740d
JS
441 } else if (strcmp(words[0], "b64read") == 0) {
442 uint64_t addr, len;
443 uint8_t *data;
444 gchar *b64_data;
445
446 g_assert(words[1] && words[2]);
447 addr = strtoull(words[1], NULL, 0);
448 len = strtoull(words[2], NULL, 0);
449
450 data = g_malloc(len);
451 cpu_physical_memory_read(addr, data, len);
452 b64_data = g_base64_encode(data, len);
453 qtest_send_prefix(chr);
454 qtest_sendf(chr, "OK %s\n", b64_data);
455
456 g_free(data);
457 g_free(b64_data);
c7f0f3b1
AL
458 } else if (strcmp(words[0], "write") == 0) {
459 uint64_t addr, len, i;
460 uint8_t *data;
461 size_t data_len;
462
463 g_assert(words[1] && words[2] && words[3]);
5dd6be06
AF
464 addr = strtoull(words[1], NULL, 0);
465 len = strtoull(words[2], NULL, 0);
c7f0f3b1
AL
466
467 data_len = strlen(words[3]);
468 if (data_len < 3) {
469 qtest_send(chr, "ERR invalid argument size\n");
470 return;
471 }
472
473 data = g_malloc(len);
474 for (i = 0; i < len; i++) {
475 if ((i * 2 + 4) <= data_len) {
476 data[i] = hex2nib(words[3][i * 2 + 2]) << 4;
477 data[i] |= hex2nib(words[3][i * 2 + 3]);
478 } else {
479 data[i] = 0;
480 }
481 }
482 cpu_physical_memory_write(addr, data, len);
483 g_free(data);
484
4d007963
JS
485 qtest_send_prefix(chr);
486 qtest_send(chr, "OK\n");
487 } else if (strcmp(words[0], "memset") == 0) {
488 uint64_t addr, len;
489 uint8_t *data;
490 uint8_t pattern;
491
492 g_assert(words[1] && words[2] && words[3]);
493 addr = strtoull(words[1], NULL, 0);
494 len = strtoull(words[2], NULL, 0);
495 pattern = strtoull(words[3], NULL, 0);
496
5f31bbf1
PM
497 if (len) {
498 data = g_malloc(len);
499 memset(data, pattern, len);
500 cpu_physical_memory_write(addr, data, len);
501 g_free(data);
502 }
4d007963 503
7a6a740d
JS
504 qtest_send_prefix(chr);
505 qtest_send(chr, "OK\n");
506 } else if (strcmp(words[0], "b64write") == 0) {
507 uint64_t addr, len;
508 uint8_t *data;
509 size_t data_len;
510 gsize out_len;
511
512 g_assert(words[1] && words[2] && words[3]);
513 addr = strtoull(words[1], NULL, 0);
514 len = strtoull(words[2], NULL, 0);
515
516 data_len = strlen(words[3]);
517 if (data_len < 3) {
518 qtest_send(chr, "ERR invalid argument size\n");
519 return;
520 }
521
522 data = g_base64_decode_inplace(words[3], &out_len);
523 if (out_len != len) {
524 qtest_log_send("b64write: data length mismatch (told %"PRIu64", "
525 "found %zu)\n",
526 len, out_len);
527 out_len = MIN(out_len, len);
528 }
529
530 cpu_physical_memory_write(addr, data, out_len);
531
c7f0f3b1
AL
532 qtest_send_prefix(chr);
533 qtest_send(chr, "OK\n");
d4fce24f 534 } else if (qtest_enabled() && strcmp(words[0], "clock_step") == 0) {
8156be56
PB
535 int64_t ns;
536
537 if (words[1]) {
538 ns = strtoll(words[1], NULL, 0);
539 } else {
40daca54 540 ns = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL);
8156be56 541 }
bc72ad67 542 qtest_clock_warp(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns);
8156be56 543 qtest_send_prefix(chr);
332cc7e9
JS
544 qtest_sendf(chr, "OK %"PRIi64"\n",
545 (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
d4fce24f 546 } else if (qtest_enabled() && strcmp(words[0], "clock_set") == 0) {
8156be56
PB
547 int64_t ns;
548
549 g_assert(words[1]);
550 ns = strtoll(words[1], NULL, 0);
551 qtest_clock_warp(ns);
552 qtest_send_prefix(chr);
332cc7e9
JS
553 qtest_sendf(chr, "OK %"PRIi64"\n",
554 (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
c7f0f3b1
AL
555 } else {
556 qtest_send_prefix(chr);
332cc7e9 557 qtest_sendf(chr, "FAIL Unknown command '%s'\n", words[0]);
c7f0f3b1
AL
558 }
559}
560
561static void qtest_process_inbuf(CharDriverState *chr, GString *inbuf)
562{
563 char *end;
564
565 while ((end = strchr(inbuf->str, '\n')) != NULL) {
566 size_t offset;
567 GString *cmd;
568 gchar **words;
569
570 offset = end - inbuf->str;
571
572 cmd = g_string_new_len(inbuf->str, offset);
573 g_string_erase(inbuf, 0, offset + 1);
574
575 words = g_strsplit(cmd->str, " ", 0);
576 qtest_process_command(chr, words);
577 g_strfreev(words);
578
579 g_string_free(cmd, TRUE);
580 }
581}
582
583static void qtest_read(void *opaque, const uint8_t *buf, int size)
584{
585 CharDriverState *chr = opaque;
586
587 g_string_append_len(inbuf, (const gchar *)buf, size);
588 qtest_process_inbuf(chr, inbuf);
589}
590
591static int qtest_can_read(void *opaque)
592{
593 return 1024;
594}
595
596static void qtest_event(void *opaque, int event)
597{
598 int i;
599
600 switch (event) {
601 case CHR_EVENT_OPENED:
ba646ff6
MA
602 /*
603 * We used to call qemu_system_reset() here, hoping we could
604 * use the same process for multiple tests that way. Never
605 * used. Injects an extra reset even when it's not used, and
606 * that can mess up tests, e.g. -boot once.
607 */
c7f0f3b1
AL
608 for (i = 0; i < ARRAY_SIZE(irq_levels); i++) {
609 irq_levels[i] = 0;
610 }
6e92466a 611 qemu_gettimeofday(&start_time);
c7f0f3b1
AL
612 qtest_opened = true;
613 if (qtest_log_fp) {
614 fprintf(qtest_log_fp, "[I " FMT_timeval "] OPENED\n",
35aa3fb3 615 (long) start_time.tv_sec, (long) start_time.tv_usec);
c7f0f3b1
AL
616 }
617 break;
618 case CHR_EVENT_CLOSED:
619 qtest_opened = false;
620 if (qtest_log_fp) {
6e92466a 621 qemu_timeval tv;
c7f0f3b1
AL
622 qtest_get_time(&tv);
623 fprintf(qtest_log_fp, "[I +" FMT_timeval "] CLOSED\n",
35aa3fb3 624 (long) tv.tv_sec, (long) tv.tv_usec);
c7f0f3b1
AL
625 }
626 break;
627 default:
628 break;
629 }
630}
631
b3adf5ac 632static int qtest_init_accel(MachineState *ms)
c7f0f3b1 633{
b3adf5ac
MA
634 QemuOpts *opts = qemu_opts_create(qemu_find_opts("icount"), NULL, 0,
635 &error_abort);
636 qemu_opt_set(opts, "shift", "0", &error_abort);
1ad9580b
ST
637 configure_icount(opts, &error_abort);
638 qemu_opts_del(opts);
d4fce24f
PB
639 return 0;
640}
641
23802b4f 642void qtest_init(const char *qtest_chrdev, const char *qtest_log, Error **errp)
d4fce24f
PB
643{
644 CharDriverState *chr;
c7f0f3b1
AL
645
646 chr = qemu_chr_new("qtest", qtest_chrdev, NULL);
647
23802b4f
FZ
648 if (chr == NULL) {
649 error_setg(errp, "Failed to initialize device for qtest: \"%s\"",
650 qtest_chrdev);
651 return;
652 }
653
c7f0f3b1
AL
654 if (qtest_log) {
655 if (strcmp(qtest_log, "none") != 0) {
656 qtest_log_fp = fopen(qtest_log, "w+");
657 }
658 } else {
659 qtest_log_fp = stderr;
660 }
661
107684c0
LL
662 qemu_chr_add_handlers(chr, qtest_can_read, qtest_read, qtest_event, chr);
663 qemu_chr_fe_set_echo(chr, true);
664
665 inbuf = g_string_new("");
c7f0f3b1 666 qtest_chr = chr;
c7f0f3b1 667}
b3be57c3
MT
668
669bool qtest_driver(void)
670{
671 return qtest_chr;
672}
3a6ce514
EH
673
674static void qtest_accel_class_init(ObjectClass *oc, void *data)
675{
676 AccelClass *ac = ACCEL_CLASS(oc);
677 ac->name = "QTest";
678 ac->available = qtest_available;
0d15da8e 679 ac->init_machine = qtest_init_accel;
3a6ce514
EH
680 ac->allowed = &qtest_allowed;
681}
682
683#define TYPE_QTEST_ACCEL ACCEL_CLASS_NAME("qtest")
684
685static const TypeInfo qtest_accel_type = {
686 .name = TYPE_QTEST_ACCEL,
687 .parent = TYPE_ACCEL,
688 .class_init = qtest_accel_class_init,
689};
690
691static void qtest_type_init(void)
692{
693 type_register_static(&qtest_accel_type);
694}
695
696type_init(qtest_type_init);