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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
41e9a804 TQ |
2 | #define _GNU_SOURCE |
3 | ||
4 | #include <assert.h> | |
47efb302 | 5 | #include <fcntl.h> |
47efb302 KX |
6 | #include <linux/perf_event.h> |
7 | #include <linux/bpf.h> | |
41e9a804 TQ |
8 | #include <sched.h> |
9 | #include <stdio.h> | |
10 | #include <stdlib.h> | |
11 | #include <sys/ioctl.h> | |
12 | #include <sys/resource.h> | |
13 | #include <sys/time.h> | |
14 | #include <sys/types.h> | |
15 | #include <sys/wait.h> | |
16 | #include <unistd.h> | |
17 | ||
47efb302 | 18 | #include "bpf_load.h" |
41e9a804 | 19 | #include "libbpf.h" |
205c8ada | 20 | #include "perf-sys.h" |
47efb302 KX |
21 | |
22 | #define SAMPLE_PERIOD 0x7fffffffffffffffULL | |
23 | ||
41e9a804 | 24 | static void check_on_cpu(int cpu, struct perf_event_attr *attr) |
47efb302 | 25 | { |
41e9a804 TQ |
26 | int pmu_fd, error = 0; |
27 | cpu_set_t set; | |
28 | __u64 value; | |
47efb302 | 29 | |
41e9a804 TQ |
30 | /* Move to target CPU */ |
31 | CPU_ZERO(&set); | |
32 | CPU_SET(cpu, &set); | |
33 | assert(sched_setaffinity(0, sizeof(set), &set) == 0); | |
34 | /* Open perf event and attach to the perf_event_array */ | |
35 | pmu_fd = sys_perf_event_open(attr, -1/*pid*/, cpu/*cpu*/, -1/*group_fd*/, 0); | |
36 | if (pmu_fd < 0) { | |
37 | fprintf(stderr, "sys_perf_event_open failed on CPU %d\n", cpu); | |
38 | error = 1; | |
39 | goto on_exit; | |
40 | } | |
41 | assert(bpf_map_update_elem(map_fd[0], &cpu, &pmu_fd, BPF_ANY) == 0); | |
42 | assert(ioctl(pmu_fd, PERF_EVENT_IOC_ENABLE, 0) == 0); | |
43 | /* Trigger the kprobe */ | |
44 | bpf_map_get_next_key(map_fd[1], &cpu, NULL); | |
45 | /* Check the value */ | |
46 | if (bpf_map_lookup_elem(map_fd[1], &cpu, &value)) { | |
47 | fprintf(stderr, "Value missing for CPU %d\n", cpu); | |
48 | error = 1; | |
49 | goto on_exit; | |
50 | } | |
51 | fprintf(stderr, "CPU %d: %llu\n", cpu, value); | |
52 | ||
53 | on_exit: | |
54 | assert(bpf_map_delete_elem(map_fd[0], &cpu) == 0 || error); | |
55 | assert(ioctl(pmu_fd, PERF_EVENT_IOC_DISABLE, 0) == 0 || error); | |
56 | assert(close(pmu_fd) == 0 || error); | |
57 | assert(bpf_map_delete_elem(map_fd[1], &cpu) == 0 || error); | |
58 | exit(error); | |
59 | } | |
60 | ||
61 | static void test_perf_event_array(struct perf_event_attr *attr, | |
62 | const char *name) | |
63 | { | |
64 | int i, status, nr_cpus = sysconf(_SC_NPROCESSORS_CONF); | |
65 | pid_t pid[nr_cpus]; | |
66 | int err = 0; | |
67 | ||
68 | printf("Test reading %s counters\n", name); | |
69 | ||
70 | for (i = 0; i < nr_cpus; i++) { | |
71 | pid[i] = fork(); | |
72 | assert(pid[i] >= 0); | |
73 | if (pid[i] == 0) { | |
74 | check_on_cpu(i, attr); | |
75 | exit(1); | |
76 | } | |
77 | } | |
78 | ||
79 | for (i = 0; i < nr_cpus; i++) { | |
80 | assert(waitpid(pid[i], &status, 0) == pid[i]); | |
81 | err |= status; | |
82 | } | |
83 | ||
84 | if (err) | |
85 | printf("Test: %s FAILED\n", name); | |
86 | } | |
87 | ||
88 | static void test_bpf_perf_event(void) | |
89 | { | |
90 | struct perf_event_attr attr_cycles = { | |
47efb302 KX |
91 | .freq = 0, |
92 | .sample_period = SAMPLE_PERIOD, | |
93 | .inherit = 0, | |
94 | .type = PERF_TYPE_HARDWARE, | |
95 | .read_format = 0, | |
96 | .sample_type = 0, | |
41e9a804 TQ |
97 | .config = PERF_COUNT_HW_CPU_CYCLES, |
98 | }; | |
99 | struct perf_event_attr attr_clock = { | |
100 | .freq = 0, | |
101 | .sample_period = SAMPLE_PERIOD, | |
102 | .inherit = 0, | |
103 | .type = PERF_TYPE_SOFTWARE, | |
104 | .read_format = 0, | |
105 | .sample_type = 0, | |
106 | .config = PERF_COUNT_SW_CPU_CLOCK, | |
107 | }; | |
108 | struct perf_event_attr attr_raw = { | |
109 | .freq = 0, | |
110 | .sample_period = SAMPLE_PERIOD, | |
111 | .inherit = 0, | |
112 | .type = PERF_TYPE_RAW, | |
113 | .read_format = 0, | |
114 | .sample_type = 0, | |
115 | /* Intel Instruction Retired */ | |
116 | .config = 0xc0, | |
117 | }; | |
118 | struct perf_event_attr attr_l1d_load = { | |
119 | .freq = 0, | |
120 | .sample_period = SAMPLE_PERIOD, | |
121 | .inherit = 0, | |
122 | .type = PERF_TYPE_HW_CACHE, | |
123 | .read_format = 0, | |
124 | .sample_type = 0, | |
125 | .config = | |
126 | PERF_COUNT_HW_CACHE_L1D | | |
127 | (PERF_COUNT_HW_CACHE_OP_READ << 8) | | |
128 | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16), | |
129 | }; | |
130 | struct perf_event_attr attr_llc_miss = { | |
131 | .freq = 0, | |
132 | .sample_period = SAMPLE_PERIOD, | |
133 | .inherit = 0, | |
134 | .type = PERF_TYPE_HW_CACHE, | |
135 | .read_format = 0, | |
136 | .sample_type = 0, | |
137 | .config = | |
138 | PERF_COUNT_HW_CACHE_LL | | |
139 | (PERF_COUNT_HW_CACHE_OP_READ << 8) | | |
140 | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16), | |
141 | }; | |
142 | struct perf_event_attr attr_msr_tsc = { | |
143 | .freq = 0, | |
144 | .sample_period = 0, | |
145 | .inherit = 0, | |
146 | /* From /sys/bus/event_source/devices/msr/ */ | |
147 | .type = 7, | |
148 | .read_format = 0, | |
149 | .sample_type = 0, | |
150 | .config = 0, | |
47efb302 KX |
151 | }; |
152 | ||
41e9a804 TQ |
153 | test_perf_event_array(&attr_cycles, "HARDWARE-cycles"); |
154 | test_perf_event_array(&attr_clock, "SOFTWARE-clock"); | |
155 | test_perf_event_array(&attr_raw, "RAW-instruction-retired"); | |
156 | test_perf_event_array(&attr_l1d_load, "HW_CACHE-L1D-load"); | |
47efb302 | 157 | |
41e9a804 TQ |
158 | /* below tests may fail in qemu */ |
159 | test_perf_event_array(&attr_llc_miss, "HW_CACHE-LLC-miss"); | |
160 | test_perf_event_array(&attr_msr_tsc, "Dynamic-msr-tsc"); | |
47efb302 KX |
161 | } |
162 | ||
163 | int main(int argc, char **argv) | |
164 | { | |
41e9a804 | 165 | struct rlimit r = {RLIM_INFINITY, RLIM_INFINITY}; |
47efb302 KX |
166 | char filename[256]; |
167 | ||
168 | snprintf(filename, sizeof(filename), "%s_kern.o", argv[0]); | |
169 | ||
41e9a804 | 170 | setrlimit(RLIMIT_MEMLOCK, &r); |
47efb302 KX |
171 | if (load_bpf_file(filename)) { |
172 | printf("%s", bpf_log_buf); | |
173 | return 1; | |
174 | } | |
175 | ||
176 | test_bpf_perf_event(); | |
47efb302 KX |
177 | return 0; |
178 | } |