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2609ec28 PMD |
1 | /* |
2 | * CPU watchpoints | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2.1 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qemu/main-loop.h" | |
22 | #include "exec/exec-all.h" | |
23 | #include "exec/translate-all.h" | |
24 | #include "sysemu/tcg.h" | |
25 | #include "sysemu/replay.h" | |
26 | #include "hw/core/tcg-cpu-ops.h" | |
27 | #include "hw/core/cpu.h" | |
28 | ||
29 | /* Add a watchpoint. */ | |
30 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, | |
31 | int flags, CPUWatchpoint **watchpoint) | |
32 | { | |
33 | CPUWatchpoint *wp; | |
34 | vaddr in_page; | |
35 | ||
36 | /* forbid ranges which are empty or run off the end of the address space */ | |
37 | if (len == 0 || (addr + len - 1) < addr) { | |
38 | error_report("tried to set invalid watchpoint at %" | |
39 | VADDR_PRIx ", len=%" VADDR_PRIu, addr, len); | |
40 | return -EINVAL; | |
41 | } | |
42 | wp = g_malloc(sizeof(*wp)); | |
43 | ||
44 | wp->vaddr = addr; | |
45 | wp->len = len; | |
46 | wp->flags = flags; | |
47 | ||
48 | /* keep all GDB-injected watchpoints in front */ | |
49 | if (flags & BP_GDB) { | |
50 | QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry); | |
51 | } else { | |
52 | QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry); | |
53 | } | |
54 | ||
55 | in_page = -(addr | TARGET_PAGE_MASK); | |
56 | if (len <= in_page) { | |
57 | tlb_flush_page(cpu, addr); | |
58 | } else { | |
59 | tlb_flush(cpu); | |
60 | } | |
61 | ||
62 | if (watchpoint) { | |
63 | *watchpoint = wp; | |
64 | } | |
65 | return 0; | |
66 | } | |
67 | ||
68 | /* Remove a specific watchpoint. */ | |
69 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, | |
70 | int flags) | |
71 | { | |
72 | CPUWatchpoint *wp; | |
73 | ||
74 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { | |
75 | if (addr == wp->vaddr && len == wp->len | |
76 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { | |
77 | cpu_watchpoint_remove_by_ref(cpu, wp); | |
78 | return 0; | |
79 | } | |
80 | } | |
81 | return -ENOENT; | |
82 | } | |
83 | ||
84 | /* Remove a specific watchpoint by reference. */ | |
85 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) | |
86 | { | |
87 | QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry); | |
88 | ||
89 | tlb_flush_page(cpu, watchpoint->vaddr); | |
90 | ||
91 | g_free(watchpoint); | |
92 | } | |
93 | ||
94 | /* Remove all matching watchpoints. */ | |
95 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask) | |
96 | { | |
97 | CPUWatchpoint *wp, *next; | |
98 | ||
99 | QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) { | |
100 | if (wp->flags & mask) { | |
101 | cpu_watchpoint_remove_by_ref(cpu, wp); | |
102 | } | |
103 | } | |
104 | } | |
105 | ||
106 | /* | |
107 | * Return true if this watchpoint address matches the specified | |
108 | * access (ie the address range covered by the watchpoint overlaps | |
109 | * partially or completely with the address range covered by the | |
110 | * access). | |
111 | */ | |
112 | static inline bool watchpoint_address_matches(CPUWatchpoint *wp, | |
113 | vaddr addr, vaddr len) | |
114 | { | |
115 | /* | |
116 | * We know the lengths are non-zero, but a little caution is | |
117 | * required to avoid errors in the case where the range ends | |
118 | * exactly at the top of the address space and so addr + len | |
119 | * wraps round to zero. | |
120 | */ | |
121 | vaddr wpend = wp->vaddr + wp->len - 1; | |
122 | vaddr addrend = addr + len - 1; | |
123 | ||
124 | return !(addr > wpend || wp->vaddr > addrend); | |
125 | } | |
126 | ||
127 | /* Return flags for watchpoints that match addr + prot. */ | |
128 | int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len) | |
129 | { | |
130 | CPUWatchpoint *wp; | |
131 | int ret = 0; | |
132 | ||
133 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { | |
134 | if (watchpoint_address_matches(wp, addr, len)) { | |
135 | ret |= wp->flags; | |
136 | } | |
137 | } | |
138 | return ret; | |
139 | } | |
140 | ||
141 | /* Generate a debug exception if a watchpoint has been hit. */ | |
142 | void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, | |
143 | MemTxAttrs attrs, int flags, uintptr_t ra) | |
144 | { | |
145 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
146 | CPUWatchpoint *wp; | |
147 | ||
148 | assert(tcg_enabled()); | |
149 | if (cpu->watchpoint_hit) { | |
150 | /* | |
151 | * We re-entered the check after replacing the TB. | |
152 | * Now raise the debug interrupt so that it will | |
153 | * trigger after the current instruction. | |
154 | */ | |
155 | qemu_mutex_lock_iothread(); | |
156 | cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG); | |
157 | qemu_mutex_unlock_iothread(); | |
158 | return; | |
159 | } | |
160 | ||
161 | if (cc->tcg_ops->adjust_watchpoint_address) { | |
162 | /* this is currently used only by ARM BE32 */ | |
163 | addr = cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len); | |
164 | } | |
019a9808 RH |
165 | |
166 | assert((flags & ~BP_MEM_ACCESS) == 0); | |
2609ec28 | 167 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
019a9808 RH |
168 | int hit_flags = wp->flags & flags; |
169 | ||
170 | if (hit_flags && watchpoint_address_matches(wp, addr, len)) { | |
2609ec28 PMD |
171 | if (replay_running_debug()) { |
172 | /* | |
173 | * replay_breakpoint reads icount. | |
174 | * Force recompile to succeed, because icount may | |
175 | * be read only at the end of the block. | |
176 | */ | |
177 | if (!cpu->can_do_io) { | |
178 | /* Force execution of one insn next time. */ | |
179 | cpu->cflags_next_tb = 1 | CF_LAST_IO | CF_NOIRQ | |
180 | | curr_cflags(cpu); | |
181 | cpu_loop_exit_restore(cpu, ra); | |
182 | } | |
183 | /* | |
184 | * Don't process the watchpoints when we are | |
185 | * in a reverse debugging operation. | |
186 | */ | |
187 | replay_breakpoint(); | |
188 | return; | |
189 | } | |
019a9808 RH |
190 | |
191 | wp->flags |= hit_flags << BP_HIT_SHIFT; | |
2609ec28 PMD |
192 | wp->hitaddr = MAX(addr, wp->vaddr); |
193 | wp->hitattrs = attrs; | |
194 | ||
019a9808 RH |
195 | if (wp->flags & BP_CPU |
196 | && cc->tcg_ops->debug_check_watchpoint | |
197 | && !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) { | |
2609ec28 PMD |
198 | wp->flags &= ~BP_WATCHPOINT_HIT; |
199 | continue; | |
200 | } | |
201 | cpu->watchpoint_hit = wp; | |
202 | ||
203 | mmap_lock(); | |
204 | /* This call also restores vCPU state */ | |
205 | tb_check_watchpoint(cpu, ra); | |
206 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { | |
207 | cpu->exception_index = EXCP_DEBUG; | |
208 | mmap_unlock(); | |
209 | cpu_loop_exit(cpu); | |
210 | } else { | |
211 | /* Force execution of one insn next time. */ | |
212 | cpu->cflags_next_tb = 1 | CF_LAST_IO | CF_NOIRQ | |
213 | | curr_cflags(cpu); | |
214 | mmap_unlock(); | |
215 | cpu_loop_exit_noexc(cpu); | |
216 | } | |
217 | } else { | |
218 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
219 | } | |
220 | } | |
221 | } |