[mirror_qemu.git] / softmmu_header.h

/*
 *  Software MMU support
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
#define DATA_TYPE uint64_t
#elif DATA_SIZE == 4
#define SUFFIX l
#define USUFFIX l
#define DATA_TYPE uint32_t
#elif DATA_SIZE == 2
#define SUFFIX w
#define USUFFIX uw
#define DATA_TYPE uint16_t
#define DATA_STYPE int16_t
#elif DATA_SIZE == 1
#define SUFFIX b
#define USUFFIX ub
#define DATA_TYPE uint8_t
#define DATA_STYPE int8_t
#else
#error unsupported data size
#endif

#if ACCESS_TYPE == 0

#define CPU_MEM_INDEX 0
#define MMUSUFFIX _mmu

#elif ACCESS_TYPE == 1

#define CPU_MEM_INDEX 1
#define MMUSUFFIX _mmu

#elif ACCESS_TYPE == 2

#ifdef TARGET_I386
#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
#elif defined (TARGET_PPC)
#define CPU_MEM_INDEX (msr_pr)
#elif defined (TARGET_MIPS)
#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
#elif defined (TARGET_SPARC)
#define CPU_MEM_INDEX ((env->psrs) == 0)
#elif defined (TARGET_ARM)
#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
#elif defined (TARGET_SH4)
#define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
#elif defined (TARGET_ALPHA)
#define CPU_MEM_INDEX ((env->ps >> 3) & 3)
#else
#error unsupported CPU
#endif
#define MMUSUFFIX _mmu

#elif ACCESS_TYPE == 3

#ifdef TARGET_I386
#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
#elif defined (TARGET_PPC)
#define CPU_MEM_INDEX (msr_pr)
#elif defined (TARGET_MIPS)
#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
#elif defined (TARGET_SPARC)
#define CPU_MEM_INDEX ((env->psrs) == 0)
#elif defined (TARGET_ARM)
#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
#elif defined (TARGET_SH4)
#define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
#elif defined (TARGET_ALPHA)
#define CPU_MEM_INDEX ((env->ps >> 3) & 3)
#else
#error unsupported CPU
#endif
#define MMUSUFFIX _cmmu

#else
#error invalid ACCESS_TYPE
#endif

#if DATA_SIZE == 8
#define RES_TYPE uint64_t
#else
#define RES_TYPE int
#endif

#if ACCESS_TYPE == 3
#define ADDR_READ addr_code
#else
#define ADDR_READ addr_read
#endif

DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                         int is_user);
void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int is_user);

#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
    (ACCESS_TYPE <= 1) && defined(ASM_SOFTMMU)

#define CPU_TLB_ENTRY_BITS 4

static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int res;

    asm volatile ("movl %1, %%edx\n"
                  "movl %1, %%eax\n"
                  "shrl %3, %%edx\n"
                  "andl %4, %%eax\n"
                  "andl %2, %%edx\n"
                  "leal %5(%%edx, %%ebp), %%edx\n"
                  "cmpl (%%edx), %%eax\n"
                  "movl %1, %%eax\n"
                  "je 1f\n"
                  "pushl %6\n"
                  "call %7\n"
                  "popl %%edx\n"
                  "movl %%eax, %0\n"
                  "jmp 2f\n"
                  "1:\n"
                  "addl 12(%%edx), %%eax\n"
#if DATA_SIZE == 1
                  "movzbl (%%eax), %0\n"
#elif DATA_SIZE == 2
                  "movzwl (%%eax), %0\n"
#elif DATA_SIZE == 4
                  "movl (%%eax), %0\n"
#else
#error unsupported size
#endif
                  "2:\n"
                  : "=r" (res)
                  : "r" (ptr), 
                  "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS), 
                  "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS), 
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
                  "i" (CPU_MEM_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
                  : "%eax", "%ecx", "%edx", "memory", "cc");
    return res;
}

#if DATA_SIZE <= 2
static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int res;

    asm volatile ("movl %1, %%edx\n"
                  "movl %1, %%eax\n"
                  "shrl %3, %%edx\n"
                  "andl %4, %%eax\n"
                  "andl %2, %%edx\n"
                  "leal %5(%%edx, %%ebp), %%edx\n"
                  "cmpl (%%edx), %%eax\n"
                  "movl %1, %%eax\n"
                  "je 1f\n"
                  "pushl %6\n"
                  "call %7\n"
                  "popl %%edx\n"
#if DATA_SIZE == 1
                  "movsbl %%al, %0\n"
#elif DATA_SIZE == 2
                  "movswl %%ax, %0\n"
#else
#error unsupported size
#endif
                  "jmp 2f\n"
                  "1:\n"
                  "addl 12(%%edx), %%eax\n"
#if DATA_SIZE == 1
                  "movsbl (%%eax), %0\n"
#elif DATA_SIZE == 2
                  "movswl (%%eax), %0\n"
#else
#error unsupported size
#endif
                  "2:\n"
                  : "=r" (res)
                  : "r" (ptr), 
                  "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS), 
                  "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS), 
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
                  "i" (CPU_MEM_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
                  : "%eax", "%ecx", "%edx", "memory", "cc");
    return res;
}
#endif

static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
{
    asm volatile ("movl %0, %%edx\n"
                  "movl %0, %%eax\n"
                  "shrl %3, %%edx\n"
                  "andl %4, %%eax\n"
                  "andl %2, %%edx\n"
                  "leal %5(%%edx, %%ebp), %%edx\n"
                  "cmpl (%%edx), %%eax\n"
                  "movl %0, %%eax\n"
                  "je 1f\n"
#if DATA_SIZE == 1
                  "movzbl %b1, %%edx\n"
#elif DATA_SIZE == 2
                  "movzwl %w1, %%edx\n"
#elif DATA_SIZE == 4
                  "movl %1, %%edx\n"
#else
#error unsupported size
#endif
                  "pushl %6\n"
                  "call %7\n"
                  "popl %%eax\n"
                  "jmp 2f\n"
                  "1:\n"
                  "addl 8(%%edx), %%eax\n"
#if DATA_SIZE == 1
                  "movb %b1, (%%eax)\n"
#elif DATA_SIZE == 2
                  "movw %w1, (%%eax)\n"
#elif DATA_SIZE == 4
                  "movl %1, (%%eax)\n"
#else
#error unsupported size
#endif
                  "2:\n"
                  : 
                  : "r" (ptr), 
/* NOTE: 'q' would be needed as constraint, but we could not use it
   with T1 ! */
                  "r" (v), 
                  "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS), 
                  "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS), 
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_write)),
                  "i" (CPU_MEM_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
                  : "%eax", "%ecx", "%edx", "memory", "cc");
}

#else

/* generic load/store macros */

static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int index;
    RES_TYPE res;
    target_ulong addr;
    unsigned long physaddr;
    int is_user;

    addr = ptr;
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    is_user = CPU_MEM_INDEX;
    if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ != 
                         (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
        res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
    } else {
        physaddr = addr + env->tlb_table[is_user][index].addend;
        res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
    }
    return res;
}

#if DATA_SIZE <= 2
static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int res, index;
    target_ulong addr;
    unsigned long physaddr;
    int is_user;

    addr = ptr;
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    is_user = CPU_MEM_INDEX;
    if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ != 
                         (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
        res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
    } else {
        physaddr = addr + env->tlb_table[is_user][index].addend;
        res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
    }
    return res;
}
#endif

#if ACCESS_TYPE != 3

/* generic store macro */

static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
{
    int index;
    target_ulong addr;
    unsigned long physaddr;
    int is_user;

    addr = ptr;
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    is_user = CPU_MEM_INDEX;
    if (__builtin_expect(env->tlb_table[is_user][index].addr_write != 
                         (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
        glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, is_user);
    } else {
        physaddr = addr + env->tlb_table[is_user][index].addend;
        glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
    }
}

#endif /* ACCESS_TYPE != 3 */

#endif /* !asm */

#if ACCESS_TYPE != 3

#if DATA_SIZE == 8
static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
{
    union {
        float64 d;
        uint64_t i;
    } u;
    u.i = glue(ldq, MEMSUFFIX)(ptr);
    return u.d;
}

static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
{
    union {
        float64 d;
        uint64_t i;
    } u;
    u.d = v;
    glue(stq, MEMSUFFIX)(ptr, u.i);
}
#endif /* DATA_SIZE == 8 */

#if DATA_SIZE == 4
static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
{
    union {
        float32 f;
        uint32_t i;
    } u;
    u.i = glue(ldl, MEMSUFFIX)(ptr);
    return u.f;
}

static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
{
    union {
        float32 f;
        uint32_t i;
    } u;
    u.f = v;
    glue(stl, MEMSUFFIX)(ptr, u.i);
}
#endif /* DATA_SIZE == 4 */

#endif /* ACCESS_TYPE != 3 */

#undef RES_TYPE
#undef DATA_TYPE
#undef DATA_STYPE
#undef SUFFIX
#undef USUFFIX
#undef DATA_SIZE
#undef CPU_MEM_INDEX
#undef MMUSUFFIX
#undef ADDR_READ
Commit	Line	Data
b92e5a22 FB	1	/*
	2	* Software MMU support
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#if DATA_SIZE == 8
	21	#define SUFFIX q
61382a50	22	#define USUFFIX q
b92e5a22 FB	23	#define DATA_TYPE uint64_t
	24	#elif DATA_SIZE == 4
	25	#define SUFFIX l
61382a50	26	#define USUFFIX l
b92e5a22 FB	27	#define DATA_TYPE uint32_t
	28	#elif DATA_SIZE == 2
	29	#define SUFFIX w
61382a50	30	#define USUFFIX uw
b92e5a22 FB	31	#define DATA_TYPE uint16_t
	32	#define DATA_STYPE int16_t
	33	#elif DATA_SIZE == 1
	34	#define SUFFIX b
61382a50	35	#define USUFFIX ub
b92e5a22 FB	36	#define DATA_TYPE uint8_t
	37	#define DATA_STYPE int8_t
	38	#else
	39	#error unsupported data size
	40	#endif
	41
61382a50 FB	42	#if ACCESS_TYPE == 0
	43
	44	#define CPU_MEM_INDEX 0
	45	#define MMUSUFFIX _mmu
	46
	47	#elif ACCESS_TYPE == 1
	48
	49	#define CPU_MEM_INDEX 1
	50	#define MMUSUFFIX _mmu
	51
	52	#elif ACCESS_TYPE == 2
	53
2d603d22	54	#ifdef TARGET_I386
61382a50	55	#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
2d603d22 FB	56	#elif defined (TARGET_PPC)
2d603d22 FB	57	#define CPU_MEM_INDEX (msr_pr)
6af0bf9c FB	58	#elif defined (TARGET_MIPS)
6af0bf9c FB	59	#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
e95c8d51 FB	60	#elif defined (TARGET_SPARC)
e95c8d51 FB	61	#define CPU_MEM_INDEX ((env->psrs) == 0)
b5ff1b31 FB	62	#elif defined (TARGET_ARM)
b5ff1b31 FB	63	#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
fdf9b3e8 FB	64	#elif defined (TARGET_SH4)
fdf9b3e8 FB	65	#define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
eddf68a6 JM	66	#elif defined (TARGET_ALPHA)
eddf68a6 JM	67	#define CPU_MEM_INDEX ((env->ps >> 3) & 3)
b5ff1b31 FB	68	#else
b5ff1b31 FB	69	#error unsupported CPU
2d603d22	70	#endif
61382a50 FB	71	#define MMUSUFFIX _mmu
	72
	73	#elif ACCESS_TYPE == 3
	74
2d603d22	75	#ifdef TARGET_I386
61382a50	76	#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
2d603d22 FB	77	#elif defined (TARGET_PPC)
2d603d22 FB	78	#define CPU_MEM_INDEX (msr_pr)
6af0bf9c FB	79	#elif defined (TARGET_MIPS)
6af0bf9c FB	80	#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
e95c8d51 FB	81	#elif defined (TARGET_SPARC)
e95c8d51 FB	82	#define CPU_MEM_INDEX ((env->psrs) == 0)
b5ff1b31 FB	83	#elif defined (TARGET_ARM)
b5ff1b31 FB	84	#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
fdf9b3e8 FB	85	#elif defined (TARGET_SH4)
fdf9b3e8 FB	86	#define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
eddf68a6 JM	87	#elif defined (TARGET_ALPHA)
eddf68a6 JM	88	#define CPU_MEM_INDEX ((env->ps >> 3) & 3)
b5ff1b31 FB	89	#else
b5ff1b31 FB	90	#error unsupported CPU
2d603d22	91	#endif
61382a50 FB	92	#define MMUSUFFIX _cmmu
61382a50 FB	93
b92e5a22	94	#else
61382a50	95	#error invalid ACCESS_TYPE
b92e5a22 FB	96	#endif
	97
	98	#if DATA_SIZE == 8
	99	#define RES_TYPE uint64_t
	100	#else
	101	#define RES_TYPE int
	102	#endif
	103
84b7b8e7 FB	104	#if ACCESS_TYPE == 3
	105	#define ADDR_READ addr_code
	106	#else
	107	#define ADDR_READ addr_read
	108	#endif
b92e5a22	109
c27004ec	110	DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50	111	int is_user);
c27004ec	112	void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int is_user);
b92e5a22	113
c27004ec FB	114	#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
c27004ec FB	115	(ACCESS_TYPE <= 1) && defined(ASM_SOFTMMU)
e16c53fa	116
84b7b8e7 FB	117	#define CPU_TLB_ENTRY_BITS 4
84b7b8e7 FB	118
c27004ec	119	static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
e16c53fa FB	120	{
	121	int res;
	122
	123	asm volatile ("movl %1, %%edx\n"
	124	"movl %1, %%eax\n"
	125	"shrl %3, %%edx\n"
	126	"andl %4, %%eax\n"
	127	"andl %2, %%edx\n"
	128	"leal %5(%%edx, %%ebp), %%edx\n"
	129	"cmpl (%%edx), %%eax\n"
	130	"movl %1, %%eax\n"
	131	"je 1f\n"
	132	"pushl %6\n"
	133	"call %7\n"
	134	"popl %%edx\n"
	135	"movl %%eax, %0\n"
	136	"jmp 2f\n"
	137	"1:\n"
84b7b8e7	138	"addl 12(%%edx), %%eax\n"
e16c53fa FB	139	#if DATA_SIZE == 1
	140	"movzbl (%%eax), %0\n"
	141	#elif DATA_SIZE == 2
	142	"movzwl (%%eax), %0\n"
	143	#elif DATA_SIZE == 4
	144	"movl (%%eax), %0\n"
	145	#else
	146	#error unsupported size
	147	#endif
	148	"2:\n"
	149	: "=r" (res)
	150	: "r" (ptr),
84b7b8e7 FB	151	"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
84b7b8e7 FB	152	"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
e16c53fa	153	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
84b7b8e7	154	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
e16c53fa FB	155	"i" (CPU_MEM_INDEX),
	156	"m" ((uint8_t )&glue(glue(__ld, SUFFIX), MMUSUFFIX))
	157	: "%eax", "%ecx", "%edx", "memory", "cc");
	158	return res;
	159	}
	160
	161	#if DATA_SIZE <= 2
c27004ec	162	static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
e16c53fa FB	163	{
	164	int res;
	165
	166	asm volatile ("movl %1, %%edx\n"
	167	"movl %1, %%eax\n"
	168	"shrl %3, %%edx\n"
	169	"andl %4, %%eax\n"
	170	"andl %2, %%edx\n"
	171	"leal %5(%%edx, %%ebp), %%edx\n"
	172	"cmpl (%%edx), %%eax\n"
	173	"movl %1, %%eax\n"
	174	"je 1f\n"
	175	"pushl %6\n"
	176	"call %7\n"
	177	"popl %%edx\n"
	178	#if DATA_SIZE == 1
	179	"movsbl %%al, %0\n"
	180	#elif DATA_SIZE == 2
	181	"movswl %%ax, %0\n"
	182	#else
	183	#error unsupported size
	184	#endif
	185	"jmp 2f\n"
	186	"1:\n"
84b7b8e7	187	"addl 12(%%edx), %%eax\n"
e16c53fa FB	188	#if DATA_SIZE == 1
	189	"movsbl (%%eax), %0\n"
	190	#elif DATA_SIZE == 2
	191	"movswl (%%eax), %0\n"
	192	#else
	193	#error unsupported size
	194	#endif
	195	"2:\n"
	196	: "=r" (res)
	197	: "r" (ptr),
84b7b8e7 FB	198	"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
84b7b8e7 FB	199	"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
e16c53fa	200	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
84b7b8e7	201	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
e16c53fa FB	202	"i" (CPU_MEM_INDEX),
	203	"m" ((uint8_t )&glue(glue(__ld, SUFFIX), MMUSUFFIX))
	204	: "%eax", "%ecx", "%edx", "memory", "cc");
	205	return res;
	206	}
	207	#endif
	208
c27004ec	209	static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
e16c53fa FB	210	{
	211	asm volatile ("movl %0, %%edx\n"
	212	"movl %0, %%eax\n"
	213	"shrl %3, %%edx\n"
	214	"andl %4, %%eax\n"
	215	"andl %2, %%edx\n"
	216	"leal %5(%%edx, %%ebp), %%edx\n"
	217	"cmpl (%%edx), %%eax\n"
	218	"movl %0, %%eax\n"
	219	"je 1f\n"
	220	#if DATA_SIZE == 1
	221	"movzbl %b1, %%edx\n"
	222	#elif DATA_SIZE == 2
	223	"movzwl %w1, %%edx\n"
	224	#elif DATA_SIZE == 4
	225	"movl %1, %%edx\n"
	226	#else
	227	#error unsupported size
	228	#endif
	229	"pushl %6\n"
	230	"call %7\n"
	231	"popl %%eax\n"
	232	"jmp 2f\n"
	233	"1:\n"
84b7b8e7	234	"addl 8(%%edx), %%eax\n"
e16c53fa FB	235	#if DATA_SIZE == 1
	236	"movb %b1, (%%eax)\n"
	237	#elif DATA_SIZE == 2
	238	"movw %w1, (%%eax)\n"
	239	#elif DATA_SIZE == 4
	240	"movl %1, (%%eax)\n"
	241	#else
	242	#error unsupported size
	243	#endif
	244	"2:\n"
	245	:
	246	: "r" (ptr),
	247	/* NOTE: 'q' would be needed as constraint, but we could not use it
	248	with T1 ! */
	249	"r" (v),
84b7b8e7 FB	250	"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
84b7b8e7 FB	251	"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
e16c53fa	252	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
84b7b8e7	253	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_write)),
e16c53fa FB	254	"i" (CPU_MEM_INDEX),
	255	"m" ((uint8_t )&glue(glue(__st, SUFFIX), MMUSUFFIX))
	256	: "%eax", "%ecx", "%edx", "memory", "cc");
	257	}
	258
	259	#else
	260
	261	/* generic load/store macros */
	262
c27004ec	263	static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
b92e5a22 FB	264	{
	265	int index;
	266	RES_TYPE res;
c27004ec FB	267	target_ulong addr;
c27004ec FB	268	unsigned long physaddr;
61382a50 FB	269	int is_user;
61382a50 FB	270
c27004ec	271	addr = ptr;
b92e5a22	272	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
61382a50	273	is_user = CPU_MEM_INDEX;
84b7b8e7	274	if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ !=
b92e5a22	275	(addr & (TARGET_PAGE_MASK \| (DATA_SIZE - 1))), 0)) {
61382a50	276	res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
b92e5a22	277	} else {
84b7b8e7	278	physaddr = addr + env->tlb_table[is_user][index].addend;
61382a50	279	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
b92e5a22 FB	280	}
	281	return res;
	282	}
	283
	284	#if DATA_SIZE <= 2
c27004ec	285	static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
b92e5a22 FB	286	{
b92e5a22 FB	287	int res, index;
c27004ec FB	288	target_ulong addr;
c27004ec FB	289	unsigned long physaddr;
61382a50 FB	290	int is_user;
61382a50 FB	291
c27004ec	292	addr = ptr;
b92e5a22	293	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
61382a50	294	is_user = CPU_MEM_INDEX;
84b7b8e7	295	if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ !=
b92e5a22	296	(addr & (TARGET_PAGE_MASK \| (DATA_SIZE - 1))), 0)) {
61382a50	297	res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
b92e5a22	298	} else {
84b7b8e7	299	physaddr = addr + env->tlb_table[is_user][index].addend;
b92e5a22 FB	300	res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
	301	}
	302	return res;
	303	}
	304	#endif
	305
84b7b8e7 FB	306	#if ACCESS_TYPE != 3
84b7b8e7 FB	307
e16c53fa FB	308	/* generic store macro */
e16c53fa FB	309
c27004ec	310	static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
b92e5a22 FB	311	{
b92e5a22 FB	312	int index;
c27004ec FB	313	target_ulong addr;
c27004ec FB	314	unsigned long physaddr;
61382a50 FB	315	int is_user;
61382a50 FB	316
c27004ec	317	addr = ptr;
b92e5a22	318	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
61382a50	319	is_user = CPU_MEM_INDEX;
84b7b8e7	320	if (__builtin_expect(env->tlb_table[is_user][index].addr_write !=
b92e5a22	321	(addr & (TARGET_PAGE_MASK \| (DATA_SIZE - 1))), 0)) {
61382a50	322	glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, is_user);
b92e5a22	323	} else {
84b7b8e7	324	physaddr = addr + env->tlb_table[is_user][index].addend;
b92e5a22 FB	325	glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
	326	}
	327	}
	328
84b7b8e7 FB	329	#endif /* ACCESS_TYPE != 3 */
	330
	331	#endif /* !asm */
	332
	333	#if ACCESS_TYPE != 3
e16c53fa	334
2d603d22	335	#if DATA_SIZE == 8
3f87bf69	336	static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
2d603d22 FB	337	{
2d603d22 FB	338	union {
3f87bf69	339	float64 d;
2d603d22 FB	340	uint64_t i;
	341	} u;
	342	u.i = glue(ldq, MEMSUFFIX)(ptr);
	343	return u.d;
	344	}
	345
3f87bf69	346	static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
2d603d22 FB	347	{
2d603d22 FB	348	union {
3f87bf69	349	float64 d;
2d603d22 FB	350	uint64_t i;
	351	} u;
	352	u.d = v;
	353	glue(stq, MEMSUFFIX)(ptr, u.i);
	354	}
	355	#endif /* DATA_SIZE == 8 */
	356
	357	#if DATA_SIZE == 4
3f87bf69	358	static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
2d603d22 FB	359	{
2d603d22 FB	360	union {
3f87bf69	361	float32 f;
2d603d22 FB	362	uint32_t i;
	363	} u;
	364	u.i = glue(ldl, MEMSUFFIX)(ptr);
	365	return u.f;
	366	}
	367
3f87bf69	368	static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
2d603d22 FB	369	{
2d603d22 FB	370	union {
3f87bf69	371	float32 f;
2d603d22 FB	372	uint32_t i;
	373	} u;
	374	u.f = v;
	375	glue(stl, MEMSUFFIX)(ptr, u.i);
	376	}
	377	#endif /* DATA_SIZE == 4 */
	378
84b7b8e7 FB	379	#endif /* ACCESS_TYPE != 3 */
84b7b8e7 FB	380
b92e5a22 FB	381	#undef RES_TYPE
	382	#undef DATA_TYPE
	383	#undef DATA_STYPE
	384	#undef SUFFIX
61382a50	385	#undef USUFFIX
b92e5a22	386	#undef DATA_SIZE
61382a50 FB	387	#undef CPU_MEM_INDEX
61382a50 FB	388	#undef MMUSUFFIX
84b7b8e7	389	#undef ADDR_READ