[mirror_qemu.git] / softmmu_header.h

/*
 *  Software MMU support
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
#define DATA_TYPE uint64_t
#elif DATA_SIZE == 4
#define SUFFIX l
#define USUFFIX l
#define DATA_TYPE uint32_t
#elif DATA_SIZE == 2
#define SUFFIX w
#define USUFFIX uw
#define DATA_TYPE uint16_t
#define DATA_STYPE int16_t
#elif DATA_SIZE == 1
#define SUFFIX b
#define USUFFIX ub
#define DATA_TYPE uint8_t
#define DATA_STYPE int8_t
#else
#error unsupported data size
#endif

#if ACCESS_TYPE == 0

#define CPU_MEM_INDEX 0
#define MMUSUFFIX _mmu

#elif ACCESS_TYPE == 1

#define CPU_MEM_INDEX 1
#define MMUSUFFIX _mmu

#elif ACCESS_TYPE == 2

#ifdef TARGET_I386
#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
#elif defined (TARGET_PPC)
#define CPU_MEM_INDEX (msr_pr)
#elif defined (TARGET_MIPS)
#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
#elif defined (TARGET_SPARC)
#define CPU_MEM_INDEX ((env->psrs) == 0)
#elif defined (TARGET_ARM)
#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
#else
#error unsupported CPU
#endif
#define MMUSUFFIX _mmu

#elif ACCESS_TYPE == 3

#ifdef TARGET_I386
#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
#elif defined (TARGET_PPC)
#define CPU_MEM_INDEX (msr_pr)
#elif defined (TARGET_MIPS)
#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
#elif defined (TARGET_SPARC)
#define CPU_MEM_INDEX ((env->psrs) == 0)
#elif defined (TARGET_ARM)
#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
#else
#error unsupported CPU
#endif
#define MMUSUFFIX _cmmu

#else
#error invalid ACCESS_TYPE
#endif

#if DATA_SIZE == 8
#define RES_TYPE uint64_t
#else
#define RES_TYPE int
#endif


DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                         int is_user);
void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int is_user);

#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
    (ACCESS_TYPE <= 1) && defined(ASM_SOFTMMU)

static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int res;

    asm volatile ("movl %1, %%edx\n"
                  "movl %1, %%eax\n"
                  "shrl %3, %%edx\n"
                  "andl %4, %%eax\n"
                  "andl %2, %%edx\n"
                  "leal %5(%%edx, %%ebp), %%edx\n"
                  "cmpl (%%edx), %%eax\n"
                  "movl %1, %%eax\n"
                  "je 1f\n"
                  "pushl %6\n"
                  "call %7\n"
                  "popl %%edx\n"
                  "movl %%eax, %0\n"
                  "jmp 2f\n"
                  "1:\n"
                  "addl 4(%%edx), %%eax\n"
#if DATA_SIZE == 1
                  "movzbl (%%eax), %0\n"
#elif DATA_SIZE == 2
                  "movzwl (%%eax), %0\n"
#elif DATA_SIZE == 4
                  "movl (%%eax), %0\n"
#else
#error unsupported size
#endif
                  "2:\n"
                  : "=r" (res)
                  : "r" (ptr), 
                  "i" ((CPU_TLB_SIZE - 1) << 3), 
                  "i" (TARGET_PAGE_BITS - 3), 
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_read[CPU_MEM_INDEX][0].address)),
                  "i" (CPU_MEM_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
                  : "%eax", "%ecx", "%edx", "memory", "cc");
    return res;
}

#if DATA_SIZE <= 2
static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int res;

    asm volatile ("movl %1, %%edx\n"
                  "movl %1, %%eax\n"
                  "shrl %3, %%edx\n"
                  "andl %4, %%eax\n"
                  "andl %2, %%edx\n"
                  "leal %5(%%edx, %%ebp), %%edx\n"
                  "cmpl (%%edx), %%eax\n"
                  "movl %1, %%eax\n"
                  "je 1f\n"
                  "pushl %6\n"
                  "call %7\n"
                  "popl %%edx\n"
#if DATA_SIZE == 1
                  "movsbl %%al, %0\n"
#elif DATA_SIZE == 2
                  "movswl %%ax, %0\n"
#else
#error unsupported size
#endif
                  "jmp 2f\n"
                  "1:\n"
                  "addl 4(%%edx), %%eax\n"
#if DATA_SIZE == 1
                  "movsbl (%%eax), %0\n"
#elif DATA_SIZE == 2
                  "movswl (%%eax), %0\n"
#else
#error unsupported size
#endif
                  "2:\n"
                  : "=r" (res)
                  : "r" (ptr), 
                  "i" ((CPU_TLB_SIZE - 1) << 3), 
                  "i" (TARGET_PAGE_BITS - 3), 
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_read[CPU_MEM_INDEX][0].address)),
                  "i" (CPU_MEM_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
                  : "%eax", "%ecx", "%edx", "memory", "cc");
    return res;
}
#endif

static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
{
    asm volatile ("movl %0, %%edx\n"
                  "movl %0, %%eax\n"
                  "shrl %3, %%edx\n"
                  "andl %4, %%eax\n"
                  "andl %2, %%edx\n"
                  "leal %5(%%edx, %%ebp), %%edx\n"
                  "cmpl (%%edx), %%eax\n"
                  "movl %0, %%eax\n"
                  "je 1f\n"
#if DATA_SIZE == 1
                  "movzbl %b1, %%edx\n"
#elif DATA_SIZE == 2
                  "movzwl %w1, %%edx\n"
#elif DATA_SIZE == 4
                  "movl %1, %%edx\n"
#else
#error unsupported size
#endif
                  "pushl %6\n"
                  "call %7\n"
                  "popl %%eax\n"
                  "jmp 2f\n"
                  "1:\n"
                  "addl 4(%%edx), %%eax\n"
#if DATA_SIZE == 1
                  "movb %b1, (%%eax)\n"
#elif DATA_SIZE == 2
                  "movw %w1, (%%eax)\n"
#elif DATA_SIZE == 4
                  "movl %1, (%%eax)\n"
#else
#error unsupported size
#endif
                  "2:\n"
                  : 
                  : "r" (ptr), 
/* NOTE: 'q' would be needed as constraint, but we could not use it
   with T1 ! */
                  "r" (v), 
                  "i" ((CPU_TLB_SIZE - 1) << 3), 
                  "i" (TARGET_PAGE_BITS - 3), 
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_write[CPU_MEM_INDEX][0].address)),
                  "i" (CPU_MEM_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
                  : "%eax", "%ecx", "%edx", "memory", "cc");
}

#else

/* generic load/store macros */

static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int index;
    RES_TYPE res;
    target_ulong addr;
    unsigned long physaddr;
    int is_user;

    addr = ptr;
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    is_user = CPU_MEM_INDEX;
    if (__builtin_expect(env->tlb_read[is_user][index].address != 
                         (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
        res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
    } else {
        physaddr = addr + env->tlb_read[is_user][index].addend;
        res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
    }
    return res;
}

#if DATA_SIZE <= 2
static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int res, index;
    target_ulong addr;
    unsigned long physaddr;
    int is_user;

    addr = ptr;
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    is_user = CPU_MEM_INDEX;
    if (__builtin_expect(env->tlb_read[is_user][index].address != 
                         (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
        res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
    } else {
        physaddr = addr + env->tlb_read[is_user][index].addend;
        res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
    }
    return res;
}
#endif

/* generic store macro */

static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
{
    int index;
    target_ulong addr;
    unsigned long physaddr;
    int is_user;

    addr = ptr;
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    is_user = CPU_MEM_INDEX;
    if (__builtin_expect(env->tlb_write[is_user][index].address != 
                         (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
        glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, is_user);
    } else {
        physaddr = addr + env->tlb_write[is_user][index].addend;
        glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
    }
}

#endif

#if DATA_SIZE == 8
static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
{
    union {
        float64 d;
        uint64_t i;
    } u;
    u.i = glue(ldq, MEMSUFFIX)(ptr);
    return u.d;
}

static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
{
    union {
        float64 d;
        uint64_t i;
    } u;
    u.d = v;
    glue(stq, MEMSUFFIX)(ptr, u.i);
}
#endif /* DATA_SIZE == 8 */

#if DATA_SIZE == 4
static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
{
    union {
        float32 f;
        uint32_t i;
    } u;
    u.i = glue(ldl, MEMSUFFIX)(ptr);
    return u.f;
}

static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
{
    union {
        float32 f;
        uint32_t i;
    } u;
    u.f = v;
    glue(stl, MEMSUFFIX)(ptr, u.i);
}
#endif /* DATA_SIZE == 4 */

#undef RES_TYPE
#undef DATA_TYPE
#undef DATA_STYPE
#undef SUFFIX
#undef USUFFIX
#undef DATA_SIZE
#undef CPU_MEM_INDEX
#undef MMUSUFFIX
Commit	Line	Data
b92e5a22 FB	1	/*
	2	* Software MMU support
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#if DATA_SIZE == 8
	21	#define SUFFIX q
61382a50	22	#define USUFFIX q
b92e5a22 FB	23	#define DATA_TYPE uint64_t
	24	#elif DATA_SIZE == 4
	25	#define SUFFIX l
61382a50	26	#define USUFFIX l
b92e5a22 FB	27	#define DATA_TYPE uint32_t
	28	#elif DATA_SIZE == 2
	29	#define SUFFIX w
61382a50	30	#define USUFFIX uw
b92e5a22 FB	31	#define DATA_TYPE uint16_t
	32	#define DATA_STYPE int16_t
	33	#elif DATA_SIZE == 1
	34	#define SUFFIX b
61382a50	35	#define USUFFIX ub
b92e5a22 FB	36	#define DATA_TYPE uint8_t
	37	#define DATA_STYPE int8_t
	38	#else
	39	#error unsupported data size
	40	#endif
	41
61382a50 FB	42	#if ACCESS_TYPE == 0
	43
	44	#define CPU_MEM_INDEX 0
	45	#define MMUSUFFIX _mmu
	46
	47	#elif ACCESS_TYPE == 1
	48
	49	#define CPU_MEM_INDEX 1
	50	#define MMUSUFFIX _mmu
	51
	52	#elif ACCESS_TYPE == 2
	53
2d603d22	54	#ifdef TARGET_I386
61382a50	55	#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
2d603d22 FB	56	#elif defined (TARGET_PPC)
2d603d22 FB	57	#define CPU_MEM_INDEX (msr_pr)
6af0bf9c FB	58	#elif defined (TARGET_MIPS)
6af0bf9c FB	59	#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
e95c8d51 FB	60	#elif defined (TARGET_SPARC)
e95c8d51 FB	61	#define CPU_MEM_INDEX ((env->psrs) == 0)
b5ff1b31 FB	62	#elif defined (TARGET_ARM)
	63	#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
	64	#else
	65	#error unsupported CPU
2d603d22	66	#endif
61382a50 FB	67	#define MMUSUFFIX _mmu
	68
	69	#elif ACCESS_TYPE == 3
	70
2d603d22	71	#ifdef TARGET_I386
61382a50	72	#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
2d603d22 FB	73	#elif defined (TARGET_PPC)
2d603d22 FB	74	#define CPU_MEM_INDEX (msr_pr)
6af0bf9c FB	75	#elif defined (TARGET_MIPS)
6af0bf9c FB	76	#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
e95c8d51 FB	77	#elif defined (TARGET_SPARC)
e95c8d51 FB	78	#define CPU_MEM_INDEX ((env->psrs) == 0)
b5ff1b31 FB	79	#elif defined (TARGET_ARM)
	80	#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
	81	#else
	82	#error unsupported CPU
2d603d22	83	#endif
61382a50 FB	84	#define MMUSUFFIX _cmmu
61382a50 FB	85
b92e5a22	86	#else
61382a50	87	#error invalid ACCESS_TYPE
b92e5a22 FB	88	#endif
	89
	90	#if DATA_SIZE == 8
	91	#define RES_TYPE uint64_t
	92	#else
	93	#define RES_TYPE int
	94	#endif
	95
	96
c27004ec	97	DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50	98	int is_user);
c27004ec	99	void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int is_user);
b92e5a22	100
c27004ec FB	101	#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
c27004ec FB	102	(ACCESS_TYPE <= 1) && defined(ASM_SOFTMMU)
e16c53fa	103
c27004ec	104	static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
e16c53fa FB	105	{
	106	int res;
	107
	108	asm volatile ("movl %1, %%edx\n"
	109	"movl %1, %%eax\n"
	110	"shrl %3, %%edx\n"
	111	"andl %4, %%eax\n"
	112	"andl %2, %%edx\n"
	113	"leal %5(%%edx, %%ebp), %%edx\n"
	114	"cmpl (%%edx), %%eax\n"
	115	"movl %1, %%eax\n"
	116	"je 1f\n"
	117	"pushl %6\n"
	118	"call %7\n"
	119	"popl %%edx\n"
	120	"movl %%eax, %0\n"
	121	"jmp 2f\n"
	122	"1:\n"
	123	"addl 4(%%edx), %%eax\n"
	124	#if DATA_SIZE == 1
	125	"movzbl (%%eax), %0\n"
	126	#elif DATA_SIZE == 2
	127	"movzwl (%%eax), %0\n"
	128	#elif DATA_SIZE == 4
	129	"movl (%%eax), %0\n"
	130	#else
	131	#error unsupported size
	132	#endif
	133	"2:\n"
	134	: "=r" (res)
	135	: "r" (ptr),
	136	"i" ((CPU_TLB_SIZE - 1) << 3),
	137	"i" (TARGET_PAGE_BITS - 3),
	138	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
	139	"m" ((uint32_t )offsetof(CPUState, tlb_read[CPU_MEM_INDEX][0].address)),
	140	"i" (CPU_MEM_INDEX),
	141	"m" ((uint8_t )&glue(glue(__ld, SUFFIX), MMUSUFFIX))
	142	: "%eax", "%ecx", "%edx", "memory", "cc");
	143	return res;
	144	}
	145
	146	#if DATA_SIZE <= 2
c27004ec	147	static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
e16c53fa FB	148	{
	149	int res;
	150
	151	asm volatile ("movl %1, %%edx\n"
	152	"movl %1, %%eax\n"
	153	"shrl %3, %%edx\n"
	154	"andl %4, %%eax\n"
	155	"andl %2, %%edx\n"
	156	"leal %5(%%edx, %%ebp), %%edx\n"
	157	"cmpl (%%edx), %%eax\n"
	158	"movl %1, %%eax\n"
	159	"je 1f\n"
	160	"pushl %6\n"
	161	"call %7\n"
	162	"popl %%edx\n"
	163	#if DATA_SIZE == 1
	164	"movsbl %%al, %0\n"
	165	#elif DATA_SIZE == 2
	166	"movswl %%ax, %0\n"
	167	#else
	168	#error unsupported size
	169	#endif
	170	"jmp 2f\n"
	171	"1:\n"
	172	"addl 4(%%edx), %%eax\n"
	173	#if DATA_SIZE == 1
	174	"movsbl (%%eax), %0\n"
	175	#elif DATA_SIZE == 2
	176	"movswl (%%eax), %0\n"
	177	#else
	178	#error unsupported size
	179	#endif
	180	"2:\n"
	181	: "=r" (res)
	182	: "r" (ptr),
	183	"i" ((CPU_TLB_SIZE - 1) << 3),
	184	"i" (TARGET_PAGE_BITS - 3),
	185	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
	186	"m" ((uint32_t )offsetof(CPUState, tlb_read[CPU_MEM_INDEX][0].address)),
	187	"i" (CPU_MEM_INDEX),
	188	"m" ((uint8_t )&glue(glue(__ld, SUFFIX), MMUSUFFIX))
	189	: "%eax", "%ecx", "%edx", "memory", "cc");
	190	return res;
	191	}
	192	#endif
	193
c27004ec	194	static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
e16c53fa FB	195	{
	196	asm volatile ("movl %0, %%edx\n"
	197	"movl %0, %%eax\n"
	198	"shrl %3, %%edx\n"
	199	"andl %4, %%eax\n"
	200	"andl %2, %%edx\n"
	201	"leal %5(%%edx, %%ebp), %%edx\n"
	202	"cmpl (%%edx), %%eax\n"
	203	"movl %0, %%eax\n"
	204	"je 1f\n"
	205	#if DATA_SIZE == 1
	206	"movzbl %b1, %%edx\n"
	207	#elif DATA_SIZE == 2
	208	"movzwl %w1, %%edx\n"
	209	#elif DATA_SIZE == 4
	210	"movl %1, %%edx\n"
	211	#else
	212	#error unsupported size
	213	#endif
	214	"pushl %6\n"
	215	"call %7\n"
	216	"popl %%eax\n"
	217	"jmp 2f\n"
	218	"1:\n"
	219	"addl 4(%%edx), %%eax\n"
	220	#if DATA_SIZE == 1
	221	"movb %b1, (%%eax)\n"
	222	#elif DATA_SIZE == 2
	223	"movw %w1, (%%eax)\n"
	224	#elif DATA_SIZE == 4
	225	"movl %1, (%%eax)\n"
	226	#else
	227	#error unsupported size
	228	#endif
	229	"2:\n"
	230	:
	231	: "r" (ptr),
	232	/* NOTE: 'q' would be needed as constraint, but we could not use it
	233	with T1 ! */
	234	"r" (v),
	235	"i" ((CPU_TLB_SIZE - 1) << 3),
	236	"i" (TARGET_PAGE_BITS - 3),
	237	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
	238	"m" ((uint32_t )offsetof(CPUState, tlb_write[CPU_MEM_INDEX][0].address)),
	239	"i" (CPU_MEM_INDEX),
	240	"m" ((uint8_t )&glue(glue(__st, SUFFIX), MMUSUFFIX))
	241	: "%eax", "%ecx", "%edx", "memory", "cc");
	242	}
	243
	244	#else
	245
	246	/* generic load/store macros */
	247
c27004ec	248	static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
b92e5a22 FB	249	{
	250	int index;
	251	RES_TYPE res;
c27004ec FB	252	target_ulong addr;
c27004ec FB	253	unsigned long physaddr;
61382a50 FB	254	int is_user;
61382a50 FB	255
c27004ec	256	addr = ptr;
b92e5a22	257	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
61382a50 FB	258	is_user = CPU_MEM_INDEX;
61382a50 FB	259	if (__builtin_expect(env->tlb_read[is_user][index].address !=
b92e5a22	260	(addr & (TARGET_PAGE_MASK \| (DATA_SIZE - 1))), 0)) {
61382a50	261	res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
b92e5a22	262	} else {
61382a50 FB	263	physaddr = addr + env->tlb_read[is_user][index].addend;
61382a50 FB	264	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
b92e5a22 FB	265	}
	266	return res;
	267	}
	268
	269	#if DATA_SIZE <= 2
c27004ec	270	static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
b92e5a22 FB	271	{
b92e5a22 FB	272	int res, index;
c27004ec FB	273	target_ulong addr;
c27004ec FB	274	unsigned long physaddr;
61382a50 FB	275	int is_user;
61382a50 FB	276
c27004ec	277	addr = ptr;
b92e5a22	278	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
61382a50 FB	279	is_user = CPU_MEM_INDEX;
61382a50 FB	280	if (__builtin_expect(env->tlb_read[is_user][index].address !=
b92e5a22	281	(addr & (TARGET_PAGE_MASK \| (DATA_SIZE - 1))), 0)) {
61382a50	282	res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
b92e5a22	283	} else {
61382a50	284	physaddr = addr + env->tlb_read[is_user][index].addend;
b92e5a22 FB	285	res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
	286	}
	287	return res;
	288	}
	289	#endif
	290
e16c53fa FB	291	/* generic store macro */
e16c53fa FB	292
c27004ec	293	static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
b92e5a22 FB	294	{
b92e5a22 FB	295	int index;
c27004ec FB	296	target_ulong addr;
c27004ec FB	297	unsigned long physaddr;
61382a50 FB	298	int is_user;
61382a50 FB	299
c27004ec	300	addr = ptr;
b92e5a22	301	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
61382a50 FB	302	is_user = CPU_MEM_INDEX;
61382a50 FB	303	if (__builtin_expect(env->tlb_write[is_user][index].address !=
b92e5a22	304	(addr & (TARGET_PAGE_MASK \| (DATA_SIZE - 1))), 0)) {
61382a50	305	glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, is_user);
b92e5a22	306	} else {
61382a50	307	physaddr = addr + env->tlb_write[is_user][index].addend;
b92e5a22 FB	308	glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
	309	}
	310	}
	311
e16c53fa FB	312	#endif
e16c53fa FB	313
2d603d22	314	#if DATA_SIZE == 8
3f87bf69	315	static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
2d603d22 FB	316	{
2d603d22 FB	317	union {
3f87bf69	318	float64 d;
2d603d22 FB	319	uint64_t i;
	320	} u;
	321	u.i = glue(ldq, MEMSUFFIX)(ptr);
	322	return u.d;
	323	}
	324
3f87bf69	325	static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
2d603d22 FB	326	{
2d603d22 FB	327	union {
3f87bf69	328	float64 d;
2d603d22 FB	329	uint64_t i;
	330	} u;
	331	u.d = v;
	332	glue(stq, MEMSUFFIX)(ptr, u.i);
	333	}
	334	#endif /* DATA_SIZE == 8 */
	335
	336	#if DATA_SIZE == 4
3f87bf69	337	static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
2d603d22 FB	338	{
2d603d22 FB	339	union {
3f87bf69	340	float32 f;
2d603d22 FB	341	uint32_t i;
	342	} u;
	343	u.i = glue(ldl, MEMSUFFIX)(ptr);
	344	return u.f;
	345	}
	346
3f87bf69	347	static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
2d603d22 FB	348	{
2d603d22 FB	349	union {
3f87bf69	350	float32 f;
2d603d22 FB	351	uint32_t i;
	352	} u;
	353	u.f = v;
	354	glue(stl, MEMSUFFIX)(ptr, u.i);
	355	}
	356	#endif /* DATA_SIZE == 4 */
	357
b92e5a22 FB	358	#undef RES_TYPE
	359	#undef DATA_TYPE
	360	#undef DATA_STYPE
	361	#undef SUFFIX
61382a50	362	#undef USUFFIX
b92e5a22	363	#undef DATA_SIZE
61382a50 FB	364	#undef CPU_MEM_INDEX
61382a50 FB	365	#undef MMUSUFFIX