[mirror_qemu.git] / softmmu_header.h

/*
 *  Software MMU support
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
#define DATA_TYPE uint64_t
#elif DATA_SIZE == 4
#define SUFFIX l
#define USUFFIX l
#define DATA_TYPE uint32_t
#elif DATA_SIZE == 2
#define SUFFIX w
#define USUFFIX uw
#define DATA_TYPE uint16_t
#define DATA_STYPE int16_t
#elif DATA_SIZE == 1
#define SUFFIX b
#define USUFFIX ub
#define DATA_TYPE uint8_t
#define DATA_STYPE int8_t
#else
#error unsupported data size
#endif

#if ACCESS_TYPE < (NB_MMU_MODES)

#define CPU_MMU_INDEX ACCESS_TYPE
#define MMUSUFFIX _mmu

#elif ACCESS_TYPE == (NB_MMU_MODES)

#define CPU_MMU_INDEX (cpu_mmu_index(env))
#define MMUSUFFIX _mmu

#elif ACCESS_TYPE == (NB_MMU_MODES + 1)

#define CPU_MMU_INDEX (cpu_mmu_index(env))
#define MMUSUFFIX _cmmu

#else
#error invalid ACCESS_TYPE
#endif

#if DATA_SIZE == 8
#define RES_TYPE uint64_t
#else
#define RES_TYPE int
#endif

#if ACCESS_TYPE == (NB_MMU_MODES + 1)
#define ADDR_READ addr_code
#else
#define ADDR_READ addr_read
#endif

#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
    (ACCESS_TYPE < NB_MMU_MODES) && defined(ASM_SOFTMMU)

static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int res;

    asm volatile ("movl %1, %%edx\n"
                  "movl %1, %%eax\n"
                  "shrl %3, %%edx\n"
                  "andl %4, %%eax\n"
                  "andl %2, %%edx\n"
                  "leal %5(%%edx, %%ebp), %%edx\n"
                  "cmpl (%%edx), %%eax\n"
                  "movl %1, %%eax\n"
                  "je 1f\n"
                  "movl %6, %%edx\n"
                  "call %7\n"
                  "movl %%eax, %0\n"
                  "jmp 2f\n"
                  "1:\n"
                  "addl 12(%%edx), %%eax\n"
#if DATA_SIZE == 1
                  "movzbl (%%eax), %0\n"
#elif DATA_SIZE == 2
                  "movzwl (%%eax), %0\n"
#elif DATA_SIZE == 4
                  "movl (%%eax), %0\n"
#else
#error unsupported size
#endif
                  "2:\n"
                  : "=r" (res)
                  : "r" (ptr),
                  "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
                  "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
                  "i" (CPU_MMU_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
                  : "%eax", "%ecx", "%edx", "memory", "cc");
    return res;
}

#if DATA_SIZE <= 2
static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int res;

    asm volatile ("movl %1, %%edx\n"
                  "movl %1, %%eax\n"
                  "shrl %3, %%edx\n"
                  "andl %4, %%eax\n"
                  "andl %2, %%edx\n"
                  "leal %5(%%edx, %%ebp), %%edx\n"
                  "cmpl (%%edx), %%eax\n"
                  "movl %1, %%eax\n"
                  "je 1f\n"
                  "movl %6, %%edx\n"
                  "call %7\n"
#if DATA_SIZE == 1
                  "movsbl %%al, %0\n"
#elif DATA_SIZE == 2
                  "movswl %%ax, %0\n"
#else
#error unsupported size
#endif
                  "jmp 2f\n"
                  "1:\n"
                  "addl 12(%%edx), %%eax\n"
#if DATA_SIZE == 1
                  "movsbl (%%eax), %0\n"
#elif DATA_SIZE == 2
                  "movswl (%%eax), %0\n"
#else
#error unsupported size
#endif
                  "2:\n"
                  : "=r" (res)
                  : "r" (ptr),
                  "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
                  "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
                  "i" (CPU_MMU_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
                  : "%eax", "%ecx", "%edx", "memory", "cc");
    return res;
}
#endif

static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
{
    asm volatile ("movl %0, %%edx\n"
                  "movl %0, %%eax\n"
                  "shrl %3, %%edx\n"
                  "andl %4, %%eax\n"
                  "andl %2, %%edx\n"
                  "leal %5(%%edx, %%ebp), %%edx\n"
                  "cmpl (%%edx), %%eax\n"
                  "movl %0, %%eax\n"
                  "je 1f\n"
#if DATA_SIZE == 1
                  "movzbl %b1, %%edx\n"
#elif DATA_SIZE == 2
                  "movzwl %w1, %%edx\n"
#elif DATA_SIZE == 4
                  "movl %1, %%edx\n"
#else
#error unsupported size
#endif
                  "movl %6, %%ecx\n"
                  "call %7\n"
                  "jmp 2f\n"
                  "1:\n"
                  "addl 8(%%edx), %%eax\n"
#if DATA_SIZE == 1
                  "movb %b1, (%%eax)\n"
#elif DATA_SIZE == 2
                  "movw %w1, (%%eax)\n"
#elif DATA_SIZE == 4
                  "movl %1, (%%eax)\n"
#else
#error unsupported size
#endif
                  "2:\n"
                  :
                  : "r" (ptr),
#if DATA_SIZE == 1
                  "q" (v),
#else
                  "r" (v),
#endif
                  "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
                  "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_write)),
                  "i" (CPU_MMU_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
                  : "%eax", "%ecx", "%edx", "memory", "cc");
}

#else

/* generic load/store macros */

static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int page_index;
    RES_TYPE res;
    target_ulong addr;
    unsigned long physaddr;
    int mmu_idx;

    addr = ptr;
    page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    mmu_idx = CPU_MMU_INDEX;
    if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
                 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
        res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
    } else {
        physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
        res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
    }
    return res;
}

#if DATA_SIZE <= 2
static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int res, page_index;
    target_ulong addr;
    unsigned long physaddr;
    int mmu_idx;

    addr = ptr;
    page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    mmu_idx = CPU_MMU_INDEX;
    if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
                 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
        res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
    } else {
        physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
        res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
    }
    return res;
}
#endif

#if ACCESS_TYPE != (NB_MMU_MODES + 1)

/* generic store macro */

static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
{
    int page_index;
    target_ulong addr;
    unsigned long physaddr;
    int mmu_idx;

    addr = ptr;
    page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    mmu_idx = CPU_MMU_INDEX;
    if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write !=
                 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
        glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, mmu_idx);
    } else {
        physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
        glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
    }
}

#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */

#endif /* !asm */

#if ACCESS_TYPE != (NB_MMU_MODES + 1)

#if DATA_SIZE == 8
static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
{
    union {
        float64 d;
        uint64_t i;
    } u;
    u.i = glue(ldq, MEMSUFFIX)(ptr);
    return u.d;
}

static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
{
    union {
        float64 d;
        uint64_t i;
    } u;
    u.d = v;
    glue(stq, MEMSUFFIX)(ptr, u.i);
}
#endif /* DATA_SIZE == 8 */

#if DATA_SIZE == 4
static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
{
    union {
        float32 f;
        uint32_t i;
    } u;
    u.i = glue(ldl, MEMSUFFIX)(ptr);
    return u.f;
}

static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
{
    union {
        float32 f;
        uint32_t i;
    } u;
    u.f = v;
    glue(stl, MEMSUFFIX)(ptr, u.i);
}
#endif /* DATA_SIZE == 4 */

#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */

#undef RES_TYPE
#undef DATA_TYPE
#undef DATA_STYPE
#undef SUFFIX
#undef USUFFIX
#undef DATA_SIZE
#undef CPU_MMU_INDEX
#undef MMUSUFFIX
#undef ADDR_READ
Commit	Line	Data
b92e5a22 FB	1	/*
b92e5a22 FB	2	* Software MMU support
5fafdf24	3	*
b92e5a22 FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
b92e5a22 FB	18	*/
	19	#if DATA_SIZE == 8
	20	#define SUFFIX q
61382a50	21	#define USUFFIX q
b92e5a22 FB	22	#define DATA_TYPE uint64_t
	23	#elif DATA_SIZE == 4
	24	#define SUFFIX l
61382a50	25	#define USUFFIX l
b92e5a22 FB	26	#define DATA_TYPE uint32_t
	27	#elif DATA_SIZE == 2
	28	#define SUFFIX w
61382a50	29	#define USUFFIX uw
b92e5a22 FB	30	#define DATA_TYPE uint16_t
	31	#define DATA_STYPE int16_t
	32	#elif DATA_SIZE == 1
	33	#define SUFFIX b
61382a50	34	#define USUFFIX ub
b92e5a22 FB	35	#define DATA_TYPE uint8_t
	36	#define DATA_STYPE int8_t
	37	#else
	38	#error unsupported data size
	39	#endif
	40
6ebbf390	41	#if ACCESS_TYPE < (NB_MMU_MODES)
61382a50	42
6ebbf390	43	#define CPU_MMU_INDEX ACCESS_TYPE
61382a50 FB	44	#define MMUSUFFIX _mmu
61382a50 FB	45
6ebbf390	46	#elif ACCESS_TYPE == (NB_MMU_MODES)
61382a50	47
6ebbf390	48	#define CPU_MMU_INDEX (cpu_mmu_index(env))
61382a50 FB	49	#define MMUSUFFIX _mmu
61382a50 FB	50
6ebbf390	51	#elif ACCESS_TYPE == (NB_MMU_MODES + 1)
61382a50	52
6ebbf390	53	#define CPU_MMU_INDEX (cpu_mmu_index(env))
61382a50 FB	54	#define MMUSUFFIX _cmmu
61382a50 FB	55
b92e5a22	56	#else
61382a50	57	#error invalid ACCESS_TYPE
b92e5a22 FB	58	#endif
	59
	60	#if DATA_SIZE == 8
	61	#define RES_TYPE uint64_t
	62	#else
	63	#define RES_TYPE int
	64	#endif
	65
6ebbf390	66	#if ACCESS_TYPE == (NB_MMU_MODES + 1)
84b7b8e7 FB	67	#define ADDR_READ addr_code
	68	#else
	69	#define ADDR_READ addr_read
	70	#endif
b92e5a22	71
c27004ec	72	#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
6ebbf390	73	(ACCESS_TYPE < NB_MMU_MODES) && defined(ASM_SOFTMMU)
e16c53fa	74
c27004ec	75	static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
e16c53fa FB	76	{
	77	int res;
	78
	79	asm volatile ("movl %1, %%edx\n"
	80	"movl %1, %%eax\n"
	81	"shrl %3, %%edx\n"
	82	"andl %4, %%eax\n"
	83	"andl %2, %%edx\n"
	84	"leal %5(%%edx, %%ebp), %%edx\n"
	85	"cmpl (%%edx), %%eax\n"
	86	"movl %1, %%eax\n"
	87	"je 1f\n"
d656469f	88	"movl %6, %%edx\n"
e16c53fa	89	"call %7\n"
e16c53fa FB	90	"movl %%eax, %0\n"
	91	"jmp 2f\n"
	92	"1:\n"
84b7b8e7	93	"addl 12(%%edx), %%eax\n"
e16c53fa FB	94	#if DATA_SIZE == 1
	95	"movzbl (%%eax), %0\n"
	96	#elif DATA_SIZE == 2
	97	"movzwl (%%eax), %0\n"
	98	#elif DATA_SIZE == 4
	99	"movl (%%eax), %0\n"
	100	#else
	101	#error unsupported size
	102	#endif
	103	"2:\n"
	104	: "=r" (res)
5fafdf24 TS	105	: "r" (ptr),
	106	"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
	107	"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
e16c53fa	108	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
6ebbf390 JM	109	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
6ebbf390 JM	110	"i" (CPU_MMU_INDEX),
e16c53fa FB	111	"m" ((uint8_t )&glue(glue(__ld, SUFFIX), MMUSUFFIX))
	112	: "%eax", "%ecx", "%edx", "memory", "cc");
	113	return res;
	114	}
	115
	116	#if DATA_SIZE <= 2
c27004ec	117	static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
e16c53fa FB	118	{
	119	int res;
	120
	121	asm volatile ("movl %1, %%edx\n"
	122	"movl %1, %%eax\n"
	123	"shrl %3, %%edx\n"
	124	"andl %4, %%eax\n"
	125	"andl %2, %%edx\n"
	126	"leal %5(%%edx, %%ebp), %%edx\n"
	127	"cmpl (%%edx), %%eax\n"
	128	"movl %1, %%eax\n"
	129	"je 1f\n"
d656469f	130	"movl %6, %%edx\n"
e16c53fa	131	"call %7\n"
e16c53fa FB	132	#if DATA_SIZE == 1
	133	"movsbl %%al, %0\n"
	134	#elif DATA_SIZE == 2
	135	"movswl %%ax, %0\n"
	136	#else
	137	#error unsupported size
	138	#endif
	139	"jmp 2f\n"
	140	"1:\n"
84b7b8e7	141	"addl 12(%%edx), %%eax\n"
e16c53fa FB	142	#if DATA_SIZE == 1
	143	"movsbl (%%eax), %0\n"
	144	#elif DATA_SIZE == 2
	145	"movswl (%%eax), %0\n"
	146	#else
	147	#error unsupported size
	148	#endif
	149	"2:\n"
	150	: "=r" (res)
5fafdf24 TS	151	: "r" (ptr),
	152	"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
	153	"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
e16c53fa	154	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
6ebbf390 JM	155	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
6ebbf390 JM	156	"i" (CPU_MMU_INDEX),
e16c53fa FB	157	"m" ((uint8_t )&glue(glue(__ld, SUFFIX), MMUSUFFIX))
	158	: "%eax", "%ecx", "%edx", "memory", "cc");
	159	return res;
	160	}
	161	#endif
	162
c27004ec	163	static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
e16c53fa FB	164	{
	165	asm volatile ("movl %0, %%edx\n"
	166	"movl %0, %%eax\n"
	167	"shrl %3, %%edx\n"
	168	"andl %4, %%eax\n"
	169	"andl %2, %%edx\n"
	170	"leal %5(%%edx, %%ebp), %%edx\n"
	171	"cmpl (%%edx), %%eax\n"
	172	"movl %0, %%eax\n"
	173	"je 1f\n"
	174	#if DATA_SIZE == 1
	175	"movzbl %b1, %%edx\n"
	176	#elif DATA_SIZE == 2
	177	"movzwl %w1, %%edx\n"
	178	#elif DATA_SIZE == 4
	179	"movl %1, %%edx\n"
	180	#else
	181	#error unsupported size
	182	#endif
d656469f	183	"movl %6, %%ecx\n"
e16c53fa	184	"call %7\n"
e16c53fa FB	185	"jmp 2f\n"
e16c53fa FB	186	"1:\n"
84b7b8e7	187	"addl 8(%%edx), %%eax\n"
e16c53fa FB	188	#if DATA_SIZE == 1
	189	"movb %b1, (%%eax)\n"
	190	#elif DATA_SIZE == 2
	191	"movw %w1, (%%eax)\n"
	192	#elif DATA_SIZE == 4
	193	"movl %1, (%%eax)\n"
	194	#else
	195	#error unsupported size
	196	#endif
	197	"2:\n"
5fafdf24 TS	198	:
5fafdf24 TS	199	: "r" (ptr),
f220f4e3 FB	200	#if DATA_SIZE == 1
	201	"q" (v),
	202	#else
5fafdf24	203	"r" (v),
f220f4e3	204	#endif
5fafdf24 TS	205	"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
5fafdf24 TS	206	"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
e16c53fa	207	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
6ebbf390 JM	208	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_write)),
6ebbf390 JM	209	"i" (CPU_MMU_INDEX),
e16c53fa FB	210	"m" ((uint8_t )&glue(glue(__st, SUFFIX), MMUSUFFIX))
	211	: "%eax", "%ecx", "%edx", "memory", "cc");
	212	}
	213
	214	#else
	215
	216	/* generic load/store macros */
	217
c27004ec	218	static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
b92e5a22	219	{
4d7a0880	220	int page_index;
b92e5a22	221	RES_TYPE res;
c27004ec FB	222	target_ulong addr;
c27004ec FB	223	unsigned long physaddr;
6ebbf390	224	int mmu_idx;
61382a50	225
c27004ec	226	addr = ptr;
4d7a0880	227	page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
6ebbf390	228	mmu_idx = CPU_MMU_INDEX;
551bd27f TS	229	if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
551bd27f TS	230	(addr & (TARGET_PAGE_MASK \| (DATA_SIZE - 1))))) {
6ebbf390	231	res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
b92e5a22	232	} else {
4d7a0880	233	physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
61382a50	234	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
b92e5a22 FB	235	}
	236	return res;
	237	}
	238
	239	#if DATA_SIZE <= 2
c27004ec	240	static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
b92e5a22	241	{
4d7a0880	242	int res, page_index;
c27004ec FB	243	target_ulong addr;
c27004ec FB	244	unsigned long physaddr;
6ebbf390	245	int mmu_idx;
61382a50	246
c27004ec	247	addr = ptr;
4d7a0880	248	page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
6ebbf390	249	mmu_idx = CPU_MMU_INDEX;
551bd27f TS	250	if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
551bd27f TS	251	(addr & (TARGET_PAGE_MASK \| (DATA_SIZE - 1))))) {
6ebbf390	252	res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
b92e5a22	253	} else {
4d7a0880	254	physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
b92e5a22 FB	255	res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
	256	}
	257	return res;
	258	}
	259	#endif
	260
6ebbf390	261	#if ACCESS_TYPE != (NB_MMU_MODES + 1)
84b7b8e7	262
e16c53fa FB	263	/* generic store macro */
e16c53fa FB	264
c27004ec	265	static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
b92e5a22	266	{
4d7a0880	267	int page_index;
c27004ec FB	268	target_ulong addr;
c27004ec FB	269	unsigned long physaddr;
6ebbf390	270	int mmu_idx;
61382a50	271
c27004ec	272	addr = ptr;
4d7a0880	273	page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
6ebbf390	274	mmu_idx = CPU_MMU_INDEX;
551bd27f TS	275	if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write !=
551bd27f TS	276	(addr & (TARGET_PAGE_MASK \| (DATA_SIZE - 1))))) {
6ebbf390	277	glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, mmu_idx);
b92e5a22	278	} else {
4d7a0880	279	physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
b92e5a22 FB	280	glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
	281	}
	282	}
	283
6ebbf390	284	#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
84b7b8e7 FB	285
	286	#endif /* !asm */
	287
6ebbf390	288	#if ACCESS_TYPE != (NB_MMU_MODES + 1)
e16c53fa	289
2d603d22	290	#if DATA_SIZE == 8
3f87bf69	291	static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
2d603d22 FB	292	{
2d603d22 FB	293	union {
3f87bf69	294	float64 d;
2d603d22 FB	295	uint64_t i;
	296	} u;
	297	u.i = glue(ldq, MEMSUFFIX)(ptr);
	298	return u.d;
	299	}
	300
3f87bf69	301	static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
2d603d22 FB	302	{
2d603d22 FB	303	union {
3f87bf69	304	float64 d;
2d603d22 FB	305	uint64_t i;
	306	} u;
	307	u.d = v;
	308	glue(stq, MEMSUFFIX)(ptr, u.i);
	309	}
	310	#endif /* DATA_SIZE == 8 */
	311
	312	#if DATA_SIZE == 4
3f87bf69	313	static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
2d603d22 FB	314	{
2d603d22 FB	315	union {
3f87bf69	316	float32 f;
2d603d22 FB	317	uint32_t i;
	318	} u;
	319	u.i = glue(ldl, MEMSUFFIX)(ptr);
	320	return u.f;
	321	}
	322
3f87bf69	323	static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
2d603d22 FB	324	{
2d603d22 FB	325	union {
3f87bf69	326	float32 f;
2d603d22 FB	327	uint32_t i;
	328	} u;
	329	u.f = v;
	330	glue(stl, MEMSUFFIX)(ptr, u.i);
	331	}
	332	#endif /* DATA_SIZE == 4 */
	333
6ebbf390	334	#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
84b7b8e7	335
b92e5a22 FB	336	#undef RES_TYPE
	337	#undef DATA_TYPE
	338	#undef DATA_STYPE
	339	#undef SUFFIX
61382a50	340	#undef USUFFIX
b92e5a22	341	#undef DATA_SIZE
6ebbf390	342	#undef CPU_MMU_INDEX
61382a50	343	#undef MMUSUFFIX
84b7b8e7	344	#undef ADDR_READ