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apic_common: improve readability of apic_reset_common
[mirror_qemu.git] / softmmu_template.h
CommitLineData
b92e5a22
FB		 1/*
2 * Software MMU support
5fafdf24 3 *
efbf29b6
BS		 4 * Generate helpers used by TCG for qemu_ld/st ops and code load
5 * functions.
6 *
7 * Included from target op helpers and exec.c.
8 *
b92e5a22
FB		 9 * Copyright (c) 2003 Fabrice Bellard
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU Lesser General Public
8167ee88 22 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
b92e5a22 23 */
1de7afc9 24#include "qemu/timer.h"
77717094 25#include "exec/address-spaces.h"
022c62cb 26#include "exec/memory.h"
29e922b6 27
b92e5a22
FB		 28#define DATA_SIZE (1 << SHIFT)
29
30#if DATA_SIZE == 8
31#define SUFFIX q
701e3a5c 32#define LSUFFIX q
c8f94df5 33#define SDATA_TYPE int64_t
dc9a353c 34#define DATA_TYPE uint64_t
b92e5a22
FB		 35#elif DATA_SIZE == 4
36#define SUFFIX l
701e3a5c 37#define LSUFFIX l
c8f94df5 38#define SDATA_TYPE int32_t
dc9a353c 39#define DATA_TYPE uint32_t
b92e5a22
FB		 40#elif DATA_SIZE == 2
41#define SUFFIX w
701e3a5c 42#define LSUFFIX uw
c8f94df5 43#define SDATA_TYPE int16_t
dc9a353c 44#define DATA_TYPE uint16_t
b92e5a22
FB		 45#elif DATA_SIZE == 1
46#define SUFFIX b
701e3a5c 47#define LSUFFIX ub
c8f94df5 48#define SDATA_TYPE int8_t
dc9a353c 49#define DATA_TYPE uint8_t
b92e5a22
FB		 50#else
51#error unsupported data size
52#endif
53
c8f94df5
RH		 54
55/* For the benefit of TCG generated code, we want to avoid the complication
56 of ABI-specific return type promotion and always return a value extended
57 to the register size of the host. This is tcg_target_long, except in the
58 case of a 32-bit host and 64-bit data, and for that we always have
59 uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */
60#if defined(SOFTMMU_CODE_ACCESS) || DATA_SIZE == 8
61# define WORD_TYPE DATA_TYPE
62# define USUFFIX SUFFIX
63#else
64# define WORD_TYPE tcg_target_ulong
65# define USUFFIX glue(u, SUFFIX)
66# define SSUFFIX glue(s, SUFFIX)
67#endif
68
b769d8fe 69#ifdef SOFTMMU_CODE_ACCESS
55e94093 70#define READ_ACCESS_TYPE MMU_INST_FETCH
84b7b8e7 71#define ADDR_READ addr_code
b769d8fe 72#else
55e94093 73#define READ_ACCESS_TYPE MMU_DATA_LOAD
84b7b8e7 74#define ADDR_READ addr_read
b769d8fe
FB		 75#endif
76
867b3201
RH		 77#if DATA_SIZE == 8
78# define BSWAP(X) bswap64(X)
79#elif DATA_SIZE == 4
80# define BSWAP(X) bswap32(X)
81#elif DATA_SIZE == 2
82# define BSWAP(X) bswap16(X)
83#else
84# define BSWAP(X) (X)
85#endif
86
87#ifdef TARGET_WORDS_BIGENDIAN
88# define TGT_BE(X) (X)
89# define TGT_LE(X) BSWAP(X)
90#else
91# define TGT_BE(X) BSWAP(X)
92# define TGT_LE(X) (X)
93#endif
94
95#if DATA_SIZE == 1
96# define helper_le_ld_name glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
97# define helper_be_ld_name helper_le_ld_name
98# define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)
99# define helper_be_lds_name helper_le_lds_name
100# define helper_le_st_name glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)
101# define helper_be_st_name helper_le_st_name
102#else
103# define helper_le_ld_name glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX)
104# define helper_be_ld_name glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX)
105# define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX)
106# define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX)
107# define helper_le_st_name glue(glue(helper_le_st, SUFFIX), MMUSUFFIX)
108# define helper_be_st_name glue(glue(helper_be_st, SUFFIX), MMUSUFFIX)
109#endif
110
111#ifdef TARGET_WORDS_BIGENDIAN
112# define helper_te_ld_name helper_be_ld_name
113# define helper_te_st_name helper_be_st_name
114#else
115# define helper_te_ld_name helper_le_ld_name
116# define helper_te_st_name helper_le_st_name
117#endif
118
88e89a57
XT		 119/* macro to check the victim tlb */
120#define VICTIM_TLB_HIT(ty) \
121({ \
122 /* we are about to do a page table walk. our last hope is the \
123 * victim tlb. try to refill from the victim tlb before walking the \
124 * page table. */ \
125 int vidx; \
e469b22f 126 CPUIOTLBEntry tmpiotlb; \
88e89a57
XT		 127 CPUTLBEntry tmptlb; \
128 for (vidx = CPU_VTLB_SIZE-1; vidx >= 0; --vidx) { \
129 if (env->tlb_v_table[mmu_idx][vidx].ty == (addr & TARGET_PAGE_MASK)) {\
130 /* found entry in victim tlb, swap tlb and iotlb */ \
131 tmptlb = env->tlb_table[mmu_idx][index]; \
132 env->tlb_table[mmu_idx][index] = env->tlb_v_table[mmu_idx][vidx]; \
133 env->tlb_v_table[mmu_idx][vidx] = tmptlb; \
134 tmpiotlb = env->iotlb[mmu_idx][index]; \
135 env->iotlb[mmu_idx][index] = env->iotlb_v[mmu_idx][vidx]; \
136 env->iotlb_v[mmu_idx][vidx] = tmpiotlb; \
137 break; \
138 } \
139 } \
140 /* return true when there is a vtlb hit, i.e. vidx >=0 */ \
141 vidx >= 0; \
142})
143
0f590e74 144#ifndef SOFTMMU_CODE_ACCESS
89c33337 145static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
e469b22f 146 CPUIOTLBEntry *iotlbentry,
2e70f6ef 147 target_ulong addr,
20503968 148 uintptr_t retaddr)
b92e5a22 149{
791af8c8 150 uint64_t val;
09daed84 151 CPUState *cpu = ENV_GET_CPU(env);
e469b22f 152 hwaddr physaddr = iotlbentry->addr;
9d82b5a7 153 MemoryRegion *mr = iotlb_to_region(cpu, physaddr);
37ec01d4 154
0f459d16 155 physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
93afeade 156 cpu->mem_io_pc = retaddr;
99df7dce 157 if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
90b40a69 158 cpu_io_recompile(cpu, retaddr);
2e70f6ef 159 }
b92e5a22 160
93afeade 161 cpu->mem_io_vaddr = addr;
3b643495 162 memory_region_dispatch_read(mr, physaddr, &val, 1 << SHIFT,
fadc1cbe 163 iotlbentry->attrs);
791af8c8 164 return val;
b92e5a22 165}
0f590e74 166#endif
b92e5a22 167
e25c3887 168#ifdef SOFTMMU_CODE_ACCESS
867b3201 169static __attribute__((unused))
e25c3887 170#endif
867b3201
RH		 171WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
172 uintptr_t retaddr)
b92e5a22 173{
aac1fb05
RH		 174 int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
175 target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
176 uintptr_t haddr;
867b3201 177 DATA_TYPE res;
3b46e624 178
0f842f8a
RH		 179 /* Adjust the given return address. */
180 retaddr -= GETPC_ADJ;
181
aac1fb05
RH		 182 /* If the TLB entry is for a different page, reload and try again. */
183 if ((addr & TARGET_PAGE_MASK)
184 != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
a64d4718 185#ifdef ALIGNED_ONLY
aac1fb05 186 if ((addr & (DATA_SIZE - 1)) != 0) {
93e22326
PB		 187 cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
188 mmu_idx, retaddr);
aac1fb05 189 }
a64d4718 190#endif
88e89a57
XT		 191 if (!VICTIM_TLB_HIT(ADDR_READ)) {
192 tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
193 mmu_idx, retaddr);
194 }
aac1fb05
RH		 195 tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
196 }
197
198 /* Handle an IO access. */
199 if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
e469b22f 200 CPUIOTLBEntry *iotlbentry;
aac1fb05
RH		 201 if ((addr & (DATA_SIZE - 1)) != 0) {
202 goto do_unaligned_access;
b92e5a22 203 }
e469b22f 204 iotlbentry = &env->iotlb[mmu_idx][index];
867b3201
RH		 205
206 /* ??? Note that the io helpers always read data in the target
207 byte ordering. We should push the LE/BE request down into io. */
e469b22f 208 res = glue(io_read, SUFFIX)(env, iotlbentry, addr, retaddr);
867b3201
RH		 209 res = TGT_LE(res);
210 return res;
aac1fb05
RH		 211 }
212
213 /* Handle slow unaligned access (it spans two pages or IO). */
214 if (DATA_SIZE > 1
215 && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
216 >= TARGET_PAGE_SIZE)) {
217 target_ulong addr1, addr2;
867b3201 218 DATA_TYPE res1, res2;
aac1fb05
RH		 219 unsigned shift;
220 do_unaligned_access:
a64d4718 221#ifdef ALIGNED_ONLY
93e22326
PB		 222 cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
223 mmu_idx, retaddr);
a64d4718 224#endif
aac1fb05
RH		 225 addr1 = addr & ~(DATA_SIZE - 1);
226 addr2 = addr1 + DATA_SIZE;
0f842f8a
RH		 227 /* Note the adjustment at the beginning of the function.
228 Undo that for the recursion. */
867b3201
RH		 229 res1 = helper_le_ld_name(env, addr1, mmu_idx, retaddr + GETPC_ADJ);
230 res2 = helper_le_ld_name(env, addr2, mmu_idx, retaddr + GETPC_ADJ);
aac1fb05 231 shift = (addr & (DATA_SIZE - 1)) * 8;
867b3201
RH		 232
233 /* Little-endian combine. */
aac1fb05 234 res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
867b3201
RH		 235 return res;
236 }
237
238 /* Handle aligned access or unaligned access in the same page. */
239#ifdef ALIGNED_ONLY
240 if ((addr & (DATA_SIZE - 1)) != 0) {
93e22326
PB		 241 cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
242 mmu_idx, retaddr);
867b3201
RH		 243 }
244#endif
245
246 haddr = addr + env->tlb_table[mmu_idx][index].addend;
247#if DATA_SIZE == 1
248 res = glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr);
249#else
250 res = glue(glue(ld, LSUFFIX), _le_p)((uint8_t *)haddr);
251#endif
252 return res;
253}
254
255#if DATA_SIZE > 1
256#ifdef SOFTMMU_CODE_ACCESS
257static __attribute__((unused))
258#endif
259WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
260 uintptr_t retaddr)
261{
262 int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
263 target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
264 uintptr_t haddr;
265 DATA_TYPE res;
266
267 /* Adjust the given return address. */
268 retaddr -= GETPC_ADJ;
269
270 /* If the TLB entry is for a different page, reload and try again. */
271 if ((addr & TARGET_PAGE_MASK)
272 != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
273#ifdef ALIGNED_ONLY
274 if ((addr & (DATA_SIZE - 1)) != 0) {
93e22326
PB		 275 cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
276 mmu_idx, retaddr);
867b3201
RH		 277 }
278#endif
88e89a57
XT		 279 if (!VICTIM_TLB_HIT(ADDR_READ)) {
280 tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
281 mmu_idx, retaddr);
282 }
867b3201
RH		 283 tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
284 }
285
286 /* Handle an IO access. */
287 if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
e469b22f 288 CPUIOTLBEntry *iotlbentry;
867b3201
RH		 289 if ((addr & (DATA_SIZE - 1)) != 0) {
290 goto do_unaligned_access;
291 }
e469b22f 292 iotlbentry = &env->iotlb[mmu_idx][index];
867b3201
RH		 293
294 /* ??? Note that the io helpers always read data in the target
295 byte ordering. We should push the LE/BE request down into io. */
e469b22f 296 res = glue(io_read, SUFFIX)(env, iotlbentry, addr, retaddr);
867b3201
RH		 297 res = TGT_BE(res);
298 return res;
299 }
300
301 /* Handle slow unaligned access (it spans two pages or IO). */
302 if (DATA_SIZE > 1
303 && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
304 >= TARGET_PAGE_SIZE)) {
305 target_ulong addr1, addr2;
306 DATA_TYPE res1, res2;
307 unsigned shift;
308 do_unaligned_access:
309#ifdef ALIGNED_ONLY
93e22326
PB		 310 cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
311 mmu_idx, retaddr);
aac1fb05 312#endif
867b3201
RH		 313 addr1 = addr & ~(DATA_SIZE - 1);
314 addr2 = addr1 + DATA_SIZE;
315 /* Note the adjustment at the beginning of the function.
316 Undo that for the recursion. */
317 res1 = helper_be_ld_name(env, addr1, mmu_idx, retaddr + GETPC_ADJ);
318 res2 = helper_be_ld_name(env, addr2, mmu_idx, retaddr + GETPC_ADJ);
319 shift = (addr & (DATA_SIZE - 1)) * 8;
320
321 /* Big-endian combine. */
322 res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
aac1fb05
RH		 323 return res;
324 }
325
326 /* Handle aligned access or unaligned access in the same page. */
327#ifdef ALIGNED_ONLY
328 if ((addr & (DATA_SIZE - 1)) != 0) {
93e22326
PB		 329 cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
330 mmu_idx, retaddr);
b92e5a22 331 }
aac1fb05
RH		 332#endif
333
334 haddr = addr + env->tlb_table[mmu_idx][index].addend;
867b3201
RH		 335 res = glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr);
336 return res;
b92e5a22 337}
867b3201 338#endif /* DATA_SIZE > 1 */
b92e5a22 339
e25c3887
RH		 340DATA_TYPE
341glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
342 int mmu_idx)
343{
867b3201 344 return helper_te_ld_name (env, addr, mmu_idx, GETRA());
e25c3887
RH		 345}
346
b769d8fe
FB		 347#ifndef SOFTMMU_CODE_ACCESS
348
c8f94df5
RH		 349/* Provide signed versions of the load routines as well. We can of course
350 avoid this for 64-bit data, or for 32-bit data on 32-bit host. */
351#if DATA_SIZE * 8 < TCG_TARGET_REG_BITS
867b3201
RH		 352WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr,
353 int mmu_idx, uintptr_t retaddr)
354{
355 return (SDATA_TYPE)helper_le_ld_name(env, addr, mmu_idx, retaddr);
356}
357
358# if DATA_SIZE > 1
359WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr,
360 int mmu_idx, uintptr_t retaddr)
c8f94df5 361{
867b3201 362 return (SDATA_TYPE)helper_be_ld_name(env, addr, mmu_idx, retaddr);
c8f94df5 363}
867b3201 364# endif
c8f94df5
RH		 365#endif
366
89c33337 367static inline void glue(io_write, SUFFIX)(CPUArchState *env,
e469b22f 368 CPUIOTLBEntry *iotlbentry,
b769d8fe 369 DATA_TYPE val,
0f459d16 370 target_ulong addr,
20503968 371 uintptr_t retaddr)
b769d8fe 372{
09daed84 373 CPUState *cpu = ENV_GET_CPU(env);
e469b22f 374 hwaddr physaddr = iotlbentry->addr;
9d82b5a7 375 MemoryRegion *mr = iotlb_to_region(cpu, physaddr);
37ec01d4 376
0f459d16 377 physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
99df7dce 378 if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
90b40a69 379 cpu_io_recompile(cpu, retaddr);
2e70f6ef 380 }
b769d8fe 381
93afeade
AF		 382 cpu->mem_io_vaddr = addr;
383 cpu->mem_io_pc = retaddr;
3b643495 384 memory_region_dispatch_write(mr, physaddr, val, 1 << SHIFT,
fadc1cbe 385 iotlbentry->attrs);
b769d8fe 386}
b92e5a22 387
867b3201
RH		 388void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
389 int mmu_idx, uintptr_t retaddr)
b92e5a22 390{
aac1fb05
RH		 391 int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
392 target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
393 uintptr_t haddr;
3b46e624 394
0f842f8a
RH		 395 /* Adjust the given return address. */
396 retaddr -= GETPC_ADJ;
397
aac1fb05
RH		 398 /* If the TLB entry is for a different page, reload and try again. */
399 if ((addr & TARGET_PAGE_MASK)
400 != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
a64d4718 401#ifdef ALIGNED_ONLY
aac1fb05 402 if ((addr & (DATA_SIZE - 1)) != 0) {
55e94093
LA		 403 cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
404 mmu_idx, retaddr);
aac1fb05 405 }
a64d4718 406#endif
88e89a57 407 if (!VICTIM_TLB_HIT(addr_write)) {
55e94093 408 tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
88e89a57 409 }
aac1fb05
RH		 410 tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
411 }
412
413 /* Handle an IO access. */
414 if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
e469b22f 415 CPUIOTLBEntry *iotlbentry;
aac1fb05
RH		 416 if ((addr & (DATA_SIZE - 1)) != 0) {
417 goto do_unaligned_access;
418 }
e469b22f 419 iotlbentry = &env->iotlb[mmu_idx][index];
867b3201
RH		 420
421 /* ??? Note that the io helpers always read data in the target
422 byte ordering. We should push the LE/BE request down into io. */
423 val = TGT_LE(val);
e469b22f 424 glue(io_write, SUFFIX)(env, iotlbentry, val, addr, retaddr);
aac1fb05
RH		 425 return;
426 }
427
428 /* Handle slow unaligned access (it spans two pages or IO). */
429 if (DATA_SIZE > 1
430 && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
431 >= TARGET_PAGE_SIZE)) {
432 int i;
433 do_unaligned_access:
a64d4718 434#ifdef ALIGNED_ONLY
55e94093
LA		 435 cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
436 mmu_idx, retaddr);
aac1fb05
RH		 437#endif
438 /* XXX: not efficient, but simple */
439 /* Note: relies on the fact that tlb_fill() does not remove the
440 * previous page from the TLB cache. */
441 for (i = DATA_SIZE - 1; i >= 0; i--) {
867b3201 442 /* Little-endian extract. */
aac1fb05 443 uint8_t val8 = val >> (i * 8);
867b3201
RH		 444 /* Note the adjustment at the beginning of the function.
445 Undo that for the recursion. */
446 glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
447 mmu_idx, retaddr + GETPC_ADJ);
448 }
449 return;
450 }
451
452 /* Handle aligned access or unaligned access in the same page. */
453#ifdef ALIGNED_ONLY
454 if ((addr & (DATA_SIZE - 1)) != 0) {
55e94093
LA		 455 cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
456 mmu_idx, retaddr);
867b3201
RH		 457 }
458#endif
459
460 haddr = addr + env->tlb_table[mmu_idx][index].addend;
461#if DATA_SIZE == 1
462 glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val);
463#else
464 glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val);
a64d4718 465#endif
867b3201
RH		 466}
467
468#if DATA_SIZE > 1
469void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
470 int mmu_idx, uintptr_t retaddr)
471{
472 int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
473 target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
474 uintptr_t haddr;
475
476 /* Adjust the given return address. */
477 retaddr -= GETPC_ADJ;
478
479 /* If the TLB entry is for a different page, reload and try again. */
480 if ((addr & TARGET_PAGE_MASK)
481 != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
482#ifdef ALIGNED_ONLY
483 if ((addr & (DATA_SIZE - 1)) != 0) {
55e94093
LA		 484 cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
485 mmu_idx, retaddr);
867b3201
RH		 486 }
487#endif
88e89a57 488 if (!VICTIM_TLB_HIT(addr_write)) {
55e94093 489 tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
88e89a57 490 }
867b3201
RH		 491 tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
492 }
493
494 /* Handle an IO access. */
495 if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
e469b22f 496 CPUIOTLBEntry *iotlbentry;
867b3201
RH		 497 if ((addr & (DATA_SIZE - 1)) != 0) {
498 goto do_unaligned_access;
499 }
e469b22f 500 iotlbentry = &env->iotlb[mmu_idx][index];
867b3201
RH		 501
502 /* ??? Note that the io helpers always read data in the target
503 byte ordering. We should push the LE/BE request down into io. */
504 val = TGT_BE(val);
e469b22f 505 glue(io_write, SUFFIX)(env, iotlbentry, val, addr, retaddr);
867b3201
RH		 506 return;
507 }
508
509 /* Handle slow unaligned access (it spans two pages or IO). */
510 if (DATA_SIZE > 1
511 && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
512 >= TARGET_PAGE_SIZE)) {
513 int i;
514 do_unaligned_access:
515#ifdef ALIGNED_ONLY
55e94093
LA		 516 cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
517 mmu_idx, retaddr);
867b3201
RH		 518#endif
519 /* XXX: not efficient, but simple */
520 /* Note: relies on the fact that tlb_fill() does not remove the
521 * previous page from the TLB cache. */
522 for (i = DATA_SIZE - 1; i >= 0; i--) {
523 /* Big-endian extract. */
524 uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8));
0f842f8a
RH		 525 /* Note the adjustment at the beginning of the function.
526 Undo that for the recursion. */
aac1fb05 527 glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
0f842f8a 528 mmu_idx, retaddr + GETPC_ADJ);
b92e5a22 529 }
aac1fb05
RH		 530 return;
531 }
532
533 /* Handle aligned access or unaligned access in the same page. */
a64d4718 534#ifdef ALIGNED_ONLY
aac1fb05 535 if ((addr & (DATA_SIZE - 1)) != 0) {
55e94093
LA		 536 cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
537 mmu_idx, retaddr);
b92e5a22 538 }
aac1fb05
RH		 539#endif
540
541 haddr = addr + env->tlb_table[mmu_idx][index].addend;
867b3201 542 glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);
b92e5a22 543}
867b3201 544#endif /* DATA_SIZE > 1 */
b92e5a22 545
e25c3887
RH		 546void
547glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
548 DATA_TYPE val, int mmu_idx)
549{
867b3201 550 helper_te_st_name(env, addr, val, mmu_idx, GETRA());
e25c3887
RH		 551}
552
b769d8fe
FB		 553#endif /* !defined(SOFTMMU_CODE_ACCESS) */
554
555#undef READ_ACCESS_TYPE
b92e5a22
FB		 556#undef SHIFT
557#undef DATA_TYPE
558#undef SUFFIX
701e3a5c 559#undef LSUFFIX
b92e5a22 560#undef DATA_SIZE
84b7b8e7 561#undef ADDR_READ
c8f94df5
RH		 562#undef WORD_TYPE
563#undef SDATA_TYPE
564#undef USUFFIX
565#undef SSUFFIX
867b3201
RH		 566#undef BSWAP
567#undef TGT_BE
568#undef TGT_LE
569#undef CPU_BE
570#undef CPU_LE
571#undef helper_le_ld_name
572#undef helper_be_ld_name
573#undef helper_le_lds_name
574#undef helper_be_lds_name
575#undef helper_le_st_name
576#undef helper_be_st_name
577#undef helper_te_ld_name
578#undef helper_te_st_name
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