[mirror_qemu.git] / softmmu_template.h

/*
 *  Software MMU support
 *
 * Generate helpers used by TCG for qemu_ld/st ops and code load
 * functions.
 *
 * Included from target op helpers and exec.c.
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#if DATA_SIZE == 8
#define SUFFIX q
#define LSUFFIX q
#define SDATA_TYPE  int64_t
#define DATA_TYPE  uint64_t
#elif DATA_SIZE == 4
#define SUFFIX l
#define LSUFFIX l
#define SDATA_TYPE  int32_t
#define DATA_TYPE  uint32_t
#elif DATA_SIZE == 2
#define SUFFIX w
#define LSUFFIX uw
#define SDATA_TYPE  int16_t
#define DATA_TYPE  uint16_t
#elif DATA_SIZE == 1
#define SUFFIX b
#define LSUFFIX ub
#define SDATA_TYPE  int8_t
#define DATA_TYPE  uint8_t
#else
#error unsupported data size
#endif


/* For the benefit of TCG generated code, we want to avoid the complication
   of ABI-specific return type promotion and always return a value extended
   to the register size of the host.  This is tcg_target_long, except in the
   case of a 32-bit host and 64-bit data, and for that we always have
   uint64_t.  Don't bother with this widened value for SOFTMMU_CODE_ACCESS.  */
#if defined(SOFTMMU_CODE_ACCESS) || DATA_SIZE == 8
# define WORD_TYPE  DATA_TYPE
# define USUFFIX    SUFFIX
#else
# define WORD_TYPE  tcg_target_ulong
# define USUFFIX    glue(u, SUFFIX)
# define SSUFFIX    glue(s, SUFFIX)
#endif

#ifdef SOFTMMU_CODE_ACCESS
#define READ_ACCESS_TYPE MMU_INST_FETCH
#define ADDR_READ addr_code
#else
#define READ_ACCESS_TYPE MMU_DATA_LOAD
#define ADDR_READ addr_read
#endif

#if DATA_SIZE == 8
# define BSWAP(X)  bswap64(X)
#elif DATA_SIZE == 4
# define BSWAP(X)  bswap32(X)
#elif DATA_SIZE == 2
# define BSWAP(X)  bswap16(X)
#else
# define BSWAP(X)  (X)
#endif

#if DATA_SIZE == 1
# define helper_le_ld_name  glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
# define helper_be_ld_name  helper_le_ld_name
# define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)
# define helper_be_lds_name helper_le_lds_name
# define helper_le_st_name  glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)
# define helper_be_st_name  helper_le_st_name
#else
# define helper_le_ld_name  glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX)
# define helper_be_ld_name  glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX)
# define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX)
# define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX)
# define helper_le_st_name  glue(glue(helper_le_st, SUFFIX), MMUSUFFIX)
# define helper_be_st_name  glue(glue(helper_be_st, SUFFIX), MMUSUFFIX)
#endif

#ifndef SOFTMMU_CODE_ACCESS
static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
                                              size_t mmu_idx, size_t index,
                                              target_ulong addr,
                                              uintptr_t retaddr)
{
    CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
    return io_readx(env, iotlbentry, addr, retaddr, DATA_SIZE);
}
#endif

WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr,
                            TCGMemOpIdx oi, uintptr_t retaddr)
{
    unsigned mmu_idx = get_mmuidx(oi);
    int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    unsigned a_bits = get_alignment_bits(get_memop(oi));
    uintptr_t haddr;
    DATA_TYPE res;

    if (addr & ((1 << a_bits) - 1)) {
        cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
                             mmu_idx, retaddr);
    }

    /* If the TLB entry is for a different page, reload and try again.  */
    if ((addr & TARGET_PAGE_MASK)
         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {
            tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
                     mmu_idx, retaddr);
        }
        tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    }

    /* Handle an IO access.  */
    if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
        if ((addr & (DATA_SIZE - 1)) != 0) {
            goto do_unaligned_access;
        }

        /* ??? Note that the io helpers always read data in the target
           byte ordering.  We should push the LE/BE request down into io.  */
        res = glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr);
        res = TGT_LE(res);
        return res;
    }

    /* Handle slow unaligned access (it spans two pages or IO).  */
    if (DATA_SIZE > 1
        && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
                    >= TARGET_PAGE_SIZE)) {
        target_ulong addr1, addr2;
        DATA_TYPE res1, res2;
        unsigned shift;
    do_unaligned_access:
        addr1 = addr & ~(DATA_SIZE - 1);
        addr2 = addr1 + DATA_SIZE;
        res1 = helper_le_ld_name(env, addr1, oi, retaddr);
        res2 = helper_le_ld_name(env, addr2, oi, retaddr);
        shift = (addr & (DATA_SIZE - 1)) * 8;

        /* Little-endian combine.  */
        res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
        return res;
    }

    haddr = addr + env->tlb_table[mmu_idx][index].addend;
#if DATA_SIZE == 1
    res = glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr);
#else
    res = glue(glue(ld, LSUFFIX), _le_p)((uint8_t *)haddr);
#endif
    return res;
}

#if DATA_SIZE > 1
WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr,
                            TCGMemOpIdx oi, uintptr_t retaddr)
{
    unsigned mmu_idx = get_mmuidx(oi);
    int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    unsigned a_bits = get_alignment_bits(get_memop(oi));
    uintptr_t haddr;
    DATA_TYPE res;

    if (addr & ((1 << a_bits) - 1)) {
        cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
                             mmu_idx, retaddr);
    }

    /* If the TLB entry is for a different page, reload and try again.  */
    if ((addr & TARGET_PAGE_MASK)
         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {
            tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
                     mmu_idx, retaddr);
        }
        tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    }

    /* Handle an IO access.  */
    if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
        if ((addr & (DATA_SIZE - 1)) != 0) {
            goto do_unaligned_access;
        }

        /* ??? Note that the io helpers always read data in the target
           byte ordering.  We should push the LE/BE request down into io.  */
        res = glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr);
        res = TGT_BE(res);
        return res;
    }

    /* Handle slow unaligned access (it spans two pages or IO).  */
    if (DATA_SIZE > 1
        && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
                    >= TARGET_PAGE_SIZE)) {
        target_ulong addr1, addr2;
        DATA_TYPE res1, res2;
        unsigned shift;
    do_unaligned_access:
        addr1 = addr & ~(DATA_SIZE - 1);
        addr2 = addr1 + DATA_SIZE;
        res1 = helper_be_ld_name(env, addr1, oi, retaddr);
        res2 = helper_be_ld_name(env, addr2, oi, retaddr);
        shift = (addr & (DATA_SIZE - 1)) * 8;

        /* Big-endian combine.  */
        res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
        return res;
    }

    haddr = addr + env->tlb_table[mmu_idx][index].addend;
    res = glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr);
    return res;
}
#endif /* DATA_SIZE > 1 */

#ifndef SOFTMMU_CODE_ACCESS

/* Provide signed versions of the load routines as well.  We can of course
   avoid this for 64-bit data, or for 32-bit data on 32-bit host.  */
#if DATA_SIZE * 8 < TCG_TARGET_REG_BITS
WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr,
                             TCGMemOpIdx oi, uintptr_t retaddr)
{
    return (SDATA_TYPE)helper_le_ld_name(env, addr, oi, retaddr);
}

# if DATA_SIZE > 1
WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr,
                             TCGMemOpIdx oi, uintptr_t retaddr)
{
    return (SDATA_TYPE)helper_be_ld_name(env, addr, oi, retaddr);
}
# endif
#endif

static inline void glue(io_write, SUFFIX)(CPUArchState *env,
                                          size_t mmu_idx, size_t index,
                                          DATA_TYPE val,
                                          target_ulong addr,
                                          uintptr_t retaddr)
{
    CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
    return io_writex(env, iotlbentry, val, addr, retaddr, DATA_SIZE);
}

void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
                       TCGMemOpIdx oi, uintptr_t retaddr)
{
    unsigned mmu_idx = get_mmuidx(oi);
    int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    unsigned a_bits = get_alignment_bits(get_memop(oi));
    uintptr_t haddr;

    if (addr & ((1 << a_bits) - 1)) {
        cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
                             mmu_idx, retaddr);
    }

    /* If the TLB entry is for a different page, reload and try again.  */
    if ((addr & TARGET_PAGE_MASK)
        != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (!VICTIM_TLB_HIT(addr_write, addr)) {
            tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
        }
        tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    }

    /* Handle an IO access.  */
    if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
        if ((addr & (DATA_SIZE - 1)) != 0) {
            goto do_unaligned_access;
        }

        /* ??? Note that the io helpers always read data in the target
           byte ordering.  We should push the LE/BE request down into io.  */
        val = TGT_LE(val);
        glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, retaddr);
        return;
    }

    /* Handle slow unaligned access (it spans two pages or IO).  */
    if (DATA_SIZE > 1
        && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
                     >= TARGET_PAGE_SIZE)) {
        int i, index2;
        target_ulong page2, tlb_addr2;
    do_unaligned_access:
        /* Ensure the second page is in the TLB.  Note that the first page
           is already guaranteed to be filled, and that the second page
           cannot evict the first.  */
        page2 = (addr + DATA_SIZE) & TARGET_PAGE_MASK;
        index2 = (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
        tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write;
        if (page2 != (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK))
            && !VICTIM_TLB_HIT(addr_write, page2)) {
            tlb_fill(ENV_GET_CPU(env), page2, MMU_DATA_STORE,
                     mmu_idx, retaddr);
        }

        /* XXX: not efficient, but simple.  */
        /* This loop must go in the forward direction to avoid issues
           with self-modifying code in Windows 64-bit.  */
        for (i = 0; i < DATA_SIZE; ++i) {
            /* Little-endian extract.  */
            uint8_t val8 = val >> (i * 8);
            glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
                                            oi, retaddr);
        }
        return;
    }

    haddr = addr + env->tlb_table[mmu_idx][index].addend;
#if DATA_SIZE == 1
    glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val);
#else
    glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val);
#endif
}

#if DATA_SIZE > 1
void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
                       TCGMemOpIdx oi, uintptr_t retaddr)
{
    unsigned mmu_idx = get_mmuidx(oi);
    int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    unsigned a_bits = get_alignment_bits(get_memop(oi));
    uintptr_t haddr;

    if (addr & ((1 << a_bits) - 1)) {
        cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
                             mmu_idx, retaddr);
    }

    /* If the TLB entry is for a different page, reload and try again.  */
    if ((addr & TARGET_PAGE_MASK)
        != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (!VICTIM_TLB_HIT(addr_write, addr)) {
            tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
        }
        tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    }

    /* Handle an IO access.  */
    if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
        if ((addr & (DATA_SIZE - 1)) != 0) {
            goto do_unaligned_access;
        }

        /* ??? Note that the io helpers always read data in the target
           byte ordering.  We should push the LE/BE request down into io.  */
        val = TGT_BE(val);
        glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, retaddr);
        return;
    }

    /* Handle slow unaligned access (it spans two pages or IO).  */
    if (DATA_SIZE > 1
        && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
                     >= TARGET_PAGE_SIZE)) {
        int i, index2;
        target_ulong page2, tlb_addr2;
    do_unaligned_access:
        /* Ensure the second page is in the TLB.  Note that the first page
           is already guaranteed to be filled, and that the second page
           cannot evict the first.  */
        page2 = (addr + DATA_SIZE) & TARGET_PAGE_MASK;
        index2 = (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
        tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write;
        if (page2 != (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK))
            && !VICTIM_TLB_HIT(addr_write, page2)) {
            tlb_fill(ENV_GET_CPU(env), page2, MMU_DATA_STORE,
                     mmu_idx, retaddr);
        }

        /* XXX: not efficient, but simple */
        /* This loop must go in the forward direction to avoid issues
           with self-modifying code.  */
        for (i = 0; i < DATA_SIZE; ++i) {
            /* Big-endian extract.  */
            uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8));
            glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
                                            oi, retaddr);
        }
        return;
    }

    haddr = addr + env->tlb_table[mmu_idx][index].addend;
    glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);
}
#endif /* DATA_SIZE > 1 */
#endif /* !defined(SOFTMMU_CODE_ACCESS) */

#undef READ_ACCESS_TYPE
#undef DATA_TYPE
#undef SUFFIX
#undef LSUFFIX
#undef DATA_SIZE
#undef ADDR_READ
#undef WORD_TYPE
#undef SDATA_TYPE
#undef USUFFIX
#undef SSUFFIX
#undef BSWAP
#undef helper_le_ld_name
#undef helper_be_ld_name
#undef helper_le_lds_name
#undef helper_be_lds_name
#undef helper_le_st_name
#undef helper_be_st_name
Commit	Line	Data
b92e5a22 FB	1	/*
b92e5a22 FB	2	* Software MMU support
5fafdf24	3	*
efbf29b6 BS	4	* Generate helpers used by TCG for qemu_ld/st ops and code load
	5	* functions.
	6	*
	7	* Included from target op helpers and exec.c.
	8	*
b92e5a22 FB	9	* Copyright (c) 2003 Fabrice Bellard
	10	*
	11	* This library is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU Lesser General Public
	13	* License as published by the Free Software Foundation; either
	14	* version 2 of the License, or (at your option) any later version.
	15	*
	16	* This library is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	19	* Lesser General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU Lesser General Public
8167ee88	22	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
b92e5a22	23	*/
b92e5a22 FB	24	#if DATA_SIZE == 8
b92e5a22 FB	25	#define SUFFIX q
701e3a5c	26	#define LSUFFIX q
c8f94df5	27	#define SDATA_TYPE int64_t
dc9a353c	28	#define DATA_TYPE uint64_t
b92e5a22 FB	29	#elif DATA_SIZE == 4
b92e5a22 FB	30	#define SUFFIX l
701e3a5c	31	#define LSUFFIX l
c8f94df5	32	#define SDATA_TYPE int32_t
dc9a353c	33	#define DATA_TYPE uint32_t
b92e5a22 FB	34	#elif DATA_SIZE == 2
b92e5a22 FB	35	#define SUFFIX w
701e3a5c	36	#define LSUFFIX uw
c8f94df5	37	#define SDATA_TYPE int16_t
dc9a353c	38	#define DATA_TYPE uint16_t
b92e5a22 FB	39	#elif DATA_SIZE == 1
b92e5a22 FB	40	#define SUFFIX b
701e3a5c	41	#define LSUFFIX ub
c8f94df5	42	#define SDATA_TYPE int8_t
dc9a353c	43	#define DATA_TYPE uint8_t
b92e5a22 FB	44	#else
	45	#error unsupported data size
	46	#endif
	47
c8f94df5 RH	48
	49	/* For the benefit of TCG generated code, we want to avoid the complication
	50	of ABI-specific return type promotion and always return a value extended
	51	to the register size of the host. This is tcg_target_long, except in the
	52	case of a 32-bit host and 64-bit data, and for that we always have
	53	uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */
	54	#if defined(SOFTMMU_CODE_ACCESS) \|\| DATA_SIZE == 8
	55	# define WORD_TYPE DATA_TYPE
	56	# define USUFFIX SUFFIX
	57	#else
	58	# define WORD_TYPE tcg_target_ulong
	59	# define USUFFIX glue(u, SUFFIX)
	60	# define SSUFFIX glue(s, SUFFIX)
	61	#endif
	62
b769d8fe	63	#ifdef SOFTMMU_CODE_ACCESS
55e94093	64	#define READ_ACCESS_TYPE MMU_INST_FETCH
84b7b8e7	65	#define ADDR_READ addr_code
b769d8fe	66	#else
55e94093	67	#define READ_ACCESS_TYPE MMU_DATA_LOAD
84b7b8e7	68	#define ADDR_READ addr_read
b769d8fe FB	69	#endif
b769d8fe FB	70
867b3201 RH	71	#if DATA_SIZE == 8
	72	# define BSWAP(X) bswap64(X)
	73	#elif DATA_SIZE == 4
	74	# define BSWAP(X) bswap32(X)
	75	#elif DATA_SIZE == 2
	76	# define BSWAP(X) bswap16(X)
	77	#else
	78	# define BSWAP(X) (X)
	79	#endif
	80
867b3201 RH	81	#if DATA_SIZE == 1
	82	# define helper_le_ld_name glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
	83	# define helper_be_ld_name helper_le_ld_name
	84	# define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)
	85	# define helper_be_lds_name helper_le_lds_name
	86	# define helper_le_st_name glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)
	87	# define helper_be_st_name helper_le_st_name
	88	#else
	89	# define helper_le_ld_name glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX)
	90	# define helper_be_ld_name glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX)
	91	# define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX)
	92	# define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX)
	93	# define helper_le_st_name glue(glue(helper_le_st, SUFFIX), MMUSUFFIX)
	94	# define helper_be_st_name glue(glue(helper_be_st, SUFFIX), MMUSUFFIX)
	95	#endif
	96
0f590e74	97	#ifndef SOFTMMU_CODE_ACCESS
89c33337	98	static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
82a45b96	99	size_t mmu_idx, size_t index,
2e70f6ef	100	target_ulong addr,
20503968	101	uintptr_t retaddr)
b92e5a22	102	{
82a45b96 RH	103	CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
82a45b96 RH	104	return io_readx(env, iotlbentry, addr, retaddr, DATA_SIZE);
b92e5a22	105	}
0f590e74	106	#endif
b92e5a22	107
3972ef6f RH	108	WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr,
3972ef6f RH	109	TCGMemOpIdx oi, uintptr_t retaddr)
b92e5a22	110	{
3972ef6f	111	unsigned mmu_idx = get_mmuidx(oi);
aac1fb05 RH	112	int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
aac1fb05 RH	113	target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
85aa8081	114	unsigned a_bits = get_alignment_bits(get_memop(oi));
aac1fb05	115	uintptr_t haddr;
867b3201	116	DATA_TYPE res;
3b46e624	117
85aa8081	118	if (addr & ((1 << a_bits) - 1)) {
1f00b27f SS	119	cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
	120	mmu_idx, retaddr);
	121	}
	122
aac1fb05 RH	123	/* If the TLB entry is for a different page, reload and try again. */
	124	if ((addr & TARGET_PAGE_MASK)
	125	!= (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
a390284b	126	if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {
88e89a57 XT	127	tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
	128	mmu_idx, retaddr);
	129	}
aac1fb05 RH	130	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
	131	}
	132
	133	/* Handle an IO access. */
	134	if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
aac1fb05 RH	135	if ((addr & (DATA_SIZE - 1)) != 0) {
aac1fb05 RH	136	goto do_unaligned_access;
b92e5a22	137	}
867b3201 RH	138
	139	/* ??? Note that the io helpers always read data in the target
	140	byte ordering. We should push the LE/BE request down into io. */
82a45b96	141	res = glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr);
867b3201 RH	142	res = TGT_LE(res);
867b3201 RH	143	return res;
aac1fb05 RH	144	}
	145
	146	/* Handle slow unaligned access (it spans two pages or IO). */
	147	if (DATA_SIZE > 1
	148	&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
	149	>= TARGET_PAGE_SIZE)) {
	150	target_ulong addr1, addr2;
867b3201	151	DATA_TYPE res1, res2;
aac1fb05 RH	152	unsigned shift;
aac1fb05 RH	153	do_unaligned_access:
aac1fb05 RH	154	addr1 = addr & ~(DATA_SIZE - 1);
aac1fb05 RH	155	addr2 = addr1 + DATA_SIZE;
01ecaf43 RH	156	res1 = helper_le_ld_name(env, addr1, oi, retaddr);
01ecaf43 RH	157	res2 = helper_le_ld_name(env, addr2, oi, retaddr);
aac1fb05	158	shift = (addr & (DATA_SIZE - 1)) * 8;
867b3201 RH	159
867b3201 RH	160	/* Little-endian combine. */
aac1fb05	161	res = (res1 >> shift) \| (res2 << ((DATA_SIZE * 8) - shift));
867b3201 RH	162	return res;
	163	}
	164
867b3201 RH	165	haddr = addr + env->tlb_table[mmu_idx][index].addend;
	166	#if DATA_SIZE == 1
	167	res = glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr);
	168	#else
	169	res = glue(glue(ld, LSUFFIX), _le_p)((uint8_t *)haddr);
	170	#endif
	171	return res;
	172	}
	173
	174	#if DATA_SIZE > 1
3972ef6f RH	175	WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr,
3972ef6f RH	176	TCGMemOpIdx oi, uintptr_t retaddr)
867b3201	177	{
3972ef6f	178	unsigned mmu_idx = get_mmuidx(oi);
867b3201 RH	179	int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
867b3201 RH	180	target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
85aa8081	181	unsigned a_bits = get_alignment_bits(get_memop(oi));
867b3201 RH	182	uintptr_t haddr;
	183	DATA_TYPE res;
	184
85aa8081	185	if (addr & ((1 << a_bits) - 1)) {
1f00b27f SS	186	cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
	187	mmu_idx, retaddr);
	188	}
	189
867b3201 RH	190	/* If the TLB entry is for a different page, reload and try again. */
	191	if ((addr & TARGET_PAGE_MASK)
	192	!= (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
a390284b	193	if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {
88e89a57 XT	194	tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
	195	mmu_idx, retaddr);
	196	}
867b3201 RH	197	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
	198	}
	199
	200	/* Handle an IO access. */
	201	if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
867b3201 RH	202	if ((addr & (DATA_SIZE - 1)) != 0) {
	203	goto do_unaligned_access;
	204	}
867b3201 RH	205
	206	/* ??? Note that the io helpers always read data in the target
	207	byte ordering. We should push the LE/BE request down into io. */
82a45b96	208	res = glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr);
867b3201 RH	209	res = TGT_BE(res);
	210	return res;
	211	}
	212
	213	/* Handle slow unaligned access (it spans two pages or IO). */
	214	if (DATA_SIZE > 1
	215	&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
	216	>= TARGET_PAGE_SIZE)) {
	217	target_ulong addr1, addr2;
	218	DATA_TYPE res1, res2;
	219	unsigned shift;
	220	do_unaligned_access:
867b3201 RH	221	addr1 = addr & ~(DATA_SIZE - 1);
867b3201 RH	222	addr2 = addr1 + DATA_SIZE;
01ecaf43 RH	223	res1 = helper_be_ld_name(env, addr1, oi, retaddr);
01ecaf43 RH	224	res2 = helper_be_ld_name(env, addr2, oi, retaddr);
867b3201 RH	225	shift = (addr & (DATA_SIZE - 1)) * 8;
	226
	227	/* Big-endian combine. */
	228	res = (res1 << shift) \| (res2 >> ((DATA_SIZE * 8) - shift));
aac1fb05 RH	229	return res;
	230	}
	231
aac1fb05	232	haddr = addr + env->tlb_table[mmu_idx][index].addend;
867b3201 RH	233	res = glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr);
867b3201 RH	234	return res;
b92e5a22	235	}
867b3201	236	#endif /* DATA_SIZE > 1 */
b92e5a22	237
b769d8fe FB	238	#ifndef SOFTMMU_CODE_ACCESS
b769d8fe FB	239
c8f94df5 RH	240	/* Provide signed versions of the load routines as well. We can of course
	241	avoid this for 64-bit data, or for 32-bit data on 32-bit host. */
	242	#if DATA_SIZE * 8 < TCG_TARGET_REG_BITS
867b3201	243	WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr,
3972ef6f	244	TCGMemOpIdx oi, uintptr_t retaddr)
867b3201	245	{
3972ef6f	246	return (SDATA_TYPE)helper_le_ld_name(env, addr, oi, retaddr);
867b3201 RH	247	}
	248
	249	# if DATA_SIZE > 1
	250	WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr,
3972ef6f	251	TCGMemOpIdx oi, uintptr_t retaddr)
c8f94df5	252	{
3972ef6f	253	return (SDATA_TYPE)helper_be_ld_name(env, addr, oi, retaddr);
c8f94df5	254	}
867b3201	255	# endif
c8f94df5 RH	256	#endif
c8f94df5 RH	257
89c33337	258	static inline void glue(io_write, SUFFIX)(CPUArchState *env,
82a45b96	259	size_t mmu_idx, size_t index,
b769d8fe	260	DATA_TYPE val,
0f459d16	261	target_ulong addr,
20503968	262	uintptr_t retaddr)
b769d8fe	263	{
82a45b96 RH	264	CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
82a45b96 RH	265	return io_writex(env, iotlbentry, val, addr, retaddr, DATA_SIZE);
b769d8fe	266	}
b92e5a22	267
867b3201	268	void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
3972ef6f	269	TCGMemOpIdx oi, uintptr_t retaddr)
b92e5a22	270	{
3972ef6f	271	unsigned mmu_idx = get_mmuidx(oi);
aac1fb05 RH	272	int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
aac1fb05 RH	273	target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
85aa8081	274	unsigned a_bits = get_alignment_bits(get_memop(oi));
aac1fb05	275	uintptr_t haddr;
3b46e624	276
85aa8081	277	if (addr & ((1 << a_bits) - 1)) {
1f00b27f SS	278	cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
	279	mmu_idx, retaddr);
	280	}
	281
aac1fb05 RH	282	/* If the TLB entry is for a different page, reload and try again. */
	283	if ((addr & TARGET_PAGE_MASK)
	284	!= (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
a390284b	285	if (!VICTIM_TLB_HIT(addr_write, addr)) {
55e94093	286	tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
88e89a57	287	}
aac1fb05 RH	288	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
	289	}
	290
	291	/* Handle an IO access. */
	292	if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
aac1fb05 RH	293	if ((addr & (DATA_SIZE - 1)) != 0) {
	294	goto do_unaligned_access;
	295	}
867b3201 RH	296
	297	/* ??? Note that the io helpers always read data in the target
	298	byte ordering. We should push the LE/BE request down into io. */
	299	val = TGT_LE(val);
82a45b96	300	glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, retaddr);
aac1fb05 RH	301	return;
	302	}
	303
	304	/* Handle slow unaligned access (it spans two pages or IO). */
	305	if (DATA_SIZE > 1
	306	&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
	307	>= TARGET_PAGE_SIZE)) {
81daabaf SD	308	int i, index2;
81daabaf SD	309	target_ulong page2, tlb_addr2;
aac1fb05	310	do_unaligned_access:
81daabaf SD	311	/* Ensure the second page is in the TLB. Note that the first page
	312	is already guaranteed to be filled, and that the second page
	313	cannot evict the first. */
	314	page2 = (addr + DATA_SIZE) & TARGET_PAGE_MASK;
	315	index2 = (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
	316	tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write;
	317	if (page2 != (tlb_addr2 & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))
	318	&& !VICTIM_TLB_HIT(addr_write, page2)) {
	319	tlb_fill(ENV_GET_CPU(env), page2, MMU_DATA_STORE,
	320	mmu_idx, retaddr);
	321	}
	322
	323	/* XXX: not efficient, but simple. */
	324	/* This loop must go in the forward direction to avoid issues
	325	with self-modifying code in Windows 64-bit. */
	326	for (i = 0; i < DATA_SIZE; ++i) {
867b3201	327	/* Little-endian extract. */
aac1fb05	328	uint8_t val8 = val >> (i * 8);
867b3201	329	glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
01ecaf43	330	oi, retaddr);
867b3201 RH	331	}
	332	return;
	333	}
	334
867b3201 RH	335	haddr = addr + env->tlb_table[mmu_idx][index].addend;
	336	#if DATA_SIZE == 1
	337	glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val);
	338	#else
	339	glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val);
a64d4718	340	#endif
867b3201 RH	341	}
	342
	343	#if DATA_SIZE > 1
	344	void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
3972ef6f	345	TCGMemOpIdx oi, uintptr_t retaddr)
867b3201	346	{
3972ef6f	347	unsigned mmu_idx = get_mmuidx(oi);
867b3201 RH	348	int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
867b3201 RH	349	target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
85aa8081	350	unsigned a_bits = get_alignment_bits(get_memop(oi));
867b3201 RH	351	uintptr_t haddr;
867b3201 RH	352
85aa8081	353	if (addr & ((1 << a_bits) - 1)) {
1f00b27f SS	354	cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
	355	mmu_idx, retaddr);
	356	}
	357
867b3201 RH	358	/* If the TLB entry is for a different page, reload and try again. */
	359	if ((addr & TARGET_PAGE_MASK)
	360	!= (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
a390284b	361	if (!VICTIM_TLB_HIT(addr_write, addr)) {
55e94093	362	tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
88e89a57	363	}
867b3201 RH	364	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
	365	}
	366
	367	/* Handle an IO access. */
	368	if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
867b3201 RH	369	if ((addr & (DATA_SIZE - 1)) != 0) {
	370	goto do_unaligned_access;
	371	}
867b3201 RH	372
	373	/* ??? Note that the io helpers always read data in the target
	374	byte ordering. We should push the LE/BE request down into io. */
	375	val = TGT_BE(val);
82a45b96	376	glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, retaddr);
867b3201 RH	377	return;
	378	}
	379
	380	/* Handle slow unaligned access (it spans two pages or IO). */
	381	if (DATA_SIZE > 1
	382	&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
	383	>= TARGET_PAGE_SIZE)) {
81daabaf SD	384	int i, index2;
81daabaf SD	385	target_ulong page2, tlb_addr2;
867b3201	386	do_unaligned_access:
81daabaf SD	387	/* Ensure the second page is in the TLB. Note that the first page
	388	is already guaranteed to be filled, and that the second page
	389	cannot evict the first. */
	390	page2 = (addr + DATA_SIZE) & TARGET_PAGE_MASK;
	391	index2 = (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
	392	tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write;
	393	if (page2 != (tlb_addr2 & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))
	394	&& !VICTIM_TLB_HIT(addr_write, page2)) {
	395	tlb_fill(ENV_GET_CPU(env), page2, MMU_DATA_STORE,
	396	mmu_idx, retaddr);
	397	}
	398
867b3201	399	/* XXX: not efficient, but simple */
81daabaf SD	400	/* This loop must go in the forward direction to avoid issues
	401	with self-modifying code. */
	402	for (i = 0; i < DATA_SIZE; ++i) {
867b3201 RH	403	/* Big-endian extract. */
867b3201 RH	404	uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8));
aac1fb05	405	glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
01ecaf43	406	oi, retaddr);
b92e5a22	407	}
aac1fb05 RH	408	return;
	409	}
	410
aac1fb05	411	haddr = addr + env->tlb_table[mmu_idx][index].addend;
867b3201	412	glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);
b92e5a22	413	}
867b3201	414	#endif /* DATA_SIZE > 1 */
b769d8fe FB	415	#endif /* !defined(SOFTMMU_CODE_ACCESS) */
	416
	417	#undef READ_ACCESS_TYPE
b92e5a22 FB	418	#undef DATA_TYPE
b92e5a22 FB	419	#undef SUFFIX
701e3a5c	420	#undef LSUFFIX
b92e5a22	421	#undef DATA_SIZE
84b7b8e7	422	#undef ADDR_READ
c8f94df5 RH	423	#undef WORD_TYPE
	424	#undef SDATA_TYPE
	425	#undef USUFFIX
	426	#undef SSUFFIX
867b3201	427	#undef BSWAP
867b3201 RH	428	#undef helper_le_ld_name
	429	#undef helper_be_ld_name
	430	#undef helper_le_lds_name
	431	#undef helper_be_lds_name
	432	#undef helper_le_st_name
	433	#undef helper_be_st_name