[mirror_qemu.git] / softmmu_template.h

/*
 *  Software MMU support
 *
 * Generate helpers used by TCG for qemu_ld/st ops and code load
 * functions.
 *
 * Included from target op helpers and exec.c.
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#include "qemu/timer.h"
#include "exec/address-spaces.h"
#include "exec/memory.h"

#define DATA_SIZE (1 << SHIFT)

#if DATA_SIZE == 8
#define SUFFIX q
#define LSUFFIX q
#define SDATA_TYPE  int64_t
#define DATA_TYPE  uint64_t
#elif DATA_SIZE == 4
#define SUFFIX l
#define LSUFFIX l
#define SDATA_TYPE  int32_t
#define DATA_TYPE  uint32_t
#elif DATA_SIZE == 2
#define SUFFIX w
#define LSUFFIX uw
#define SDATA_TYPE  int16_t
#define DATA_TYPE  uint16_t
#elif DATA_SIZE == 1
#define SUFFIX b
#define LSUFFIX ub
#define SDATA_TYPE  int8_t
#define DATA_TYPE  uint8_t
#else
#error unsupported data size
#endif


/* For the benefit of TCG generated code, we want to avoid the complication
   of ABI-specific return type promotion and always return a value extended
   to the register size of the host.  This is tcg_target_long, except in the
   case of a 32-bit host and 64-bit data, and for that we always have
   uint64_t.  Don't bother with this widened value for SOFTMMU_CODE_ACCESS.  */
#if defined(SOFTMMU_CODE_ACCESS) || DATA_SIZE == 8
# define WORD_TYPE  DATA_TYPE
# define USUFFIX    SUFFIX
#else
# define WORD_TYPE  tcg_target_ulong
# define USUFFIX    glue(u, SUFFIX)
# define SSUFFIX    glue(s, SUFFIX)
#endif

#ifdef SOFTMMU_CODE_ACCESS
#define READ_ACCESS_TYPE 2
#define ADDR_READ addr_code
#else
#define READ_ACCESS_TYPE 0
#define ADDR_READ addr_read
#endif

#if DATA_SIZE == 8
# define BSWAP(X)  bswap64(X)
#elif DATA_SIZE == 4
# define BSWAP(X)  bswap32(X)
#elif DATA_SIZE == 2
# define BSWAP(X)  bswap16(X)
#else
# define BSWAP(X)  (X)
#endif

#ifdef TARGET_WORDS_BIGENDIAN
# define TGT_BE(X)  (X)
# define TGT_LE(X)  BSWAP(X)
#else
# define TGT_BE(X)  BSWAP(X)
# define TGT_LE(X)  (X)
#endif

#if DATA_SIZE == 1
# define helper_le_ld_name  glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
# define helper_be_ld_name  helper_le_ld_name
# define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)
# define helper_be_lds_name helper_le_lds_name
# define helper_le_st_name  glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)
# define helper_be_st_name  helper_le_st_name
#else
# define helper_le_ld_name  glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX)
# define helper_be_ld_name  glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX)
# define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX)
# define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX)
# define helper_le_st_name  glue(glue(helper_le_st, SUFFIX), MMUSUFFIX)
# define helper_be_st_name  glue(glue(helper_be_st, SUFFIX), MMUSUFFIX)
#endif

#ifdef TARGET_WORDS_BIGENDIAN
# define helper_te_ld_name  helper_be_ld_name
# define helper_te_st_name  helper_be_st_name
#else
# define helper_te_ld_name  helper_le_ld_name
# define helper_te_st_name  helper_le_st_name
#endif

#ifndef SOFTMMU_CODE_ACCESS
static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
                                              hwaddr physaddr,
                                              target_ulong addr,
                                              uintptr_t retaddr)
{
    uint64_t val;
    CPUState *cpu = ENV_GET_CPU(env);
    MemoryRegion *mr = iotlb_to_region(cpu->as, physaddr);

    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
    cpu->mem_io_pc = retaddr;
    if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
        cpu_io_recompile(cpu, retaddr);
    }

    cpu->mem_io_vaddr = addr;
    io_mem_read(mr, physaddr, &val, 1 << SHIFT);
    return val;
}
#endif

#ifdef SOFTMMU_CODE_ACCESS
static __attribute__((unused))
#endif
WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
                            uintptr_t retaddr)
{
    int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    uintptr_t haddr;
    DATA_TYPE res;

    /* Adjust the given return address.  */
    retaddr -= GETPC_ADJ;

    /* If the TLB entry is for a different page, reload and try again.  */
    if ((addr & TARGET_PAGE_MASK)
         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0) {
            cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
                                 mmu_idx, retaddr);
        }
#endif
        tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
        tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    }

    /* Handle an IO access.  */
    if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
        hwaddr ioaddr;
        if ((addr & (DATA_SIZE - 1)) != 0) {
            goto do_unaligned_access;
        }
        ioaddr = env->iotlb[mmu_idx][index];

        /* ??? Note that the io helpers always read data in the target
           byte ordering.  We should push the LE/BE request down into io.  */
        res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
        res = TGT_LE(res);
        return res;
    }

    /* Handle slow unaligned access (it spans two pages or IO).  */
    if (DATA_SIZE > 1
        && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
                    >= TARGET_PAGE_SIZE)) {
        target_ulong addr1, addr2;
        DATA_TYPE res1, res2;
        unsigned shift;
    do_unaligned_access:
#ifdef ALIGNED_ONLY
        cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
                             mmu_idx, retaddr);
#endif
        addr1 = addr & ~(DATA_SIZE - 1);
        addr2 = addr1 + DATA_SIZE;
        /* Note the adjustment at the beginning of the function.
           Undo that for the recursion.  */
        res1 = helper_le_ld_name(env, addr1, mmu_idx, retaddr + GETPC_ADJ);
        res2 = helper_le_ld_name(env, addr2, mmu_idx, retaddr + GETPC_ADJ);
        shift = (addr & (DATA_SIZE - 1)) * 8;

        /* Little-endian combine.  */
        res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
        return res;
    }

    /* Handle aligned access or unaligned access in the same page.  */
#ifdef ALIGNED_ONLY
    if ((addr & (DATA_SIZE - 1)) != 0) {
        cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
                             mmu_idx, retaddr);
    }
#endif

    haddr = addr + env->tlb_table[mmu_idx][index].addend;
#if DATA_SIZE == 1
    res = glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr);
#else
    res = glue(glue(ld, LSUFFIX), _le_p)((uint8_t *)haddr);
#endif
    return res;
}

#if DATA_SIZE > 1
#ifdef SOFTMMU_CODE_ACCESS
static __attribute__((unused))
#endif
WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
                            uintptr_t retaddr)
{
    int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    uintptr_t haddr;
    DATA_TYPE res;

    /* Adjust the given return address.  */
    retaddr -= GETPC_ADJ;

    /* If the TLB entry is for a different page, reload and try again.  */
    if ((addr & TARGET_PAGE_MASK)
         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0) {
            cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
                                 mmu_idx, retaddr);
        }
#endif
        tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
        tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    }

    /* Handle an IO access.  */
    if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
        hwaddr ioaddr;
        if ((addr & (DATA_SIZE - 1)) != 0) {
            goto do_unaligned_access;
        }
        ioaddr = env->iotlb[mmu_idx][index];

        /* ??? Note that the io helpers always read data in the target
           byte ordering.  We should push the LE/BE request down into io.  */
        res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
        res = TGT_BE(res);
        return res;
    }

    /* Handle slow unaligned access (it spans two pages or IO).  */
    if (DATA_SIZE > 1
        && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
                    >= TARGET_PAGE_SIZE)) {
        target_ulong addr1, addr2;
        DATA_TYPE res1, res2;
        unsigned shift;
    do_unaligned_access:
#ifdef ALIGNED_ONLY
        cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
                             mmu_idx, retaddr);
#endif
        addr1 = addr & ~(DATA_SIZE - 1);
        addr2 = addr1 + DATA_SIZE;
        /* Note the adjustment at the beginning of the function.
           Undo that for the recursion.  */
        res1 = helper_be_ld_name(env, addr1, mmu_idx, retaddr + GETPC_ADJ);
        res2 = helper_be_ld_name(env, addr2, mmu_idx, retaddr + GETPC_ADJ);
        shift = (addr & (DATA_SIZE - 1)) * 8;

        /* Big-endian combine.  */
        res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
        return res;
    }

    /* Handle aligned access or unaligned access in the same page.  */
#ifdef ALIGNED_ONLY
    if ((addr & (DATA_SIZE - 1)) != 0) {
        cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
                             mmu_idx, retaddr);
    }
#endif

    haddr = addr + env->tlb_table[mmu_idx][index].addend;
    res = glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr);
    return res;
}
#endif /* DATA_SIZE > 1 */

DATA_TYPE
glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
                                         int mmu_idx)
{
    return helper_te_ld_name (env, addr, mmu_idx, GETRA());
}

#ifndef SOFTMMU_CODE_ACCESS

/* Provide signed versions of the load routines as well.  We can of course
   avoid this for 64-bit data, or for 32-bit data on 32-bit host.  */
#if DATA_SIZE * 8 < TCG_TARGET_REG_BITS
WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr,
                             int mmu_idx, uintptr_t retaddr)
{
    return (SDATA_TYPE)helper_le_ld_name(env, addr, mmu_idx, retaddr);
}

# if DATA_SIZE > 1
WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr,
                             int mmu_idx, uintptr_t retaddr)
{
    return (SDATA_TYPE)helper_be_ld_name(env, addr, mmu_idx, retaddr);
}
# endif
#endif

static inline void glue(io_write, SUFFIX)(CPUArchState *env,
                                          hwaddr physaddr,
                                          DATA_TYPE val,
                                          target_ulong addr,
                                          uintptr_t retaddr)
{
    CPUState *cpu = ENV_GET_CPU(env);
    MemoryRegion *mr = iotlb_to_region(cpu->as, physaddr);

    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
    if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
        cpu_io_recompile(cpu, retaddr);
    }

    cpu->mem_io_vaddr = addr;
    cpu->mem_io_pc = retaddr;
    io_mem_write(mr, physaddr, val, 1 << SHIFT);
}

void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
                       int mmu_idx, uintptr_t retaddr)
{
    int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    uintptr_t haddr;

    /* Adjust the given return address.  */
    retaddr -= GETPC_ADJ;

    /* If the TLB entry is for a different page, reload and try again.  */
    if ((addr & TARGET_PAGE_MASK)
        != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0) {
            cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
        }
#endif
        tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
        tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    }

    /* Handle an IO access.  */
    if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
        hwaddr ioaddr;
        if ((addr & (DATA_SIZE - 1)) != 0) {
            goto do_unaligned_access;
        }
        ioaddr = env->iotlb[mmu_idx][index];

        /* ??? Note that the io helpers always read data in the target
           byte ordering.  We should push the LE/BE request down into io.  */
        val = TGT_LE(val);
        glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
        return;
    }

    /* Handle slow unaligned access (it spans two pages or IO).  */
    if (DATA_SIZE > 1
        && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
                     >= TARGET_PAGE_SIZE)) {
        int i;
    do_unaligned_access:
#ifdef ALIGNED_ONLY
        cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
#endif
        /* XXX: not efficient, but simple */
        /* Note: relies on the fact that tlb_fill() does not remove the
         * previous page from the TLB cache.  */
        for (i = DATA_SIZE - 1; i >= 0; i--) {
            /* Little-endian extract.  */
            uint8_t val8 = val >> (i * 8);
            /* Note the adjustment at the beginning of the function.
               Undo that for the recursion.  */
            glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
                                            mmu_idx, retaddr + GETPC_ADJ);
        }
        return;
    }

    /* Handle aligned access or unaligned access in the same page.  */
#ifdef ALIGNED_ONLY
    if ((addr & (DATA_SIZE - 1)) != 0) {
        cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
    }
#endif

    haddr = addr + env->tlb_table[mmu_idx][index].addend;
#if DATA_SIZE == 1
    glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val);
#else
    glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val);
#endif
}

#if DATA_SIZE > 1
void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
                       int mmu_idx, uintptr_t retaddr)
{
    int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    uintptr_t haddr;

    /* Adjust the given return address.  */
    retaddr -= GETPC_ADJ;

    /* If the TLB entry is for a different page, reload and try again.  */
    if ((addr & TARGET_PAGE_MASK)
        != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0) {
            cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
        }
#endif
        tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
        tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    }

    /* Handle an IO access.  */
    if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
        hwaddr ioaddr;
        if ((addr & (DATA_SIZE - 1)) != 0) {
            goto do_unaligned_access;
        }
        ioaddr = env->iotlb[mmu_idx][index];

        /* ??? Note that the io helpers always read data in the target
           byte ordering.  We should push the LE/BE request down into io.  */
        val = TGT_BE(val);
        glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
        return;
    }

    /* Handle slow unaligned access (it spans two pages or IO).  */
    if (DATA_SIZE > 1
        && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
                     >= TARGET_PAGE_SIZE)) {
        int i;
    do_unaligned_access:
#ifdef ALIGNED_ONLY
        cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
#endif
        /* XXX: not efficient, but simple */
        /* Note: relies on the fact that tlb_fill() does not remove the
         * previous page from the TLB cache.  */
        for (i = DATA_SIZE - 1; i >= 0; i--) {
            /* Big-endian extract.  */
            uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8));
            /* Note the adjustment at the beginning of the function.
               Undo that for the recursion.  */
            glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
                                            mmu_idx, retaddr + GETPC_ADJ);
        }
        return;
    }

    /* Handle aligned access or unaligned access in the same page.  */
#ifdef ALIGNED_ONLY
    if ((addr & (DATA_SIZE - 1)) != 0) {
        cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
    }
#endif

    haddr = addr + env->tlb_table[mmu_idx][index].addend;
    glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);
}
#endif /* DATA_SIZE > 1 */

void
glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
                                         DATA_TYPE val, int mmu_idx)
{
    helper_te_st_name(env, addr, val, mmu_idx, GETRA());
}

#endif /* !defined(SOFTMMU_CODE_ACCESS) */

#undef READ_ACCESS_TYPE
#undef SHIFT
#undef DATA_TYPE
#undef SUFFIX
#undef LSUFFIX
#undef DATA_SIZE
#undef ADDR_READ
#undef WORD_TYPE
#undef SDATA_TYPE
#undef USUFFIX
#undef SSUFFIX
#undef BSWAP
#undef TGT_BE
#undef TGT_LE
#undef CPU_BE
#undef CPU_LE
#undef helper_le_ld_name
#undef helper_be_ld_name
#undef helper_le_lds_name
#undef helper_be_lds_name
#undef helper_le_st_name
#undef helper_be_st_name
#undef helper_te_ld_name
#undef helper_te_st_name
Commit	Line	Data
b92e5a22 FB	1	/*
b92e5a22 FB	2	* Software MMU support
5fafdf24	3	*
efbf29b6 BS	4	* Generate helpers used by TCG for qemu_ld/st ops and code load
	5	* functions.
	6	*
	7	* Included from target op helpers and exec.c.
	8	*
b92e5a22 FB	9	* Copyright (c) 2003 Fabrice Bellard
	10	*
	11	* This library is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU Lesser General Public
	13	* License as published by the Free Software Foundation; either
	14	* version 2 of the License, or (at your option) any later version.
	15	*
	16	* This library is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	19	* Lesser General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU Lesser General Public
8167ee88	22	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
b92e5a22	23	*/
1de7afc9	24	#include "qemu/timer.h"
77717094	25	#include "exec/address-spaces.h"
022c62cb	26	#include "exec/memory.h"
29e922b6	27
b92e5a22 FB	28	#define DATA_SIZE (1 << SHIFT)
	29
	30	#if DATA_SIZE == 8
	31	#define SUFFIX q
701e3a5c	32	#define LSUFFIX q
c8f94df5	33	#define SDATA_TYPE int64_t
dc9a353c	34	#define DATA_TYPE uint64_t
b92e5a22 FB	35	#elif DATA_SIZE == 4
b92e5a22 FB	36	#define SUFFIX l
701e3a5c	37	#define LSUFFIX l
c8f94df5	38	#define SDATA_TYPE int32_t
dc9a353c	39	#define DATA_TYPE uint32_t
b92e5a22 FB	40	#elif DATA_SIZE == 2
b92e5a22 FB	41	#define SUFFIX w
701e3a5c	42	#define LSUFFIX uw
c8f94df5	43	#define SDATA_TYPE int16_t
dc9a353c	44	#define DATA_TYPE uint16_t
b92e5a22 FB	45	#elif DATA_SIZE == 1
b92e5a22 FB	46	#define SUFFIX b
701e3a5c	47	#define LSUFFIX ub
c8f94df5	48	#define SDATA_TYPE int8_t
dc9a353c	49	#define DATA_TYPE uint8_t
b92e5a22 FB	50	#else
	51	#error unsupported data size
	52	#endif
	53
c8f94df5 RH	54
	55	/* For the benefit of TCG generated code, we want to avoid the complication
	56	of ABI-specific return type promotion and always return a value extended
	57	to the register size of the host. This is tcg_target_long, except in the
	58	case of a 32-bit host and 64-bit data, and for that we always have
	59	uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */
	60	#if defined(SOFTMMU_CODE_ACCESS) \|\| DATA_SIZE == 8
	61	# define WORD_TYPE DATA_TYPE
	62	# define USUFFIX SUFFIX
	63	#else
	64	# define WORD_TYPE tcg_target_ulong
	65	# define USUFFIX glue(u, SUFFIX)
	66	# define SSUFFIX glue(s, SUFFIX)
	67	#endif
	68
b769d8fe FB	69	#ifdef SOFTMMU_CODE_ACCESS
b769d8fe FB	70	#define READ_ACCESS_TYPE 2
84b7b8e7	71	#define ADDR_READ addr_code
b769d8fe FB	72	#else
b769d8fe FB	73	#define READ_ACCESS_TYPE 0
84b7b8e7	74	#define ADDR_READ addr_read
b769d8fe FB	75	#endif
b769d8fe FB	76
867b3201 RH	77	#if DATA_SIZE == 8
	78	# define BSWAP(X) bswap64(X)
	79	#elif DATA_SIZE == 4
	80	# define BSWAP(X) bswap32(X)
	81	#elif DATA_SIZE == 2
	82	# define BSWAP(X) bswap16(X)
	83	#else
	84	# define BSWAP(X) (X)
	85	#endif
	86
	87	#ifdef TARGET_WORDS_BIGENDIAN
	88	# define TGT_BE(X) (X)
	89	# define TGT_LE(X) BSWAP(X)
	90	#else
	91	# define TGT_BE(X) BSWAP(X)
	92	# define TGT_LE(X) (X)
	93	#endif
	94
	95	#if DATA_SIZE == 1
	96	# define helper_le_ld_name glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
	97	# define helper_be_ld_name helper_le_ld_name
	98	# define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)
	99	# define helper_be_lds_name helper_le_lds_name
	100	# define helper_le_st_name glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)
	101	# define helper_be_st_name helper_le_st_name
	102	#else
	103	# define helper_le_ld_name glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX)
	104	# define helper_be_ld_name glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX)
	105	# define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX)
	106	# define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX)
	107	# define helper_le_st_name glue(glue(helper_le_st, SUFFIX), MMUSUFFIX)
	108	# define helper_be_st_name glue(glue(helper_be_st, SUFFIX), MMUSUFFIX)
	109	#endif
	110
	111	#ifdef TARGET_WORDS_BIGENDIAN
	112	# define helper_te_ld_name helper_be_ld_name
	113	# define helper_te_st_name helper_be_st_name
	114	#else
	115	# define helper_te_ld_name helper_le_ld_name
	116	# define helper_te_st_name helper_le_st_name
	117	#endif
	118
0f590e74	119	#ifndef SOFTMMU_CODE_ACCESS
89c33337	120	static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
a8170e5e	121	hwaddr physaddr,
2e70f6ef	122	target_ulong addr,
20503968	123	uintptr_t retaddr)
b92e5a22	124	{
791af8c8	125	uint64_t val;
09daed84 EI	126	CPUState *cpu = ENV_GET_CPU(env);
09daed84 EI	127	MemoryRegion *mr = iotlb_to_region(cpu->as, physaddr);
37ec01d4	128
0f459d16	129	physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
93afeade	130	cpu->mem_io_pc = retaddr;
99df7dce	131	if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
90b40a69	132	cpu_io_recompile(cpu, retaddr);
2e70f6ef	133	}
b92e5a22	134
93afeade	135	cpu->mem_io_vaddr = addr;
791af8c8 PB	136	io_mem_read(mr, physaddr, &val, 1 << SHIFT);
791af8c8 PB	137	return val;
b92e5a22	138	}
0f590e74	139	#endif
b92e5a22	140
e25c3887	141	#ifdef SOFTMMU_CODE_ACCESS
867b3201	142	static __attribute__((unused))
e25c3887	143	#endif
867b3201 RH	144	WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
867b3201 RH	145	uintptr_t retaddr)
b92e5a22	146	{
aac1fb05 RH	147	int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
	148	target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
	149	uintptr_t haddr;
867b3201	150	DATA_TYPE res;
3b46e624	151
0f842f8a RH	152	/* Adjust the given return address. */
	153	retaddr -= GETPC_ADJ;
	154
aac1fb05 RH	155	/* If the TLB entry is for a different page, reload and try again. */
	156	if ((addr & TARGET_PAGE_MASK)
	157	!= (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
a64d4718	158	#ifdef ALIGNED_ONLY
aac1fb05	159	if ((addr & (DATA_SIZE - 1)) != 0) {
93e22326 PB	160	cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
93e22326 PB	161	mmu_idx, retaddr);
aac1fb05	162	}
a64d4718	163	#endif
d5a11fef	164	tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
aac1fb05 RH	165	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
	166	}
	167
	168	/* Handle an IO access. */
	169	if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
	170	hwaddr ioaddr;
	171	if ((addr & (DATA_SIZE - 1)) != 0) {
	172	goto do_unaligned_access;
b92e5a22	173	}
aac1fb05	174	ioaddr = env->iotlb[mmu_idx][index];
867b3201 RH	175
	176	/* ??? Note that the io helpers always read data in the target
	177	byte ordering. We should push the LE/BE request down into io. */
	178	res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
	179	res = TGT_LE(res);
	180	return res;
aac1fb05 RH	181	}
	182
	183	/* Handle slow unaligned access (it spans two pages or IO). */
	184	if (DATA_SIZE > 1
	185	&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
	186	>= TARGET_PAGE_SIZE)) {
	187	target_ulong addr1, addr2;
867b3201	188	DATA_TYPE res1, res2;
aac1fb05 RH	189	unsigned shift;
aac1fb05 RH	190	do_unaligned_access:
a64d4718	191	#ifdef ALIGNED_ONLY
93e22326 PB	192	cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
93e22326 PB	193	mmu_idx, retaddr);
a64d4718	194	#endif
aac1fb05 RH	195	addr1 = addr & ~(DATA_SIZE - 1);
aac1fb05 RH	196	addr2 = addr1 + DATA_SIZE;
0f842f8a RH	197	/* Note the adjustment at the beginning of the function.
0f842f8a RH	198	Undo that for the recursion. */
867b3201 RH	199	res1 = helper_le_ld_name(env, addr1, mmu_idx, retaddr + GETPC_ADJ);
867b3201 RH	200	res2 = helper_le_ld_name(env, addr2, mmu_idx, retaddr + GETPC_ADJ);
aac1fb05	201	shift = (addr & (DATA_SIZE - 1)) * 8;
867b3201 RH	202
867b3201 RH	203	/* Little-endian combine. */
aac1fb05	204	res = (res1 >> shift) \| (res2 << ((DATA_SIZE * 8) - shift));
867b3201 RH	205	return res;
	206	}
	207
	208	/* Handle aligned access or unaligned access in the same page. */
	209	#ifdef ALIGNED_ONLY
	210	if ((addr & (DATA_SIZE - 1)) != 0) {
93e22326 PB	211	cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
93e22326 PB	212	mmu_idx, retaddr);
867b3201 RH	213	}
	214	#endif
	215
	216	haddr = addr + env->tlb_table[mmu_idx][index].addend;
	217	#if DATA_SIZE == 1
	218	res = glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr);
	219	#else
	220	res = glue(glue(ld, LSUFFIX), _le_p)((uint8_t *)haddr);
	221	#endif
	222	return res;
	223	}
	224
	225	#if DATA_SIZE > 1
	226	#ifdef SOFTMMU_CODE_ACCESS
	227	static __attribute__((unused))
	228	#endif
	229	WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
	230	uintptr_t retaddr)
	231	{
	232	int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
	233	target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
	234	uintptr_t haddr;
	235	DATA_TYPE res;
	236
	237	/* Adjust the given return address. */
	238	retaddr -= GETPC_ADJ;
	239
	240	/* If the TLB entry is for a different page, reload and try again. */
	241	if ((addr & TARGET_PAGE_MASK)
	242	!= (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
	243	#ifdef ALIGNED_ONLY
	244	if ((addr & (DATA_SIZE - 1)) != 0) {
93e22326 PB	245	cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
93e22326 PB	246	mmu_idx, retaddr);
867b3201 RH	247	}
867b3201 RH	248	#endif
d5a11fef	249	tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
867b3201 RH	250	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
	251	}
	252
	253	/* Handle an IO access. */
	254	if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
	255	hwaddr ioaddr;
	256	if ((addr & (DATA_SIZE - 1)) != 0) {
	257	goto do_unaligned_access;
	258	}
	259	ioaddr = env->iotlb[mmu_idx][index];
	260
	261	/* ??? Note that the io helpers always read data in the target
	262	byte ordering. We should push the LE/BE request down into io. */
	263	res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
	264	res = TGT_BE(res);
	265	return res;
	266	}
	267
	268	/* Handle slow unaligned access (it spans two pages or IO). */
	269	if (DATA_SIZE > 1
	270	&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
	271	>= TARGET_PAGE_SIZE)) {
	272	target_ulong addr1, addr2;
	273	DATA_TYPE res1, res2;
	274	unsigned shift;
	275	do_unaligned_access:
	276	#ifdef ALIGNED_ONLY
93e22326 PB	277	cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
93e22326 PB	278	mmu_idx, retaddr);
aac1fb05	279	#endif
867b3201 RH	280	addr1 = addr & ~(DATA_SIZE - 1);
	281	addr2 = addr1 + DATA_SIZE;
	282	/* Note the adjustment at the beginning of the function.
	283	Undo that for the recursion. */
	284	res1 = helper_be_ld_name(env, addr1, mmu_idx, retaddr + GETPC_ADJ);
	285	res2 = helper_be_ld_name(env, addr2, mmu_idx, retaddr + GETPC_ADJ);
	286	shift = (addr & (DATA_SIZE - 1)) * 8;
	287
	288	/* Big-endian combine. */
	289	res = (res1 << shift) \| (res2 >> ((DATA_SIZE * 8) - shift));
aac1fb05 RH	290	return res;
	291	}
	292
	293	/* Handle aligned access or unaligned access in the same page. */
	294	#ifdef ALIGNED_ONLY
	295	if ((addr & (DATA_SIZE - 1)) != 0) {
93e22326 PB	296	cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
93e22326 PB	297	mmu_idx, retaddr);
b92e5a22	298	}
aac1fb05 RH	299	#endif
	300
	301	haddr = addr + env->tlb_table[mmu_idx][index].addend;
867b3201 RH	302	res = glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr);
867b3201 RH	303	return res;
b92e5a22	304	}
867b3201	305	#endif /* DATA_SIZE > 1 */
b92e5a22	306
e25c3887 RH	307	DATA_TYPE
	308	glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
	309	int mmu_idx)
	310	{
867b3201	311	return helper_te_ld_name (env, addr, mmu_idx, GETRA());
e25c3887 RH	312	}
e25c3887 RH	313
b769d8fe FB	314	#ifndef SOFTMMU_CODE_ACCESS
b769d8fe FB	315
c8f94df5 RH	316	/* Provide signed versions of the load routines as well. We can of course
	317	avoid this for 64-bit data, or for 32-bit data on 32-bit host. */
	318	#if DATA_SIZE * 8 < TCG_TARGET_REG_BITS
867b3201 RH	319	WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr,
	320	int mmu_idx, uintptr_t retaddr)
	321	{
	322	return (SDATA_TYPE)helper_le_ld_name(env, addr, mmu_idx, retaddr);
	323	}
	324
	325	# if DATA_SIZE > 1
	326	WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr,
	327	int mmu_idx, uintptr_t retaddr)
c8f94df5	328	{
867b3201	329	return (SDATA_TYPE)helper_be_ld_name(env, addr, mmu_idx, retaddr);
c8f94df5	330	}
867b3201	331	# endif
c8f94df5 RH	332	#endif
c8f94df5 RH	333
89c33337	334	static inline void glue(io_write, SUFFIX)(CPUArchState *env,
a8170e5e	335	hwaddr physaddr,
b769d8fe	336	DATA_TYPE val,
0f459d16	337	target_ulong addr,
20503968	338	uintptr_t retaddr)
b769d8fe	339	{
09daed84 EI	340	CPUState *cpu = ENV_GET_CPU(env);
09daed84 EI	341	MemoryRegion *mr = iotlb_to_region(cpu->as, physaddr);
37ec01d4	342
0f459d16	343	physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
99df7dce	344	if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
90b40a69	345	cpu_io_recompile(cpu, retaddr);
2e70f6ef	346	}
b769d8fe	347
93afeade AF	348	cpu->mem_io_vaddr = addr;
93afeade AF	349	cpu->mem_io_pc = retaddr;
37ec01d4	350	io_mem_write(mr, physaddr, val, 1 << SHIFT);
b769d8fe	351	}
b92e5a22	352
867b3201 RH	353	void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
867b3201 RH	354	int mmu_idx, uintptr_t retaddr)
b92e5a22	355	{
aac1fb05 RH	356	int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
	357	target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
	358	uintptr_t haddr;
3b46e624	359
0f842f8a RH	360	/* Adjust the given return address. */
	361	retaddr -= GETPC_ADJ;
	362
aac1fb05 RH	363	/* If the TLB entry is for a different page, reload and try again. */
	364	if ((addr & TARGET_PAGE_MASK)
	365	!= (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
a64d4718	366	#ifdef ALIGNED_ONLY
aac1fb05	367	if ((addr & (DATA_SIZE - 1)) != 0) {
93e22326	368	cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
aac1fb05	369	}
a64d4718	370	#endif
d5a11fef	371	tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
aac1fb05 RH	372	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
	373	}
	374
	375	/* Handle an IO access. */
	376	if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
	377	hwaddr ioaddr;
	378	if ((addr & (DATA_SIZE - 1)) != 0) {
	379	goto do_unaligned_access;
	380	}
	381	ioaddr = env->iotlb[mmu_idx][index];
867b3201 RH	382
	383	/* ??? Note that the io helpers always read data in the target
	384	byte ordering. We should push the LE/BE request down into io. */
	385	val = TGT_LE(val);
aac1fb05 RH	386	glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
	387	return;
	388	}
	389
	390	/* Handle slow unaligned access (it spans two pages or IO). */
	391	if (DATA_SIZE > 1
	392	&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
	393	>= TARGET_PAGE_SIZE)) {
	394	int i;
	395	do_unaligned_access:
a64d4718	396	#ifdef ALIGNED_ONLY
93e22326	397	cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
aac1fb05 RH	398	#endif
	399	/* XXX: not efficient, but simple */
	400	/* Note: relies on the fact that tlb_fill() does not remove the
	401	* previous page from the TLB cache. */
	402	for (i = DATA_SIZE - 1; i >= 0; i--) {
867b3201	403	/* Little-endian extract. */
aac1fb05	404	uint8_t val8 = val >> (i * 8);
867b3201 RH	405	/* Note the adjustment at the beginning of the function.
	406	Undo that for the recursion. */
	407	glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
	408	mmu_idx, retaddr + GETPC_ADJ);
	409	}
	410	return;
	411	}
	412
	413	/* Handle aligned access or unaligned access in the same page. */
	414	#ifdef ALIGNED_ONLY
	415	if ((addr & (DATA_SIZE - 1)) != 0) {
93e22326	416	cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
867b3201 RH	417	}
	418	#endif
	419
	420	haddr = addr + env->tlb_table[mmu_idx][index].addend;
	421	#if DATA_SIZE == 1
	422	glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val);
	423	#else
	424	glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val);
a64d4718	425	#endif
867b3201 RH	426	}
	427
	428	#if DATA_SIZE > 1
	429	void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
	430	int mmu_idx, uintptr_t retaddr)
	431	{
	432	int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
	433	target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
	434	uintptr_t haddr;
	435
	436	/* Adjust the given return address. */
	437	retaddr -= GETPC_ADJ;
	438
	439	/* If the TLB entry is for a different page, reload and try again. */
	440	if ((addr & TARGET_PAGE_MASK)
	441	!= (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
	442	#ifdef ALIGNED_ONLY
	443	if ((addr & (DATA_SIZE - 1)) != 0) {
93e22326	444	cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
867b3201 RH	445	}
867b3201 RH	446	#endif
d5a11fef	447	tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
867b3201 RH	448	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
	449	}
	450
	451	/* Handle an IO access. */
	452	if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
	453	hwaddr ioaddr;
	454	if ((addr & (DATA_SIZE - 1)) != 0) {
	455	goto do_unaligned_access;
	456	}
	457	ioaddr = env->iotlb[mmu_idx][index];
	458
	459	/* ??? Note that the io helpers always read data in the target
	460	byte ordering. We should push the LE/BE request down into io. */
	461	val = TGT_BE(val);
	462	glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
	463	return;
	464	}
	465
	466	/* Handle slow unaligned access (it spans two pages or IO). */
	467	if (DATA_SIZE > 1
	468	&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
	469	>= TARGET_PAGE_SIZE)) {
	470	int i;
	471	do_unaligned_access:
	472	#ifdef ALIGNED_ONLY
93e22326	473	cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
867b3201 RH	474	#endif
	475	/* XXX: not efficient, but simple */
	476	/* Note: relies on the fact that tlb_fill() does not remove the
	477	* previous page from the TLB cache. */
	478	for (i = DATA_SIZE - 1; i >= 0; i--) {
	479	/* Big-endian extract. */
	480	uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8));
0f842f8a RH	481	/* Note the adjustment at the beginning of the function.
0f842f8a RH	482	Undo that for the recursion. */
aac1fb05	483	glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
0f842f8a	484	mmu_idx, retaddr + GETPC_ADJ);
b92e5a22	485	}
aac1fb05 RH	486	return;
	487	}
	488
	489	/* Handle aligned access or unaligned access in the same page. */
a64d4718	490	#ifdef ALIGNED_ONLY
aac1fb05	491	if ((addr & (DATA_SIZE - 1)) != 0) {
93e22326	492	cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
b92e5a22	493	}
aac1fb05 RH	494	#endif
	495
	496	haddr = addr + env->tlb_table[mmu_idx][index].addend;
867b3201	497	glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);
b92e5a22	498	}
867b3201	499	#endif /* DATA_SIZE > 1 */
b92e5a22	500
e25c3887 RH	501	void
	502	glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
	503	DATA_TYPE val, int mmu_idx)
	504	{
867b3201	505	helper_te_st_name(env, addr, val, mmu_idx, GETRA());
e25c3887 RH	506	}
e25c3887 RH	507
b769d8fe FB	508	#endif /* !defined(SOFTMMU_CODE_ACCESS) */
	509
	510	#undef READ_ACCESS_TYPE
b92e5a22 FB	511	#undef SHIFT
	512	#undef DATA_TYPE
	513	#undef SUFFIX
701e3a5c	514	#undef LSUFFIX
b92e5a22	515	#undef DATA_SIZE
84b7b8e7	516	#undef ADDR_READ
c8f94df5 RH	517	#undef WORD_TYPE
	518	#undef SDATA_TYPE
	519	#undef USUFFIX
	520	#undef SSUFFIX
867b3201 RH	521	#undef BSWAP
	522	#undef TGT_BE
	523	#undef TGT_LE
	524	#undef CPU_BE
	525	#undef CPU_LE
	526	#undef helper_le_ld_name
	527	#undef helper_be_ld_name
	528	#undef helper_le_lds_name
	529	#undef helper_be_lds_name
	530	#undef helper_le_st_name
	531	#undef helper_be_st_name
	532	#undef helper_te_ld_name
	533	#undef helper_te_st_name